1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag>, neverHasSideEffects = 1 in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX,
1636 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1637 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1638 SSEPackedSingle, SSE_CVT_PS>, TB, VEX,
1642 let Pattern = []<dag>, neverHasSideEffects = 1 in {
1643 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1644 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1645 SSE_CVT_SS2SI_32>, XS;
1646 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1647 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1648 SSE_CVT_SS2SI_64>, XS, REX_W;
1649 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1650 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1651 SSEPackedSingle, SSE_CVT_PS>, TB,
1652 Requires<[HasSSE2]>;
1655 let Predicates = [HasAVX] in {
1656 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1657 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1658 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1659 (VCVTSS2SIrm addr:$src)>;
1660 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1661 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1662 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1663 (VCVTSS2SI64rm addr:$src)>;
1666 let Predicates = [HasSSE1] in {
1667 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1668 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1669 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1670 (CVTSS2SIrm addr:$src)>;
1671 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1672 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1673 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1674 (CVTSS2SI64rm addr:$src)>;
1679 // Convert scalar double to scalar single
1680 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1681 (ins FR64:$src1, FR64:$src2),
1682 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1683 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1685 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1686 (ins FR64:$src1, f64mem:$src2),
1687 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1688 [], IIC_SSE_CVT_Scalar_RM>,
1689 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1691 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1694 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1695 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1696 [(set FR32:$dst, (fround FR64:$src))],
1697 IIC_SSE_CVT_Scalar_RR>;
1698 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1699 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1700 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1701 IIC_SSE_CVT_Scalar_RM>,
1703 Requires<[HasSSE2, OptForSize]>;
1705 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1706 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1709 let Constraints = "$src1 = $dst" in
1710 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1711 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1712 SSE_CVT_Scalar>, XS;
1714 // Convert scalar single to scalar double
1715 // SSE2 instructions with XS prefix
1716 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1717 (ins FR32:$src1, FR32:$src2),
1718 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1719 [], IIC_SSE_CVT_Scalar_RR>,
1720 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1722 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1723 (ins FR32:$src1, f32mem:$src2),
1724 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1725 [], IIC_SSE_CVT_Scalar_RM>,
1726 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1728 let Predicates = [HasAVX] in {
1729 def : Pat<(f64 (fextend FR32:$src)),
1730 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1731 def : Pat<(fextend (loadf32 addr:$src)),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1733 def : Pat<(extloadf32 addr:$src),
1734 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1737 def : Pat<(extloadf32 addr:$src),
1738 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1739 Requires<[HasAVX, OptForSpeed]>;
1741 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1742 "cvtss2sd\t{$src, $dst|$dst, $src}",
1743 [(set FR64:$dst, (fextend FR32:$src))],
1744 IIC_SSE_CVT_Scalar_RR>, XS,
1745 Requires<[HasSSE2]>;
1746 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1747 "cvtss2sd\t{$src, $dst|$dst, $src}",
1748 [(set FR64:$dst, (extloadf32 addr:$src))],
1749 IIC_SSE_CVT_Scalar_RM>, XS,
1750 Requires<[HasSSE2, OptForSize]>;
1752 // extload f32 -> f64. This matches load+fextend because we have a hack in
1753 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1755 // Since these loads aren't folded into the fextend, we have to match it
1757 def : Pat<(fextend (loadf32 addr:$src)),
1758 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1759 def : Pat<(extloadf32 addr:$src),
1760 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1762 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1763 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1764 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1765 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1767 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1769 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1770 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1771 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1772 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1773 (load addr:$src2)))],
1774 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1776 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1777 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1778 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1779 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1780 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1782 IIC_SSE_CVT_Scalar_RR>, XS,
1783 Requires<[HasSSE2]>;
1784 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1785 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1786 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1787 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1788 (load addr:$src2)))],
1789 IIC_SSE_CVT_Scalar_RM>, XS,
1790 Requires<[HasSSE2]>;
1793 // Convert packed single/double fp to doubleword
1794 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1795 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1796 IIC_SSE_CVT_PS_RR>, VEX;
1797 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1798 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1799 IIC_SSE_CVT_PS_RM>, VEX;
1800 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1801 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1802 IIC_SSE_CVT_PS_RR>, VEX;
1803 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1804 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1805 IIC_SSE_CVT_PS_RM>, VEX;
1806 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1807 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1809 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1810 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1813 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1814 "cvtps2dq\t{$src, $dst|$dst, $src}",
1815 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1818 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1820 "cvtps2dq\t{$src, $dst|$dst, $src}",
1821 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1822 (memop addr:$src)))],
1823 IIC_SSE_CVT_PS_RM>, VEX;
1824 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1825 "cvtps2dq\t{$src, $dst|$dst, $src}",
1826 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1828 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1829 "cvtps2dq\t{$src, $dst|$dst, $src}",
1830 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1831 (memop addr:$src)))],
1834 // Convert Packed Double FP to Packed DW Integers
1835 let Predicates = [HasAVX] in {
1836 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1837 // register, but the same isn't true when using memory operands instead.
1838 // Provide other assembly rr and rm forms to address this explicitly.
1839 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1840 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1841 def VCVTPD2DQXrYr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1842 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1845 def VCVTPD2DQXrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1846 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1847 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1848 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1851 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1852 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX;
1853 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1854 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1857 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1858 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
1860 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1861 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
1864 let Predicates = [HasAVX] in {
1865 def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
1866 (VCVTPD2DQrr VR128:$src)>;
1867 def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
1868 (VCVTPD2DQXrm addr:$src)>;
1871 let Predicates = [HasSSE2] in {
1872 def : Pat<(int_x86_sse2_cvtpd2dq VR128:$src),
1873 (CVTPD2DQrr VR128:$src)>;
1874 def : Pat<(int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)),
1875 (CVTPD2DQrm addr:$src)>;
1878 // Convert with truncation packed single/double fp to doubleword
1879 // SSE2 packed instructions with XS prefix
1880 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1881 "cvttps2dq\t{$src, $dst|$dst, $src}",
1883 (int_x86_sse2_cvttps2dq VR128:$src))],
1884 IIC_SSE_CVT_PS_RR>, VEX;
1885 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1886 "cvttps2dq\t{$src, $dst|$dst, $src}",
1887 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1888 (memop addr:$src)))],
1889 IIC_SSE_CVT_PS_RM>, VEX;
1890 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1891 "cvttps2dq\t{$src, $dst|$dst, $src}",
1893 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1894 IIC_SSE_CVT_PS_RR>, VEX;
1895 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1896 "cvttps2dq\t{$src, $dst|$dst, $src}",
1897 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1898 (memopv8f32 addr:$src)))],
1899 IIC_SSE_CVT_PS_RM>, VEX;
1901 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1902 "cvttps2dq\t{$src, $dst|$dst, $src}",
1904 (int_x86_sse2_cvttps2dq VR128:$src))],
1906 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1907 "cvttps2dq\t{$src, $dst|$dst, $src}",
1909 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1912 let Predicates = [HasAVX] in {
1913 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1914 (VCVTDQ2PSrr VR128:$src)>;
1915 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1916 (VCVTDQ2PSrm addr:$src)>;
1918 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1919 (VCVTDQ2PSrr VR128:$src)>;
1920 def : Pat<(int_x86_sse2_cvtdq2ps (bitconvert (memopv2i64 addr:$src))),
1921 (VCVTDQ2PSrm addr:$src)>;
1923 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1924 (VCVTTPS2DQrr VR128:$src)>;
1925 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1926 (VCVTTPS2DQrm addr:$src)>;
1928 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1929 (VCVTDQ2PSYrr VR256:$src)>;
1930 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1931 (VCVTDQ2PSYrm addr:$src)>;
1933 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1934 (VCVTTPS2DQYrr VR256:$src)>;
1935 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1936 (VCVTTPS2DQYrm addr:$src)>;
1939 let Predicates = [HasSSE2] in {
1940 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1941 (CVTDQ2PSrr VR128:$src)>;
1942 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1943 (CVTDQ2PSrm addr:$src)>;
1945 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
1946 (CVTDQ2PSrr VR128:$src)>;
1947 def : Pat<(int_x86_sse2_cvtdq2ps (bitconvert (memopv2i64 addr:$src))),
1948 (CVTDQ2PSrm addr:$src)>;
1950 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1951 (CVTTPS2DQrr VR128:$src)>;
1952 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1953 (CVTTPS2DQrm addr:$src)>;
1956 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1957 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1959 (int_x86_sse2_cvttpd2dq VR128:$src))],
1960 IIC_SSE_CVT_PD_RR>, VEX;
1961 let isCodeGenOnly = 1 in
1962 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1963 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1964 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1965 (memop addr:$src)))],
1966 IIC_SSE_CVT_PD_RM>, VEX;
1967 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1971 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1972 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1973 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1974 (memop addr:$src)))],
1977 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1978 // register, but the same isn't true when using memory operands instead.
1979 // Provide other assembly rr and rm forms to address this explicitly.
1980 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1981 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
1982 IIC_SSE_CVT_PD_RR>, VEX;
1985 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1986 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
1987 IIC_SSE_CVT_PD_RR>, VEX;
1988 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1989 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
1990 IIC_SSE_CVT_PD_RM>, VEX;
1993 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1994 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
1995 IIC_SSE_CVT_PD_RR>, VEX;
1996 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1997 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
1998 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2000 let Predicates = [HasAVX] in {
2001 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2002 (VCVTTPD2DQYrr VR256:$src)>;
2003 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2004 (VCVTTPD2DQYrm addr:$src)>;
2005 } // Predicates = [HasAVX]
2007 // Convert packed single to packed double
2008 let Predicates = [HasAVX] in {
2009 // SSE2 instructions without OpSize prefix
2010 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2011 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2012 IIC_SSE_CVT_PD_RR>, TB, VEX;
2013 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2014 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2015 IIC_SSE_CVT_PD_RM>, TB, VEX;
2016 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2017 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2018 IIC_SSE_CVT_PD_RR>, TB, VEX;
2019 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2020 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2021 IIC_SSE_CVT_PD_RM>, TB, VEX;
2023 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2024 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2025 IIC_SSE_CVT_PD_RR>, TB;
2026 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2027 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2028 IIC_SSE_CVT_PD_RM>, TB;
2030 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2031 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2032 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2034 TB, VEX, Requires<[HasAVX]>;
2035 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2036 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2037 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2038 (load addr:$src)))],
2040 TB, VEX, Requires<[HasAVX]>;
2041 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2042 "cvtps2pd\t{$src, $dst|$dst, $src}",
2043 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2045 TB, Requires<[HasSSE2]>;
2046 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2047 "cvtps2pd\t{$src, $dst|$dst, $src}",
2048 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2049 (load addr:$src)))],
2051 TB, Requires<[HasSSE2]>;
2053 // Convert Packed DW Integers to Packed Double FP
2054 let Predicates = [HasAVX] in {
2055 def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2056 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2057 def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2058 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2059 def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2060 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2061 def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2062 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2065 def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2066 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2068 def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2069 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2072 // 128 bit register conversion intrinsics
2073 let Predicates = [HasAVX] in
2074 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
2075 (VCVTDQ2PDrr VR128:$src)>;
2077 let Predicates = [HasSSE2] in
2078 def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
2079 (CVTDQ2PDrr VR128:$src)>;
2081 // AVX 256-bit register conversion intrinsics
2082 let Predicates = [HasAVX] in {
2083 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
2084 (VCVTDQ2PDYrr VR128:$src)>;
2085 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
2086 (VCVTDQ2PDYrm addr:$src)>;
2088 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
2089 (VCVTPD2DQYrr VR256:$src)>;
2090 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
2091 (VCVTPD2DQYrm addr:$src)>;
2093 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2094 (VCVTDQ2PDYrr VR128:$src)>;
2095 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2096 (VCVTDQ2PDYrm addr:$src)>;
2097 } // Predicates = [HasAVX]
2099 // Convert packed double to packed single
2100 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2101 // register, but the same isn't true when using memory operands instead.
2102 // Provide other assembly rr and rm forms to address this explicitly.
2103 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2104 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2105 IIC_SSE_CVT_PD_RR>, VEX;
2106 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2107 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2108 IIC_SSE_CVT_PD_RR>, VEX;
2111 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2112 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2113 IIC_SSE_CVT_PD_RR>, VEX;
2114 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2115 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2116 IIC_SSE_CVT_PD_RM>, VEX;
2119 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2120 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2121 IIC_SSE_CVT_PD_RR>, VEX;
2122 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2123 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}", [],
2124 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2125 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2126 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2128 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2129 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2133 let Predicates = [HasAVX] in {
2134 def : Pat<(int_x86_sse2_cvtpd2ps VR128:$src),
2135 (VCVTPD2PSrr VR128:$src)>;
2136 def : Pat<(int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)),
2137 (VCVTPD2PSrr VR128:$src)>;
2140 let Predicates = [HasSSE2] in {
2141 def : Pat<(int_x86_sse2_cvtpd2ps VR128:$src),
2142 (CVTPD2PSrr VR128:$src)>;
2143 def : Pat<(int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)),
2144 (CVTPD2PSrr VR128:$src)>;
2147 // AVX 256-bit register conversion intrinsics
2148 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2149 // whenever possible to avoid declaring two versions of each one.
2150 let Predicates = [HasAVX] in {
2151 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2152 (VCVTDQ2PSYrr VR256:$src)>;
2153 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2154 (VCVTDQ2PSYrm addr:$src)>;
2156 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2157 (VCVTPD2PSYrr VR256:$src)>;
2158 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2159 (VCVTPD2PSYrm addr:$src)>;
2161 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2162 (VCVTPS2DQYrr VR256:$src)>;
2163 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2164 (VCVTPS2DQYrm addr:$src)>;
2166 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2167 (VCVTPS2PDYrr VR128:$src)>;
2168 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2169 (VCVTPS2PDYrm addr:$src)>;
2171 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2172 (VCVTTPD2DQYrr VR256:$src)>;
2173 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2174 (VCVTTPD2DQYrm addr:$src)>;
2176 // Match fround and fextend for 128/256-bit conversions
2177 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2178 (VCVTPD2PSYrr VR256:$src)>;
2179 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2180 (VCVTPD2PSYrm addr:$src)>;
2182 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2183 (VCVTPS2PDYrr VR128:$src)>;
2184 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2185 (VCVTPS2PDYrm addr:$src)>;
2188 //===----------------------------------------------------------------------===//
2189 // SSE 1 & 2 - Compare Instructions
2190 //===----------------------------------------------------------------------===//
2192 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2193 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2194 Operand CC, SDNode OpNode, ValueType VT,
2195 PatFrag ld_frag, string asm, string asm_alt,
2197 def rr : SIi8<0xC2, MRMSrcReg,
2198 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2199 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2201 def rm : SIi8<0xC2, MRMSrcMem,
2202 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2203 [(set RC:$dst, (OpNode (VT RC:$src1),
2204 (ld_frag addr:$src2), imm:$cc))],
2207 // Accept explicit immediate argument form instead of comparison code.
2208 let neverHasSideEffects = 1 in {
2209 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2210 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2211 IIC_SSE_ALU_F32S_RR>;
2213 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2214 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2215 IIC_SSE_ALU_F32S_RM>;
2219 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2220 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2221 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2223 XS, VEX_4V, VEX_LIG;
2224 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2225 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2226 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2227 SSE_ALU_F32S>, // same latency as 32 bit compare
2228 XD, VEX_4V, VEX_LIG;
2230 let Constraints = "$src1 = $dst" in {
2231 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2232 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2233 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2235 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2236 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2237 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2238 SSE_ALU_F32S>, // same latency as 32 bit compare
2242 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2243 Intrinsic Int, string asm, OpndItins itins> {
2244 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2245 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2246 [(set VR128:$dst, (Int VR128:$src1,
2247 VR128:$src, imm:$cc))],
2249 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2250 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2251 [(set VR128:$dst, (Int VR128:$src1,
2252 (load addr:$src), imm:$cc))],
2256 // Aliases to match intrinsics which expect XMM operand(s).
2257 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2258 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2261 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2262 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2263 SSE_ALU_F32S>, // same latency as f32
2265 let Constraints = "$src1 = $dst" in {
2266 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2267 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2269 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2270 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2271 SSE_ALU_F32S>, // same latency as f32
2276 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2277 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2278 ValueType vt, X86MemOperand x86memop,
2279 PatFrag ld_frag, string OpcodeStr, Domain d> {
2280 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2281 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2282 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2283 IIC_SSE_COMIS_RR, d>;
2284 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2285 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2286 [(set EFLAGS, (OpNode (vt RC:$src1),
2287 (ld_frag addr:$src2)))],
2288 IIC_SSE_COMIS_RM, d>;
2291 let Defs = [EFLAGS] in {
2292 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2293 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2294 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2295 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2297 let Pattern = []<dag> in {
2298 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2299 "comiss", SSEPackedSingle>, TB, VEX,
2301 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2302 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2306 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2307 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2308 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2309 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2311 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2312 load, "comiss", SSEPackedSingle>, TB, VEX;
2313 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2314 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2315 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2316 "ucomiss", SSEPackedSingle>, TB;
2317 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2318 "ucomisd", SSEPackedDouble>, TB, OpSize;
2320 let Pattern = []<dag> in {
2321 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2322 "comiss", SSEPackedSingle>, TB;
2323 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2324 "comisd", SSEPackedDouble>, TB, OpSize;
2327 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2328 load, "ucomiss", SSEPackedSingle>, TB;
2329 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2330 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2332 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2333 "comiss", SSEPackedSingle>, TB;
2334 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2335 "comisd", SSEPackedDouble>, TB, OpSize;
2336 } // Defs = [EFLAGS]
2338 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2339 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2340 Operand CC, Intrinsic Int, string asm,
2341 string asm_alt, Domain d> {
2342 def rri : PIi8<0xC2, MRMSrcReg,
2343 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2344 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2345 IIC_SSE_CMPP_RR, d>;
2346 def rmi : PIi8<0xC2, MRMSrcMem,
2347 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2348 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2349 IIC_SSE_CMPP_RM, d>;
2351 // Accept explicit immediate argument form instead of comparison code.
2352 let neverHasSideEffects = 1 in {
2353 def rri_alt : PIi8<0xC2, MRMSrcReg,
2354 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2355 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2356 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2358 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2362 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2363 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2364 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2365 SSEPackedSingle>, TB, VEX_4V;
2366 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2367 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2368 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2369 SSEPackedDouble>, TB, OpSize, VEX_4V;
2370 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2371 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2372 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2373 SSEPackedSingle>, TB, VEX_4V;
2374 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2375 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2376 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2377 SSEPackedDouble>, TB, OpSize, VEX_4V;
2378 let Constraints = "$src1 = $dst" in {
2379 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2380 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2381 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2382 SSEPackedSingle>, TB;
2383 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2384 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2385 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2386 SSEPackedDouble>, TB, OpSize;
2389 let Predicates = [HasAVX] in {
2390 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2391 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2392 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2393 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2394 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2395 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2396 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2397 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2399 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2400 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2401 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2402 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2403 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2404 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2405 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2406 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2409 let Predicates = [HasSSE1] in {
2410 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2411 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2412 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2413 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2416 let Predicates = [HasSSE2] in {
2417 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2418 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2419 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2420 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2423 //===----------------------------------------------------------------------===//
2424 // SSE 1 & 2 - Shuffle Instructions
2425 //===----------------------------------------------------------------------===//
2427 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2428 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2429 ValueType vt, string asm, PatFrag mem_frag,
2430 Domain d, bit IsConvertibleToThreeAddress = 0> {
2431 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2432 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2433 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2434 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2435 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2436 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2437 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2438 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2439 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2442 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2443 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2444 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2445 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2446 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2447 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2448 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2449 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2450 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2451 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2452 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2453 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2455 let Constraints = "$src1 = $dst" in {
2456 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2457 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2458 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2460 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2461 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2462 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2466 let Predicates = [HasAVX] in {
2467 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2468 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2469 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2470 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2471 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2473 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2474 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2475 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2476 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2477 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2480 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2481 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2482 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2483 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2484 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2486 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2487 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2488 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2489 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2490 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2493 let Predicates = [HasSSE1] in {
2494 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2495 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2496 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2497 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2498 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2501 let Predicates = [HasSSE2] in {
2502 // Generic SHUFPD patterns
2503 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2504 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2505 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2506 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2507 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2510 //===----------------------------------------------------------------------===//
2511 // SSE 1 & 2 - Unpack Instructions
2512 //===----------------------------------------------------------------------===//
2514 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2515 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2516 PatFrag mem_frag, RegisterClass RC,
2517 X86MemOperand x86memop, string asm,
2519 def rr : PI<opc, MRMSrcReg,
2520 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2522 (vt (OpNode RC:$src1, RC:$src2)))],
2524 def rm : PI<opc, MRMSrcMem,
2525 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2527 (vt (OpNode RC:$src1,
2528 (mem_frag addr:$src2))))],
2532 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2533 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2534 SSEPackedSingle>, TB, VEX_4V;
2535 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2536 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2537 SSEPackedDouble>, TB, OpSize, VEX_4V;
2538 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2539 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2540 SSEPackedSingle>, TB, VEX_4V;
2541 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2542 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2543 SSEPackedDouble>, TB, OpSize, VEX_4V;
2545 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2546 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2547 SSEPackedSingle>, TB, VEX_4V;
2548 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2549 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2550 SSEPackedDouble>, TB, OpSize, VEX_4V;
2551 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2552 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2553 SSEPackedSingle>, TB, VEX_4V;
2554 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2555 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2556 SSEPackedDouble>, TB, OpSize, VEX_4V;
2558 let Constraints = "$src1 = $dst" in {
2559 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2560 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2561 SSEPackedSingle>, TB;
2562 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2563 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2564 SSEPackedDouble>, TB, OpSize;
2565 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2566 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2567 SSEPackedSingle>, TB;
2568 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2569 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2570 SSEPackedDouble>, TB, OpSize;
2571 } // Constraints = "$src1 = $dst"
2573 let Predicates = [HasAVX], AddedComplexity = 1 in {
2574 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2575 // problem is during lowering, where it's not possible to recognize the load
2576 // fold cause it has two uses through a bitcast. One use disappears at isel
2577 // time and the fold opportunity reappears.
2578 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2579 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2582 let Predicates = [HasSSE2] in {
2583 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2584 // problem is during lowering, where it's not possible to recognize the load
2585 // fold cause it has two uses through a bitcast. One use disappears at isel
2586 // time and the fold opportunity reappears.
2587 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2588 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2591 //===----------------------------------------------------------------------===//
2592 // SSE 1 & 2 - Extract Floating-Point Sign mask
2593 //===----------------------------------------------------------------------===//
2595 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2596 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2598 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2599 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2600 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2601 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2602 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2603 IIC_SSE_MOVMSK, d>, REX_W;
2606 let Predicates = [HasAVX] in {
2607 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2608 "movmskps", SSEPackedSingle>, TB, VEX;
2609 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2610 "movmskpd", SSEPackedDouble>, TB,
2612 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2613 "movmskps", SSEPackedSingle>, TB, VEX;
2614 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2615 "movmskpd", SSEPackedDouble>, TB,
2618 def : Pat<(i32 (X86fgetsign FR32:$src)),
2619 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2621 def : Pat<(i64 (X86fgetsign FR32:$src)),
2622 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2624 def : Pat<(i32 (X86fgetsign FR64:$src)),
2625 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2627 def : Pat<(i64 (X86fgetsign FR64:$src)),
2628 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2632 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2633 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2634 SSEPackedSingle>, TB, VEX;
2635 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2636 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2637 SSEPackedDouble>, TB,
2639 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2640 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2641 SSEPackedSingle>, TB, VEX;
2642 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2643 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2644 SSEPackedDouble>, TB,
2648 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2649 SSEPackedSingle>, TB;
2650 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2651 SSEPackedDouble>, TB, OpSize;
2653 def : Pat<(i32 (X86fgetsign FR32:$src)),
2654 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2655 sub_ss))>, Requires<[HasSSE1]>;
2656 def : Pat<(i64 (X86fgetsign FR32:$src)),
2657 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2658 sub_ss))>, Requires<[HasSSE1]>;
2659 def : Pat<(i32 (X86fgetsign FR64:$src)),
2660 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2661 sub_sd))>, Requires<[HasSSE2]>;
2662 def : Pat<(i64 (X86fgetsign FR64:$src)),
2663 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2664 sub_sd))>, Requires<[HasSSE2]>;
2666 //===---------------------------------------------------------------------===//
2667 // SSE2 - Packed Integer Logical Instructions
2668 //===---------------------------------------------------------------------===//
2670 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2672 /// PDI_binop_rm - Simple SSE2 binary operator.
2673 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2674 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2675 X86MemOperand x86memop,
2677 bit IsCommutable = 0,
2679 let isCommutable = IsCommutable in
2680 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2681 (ins RC:$src1, RC:$src2),
2683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2684 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2685 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2686 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2687 (ins RC:$src1, x86memop:$src2),
2689 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2690 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2691 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2692 (bitconvert (memop_frag addr:$src2)))))],
2695 } // ExeDomain = SSEPackedInt
2697 // These are ordered here for pattern ordering requirements with the fp versions
2699 let Predicates = [HasAVX] in {
2700 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2701 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2702 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2703 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2704 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2705 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2706 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2707 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2710 let Constraints = "$src1 = $dst" in {
2711 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2712 i128mem, SSE_BIT_ITINS_P, 1>;
2713 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2714 i128mem, SSE_BIT_ITINS_P, 1>;
2715 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2716 i128mem, SSE_BIT_ITINS_P, 1>;
2717 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2718 i128mem, SSE_BIT_ITINS_P, 0>;
2719 } // Constraints = "$src1 = $dst"
2721 let Predicates = [HasAVX2] in {
2722 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2723 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2724 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2725 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2726 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2727 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2728 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2729 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2732 //===----------------------------------------------------------------------===//
2733 // SSE 1 & 2 - Logical Instructions
2734 //===----------------------------------------------------------------------===//
2736 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2738 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2739 SDNode OpNode, OpndItins itins> {
2740 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2741 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2744 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2745 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2748 let Constraints = "$src1 = $dst" in {
2749 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2750 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2753 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2754 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2759 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2760 let mayLoad = 0 in {
2761 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2763 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2765 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2769 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2770 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2773 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2775 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2777 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2778 // are all promoted to v2i64, and the patterns are covered by the int
2779 // version. This is needed in SSE only, because v2i64 isn't supported on
2780 // SSE1, but only on SSE2.
2781 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2782 !strconcat(OpcodeStr, "ps"), f128mem, [],
2783 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2784 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2786 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2787 !strconcat(OpcodeStr, "pd"), f128mem,
2788 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2789 (bc_v2i64 (v2f64 VR128:$src2))))],
2790 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2791 (memopv2i64 addr:$src2)))], 0>,
2793 let Constraints = "$src1 = $dst" in {
2794 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2795 !strconcat(OpcodeStr, "ps"), f128mem,
2796 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2797 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2798 (memopv2i64 addr:$src2)))]>, TB;
2800 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2801 !strconcat(OpcodeStr, "pd"), f128mem,
2802 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2803 (bc_v2i64 (v2f64 VR128:$src2))))],
2804 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2805 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2809 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2811 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2813 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2814 !strconcat(OpcodeStr, "ps"), f256mem,
2815 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2816 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2817 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2819 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2820 !strconcat(OpcodeStr, "pd"), f256mem,
2821 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2822 (bc_v4i64 (v4f64 VR256:$src2))))],
2823 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2824 (memopv4i64 addr:$src2)))], 0>,
2828 // AVX 256-bit packed logical ops forms
2829 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2830 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2831 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2832 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2834 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2835 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2836 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2837 let isCommutable = 0 in
2838 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2840 //===----------------------------------------------------------------------===//
2841 // SSE 1 & 2 - Arithmetic Instructions
2842 //===----------------------------------------------------------------------===//
2844 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2847 /// In addition, we also have a special variant of the scalar form here to
2848 /// represent the associated intrinsic operation. This form is unlike the
2849 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2850 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2852 /// These three forms can each be reg+reg or reg+mem.
2855 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2857 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2860 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2861 OpNode, FR32, f32mem,
2862 itins.s, Is2Addr>, XS;
2863 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2864 OpNode, FR64, f64mem,
2865 itins.d, Is2Addr>, XD;
2868 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2871 let mayLoad = 0 in {
2872 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2873 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2875 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2876 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2881 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2884 let mayLoad = 0 in {
2885 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2886 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2888 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2889 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2894 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2897 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2898 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2899 itins.s, Is2Addr>, XS;
2900 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2901 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2902 itins.d, Is2Addr>, XD;
2905 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2908 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2909 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2910 SSEPackedSingle, itins.s, Is2Addr>,
2913 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2914 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2915 SSEPackedDouble, itins.d, Is2Addr>,
2919 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2921 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2922 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2923 SSEPackedSingle, itins.s, 0>, TB;
2925 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2926 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2927 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2930 // Binary Arithmetic instructions
2931 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2932 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2934 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2935 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2937 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2938 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2940 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2941 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2944 let isCommutable = 0 in {
2945 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2946 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2948 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2949 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2950 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2951 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2953 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2954 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2956 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2957 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2959 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2960 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2961 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2962 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2964 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2965 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2967 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2968 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2969 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2970 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2974 let Constraints = "$src1 = $dst" in {
2975 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2976 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2977 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2978 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2979 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2980 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2982 let isCommutable = 0 in {
2983 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2984 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2985 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2986 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2987 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2988 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2989 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2990 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2991 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2992 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2993 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2994 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2995 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2996 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
3001 /// In addition, we also have a special variant of the scalar form here to
3002 /// represent the associated intrinsic operation. This form is unlike the
3003 /// plain scalar form, in that it takes an entire vector (instead of a
3004 /// scalar) and leaves the top elements undefined.
3006 /// And, we have a special variant form for a full-vector intrinsic form.
3008 def SSE_SQRTP : OpndItins<
3009 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
3012 def SSE_SQRTS : OpndItins<
3013 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
3016 def SSE_RCPP : OpndItins<
3017 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3020 def SSE_RCPS : OpndItins<
3021 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3024 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3025 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3026 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3027 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3028 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3029 [(set FR32:$dst, (OpNode FR32:$src))]>;
3030 // For scalar unary operations, fold a load into the operation
3031 // only in OptForSize mode. It eliminates an instruction, but it also
3032 // eliminates a whole-register clobber (the load), so it introduces a
3033 // partial register update condition.
3034 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3035 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3036 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3037 Requires<[HasSSE1, OptForSize]>;
3038 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3039 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3040 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3041 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3042 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3043 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3046 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3047 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3048 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3049 !strconcat(OpcodeStr,
3050 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3052 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3053 !strconcat(OpcodeStr,
3054 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3055 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3056 (ins VR128:$src1, ssmem:$src2),
3057 !strconcat(OpcodeStr,
3058 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3061 /// sse1_fp_unop_p - SSE1 unops in packed form.
3062 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3064 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3065 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3066 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3067 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3068 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3069 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3072 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3073 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3075 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3076 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3077 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3079 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3080 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3081 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3085 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3086 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3087 Intrinsic V4F32Int, OpndItins itins> {
3088 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3089 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3090 [(set VR128:$dst, (V4F32Int VR128:$src))],
3092 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3093 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3094 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3098 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3099 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3100 Intrinsic V4F32Int, OpndItins itins> {
3101 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3102 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3103 [(set VR256:$dst, (V4F32Int VR256:$src))],
3105 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3106 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3107 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3111 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3112 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3113 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3114 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3115 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3116 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3117 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3118 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3119 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3120 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3121 Requires<[HasSSE2, OptForSize]>;
3122 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3123 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3124 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3125 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3126 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3127 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3130 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3131 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3132 let neverHasSideEffects = 1 in {
3133 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3134 !strconcat(OpcodeStr,
3135 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3137 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3138 !strconcat(OpcodeStr,
3139 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3141 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3142 (ins VR128:$src1, sdmem:$src2),
3143 !strconcat(OpcodeStr,
3144 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3147 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3148 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3149 SDNode OpNode, OpndItins itins> {
3150 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3151 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3152 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3153 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3154 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3155 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3158 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3159 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3161 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3162 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3163 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3165 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3166 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3167 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3171 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3172 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3173 Intrinsic V2F64Int, OpndItins itins> {
3174 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3175 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3176 [(set VR128:$dst, (V2F64Int VR128:$src))],
3178 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3179 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3180 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3184 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3185 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3186 Intrinsic V2F64Int, OpndItins itins> {
3187 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3188 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3189 [(set VR256:$dst, (V2F64Int VR256:$src))],
3191 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3192 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3193 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3197 let Predicates = [HasAVX] in {
3199 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3200 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3202 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3203 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3204 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3205 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3206 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3208 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3210 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3212 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3216 // Reciprocal approximations. Note that these typically require refinement
3217 // in order to obtain suitable precision.
3218 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3219 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3220 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3221 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3223 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3226 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3227 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3228 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3229 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3231 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3235 let AddedComplexity = 1 in {
3236 def : Pat<(f32 (fsqrt FR32:$src)),
3237 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3238 def : Pat<(f32 (fsqrt (load addr:$src))),
3239 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3240 Requires<[HasAVX, OptForSize]>;
3241 def : Pat<(f64 (fsqrt FR64:$src)),
3242 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3243 def : Pat<(f64 (fsqrt (load addr:$src))),
3244 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3245 Requires<[HasAVX, OptForSize]>;
3247 def : Pat<(f32 (X86frsqrt FR32:$src)),
3248 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3249 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3250 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3251 Requires<[HasAVX, OptForSize]>;
3253 def : Pat<(f32 (X86frcp FR32:$src)),
3254 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3255 def : Pat<(f32 (X86frcp (load addr:$src))),
3256 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3257 Requires<[HasAVX, OptForSize]>;
3260 let Predicates = [HasAVX], AddedComplexity = 1 in {
3261 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3262 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3263 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3264 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3266 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3267 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3269 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3270 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3271 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3272 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3274 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3275 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3277 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3278 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3279 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3280 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3282 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3283 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3285 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3287 (VRCPSSr (f32 (IMPLICIT_DEF)),
3288 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3290 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3291 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3295 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3297 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3298 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3299 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3301 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3302 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3304 // Reciprocal approximations. Note that these typically require refinement
3305 // in order to obtain suitable precision.
3306 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3308 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3309 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3311 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3313 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3314 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3316 // There is no f64 version of the reciprocal approximation instructions.
3318 //===----------------------------------------------------------------------===//
3319 // SSE 1 & 2 - Non-temporal stores
3320 //===----------------------------------------------------------------------===//
3322 let AddedComplexity = 400 in { // Prefer non-temporal versions
3323 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3324 (ins f128mem:$dst, VR128:$src),
3325 "movntps\t{$src, $dst|$dst, $src}",
3326 [(alignednontemporalstore (v4f32 VR128:$src),
3328 IIC_SSE_MOVNT>, VEX;
3329 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3330 (ins f128mem:$dst, VR128:$src),
3331 "movntpd\t{$src, $dst|$dst, $src}",
3332 [(alignednontemporalstore (v2f64 VR128:$src),
3334 IIC_SSE_MOVNT>, VEX;
3336 let ExeDomain = SSEPackedInt in
3337 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3338 (ins f128mem:$dst, VR128:$src),
3339 "movntdq\t{$src, $dst|$dst, $src}",
3340 [(alignednontemporalstore (v2i64 VR128:$src),
3342 IIC_SSE_MOVNT>, VEX;
3344 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3345 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3347 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3348 (ins f256mem:$dst, VR256:$src),
3349 "movntps\t{$src, $dst|$dst, $src}",
3350 [(alignednontemporalstore (v8f32 VR256:$src),
3352 IIC_SSE_MOVNT>, VEX;
3353 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3354 (ins f256mem:$dst, VR256:$src),
3355 "movntpd\t{$src, $dst|$dst, $src}",
3356 [(alignednontemporalstore (v4f64 VR256:$src),
3358 IIC_SSE_MOVNT>, VEX;
3359 let ExeDomain = SSEPackedInt in
3360 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3361 (ins f256mem:$dst, VR256:$src),
3362 "movntdq\t{$src, $dst|$dst, $src}",
3363 [(alignednontemporalstore (v4i64 VR256:$src),
3365 IIC_SSE_MOVNT>, VEX;
3368 let AddedComplexity = 400 in { // Prefer non-temporal versions
3369 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3370 "movntps\t{$src, $dst|$dst, $src}",
3371 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3373 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3374 "movntpd\t{$src, $dst|$dst, $src}",
3375 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3378 let ExeDomain = SSEPackedInt in
3379 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3380 "movntdq\t{$src, $dst|$dst, $src}",
3381 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3384 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3385 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3387 // There is no AVX form for instructions below this point
3388 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3389 "movnti{l}\t{$src, $dst|$dst, $src}",
3390 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3392 TB, Requires<[HasSSE2]>;
3393 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3394 "movnti{q}\t{$src, $dst|$dst, $src}",
3395 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3397 TB, Requires<[HasSSE2]>;
3400 //===----------------------------------------------------------------------===//
3401 // SSE 1 & 2 - Prefetch and memory fence
3402 //===----------------------------------------------------------------------===//
3404 // Prefetch intrinsic.
3405 let Predicates = [HasSSE1] in {
3406 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3407 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3408 IIC_SSE_PREFETCH>, TB;
3409 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3410 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3411 IIC_SSE_PREFETCH>, TB;
3412 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3413 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3414 IIC_SSE_PREFETCH>, TB;
3415 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3416 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3417 IIC_SSE_PREFETCH>, TB;
3421 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3422 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3423 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3425 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3426 // was introduced with SSE2, it's backward compatible.
3427 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3429 // Load, store, and memory fence
3430 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3431 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3432 TB, Requires<[HasSSE1]>;
3433 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3434 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3435 TB, Requires<[HasSSE2]>;
3436 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3437 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3438 TB, Requires<[HasSSE2]>;
3440 def : Pat<(X86SFence), (SFENCE)>;
3441 def : Pat<(X86LFence), (LFENCE)>;
3442 def : Pat<(X86MFence), (MFENCE)>;
3444 //===----------------------------------------------------------------------===//
3445 // SSE 1 & 2 - Load/Store XCSR register
3446 //===----------------------------------------------------------------------===//
3448 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3449 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3450 IIC_SSE_LDMXCSR>, VEX;
3451 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3452 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3453 IIC_SSE_STMXCSR>, VEX;
3455 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3456 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3458 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3459 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3462 //===---------------------------------------------------------------------===//
3463 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3464 //===---------------------------------------------------------------------===//
3466 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3468 let neverHasSideEffects = 1 in {
3469 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3470 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3472 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3473 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3476 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3477 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3479 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3480 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3484 let isCodeGenOnly = 1 in {
3485 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3486 "movdqa\t{$src, $dst|$dst, $src}", [],
3489 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3490 "movdqa\t{$src, $dst|$dst, $src}", [],
3493 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3494 "movdqu\t{$src, $dst|$dst, $src}", [],
3497 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3498 "movdqu\t{$src, $dst|$dst, $src}", [],
3503 let canFoldAsLoad = 1, mayLoad = 1 in {
3504 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3505 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3507 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3508 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3510 let Predicates = [HasAVX] in {
3511 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3512 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3514 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3515 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3520 let mayStore = 1 in {
3521 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3522 (ins i128mem:$dst, VR128:$src),
3523 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3525 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3526 (ins i256mem:$dst, VR256:$src),
3527 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3529 let Predicates = [HasAVX] in {
3530 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3531 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3533 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3534 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3539 let neverHasSideEffects = 1 in
3540 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3541 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3543 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3544 "movdqu\t{$src, $dst|$dst, $src}",
3545 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3548 let isCodeGenOnly = 1 in {
3549 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3550 "movdqa\t{$src, $dst|$dst, $src}", [],
3553 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3554 "movdqu\t{$src, $dst|$dst, $src}",
3555 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3558 let canFoldAsLoad = 1, mayLoad = 1 in {
3559 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3560 "movdqa\t{$src, $dst|$dst, $src}",
3561 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3563 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3564 "movdqu\t{$src, $dst|$dst, $src}",
3565 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3567 XS, Requires<[HasSSE2]>;
3570 let mayStore = 1 in {
3571 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3572 "movdqa\t{$src, $dst|$dst, $src}",
3573 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3575 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3576 "movdqu\t{$src, $dst|$dst, $src}",
3577 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3579 XS, Requires<[HasSSE2]>;
3582 // Intrinsic forms of MOVDQU load and store
3583 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3584 "vmovdqu\t{$src, $dst|$dst, $src}",
3585 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3587 XS, VEX, Requires<[HasAVX]>;
3589 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3590 "movdqu\t{$src, $dst|$dst, $src}",
3591 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3593 XS, Requires<[HasSSE2]>;
3595 } // ExeDomain = SSEPackedInt
3597 let Predicates = [HasAVX] in {
3598 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3599 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3602 //===---------------------------------------------------------------------===//
3603 // SSE2 - Packed Integer Arithmetic Instructions
3604 //===---------------------------------------------------------------------===//
3606 def SSE_PMADD : OpndItins<
3607 IIC_SSE_PMADD, IIC_SSE_PMADD
3610 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3612 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3613 RegisterClass RC, PatFrag memop_frag,
3614 X86MemOperand x86memop,
3616 bit IsCommutable = 0,
3618 let isCommutable = IsCommutable in
3619 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3620 (ins RC:$src1, RC:$src2),
3622 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3624 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3625 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3626 (ins RC:$src1, x86memop:$src2),
3628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3629 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3630 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3634 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3635 string OpcodeStr, SDNode OpNode,
3636 SDNode OpNode2, RegisterClass RC,
3637 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3638 ShiftOpndItins itins,
3640 // src2 is always 128-bit
3641 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3642 (ins RC:$src1, VR128:$src2),
3644 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3645 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3646 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3648 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3649 (ins RC:$src1, i128mem:$src2),
3651 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3652 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3653 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3654 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3655 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3656 (ins RC:$src1, i32i8imm:$src2),
3658 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3659 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3660 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3663 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3664 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3665 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3666 PatFrag memop_frag, X86MemOperand x86memop,
3668 bit IsCommutable = 0, bit Is2Addr = 1> {
3669 let isCommutable = IsCommutable in
3670 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3671 (ins RC:$src1, RC:$src2),
3673 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3674 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3675 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3676 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3677 (ins RC:$src1, x86memop:$src2),
3679 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3680 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3681 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3682 (bitconvert (memop_frag addr:$src2)))))]>;
3684 } // ExeDomain = SSEPackedInt
3686 // 128-bit Integer Arithmetic
3688 let Predicates = [HasAVX] in {
3689 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3690 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3692 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3693 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3694 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3695 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3696 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3697 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3698 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3699 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3700 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3701 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3702 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3703 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3704 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3705 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3706 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3707 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3708 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3709 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3713 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3714 VR128, memopv2i64, i128mem,
3715 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3716 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3717 VR128, memopv2i64, i128mem,
3718 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3719 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3720 VR128, memopv2i64, i128mem,
3721 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3722 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3723 VR128, memopv2i64, i128mem,
3724 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3725 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3726 VR128, memopv2i64, i128mem,
3727 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3728 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3729 VR128, memopv2i64, i128mem,
3730 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3731 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3732 VR128, memopv2i64, i128mem,
3733 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3734 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3735 VR128, memopv2i64, i128mem,
3736 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3737 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3738 VR128, memopv2i64, i128mem,
3739 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3740 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3741 VR128, memopv2i64, i128mem,
3742 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3743 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3744 VR128, memopv2i64, i128mem,
3745 SSE_PMADD, 1, 0>, VEX_4V;
3746 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3747 VR128, memopv2i64, i128mem,
3748 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3749 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3750 VR128, memopv2i64, i128mem,
3751 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3752 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3753 VR128, memopv2i64, i128mem,
3754 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3755 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3756 VR128, memopv2i64, i128mem,
3757 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3758 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3759 VR128, memopv2i64, i128mem,
3760 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3761 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3762 VR128, memopv2i64, i128mem,
3763 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3764 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3765 VR128, memopv2i64, i128mem,
3766 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3769 let Predicates = [HasAVX2] in {
3770 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3771 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3772 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3773 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3774 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3775 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3776 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3777 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3778 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3779 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3780 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3781 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3782 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3783 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3784 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3785 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3786 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3787 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3788 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3789 VR256, memopv4i64, i256mem,
3790 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3793 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3794 VR256, memopv4i64, i256mem,
3795 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3796 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3797 VR256, memopv4i64, i256mem,
3798 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3799 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3800 VR256, memopv4i64, i256mem,
3801 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3802 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3803 VR256, memopv4i64, i256mem,
3804 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3805 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3806 VR256, memopv4i64, i256mem,
3807 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3808 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3809 VR256, memopv4i64, i256mem,
3810 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3811 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3812 VR256, memopv4i64, i256mem,
3813 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3814 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3815 VR256, memopv4i64, i256mem,
3816 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3817 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3818 VR256, memopv4i64, i256mem,
3819 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3820 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3821 VR256, memopv4i64, i256mem,
3822 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3823 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3824 VR256, memopv4i64, i256mem,
3825 SSE_PMADD, 1, 0>, VEX_4V;
3826 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3827 VR256, memopv4i64, i256mem,
3828 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3829 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3830 VR256, memopv4i64, i256mem,
3831 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3832 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3833 VR256, memopv4i64, i256mem,
3834 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3835 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3836 VR256, memopv4i64, i256mem,
3837 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3838 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3839 VR256, memopv4i64, i256mem,
3840 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3841 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3842 VR256, memopv4i64, i256mem,
3843 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3844 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3845 VR256, memopv4i64, i256mem,
3846 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3849 let Constraints = "$src1 = $dst" in {
3850 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3851 i128mem, SSE_INTALU_ITINS_P, 1>;
3852 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3853 i128mem, SSE_INTALU_ITINS_P, 1>;
3854 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3855 i128mem, SSE_INTALU_ITINS_P, 1>;
3856 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3857 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3858 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3859 i128mem, SSE_INTMUL_ITINS_P, 1>;
3860 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3861 i128mem, SSE_INTALU_ITINS_P>;
3862 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3863 i128mem, SSE_INTALU_ITINS_P>;
3864 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3865 i128mem, SSE_INTALU_ITINS_P>;
3866 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3867 i128mem, SSE_INTALUQ_ITINS_P>;
3868 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3869 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3872 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3873 VR128, memopv2i64, i128mem,
3874 SSE_INTALU_ITINS_P>;
3875 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3876 VR128, memopv2i64, i128mem,
3877 SSE_INTALU_ITINS_P>;
3878 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3879 VR128, memopv2i64, i128mem,
3880 SSE_INTALU_ITINS_P>;
3881 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3882 VR128, memopv2i64, i128mem,
3883 SSE_INTALU_ITINS_P>;
3884 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3885 VR128, memopv2i64, i128mem,
3886 SSE_INTALU_ITINS_P, 1>;
3887 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3888 VR128, memopv2i64, i128mem,
3889 SSE_INTALU_ITINS_P, 1>;
3890 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3891 VR128, memopv2i64, i128mem,
3892 SSE_INTALU_ITINS_P, 1>;
3893 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3894 VR128, memopv2i64, i128mem,
3895 SSE_INTALU_ITINS_P, 1>;
3896 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3897 VR128, memopv2i64, i128mem,
3898 SSE_INTMUL_ITINS_P, 1>;
3899 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3900 VR128, memopv2i64, i128mem,
3901 SSE_INTMUL_ITINS_P, 1>;
3902 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3903 VR128, memopv2i64, i128mem,
3905 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3906 VR128, memopv2i64, i128mem,
3907 SSE_INTALU_ITINS_P, 1>;
3908 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3909 VR128, memopv2i64, i128mem,
3910 SSE_INTALU_ITINS_P, 1>;
3911 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3912 VR128, memopv2i64, i128mem,
3913 SSE_INTALU_ITINS_P, 1>;
3914 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3915 VR128, memopv2i64, i128mem,
3916 SSE_INTALU_ITINS_P, 1>;
3917 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3918 VR128, memopv2i64, i128mem,
3919 SSE_INTALU_ITINS_P, 1>;
3920 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3921 VR128, memopv2i64, i128mem,
3922 SSE_INTALU_ITINS_P, 1>;
3923 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3924 VR128, memopv2i64, i128mem,
3925 SSE_INTALU_ITINS_P, 1>;
3927 } // Constraints = "$src1 = $dst"
3929 //===---------------------------------------------------------------------===//
3930 // SSE2 - Packed Integer Logical Instructions
3931 //===---------------------------------------------------------------------===//
3933 let Predicates = [HasAVX] in {
3934 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3935 VR128, v8i16, v8i16, bc_v8i16,
3936 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3937 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3938 VR128, v4i32, v4i32, bc_v4i32,
3939 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3940 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3941 VR128, v2i64, v2i64, bc_v2i64,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3944 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3945 VR128, v8i16, v8i16, bc_v8i16,
3946 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3947 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3948 VR128, v4i32, v4i32, bc_v4i32,
3949 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3950 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3951 VR128, v2i64, v2i64, bc_v2i64,
3952 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3954 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3955 VR128, v8i16, v8i16, bc_v8i16,
3956 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3957 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3958 VR128, v4i32, v4i32, bc_v4i32,
3959 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3961 let ExeDomain = SSEPackedInt in {
3962 // 128-bit logical shifts.
3963 def VPSLLDQri : PDIi8<0x73, MRM7r,
3964 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3965 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3967 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3969 def VPSRLDQri : PDIi8<0x73, MRM3r,
3970 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3971 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3973 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3975 // PSRADQri doesn't exist in SSE[1-3].
3977 } // Predicates = [HasAVX]
3979 let Predicates = [HasAVX2] in {
3980 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3981 VR256, v16i16, v8i16, bc_v8i16,
3982 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3983 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3984 VR256, v8i32, v4i32, bc_v4i32,
3985 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3986 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3987 VR256, v4i64, v2i64, bc_v2i64,
3988 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3990 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3991 VR256, v16i16, v8i16, bc_v8i16,
3992 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3993 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3994 VR256, v8i32, v4i32, bc_v4i32,
3995 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3996 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3997 VR256, v4i64, v2i64, bc_v2i64,
3998 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4000 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4001 VR256, v16i16, v8i16, bc_v8i16,
4002 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4003 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4004 VR256, v8i32, v4i32, bc_v4i32,
4005 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4007 let ExeDomain = SSEPackedInt in {
4008 // 256-bit logical shifts.
4009 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4010 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4011 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4013 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4015 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4016 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4017 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4019 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4021 // PSRADQYri doesn't exist in SSE[1-3].
4023 } // Predicates = [HasAVX2]
4025 let Constraints = "$src1 = $dst" in {
4026 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4027 VR128, v8i16, v8i16, bc_v8i16,
4028 SSE_INTSHIFT_ITINS_P>;
4029 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4030 VR128, v4i32, v4i32, bc_v4i32,
4031 SSE_INTSHIFT_ITINS_P>;
4032 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4033 VR128, v2i64, v2i64, bc_v2i64,
4034 SSE_INTSHIFT_ITINS_P>;
4036 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4037 VR128, v8i16, v8i16, bc_v8i16,
4038 SSE_INTSHIFT_ITINS_P>;
4039 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4040 VR128, v4i32, v4i32, bc_v4i32,
4041 SSE_INTSHIFT_ITINS_P>;
4042 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4043 VR128, v2i64, v2i64, bc_v2i64,
4044 SSE_INTSHIFT_ITINS_P>;
4046 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4047 VR128, v8i16, v8i16, bc_v8i16,
4048 SSE_INTSHIFT_ITINS_P>;
4049 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4050 VR128, v4i32, v4i32, bc_v4i32,
4051 SSE_INTSHIFT_ITINS_P>;
4053 let ExeDomain = SSEPackedInt in {
4054 // 128-bit logical shifts.
4055 def PSLLDQri : PDIi8<0x73, MRM7r,
4056 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4057 "pslldq\t{$src2, $dst|$dst, $src2}",
4059 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4060 def PSRLDQri : PDIi8<0x73, MRM3r,
4061 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4062 "psrldq\t{$src2, $dst|$dst, $src2}",
4064 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4065 // PSRADQri doesn't exist in SSE[1-3].
4067 } // Constraints = "$src1 = $dst"
4069 let Predicates = [HasAVX] in {
4070 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4071 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4072 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4073 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4074 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4075 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4077 // Shift up / down and insert zero's.
4078 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4079 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4080 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4081 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4084 let Predicates = [HasAVX2] in {
4085 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4086 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4087 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4088 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4091 let Predicates = [HasSSE2] in {
4092 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4093 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4094 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4095 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4096 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4097 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4099 // Shift up / down and insert zero's.
4100 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4101 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4102 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4103 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4106 //===---------------------------------------------------------------------===//
4107 // SSE2 - Packed Integer Comparison Instructions
4108 //===---------------------------------------------------------------------===//
4110 let Predicates = [HasAVX] in {
4111 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4112 VR128, memopv2i64, i128mem,
4113 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4114 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4115 VR128, memopv2i64, i128mem,
4116 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4117 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4118 VR128, memopv2i64, i128mem,
4119 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4120 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4121 VR128, memopv2i64, i128mem,
4122 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4123 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4124 VR128, memopv2i64, i128mem,
4125 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4126 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4127 VR128, memopv2i64, i128mem,
4128 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4131 let Predicates = [HasAVX2] in {
4132 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4133 VR256, memopv4i64, i256mem,
4134 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4135 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4136 VR256, memopv4i64, i256mem,
4137 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4138 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4139 VR256, memopv4i64, i256mem,
4140 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4141 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4142 VR256, memopv4i64, i256mem,
4143 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4144 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4145 VR256, memopv4i64, i256mem,
4146 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4147 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4148 VR256, memopv4i64, i256mem,
4149 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4152 let Constraints = "$src1 = $dst" in {
4153 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4154 VR128, memopv2i64, i128mem,
4155 SSE_INTALU_ITINS_P, 1>;
4156 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4157 VR128, memopv2i64, i128mem,
4158 SSE_INTALU_ITINS_P, 1>;
4159 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4160 VR128, memopv2i64, i128mem,
4161 SSE_INTALU_ITINS_P, 1>;
4162 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4163 VR128, memopv2i64, i128mem,
4164 SSE_INTALU_ITINS_P>;
4165 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4166 VR128, memopv2i64, i128mem,
4167 SSE_INTALU_ITINS_P>;
4168 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4169 VR128, memopv2i64, i128mem,
4170 SSE_INTALU_ITINS_P>;
4171 } // Constraints = "$src1 = $dst"
4173 //===---------------------------------------------------------------------===//
4174 // SSE2 - Packed Integer Pack Instructions
4175 //===---------------------------------------------------------------------===//
4177 let Predicates = [HasAVX] in {
4178 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4179 VR128, memopv2i64, i128mem,
4180 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4181 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4182 VR128, memopv2i64, i128mem,
4183 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4184 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4185 VR128, memopv2i64, i128mem,
4186 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4189 let Predicates = [HasAVX2] in {
4190 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4191 VR256, memopv4i64, i256mem,
4192 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4193 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4194 VR256, memopv4i64, i256mem,
4195 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4196 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4197 VR256, memopv4i64, i256mem,
4198 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4201 let Constraints = "$src1 = $dst" in {
4202 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4203 VR128, memopv2i64, i128mem,
4204 SSE_INTALU_ITINS_P>;
4205 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4206 VR128, memopv2i64, i128mem,
4207 SSE_INTALU_ITINS_P>;
4208 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4209 VR128, memopv2i64, i128mem,
4210 SSE_INTALU_ITINS_P>;
4211 } // Constraints = "$src1 = $dst"
4213 //===---------------------------------------------------------------------===//
4214 // SSE2 - Packed Integer Shuffle Instructions
4215 //===---------------------------------------------------------------------===//
4217 let ExeDomain = SSEPackedInt in {
4218 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4219 def ri : Ii8<0x70, MRMSrcReg,
4220 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4221 !strconcat(OpcodeStr,
4222 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4223 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4225 def mi : Ii8<0x70, MRMSrcMem,
4226 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4227 !strconcat(OpcodeStr,
4228 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4230 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4235 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4236 def Yri : Ii8<0x70, MRMSrcReg,
4237 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4238 !strconcat(OpcodeStr,
4239 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4240 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4241 def Ymi : Ii8<0x70, MRMSrcMem,
4242 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4243 !strconcat(OpcodeStr,
4244 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4246 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4247 (i8 imm:$src2))))]>;
4249 } // ExeDomain = SSEPackedInt
4251 let Predicates = [HasAVX] in {
4252 let AddedComplexity = 5 in
4253 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4255 // SSE2 with ImmT == Imm8 and XS prefix.
4256 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4258 // SSE2 with ImmT == Imm8 and XD prefix.
4259 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4261 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4262 (VPSHUFDmi addr:$src1, imm:$imm)>;
4263 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4264 (VPSHUFDri VR128:$src1, imm:$imm)>;
4267 let Predicates = [HasAVX2] in {
4268 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4269 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4270 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4273 let Predicates = [HasSSE2] in {
4274 let AddedComplexity = 5 in
4275 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4277 // SSE2 with ImmT == Imm8 and XS prefix.
4278 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4280 // SSE2 with ImmT == Imm8 and XD prefix.
4281 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4283 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4284 (PSHUFDmi addr:$src1, imm:$imm)>;
4285 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4286 (PSHUFDri VR128:$src1, imm:$imm)>;
4289 //===---------------------------------------------------------------------===//
4290 // SSE2 - Packed Integer Unpack Instructions
4291 //===---------------------------------------------------------------------===//
4293 let ExeDomain = SSEPackedInt in {
4294 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4295 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4296 def rr : PDI<opc, MRMSrcReg,
4297 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4299 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4300 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4301 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4303 def rm : PDI<opc, MRMSrcMem,
4304 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4306 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4307 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4308 [(set VR128:$dst, (OpNode VR128:$src1,
4309 (bc_frag (memopv2i64
4314 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4315 SDNode OpNode, PatFrag bc_frag> {
4316 def Yrr : PDI<opc, MRMSrcReg,
4317 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4318 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4319 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4320 def Yrm : PDI<opc, MRMSrcMem,
4321 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4322 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4323 [(set VR256:$dst, (OpNode VR256:$src1,
4324 (bc_frag (memopv4i64 addr:$src2))))]>;
4327 let Predicates = [HasAVX] in {
4328 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4329 bc_v16i8, 0>, VEX_4V;
4330 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4331 bc_v8i16, 0>, VEX_4V;
4332 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4333 bc_v4i32, 0>, VEX_4V;
4334 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4335 bc_v2i64, 0>, VEX_4V;
4337 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4338 bc_v16i8, 0>, VEX_4V;
4339 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4340 bc_v8i16, 0>, VEX_4V;
4341 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4342 bc_v4i32, 0>, VEX_4V;
4343 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4344 bc_v2i64, 0>, VEX_4V;
4347 let Predicates = [HasAVX2] in {
4348 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4350 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4352 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4354 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4357 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4359 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4361 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4363 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4367 let Constraints = "$src1 = $dst" in {
4368 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4370 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4372 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4374 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4377 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4379 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4381 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4383 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4386 } // ExeDomain = SSEPackedInt
4388 // Patterns for using AVX1 instructions with integer vectors
4389 // Here to give AVX2 priority
4390 let Predicates = [HasAVX] in {
4391 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4392 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4393 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4394 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4395 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4396 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4397 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4398 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4400 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4401 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4402 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4403 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4404 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4405 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4406 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4407 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4410 //===---------------------------------------------------------------------===//
4411 // SSE2 - Packed Integer Extract and Insert
4412 //===---------------------------------------------------------------------===//
4414 let ExeDomain = SSEPackedInt in {
4415 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4416 def rri : Ii8<0xC4, MRMSrcReg,
4417 (outs VR128:$dst), (ins VR128:$src1,
4418 GR32:$src2, i32i8imm:$src3),
4420 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4421 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4423 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4424 def rmi : Ii8<0xC4, MRMSrcMem,
4425 (outs VR128:$dst), (ins VR128:$src1,
4426 i16mem:$src2, i32i8imm:$src3),
4428 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4429 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4431 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4432 imm:$src3))], IIC_SSE_PINSRW>;
4436 let Predicates = [HasAVX] in
4437 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4438 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4439 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4440 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4441 imm:$src2))]>, TB, OpSize, VEX;
4442 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4443 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4444 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4445 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4446 imm:$src2))], IIC_SSE_PEXTRW>;
4449 let Predicates = [HasAVX] in {
4450 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4451 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4452 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4453 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4454 []>, TB, OpSize, VEX_4V;
4457 let Constraints = "$src1 = $dst" in
4458 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4460 } // ExeDomain = SSEPackedInt
4462 //===---------------------------------------------------------------------===//
4463 // SSE2 - Packed Mask Creation
4464 //===---------------------------------------------------------------------===//
4466 let ExeDomain = SSEPackedInt in {
4468 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4469 "pmovmskb\t{$src, $dst|$dst, $src}",
4470 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4471 IIC_SSE_MOVMSK>, VEX;
4472 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4473 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4475 let Predicates = [HasAVX2] in {
4476 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4477 "pmovmskb\t{$src, $dst|$dst, $src}",
4478 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4479 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4480 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4483 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4484 "pmovmskb\t{$src, $dst|$dst, $src}",
4485 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4488 } // ExeDomain = SSEPackedInt
4490 //===---------------------------------------------------------------------===//
4491 // SSE2 - Conditional Store
4492 //===---------------------------------------------------------------------===//
4494 let ExeDomain = SSEPackedInt in {
4497 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4498 (ins VR128:$src, VR128:$mask),
4499 "maskmovdqu\t{$mask, $src|$src, $mask}",
4500 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4501 IIC_SSE_MASKMOV>, VEX;
4503 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4504 (ins VR128:$src, VR128:$mask),
4505 "maskmovdqu\t{$mask, $src|$src, $mask}",
4506 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4507 IIC_SSE_MASKMOV>, VEX;
4510 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4511 "maskmovdqu\t{$mask, $src|$src, $mask}",
4512 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4515 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4516 "maskmovdqu\t{$mask, $src|$src, $mask}",
4517 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4520 } // ExeDomain = SSEPackedInt
4522 //===---------------------------------------------------------------------===//
4523 // SSE2 - Move Doubleword
4524 //===---------------------------------------------------------------------===//
4526 //===---------------------------------------------------------------------===//
4527 // Move Int Doubleword to Packed Double Int
4529 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4530 "movd\t{$src, $dst|$dst, $src}",
4532 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4534 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4535 "movd\t{$src, $dst|$dst, $src}",
4537 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4540 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4541 "mov{d|q}\t{$src, $dst|$dst, $src}",
4543 (v2i64 (scalar_to_vector GR64:$src)))],
4544 IIC_SSE_MOVDQ>, VEX;
4545 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4546 "mov{d|q}\t{$src, $dst|$dst, $src}",
4547 [(set FR64:$dst, (bitconvert GR64:$src))],
4548 IIC_SSE_MOVDQ>, VEX;
4550 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4551 "movd\t{$src, $dst|$dst, $src}",
4553 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4554 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4555 "movd\t{$src, $dst|$dst, $src}",
4557 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4559 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4560 "mov{d|q}\t{$src, $dst|$dst, $src}",
4562 (v2i64 (scalar_to_vector GR64:$src)))],
4564 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4565 "mov{d|q}\t{$src, $dst|$dst, $src}",
4566 [(set FR64:$dst, (bitconvert GR64:$src))],
4569 //===---------------------------------------------------------------------===//
4570 // Move Int Doubleword to Single Scalar
4572 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4573 "movd\t{$src, $dst|$dst, $src}",
4574 [(set FR32:$dst, (bitconvert GR32:$src))],
4575 IIC_SSE_MOVDQ>, VEX;
4577 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4578 "movd\t{$src, $dst|$dst, $src}",
4579 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4582 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4583 "movd\t{$src, $dst|$dst, $src}",
4584 [(set FR32:$dst, (bitconvert GR32:$src))],
4587 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4588 "movd\t{$src, $dst|$dst, $src}",
4589 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4592 //===---------------------------------------------------------------------===//
4593 // Move Packed Doubleword Int to Packed Double Int
4595 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4596 "movd\t{$src, $dst|$dst, $src}",
4597 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4598 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4599 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4600 (ins i32mem:$dst, VR128:$src),
4601 "movd\t{$src, $dst|$dst, $src}",
4602 [(store (i32 (vector_extract (v4i32 VR128:$src),
4603 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4605 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4606 "movd\t{$src, $dst|$dst, $src}",
4607 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4608 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4609 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4610 "movd\t{$src, $dst|$dst, $src}",
4611 [(store (i32 (vector_extract (v4i32 VR128:$src),
4612 (iPTR 0))), addr:$dst)],
4615 //===---------------------------------------------------------------------===//
4616 // Move Packed Doubleword Int first element to Doubleword Int
4618 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4619 "mov{d|q}\t{$src, $dst|$dst, $src}",
4620 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4623 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4625 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4626 "mov{d|q}\t{$src, $dst|$dst, $src}",
4627 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4631 //===---------------------------------------------------------------------===//
4632 // Bitcast FR64 <-> GR64
4634 let Predicates = [HasAVX] in
4635 def VMOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4636 "vmovq\t{$src, $dst|$dst, $src}",
4637 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4639 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4640 "mov{d|q}\t{$src, $dst|$dst, $src}",
4641 [(set GR64:$dst, (bitconvert FR64:$src))],
4642 IIC_SSE_MOVDQ>, VEX;
4643 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4644 "movq\t{$src, $dst|$dst, $src}",
4645 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4646 IIC_SSE_MOVDQ>, VEX;
4648 def MOV64toSDrm : SSDI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4649 "movq\t{$src, $dst|$dst, $src}",
4650 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4652 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4653 "mov{d|q}\t{$src, $dst|$dst, $src}",
4654 [(set GR64:$dst, (bitconvert FR64:$src))],
4656 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4657 "movq\t{$src, $dst|$dst, $src}",
4658 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4661 //===---------------------------------------------------------------------===//
4662 // Move Scalar Single to Double Int
4664 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4665 "movd\t{$src, $dst|$dst, $src}",
4666 [(set GR32:$dst, (bitconvert FR32:$src))],
4667 IIC_SSE_MOVD_ToGP>, VEX;
4668 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4669 "movd\t{$src, $dst|$dst, $src}",
4670 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4671 IIC_SSE_MOVDQ>, VEX;
4672 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4673 "movd\t{$src, $dst|$dst, $src}",
4674 [(set GR32:$dst, (bitconvert FR32:$src))],
4676 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4677 "movd\t{$src, $dst|$dst, $src}",
4678 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4681 //===---------------------------------------------------------------------===//
4682 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4684 let AddedComplexity = 15 in {
4685 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4686 "movd\t{$src, $dst|$dst, $src}",
4687 [(set VR128:$dst, (v4i32 (X86vzmovl
4688 (v4i32 (scalar_to_vector GR32:$src)))))],
4689 IIC_SSE_MOVDQ>, VEX;
4690 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4691 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4692 [(set VR128:$dst, (v2i64 (X86vzmovl
4693 (v2i64 (scalar_to_vector GR64:$src)))))],
4697 let AddedComplexity = 15 in {
4698 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4699 "movd\t{$src, $dst|$dst, $src}",
4700 [(set VR128:$dst, (v4i32 (X86vzmovl
4701 (v4i32 (scalar_to_vector GR32:$src)))))],
4703 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4704 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4705 [(set VR128:$dst, (v2i64 (X86vzmovl
4706 (v2i64 (scalar_to_vector GR64:$src)))))],
4710 let AddedComplexity = 20 in {
4711 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4712 "movd\t{$src, $dst|$dst, $src}",
4714 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4715 (loadi32 addr:$src))))))],
4716 IIC_SSE_MOVDQ>, VEX;
4717 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4718 "movd\t{$src, $dst|$dst, $src}",
4720 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4721 (loadi32 addr:$src))))))],
4725 let Predicates = [HasAVX] in {
4726 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4727 let AddedComplexity = 20 in {
4728 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4729 (VMOVZDI2PDIrm addr:$src)>;
4730 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4731 (VMOVZDI2PDIrm addr:$src)>;
4733 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4734 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4735 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4736 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4737 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4738 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4739 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4742 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4743 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4744 (MOVZDI2PDIrm addr:$src)>;
4745 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4746 (MOVZDI2PDIrm addr:$src)>;
4749 // These are the correct encodings of the instructions so that we know how to
4750 // read correct assembly, even though we continue to emit the wrong ones for
4751 // compatibility with Darwin's buggy assembler.
4752 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4753 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4754 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4755 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4756 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4757 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4758 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4759 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4760 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4761 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4762 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4763 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4765 //===---------------------------------------------------------------------===//
4766 // SSE2 - Move Quadword
4767 //===---------------------------------------------------------------------===//
4769 //===---------------------------------------------------------------------===//
4770 // Move Quadword Int to Packed Quadword Int
4772 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4773 "vmovq\t{$src, $dst|$dst, $src}",
4775 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4776 VEX, Requires<[HasAVX]>;
4777 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4778 "movq\t{$src, $dst|$dst, $src}",
4780 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4782 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4784 //===---------------------------------------------------------------------===//
4785 // Move Packed Quadword Int to Quadword Int
4787 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4788 "movq\t{$src, $dst|$dst, $src}",
4789 [(store (i64 (vector_extract (v2i64 VR128:$src),
4790 (iPTR 0))), addr:$dst)],
4791 IIC_SSE_MOVDQ>, VEX;
4792 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4793 "movq\t{$src, $dst|$dst, $src}",
4794 [(store (i64 (vector_extract (v2i64 VR128:$src),
4795 (iPTR 0))), addr:$dst)],
4798 //===---------------------------------------------------------------------===//
4799 // Store / copy lower 64-bits of a XMM register.
4801 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4802 "movq\t{$src, $dst|$dst, $src}",
4803 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4804 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4805 "movq\t{$src, $dst|$dst, $src}",
4806 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4809 let AddedComplexity = 20 in
4810 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4811 "vmovq\t{$src, $dst|$dst, $src}",
4813 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4814 (loadi64 addr:$src))))))],
4816 XS, VEX, Requires<[HasAVX]>;
4818 let AddedComplexity = 20 in
4819 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4820 "movq\t{$src, $dst|$dst, $src}",
4822 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4823 (loadi64 addr:$src))))))],
4825 XS, Requires<[HasSSE2]>;
4827 let Predicates = [HasAVX], AddedComplexity = 20 in {
4828 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4829 (VMOVZQI2PQIrm addr:$src)>;
4830 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4831 (VMOVZQI2PQIrm addr:$src)>;
4832 def : Pat<(v2i64 (X86vzload addr:$src)),
4833 (VMOVZQI2PQIrm addr:$src)>;
4836 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4837 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4838 (MOVZQI2PQIrm addr:$src)>;
4839 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4840 (MOVZQI2PQIrm addr:$src)>;
4841 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4844 let Predicates = [HasAVX] in {
4845 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4846 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4847 def : Pat<(v4i64 (X86vzload addr:$src)),
4848 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4851 //===---------------------------------------------------------------------===//
4852 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4853 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4855 let AddedComplexity = 15 in
4856 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4857 "vmovq\t{$src, $dst|$dst, $src}",
4858 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4860 XS, VEX, Requires<[HasAVX]>;
4861 let AddedComplexity = 15 in
4862 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4863 "movq\t{$src, $dst|$dst, $src}",
4864 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4866 XS, Requires<[HasSSE2]>;
4868 let AddedComplexity = 20 in
4869 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4870 "vmovq\t{$src, $dst|$dst, $src}",
4871 [(set VR128:$dst, (v2i64 (X86vzmovl
4872 (loadv2i64 addr:$src))))],
4874 XS, VEX, Requires<[HasAVX]>;
4875 let AddedComplexity = 20 in {
4876 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4877 "movq\t{$src, $dst|$dst, $src}",
4878 [(set VR128:$dst, (v2i64 (X86vzmovl
4879 (loadv2i64 addr:$src))))],
4881 XS, Requires<[HasSSE2]>;
4884 let AddedComplexity = 20 in {
4885 let Predicates = [HasAVX] in {
4886 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4887 (VMOVZPQILo2PQIrm addr:$src)>;
4888 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4889 (VMOVZPQILo2PQIrr VR128:$src)>;
4891 let Predicates = [HasSSE2] in {
4892 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4893 (MOVZPQILo2PQIrm addr:$src)>;
4894 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4895 (MOVZPQILo2PQIrr VR128:$src)>;
4899 // Instructions to match in the assembler
4900 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4901 "movq\t{$src, $dst|$dst, $src}", [],
4902 IIC_SSE_MOVDQ>, VEX, VEX_W;
4903 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4904 "movq\t{$src, $dst|$dst, $src}", [],
4905 IIC_SSE_MOVDQ>, VEX, VEX_W;
4906 // Recognize "movd" with GR64 destination, but encode as a "movq"
4907 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4908 "movd\t{$src, $dst|$dst, $src}", [],
4909 IIC_SSE_MOVDQ>, VEX, VEX_W;
4911 // Instructions for the disassembler
4912 // xr = XMM register
4915 let Predicates = [HasAVX] in
4916 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4917 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4918 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4919 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4921 //===---------------------------------------------------------------------===//
4922 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4923 //===---------------------------------------------------------------------===//
4924 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4925 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4926 X86MemOperand x86memop> {
4927 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4928 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4929 [(set RC:$dst, (vt (OpNode RC:$src)))],
4931 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4932 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4933 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4937 let Predicates = [HasAVX] in {
4938 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4939 v4f32, VR128, memopv4f32, f128mem>, VEX;
4940 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4941 v4f32, VR128, memopv4f32, f128mem>, VEX;
4942 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4943 v8f32, VR256, memopv8f32, f256mem>, VEX;
4944 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4945 v8f32, VR256, memopv8f32, f256mem>, VEX;
4947 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4948 memopv4f32, f128mem>;
4949 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4950 memopv4f32, f128mem>;
4952 let Predicates = [HasAVX] in {
4953 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4954 (VMOVSHDUPrr VR128:$src)>;
4955 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4956 (VMOVSHDUPrm addr:$src)>;
4957 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4958 (VMOVSLDUPrr VR128:$src)>;
4959 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4960 (VMOVSLDUPrm addr:$src)>;
4961 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4962 (VMOVSHDUPYrr VR256:$src)>;
4963 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4964 (VMOVSHDUPYrm addr:$src)>;
4965 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4966 (VMOVSLDUPYrr VR256:$src)>;
4967 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4968 (VMOVSLDUPYrm addr:$src)>;
4971 let Predicates = [HasSSE3] in {
4972 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4973 (MOVSHDUPrr VR128:$src)>;
4974 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4975 (MOVSHDUPrm addr:$src)>;
4976 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4977 (MOVSLDUPrr VR128:$src)>;
4978 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4979 (MOVSLDUPrm addr:$src)>;
4982 //===---------------------------------------------------------------------===//
4983 // SSE3 - Replicate Double FP - MOVDDUP
4984 //===---------------------------------------------------------------------===//
4986 multiclass sse3_replicate_dfp<string OpcodeStr> {
4987 let neverHasSideEffects = 1 in
4988 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4989 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4990 [], IIC_SSE_MOV_LH>;
4991 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4992 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4995 (scalar_to_vector (loadf64 addr:$src)))))],
4999 // FIXME: Merge with above classe when there're patterns for the ymm version
5000 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5001 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5002 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5003 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
5004 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5005 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5008 (scalar_to_vector (loadf64 addr:$src)))))]>;
5011 let Predicates = [HasAVX] in {
5012 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5013 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
5016 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5018 let Predicates = [HasAVX] in {
5019 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5020 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5021 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5022 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5023 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5024 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5025 def : Pat<(X86Movddup (bc_v2f64
5026 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5027 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5030 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5031 (VMOVDDUPYrm addr:$src)>;
5032 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5033 (VMOVDDUPYrm addr:$src)>;
5034 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5035 (VMOVDDUPYrm addr:$src)>;
5036 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5037 (VMOVDDUPYrr VR256:$src)>;
5040 let Predicates = [HasSSE3] in {
5041 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5042 (MOVDDUPrm addr:$src)>;
5043 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5044 (MOVDDUPrm addr:$src)>;
5045 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5046 (MOVDDUPrm addr:$src)>;
5047 def : Pat<(X86Movddup (bc_v2f64
5048 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5049 (MOVDDUPrm addr:$src)>;
5052 //===---------------------------------------------------------------------===//
5053 // SSE3 - Move Unaligned Integer
5054 //===---------------------------------------------------------------------===//
5056 let Predicates = [HasAVX] in {
5057 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5058 "vlddqu\t{$src, $dst|$dst, $src}",
5059 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5060 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5061 "vlddqu\t{$src, $dst|$dst, $src}",
5062 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5064 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5065 "lddqu\t{$src, $dst|$dst, $src}",
5066 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5069 //===---------------------------------------------------------------------===//
5070 // SSE3 - Arithmetic
5071 //===---------------------------------------------------------------------===//
5073 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5074 X86MemOperand x86memop, OpndItins itins,
5076 def rr : I<0xD0, MRMSrcReg,
5077 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5079 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5080 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5081 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5082 def rm : I<0xD0, MRMSrcMem,
5083 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5085 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5086 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5087 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5090 let Predicates = [HasAVX] in {
5091 let ExeDomain = SSEPackedSingle in {
5092 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5093 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5094 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5095 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5097 let ExeDomain = SSEPackedDouble in {
5098 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5099 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5100 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5101 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5104 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5105 let ExeDomain = SSEPackedSingle in
5106 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5107 f128mem, SSE_ALU_F32P>, TB, XD;
5108 let ExeDomain = SSEPackedDouble in
5109 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5110 f128mem, SSE_ALU_F64P>, TB, OpSize;
5113 //===---------------------------------------------------------------------===//
5114 // SSE3 Instructions
5115 //===---------------------------------------------------------------------===//
5118 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5119 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5120 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5122 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5123 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5124 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5126 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5130 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5131 IIC_SSE_HADDSUB_RM>;
5133 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5134 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5135 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5137 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5138 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5139 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5141 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5143 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5144 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5145 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5146 IIC_SSE_HADDSUB_RM>;
5149 let Predicates = [HasAVX] in {
5150 let ExeDomain = SSEPackedSingle in {
5151 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5152 X86fhadd, 0>, VEX_4V;
5153 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5154 X86fhsub, 0>, VEX_4V;
5155 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5156 X86fhadd, 0>, VEX_4V;
5157 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5158 X86fhsub, 0>, VEX_4V;
5160 let ExeDomain = SSEPackedDouble in {
5161 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5162 X86fhadd, 0>, VEX_4V;
5163 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5164 X86fhsub, 0>, VEX_4V;
5165 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5166 X86fhadd, 0>, VEX_4V;
5167 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5168 X86fhsub, 0>, VEX_4V;
5172 let Constraints = "$src1 = $dst" in {
5173 let ExeDomain = SSEPackedSingle in {
5174 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5175 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5177 let ExeDomain = SSEPackedDouble in {
5178 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5179 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5183 //===---------------------------------------------------------------------===//
5184 // SSSE3 - Packed Absolute Instructions
5185 //===---------------------------------------------------------------------===//
5188 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5189 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5190 Intrinsic IntId128> {
5191 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5193 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5194 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5197 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5199 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5202 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5206 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5207 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5208 Intrinsic IntId256> {
5209 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5212 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5215 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5217 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5220 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5223 let Predicates = [HasAVX] in {
5224 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5225 int_x86_ssse3_pabs_b_128>, VEX;
5226 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5227 int_x86_ssse3_pabs_w_128>, VEX;
5228 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5229 int_x86_ssse3_pabs_d_128>, VEX;
5232 let Predicates = [HasAVX2] in {
5233 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5234 int_x86_avx2_pabs_b>, VEX;
5235 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5236 int_x86_avx2_pabs_w>, VEX;
5237 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5238 int_x86_avx2_pabs_d>, VEX;
5241 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5242 int_x86_ssse3_pabs_b_128>;
5243 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5244 int_x86_ssse3_pabs_w_128>;
5245 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5246 int_x86_ssse3_pabs_d_128>;
5248 //===---------------------------------------------------------------------===//
5249 // SSSE3 - Packed Binary Operator Instructions
5250 //===---------------------------------------------------------------------===//
5252 def SSE_PHADDSUBD : OpndItins<
5253 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5255 def SSE_PHADDSUBSW : OpndItins<
5256 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5258 def SSE_PHADDSUBW : OpndItins<
5259 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5261 def SSE_PSHUFB : OpndItins<
5262 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5264 def SSE_PSIGN : OpndItins<
5265 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5267 def SSE_PMULHRSW : OpndItins<
5268 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5271 /// SS3I_binop_rm - Simple SSSE3 bin op
5272 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5273 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5274 X86MemOperand x86memop, OpndItins itins,
5276 let isCommutable = 1 in
5277 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5278 (ins RC:$src1, RC:$src2),
5280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5282 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5284 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5285 (ins RC:$src1, x86memop:$src2),
5287 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5290 (OpVT (OpNode RC:$src1,
5291 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5294 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5295 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5296 Intrinsic IntId128, OpndItins itins,
5298 let isCommutable = 1 in
5299 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5300 (ins VR128:$src1, VR128:$src2),
5302 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5303 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5304 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5306 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5307 (ins VR128:$src1, i128mem:$src2),
5309 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5310 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5312 (IntId128 VR128:$src1,
5313 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5316 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5317 Intrinsic IntId256> {
5318 let isCommutable = 1 in
5319 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5320 (ins VR256:$src1, VR256:$src2),
5321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5322 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5324 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5325 (ins VR256:$src1, i256mem:$src2),
5326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5328 (IntId256 VR256:$src1,
5329 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5332 let ImmT = NoImm, Predicates = [HasAVX] in {
5333 let isCommutable = 0 in {
5334 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5335 memopv2i64, i128mem,
5336 SSE_PHADDSUBW, 0>, VEX_4V;
5337 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5338 memopv2i64, i128mem,
5339 SSE_PHADDSUBD, 0>, VEX_4V;
5340 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5341 memopv2i64, i128mem,
5342 SSE_PHADDSUBW, 0>, VEX_4V;
5343 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5344 memopv2i64, i128mem,
5345 SSE_PHADDSUBD, 0>, VEX_4V;
5346 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5347 memopv2i64, i128mem,
5348 SSE_PSIGN, 0>, VEX_4V;
5349 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5350 memopv2i64, i128mem,
5351 SSE_PSIGN, 0>, VEX_4V;
5352 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5353 memopv2i64, i128mem,
5354 SSE_PSIGN, 0>, VEX_4V;
5355 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5356 memopv2i64, i128mem,
5357 SSE_PSHUFB, 0>, VEX_4V;
5358 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5359 int_x86_ssse3_phadd_sw_128,
5360 SSE_PHADDSUBSW, 0>, VEX_4V;
5361 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5362 int_x86_ssse3_phsub_sw_128,
5363 SSE_PHADDSUBSW, 0>, VEX_4V;
5364 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5365 int_x86_ssse3_pmadd_ub_sw_128,
5366 SSE_PMADD, 0>, VEX_4V;
5368 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5369 int_x86_ssse3_pmul_hr_sw_128,
5370 SSE_PMULHRSW, 0>, VEX_4V;
5373 let ImmT = NoImm, Predicates = [HasAVX2] in {
5374 let isCommutable = 0 in {
5375 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5376 memopv4i64, i256mem,
5377 SSE_PHADDSUBW, 0>, VEX_4V;
5378 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5379 memopv4i64, i256mem,
5380 SSE_PHADDSUBW, 0>, VEX_4V;
5381 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5382 memopv4i64, i256mem,
5383 SSE_PHADDSUBW, 0>, VEX_4V;
5384 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5385 memopv4i64, i256mem,
5386 SSE_PHADDSUBW, 0>, VEX_4V;
5387 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5388 memopv4i64, i256mem,
5389 SSE_PHADDSUBW, 0>, VEX_4V;
5390 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5391 memopv4i64, i256mem,
5392 SSE_PHADDSUBW, 0>, VEX_4V;
5393 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5394 memopv4i64, i256mem,
5395 SSE_PHADDSUBW, 0>, VEX_4V;
5396 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5397 memopv4i64, i256mem,
5398 SSE_PHADDSUBW, 0>, VEX_4V;
5399 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5400 int_x86_avx2_phadd_sw>, VEX_4V;
5401 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5402 int_x86_avx2_phsub_sw>, VEX_4V;
5403 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5404 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5406 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5407 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5410 // None of these have i8 immediate fields.
5411 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5412 let isCommutable = 0 in {
5413 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5414 memopv2i64, i128mem, SSE_PHADDSUBW>;
5415 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5416 memopv2i64, i128mem, SSE_PHADDSUBD>;
5417 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5418 memopv2i64, i128mem, SSE_PHADDSUBW>;
5419 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5420 memopv2i64, i128mem, SSE_PHADDSUBD>;
5421 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5422 memopv2i64, i128mem, SSE_PSIGN>;
5423 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5424 memopv2i64, i128mem, SSE_PSIGN>;
5425 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5426 memopv2i64, i128mem, SSE_PSIGN>;
5427 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5428 memopv2i64, i128mem, SSE_PSHUFB>;
5429 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5430 int_x86_ssse3_phadd_sw_128,
5432 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5433 int_x86_ssse3_phsub_sw_128,
5435 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5436 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5438 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5439 int_x86_ssse3_pmul_hr_sw_128,
5443 //===---------------------------------------------------------------------===//
5444 // SSSE3 - Packed Align Instruction Patterns
5445 //===---------------------------------------------------------------------===//
5447 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5448 let neverHasSideEffects = 1 in {
5449 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5450 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5452 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5454 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5455 [], IIC_SSE_PALIGNR>, OpSize;
5457 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5458 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5460 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5462 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5463 [], IIC_SSE_PALIGNR>, OpSize;
5467 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5468 let neverHasSideEffects = 1 in {
5469 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5470 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5472 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5475 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5476 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5478 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5483 let Predicates = [HasAVX] in
5484 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5485 let Predicates = [HasAVX2] in
5486 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5487 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5488 defm PALIGN : ssse3_palign<"palignr">;
5490 let Predicates = [HasAVX2] in {
5491 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5492 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5493 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5494 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5495 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5496 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5497 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5498 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5501 let Predicates = [HasAVX] in {
5502 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5503 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5504 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5505 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5506 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5507 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5508 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5509 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5512 let Predicates = [HasSSSE3] in {
5513 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5514 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5515 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5516 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5517 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5518 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5519 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5520 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5523 //===---------------------------------------------------------------------===//
5524 // SSSE3 - Thread synchronization
5525 //===---------------------------------------------------------------------===//
5527 let usesCustomInserter = 1 in {
5528 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5529 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5530 Requires<[HasSSE3]>;
5531 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5532 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5533 Requires<[HasSSE3]>;
5536 let Uses = [EAX, ECX, EDX] in
5537 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5538 TB, Requires<[HasSSE3]>;
5539 let Uses = [ECX, EAX] in
5540 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5541 TB, Requires<[HasSSE3]>;
5543 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5544 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5546 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5547 Requires<[In32BitMode]>;
5548 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5549 Requires<[In64BitMode]>;
5551 //===----------------------------------------------------------------------===//
5552 // SSE4.1 - Packed Move with Sign/Zero Extend
5553 //===----------------------------------------------------------------------===//
5555 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5556 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5557 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5558 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5560 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5561 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5563 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5567 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5569 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5570 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5571 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5573 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5575 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5578 let Predicates = [HasAVX] in {
5579 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5581 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5583 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5585 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5587 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5589 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5593 let Predicates = [HasAVX2] in {
5594 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5595 int_x86_avx2_pmovsxbw>, VEX;
5596 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5597 int_x86_avx2_pmovsxwd>, VEX;
5598 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5599 int_x86_avx2_pmovsxdq>, VEX;
5600 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5601 int_x86_avx2_pmovzxbw>, VEX;
5602 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5603 int_x86_avx2_pmovzxwd>, VEX;
5604 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5605 int_x86_avx2_pmovzxdq>, VEX;
5608 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5609 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5610 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5611 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5612 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5613 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5615 let Predicates = [HasAVX] in {
5616 // Common patterns involving scalar load.
5617 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5618 (VPMOVSXBWrm addr:$src)>;
5619 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5620 (VPMOVSXBWrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5623 (VPMOVSXWDrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5625 (VPMOVSXWDrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5628 (VPMOVSXDQrm addr:$src)>;
5629 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5630 (VPMOVSXDQrm addr:$src)>;
5632 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5633 (VPMOVZXBWrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5635 (VPMOVZXBWrm addr:$src)>;
5637 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5638 (VPMOVZXWDrm addr:$src)>;
5639 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5640 (VPMOVZXWDrm addr:$src)>;
5642 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5643 (VPMOVZXDQrm addr:$src)>;
5644 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5645 (VPMOVZXDQrm addr:$src)>;
5648 let Predicates = [HasSSE41] in {
5649 // Common patterns involving scalar load.
5650 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5651 (PMOVSXBWrm addr:$src)>;
5652 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5653 (PMOVSXBWrm addr:$src)>;
5655 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5656 (PMOVSXWDrm addr:$src)>;
5657 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5658 (PMOVSXWDrm addr:$src)>;
5660 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5661 (PMOVSXDQrm addr:$src)>;
5662 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5663 (PMOVSXDQrm addr:$src)>;
5665 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5666 (PMOVZXBWrm addr:$src)>;
5667 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5668 (PMOVZXBWrm addr:$src)>;
5670 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5671 (PMOVZXWDrm addr:$src)>;
5672 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5673 (PMOVZXWDrm addr:$src)>;
5675 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5676 (PMOVZXDQrm addr:$src)>;
5677 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5678 (PMOVZXDQrm addr:$src)>;
5681 let Predicates = [HasAVX2] in {
5682 let AddedComplexity = 15 in {
5683 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5684 (VPMOVZXDQYrr VR128:$src)>;
5685 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5686 (VPMOVZXWDYrr VR128:$src)>;
5689 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5690 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5693 let Predicates = [HasAVX] in {
5694 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5695 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5698 let Predicates = [HasSSE41] in {
5699 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5700 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5704 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5705 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5706 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5707 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5709 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5710 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5712 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5716 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5718 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5720 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5722 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5723 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5725 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5729 let Predicates = [HasAVX] in {
5730 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5732 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5734 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5736 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5740 let Predicates = [HasAVX2] in {
5741 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5742 int_x86_avx2_pmovsxbd>, VEX;
5743 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5744 int_x86_avx2_pmovsxwq>, VEX;
5745 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5746 int_x86_avx2_pmovzxbd>, VEX;
5747 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5748 int_x86_avx2_pmovzxwq>, VEX;
5751 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5752 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5753 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5754 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5756 let Predicates = [HasAVX] in {
5757 // Common patterns involving scalar load
5758 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5759 (VPMOVSXBDrm addr:$src)>;
5760 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5761 (VPMOVSXWQrm addr:$src)>;
5763 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5764 (VPMOVZXBDrm addr:$src)>;
5765 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5766 (VPMOVZXWQrm addr:$src)>;
5769 let Predicates = [HasSSE41] in {
5770 // Common patterns involving scalar load
5771 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5772 (PMOVSXBDrm addr:$src)>;
5773 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5774 (PMOVSXWQrm addr:$src)>;
5776 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5777 (PMOVZXBDrm addr:$src)>;
5778 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5779 (PMOVZXWQrm addr:$src)>;
5782 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5783 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5785 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5787 // Expecting a i16 load any extended to i32 value.
5788 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5789 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5790 [(set VR128:$dst, (IntId (bitconvert
5791 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5795 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5797 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5798 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5799 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5801 // Expecting a i16 load any extended to i32 value.
5802 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5803 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5804 [(set VR256:$dst, (IntId (bitconvert
5805 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5809 let Predicates = [HasAVX] in {
5810 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5812 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5815 let Predicates = [HasAVX2] in {
5816 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5817 int_x86_avx2_pmovsxbq>, VEX;
5818 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5819 int_x86_avx2_pmovzxbq>, VEX;
5821 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5822 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5824 let Predicates = [HasAVX] in {
5825 // Common patterns involving scalar load
5826 def : Pat<(int_x86_sse41_pmovsxbq
5827 (bitconvert (v4i32 (X86vzmovl
5828 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5829 (VPMOVSXBQrm addr:$src)>;
5831 def : Pat<(int_x86_sse41_pmovzxbq
5832 (bitconvert (v4i32 (X86vzmovl
5833 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5834 (VPMOVZXBQrm addr:$src)>;
5837 let Predicates = [HasSSE41] in {
5838 // Common patterns involving scalar load
5839 def : Pat<(int_x86_sse41_pmovsxbq
5840 (bitconvert (v4i32 (X86vzmovl
5841 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5842 (PMOVSXBQrm addr:$src)>;
5844 def : Pat<(int_x86_sse41_pmovzxbq
5845 (bitconvert (v4i32 (X86vzmovl
5846 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5847 (PMOVZXBQrm addr:$src)>;
5850 //===----------------------------------------------------------------------===//
5851 // SSE4.1 - Extract Instructions
5852 //===----------------------------------------------------------------------===//
5854 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5855 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5856 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5857 (ins VR128:$src1, i32i8imm:$src2),
5858 !strconcat(OpcodeStr,
5859 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5860 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5862 let neverHasSideEffects = 1, mayStore = 1 in
5863 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5864 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5865 !strconcat(OpcodeStr,
5866 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5869 // There's an AssertZext in the way of writing the store pattern
5870 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5873 let Predicates = [HasAVX] in {
5874 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5875 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5876 (ins VR128:$src1, i32i8imm:$src2),
5877 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5880 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5883 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5884 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5885 let neverHasSideEffects = 1, mayStore = 1 in
5886 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5887 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5888 !strconcat(OpcodeStr,
5889 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5892 // There's an AssertZext in the way of writing the store pattern
5893 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5896 let Predicates = [HasAVX] in
5897 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5899 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5902 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5903 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5904 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5905 (ins VR128:$src1, i32i8imm:$src2),
5906 !strconcat(OpcodeStr,
5907 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5909 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5910 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5911 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5912 !strconcat(OpcodeStr,
5913 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5914 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5915 addr:$dst)]>, OpSize;
5918 let Predicates = [HasAVX] in
5919 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5921 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5923 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5924 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5925 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5926 (ins VR128:$src1, i32i8imm:$src2),
5927 !strconcat(OpcodeStr,
5928 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5930 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5931 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5932 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5933 !strconcat(OpcodeStr,
5934 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5935 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5936 addr:$dst)]>, OpSize, REX_W;
5939 let Predicates = [HasAVX] in
5940 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5942 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5944 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5946 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5947 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5948 (ins VR128:$src1, i32i8imm:$src2),
5949 !strconcat(OpcodeStr,
5950 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5952 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5954 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5955 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
5956 !strconcat(OpcodeStr,
5957 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5958 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
5959 addr:$dst)]>, OpSize;
5962 let ExeDomain = SSEPackedSingle in {
5963 let Predicates = [HasAVX] in {
5964 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
5965 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
5966 (ins VR128:$src1, i32i8imm:$src2),
5967 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
5970 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
5973 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
5974 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5977 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5979 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
5982 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
5983 Requires<[HasSSE41]>;
5985 //===----------------------------------------------------------------------===//
5986 // SSE4.1 - Insert Instructions
5987 //===----------------------------------------------------------------------===//
5989 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
5990 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5991 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
5993 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5995 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5997 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
5998 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5999 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6001 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6003 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6005 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6006 imm:$src3))]>, OpSize;
6009 let Predicates = [HasAVX] in
6010 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6011 let Constraints = "$src1 = $dst" in
6012 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6014 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6015 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6016 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6018 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6020 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6022 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6024 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6025 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6027 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6029 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6031 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6032 imm:$src3)))]>, OpSize;
6035 let Predicates = [HasAVX] in
6036 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6037 let Constraints = "$src1 = $dst" in
6038 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6040 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6041 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6042 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6044 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6046 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6048 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6050 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6051 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6053 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6055 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6057 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6058 imm:$src3)))]>, OpSize;
6061 let Predicates = [HasAVX] in
6062 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6063 let Constraints = "$src1 = $dst" in
6064 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6066 // insertps has a few different modes, there's the first two here below which
6067 // are optimized inserts that won't zero arbitrary elements in the destination
6068 // vector. The next one matches the intrinsic and could zero arbitrary elements
6069 // in the target vector.
6070 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6071 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6072 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6074 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6076 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6078 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6080 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6081 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6083 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6085 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6087 (X86insrtps VR128:$src1,
6088 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6089 imm:$src3))]>, OpSize;
6092 let ExeDomain = SSEPackedSingle in {
6093 let Predicates = [HasAVX] in
6094 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6095 let Constraints = "$src1 = $dst" in
6096 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6099 //===----------------------------------------------------------------------===//
6100 // SSE4.1 - Round Instructions
6101 //===----------------------------------------------------------------------===//
6103 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6104 X86MemOperand x86memop, RegisterClass RC,
6105 PatFrag mem_frag32, PatFrag mem_frag64,
6106 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6107 let ExeDomain = SSEPackedSingle in {
6108 // Intrinsic operation, reg.
6109 // Vector intrinsic operation, reg
6110 def PSr : SS4AIi8<opcps, MRMSrcReg,
6111 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6112 !strconcat(OpcodeStr,
6113 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6114 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6117 // Vector intrinsic operation, mem
6118 def PSm : SS4AIi8<opcps, MRMSrcMem,
6119 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6120 !strconcat(OpcodeStr,
6121 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6123 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6125 } // ExeDomain = SSEPackedSingle
6127 let ExeDomain = SSEPackedDouble in {
6128 // Vector intrinsic operation, reg
6129 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6130 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6131 !strconcat(OpcodeStr,
6132 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6133 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6136 // Vector intrinsic operation, mem
6137 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6138 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6139 !strconcat(OpcodeStr,
6140 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6142 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6144 } // ExeDomain = SSEPackedDouble
6147 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6150 Intrinsic F64Int, bit Is2Addr = 1> {
6151 let ExeDomain = GenericDomain in {
6153 def SSr : SS4AIi8<opcss, MRMSrcReg,
6154 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6156 !strconcat(OpcodeStr,
6157 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6158 !strconcat(OpcodeStr,
6159 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6162 // Intrinsic operation, reg.
6163 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6164 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6166 !strconcat(OpcodeStr,
6167 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6168 !strconcat(OpcodeStr,
6169 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6170 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6173 // Intrinsic operation, mem.
6174 def SSm : SS4AIi8<opcss, MRMSrcMem,
6175 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6177 !strconcat(OpcodeStr,
6178 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6179 !strconcat(OpcodeStr,
6180 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6182 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6186 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6187 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6189 !strconcat(OpcodeStr,
6190 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6191 !strconcat(OpcodeStr,
6192 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6195 // Intrinsic operation, reg.
6196 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6197 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6199 !strconcat(OpcodeStr,
6200 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6201 !strconcat(OpcodeStr,
6202 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6203 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6206 // Intrinsic operation, mem.
6207 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6208 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6210 !strconcat(OpcodeStr,
6211 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6212 !strconcat(OpcodeStr,
6213 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6215 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6217 } // ExeDomain = GenericDomain
6220 // FP round - roundss, roundps, roundsd, roundpd
6221 let Predicates = [HasAVX] in {
6223 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6224 memopv4f32, memopv2f64,
6225 int_x86_sse41_round_ps,
6226 int_x86_sse41_round_pd>, VEX;
6227 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6228 memopv8f32, memopv4f64,
6229 int_x86_avx_round_ps_256,
6230 int_x86_avx_round_pd_256>, VEX;
6231 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6232 int_x86_sse41_round_ss,
6233 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6235 def : Pat<(ffloor FR32:$src),
6236 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6237 def : Pat<(f64 (ffloor FR64:$src)),
6238 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6239 def : Pat<(f32 (fnearbyint FR32:$src)),
6240 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6241 def : Pat<(f64 (fnearbyint FR64:$src)),
6242 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6243 def : Pat<(f32 (fceil FR32:$src)),
6244 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6245 def : Pat<(f64 (fceil FR64:$src)),
6246 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6247 def : Pat<(f32 (frint FR32:$src)),
6248 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6249 def : Pat<(f64 (frint FR64:$src)),
6250 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6251 def : Pat<(f32 (ftrunc FR32:$src)),
6252 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6253 def : Pat<(f64 (ftrunc FR64:$src)),
6254 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6257 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6258 memopv4f32, memopv2f64,
6259 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6260 let Constraints = "$src1 = $dst" in
6261 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6262 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6264 def : Pat<(ffloor FR32:$src),
6265 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6266 def : Pat<(f64 (ffloor FR64:$src)),
6267 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6268 def : Pat<(f32 (fnearbyint FR32:$src)),
6269 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6270 def : Pat<(f64 (fnearbyint FR64:$src)),
6271 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6272 def : Pat<(f32 (fceil FR32:$src)),
6273 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6274 def : Pat<(f64 (fceil FR64:$src)),
6275 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6276 def : Pat<(f32 (frint FR32:$src)),
6277 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6278 def : Pat<(f64 (frint FR64:$src)),
6279 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6280 def : Pat<(f32 (ftrunc FR32:$src)),
6281 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6282 def : Pat<(f64 (ftrunc FR64:$src)),
6283 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6285 //===----------------------------------------------------------------------===//
6286 // SSE4.1 - Packed Bit Test
6287 //===----------------------------------------------------------------------===//
6289 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6290 // the intel intrinsic that corresponds to this.
6291 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6292 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6293 "vptest\t{$src2, $src1|$src1, $src2}",
6294 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6296 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6297 "vptest\t{$src2, $src1|$src1, $src2}",
6298 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6301 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6302 "vptest\t{$src2, $src1|$src1, $src2}",
6303 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6305 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6306 "vptest\t{$src2, $src1|$src1, $src2}",
6307 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6311 let Defs = [EFLAGS] in {
6312 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6313 "ptest\t{$src2, $src1|$src1, $src2}",
6314 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6316 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6317 "ptest\t{$src2, $src1|$src1, $src2}",
6318 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6322 // The bit test instructions below are AVX only
6323 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6324 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6325 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6326 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6327 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6328 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6329 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6330 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6334 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6335 let ExeDomain = SSEPackedSingle in {
6336 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6337 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6339 let ExeDomain = SSEPackedDouble in {
6340 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6341 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6345 //===----------------------------------------------------------------------===//
6346 // SSE4.1 - Misc Instructions
6347 //===----------------------------------------------------------------------===//
6349 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6350 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6351 "popcnt{w}\t{$src, $dst|$dst, $src}",
6352 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6354 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6355 "popcnt{w}\t{$src, $dst|$dst, $src}",
6356 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6357 (implicit EFLAGS)]>, OpSize, XS;
6359 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6360 "popcnt{l}\t{$src, $dst|$dst, $src}",
6361 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6363 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6364 "popcnt{l}\t{$src, $dst|$dst, $src}",
6365 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6366 (implicit EFLAGS)]>, XS;
6368 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6369 "popcnt{q}\t{$src, $dst|$dst, $src}",
6370 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6372 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6373 "popcnt{q}\t{$src, $dst|$dst, $src}",
6374 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6375 (implicit EFLAGS)]>, XS;
6380 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6381 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6382 Intrinsic IntId128> {
6383 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6385 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6386 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6387 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6389 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6392 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6395 let Predicates = [HasAVX] in
6396 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6397 int_x86_sse41_phminposuw>, VEX;
6398 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6399 int_x86_sse41_phminposuw>;
6401 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6402 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6403 Intrinsic IntId128, bit Is2Addr = 1> {
6404 let isCommutable = 1 in
6405 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6406 (ins VR128:$src1, VR128:$src2),
6408 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6409 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6410 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6411 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6412 (ins VR128:$src1, i128mem:$src2),
6414 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6415 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6417 (IntId128 VR128:$src1,
6418 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6421 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6422 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6423 Intrinsic IntId256> {
6424 let isCommutable = 1 in
6425 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6426 (ins VR256:$src1, VR256:$src2),
6427 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6428 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6429 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6430 (ins VR256:$src1, i256mem:$src2),
6431 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6433 (IntId256 VR256:$src1,
6434 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6437 let Predicates = [HasAVX] in {
6438 let isCommutable = 0 in
6439 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6441 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6443 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6445 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6447 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6449 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6451 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6453 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6455 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6457 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6461 let Predicates = [HasAVX2] in {
6462 let isCommutable = 0 in
6463 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6464 int_x86_avx2_packusdw>, VEX_4V;
6465 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6466 int_x86_avx2_pmins_b>, VEX_4V;
6467 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6468 int_x86_avx2_pmins_d>, VEX_4V;
6469 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6470 int_x86_avx2_pminu_d>, VEX_4V;
6471 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6472 int_x86_avx2_pminu_w>, VEX_4V;
6473 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6474 int_x86_avx2_pmaxs_b>, VEX_4V;
6475 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6476 int_x86_avx2_pmaxs_d>, VEX_4V;
6477 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6478 int_x86_avx2_pmaxu_d>, VEX_4V;
6479 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6480 int_x86_avx2_pmaxu_w>, VEX_4V;
6481 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6482 int_x86_avx2_pmul_dq>, VEX_4V;
6485 let Constraints = "$src1 = $dst" in {
6486 let isCommutable = 0 in
6487 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6488 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6489 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6490 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6491 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6492 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6493 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6494 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6495 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6496 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6499 /// SS48I_binop_rm - Simple SSE41 binary operator.
6500 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6501 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6502 X86MemOperand x86memop, bit Is2Addr = 1> {
6503 let isCommutable = 1 in
6504 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6505 (ins RC:$src1, RC:$src2),
6507 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6508 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6509 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6510 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6511 (ins RC:$src1, x86memop:$src2),
6513 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6514 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6516 (OpVT (OpNode RC:$src1,
6517 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6520 let Predicates = [HasAVX] in {
6521 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6522 memopv2i64, i128mem, 0>, VEX_4V;
6523 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6524 memopv2i64, i128mem, 0>, VEX_4V;
6526 let Predicates = [HasAVX2] in {
6527 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6528 memopv4i64, i256mem, 0>, VEX_4V;
6529 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6530 memopv4i64, i256mem, 0>, VEX_4V;
6533 let Constraints = "$src1 = $dst" in {
6534 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6535 memopv2i64, i128mem>;
6536 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6537 memopv2i64, i128mem>;
6540 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6541 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6542 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6543 X86MemOperand x86memop, bit Is2Addr = 1> {
6544 let isCommutable = 1 in
6545 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6546 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6548 !strconcat(OpcodeStr,
6549 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6550 !strconcat(OpcodeStr,
6551 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6552 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6554 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6555 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6557 !strconcat(OpcodeStr,
6558 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6559 !strconcat(OpcodeStr,
6560 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6563 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6567 let Predicates = [HasAVX] in {
6568 let isCommutable = 0 in {
6569 let ExeDomain = SSEPackedSingle in {
6570 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6571 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6572 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6573 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6575 let ExeDomain = SSEPackedDouble in {
6576 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6577 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6578 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6579 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6581 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6582 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6583 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6584 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6586 let ExeDomain = SSEPackedSingle in
6587 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6588 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6589 let ExeDomain = SSEPackedDouble in
6590 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6591 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6592 let ExeDomain = SSEPackedSingle in
6593 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6594 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6597 let Predicates = [HasAVX2] in {
6598 let isCommutable = 0 in {
6599 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6600 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6601 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6602 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6606 let Constraints = "$src1 = $dst" in {
6607 let isCommutable = 0 in {
6608 let ExeDomain = SSEPackedSingle in
6609 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6610 VR128, memopv4f32, i128mem>;
6611 let ExeDomain = SSEPackedDouble in
6612 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6613 VR128, memopv2f64, i128mem>;
6614 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6615 VR128, memopv2i64, i128mem>;
6616 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6617 VR128, memopv2i64, i128mem>;
6619 let ExeDomain = SSEPackedSingle in
6620 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6621 VR128, memopv4f32, i128mem>;
6622 let ExeDomain = SSEPackedDouble in
6623 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6624 VR128, memopv2f64, i128mem>;
6627 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6628 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6629 RegisterClass RC, X86MemOperand x86memop,
6630 PatFrag mem_frag, Intrinsic IntId> {
6631 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6632 (ins RC:$src1, RC:$src2, RC:$src3),
6633 !strconcat(OpcodeStr,
6634 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6635 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6636 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6638 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6639 (ins RC:$src1, x86memop:$src2, RC:$src3),
6640 !strconcat(OpcodeStr,
6641 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6643 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6645 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6648 let Predicates = [HasAVX] in {
6649 let ExeDomain = SSEPackedDouble in {
6650 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6651 memopv2f64, int_x86_sse41_blendvpd>;
6652 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6653 memopv4f64, int_x86_avx_blendv_pd_256>;
6654 } // ExeDomain = SSEPackedDouble
6655 let ExeDomain = SSEPackedSingle in {
6656 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6657 memopv4f32, int_x86_sse41_blendvps>;
6658 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6659 memopv8f32, int_x86_avx_blendv_ps_256>;
6660 } // ExeDomain = SSEPackedSingle
6661 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6662 memopv2i64, int_x86_sse41_pblendvb>;
6665 let Predicates = [HasAVX2] in {
6666 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6667 memopv4i64, int_x86_avx2_pblendvb>;
6670 let Predicates = [HasAVX] in {
6671 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6672 (v16i8 VR128:$src2))),
6673 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6674 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6675 (v4i32 VR128:$src2))),
6676 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6677 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6678 (v4f32 VR128:$src2))),
6679 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6680 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6681 (v2i64 VR128:$src2))),
6682 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6683 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6684 (v2f64 VR128:$src2))),
6685 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6686 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6687 (v8i32 VR256:$src2))),
6688 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6689 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6690 (v8f32 VR256:$src2))),
6691 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6692 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6693 (v4i64 VR256:$src2))),
6694 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6695 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6696 (v4f64 VR256:$src2))),
6697 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6699 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6701 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6702 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6704 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6706 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6708 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6709 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6711 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6712 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6714 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6717 let Predicates = [HasAVX2] in {
6718 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6719 (v32i8 VR256:$src2))),
6720 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6721 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6723 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6726 /// SS41I_ternary_int - SSE 4.1 ternary operator
6727 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6728 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6730 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6731 (ins VR128:$src1, VR128:$src2),
6732 !strconcat(OpcodeStr,
6733 "\t{$src2, $dst|$dst, $src2}"),
6734 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6737 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6738 (ins VR128:$src1, i128mem:$src2),
6739 !strconcat(OpcodeStr,
6740 "\t{$src2, $dst|$dst, $src2}"),
6743 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6747 let ExeDomain = SSEPackedDouble in
6748 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6749 int_x86_sse41_blendvpd>;
6750 let ExeDomain = SSEPackedSingle in
6751 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6752 int_x86_sse41_blendvps>;
6753 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6754 int_x86_sse41_pblendvb>;
6756 let Predicates = [HasSSE41] in {
6757 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6758 (v16i8 VR128:$src2))),
6759 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6760 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6761 (v4i32 VR128:$src2))),
6762 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6763 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6764 (v4f32 VR128:$src2))),
6765 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6766 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6767 (v2i64 VR128:$src2))),
6768 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6769 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6770 (v2f64 VR128:$src2))),
6771 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6773 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6775 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6776 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6778 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6779 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6781 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6785 let Predicates = [HasAVX] in
6786 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6787 "vmovntdqa\t{$src, $dst|$dst, $src}",
6788 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6790 let Predicates = [HasAVX2] in
6791 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6792 "vmovntdqa\t{$src, $dst|$dst, $src}",
6793 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6795 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6796 "movntdqa\t{$src, $dst|$dst, $src}",
6797 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6800 //===----------------------------------------------------------------------===//
6801 // SSE4.2 - Compare Instructions
6802 //===----------------------------------------------------------------------===//
6804 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6805 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6806 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6807 X86MemOperand x86memop, bit Is2Addr = 1> {
6808 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6809 (ins RC:$src1, RC:$src2),
6811 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6812 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6813 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6815 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6816 (ins RC:$src1, x86memop:$src2),
6818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6819 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6821 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6824 let Predicates = [HasAVX] in
6825 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6826 memopv2i64, i128mem, 0>, VEX_4V;
6828 let Predicates = [HasAVX2] in
6829 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6830 memopv4i64, i256mem, 0>, VEX_4V;
6832 let Constraints = "$src1 = $dst" in
6833 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6834 memopv2i64, i128mem>;
6836 //===----------------------------------------------------------------------===//
6837 // SSE4.2 - String/text Processing Instructions
6838 //===----------------------------------------------------------------------===//
6840 // Packed Compare Implicit Length Strings, Return Mask
6841 multiclass pseudo_pcmpistrm<string asm> {
6842 def REG : PseudoI<(outs VR128:$dst),
6843 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6844 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6846 def MEM : PseudoI<(outs VR128:$dst),
6847 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6848 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6849 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6852 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6853 let AddedComplexity = 1 in
6854 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6855 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6858 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6859 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6860 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6861 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6863 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6864 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6865 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6868 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6869 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6870 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6871 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6873 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6874 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6875 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6878 // Packed Compare Explicit Length Strings, Return Mask
6879 multiclass pseudo_pcmpestrm<string asm> {
6880 def REG : PseudoI<(outs VR128:$dst),
6881 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6882 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6883 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6884 def MEM : PseudoI<(outs VR128:$dst),
6885 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6886 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6887 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6890 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6891 let AddedComplexity = 1 in
6892 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6893 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6896 let Predicates = [HasAVX],
6897 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6898 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6899 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6900 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6902 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6903 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6904 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6907 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6908 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6909 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6910 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6912 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6913 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6914 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6917 // Packed Compare Implicit Length Strings, Return Index
6918 let Defs = [ECX, EFLAGS] in {
6919 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6920 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6921 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6922 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6923 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6924 (implicit EFLAGS)]>, OpSize;
6925 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6926 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6927 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6928 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6929 (implicit EFLAGS)]>, OpSize;
6933 let Predicates = [HasAVX] in {
6934 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6936 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6938 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6940 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6942 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6944 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6948 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6949 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6950 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6951 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6952 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6953 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
6955 // Packed Compare Explicit Length Strings, Return Index
6956 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
6957 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
6958 def rr : SS42AI<0x61, MRMSrcReg, (outs),
6959 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6960 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6961 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
6962 (implicit EFLAGS)]>, OpSize;
6963 def rm : SS42AI<0x61, MRMSrcMem, (outs),
6964 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6965 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
6967 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
6968 (implicit EFLAGS)]>, OpSize;
6972 let Predicates = [HasAVX] in {
6973 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
6975 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
6977 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
6979 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
6981 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
6983 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
6987 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
6988 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
6989 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
6990 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
6991 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
6992 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
6994 //===----------------------------------------------------------------------===//
6995 // SSE4.2 - CRC Instructions
6996 //===----------------------------------------------------------------------===//
6998 // No CRC instructions have AVX equivalents
7000 // crc intrinsic instruction
7001 // This set of instructions are only rm, the only difference is the size
7003 let Constraints = "$src1 = $dst" in {
7004 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7005 (ins GR32:$src1, i8mem:$src2),
7006 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7008 (int_x86_sse42_crc32_32_8 GR32:$src1,
7009 (load addr:$src2)))]>;
7010 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7011 (ins GR32:$src1, GR8:$src2),
7012 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7014 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7015 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7016 (ins GR32:$src1, i16mem:$src2),
7017 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7019 (int_x86_sse42_crc32_32_16 GR32:$src1,
7020 (load addr:$src2)))]>,
7022 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7023 (ins GR32:$src1, GR16:$src2),
7024 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7026 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7028 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7029 (ins GR32:$src1, i32mem:$src2),
7030 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7032 (int_x86_sse42_crc32_32_32 GR32:$src1,
7033 (load addr:$src2)))]>;
7034 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7035 (ins GR32:$src1, GR32:$src2),
7036 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7038 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7039 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7040 (ins GR64:$src1, i8mem:$src2),
7041 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7043 (int_x86_sse42_crc32_64_8 GR64:$src1,
7044 (load addr:$src2)))]>,
7046 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7047 (ins GR64:$src1, GR8:$src2),
7048 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7050 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7052 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7053 (ins GR64:$src1, i64mem:$src2),
7054 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7056 (int_x86_sse42_crc32_64_64 GR64:$src1,
7057 (load addr:$src2)))]>,
7059 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7060 (ins GR64:$src1, GR64:$src2),
7061 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7063 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7067 //===----------------------------------------------------------------------===//
7068 // AES-NI Instructions
7069 //===----------------------------------------------------------------------===//
7071 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7072 Intrinsic IntId128, bit Is2Addr = 1> {
7073 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7074 (ins VR128:$src1, VR128:$src2),
7076 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7077 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7078 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7080 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7081 (ins VR128:$src1, i128mem:$src2),
7083 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7084 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7086 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7089 // Perform One Round of an AES Encryption/Decryption Flow
7090 let Predicates = [HasAVX, HasAES] in {
7091 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7092 int_x86_aesni_aesenc, 0>, VEX_4V;
7093 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7094 int_x86_aesni_aesenclast, 0>, VEX_4V;
7095 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7096 int_x86_aesni_aesdec, 0>, VEX_4V;
7097 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7098 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7101 let Constraints = "$src1 = $dst" in {
7102 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7103 int_x86_aesni_aesenc>;
7104 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7105 int_x86_aesni_aesenclast>;
7106 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7107 int_x86_aesni_aesdec>;
7108 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7109 int_x86_aesni_aesdeclast>;
7112 // Perform the AES InvMixColumn Transformation
7113 let Predicates = [HasAVX, HasAES] in {
7114 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7116 "vaesimc\t{$src1, $dst|$dst, $src1}",
7118 (int_x86_aesni_aesimc VR128:$src1))]>,
7120 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7121 (ins i128mem:$src1),
7122 "vaesimc\t{$src1, $dst|$dst, $src1}",
7123 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7126 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7128 "aesimc\t{$src1, $dst|$dst, $src1}",
7130 (int_x86_aesni_aesimc VR128:$src1))]>,
7132 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7133 (ins i128mem:$src1),
7134 "aesimc\t{$src1, $dst|$dst, $src1}",
7135 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7138 // AES Round Key Generation Assist
7139 let Predicates = [HasAVX, HasAES] in {
7140 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7141 (ins VR128:$src1, i8imm:$src2),
7142 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7144 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7146 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7147 (ins i128mem:$src1, i8imm:$src2),
7148 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7150 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7153 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7154 (ins VR128:$src1, i8imm:$src2),
7155 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7157 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7159 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7160 (ins i128mem:$src1, i8imm:$src2),
7161 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7163 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7166 //===----------------------------------------------------------------------===//
7167 // PCLMUL Instructions
7168 //===----------------------------------------------------------------------===//
7170 // AVX carry-less Multiplication instructions
7171 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7172 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7173 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7175 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7177 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7178 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7179 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7180 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7181 (memopv2i64 addr:$src2), imm:$src3))]>;
7183 // Carry-less Multiplication instructions
7184 let Constraints = "$src1 = $dst" in {
7185 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7186 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7187 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7189 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7191 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7192 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7193 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7194 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7195 (memopv2i64 addr:$src2), imm:$src3))]>;
7196 } // Constraints = "$src1 = $dst"
7199 multiclass pclmul_alias<string asm, int immop> {
7200 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7201 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7203 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7204 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7206 def : InstAlias<!strconcat("vpclmul", asm,
7207 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7208 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7210 def : InstAlias<!strconcat("vpclmul", asm,
7211 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7212 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7214 defm : pclmul_alias<"hqhq", 0x11>;
7215 defm : pclmul_alias<"hqlq", 0x01>;
7216 defm : pclmul_alias<"lqhq", 0x10>;
7217 defm : pclmul_alias<"lqlq", 0x00>;
7219 //===----------------------------------------------------------------------===//
7220 // SSE4A Instructions
7221 //===----------------------------------------------------------------------===//
7223 let Predicates = [HasSSE4A] in {
7225 let Constraints = "$src = $dst" in {
7226 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7227 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7228 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7229 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7230 imm:$idx))]>, TB, OpSize;
7231 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7232 (ins VR128:$src, VR128:$mask),
7233 "extrq\t{$mask, $src|$src, $mask}",
7234 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7235 VR128:$mask))]>, TB, OpSize;
7237 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7238 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7239 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7240 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7241 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7242 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7243 (ins VR128:$src, VR128:$mask),
7244 "insertq\t{$mask, $src|$src, $mask}",
7245 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7246 VR128:$mask))]>, XD;
7249 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7250 "movntss\t{$src, $dst|$dst, $src}",
7251 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7253 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7254 "movntsd\t{$src, $dst|$dst, $src}",
7255 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7258 //===----------------------------------------------------------------------===//
7260 //===----------------------------------------------------------------------===//
7262 //===----------------------------------------------------------------------===//
7263 // VBROADCAST - Load from memory and broadcast to all elements of the
7264 // destination operand
7266 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7267 X86MemOperand x86memop, Intrinsic Int> :
7268 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7269 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7270 [(set RC:$dst, (Int addr:$src))]>, VEX;
7272 // AVX2 adds register forms
7273 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7275 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7276 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7277 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7279 let ExeDomain = SSEPackedSingle in {
7280 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7281 int_x86_avx_vbroadcast_ss>;
7282 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7283 int_x86_avx_vbroadcast_ss_256>;
7285 let ExeDomain = SSEPackedDouble in
7286 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7287 int_x86_avx_vbroadcast_sd_256>;
7288 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7289 int_x86_avx_vbroadcastf128_pd_256>;
7291 let ExeDomain = SSEPackedSingle in {
7292 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7293 int_x86_avx2_vbroadcast_ss_ps>;
7294 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7295 int_x86_avx2_vbroadcast_ss_ps_256>;
7297 let ExeDomain = SSEPackedDouble in
7298 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7299 int_x86_avx2_vbroadcast_sd_pd_256>;
7301 let Predicates = [HasAVX2] in
7302 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7303 int_x86_avx2_vbroadcasti128>;
7305 let Predicates = [HasAVX] in
7306 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7307 (VBROADCASTF128 addr:$src)>;
7310 //===----------------------------------------------------------------------===//
7311 // VINSERTF128 - Insert packed floating-point values
7313 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7314 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7315 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7316 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7319 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7320 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7321 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7325 let Predicates = [HasAVX] in {
7326 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7328 (VINSERTF128rr VR256:$src1, VR128:$src2,
7329 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7330 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7332 (VINSERTF128rr VR256:$src1, VR128:$src2,
7333 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7334 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7336 (VINSERTF128rr VR256:$src1, VR128:$src2,
7337 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7338 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7340 (VINSERTF128rr VR256:$src1, VR128:$src2,
7341 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7342 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7344 (VINSERTF128rr VR256:$src1, VR128:$src2,
7345 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7346 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7348 (VINSERTF128rr VR256:$src1, VR128:$src2,
7349 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7351 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7353 (VINSERTF128rm VR256:$src1, addr:$src2,
7354 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7355 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7357 (VINSERTF128rm VR256:$src1, addr:$src2,
7358 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7359 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7361 (VINSERTF128rm VR256:$src1, addr:$src2,
7362 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7365 //===----------------------------------------------------------------------===//
7366 // VEXTRACTF128 - Extract packed floating-point values
7368 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7369 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7370 (ins VR256:$src1, i8imm:$src2),
7371 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7374 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7375 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7376 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7380 // Extract and store.
7381 let Predicates = [HasAVX] in {
7382 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7383 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7384 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7385 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7386 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7387 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7389 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7390 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7391 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7392 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7393 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7394 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7398 let Predicates = [HasAVX] in {
7399 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7400 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7401 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7402 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7403 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7404 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7406 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7407 (v4f32 (VEXTRACTF128rr
7408 (v8f32 VR256:$src1),
7409 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7410 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7411 (v2f64 (VEXTRACTF128rr
7412 (v4f64 VR256:$src1),
7413 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7414 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7415 (v2i64 (VEXTRACTF128rr
7416 (v4i64 VR256:$src1),
7417 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7418 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7419 (v4i32 (VEXTRACTF128rr
7420 (v8i32 VR256:$src1),
7421 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7422 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7423 (v8i16 (VEXTRACTF128rr
7424 (v16i16 VR256:$src1),
7425 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7426 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7427 (v16i8 (VEXTRACTF128rr
7428 (v32i8 VR256:$src1),
7429 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7432 //===----------------------------------------------------------------------===//
7433 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7435 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7436 Intrinsic IntLd, Intrinsic IntLd256,
7437 Intrinsic IntSt, Intrinsic IntSt256> {
7438 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7439 (ins VR128:$src1, f128mem:$src2),
7440 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7441 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7443 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7444 (ins VR256:$src1, f256mem:$src2),
7445 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7446 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7448 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7449 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7450 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7451 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7452 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7453 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7454 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7455 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7458 let ExeDomain = SSEPackedSingle in
7459 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7460 int_x86_avx_maskload_ps,
7461 int_x86_avx_maskload_ps_256,
7462 int_x86_avx_maskstore_ps,
7463 int_x86_avx_maskstore_ps_256>;
7464 let ExeDomain = SSEPackedDouble in
7465 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7466 int_x86_avx_maskload_pd,
7467 int_x86_avx_maskload_pd_256,
7468 int_x86_avx_maskstore_pd,
7469 int_x86_avx_maskstore_pd_256>;
7471 //===----------------------------------------------------------------------===//
7472 // VPERMIL - Permute Single and Double Floating-Point Values
7474 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7475 RegisterClass RC, X86MemOperand x86memop_f,
7476 X86MemOperand x86memop_i, PatFrag i_frag,
7477 Intrinsic IntVar, ValueType vt> {
7478 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7479 (ins RC:$src1, RC:$src2),
7480 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7481 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7482 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7483 (ins RC:$src1, x86memop_i:$src2),
7484 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7485 [(set RC:$dst, (IntVar RC:$src1,
7486 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7488 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7489 (ins RC:$src1, i8imm:$src2),
7490 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7491 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7492 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7493 (ins x86memop_f:$src1, i8imm:$src2),
7494 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7496 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7499 let ExeDomain = SSEPackedSingle in {
7500 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7501 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7502 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7503 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7505 let ExeDomain = SSEPackedDouble in {
7506 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7507 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7508 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7509 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7512 let Predicates = [HasAVX] in {
7513 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7514 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7515 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7516 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7517 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7519 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7520 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7521 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7523 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7524 (VPERMILPDri VR128:$src1, imm:$imm)>;
7525 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7526 (VPERMILPDmi addr:$src1, imm:$imm)>;
7529 //===----------------------------------------------------------------------===//
7530 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7532 let ExeDomain = SSEPackedSingle in {
7533 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7534 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7535 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7536 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7537 (i8 imm:$src3))))]>, VEX_4V;
7538 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7539 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7540 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7541 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7542 (i8 imm:$src3)))]>, VEX_4V;
7545 let Predicates = [HasAVX] in {
7546 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7547 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7548 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7549 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7550 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7551 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7552 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7553 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7554 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7555 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7557 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7558 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7559 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7560 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7561 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7562 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7563 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7564 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7565 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7566 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7567 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7568 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7569 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7570 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7571 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7572 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7573 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7574 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7577 //===----------------------------------------------------------------------===//
7578 // VZERO - Zero YMM registers
7580 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7581 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7582 // Zero All YMM registers
7583 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7584 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7586 // Zero Upper bits of YMM registers
7587 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7588 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7591 //===----------------------------------------------------------------------===//
7592 // Half precision conversion instructions
7593 //===----------------------------------------------------------------------===//
7594 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7595 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7596 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7597 [(set RC:$dst, (Int VR128:$src))]>,
7599 let neverHasSideEffects = 1, mayLoad = 1 in
7600 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7601 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7604 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7605 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7606 (ins RC:$src1, i32i8imm:$src2),
7607 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7608 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7610 let neverHasSideEffects = 1, mayStore = 1 in
7611 def mr : Ii8<0x1D, MRMDestMem, (outs),
7612 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7613 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7617 let Predicates = [HasAVX, HasF16C] in {
7618 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7619 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7620 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7621 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7624 //===----------------------------------------------------------------------===//
7625 // AVX2 Instructions
7626 //===----------------------------------------------------------------------===//
7628 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7629 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7630 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7631 X86MemOperand x86memop> {
7632 let isCommutable = 1 in
7633 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7634 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7635 !strconcat(OpcodeStr,
7636 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7637 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7639 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7640 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7641 !strconcat(OpcodeStr,
7642 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7645 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7649 let isCommutable = 0 in {
7650 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7651 VR128, memopv2i64, i128mem>;
7652 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7653 VR256, memopv4i64, i256mem>;
7656 //===----------------------------------------------------------------------===//
7657 // VPBROADCAST - Load from memory and broadcast to all elements of the
7658 // destination operand
7660 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7661 X86MemOperand x86memop, PatFrag ld_frag,
7662 Intrinsic Int128, Intrinsic Int256> {
7663 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7664 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7665 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7666 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7667 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7669 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7670 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7671 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7672 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7673 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7674 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7676 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7679 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7680 int_x86_avx2_pbroadcastb_128,
7681 int_x86_avx2_pbroadcastb_256>;
7682 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7683 int_x86_avx2_pbroadcastw_128,
7684 int_x86_avx2_pbroadcastw_256>;
7685 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7686 int_x86_avx2_pbroadcastd_128,
7687 int_x86_avx2_pbroadcastd_256>;
7688 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7689 int_x86_avx2_pbroadcastq_128,
7690 int_x86_avx2_pbroadcastq_256>;
7692 let Predicates = [HasAVX2] in {
7693 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7694 (VPBROADCASTBrm addr:$src)>;
7695 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7696 (VPBROADCASTBYrm addr:$src)>;
7697 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7698 (VPBROADCASTWrm addr:$src)>;
7699 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7700 (VPBROADCASTWYrm addr:$src)>;
7701 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7702 (VPBROADCASTDrm addr:$src)>;
7703 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7704 (VPBROADCASTDYrm addr:$src)>;
7705 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7706 (VPBROADCASTQrm addr:$src)>;
7707 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7708 (VPBROADCASTQYrm addr:$src)>;
7710 // Provide fallback in case the load node that is used in the patterns above
7711 // is used by additional users, which prevents the pattern selection.
7712 let AddedComplexity = 20 in {
7713 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7715 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7716 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7718 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7719 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7721 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7723 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7725 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7726 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7728 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7729 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7731 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7735 // AVX1 broadcast patterns
7736 let Predicates = [HasAVX] in {
7737 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7738 (VBROADCASTSSYrm addr:$src)>;
7739 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7740 (VBROADCASTSDrm addr:$src)>;
7741 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7742 (VBROADCASTSSYrm addr:$src)>;
7743 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7744 (VBROADCASTSDrm addr:$src)>;
7745 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7746 (VBROADCASTSSrm addr:$src)>;
7747 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7748 (VBROADCASTSSrm addr:$src)>;
7750 // Provide fallback in case the load node that is used in the patterns above
7751 // is used by additional users, which prevents the pattern selection.
7752 let AddedComplexity = 20 in {
7753 // 128bit broadcasts:
7754 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7756 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7757 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7758 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7760 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7763 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7765 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7766 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7768 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7771 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7774 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7776 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7777 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7778 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7780 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7783 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7785 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7786 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7788 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7791 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7796 //===----------------------------------------------------------------------===//
7797 // VPERM - Permute instructions
7800 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7802 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7803 (ins VR256:$src1, VR256:$src2),
7804 !strconcat(OpcodeStr,
7805 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7807 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7808 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7809 (ins VR256:$src1, i256mem:$src2),
7810 !strconcat(OpcodeStr,
7811 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7813 (OpVT (X86VPermv VR256:$src1,
7814 (bitconvert (mem_frag addr:$src2)))))]>,
7818 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7819 let ExeDomain = SSEPackedSingle in
7820 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7822 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7824 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7825 (ins VR256:$src1, i8imm:$src2),
7826 !strconcat(OpcodeStr,
7827 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7829 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7830 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7831 (ins i256mem:$src1, i8imm:$src2),
7832 !strconcat(OpcodeStr,
7833 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7835 (OpVT (X86VPermi (mem_frag addr:$src1),
7836 (i8 imm:$src2))))]>, VEX;
7839 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7840 let ExeDomain = SSEPackedDouble in
7841 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7843 //===----------------------------------------------------------------------===//
7844 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7846 let AddedComplexity = 1 in {
7847 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7848 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7849 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7850 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7851 (i8 imm:$src3))))]>, VEX_4V;
7852 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7853 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7854 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7855 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7856 (i8 imm:$src3)))]>, VEX_4V;
7859 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7860 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7861 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7862 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7863 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7864 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7865 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7867 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7869 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7870 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7871 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7872 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7873 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7875 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7879 //===----------------------------------------------------------------------===//
7880 // VINSERTI128 - Insert packed integer values
7882 let neverHasSideEffects = 1 in {
7883 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7884 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7885 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7888 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7889 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7890 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7894 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7895 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7897 (VINSERTI128rr VR256:$src1, VR128:$src2,
7898 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7899 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7901 (VINSERTI128rr VR256:$src1, VR128:$src2,
7902 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7903 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7905 (VINSERTI128rr VR256:$src1, VR128:$src2,
7906 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7907 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7909 (VINSERTI128rr VR256:$src1, VR128:$src2,
7910 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7913 //===----------------------------------------------------------------------===//
7914 // VEXTRACTI128 - Extract packed integer values
7916 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7917 (ins VR256:$src1, i8imm:$src2),
7918 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7920 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7922 let neverHasSideEffects = 1, mayStore = 1 in
7923 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7924 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7925 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7927 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7928 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7929 (v2i64 (VEXTRACTI128rr
7930 (v4i64 VR256:$src1),
7931 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7932 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7933 (v4i32 (VEXTRACTI128rr
7934 (v8i32 VR256:$src1),
7935 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7936 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7937 (v8i16 (VEXTRACTI128rr
7938 (v16i16 VR256:$src1),
7939 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7940 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7941 (v16i8 (VEXTRACTI128rr
7942 (v32i8 VR256:$src1),
7943 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7946 //===----------------------------------------------------------------------===//
7947 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7949 multiclass avx2_pmovmask<string OpcodeStr,
7950 Intrinsic IntLd128, Intrinsic IntLd256,
7951 Intrinsic IntSt128, Intrinsic IntSt256> {
7952 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7953 (ins VR128:$src1, i128mem:$src2),
7954 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7955 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
7956 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
7957 (ins VR256:$src1, i256mem:$src2),
7958 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7959 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
7960 def mr : AVX28I<0x8e, MRMDestMem, (outs),
7961 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
7962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7963 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7964 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
7965 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
7966 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7967 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7970 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
7971 int_x86_avx2_maskload_d,
7972 int_x86_avx2_maskload_d_256,
7973 int_x86_avx2_maskstore_d,
7974 int_x86_avx2_maskstore_d_256>;
7975 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
7976 int_x86_avx2_maskload_q,
7977 int_x86_avx2_maskload_q_256,
7978 int_x86_avx2_maskstore_q,
7979 int_x86_avx2_maskstore_q_256>, VEX_W;
7982 //===----------------------------------------------------------------------===//
7983 // Variable Bit Shifts
7985 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
7986 ValueType vt128, ValueType vt256> {
7987 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
7988 (ins VR128:$src1, VR128:$src2),
7989 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7991 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
7993 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
7994 (ins VR128:$src1, i128mem:$src2),
7995 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7997 (vt128 (OpNode VR128:$src1,
7998 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8000 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8001 (ins VR256:$src1, VR256:$src2),
8002 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8004 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8006 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8007 (ins VR256:$src1, i256mem:$src2),
8008 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8010 (vt256 (OpNode VR256:$src1,
8011 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8015 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8016 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8017 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8018 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8019 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;