1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 def SSE_BIT_ITINS_P : OpndItins<
124 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
127 let Sched = WriteVecALU in {
128 def SSE_INTALU_ITINS_P : OpndItins<
129 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
132 def SSE_INTALUQ_ITINS_P : OpndItins<
133 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
137 let Sched = WriteVecIMul in
138 def SSE_INTMUL_ITINS_P : OpndItins<
139 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
142 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
143 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
146 def SSE_MOVA_ITINS : OpndItins<
147 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
150 def SSE_MOVU_ITINS : OpndItins<
151 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
154 //===----------------------------------------------------------------------===//
155 // SSE 1 & 2 Instructions Classes
156 //===----------------------------------------------------------------------===//
158 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
159 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
160 RegisterClass RC, X86MemOperand x86memop,
163 let isCommutable = 1 in {
164 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
166 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
167 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
168 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
169 Sched<[itins.Sched]>;
171 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
174 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
175 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
176 Sched<[itins.Sched.Folded, ReadAfterLd]>;
179 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
180 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
181 string asm, string SSEVer, string FPSizeStr,
182 Operand memopr, ComplexPattern mem_cpat,
185 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
187 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
188 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
189 [(set RC:$dst, (!cast<Intrinsic>(
190 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
191 RC:$src1, RC:$src2))], itins.rr>,
192 Sched<[itins.Sched]>;
193 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
195 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
196 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
197 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
198 SSEVer, "_", OpcodeStr, FPSizeStr))
199 RC:$src1, mem_cpat:$src2))], itins.rm>,
200 Sched<[itins.Sched.Folded, ReadAfterLd]>;
203 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
204 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
205 RegisterClass RC, ValueType vt,
206 X86MemOperand x86memop, PatFrag mem_frag,
207 Domain d, OpndItins itins, bit Is2Addr = 1> {
208 let isCommutable = 1 in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
214 Sched<[itins.Sched]>;
216 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
218 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
219 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
220 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
222 Sched<[itins.Sched.Folded, ReadAfterLd]>;
225 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
226 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
227 string OpcodeStr, X86MemOperand x86memop,
228 list<dag> pat_rr, list<dag> pat_rm,
230 let isCommutable = 1, hasSideEffects = 0 in
231 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
233 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
234 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
235 pat_rr, NoItinerary, d>,
236 Sched<[WriteVecLogic]>;
237 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
239 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
241 pat_rm, NoItinerary, d>,
242 Sched<[WriteVecLogicLd, ReadAfterLd]>;
245 //===----------------------------------------------------------------------===//
246 // Non-instruction patterns
247 //===----------------------------------------------------------------------===//
249 // A vector extract of the first f32/f64 position is a subregister copy
250 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
251 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
252 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
253 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
255 // A 128-bit subvector extract from the first 256-bit vector position
256 // is a subregister copy that needs no instruction.
257 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
258 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
259 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
260 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
262 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
263 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
264 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
265 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
267 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
268 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
269 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
270 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
272 // A 128-bit subvector insert to the first 256-bit vector position
273 // is a subregister copy that needs no instruction.
274 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
275 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
276 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
278 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
280 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
282 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
283 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
284 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
285 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
286 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
289 // Implicitly promote a 32-bit scalar to a vector.
290 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
291 (COPY_TO_REGCLASS FR32:$src, VR128)>;
292 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
293 (COPY_TO_REGCLASS FR32:$src, VR128)>;
294 // Implicitly promote a 64-bit scalar to a vector.
295 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
296 (COPY_TO_REGCLASS FR64:$src, VR128)>;
297 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
298 (COPY_TO_REGCLASS FR64:$src, VR128)>;
300 // Bitcasts between 128-bit vector types. Return the original type since
301 // no instruction is needed for the conversion
302 let Predicates = [HasSSE2] in {
303 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
304 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
305 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
306 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
307 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
308 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
309 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
310 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
311 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
312 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
313 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
314 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
315 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
316 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
317 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
318 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
319 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
320 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
321 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
322 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
323 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
324 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
325 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
326 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
327 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
328 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
329 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
330 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
331 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
332 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
335 // Bitcasts between 256-bit vector types. Return the original type since
336 // no instruction is needed for the conversion
337 let Predicates = [HasAVX] in {
338 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
339 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
340 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
341 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
342 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
343 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
344 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
345 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
346 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
347 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
348 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
349 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
350 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
351 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
352 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
353 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
354 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
355 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
356 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
357 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
358 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
359 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
360 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
361 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
362 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
363 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
364 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
365 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
366 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
367 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
370 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
371 // This is expanded by ExpandPostRAPseudos.
372 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
373 isPseudo = 1, SchedRW = [WriteZero] in {
374 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
375 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
376 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
377 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
380 //===----------------------------------------------------------------------===//
381 // AVX & SSE - Zero/One Vectors
382 //===----------------------------------------------------------------------===//
384 // Alias instruction that maps zero vector to pxor / xorp* for sse.
385 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
386 // swizzled by ExecutionDepsFix to pxor.
387 // We set canFoldAsLoad because this can be converted to a constant-pool
388 // load of an all-zeros value if folding it would be beneficial.
389 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
390 isPseudo = 1, SchedRW = [WriteZero] in {
391 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
392 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
395 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
396 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
397 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
398 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
399 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
402 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
403 // and doesn't need it because on sandy bridge the register is set to zero
404 // at the rename stage without using any execution unit, so SET0PSY
405 // and SET0PDY can be used for vector int instructions without penalty
406 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
407 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
408 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
409 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
412 let Predicates = [HasAVX] in
413 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
415 let Predicates = [HasAVX2] in {
416 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
417 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
418 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
419 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
422 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
423 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
424 let Predicates = [HasAVX1Only] in {
425 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
426 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
427 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
429 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
430 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
431 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
433 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
434 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
435 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
437 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
438 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
439 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
445 isPseudo = 1, SchedRW = [WriteZero] in {
446 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
447 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
448 let Predicates = [HasAVX2] in
449 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
450 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
454 //===----------------------------------------------------------------------===//
455 // SSE 1 & 2 - Move FP Scalar Instructions
457 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
458 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
459 // is used instead. Register-to-register movss/movsd is not modeled as an
460 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
461 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
462 //===----------------------------------------------------------------------===//
464 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
465 X86MemOperand x86memop, string base_opc,
467 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
468 (ins VR128:$src1, RC:$src2),
469 !strconcat(base_opc, asm_opr),
470 [(set VR128:$dst, (vt (OpNode VR128:$src1,
471 (scalar_to_vector RC:$src2))))],
472 IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
474 // For the disassembler
475 let isCodeGenOnly = 1, hasSideEffects = 0 in
476 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
477 (ins VR128:$src1, RC:$src2),
478 !strconcat(base_opc, asm_opr),
479 [], IIC_SSE_MOV_S_RR>, Sched<[WriteMove]>;
482 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
483 X86MemOperand x86memop, string OpcodeStr> {
485 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
486 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
489 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
490 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
491 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
492 VEX, VEX_LIG, Sched<[WriteStore]>;
494 let Constraints = "$src1 = $dst" in {
495 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
496 "\t{$src2, $dst|$dst, $src2}">;
499 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
500 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
501 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
505 // Loading from memory automatically zeroing upper bits.
506 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
507 PatFrag mem_pat, string OpcodeStr> {
508 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
510 [(set RC:$dst, (mem_pat addr:$src))],
511 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
512 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
513 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
514 [(set RC:$dst, (mem_pat addr:$src))],
515 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
518 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
519 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
521 let canFoldAsLoad = 1, isReMaterializable = 1 in {
522 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
524 let AddedComplexity = 20 in
525 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
529 let Predicates = [HasAVX] in {
530 let AddedComplexity = 15 in {
531 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
532 // MOVS{S,D} to the lower bits.
533 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
534 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
535 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
536 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
537 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
538 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
539 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
540 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
542 // Move low f32 and clear high bits.
543 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
544 (SUBREG_TO_REG (i32 0),
545 (VMOVSSrr (v4f32 (V_SET0)),
546 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
547 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
548 (SUBREG_TO_REG (i32 0),
549 (VMOVSSrr (v4i32 (V_SET0)),
550 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
553 let AddedComplexity = 20 in {
554 // MOVSSrm zeros the high parts of the register; represent this
555 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
556 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
557 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
558 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
559 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
560 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
561 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
563 // MOVSDrm zeros the high parts of the register; represent this
564 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
565 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
566 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
567 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
568 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
569 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
570 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
571 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
572 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
573 def : Pat<(v2f64 (X86vzload addr:$src)),
574 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
576 // Represent the same patterns above but in the form they appear for
578 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
579 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
580 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
581 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
582 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
583 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
584 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
585 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
586 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
588 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
589 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
590 (SUBREG_TO_REG (i32 0),
591 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
593 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
594 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
595 (SUBREG_TO_REG (i64 0),
596 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
598 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
599 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
600 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
602 // Move low f64 and clear high bits.
603 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
604 (SUBREG_TO_REG (i32 0),
605 (VMOVSDrr (v2f64 (V_SET0)),
606 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
608 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
609 (SUBREG_TO_REG (i32 0),
610 (VMOVSDrr (v2i64 (V_SET0)),
611 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
613 // Extract and store.
614 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
616 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
617 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
619 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
621 // Shuffle with VMOVSS
622 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
623 (VMOVSSrr (v4i32 VR128:$src1),
624 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
625 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
626 (VMOVSSrr (v4f32 VR128:$src1),
627 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
630 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
631 (SUBREG_TO_REG (i32 0),
632 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
633 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
635 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
636 (SUBREG_TO_REG (i32 0),
637 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
638 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
641 // Shuffle with VMOVSD
642 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
643 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
644 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
645 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
646 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
647 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
648 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
649 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
652 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
653 (SUBREG_TO_REG (i32 0),
654 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
655 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
657 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
658 (SUBREG_TO_REG (i32 0),
659 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
660 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
664 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
665 // is during lowering, where it's not possible to recognize the fold cause
666 // it has two uses through a bitcast. One use disappears at isel time and the
667 // fold opportunity reappears.
668 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
669 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
670 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
671 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
672 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
673 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
674 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
675 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
678 let Predicates = [UseSSE1] in {
679 let AddedComplexity = 15 in {
680 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
681 // MOVSS to the lower bits.
682 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
683 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
684 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
685 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
686 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
687 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
690 let AddedComplexity = 20 in {
691 // MOVSSrm already zeros the high parts of the register.
692 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
693 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
694 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
695 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
696 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
697 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
700 // Extract and store.
701 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
703 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
705 // Shuffle with MOVSS
706 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
707 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
708 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
709 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
712 let Predicates = [UseSSE2] in {
713 let AddedComplexity = 15 in {
714 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
715 // MOVSD to the lower bits.
716 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
717 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
720 let AddedComplexity = 20 in {
721 // MOVSDrm already zeros the high parts of the register.
722 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
723 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
724 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
725 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
726 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
727 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
728 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
729 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
730 def : Pat<(v2f64 (X86vzload addr:$src)),
731 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
734 // Extract and store.
735 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
737 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
739 // Shuffle with MOVSD
740 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
741 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
742 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
743 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
744 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
745 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
746 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
747 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
749 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
750 // is during lowering, where it's not possible to recognize the fold cause
751 // it has two uses through a bitcast. One use disappears at isel time and the
752 // fold opportunity reappears.
753 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
756 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
760 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 //===----------------------------------------------------------------------===//
764 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
765 //===----------------------------------------------------------------------===//
767 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
768 X86MemOperand x86memop, PatFrag ld_frag,
769 string asm, Domain d,
771 bit IsReMaterializable = 1> {
772 let neverHasSideEffects = 1 in
773 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
774 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
776 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
777 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
778 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
779 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
783 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
784 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
786 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
787 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
789 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
790 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
792 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
793 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
796 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
797 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
799 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
800 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
801 TB, OpSize, VEX, VEX_L;
802 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
803 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
805 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
806 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
807 TB, OpSize, VEX, VEX_L;
808 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
809 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
811 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
812 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
814 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
815 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
817 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
818 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
821 let SchedRW = [WriteStore] in {
822 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
823 "movaps\t{$src, $dst|$dst, $src}",
824 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
825 IIC_SSE_MOVA_P_MR>, VEX;
826 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
827 "movapd\t{$src, $dst|$dst, $src}",
828 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
829 IIC_SSE_MOVA_P_MR>, VEX;
830 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
831 "movups\t{$src, $dst|$dst, $src}",
832 [(store (v4f32 VR128:$src), addr:$dst)],
833 IIC_SSE_MOVU_P_MR>, VEX;
834 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
835 "movupd\t{$src, $dst|$dst, $src}",
836 [(store (v2f64 VR128:$src), addr:$dst)],
837 IIC_SSE_MOVU_P_MR>, VEX;
838 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
839 "movaps\t{$src, $dst|$dst, $src}",
840 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
841 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
842 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
843 "movapd\t{$src, $dst|$dst, $src}",
844 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
845 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
846 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
847 "movups\t{$src, $dst|$dst, $src}",
848 [(store (v8f32 VR256:$src), addr:$dst)],
849 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
850 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
851 "movupd\t{$src, $dst|$dst, $src}",
852 [(store (v4f64 VR256:$src), addr:$dst)],
853 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
857 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
858 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
860 "movaps\t{$src, $dst|$dst, $src}", [],
861 IIC_SSE_MOVA_P_RR>, VEX;
862 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
864 "movapd\t{$src, $dst|$dst, $src}", [],
865 IIC_SSE_MOVA_P_RR>, VEX;
866 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
868 "movups\t{$src, $dst|$dst, $src}", [],
869 IIC_SSE_MOVU_P_RR>, VEX;
870 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
872 "movupd\t{$src, $dst|$dst, $src}", [],
873 IIC_SSE_MOVU_P_RR>, VEX;
874 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
876 "movaps\t{$src, $dst|$dst, $src}", [],
877 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
878 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
880 "movapd\t{$src, $dst|$dst, $src}", [],
881 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
882 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
884 "movups\t{$src, $dst|$dst, $src}", [],
885 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
886 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
888 "movupd\t{$src, $dst|$dst, $src}", [],
889 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
892 let Predicates = [HasAVX] in {
893 def : Pat<(v8i32 (X86vzmovl
894 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
895 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
896 def : Pat<(v4i64 (X86vzmovl
897 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
898 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
899 def : Pat<(v8f32 (X86vzmovl
900 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
901 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
902 def : Pat<(v4f64 (X86vzmovl
903 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
904 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
908 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
909 (VMOVUPSYmr addr:$dst, VR256:$src)>;
910 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
911 (VMOVUPDYmr addr:$dst, VR256:$src)>;
913 let SchedRW = [WriteStore] in {
914 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
915 "movaps\t{$src, $dst|$dst, $src}",
916 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
918 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
919 "movapd\t{$src, $dst|$dst, $src}",
920 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
922 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
923 "movups\t{$src, $dst|$dst, $src}",
924 [(store (v4f32 VR128:$src), addr:$dst)],
926 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
927 "movupd\t{$src, $dst|$dst, $src}",
928 [(store (v2f64 VR128:$src), addr:$dst)],
933 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
934 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
935 "movaps\t{$src, $dst|$dst, $src}", [],
937 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
938 "movapd\t{$src, $dst|$dst, $src}", [],
940 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
941 "movups\t{$src, $dst|$dst, $src}", [],
943 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
944 "movupd\t{$src, $dst|$dst, $src}", [],
948 let Predicates = [HasAVX] in {
949 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
950 (VMOVUPSmr addr:$dst, VR128:$src)>;
951 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
952 (VMOVUPDmr addr:$dst, VR128:$src)>;
955 let Predicates = [UseSSE1] in
956 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
957 (MOVUPSmr addr:$dst, VR128:$src)>;
958 let Predicates = [UseSSE2] in
959 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
960 (MOVUPDmr addr:$dst, VR128:$src)>;
962 // Use vmovaps/vmovups for AVX integer load/store.
963 let Predicates = [HasAVX] in {
964 // 128-bit load/store
965 def : Pat<(alignedloadv2i64 addr:$src),
966 (VMOVAPSrm addr:$src)>;
967 def : Pat<(loadv2i64 addr:$src),
968 (VMOVUPSrm addr:$src)>;
970 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
971 (VMOVAPSmr addr:$dst, VR128:$src)>;
972 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
973 (VMOVAPSmr addr:$dst, VR128:$src)>;
974 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
975 (VMOVAPSmr addr:$dst, VR128:$src)>;
976 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
977 (VMOVAPSmr addr:$dst, VR128:$src)>;
978 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
979 (VMOVUPSmr addr:$dst, VR128:$src)>;
980 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
981 (VMOVUPSmr addr:$dst, VR128:$src)>;
982 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
983 (VMOVUPSmr addr:$dst, VR128:$src)>;
984 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
985 (VMOVUPSmr addr:$dst, VR128:$src)>;
987 // 256-bit load/store
988 def : Pat<(alignedloadv4i64 addr:$src),
989 (VMOVAPSYrm addr:$src)>;
990 def : Pat<(loadv4i64 addr:$src),
991 (VMOVUPSYrm addr:$src)>;
992 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
993 (VMOVAPSYmr addr:$dst, VR256:$src)>;
994 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
995 (VMOVAPSYmr addr:$dst, VR256:$src)>;
996 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
997 (VMOVAPSYmr addr:$dst, VR256:$src)>;
998 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
999 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1000 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1001 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1002 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1003 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1004 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1005 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1006 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1007 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1009 // Special patterns for storing subvector extracts of lower 128-bits
1010 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1011 def : Pat<(alignedstore (v2f64 (extract_subvector
1012 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1013 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1014 def : Pat<(alignedstore (v4f32 (extract_subvector
1015 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1016 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1017 def : Pat<(alignedstore (v2i64 (extract_subvector
1018 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1019 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1020 def : Pat<(alignedstore (v4i32 (extract_subvector
1021 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1022 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1023 def : Pat<(alignedstore (v8i16 (extract_subvector
1024 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1025 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1026 def : Pat<(alignedstore (v16i8 (extract_subvector
1027 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1028 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1030 def : Pat<(store (v2f64 (extract_subvector
1031 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1032 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1033 def : Pat<(store (v4f32 (extract_subvector
1034 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1035 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1036 def : Pat<(store (v2i64 (extract_subvector
1037 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1038 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1039 def : Pat<(store (v4i32 (extract_subvector
1040 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1041 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1042 def : Pat<(store (v8i16 (extract_subvector
1043 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1044 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1045 def : Pat<(store (v16i8 (extract_subvector
1046 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1047 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1050 // Use movaps / movups for SSE integer load / store (one byte shorter).
1051 // The instructions selected below are then converted to MOVDQA/MOVDQU
1052 // during the SSE domain pass.
1053 let Predicates = [UseSSE1] in {
1054 def : Pat<(alignedloadv2i64 addr:$src),
1055 (MOVAPSrm addr:$src)>;
1056 def : Pat<(loadv2i64 addr:$src),
1057 (MOVUPSrm addr:$src)>;
1059 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1060 (MOVAPSmr addr:$dst, VR128:$src)>;
1061 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1062 (MOVAPSmr addr:$dst, VR128:$src)>;
1063 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1064 (MOVAPSmr addr:$dst, VR128:$src)>;
1065 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1066 (MOVAPSmr addr:$dst, VR128:$src)>;
1067 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1068 (MOVUPSmr addr:$dst, VR128:$src)>;
1069 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1070 (MOVUPSmr addr:$dst, VR128:$src)>;
1071 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1072 (MOVUPSmr addr:$dst, VR128:$src)>;
1073 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1074 (MOVUPSmr addr:$dst, VR128:$src)>;
1077 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1078 // bits are disregarded. FIXME: Set encoding to pseudo!
1079 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
1080 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1081 "movaps\t{$src, $dst|$dst, $src}", [],
1082 IIC_SSE_MOVA_P_RR>, VEX;
1083 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1084 "movapd\t{$src, $dst|$dst, $src}", [],
1085 IIC_SSE_MOVA_P_RR>, VEX;
1086 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1087 "movaps\t{$src, $dst|$dst, $src}", [],
1089 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1090 "movapd\t{$src, $dst|$dst, $src}", [],
1094 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1095 // bits are disregarded. FIXME: Set encoding to pseudo!
1096 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1097 let isCodeGenOnly = 1 in {
1098 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1099 "movaps\t{$src, $dst|$dst, $src}",
1100 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1101 IIC_SSE_MOVA_P_RM>, VEX;
1102 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1103 "movapd\t{$src, $dst|$dst, $src}",
1104 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1105 IIC_SSE_MOVA_P_RM>, VEX;
1107 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1108 "movaps\t{$src, $dst|$dst, $src}",
1109 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1111 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1112 "movapd\t{$src, $dst|$dst, $src}",
1113 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1117 //===----------------------------------------------------------------------===//
1118 // SSE 1 & 2 - Move Low packed FP Instructions
1119 //===----------------------------------------------------------------------===//
1121 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1122 string base_opc, string asm_opr,
1123 InstrItinClass itin> {
1124 def PSrm : PI<opc, MRMSrcMem,
1125 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1126 !strconcat(base_opc, "s", asm_opr),
1128 (psnode VR128:$src1,
1129 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1130 itin, SSEPackedSingle>, TB,
1131 Sched<[WriteShuffleLd, ReadAfterLd]>;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize,
1139 Sched<[WriteShuffleLd, ReadAfterLd]>;
1143 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1144 string base_opc, InstrItinClass itin> {
1145 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1146 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1149 let Constraints = "$src1 = $dst" in
1150 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1151 "\t{$src2, $dst|$dst, $src2}",
1155 let AddedComplexity = 20 in {
1156 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1160 let SchedRW = [WriteStore] in {
1161 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1162 "movlps\t{$src, $dst|$dst, $src}",
1163 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1164 (iPTR 0))), addr:$dst)],
1165 IIC_SSE_MOV_LH>, VEX;
1166 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1167 "movlpd\t{$src, $dst|$dst, $src}",
1168 [(store (f64 (vector_extract (v2f64 VR128:$src),
1169 (iPTR 0))), addr:$dst)],
1170 IIC_SSE_MOV_LH>, VEX;
1171 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1172 "movlps\t{$src, $dst|$dst, $src}",
1173 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1174 (iPTR 0))), addr:$dst)],
1176 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1177 "movlpd\t{$src, $dst|$dst, $src}",
1178 [(store (f64 (vector_extract (v2f64 VR128:$src),
1179 (iPTR 0))), addr:$dst)],
1183 let Predicates = [HasAVX] in {
1184 // Shuffle with VMOVLPS
1185 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1186 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1188 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1190 // Shuffle with VMOVLPD
1191 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1192 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1193 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1194 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1197 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1199 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1200 def : Pat<(store (v4i32 (X86Movlps
1201 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1202 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1203 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1205 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1206 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1208 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1211 let Predicates = [UseSSE1] in {
1212 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1213 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1214 (iPTR 0))), addr:$src1),
1215 (MOVLPSmr addr:$src1, VR128:$src2)>;
1217 // Shuffle with MOVLPS
1218 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1219 (MOVLPSrm VR128:$src1, addr:$src2)>;
1220 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1221 (MOVLPSrm VR128:$src1, addr:$src2)>;
1222 def : Pat<(X86Movlps VR128:$src1,
1223 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1224 (MOVLPSrm VR128:$src1, addr:$src2)>;
1227 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1229 (MOVLPSmr addr:$src1, VR128:$src2)>;
1230 def : Pat<(store (v4i32 (X86Movlps
1231 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1233 (MOVLPSmr addr:$src1, VR128:$src2)>;
1236 let Predicates = [UseSSE2] in {
1237 // Shuffle with MOVLPD
1238 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1239 (MOVLPDrm VR128:$src1, addr:$src2)>;
1240 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1241 (MOVLPDrm VR128:$src1, addr:$src2)>;
1244 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1246 (MOVLPDmr addr:$src1, VR128:$src2)>;
1247 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1249 (MOVLPDmr addr:$src1, VR128:$src2)>;
1252 //===----------------------------------------------------------------------===//
1253 // SSE 1 & 2 - Move Hi packed FP Instructions
1254 //===----------------------------------------------------------------------===//
1256 let AddedComplexity = 20 in {
1257 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1261 let SchedRW = [WriteStore] in {
1262 // v2f64 extract element 1 is always custom lowered to unpack high to low
1263 // and extract element 0 so the non-store version isn't too horrible.
1264 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1265 "movhps\t{$src, $dst|$dst, $src}",
1266 [(store (f64 (vector_extract
1267 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1268 (bc_v2f64 (v4f32 VR128:$src))),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhpd\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1274 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1275 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1276 "movhps\t{$src, $dst|$dst, $src}",
1277 [(store (f64 (vector_extract
1278 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1279 (bc_v2f64 (v4f32 VR128:$src))),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1281 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1282 "movhpd\t{$src, $dst|$dst, $src}",
1283 [(store (f64 (vector_extract
1284 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1285 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1288 let Predicates = [HasAVX] in {
1290 def : Pat<(X86Movlhps VR128:$src1,
1291 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1292 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1293 def : Pat<(X86Movlhps VR128:$src1,
1294 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1295 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1297 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1298 // is during lowering, where it's not possible to recognize the load fold
1299 // cause it has two uses through a bitcast. One use disappears at isel time
1300 // and the fold opportunity reappears.
1301 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1302 (scalar_to_vector (loadf64 addr:$src2)))),
1303 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1306 let Predicates = [UseSSE1] in {
1308 def : Pat<(X86Movlhps VR128:$src1,
1309 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1310 (MOVHPSrm VR128:$src1, addr:$src2)>;
1311 def : Pat<(X86Movlhps VR128:$src1,
1312 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1313 (MOVHPSrm VR128:$src1, addr:$src2)>;
1316 let Predicates = [UseSSE2] in {
1317 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1318 // is during lowering, where it's not possible to recognize the load fold
1319 // cause it has two uses through a bitcast. One use disappears at isel time
1320 // and the fold opportunity reappears.
1321 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1322 (scalar_to_vector (loadf64 addr:$src2)))),
1323 (MOVHPDrm VR128:$src1, addr:$src2)>;
1326 //===----------------------------------------------------------------------===//
1327 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1328 //===----------------------------------------------------------------------===//
1330 let AddedComplexity = 20 in {
1331 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1332 (ins VR128:$src1, VR128:$src2),
1333 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1335 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1337 VEX_4V, Sched<[WriteShuffle]>;
1338 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1339 (ins VR128:$src1, VR128:$src2),
1340 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1342 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1344 VEX_4V, Sched<[WriteShuffle]>;
1346 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1347 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movlhps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1352 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1353 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1354 (ins VR128:$src1, VR128:$src2),
1355 "movhlps\t{$src2, $dst|$dst, $src2}",
1357 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1358 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
1361 let Predicates = [HasAVX] in {
1363 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1364 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1365 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1366 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1369 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1370 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1373 let Predicates = [UseSSE1] in {
1375 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1376 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1377 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1378 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1381 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1382 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1385 //===----------------------------------------------------------------------===//
1386 // SSE 1 & 2 - Conversion Instructions
1387 //===----------------------------------------------------------------------===//
1389 def SSE_CVT_PD : OpndItins<
1390 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1393 let Sched = WriteCvtI2F in
1394 def SSE_CVT_PS : OpndItins<
1395 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1398 let Sched = WriteCvtI2F in
1399 def SSE_CVT_Scalar : OpndItins<
1400 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1403 let Sched = WriteCvtF2I in
1404 def SSE_CVT_SS2SI_32 : OpndItins<
1405 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1408 let Sched = WriteCvtF2I in
1409 def SSE_CVT_SS2SI_64 : OpndItins<
1410 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1413 let Sched = WriteCvtF2I in
1414 def SSE_CVT_SD2SI : OpndItins<
1415 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1418 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, OpndItins itins> {
1421 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1423 itins.rr>, Sched<[itins.Sched]>;
1424 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1426 itins.rm>, Sched<[itins.Sched.Folded]>;
1429 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm, Domain d,
1432 let neverHasSideEffects = 1 in {
1433 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1434 [], itins.rr, d>, Sched<[itins.Sched]>;
1436 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1437 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1441 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1442 X86MemOperand x86memop, string asm> {
1443 let neverHasSideEffects = 1 in {
1444 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1445 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1446 Sched<[WriteCvtI2F]>;
1448 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1449 (ins DstRC:$src1, x86memop:$src),
1450 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1451 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1452 } // neverHasSideEffects = 1
1455 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1456 "cvttss2si\t{$src, $dst|$dst, $src}",
1459 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1460 "cvttss2si\t{$src, $dst|$dst, $src}",
1462 XS, VEX, VEX_W, VEX_LIG;
1463 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1464 "cvttsd2si\t{$src, $dst|$dst, $src}",
1467 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1468 "cvttsd2si\t{$src, $dst|$dst, $src}",
1470 XD, VEX, VEX_W, VEX_LIG;
1472 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1473 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1474 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1475 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1476 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1477 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1478 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1479 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1480 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1481 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1482 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1483 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1484 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1485 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1486 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1487 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1489 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1490 // register, but the same isn't true when only using memory operands,
1491 // provide other assembly "l" and "q" forms to address this explicitly
1492 // where appropriate to do so.
1493 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1494 XS, VEX_4V, VEX_LIG;
1495 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1496 XS, VEX_4V, VEX_W, VEX_LIG;
1497 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1498 XD, VEX_4V, VEX_LIG;
1499 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1500 XD, VEX_4V, VEX_W, VEX_LIG;
1502 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1503 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1504 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1505 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src)>;
1507 let Predicates = [HasAVX] in {
1508 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1509 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1510 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1511 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1512 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1513 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1514 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1515 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1517 def : Pat<(f32 (sint_to_fp GR32:$src)),
1518 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1519 def : Pat<(f32 (sint_to_fp GR64:$src)),
1520 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1521 def : Pat<(f64 (sint_to_fp GR32:$src)),
1522 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1523 def : Pat<(f64 (sint_to_fp GR64:$src)),
1524 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1527 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1528 "cvttss2si\t{$src, $dst|$dst, $src}",
1529 SSE_CVT_SS2SI_32>, XS;
1530 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1531 "cvttss2si\t{$src, $dst|$dst, $src}",
1532 SSE_CVT_SS2SI_64>, XS, REX_W;
1533 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1534 "cvttsd2si\t{$src, $dst|$dst, $src}",
1536 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1537 "cvttsd2si\t{$src, $dst|$dst, $src}",
1538 SSE_CVT_SD2SI>, XD, REX_W;
1539 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1540 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1541 SSE_CVT_Scalar>, XS;
1542 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1543 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1544 SSE_CVT_Scalar>, XS, REX_W;
1545 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1546 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1547 SSE_CVT_Scalar>, XD;
1548 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1549 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1550 SSE_CVT_Scalar>, XD, REX_W;
1552 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1553 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1554 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1555 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1556 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1557 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1558 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1559 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1560 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1561 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1562 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1563 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1564 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1565 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1566 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1567 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1569 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1570 (CVTSI2SSrm FR64:$dst, i32mem:$src)>;
1571 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1572 (CVTSI2SDrm FR64:$dst, i32mem:$src)>;
1574 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1575 // and/or XMM operand(s).
1577 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1578 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1579 string asm, OpndItins itins> {
1580 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1581 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1582 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1583 Sched<[itins.Sched]>;
1584 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1585 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1586 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1587 Sched<[itins.Sched.Folded]>;
1590 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1591 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1592 PatFrag ld_frag, string asm, OpndItins itins,
1594 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1596 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1597 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1598 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1599 itins.rr>, Sched<[itins.Sched]>;
1600 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1601 (ins DstRC:$src1, x86memop:$src2),
1603 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1604 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1605 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1606 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1609 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1610 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1611 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1612 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1613 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1614 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1616 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1617 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1618 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1619 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1622 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1623 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1624 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1625 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1626 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1627 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1629 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1630 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1631 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1632 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1633 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1634 SSE_CVT_Scalar, 0>, XD,
1637 let Constraints = "$src1 = $dst" in {
1638 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1639 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1640 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1641 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1642 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1643 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1644 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1645 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1646 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1647 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1648 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1649 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1654 // Aliases for intrinsics
1655 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1656 ssmem, sse_load_f32, "cvttss2si",
1657 SSE_CVT_SS2SI_32>, XS, VEX;
1658 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1659 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1660 "cvttss2si", SSE_CVT_SS2SI_64>,
1662 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1663 sdmem, sse_load_f64, "cvttsd2si",
1664 SSE_CVT_SD2SI>, XD, VEX;
1665 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1666 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1667 "cvttsd2si", SSE_CVT_SD2SI>,
1669 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1670 ssmem, sse_load_f32, "cvttss2si",
1671 SSE_CVT_SS2SI_32>, XS;
1672 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1673 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1674 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1675 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1676 sdmem, sse_load_f64, "cvttsd2si",
1678 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1679 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1680 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1682 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1683 ssmem, sse_load_f32, "cvtss2si",
1684 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1685 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1686 ssmem, sse_load_f32, "cvtss2si",
1687 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1689 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1690 ssmem, sse_load_f32, "cvtss2si",
1691 SSE_CVT_SS2SI_32>, XS;
1692 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1693 ssmem, sse_load_f32, "cvtss2si",
1694 SSE_CVT_SS2SI_64>, XS, REX_W;
1696 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1697 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1698 SSEPackedSingle, SSE_CVT_PS>,
1699 TB, VEX, Requires<[HasAVX]>;
1700 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1701 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1702 SSEPackedSingle, SSE_CVT_PS>,
1703 TB, VEX, VEX_L, Requires<[HasAVX]>;
1705 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1706 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1707 SSEPackedSingle, SSE_CVT_PS>,
1708 TB, Requires<[UseSSE2]>;
1710 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1711 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1712 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1713 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1714 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1715 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1716 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1717 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1718 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1719 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1720 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1721 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1722 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1723 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1724 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1725 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1727 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1728 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1729 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1730 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1731 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1732 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1733 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1734 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1735 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1736 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1737 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1738 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1739 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1740 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1741 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1742 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1746 // Convert scalar double to scalar single
1747 let neverHasSideEffects = 1 in {
1748 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1749 (ins FR64:$src1, FR64:$src2),
1750 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1751 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1752 Sched<[WriteCvtF2F]>;
1754 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1755 (ins FR64:$src1, f64mem:$src2),
1756 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1757 [], IIC_SSE_CVT_Scalar_RM>,
1758 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1759 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1762 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1765 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1766 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1767 [(set FR32:$dst, (fround FR64:$src))],
1768 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1769 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1770 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1771 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1772 IIC_SSE_CVT_Scalar_RM>,
1774 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1776 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1777 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1778 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1780 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1781 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[HasAVX]>,
1782 Sched<[WriteCvtF2F]>;
1783 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1784 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1785 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1786 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1787 VR128:$src1, sse_load_f64:$src2))],
1788 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[HasAVX]>,
1789 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1791 let Constraints = "$src1 = $dst" in {
1792 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1793 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1794 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1796 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1797 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1798 Sched<[WriteCvtF2F]>;
1799 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1800 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1801 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1802 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1803 VR128:$src1, sse_load_f64:$src2))],
1804 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1805 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1808 // Convert scalar single to scalar double
1809 // SSE2 instructions with XS prefix
1810 let neverHasSideEffects = 1 in {
1811 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1812 (ins FR32:$src1, FR32:$src2),
1813 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1814 [], IIC_SSE_CVT_Scalar_RR>,
1815 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1816 Sched<[WriteCvtF2F]>;
1818 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1819 (ins FR32:$src1, f32mem:$src2),
1820 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1821 [], IIC_SSE_CVT_Scalar_RM>,
1822 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1823 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1826 def : Pat<(f64 (fextend FR32:$src)),
1827 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[HasAVX]>;
1828 def : Pat<(fextend (loadf32 addr:$src)),
1829 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX]>;
1831 def : Pat<(extloadf32 addr:$src),
1832 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1833 Requires<[HasAVX, OptForSize]>;
1834 def : Pat<(extloadf32 addr:$src),
1835 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1836 Requires<[HasAVX, OptForSpeed]>;
1838 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1839 "cvtss2sd\t{$src, $dst|$dst, $src}",
1840 [(set FR64:$dst, (fextend FR32:$src))],
1841 IIC_SSE_CVT_Scalar_RR>, XS,
1842 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1843 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1844 "cvtss2sd\t{$src, $dst|$dst, $src}",
1845 [(set FR64:$dst, (extloadf32 addr:$src))],
1846 IIC_SSE_CVT_Scalar_RM>, XS,
1847 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1849 // extload f32 -> f64. This matches load+fextend because we have a hack in
1850 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1852 // Since these loads aren't folded into the fextend, we have to match it
1854 def : Pat<(fextend (loadf32 addr:$src)),
1855 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1856 def : Pat<(extloadf32 addr:$src),
1857 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1859 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1860 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1861 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1863 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1864 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[HasAVX]>,
1865 Sched<[WriteCvtF2F]>;
1866 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1867 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1868 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1870 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1871 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[HasAVX]>,
1872 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1873 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1874 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1875 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1876 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1878 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1879 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1880 Sched<[WriteCvtF2F]>;
1881 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1882 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1883 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1885 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1886 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1887 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1890 // Convert packed single/double fp to doubleword
1891 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1892 "cvtps2dq\t{$src, $dst|$dst, $src}",
1893 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1894 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1895 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1896 "cvtps2dq\t{$src, $dst|$dst, $src}",
1898 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1899 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1900 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1901 "cvtps2dq\t{$src, $dst|$dst, $src}",
1903 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1904 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1905 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1906 "cvtps2dq\t{$src, $dst|$dst, $src}",
1908 (int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)))],
1909 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1910 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvtps2dq\t{$src, $dst|$dst, $src}",
1912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1913 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1914 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1915 "cvtps2dq\t{$src, $dst|$dst, $src}",
1917 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1918 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1921 // Convert Packed Double FP to Packed DW Integers
1922 let Predicates = [HasAVX] in {
1923 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1924 // register, but the same isn't true when using memory operands instead.
1925 // Provide other assembly rr and rm forms to address this explicitly.
1926 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1927 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1928 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1929 VEX, Sched<[WriteCvtF2I]>;
1932 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1933 (VCVTPD2DQrr VR128:$dst, VR128:$src)>;
1934 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1935 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
1937 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))]>, VEX,
1938 Sched<[WriteCvtF2ILd]>;
1941 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1942 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1944 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
1945 Sched<[WriteCvtF2I]>;
1946 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1947 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
1949 (int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)))]>,
1950 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1951 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
1952 (VCVTPD2DQYrr VR128:$dst, VR256:$src)>;
1955 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1956 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1958 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
1959 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
1960 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1961 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1962 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1963 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
1965 // Convert with truncation packed single/double fp to doubleword
1966 // SSE2 packed instructions with XS prefix
1967 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvttps2dq\t{$src, $dst|$dst, $src}",
1970 (int_x86_sse2_cvttps2dq VR128:$src))],
1971 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1972 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1973 "cvttps2dq\t{$src, $dst|$dst, $src}",
1974 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1975 (memopv4f32 addr:$src)))],
1976 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1977 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1978 "cvttps2dq\t{$src, $dst|$dst, $src}",
1980 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1981 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1982 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1983 "cvttps2dq\t{$src, $dst|$dst, $src}",
1984 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1985 (memopv8f32 addr:$src)))],
1986 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
1987 Sched<[WriteCvtF2ILd]>;
1989 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1990 "cvttps2dq\t{$src, $dst|$dst, $src}",
1991 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
1992 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1993 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1994 "cvttps2dq\t{$src, $dst|$dst, $src}",
1996 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
1997 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1999 let Predicates = [HasAVX] in {
2000 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2001 (VCVTDQ2PSrr VR128:$src)>;
2002 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2003 (VCVTDQ2PSrm addr:$src)>;
2005 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2006 (VCVTDQ2PSrr VR128:$src)>;
2007 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2008 (VCVTDQ2PSrm addr:$src)>;
2010 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2011 (VCVTTPS2DQrr VR128:$src)>;
2012 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2013 (VCVTTPS2DQrm addr:$src)>;
2015 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2016 (VCVTDQ2PSYrr VR256:$src)>;
2017 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
2018 (VCVTDQ2PSYrm addr:$src)>;
2020 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2021 (VCVTTPS2DQYrr VR256:$src)>;
2022 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
2023 (VCVTTPS2DQYrm addr:$src)>;
2026 let Predicates = [UseSSE2] in {
2027 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2028 (CVTDQ2PSrr VR128:$src)>;
2029 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2030 (CVTDQ2PSrm addr:$src)>;
2032 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2033 (CVTDQ2PSrr VR128:$src)>;
2034 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2035 (CVTDQ2PSrm addr:$src)>;
2037 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2038 (CVTTPS2DQrr VR128:$src)>;
2039 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2040 (CVTTPS2DQrm addr:$src)>;
2043 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttpd2dq VR128:$src))],
2047 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2049 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2050 // register, but the same isn't true when using memory operands instead.
2051 // Provide other assembly rr and rm forms to address this explicitly.
2054 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2055 (VCVTTPD2DQrr VR128:$dst, VR128:$src)>;
2056 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2057 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2058 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2059 (memopv2f64 addr:$src)))],
2060 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2063 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2064 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2066 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2067 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2068 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2069 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2071 (int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)))],
2072 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2073 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2074 (VCVTTPD2DQYrr VR128:$dst, VR256:$src)>;
2076 let Predicates = [HasAVX] in {
2077 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2078 (VCVTTPD2DQYrr VR256:$src)>;
2079 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
2080 (VCVTTPD2DQYrm addr:$src)>;
2081 } // Predicates = [HasAVX]
2083 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2084 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2085 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2086 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2087 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2088 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2089 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2090 (memopv2f64 addr:$src)))],
2092 Sched<[WriteCvtF2ILd]>;
2094 // Convert packed single to packed double
2095 let Predicates = [HasAVX] in {
2096 // SSE2 instructions without OpSize prefix
2097 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2098 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2099 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2100 IIC_SSE_CVT_PD_RR>, TB, VEX, Sched<[WriteCvtF2F]>;
2101 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2102 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2103 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2104 IIC_SSE_CVT_PD_RM>, TB, VEX, Sched<[WriteCvtF2FLd]>;
2105 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2106 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2108 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2109 IIC_SSE_CVT_PD_RR>, TB, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2110 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2111 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2113 (int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)))],
2114 IIC_SSE_CVT_PD_RM>, TB, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2117 let Predicates = [UseSSE2] in {
2118 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2119 "cvtps2pd\t{$src, $dst|$dst, $src}",
2120 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2121 IIC_SSE_CVT_PD_RR>, TB, Sched<[WriteCvtF2F]>;
2122 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2123 "cvtps2pd\t{$src, $dst|$dst, $src}",
2124 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2125 IIC_SSE_CVT_PD_RM>, TB, Sched<[WriteCvtF2FLd]>;
2128 // Convert Packed DW Integers to Packed Double FP
2129 let Predicates = [HasAVX] in {
2130 let neverHasSideEffects = 1, mayLoad = 1 in
2131 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2132 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2133 []>, VEX, Sched<[WriteCvtI2FLd]>;
2134 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2135 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2137 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2138 Sched<[WriteCvtI2F]>;
2139 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2140 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtdq2_pd_256
2143 (bitconvert (memopv2i64 addr:$src))))]>, VEX, VEX_L,
2144 Sched<[WriteCvtI2FLd]>;
2145 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2146 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2148 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2149 Sched<[WriteCvtI2F]>;
2152 let neverHasSideEffects = 1, mayLoad = 1 in
2153 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2154 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2155 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2156 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2157 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2158 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2159 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2161 // AVX 256-bit register conversion intrinsics
2162 let Predicates = [HasAVX] in {
2163 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2164 (VCVTDQ2PDYrr VR128:$src)>;
2165 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2166 (VCVTDQ2PDYrm addr:$src)>;
2167 } // Predicates = [HasAVX]
2169 // Convert packed double to packed single
2170 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2171 // register, but the same isn't true when using memory operands instead.
2172 // Provide other assembly rr and rm forms to address this explicitly.
2173 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2179 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2180 (VCVTPD2PSrr VR128:$dst, VR128:$src)>;
2181 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2182 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2184 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2185 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2188 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2189 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2191 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2192 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2193 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2194 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2196 (int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)))],
2197 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2198 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2199 (VCVTPD2PSYrr VR128:$dst, VR256:$src)>;
2201 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2202 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2203 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2204 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2205 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2206 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2208 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2209 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2212 // AVX 256-bit register conversion intrinsics
2213 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2214 // whenever possible to avoid declaring two versions of each one.
2215 let Predicates = [HasAVX] in {
2216 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2217 (VCVTDQ2PSYrr VR256:$src)>;
2218 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2219 (VCVTDQ2PSYrm addr:$src)>;
2221 // Match fround and fextend for 128/256-bit conversions
2222 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2223 (VCVTPD2PSrr VR128:$src)>;
2224 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2225 (VCVTPD2PSXrm addr:$src)>;
2226 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2227 (VCVTPD2PSYrr VR256:$src)>;
2228 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2229 (VCVTPD2PSYrm addr:$src)>;
2231 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2232 (VCVTPS2PDrr VR128:$src)>;
2233 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2234 (VCVTPS2PDYrr VR128:$src)>;
2235 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2236 (VCVTPS2PDYrm addr:$src)>;
2239 let Predicates = [UseSSE2] in {
2240 // Match fround and fextend for 128 conversions
2241 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2242 (CVTPD2PSrr VR128:$src)>;
2243 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2244 (CVTPD2PSrm addr:$src)>;
2246 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2247 (CVTPS2PDrr VR128:$src)>;
2250 //===----------------------------------------------------------------------===//
2251 // SSE 1 & 2 - Compare Instructions
2252 //===----------------------------------------------------------------------===//
2254 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2255 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2256 Operand CC, SDNode OpNode, ValueType VT,
2257 PatFrag ld_frag, string asm, string asm_alt,
2259 def rr : SIi8<0xC2, MRMSrcReg,
2260 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2261 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2262 itins.rr>, Sched<[itins.Sched]>;
2263 def rm : SIi8<0xC2, MRMSrcMem,
2264 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2265 [(set RC:$dst, (OpNode (VT RC:$src1),
2266 (ld_frag addr:$src2), imm:$cc))],
2268 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2270 // Accept explicit immediate argument form instead of comparison code.
2271 let neverHasSideEffects = 1 in {
2272 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2273 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2274 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2276 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2277 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2278 IIC_SSE_ALU_F32S_RM>,
2279 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2283 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2284 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2285 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2287 XS, VEX_4V, VEX_LIG;
2288 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2289 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2290 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2291 SSE_ALU_F32S>, // same latency as 32 bit compare
2292 XD, VEX_4V, VEX_LIG;
2294 let Constraints = "$src1 = $dst" in {
2295 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2296 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2297 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2299 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2300 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2301 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2302 SSE_ALU_F32S>, // same latency as 32 bit compare
2306 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2307 Intrinsic Int, string asm, OpndItins itins> {
2308 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2309 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2310 [(set VR128:$dst, (Int VR128:$src1,
2311 VR128:$src, imm:$cc))],
2313 Sched<[itins.Sched]>;
2314 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2315 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2316 [(set VR128:$dst, (Int VR128:$src1,
2317 (load addr:$src), imm:$cc))],
2319 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2322 // Aliases to match intrinsics which expect XMM operand(s).
2323 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2324 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2327 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2328 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2329 SSE_ALU_F32S>, // same latency as f32
2331 let Constraints = "$src1 = $dst" in {
2332 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2333 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2335 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2336 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2337 SSE_ALU_F32S>, // same latency as f32
2342 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2343 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2344 ValueType vt, X86MemOperand x86memop,
2345 PatFrag ld_frag, string OpcodeStr> {
2346 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2347 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2348 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2351 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2352 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2353 [(set EFLAGS, (OpNode (vt RC:$src1),
2354 (ld_frag addr:$src2)))],
2356 Sched<[WriteFAddLd, ReadAfterLd]>;
2359 let Defs = [EFLAGS] in {
2360 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2361 "ucomiss">, TB, VEX, VEX_LIG;
2362 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2363 "ucomisd">, TB, OpSize, VEX, VEX_LIG;
2364 let Pattern = []<dag> in {
2365 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2366 "comiss">, TB, VEX, VEX_LIG;
2367 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2368 "comisd">, TB, OpSize, VEX, VEX_LIG;
2371 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2372 load, "ucomiss">, TB, VEX;
2373 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2374 load, "ucomisd">, TB, OpSize, VEX;
2376 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2377 load, "comiss">, TB, VEX;
2378 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2379 load, "comisd">, TB, OpSize, VEX;
2380 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2382 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2383 "ucomisd">, TB, OpSize;
2385 let Pattern = []<dag> in {
2386 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2388 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2389 "comisd">, TB, OpSize;
2392 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2393 load, "ucomiss">, TB;
2394 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2395 load, "ucomisd">, TB, OpSize;
2397 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2399 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2400 "comisd">, TB, OpSize;
2401 } // Defs = [EFLAGS]
2403 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2404 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2405 Operand CC, Intrinsic Int, string asm,
2406 string asm_alt, Domain d> {
2407 def rri : PIi8<0xC2, MRMSrcReg,
2408 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2409 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2410 IIC_SSE_CMPP_RR, d>,
2412 def rmi : PIi8<0xC2, MRMSrcMem,
2413 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2414 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2415 IIC_SSE_CMPP_RM, d>,
2416 Sched<[WriteFAddLd, ReadAfterLd]>;
2418 // Accept explicit immediate argument form instead of comparison code.
2419 let neverHasSideEffects = 1 in {
2420 def rri_alt : PIi8<0xC2, MRMSrcReg,
2421 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2422 asm_alt, [], IIC_SSE_CMPP_RR, d>, Sched<[WriteFAdd]>;
2423 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2424 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2425 asm_alt, [], IIC_SSE_CMPP_RM, d>,
2426 Sched<[WriteFAddLd, ReadAfterLd]>;
2430 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2431 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2432 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2433 SSEPackedSingle>, TB, VEX_4V;
2434 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2435 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2436 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2437 SSEPackedDouble>, TB, OpSize, VEX_4V;
2438 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2439 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2440 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2441 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2442 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2443 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2444 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2445 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2446 let Constraints = "$src1 = $dst" in {
2447 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2448 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2449 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2450 SSEPackedSingle>, TB;
2451 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2452 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2453 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2454 SSEPackedDouble>, TB, OpSize;
2457 let Predicates = [HasAVX] in {
2458 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2459 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2460 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2461 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2462 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2463 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2464 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2465 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2467 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2468 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2469 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2470 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2471 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2472 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2473 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2474 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2477 let Predicates = [UseSSE1] in {
2478 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2479 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2480 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2481 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2484 let Predicates = [UseSSE2] in {
2485 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2486 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2487 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2488 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2491 //===----------------------------------------------------------------------===//
2492 // SSE 1 & 2 - Shuffle Instructions
2493 //===----------------------------------------------------------------------===//
2495 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2496 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2497 ValueType vt, string asm, PatFrag mem_frag,
2498 Domain d, bit IsConvertibleToThreeAddress = 0> {
2499 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2500 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2501 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2502 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2503 Sched<[WriteShuffleLd, ReadAfterLd]>;
2504 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2505 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2506 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2507 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2508 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2509 Sched<[WriteShuffle]>;
2512 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2513 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2514 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2515 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2516 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2517 memopv8f32, SSEPackedSingle>, TB, VEX_4V, VEX_L;
2518 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2519 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2520 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2521 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2522 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2523 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2525 let Constraints = "$src1 = $dst" in {
2526 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2527 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2528 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2530 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2531 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2532 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2536 let Predicates = [HasAVX] in {
2537 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2538 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2539 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2540 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2541 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2543 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2544 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2545 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2546 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2547 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2550 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2551 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2552 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2553 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2554 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2556 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2557 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2558 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2559 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2560 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2563 let Predicates = [UseSSE1] in {
2564 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2565 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2566 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2567 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2568 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2571 let Predicates = [UseSSE2] in {
2572 // Generic SHUFPD patterns
2573 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2574 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2575 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2576 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2577 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2580 //===----------------------------------------------------------------------===//
2581 // SSE 1 & 2 - Unpack Instructions
2582 //===----------------------------------------------------------------------===//
2584 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2585 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2586 PatFrag mem_frag, RegisterClass RC,
2587 X86MemOperand x86memop, string asm,
2589 def rr : PI<opc, MRMSrcReg,
2590 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2592 (vt (OpNode RC:$src1, RC:$src2)))],
2593 IIC_SSE_UNPCK, d>, Sched<[WriteShuffle]>;
2594 def rm : PI<opc, MRMSrcMem,
2595 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2597 (vt (OpNode RC:$src1,
2598 (mem_frag addr:$src2))))],
2600 Sched<[WriteShuffleLd, ReadAfterLd]>;
2603 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2604 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2605 SSEPackedSingle>, TB, VEX_4V;
2606 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2607 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2608 SSEPackedDouble>, TB, OpSize, VEX_4V;
2609 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2610 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2611 SSEPackedSingle>, TB, VEX_4V;
2612 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2613 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2614 SSEPackedDouble>, TB, OpSize, VEX_4V;
2616 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2617 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2618 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2619 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2620 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2621 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2622 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2623 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2624 SSEPackedSingle>, TB, VEX_4V, VEX_L;
2625 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2626 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2627 SSEPackedDouble>, TB, OpSize, VEX_4V, VEX_L;
2629 let Constraints = "$src1 = $dst" in {
2630 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2631 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2632 SSEPackedSingle>, TB;
2633 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2634 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2635 SSEPackedDouble>, TB, OpSize;
2636 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2637 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2638 SSEPackedSingle>, TB;
2639 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2640 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2641 SSEPackedDouble>, TB, OpSize;
2642 } // Constraints = "$src1 = $dst"
2644 let Predicates = [HasAVX1Only] in {
2645 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2646 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2647 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2648 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2649 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
2650 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2651 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2652 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2654 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
2655 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2656 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2657 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2658 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
2659 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2660 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2661 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2664 let Predicates = [HasAVX] in {
2665 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2666 // problem is during lowering, where it's not possible to recognize the load
2667 // fold cause it has two uses through a bitcast. One use disappears at isel
2668 // time and the fold opportunity reappears.
2669 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2670 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2673 let Predicates = [UseSSE2] in {
2674 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2675 // problem is during lowering, where it's not possible to recognize the load
2676 // fold cause it has two uses through a bitcast. One use disappears at isel
2677 // time and the fold opportunity reappears.
2678 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2679 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2682 //===----------------------------------------------------------------------===//
2683 // SSE 1 & 2 - Extract Floating-Point Sign mask
2684 //===----------------------------------------------------------------------===//
2686 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2687 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2689 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2690 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2691 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2692 Sched<[WriteVecLogic]>;
2693 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2694 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2695 IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;
2698 let Predicates = [HasAVX] in {
2699 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2700 "movmskps", SSEPackedSingle>, TB, VEX;
2701 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2702 "movmskpd", SSEPackedDouble>, TB,
2704 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2705 "movmskps", SSEPackedSingle>, TB,
2707 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2708 "movmskpd", SSEPackedDouble>, TB,
2711 def : Pat<(i32 (X86fgetsign FR32:$src)),
2712 (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2713 def : Pat<(i64 (X86fgetsign FR32:$src)),
2714 (VMOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>;
2715 def : Pat<(i32 (X86fgetsign FR64:$src)),
2716 (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2717 def : Pat<(i64 (X86fgetsign FR64:$src)),
2718 (VMOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>;
2721 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2722 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2723 SSEPackedSingle>, TB, VEX, Sched<[WriteVecLogic]>;
2724 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2725 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2726 SSEPackedDouble>, TB,
2727 OpSize, VEX, Sched<[WriteVecLogic]>;
2728 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2729 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2730 SSEPackedSingle>, TB, VEX, VEX_L, Sched<[WriteVecLogic]>;
2731 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2732 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2733 SSEPackedDouble>, TB,
2734 OpSize, VEX, VEX_L, Sched<[WriteVecLogic]>;
2737 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2738 SSEPackedSingle>, TB;
2739 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2740 SSEPackedDouble>, TB, OpSize;
2742 def : Pat<(i32 (X86fgetsign FR32:$src)),
2743 (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2744 Requires<[UseSSE1]>;
2745 def : Pat<(i64 (X86fgetsign FR32:$src)),
2746 (MOVMSKPSrr64 (COPY_TO_REGCLASS FR32:$src, VR128))>,
2747 Requires<[UseSSE1]>;
2748 def : Pat<(i32 (X86fgetsign FR64:$src)),
2749 (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2750 Requires<[UseSSE2]>;
2751 def : Pat<(i64 (X86fgetsign FR64:$src)),
2752 (MOVMSKPDrr64 (COPY_TO_REGCLASS FR64:$src, VR128))>,
2753 Requires<[UseSSE2]>;
2755 //===---------------------------------------------------------------------===//
2756 // SSE2 - Packed Integer Logical Instructions
2757 //===---------------------------------------------------------------------===//
2759 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2761 /// PDI_binop_rm - Simple SSE2 binary operator.
2762 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2763 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2764 X86MemOperand x86memop, OpndItins itins,
2765 bit IsCommutable, bit Is2Addr> {
2766 let isCommutable = IsCommutable in
2767 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2768 (ins RC:$src1, RC:$src2),
2770 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2771 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2772 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2773 Sched<[itins.Sched]>;
2774 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2775 (ins RC:$src1, x86memop:$src2),
2777 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2778 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2779 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2780 (bitconvert (memop_frag addr:$src2)))))],
2782 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2784 } // ExeDomain = SSEPackedInt
2786 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2787 ValueType OpVT128, ValueType OpVT256,
2788 OpndItins itins, bit IsCommutable = 0> {
2789 let Predicates = [HasAVX] in
2790 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2791 VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2793 let Constraints = "$src1 = $dst" in
2794 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2795 memopv2i64, i128mem, itins, IsCommutable, 1>;
2797 let Predicates = [HasAVX2] in
2798 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2799 OpVT256, VR256, memopv4i64, i256mem, itins,
2800 IsCommutable, 0>, VEX_4V, VEX_L;
2803 // These are ordered here for pattern ordering requirements with the fp versions
2805 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2806 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2807 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64, SSE_BIT_ITINS_P, 1>;
2808 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2809 SSE_BIT_ITINS_P, 0>;
2811 //===----------------------------------------------------------------------===//
2812 // SSE 1 & 2 - Logical Instructions
2813 //===----------------------------------------------------------------------===//
2815 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2817 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2818 SDNode OpNode, OpndItins itins> {
2819 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2820 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2823 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2824 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2827 let Constraints = "$src1 = $dst" in {
2828 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2829 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2832 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2833 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2838 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2839 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2841 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2843 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2846 let isCommutable = 0 in
2847 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2850 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2852 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2854 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2855 !strconcat(OpcodeStr, "ps"), f256mem,
2856 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2857 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2858 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V, VEX_L;
2860 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2861 !strconcat(OpcodeStr, "pd"), f256mem,
2862 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2863 (bc_v4i64 (v4f64 VR256:$src2))))],
2864 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2865 (memopv4i64 addr:$src2)))], 0>,
2866 TB, OpSize, VEX_4V, VEX_L;
2868 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2869 // are all promoted to v2i64, and the patterns are covered by the int
2870 // version. This is needed in SSE only, because v2i64 isn't supported on
2871 // SSE1, but only on SSE2.
2872 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2873 !strconcat(OpcodeStr, "ps"), f128mem, [],
2874 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2875 (memopv2i64 addr:$src2)))], 0>, TB, VEX_4V;
2877 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2878 !strconcat(OpcodeStr, "pd"), f128mem,
2879 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2880 (bc_v2i64 (v2f64 VR128:$src2))))],
2881 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2882 (memopv2i64 addr:$src2)))], 0>,
2885 let Constraints = "$src1 = $dst" in {
2886 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2887 !strconcat(OpcodeStr, "ps"), f128mem,
2888 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2889 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2890 (memopv2i64 addr:$src2)))]>, TB;
2892 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2893 !strconcat(OpcodeStr, "pd"), f128mem,
2894 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2895 (bc_v2i64 (v2f64 VR128:$src2))))],
2896 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2897 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2901 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2902 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2903 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2904 let isCommutable = 0 in
2905 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2907 //===----------------------------------------------------------------------===//
2908 // SSE 1 & 2 - Arithmetic Instructions
2909 //===----------------------------------------------------------------------===//
2911 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2914 /// In addition, we also have a special variant of the scalar form here to
2915 /// represent the associated intrinsic operation. This form is unlike the
2916 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2917 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2919 /// These three forms can each be reg+reg or reg+mem.
2922 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2924 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2927 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2928 OpNode, FR32, f32mem,
2929 itins.s, Is2Addr>, XS;
2930 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2931 OpNode, FR64, f64mem,
2932 itins.d, Is2Addr>, XD;
2935 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
2936 SDNode OpNode, SizeItins itins> {
2937 let Predicates = [HasAVX] in {
2938 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2939 VR128, v4f32, f128mem, memopv4f32,
2940 SSEPackedSingle, itins.s, 0>, TB, VEX_4V;
2941 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2942 VR128, v2f64, f128mem, memopv2f64,
2943 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V;
2945 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
2946 OpNode, VR256, v8f32, f256mem, memopv8f32,
2947 SSEPackedSingle, itins.s, 0>, TB, VEX_4V, VEX_L;
2948 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
2949 OpNode, VR256, v4f64, f256mem, memopv4f64,
2950 SSEPackedDouble, itins.d, 0>, TB, OpSize, VEX_4V, VEX_L;
2953 let Constraints = "$src1 = $dst" in {
2954 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2955 v4f32, f128mem, memopv4f32, SSEPackedSingle,
2957 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2958 v2f64, f128mem, memopv2f64, SSEPackedDouble,
2959 itins.d, 1>, TB, OpSize;
2963 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2966 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2967 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2968 itins.s, Is2Addr>, XS;
2969 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2970 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2971 itins.d, Is2Addr>, XD;
2974 // Binary Arithmetic instructions
2975 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>;
2976 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>;
2977 let isCommutable = 0 in {
2978 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>;
2979 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>;
2980 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>;
2981 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>;
2984 let isCodeGenOnly = 1 in {
2985 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>;
2986 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>;
2989 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2990 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2992 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2993 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2996 let isCommutable = 0 in {
2997 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2998 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
3000 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
3001 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
3003 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
3004 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
3006 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
3007 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
3011 let Constraints = "$src1 = $dst" in {
3012 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3013 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3014 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3015 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3017 let isCommutable = 0 in {
3018 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3019 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3020 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3021 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3022 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3023 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3024 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3025 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3029 let isCodeGenOnly = 1 in {
3030 defm VMAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S, 0>,
3032 defm VMINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S, 0>,
3034 let Constraints = "$src1 = $dst" in {
3035 defm MAXC: basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3036 defm MINC: basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3041 /// In addition, we also have a special variant of the scalar form here to
3042 /// represent the associated intrinsic operation. This form is unlike the
3043 /// plain scalar form, in that it takes an entire vector (instead of a
3044 /// scalar) and leaves the top elements undefined.
3046 /// And, we have a special variant form for a full-vector intrinsic form.
3048 let Sched = WriteFSqrt in {
3049 def SSE_SQRTPS : OpndItins<
3050 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3053 def SSE_SQRTSS : OpndItins<
3054 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3057 def SSE_SQRTPD : OpndItins<
3058 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3061 def SSE_SQRTSD : OpndItins<
3062 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3066 let Sched = WriteFRcp in {
3067 def SSE_RCPP : OpndItins<
3068 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3071 def SSE_RCPS : OpndItins<
3072 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3076 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3077 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3078 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3079 let Predicates = [HasAVX], hasSideEffects = 0 in {
3080 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3081 (ins FR32:$src1, FR32:$src2),
3082 !strconcat("v", OpcodeStr,
3083 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3084 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3085 let mayLoad = 1 in {
3086 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3087 (ins FR32:$src1,f32mem:$src2),
3088 !strconcat("v", OpcodeStr,
3089 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3090 []>, VEX_4V, VEX_LIG,
3091 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3092 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3093 (ins VR128:$src1, ssmem:$src2),
3094 !strconcat("v", OpcodeStr,
3095 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3096 []>, VEX_4V, VEX_LIG,
3097 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3101 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3102 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3103 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3104 // For scalar unary operations, fold a load into the operation
3105 // only in OptForSize mode. It eliminates an instruction, but it also
3106 // eliminates a whole-register clobber (the load), so it introduces a
3107 // partial register update condition.
3108 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3109 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3110 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3111 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3112 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3113 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3114 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3115 Sched<[itins.Sched]>;
3116 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3117 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3118 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3119 Sched<[itins.Sched.Folded]>;
3122 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3123 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3125 let Predicates = [HasAVX], hasSideEffects = 0 in {
3126 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3127 (ins FR32:$src1, FR32:$src2),
3128 !strconcat("v", OpcodeStr,
3129 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3130 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3131 let mayLoad = 1 in {
3132 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3133 (ins FR32:$src1,f32mem:$src2),
3134 !strconcat("v", OpcodeStr,
3135 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3136 []>, VEX_4V, VEX_LIG,
3137 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3138 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3139 (ins VR128:$src1, ssmem:$src2),
3140 !strconcat("v", OpcodeStr,
3141 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3142 []>, VEX_4V, VEX_LIG,
3143 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3147 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3148 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3149 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3150 // For scalar unary operations, fold a load into the operation
3151 // only in OptForSize mode. It eliminates an instruction, but it also
3152 // eliminates a whole-register clobber (the load), so it introduces a
3153 // partial register update condition.
3154 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3155 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3156 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3157 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3158 let Constraints = "$src1 = $dst" in {
3159 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3160 (ins VR128:$src1, VR128:$src2),
3161 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3162 [], itins.rr>, Sched<[itins.Sched]>;
3163 let mayLoad = 1, hasSideEffects = 0 in
3164 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3165 (ins VR128:$src1, ssmem:$src2),
3166 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3167 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3171 /// sse1_fp_unop_p - SSE1 unops in packed form.
3172 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3174 let Predicates = [HasAVX] in {
3175 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3176 !strconcat("v", OpcodeStr,
3177 "ps\t{$src, $dst|$dst, $src}"),
3178 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3179 itins.rr>, VEX, Sched<[itins.Sched]>;
3180 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3181 !strconcat("v", OpcodeStr,
3182 "ps\t{$src, $dst|$dst, $src}"),
3183 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))],
3184 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3185 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3186 !strconcat("v", OpcodeStr,
3187 "ps\t{$src, $dst|$dst, $src}"),
3188 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3189 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3190 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3191 !strconcat("v", OpcodeStr,
3192 "ps\t{$src, $dst|$dst, $src}"),
3193 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3194 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3197 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3198 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3199 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3200 Sched<[itins.Sched]>;
3201 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3202 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3203 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3204 Sched<[itins.Sched.Folded]>;
3207 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3208 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3209 Intrinsic V4F32Int, Intrinsic V8F32Int,
3211 let Predicates = [HasAVX] in {
3212 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3213 !strconcat("v", OpcodeStr,
3214 "ps\t{$src, $dst|$dst, $src}"),
3215 [(set VR128:$dst, (V4F32Int VR128:$src))],
3216 itins.rr>, VEX, Sched<[itins.Sched]>;
3217 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3218 !strconcat("v", OpcodeStr,
3219 "ps\t{$src, $dst|$dst, $src}"),
3220 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3221 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3222 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3223 !strconcat("v", OpcodeStr,
3224 "ps\t{$src, $dst|$dst, $src}"),
3225 [(set VR256:$dst, (V8F32Int VR256:$src))],
3226 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3227 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3229 !strconcat("v", OpcodeStr,
3230 "ps\t{$src, $dst|$dst, $src}"),
3231 [(set VR256:$dst, (V8F32Int (memopv8f32 addr:$src)))],
3232 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3235 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3236 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3237 [(set VR128:$dst, (V4F32Int VR128:$src))],
3238 itins.rr>, Sched<[itins.Sched]>;
3239 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3240 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3241 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3242 itins.rm>, Sched<[itins.Sched.Folded]>;
3245 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3246 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3247 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3248 let Predicates = [HasAVX], hasSideEffects = 0 in {
3249 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3250 (ins FR64:$src1, FR64:$src2),
3251 !strconcat("v", OpcodeStr,
3252 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3253 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3254 let mayLoad = 1 in {
3255 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3256 (ins FR64:$src1,f64mem:$src2),
3257 !strconcat("v", OpcodeStr,
3258 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3259 []>, VEX_4V, VEX_LIG,
3260 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3261 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3262 (ins VR128:$src1, sdmem:$src2),
3263 !strconcat("v", OpcodeStr,
3264 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3265 []>, VEX_4V, VEX_LIG,
3266 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3270 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3271 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3272 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3273 Sched<[itins.Sched]>;
3274 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3275 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3276 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3277 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3278 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3279 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3280 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3281 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3282 Sched<[itins.Sched]>;
3283 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3284 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3285 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3286 Sched<[itins.Sched.Folded]>;
3289 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3290 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3291 SDNode OpNode, OpndItins itins> {
3292 let Predicates = [HasAVX] in {
3293 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3294 !strconcat("v", OpcodeStr,
3295 "pd\t{$src, $dst|$dst, $src}"),
3296 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3297 itins.rr>, VEX, Sched<[itins.Sched]>;
3298 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3299 !strconcat("v", OpcodeStr,
3300 "pd\t{$src, $dst|$dst, $src}"),
3301 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))],
3302 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3303 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3304 !strconcat("v", OpcodeStr,
3305 "pd\t{$src, $dst|$dst, $src}"),
3306 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3307 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3308 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3309 !strconcat("v", OpcodeStr,
3310 "pd\t{$src, $dst|$dst, $src}"),
3311 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3312 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3315 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3316 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3317 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3318 Sched<[itins.Sched]>;
3319 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3320 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3321 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3322 Sched<[itins.Sched.Folded]>;
3326 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3328 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3329 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3331 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3333 // Reciprocal approximations. Note that these typically require refinement
3334 // in order to obtain suitable precision.
3335 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_SQRTSS>,
3336 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTPS>,
3337 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3338 int_x86_avx_rsqrt_ps_256, SSE_SQRTPS>;
3339 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3340 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3341 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3342 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3344 def : Pat<(f32 (fsqrt FR32:$src)),
3345 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3346 def : Pat<(f32 (fsqrt (load addr:$src))),
3347 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3348 Requires<[HasAVX, OptForSize]>;
3349 def : Pat<(f64 (fsqrt FR64:$src)),
3350 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3351 def : Pat<(f64 (fsqrt (load addr:$src))),
3352 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3353 Requires<[HasAVX, OptForSize]>;
3355 def : Pat<(f32 (X86frsqrt FR32:$src)),
3356 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3357 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3358 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3359 Requires<[HasAVX, OptForSize]>;
3361 def : Pat<(f32 (X86frcp FR32:$src)),
3362 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3363 def : Pat<(f32 (X86frcp (load addr:$src))),
3364 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3365 Requires<[HasAVX, OptForSize]>;
3367 let Predicates = [HasAVX] in {
3368 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3369 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3370 (COPY_TO_REGCLASS VR128:$src, FR32)),
3372 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3373 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3375 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3376 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3377 (COPY_TO_REGCLASS VR128:$src, FR64)),
3379 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3380 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3382 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3383 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3384 (COPY_TO_REGCLASS VR128:$src, FR32)),
3386 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3387 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3389 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3390 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3391 (COPY_TO_REGCLASS VR128:$src, FR32)),
3393 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3394 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3397 // Reciprocal approximations. Note that these typically require refinement
3398 // in order to obtain suitable precision.
3399 let Predicates = [UseSSE1] in {
3400 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3401 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3402 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3403 (RCPSSr_Int VR128:$src, VR128:$src)>;
3406 // There is no f64 version of the reciprocal approximation instructions.
3408 //===----------------------------------------------------------------------===//
3409 // SSE 1 & 2 - Non-temporal stores
3410 //===----------------------------------------------------------------------===//
3412 let AddedComplexity = 400 in { // Prefer non-temporal versions
3413 let SchedRW = [WriteStore] in {
3414 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3415 (ins f128mem:$dst, VR128:$src),
3416 "movntps\t{$src, $dst|$dst, $src}",
3417 [(alignednontemporalstore (v4f32 VR128:$src),
3419 IIC_SSE_MOVNT>, VEX;
3420 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3421 (ins f128mem:$dst, VR128:$src),
3422 "movntpd\t{$src, $dst|$dst, $src}",
3423 [(alignednontemporalstore (v2f64 VR128:$src),
3425 IIC_SSE_MOVNT>, VEX;
3427 let ExeDomain = SSEPackedInt in
3428 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3429 (ins f128mem:$dst, VR128:$src),
3430 "movntdq\t{$src, $dst|$dst, $src}",
3431 [(alignednontemporalstore (v2i64 VR128:$src),
3433 IIC_SSE_MOVNT>, VEX;
3435 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3436 (ins f256mem:$dst, VR256:$src),
3437 "movntps\t{$src, $dst|$dst, $src}",
3438 [(alignednontemporalstore (v8f32 VR256:$src),
3440 IIC_SSE_MOVNT>, VEX, VEX_L;
3441 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3442 (ins f256mem:$dst, VR256:$src),
3443 "movntpd\t{$src, $dst|$dst, $src}",
3444 [(alignednontemporalstore (v4f64 VR256:$src),
3446 IIC_SSE_MOVNT>, VEX, VEX_L;
3447 let ExeDomain = SSEPackedInt in
3448 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3449 (ins f256mem:$dst, VR256:$src),
3450 "movntdq\t{$src, $dst|$dst, $src}",
3451 [(alignednontemporalstore (v4i64 VR256:$src),
3453 IIC_SSE_MOVNT>, VEX, VEX_L;
3455 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3456 "movntps\t{$src, $dst|$dst, $src}",
3457 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3459 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3460 "movntpd\t{$src, $dst|$dst, $src}",
3461 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3464 let ExeDomain = SSEPackedInt in
3465 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3466 "movntdq\t{$src, $dst|$dst, $src}",
3467 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3470 // There is no AVX form for instructions below this point
3471 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3472 "movnti{l}\t{$src, $dst|$dst, $src}",
3473 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3475 TB, Requires<[HasSSE2]>;
3476 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3477 "movnti{q}\t{$src, $dst|$dst, $src}",
3478 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3480 TB, Requires<[HasSSE2]>;
3481 } // SchedRW = [WriteStore]
3483 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3484 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3486 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3487 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[UseSSE2]>;
3488 } // AddedComplexity
3490 //===----------------------------------------------------------------------===//
3491 // SSE 1 & 2 - Prefetch and memory fence
3492 //===----------------------------------------------------------------------===//
3494 // Prefetch intrinsic.
3495 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3496 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3497 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3498 IIC_SSE_PREFETCH>, TB;
3499 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3500 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3501 IIC_SSE_PREFETCH>, TB;
3502 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3503 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3504 IIC_SSE_PREFETCH>, TB;
3505 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3506 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3507 IIC_SSE_PREFETCH>, TB;
3510 // FIXME: How should these memory instructions be modeled?
3511 let SchedRW = [WriteLoad] in {
3513 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3514 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3515 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3517 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3518 // was introduced with SSE2, it's backward compatible.
3519 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3521 // Load, store, and memory fence
3522 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3523 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3524 TB, Requires<[HasSSE1]>;
3525 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3526 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3527 TB, Requires<[HasSSE2]>;
3528 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3529 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3530 TB, Requires<[HasSSE2]>;
3533 def : Pat<(X86SFence), (SFENCE)>;
3534 def : Pat<(X86LFence), (LFENCE)>;
3535 def : Pat<(X86MFence), (MFENCE)>;
3537 //===----------------------------------------------------------------------===//
3538 // SSE 1 & 2 - Load/Store XCSR register
3539 //===----------------------------------------------------------------------===//
3541 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3542 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3543 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3544 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3545 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3546 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3548 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3549 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3550 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3551 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3552 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3553 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3555 //===---------------------------------------------------------------------===//
3556 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3557 //===---------------------------------------------------------------------===//
3559 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3561 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3562 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3563 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3565 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3566 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3568 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3569 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3571 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3572 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3577 let isCodeGenOnly = 1, hasSideEffects = 0, SchedRW = [WriteMove] in {
3578 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3579 "movdqa\t{$src, $dst|$dst, $src}", [],
3582 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3583 "movdqa\t{$src, $dst|$dst, $src}", [],
3584 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3585 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3586 "movdqu\t{$src, $dst|$dst, $src}", [],
3589 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3590 "movdqu\t{$src, $dst|$dst, $src}", [],
3591 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3594 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3595 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3596 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3597 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3599 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3600 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3602 let Predicates = [HasAVX] in {
3603 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3604 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3606 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3607 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3612 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3613 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3614 (ins i128mem:$dst, VR128:$src),
3615 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3617 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3618 (ins i256mem:$dst, VR256:$src),
3619 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3621 let Predicates = [HasAVX] in {
3622 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3623 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3625 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3626 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3631 let SchedRW = [WriteMove] in {
3632 let neverHasSideEffects = 1 in
3633 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3634 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3636 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3637 "movdqu\t{$src, $dst|$dst, $src}",
3638 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3641 let isCodeGenOnly = 1, hasSideEffects = 0 in {
3642 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3643 "movdqa\t{$src, $dst|$dst, $src}", [],
3646 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3647 "movdqu\t{$src, $dst|$dst, $src}",
3648 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3652 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3653 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3654 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3655 "movdqa\t{$src, $dst|$dst, $src}",
3656 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3658 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3659 "movdqu\t{$src, $dst|$dst, $src}",
3660 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3662 XS, Requires<[UseSSE2]>;
3665 let mayStore = 1, SchedRW = [WriteStore] in {
3666 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3667 "movdqa\t{$src, $dst|$dst, $src}",
3668 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3670 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3671 "movdqu\t{$src, $dst|$dst, $src}",
3672 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3674 XS, Requires<[UseSSE2]>;
3677 } // ExeDomain = SSEPackedInt
3679 let Predicates = [HasAVX] in {
3680 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3681 (VMOVDQUmr addr:$dst, VR128:$src)>;
3682 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3683 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3685 let Predicates = [UseSSE2] in
3686 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3687 (MOVDQUmr addr:$dst, VR128:$src)>;
3689 //===---------------------------------------------------------------------===//
3690 // SSE2 - Packed Integer Arithmetic Instructions
3691 //===---------------------------------------------------------------------===//
3693 let Sched = WriteVecIMul in
3694 def SSE_PMADD : OpndItins<
3695 IIC_SSE_PMADD, IIC_SSE_PMADD
3698 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3700 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3701 RegisterClass RC, PatFrag memop_frag,
3702 X86MemOperand x86memop,
3704 bit IsCommutable = 0,
3706 let isCommutable = IsCommutable in
3707 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3708 (ins RC:$src1, RC:$src2),
3710 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3711 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3712 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3713 Sched<[itins.Sched]>;
3714 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3715 (ins RC:$src1, x86memop:$src2),
3717 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3718 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3719 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3720 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3723 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3724 Intrinsic IntId256, OpndItins itins,
3725 bit IsCommutable = 0> {
3726 let Predicates = [HasAVX] in
3727 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3728 VR128, memopv2i64, i128mem, itins,
3729 IsCommutable, 0>, VEX_4V;
3731 let Constraints = "$src1 = $dst" in
3732 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3733 i128mem, itins, IsCommutable, 1>;
3735 let Predicates = [HasAVX2] in
3736 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3737 VR256, memopv4i64, i256mem, itins,
3738 IsCommutable, 0>, VEX_4V, VEX_L;
3741 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3742 string OpcodeStr, SDNode OpNode,
3743 SDNode OpNode2, RegisterClass RC,
3744 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3745 ShiftOpndItins itins,
3747 // src2 is always 128-bit
3748 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3749 (ins RC:$src1, VR128:$src2),
3751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3753 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3754 itins.rr>, Sched<[WriteVecShift]>;
3755 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3756 (ins RC:$src1, i128mem:$src2),
3758 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3759 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3760 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3761 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
3762 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3763 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3764 (ins RC:$src1, i32i8imm:$src2),
3766 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3767 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3768 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>,
3769 Sched<[WriteVecShift]>;
3772 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3773 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3774 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3775 PatFrag memop_frag, X86MemOperand x86memop,
3777 bit IsCommutable = 0, bit Is2Addr = 1> {
3778 let isCommutable = IsCommutable in
3779 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3780 (ins RC:$src1, RC:$src2),
3782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3783 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3784 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3785 Sched<[itins.Sched]>;
3786 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3787 (ins RC:$src1, x86memop:$src2),
3789 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3790 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3791 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3792 (bitconvert (memop_frag addr:$src2)))))]>,
3793 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3795 } // ExeDomain = SSEPackedInt
3797 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
3798 SSE_INTALU_ITINS_P, 1>;
3799 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
3800 SSE_INTALU_ITINS_P, 1>;
3801 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
3802 SSE_INTALU_ITINS_P, 1>;
3803 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
3804 SSE_INTALUQ_ITINS_P, 1>;
3805 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
3806 SSE_INTMUL_ITINS_P, 1>;
3807 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
3808 SSE_INTALU_ITINS_P, 0>;
3809 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
3810 SSE_INTALU_ITINS_P, 0>;
3811 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
3812 SSE_INTALU_ITINS_P, 0>;
3813 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
3814 SSE_INTALUQ_ITINS_P, 0>;
3815 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
3816 SSE_INTALU_ITINS_P, 0>;
3817 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
3818 SSE_INTALU_ITINS_P, 0>;
3819 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
3820 SSE_INTALU_ITINS_P, 1>;
3821 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
3822 SSE_INTALU_ITINS_P, 1>;
3823 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
3824 SSE_INTALU_ITINS_P, 1>;
3825 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
3826 SSE_INTALU_ITINS_P, 1>;
3829 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
3830 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
3831 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3832 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
3833 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3834 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
3835 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3836 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
3837 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3838 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
3839 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3840 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
3841 defm PMULHUW : PDI_binop_all_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3842 int_x86_avx2_pmulhu_w, SSE_INTMUL_ITINS_P, 1>;
3843 defm PMULHW : PDI_binop_all_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3844 int_x86_avx2_pmulh_w, SSE_INTMUL_ITINS_P, 1>;
3845 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3846 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
3847 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3848 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
3849 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3850 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
3851 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3852 int_x86_avx2_psad_bw, SSE_INTALU_ITINS_P, 1>;
3854 let Predicates = [HasAVX] in
3855 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3856 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3858 let Predicates = [HasAVX2] in
3859 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3860 VR256, memopv4i64, i256mem,
3861 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
3862 let Constraints = "$src1 = $dst" in
3863 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3864 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3866 //===---------------------------------------------------------------------===//
3867 // SSE2 - Packed Integer Logical Instructions
3868 //===---------------------------------------------------------------------===//
3870 let Predicates = [HasAVX] in {
3871 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3872 VR128, v8i16, v8i16, bc_v8i16,
3873 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3874 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3875 VR128, v4i32, v4i32, bc_v4i32,
3876 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3877 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3878 VR128, v2i64, v2i64, bc_v2i64,
3879 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3881 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3882 VR128, v8i16, v8i16, bc_v8i16,
3883 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3884 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3885 VR128, v4i32, v4i32, bc_v4i32,
3886 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3887 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3888 VR128, v2i64, v2i64, bc_v2i64,
3889 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3891 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3892 VR128, v8i16, v8i16, bc_v8i16,
3893 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3894 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3895 VR128, v4i32, v4i32, bc_v4i32,
3896 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3898 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3899 // 128-bit logical shifts.
3900 def VPSLLDQri : PDIi8<0x73, MRM7r,
3901 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3902 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3904 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3906 def VPSRLDQri : PDIi8<0x73, MRM3r,
3907 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3908 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3910 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3912 // PSRADQri doesn't exist in SSE[1-3].
3914 } // Predicates = [HasAVX]
3916 let Predicates = [HasAVX2] in {
3917 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3918 VR256, v16i16, v8i16, bc_v8i16,
3919 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3920 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3921 VR256, v8i32, v4i32, bc_v4i32,
3922 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3923 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3924 VR256, v4i64, v2i64, bc_v2i64,
3925 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3927 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3928 VR256, v16i16, v8i16, bc_v8i16,
3929 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3930 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3931 VR256, v8i32, v4i32, bc_v4i32,
3932 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3933 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3934 VR256, v4i64, v2i64, bc_v2i64,
3935 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3937 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3938 VR256, v16i16, v8i16, bc_v8i16,
3939 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3940 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3941 VR256, v8i32, v4i32, bc_v4i32,
3942 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
3944 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3945 // 256-bit logical shifts.
3946 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3947 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3948 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3950 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3952 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3953 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3954 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3956 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3958 // PSRADQYri doesn't exist in SSE[1-3].
3960 } // Predicates = [HasAVX2]
3962 let Constraints = "$src1 = $dst" in {
3963 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3964 VR128, v8i16, v8i16, bc_v8i16,
3965 SSE_INTSHIFT_ITINS_P>;
3966 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
3967 VR128, v4i32, v4i32, bc_v4i32,
3968 SSE_INTSHIFT_ITINS_P>;
3969 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
3970 VR128, v2i64, v2i64, bc_v2i64,
3971 SSE_INTSHIFT_ITINS_P>;
3973 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
3974 VR128, v8i16, v8i16, bc_v8i16,
3975 SSE_INTSHIFT_ITINS_P>;
3976 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
3977 VR128, v4i32, v4i32, bc_v4i32,
3978 SSE_INTSHIFT_ITINS_P>;
3979 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
3980 VR128, v2i64, v2i64, bc_v2i64,
3981 SSE_INTSHIFT_ITINS_P>;
3983 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
3984 VR128, v8i16, v8i16, bc_v8i16,
3985 SSE_INTSHIFT_ITINS_P>;
3986 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
3987 VR128, v4i32, v4i32, bc_v4i32,
3988 SSE_INTSHIFT_ITINS_P>;
3990 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
3991 // 128-bit logical shifts.
3992 def PSLLDQri : PDIi8<0x73, MRM7r,
3993 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3994 "pslldq\t{$src2, $dst|$dst, $src2}",
3996 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
3997 def PSRLDQri : PDIi8<0x73, MRM3r,
3998 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3999 "psrldq\t{$src2, $dst|$dst, $src2}",
4001 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4002 // PSRADQri doesn't exist in SSE[1-3].
4004 } // Constraints = "$src1 = $dst"
4006 let Predicates = [HasAVX] in {
4007 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4008 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4009 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4010 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4011 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4012 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4014 // Shift up / down and insert zero's.
4015 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4016 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4017 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4018 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4021 let Predicates = [HasAVX2] in {
4022 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4023 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4024 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4025 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4028 let Predicates = [UseSSE2] in {
4029 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4030 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4031 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4032 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4033 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4034 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4036 // Shift up / down and insert zero's.
4037 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4038 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4039 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4040 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4043 //===---------------------------------------------------------------------===//
4044 // SSE2 - Packed Integer Comparison Instructions
4045 //===---------------------------------------------------------------------===//
4047 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4048 SSE_INTALU_ITINS_P, 1>;
4049 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4050 SSE_INTALU_ITINS_P, 1>;
4051 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4052 SSE_INTALU_ITINS_P, 1>;
4053 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4054 SSE_INTALU_ITINS_P, 0>;
4055 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4056 SSE_INTALU_ITINS_P, 0>;
4057 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4058 SSE_INTALU_ITINS_P, 0>;
4060 //===---------------------------------------------------------------------===//
4061 // SSE2 - Packed Integer Pack Instructions
4062 //===---------------------------------------------------------------------===//
4064 defm PACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4065 int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
4066 defm PACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4067 int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
4068 defm PACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4069 int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
4071 //===---------------------------------------------------------------------===//
4072 // SSE2 - Packed Integer Shuffle Instructions
4073 //===---------------------------------------------------------------------===//
4075 let ExeDomain = SSEPackedInt in {
4076 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4078 let Predicates = [HasAVX] in {
4079 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4080 (ins VR128:$src1, i8imm:$src2),
4081 !strconcat("v", OpcodeStr,
4082 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4084 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4085 IIC_SSE_PSHUF>, VEX, Sched<[WriteShuffle]>;
4086 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4087 (ins i128mem:$src1, i8imm:$src2),
4088 !strconcat("v", OpcodeStr,
4089 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4091 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4092 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX,
4093 Sched<[WriteShuffleLd]>;
4096 let Predicates = [HasAVX2] in {
4097 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4098 (ins VR256:$src1, i8imm:$src2),
4099 !strconcat("v", OpcodeStr,
4100 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4102 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4103 IIC_SSE_PSHUF>, VEX, VEX_L, Sched<[WriteShuffle]>;
4104 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4105 (ins i256mem:$src1, i8imm:$src2),
4106 !strconcat("v", OpcodeStr,
4107 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4109 (vt256 (OpNode (bitconvert (memopv4i64 addr:$src1)),
4110 (i8 imm:$src2))))], IIC_SSE_PSHUF>, VEX, VEX_L,
4111 Sched<[WriteShuffleLd]>;
4114 let Predicates = [UseSSE2] in {
4115 def ri : Ii8<0x70, MRMSrcReg,
4116 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4117 !strconcat(OpcodeStr,
4118 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4120 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4121 IIC_SSE_PSHUF>, Sched<[WriteShuffle]>;
4122 def mi : Ii8<0x70, MRMSrcMem,
4123 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4124 !strconcat(OpcodeStr,
4125 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4127 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4128 (i8 imm:$src2))))], IIC_SSE_PSHUF>,
4129 Sched<[WriteShuffleLd]>;
4132 } // ExeDomain = SSEPackedInt
4134 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, TB, OpSize;
4135 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4136 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4138 let Predicates = [HasAVX] in {
4139 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4140 (VPSHUFDmi addr:$src1, imm:$imm)>;
4141 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4142 (VPSHUFDri VR128:$src1, imm:$imm)>;
4145 let Predicates = [UseSSE2] in {
4146 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4147 (PSHUFDmi addr:$src1, imm:$imm)>;
4148 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4149 (PSHUFDri VR128:$src1, imm:$imm)>;
4152 //===---------------------------------------------------------------------===//
4153 // SSE2 - Packed Integer Unpack Instructions
4154 //===---------------------------------------------------------------------===//
4156 let ExeDomain = SSEPackedInt in {
4157 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4158 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4159 def rr : PDI<opc, MRMSrcReg,
4160 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4162 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4163 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4164 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4165 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4166 def rm : PDI<opc, MRMSrcMem,
4167 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4169 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4170 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4171 [(set VR128:$dst, (OpNode VR128:$src1,
4172 (bc_frag (memopv2i64
4175 Sched<[WriteShuffleLd, ReadAfterLd]>;
4178 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4179 SDNode OpNode, PatFrag bc_frag> {
4180 def Yrr : PDI<opc, MRMSrcReg,
4181 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4182 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4183 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4184 Sched<[WriteShuffle]>;
4185 def Yrm : PDI<opc, MRMSrcMem,
4186 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4187 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4188 [(set VR256:$dst, (OpNode VR256:$src1,
4189 (bc_frag (memopv4i64 addr:$src2))))]>,
4190 Sched<[WriteShuffleLd, ReadAfterLd]>;
4193 let Predicates = [HasAVX] in {
4194 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4195 bc_v16i8, 0>, VEX_4V;
4196 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4197 bc_v8i16, 0>, VEX_4V;
4198 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4199 bc_v4i32, 0>, VEX_4V;
4200 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4201 bc_v2i64, 0>, VEX_4V;
4203 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4204 bc_v16i8, 0>, VEX_4V;
4205 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4206 bc_v8i16, 0>, VEX_4V;
4207 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4208 bc_v4i32, 0>, VEX_4V;
4209 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4210 bc_v2i64, 0>, VEX_4V;
4213 let Predicates = [HasAVX2] in {
4214 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4215 bc_v32i8>, VEX_4V, VEX_L;
4216 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4217 bc_v16i16>, VEX_4V, VEX_L;
4218 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4219 bc_v8i32>, VEX_4V, VEX_L;
4220 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4221 bc_v4i64>, VEX_4V, VEX_L;
4223 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4224 bc_v32i8>, VEX_4V, VEX_L;
4225 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4226 bc_v16i16>, VEX_4V, VEX_L;
4227 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4228 bc_v8i32>, VEX_4V, VEX_L;
4229 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4230 bc_v4i64>, VEX_4V, VEX_L;
4233 let Constraints = "$src1 = $dst" in {
4234 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4236 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4238 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4240 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4243 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4245 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4247 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4249 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4252 } // ExeDomain = SSEPackedInt
4254 //===---------------------------------------------------------------------===//
4255 // SSE2 - Packed Integer Extract and Insert
4256 //===---------------------------------------------------------------------===//
4258 let ExeDomain = SSEPackedInt in {
4259 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4260 def rri : Ii8<0xC4, MRMSrcReg,
4261 (outs VR128:$dst), (ins VR128:$src1,
4262 GR32:$src2, i32i8imm:$src3),
4264 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4265 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4267 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,
4268 Sched<[WriteShuffle]>;
4269 def rmi : Ii8<0xC4, MRMSrcMem,
4270 (outs VR128:$dst), (ins VR128:$src1,
4271 i16mem:$src2, i32i8imm:$src3),
4273 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4274 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4276 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4277 imm:$src3))], IIC_SSE_PINSRW>,
4278 Sched<[WriteShuffleLd, ReadAfterLd]>;
4282 let Predicates = [HasAVX] in
4283 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4284 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4285 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4286 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4287 imm:$src2))]>, TB, OpSize, VEX,
4288 Sched<[WriteShuffle]>;
4289 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4290 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4291 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4292 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4293 imm:$src2))], IIC_SSE_PEXTRW>,
4294 Sched<[WriteShuffleLd, ReadAfterLd]>;
4297 let Predicates = [HasAVX] in {
4298 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4299 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4300 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4301 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4302 []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;
4305 let Constraints = "$src1 = $dst" in
4306 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[UseSSE2]>;
4308 } // ExeDomain = SSEPackedInt
4310 //===---------------------------------------------------------------------===//
4311 // SSE2 - Packed Mask Creation
4312 //===---------------------------------------------------------------------===//
4314 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4316 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4317 "pmovmskb\t{$src, $dst|$dst, $src}",
4318 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4319 IIC_SSE_MOVMSK>, VEX;
4320 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4321 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4323 let Predicates = [HasAVX2] in {
4324 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4325 "pmovmskb\t{$src, $dst|$dst, $src}",
4326 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;
4327 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4328 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4331 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4332 "pmovmskb\t{$src, $dst|$dst, $src}",
4333 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4336 } // ExeDomain = SSEPackedInt
4338 //===---------------------------------------------------------------------===//
4339 // SSE2 - Conditional Store
4340 //===---------------------------------------------------------------------===//
4342 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4345 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4346 (ins VR128:$src, VR128:$mask),
4347 "maskmovdqu\t{$mask, $src|$src, $mask}",
4348 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4349 IIC_SSE_MASKMOV>, VEX;
4351 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4352 (ins VR128:$src, VR128:$mask),
4353 "maskmovdqu\t{$mask, $src|$src, $mask}",
4354 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4355 IIC_SSE_MASKMOV>, VEX;
4358 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4359 "maskmovdqu\t{$mask, $src|$src, $mask}",
4360 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4363 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4364 "maskmovdqu\t{$mask, $src|$src, $mask}",
4365 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4368 } // ExeDomain = SSEPackedInt
4370 //===---------------------------------------------------------------------===//
4371 // SSE2 - Move Doubleword
4372 //===---------------------------------------------------------------------===//
4374 //===---------------------------------------------------------------------===//
4375 // Move Int Doubleword to Packed Double Int
4377 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4378 "movd\t{$src, $dst|$dst, $src}",
4380 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4381 VEX, Sched<[WriteMove]>;
4382 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4383 "movd\t{$src, $dst|$dst, $src}",
4385 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4387 VEX, Sched<[WriteLoad]>;
4388 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4389 "mov{d|q}\t{$src, $dst|$dst, $src}",
4391 (v2i64 (scalar_to_vector GR64:$src)))],
4392 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4393 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4394 "mov{d|q}\t{$src, $dst|$dst, $src}",
4395 [(set FR64:$dst, (bitconvert GR64:$src))],
4396 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4398 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4399 "movd\t{$src, $dst|$dst, $src}",
4401 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4403 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4404 "movd\t{$src, $dst|$dst, $src}",
4406 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4407 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4408 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4409 "mov{d|q}\t{$src, $dst|$dst, $src}",
4411 (v2i64 (scalar_to_vector GR64:$src)))],
4412 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4413 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4414 "mov{d|q}\t{$src, $dst|$dst, $src}",
4415 [(set FR64:$dst, (bitconvert GR64:$src))],
4416 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4418 //===---------------------------------------------------------------------===//
4419 // Move Int Doubleword to Single Scalar
4421 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4422 "movd\t{$src, $dst|$dst, $src}",
4423 [(set FR32:$dst, (bitconvert GR32:$src))],
4424 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4426 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4427 "movd\t{$src, $dst|$dst, $src}",
4428 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4430 VEX, Sched<[WriteLoad]>;
4431 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4432 "movd\t{$src, $dst|$dst, $src}",
4433 [(set FR32:$dst, (bitconvert GR32:$src))],
4434 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4436 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4437 "movd\t{$src, $dst|$dst, $src}",
4438 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4439 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4441 //===---------------------------------------------------------------------===//
4442 // Move Packed Doubleword Int to Packed Double Int
4444 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4445 "movd\t{$src, $dst|$dst, $src}",
4446 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4447 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4449 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4450 (ins i32mem:$dst, VR128:$src),
4451 "movd\t{$src, $dst|$dst, $src}",
4452 [(store (i32 (vector_extract (v4i32 VR128:$src),
4453 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4454 VEX, Sched<[WriteLoad]>;
4455 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4456 "movd\t{$src, $dst|$dst, $src}",
4457 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4458 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4460 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4461 "movd\t{$src, $dst|$dst, $src}",
4462 [(store (i32 (vector_extract (v4i32 VR128:$src),
4463 (iPTR 0))), addr:$dst)],
4464 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4466 //===---------------------------------------------------------------------===//
4467 // Move Packed Doubleword Int first element to Doubleword Int
4469 let SchedRW = [WriteMove] in {
4470 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4471 "mov{d|q}\t{$src, $dst|$dst, $src}",
4472 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4477 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4478 "mov{d|q}\t{$src, $dst|$dst, $src}",
4479 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4484 //===---------------------------------------------------------------------===//
4485 // Bitcast FR64 <-> GR64
4487 let Predicates = [HasAVX] in
4488 def VMOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4489 "vmovq\t{$src, $dst|$dst, $src}",
4490 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4491 VEX, Sched<[WriteLoad]>;
4492 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4493 "mov{d|q}\t{$src, $dst|$dst, $src}",
4494 [(set GR64:$dst, (bitconvert FR64:$src))],
4495 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4496 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4497 "movq\t{$src, $dst|$dst, $src}",
4498 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4499 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4501 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4502 "movq\t{$src, $dst|$dst, $src}",
4503 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4504 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4505 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4506 "mov{d|q}\t{$src, $dst|$dst, $src}",
4507 [(set GR64:$dst, (bitconvert FR64:$src))],
4508 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4509 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4510 "movq\t{$src, $dst|$dst, $src}",
4511 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4512 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4514 //===---------------------------------------------------------------------===//
4515 // Move Scalar Single to Double Int
4517 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4518 "movd\t{$src, $dst|$dst, $src}",
4519 [(set GR32:$dst, (bitconvert FR32:$src))],
4520 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4521 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4522 "movd\t{$src, $dst|$dst, $src}",
4523 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4524 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4525 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4526 "movd\t{$src, $dst|$dst, $src}",
4527 [(set GR32:$dst, (bitconvert FR32:$src))],
4528 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4529 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4530 "movd\t{$src, $dst|$dst, $src}",
4531 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4532 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4534 //===---------------------------------------------------------------------===//
4535 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4537 let SchedRW = [WriteMove] in {
4538 let AddedComplexity = 15 in {
4539 def VMOVZDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4540 "movd\t{$src, $dst|$dst, $src}",
4541 [(set VR128:$dst, (v4i32 (X86vzmovl
4542 (v4i32 (scalar_to_vector GR32:$src)))))],
4543 IIC_SSE_MOVDQ>, VEX;
4544 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4545 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4546 [(set VR128:$dst, (v2i64 (X86vzmovl
4547 (v2i64 (scalar_to_vector GR64:$src)))))],
4551 let AddedComplexity = 15 in {
4552 def MOVZDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4553 "movd\t{$src, $dst|$dst, $src}",
4554 [(set VR128:$dst, (v4i32 (X86vzmovl
4555 (v4i32 (scalar_to_vector GR32:$src)))))],
4557 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4558 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4559 [(set VR128:$dst, (v2i64 (X86vzmovl
4560 (v2i64 (scalar_to_vector GR64:$src)))))],
4565 let AddedComplexity = 20, SchedRW = [WriteLoad] in {
4566 def VMOVZDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4567 "movd\t{$src, $dst|$dst, $src}",
4569 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4570 (loadi32 addr:$src))))))],
4571 IIC_SSE_MOVDQ>, VEX;
4572 def MOVZDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4573 "movd\t{$src, $dst|$dst, $src}",
4575 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4576 (loadi32 addr:$src))))))],
4578 } // AddedComplexity, SchedRW
4580 let Predicates = [HasAVX] in {
4581 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4582 let AddedComplexity = 20 in {
4583 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4584 (VMOVZDI2PDIrm addr:$src)>;
4585 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4586 (VMOVZDI2PDIrm addr:$src)>;
4588 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4589 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4590 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4591 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4592 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4593 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4594 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4597 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4598 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4599 (MOVZDI2PDIrm addr:$src)>;
4600 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4601 (MOVZDI2PDIrm addr:$src)>;
4604 // These are the correct encodings of the instructions so that we know how to
4605 // read correct assembly, even though we continue to emit the wrong ones for
4606 // compatibility with Darwin's buggy assembler.
4607 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4608 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4609 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4610 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4611 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4612 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4613 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4614 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4615 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4616 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4617 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4618 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4620 //===---------------------------------------------------------------------===//
4621 // SSE2 - Move Quadword
4622 //===---------------------------------------------------------------------===//
4624 //===---------------------------------------------------------------------===//
4625 // Move Quadword Int to Packed Quadword Int
4628 let SchedRW = [WriteLoad] in {
4629 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4630 "vmovq\t{$src, $dst|$dst, $src}",
4632 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4633 VEX, Requires<[HasAVX]>;
4634 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4635 "movq\t{$src, $dst|$dst, $src}",
4637 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4639 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4642 //===---------------------------------------------------------------------===//
4643 // Move Packed Quadword Int to Quadword Int
4645 let SchedRW = [WriteStore] in {
4646 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4647 "movq\t{$src, $dst|$dst, $src}",
4648 [(store (i64 (vector_extract (v2i64 VR128:$src),
4649 (iPTR 0))), addr:$dst)],
4650 IIC_SSE_MOVDQ>, VEX;
4651 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4652 "movq\t{$src, $dst|$dst, $src}",
4653 [(store (i64 (vector_extract (v2i64 VR128:$src),
4654 (iPTR 0))), addr:$dst)],
4658 //===---------------------------------------------------------------------===//
4659 // Store / copy lower 64-bits of a XMM register.
4661 def VMOVLQ128mr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4662 "movq\t{$src, $dst|$dst, $src}",
4663 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX,
4664 Sched<[WriteStore]>;
4665 def MOVLQ128mr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4666 "movq\t{$src, $dst|$dst, $src}",
4667 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4668 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4670 let AddedComplexity = 20 in
4671 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4672 "vmovq\t{$src, $dst|$dst, $src}",
4674 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4675 (loadi64 addr:$src))))))],
4677 XS, VEX, Requires<[HasAVX]>, Sched<[WriteLoad]>;
4679 let AddedComplexity = 20 in
4680 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4681 "movq\t{$src, $dst|$dst, $src}",
4683 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4684 (loadi64 addr:$src))))))],
4686 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
4688 let Predicates = [HasAVX], AddedComplexity = 20 in {
4689 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4690 (VMOVZQI2PQIrm addr:$src)>;
4691 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4692 (VMOVZQI2PQIrm addr:$src)>;
4693 def : Pat<(v2i64 (X86vzload addr:$src)),
4694 (VMOVZQI2PQIrm addr:$src)>;
4697 let Predicates = [UseSSE2], AddedComplexity = 20 in {
4698 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4699 (MOVZQI2PQIrm addr:$src)>;
4700 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4701 (MOVZQI2PQIrm addr:$src)>;
4702 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4705 let Predicates = [HasAVX] in {
4706 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4707 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4708 def : Pat<(v4i64 (X86vzload addr:$src)),
4709 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4712 //===---------------------------------------------------------------------===//
4713 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4714 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4716 let SchedRW = [WriteVecLogic] in {
4717 let AddedComplexity = 15 in
4718 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4719 "vmovq\t{$src, $dst|$dst, $src}",
4720 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4722 XS, VEX, Requires<[HasAVX]>;
4723 let AddedComplexity = 15 in
4724 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4725 "movq\t{$src, $dst|$dst, $src}",
4726 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4728 XS, Requires<[UseSSE2]>;
4731 let SchedRW = [WriteVecLogicLd] in {
4732 let AddedComplexity = 20 in
4733 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4734 "vmovq\t{$src, $dst|$dst, $src}",
4735 [(set VR128:$dst, (v2i64 (X86vzmovl
4736 (loadv2i64 addr:$src))))],
4738 XS, VEX, Requires<[HasAVX]>;
4739 let AddedComplexity = 20 in {
4740 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4741 "movq\t{$src, $dst|$dst, $src}",
4742 [(set VR128:$dst, (v2i64 (X86vzmovl
4743 (loadv2i64 addr:$src))))],
4745 XS, Requires<[UseSSE2]>;
4749 let AddedComplexity = 20 in {
4750 let Predicates = [HasAVX] in {
4751 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4752 (VMOVZPQILo2PQIrm addr:$src)>;
4753 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4754 (VMOVZPQILo2PQIrr VR128:$src)>;
4756 let Predicates = [UseSSE2] in {
4757 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4758 (MOVZPQILo2PQIrm addr:$src)>;
4759 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4760 (MOVZPQILo2PQIrr VR128:$src)>;
4764 // Instructions to match in the assembler
4765 let SchedRW = [WriteMove] in {
4766 def VMOVQs64rr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4767 "movq\t{$src, $dst|$dst, $src}", [],
4768 IIC_SSE_MOVDQ>, VEX, VEX_W;
4769 def VMOVQd64rr : VS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4770 "movq\t{$src, $dst|$dst, $src}", [],
4771 IIC_SSE_MOVDQ>, VEX, VEX_W;
4772 // Recognize "movd" with GR64 destination, but encode as a "movq"
4773 def VMOVQd64rr_alt : VS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4774 "movd\t{$src, $dst|$dst, $src}", [],
4775 IIC_SSE_MOVDQ>, VEX, VEX_W;
4778 // Instructions for the disassembler
4779 // xr = XMM register
4782 let SchedRW = [WriteMove] in {
4783 let Predicates = [HasAVX] in
4784 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4785 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4786 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4787 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4790 //===---------------------------------------------------------------------===//
4791 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4792 //===---------------------------------------------------------------------===//
4793 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4794 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4795 X86MemOperand x86memop> {
4796 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4797 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4798 [(set RC:$dst, (vt (OpNode RC:$src)))],
4799 IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4800 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4801 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4802 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4803 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4806 let Predicates = [HasAVX] in {
4807 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4808 v4f32, VR128, memopv4f32, f128mem>, VEX;
4809 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4810 v4f32, VR128, memopv4f32, f128mem>, VEX;
4811 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4812 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4813 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4814 v8f32, VR256, memopv8f32, f256mem>, VEX, VEX_L;
4816 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4817 memopv4f32, f128mem>;
4818 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4819 memopv4f32, f128mem>;
4821 let Predicates = [HasAVX] in {
4822 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4823 (VMOVSHDUPrr VR128:$src)>;
4824 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4825 (VMOVSHDUPrm addr:$src)>;
4826 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4827 (VMOVSLDUPrr VR128:$src)>;
4828 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4829 (VMOVSLDUPrm addr:$src)>;
4830 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
4831 (VMOVSHDUPYrr VR256:$src)>;
4832 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
4833 (VMOVSHDUPYrm addr:$src)>;
4834 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
4835 (VMOVSLDUPYrr VR256:$src)>;
4836 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
4837 (VMOVSLDUPYrm addr:$src)>;
4840 let Predicates = [UseSSE3] in {
4841 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4842 (MOVSHDUPrr VR128:$src)>;
4843 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
4844 (MOVSHDUPrm addr:$src)>;
4845 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
4846 (MOVSLDUPrr VR128:$src)>;
4847 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
4848 (MOVSLDUPrm addr:$src)>;
4851 //===---------------------------------------------------------------------===//
4852 // SSE3 - Replicate Double FP - MOVDDUP
4853 //===---------------------------------------------------------------------===//
4855 multiclass sse3_replicate_dfp<string OpcodeStr> {
4856 let neverHasSideEffects = 1 in
4857 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4858 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4859 [], IIC_SSE_MOV_LH>, Sched<[WriteShuffle]>;
4860 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
4861 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4864 (scalar_to_vector (loadf64 addr:$src)))))],
4865 IIC_SSE_MOV_LH>, Sched<[WriteShuffleLd]>;
4868 // FIXME: Merge with above classe when there're patterns for the ymm version
4869 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
4870 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
4871 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4872 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
4873 Sched<[WriteShuffle]>;
4874 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
4875 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4878 (scalar_to_vector (loadf64 addr:$src)))))]>,
4879 Sched<[WriteShuffleLd]>;
4882 let Predicates = [HasAVX] in {
4883 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
4884 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
4887 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
4889 let Predicates = [HasAVX] in {
4890 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4891 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4892 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4893 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4894 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4895 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4896 def : Pat<(X86Movddup (bc_v2f64
4897 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4898 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
4901 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
4902 (VMOVDDUPYrm addr:$src)>;
4903 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
4904 (VMOVDDUPYrm addr:$src)>;
4905 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
4906 (VMOVDDUPYrm addr:$src)>;
4907 def : Pat<(X86Movddup (v4i64 VR256:$src)),
4908 (VMOVDDUPYrr VR256:$src)>;
4911 let Predicates = [UseSSE3] in {
4912 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
4913 (MOVDDUPrm addr:$src)>;
4914 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
4915 (MOVDDUPrm addr:$src)>;
4916 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
4917 (MOVDDUPrm addr:$src)>;
4918 def : Pat<(X86Movddup (bc_v2f64
4919 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
4920 (MOVDDUPrm addr:$src)>;
4923 //===---------------------------------------------------------------------===//
4924 // SSE3 - Move Unaligned Integer
4925 //===---------------------------------------------------------------------===//
4927 let SchedRW = [WriteLoad] in {
4928 let Predicates = [HasAVX] in {
4929 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4930 "vlddqu\t{$src, $dst|$dst, $src}",
4931 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
4932 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
4933 "vlddqu\t{$src, $dst|$dst, $src}",
4934 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
4937 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4938 "lddqu\t{$src, $dst|$dst, $src}",
4939 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
4943 //===---------------------------------------------------------------------===//
4944 // SSE3 - Arithmetic
4945 //===---------------------------------------------------------------------===//
4947 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
4948 X86MemOperand x86memop, OpndItins itins,
4950 def rr : I<0xD0, MRMSrcReg,
4951 (outs RC:$dst), (ins RC:$src1, RC:$src2),
4953 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4954 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4955 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
4956 Sched<[itins.Sched]>;
4957 def rm : I<0xD0, MRMSrcMem,
4958 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
4960 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4961 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4962 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
4963 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4966 let Predicates = [HasAVX] in {
4967 let ExeDomain = SSEPackedSingle in {
4968 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
4969 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
4970 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
4971 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V, VEX_L;
4973 let ExeDomain = SSEPackedDouble in {
4974 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
4975 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
4976 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
4977 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V, VEX_L;
4980 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
4981 let ExeDomain = SSEPackedSingle in
4982 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
4983 f128mem, SSE_ALU_F32P>, TB, XD;
4984 let ExeDomain = SSEPackedDouble in
4985 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
4986 f128mem, SSE_ALU_F64P>, TB, OpSize;
4989 //===---------------------------------------------------------------------===//
4990 // SSE3 Instructions
4991 //===---------------------------------------------------------------------===//
4994 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
4995 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
4996 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
4998 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5000 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5003 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5005 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5007 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5008 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5010 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5011 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5012 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5014 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5015 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5016 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5019 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5021 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5022 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5023 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5024 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5027 let Predicates = [HasAVX] in {
5028 let ExeDomain = SSEPackedSingle in {
5029 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5030 X86fhadd, 0>, VEX_4V;
5031 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5032 X86fhsub, 0>, VEX_4V;
5033 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5034 X86fhadd, 0>, VEX_4V, VEX_L;
5035 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5036 X86fhsub, 0>, VEX_4V, VEX_L;
5038 let ExeDomain = SSEPackedDouble in {
5039 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5040 X86fhadd, 0>, VEX_4V;
5041 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5042 X86fhsub, 0>, VEX_4V;
5043 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5044 X86fhadd, 0>, VEX_4V, VEX_L;
5045 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5046 X86fhsub, 0>, VEX_4V, VEX_L;
5050 let Constraints = "$src1 = $dst" in {
5051 let ExeDomain = SSEPackedSingle in {
5052 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5053 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5055 let ExeDomain = SSEPackedDouble in {
5056 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5057 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5061 //===---------------------------------------------------------------------===//
5062 // SSSE3 - Packed Absolute Instructions
5063 //===---------------------------------------------------------------------===//
5066 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5067 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5068 Intrinsic IntId128> {
5069 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5071 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5072 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5073 OpSize, Sched<[WriteVecALU]>;
5075 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5077 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5080 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5081 OpSize, Sched<[WriteVecALULd]>;
5084 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5085 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5086 Intrinsic IntId256> {
5087 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5089 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5090 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5091 OpSize, Sched<[WriteVecALU]>;
5093 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5095 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5098 (bitconvert (memopv4i64 addr:$src))))]>, OpSize,
5099 Sched<[WriteVecALULd]>;
5102 // Helper fragments to match sext vXi1 to vXiY.
5103 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5105 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i32 15)))>;
5106 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i32 31)))>;
5107 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5109 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i32 15)))>;
5110 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i32 31)))>;
5112 let Predicates = [HasAVX] in {
5113 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5114 int_x86_ssse3_pabs_b_128>, VEX;
5115 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5116 int_x86_ssse3_pabs_w_128>, VEX;
5117 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5118 int_x86_ssse3_pabs_d_128>, VEX;
5121 (bc_v2i64 (v16i1sextv16i8)),
5122 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5123 (VPABSBrr128 VR128:$src)>;
5125 (bc_v2i64 (v8i1sextv8i16)),
5126 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5127 (VPABSWrr128 VR128:$src)>;
5129 (bc_v2i64 (v4i1sextv4i32)),
5130 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5131 (VPABSDrr128 VR128:$src)>;
5134 let Predicates = [HasAVX2] in {
5135 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5136 int_x86_avx2_pabs_b>, VEX, VEX_L;
5137 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5138 int_x86_avx2_pabs_w>, VEX, VEX_L;
5139 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5140 int_x86_avx2_pabs_d>, VEX, VEX_L;
5143 (bc_v4i64 (v32i1sextv32i8)),
5144 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5145 (VPABSBrr256 VR256:$src)>;
5147 (bc_v4i64 (v16i1sextv16i16)),
5148 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5149 (VPABSWrr256 VR256:$src)>;
5151 (bc_v4i64 (v8i1sextv8i32)),
5152 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5153 (VPABSDrr256 VR256:$src)>;
5156 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5157 int_x86_ssse3_pabs_b_128>;
5158 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5159 int_x86_ssse3_pabs_w_128>;
5160 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5161 int_x86_ssse3_pabs_d_128>;
5163 let Predicates = [HasSSSE3] in {
5165 (bc_v2i64 (v16i1sextv16i8)),
5166 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5167 (PABSBrr128 VR128:$src)>;
5169 (bc_v2i64 (v8i1sextv8i16)),
5170 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5171 (PABSWrr128 VR128:$src)>;
5173 (bc_v2i64 (v4i1sextv4i32)),
5174 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5175 (PABSDrr128 VR128:$src)>;
5178 //===---------------------------------------------------------------------===//
5179 // SSSE3 - Packed Binary Operator Instructions
5180 //===---------------------------------------------------------------------===//
5182 let Sched = WriteVecALU in {
5183 def SSE_PHADDSUBD : OpndItins<
5184 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5186 def SSE_PHADDSUBSW : OpndItins<
5187 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5189 def SSE_PHADDSUBW : OpndItins<
5190 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5193 let Sched = WriteShuffle in
5194 def SSE_PSHUFB : OpndItins<
5195 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5197 let Sched = WriteVecALU in
5198 def SSE_PSIGN : OpndItins<
5199 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5201 let Sched = WriteVecIMul in
5202 def SSE_PMULHRSW : OpndItins<
5203 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5206 /// SS3I_binop_rm - Simple SSSE3 bin op
5207 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5208 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5209 X86MemOperand x86memop, OpndItins itins,
5211 let isCommutable = 1 in
5212 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5213 (ins RC:$src1, RC:$src2),
5215 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5217 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5218 OpSize, Sched<[itins.Sched]>;
5219 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5220 (ins RC:$src1, x86memop:$src2),
5222 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5223 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5225 (OpVT (OpNode RC:$src1,
5226 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize,
5227 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5230 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5231 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5232 Intrinsic IntId128, OpndItins itins,
5234 let isCommutable = 1 in
5235 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5236 (ins VR128:$src1, VR128:$src2),
5238 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5240 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5241 OpSize, Sched<[itins.Sched]>;
5242 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5243 (ins VR128:$src1, i128mem:$src2),
5245 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5246 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5248 (IntId128 VR128:$src1,
5249 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize,
5250 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5253 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5254 Intrinsic IntId256> {
5255 let isCommutable = 1 in
5256 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5257 (ins VR256:$src1, VR256:$src2),
5258 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5259 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5261 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5262 (ins VR256:$src1, i256mem:$src2),
5263 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5265 (IntId256 VR256:$src1,
5266 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5269 let ImmT = NoImm, Predicates = [HasAVX] in {
5270 let isCommutable = 0 in {
5271 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5272 memopv2i64, i128mem,
5273 SSE_PHADDSUBW, 0>, VEX_4V;
5274 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5275 memopv2i64, i128mem,
5276 SSE_PHADDSUBD, 0>, VEX_4V;
5277 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5278 memopv2i64, i128mem,
5279 SSE_PHADDSUBW, 0>, VEX_4V;
5280 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5281 memopv2i64, i128mem,
5282 SSE_PHADDSUBD, 0>, VEX_4V;
5283 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5284 memopv2i64, i128mem,
5285 SSE_PSIGN, 0>, VEX_4V;
5286 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5287 memopv2i64, i128mem,
5288 SSE_PSIGN, 0>, VEX_4V;
5289 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5290 memopv2i64, i128mem,
5291 SSE_PSIGN, 0>, VEX_4V;
5292 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5293 memopv2i64, i128mem,
5294 SSE_PSHUFB, 0>, VEX_4V;
5295 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5296 int_x86_ssse3_phadd_sw_128,
5297 SSE_PHADDSUBSW, 0>, VEX_4V;
5298 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5299 int_x86_ssse3_phsub_sw_128,
5300 SSE_PHADDSUBSW, 0>, VEX_4V;
5301 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5302 int_x86_ssse3_pmadd_ub_sw_128,
5303 SSE_PMADD, 0>, VEX_4V;
5305 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5306 int_x86_ssse3_pmul_hr_sw_128,
5307 SSE_PMULHRSW, 0>, VEX_4V;
5310 let ImmT = NoImm, Predicates = [HasAVX2] in {
5311 let isCommutable = 0 in {
5312 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5313 memopv4i64, i256mem,
5314 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5315 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5316 memopv4i64, i256mem,
5317 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5318 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5319 memopv4i64, i256mem,
5320 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5321 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5322 memopv4i64, i256mem,
5323 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5324 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5325 memopv4i64, i256mem,
5326 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5327 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5328 memopv4i64, i256mem,
5329 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5330 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5331 memopv4i64, i256mem,
5332 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5333 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5334 memopv4i64, i256mem,
5335 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5336 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5337 int_x86_avx2_phadd_sw>, VEX_4V, VEX_L;
5338 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5339 int_x86_avx2_phsub_sw>, VEX_4V, VEX_L;
5340 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5341 int_x86_avx2_pmadd_ub_sw>, VEX_4V, VEX_L;
5343 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5344 int_x86_avx2_pmul_hr_sw>, VEX_4V, VEX_L;
5347 // None of these have i8 immediate fields.
5348 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5349 let isCommutable = 0 in {
5350 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5351 memopv2i64, i128mem, SSE_PHADDSUBW>;
5352 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5353 memopv2i64, i128mem, SSE_PHADDSUBD>;
5354 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5355 memopv2i64, i128mem, SSE_PHADDSUBW>;
5356 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5357 memopv2i64, i128mem, SSE_PHADDSUBD>;
5358 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5359 memopv2i64, i128mem, SSE_PSIGN>;
5360 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5361 memopv2i64, i128mem, SSE_PSIGN>;
5362 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5363 memopv2i64, i128mem, SSE_PSIGN>;
5364 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5365 memopv2i64, i128mem, SSE_PSHUFB>;
5366 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5367 int_x86_ssse3_phadd_sw_128,
5369 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5370 int_x86_ssse3_phsub_sw_128,
5372 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5373 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5375 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5376 int_x86_ssse3_pmul_hr_sw_128,
5380 //===---------------------------------------------------------------------===//
5381 // SSSE3 - Packed Align Instruction Patterns
5382 //===---------------------------------------------------------------------===//
5384 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5385 let neverHasSideEffects = 1 in {
5386 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5387 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5389 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5391 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5392 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffle]>;
5394 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5395 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5397 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5399 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5400 [], IIC_SSE_PALIGNR>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5404 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5405 let neverHasSideEffects = 1 in {
5406 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5407 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5409 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5410 []>, OpSize, Sched<[WriteShuffle]>;
5412 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5413 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5415 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5416 []>, OpSize, Sched<[WriteShuffleLd, ReadAfterLd]>;
5420 let Predicates = [HasAVX] in
5421 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5422 let Predicates = [HasAVX2] in
5423 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5424 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5425 defm PALIGN : ssse3_palignr<"palignr">;
5427 let Predicates = [HasAVX2] in {
5428 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5429 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5430 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5431 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5432 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5433 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5434 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5435 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5438 let Predicates = [HasAVX] in {
5439 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5440 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5441 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5442 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5443 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5444 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5445 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5446 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5449 let Predicates = [UseSSSE3] in {
5450 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5451 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5452 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5453 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5454 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5455 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5456 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5457 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5460 //===---------------------------------------------------------------------===//
5461 // SSSE3 - Thread synchronization
5462 //===---------------------------------------------------------------------===//
5464 let SchedRW = [WriteSystem] in {
5465 let usesCustomInserter = 1 in {
5466 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5467 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5468 Requires<[HasSSE3]>;
5471 let Uses = [EAX, ECX, EDX] in
5472 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5473 TB, Requires<[HasSSE3]>;
5474 let Uses = [ECX, EAX] in
5475 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5476 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5477 TB, Requires<[HasSSE3]>;
5480 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[In32BitMode]>;
5481 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5483 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5484 Requires<[In32BitMode]>;
5485 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5486 Requires<[In64BitMode]>;
5488 //===----------------------------------------------------------------------===//
5489 // SSE4.1 - Packed Move with Sign/Zero Extend
5490 //===----------------------------------------------------------------------===//
5492 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5493 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5494 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5495 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5497 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5498 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5500 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5504 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5506 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5507 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5508 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5510 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5511 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5512 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5515 let Predicates = [HasAVX] in {
5516 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5518 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5520 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5522 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5524 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5526 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5530 let Predicates = [HasAVX2] in {
5531 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5532 int_x86_avx2_pmovsxbw>, VEX, VEX_L;
5533 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5534 int_x86_avx2_pmovsxwd>, VEX, VEX_L;
5535 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5536 int_x86_avx2_pmovsxdq>, VEX, VEX_L;
5537 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5538 int_x86_avx2_pmovzxbw>, VEX, VEX_L;
5539 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5540 int_x86_avx2_pmovzxwd>, VEX, VEX_L;
5541 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5542 int_x86_avx2_pmovzxdq>, VEX, VEX_L;
5545 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5546 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5547 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5548 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5549 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5550 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5552 let Predicates = [HasAVX] in {
5553 // Common patterns involving scalar load.
5554 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5555 (VPMOVSXBWrm addr:$src)>;
5556 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5557 (VPMOVSXBWrm addr:$src)>;
5558 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5559 (VPMOVSXBWrm addr:$src)>;
5561 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5562 (VPMOVSXWDrm addr:$src)>;
5563 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5564 (VPMOVSXWDrm addr:$src)>;
5565 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5566 (VPMOVSXWDrm addr:$src)>;
5568 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5569 (VPMOVSXDQrm addr:$src)>;
5570 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5571 (VPMOVSXDQrm addr:$src)>;
5572 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5573 (VPMOVSXDQrm addr:$src)>;
5575 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5576 (VPMOVZXBWrm addr:$src)>;
5577 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5578 (VPMOVZXBWrm addr:$src)>;
5579 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5580 (VPMOVZXBWrm addr:$src)>;
5582 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5583 (VPMOVZXWDrm addr:$src)>;
5584 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5585 (VPMOVZXWDrm addr:$src)>;
5586 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5587 (VPMOVZXWDrm addr:$src)>;
5589 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5590 (VPMOVZXDQrm addr:$src)>;
5591 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5592 (VPMOVZXDQrm addr:$src)>;
5593 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5594 (VPMOVZXDQrm addr:$src)>;
5597 let Predicates = [UseSSE41] in {
5598 // Common patterns involving scalar load.
5599 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5600 (PMOVSXBWrm addr:$src)>;
5601 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5602 (PMOVSXBWrm addr:$src)>;
5603 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
5604 (PMOVSXBWrm addr:$src)>;
5606 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5607 (PMOVSXWDrm addr:$src)>;
5608 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5609 (PMOVSXWDrm addr:$src)>;
5610 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
5611 (PMOVSXWDrm addr:$src)>;
5613 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5614 (PMOVSXDQrm addr:$src)>;
5615 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5616 (PMOVSXDQrm addr:$src)>;
5617 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
5618 (PMOVSXDQrm addr:$src)>;
5620 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5621 (PMOVZXBWrm addr:$src)>;
5622 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5623 (PMOVZXBWrm addr:$src)>;
5624 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
5625 (PMOVZXBWrm addr:$src)>;
5627 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5628 (PMOVZXWDrm addr:$src)>;
5629 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5630 (PMOVZXWDrm addr:$src)>;
5631 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
5632 (PMOVZXWDrm addr:$src)>;
5634 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5635 (PMOVZXDQrm addr:$src)>;
5636 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5637 (PMOVZXDQrm addr:$src)>;
5638 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
5639 (PMOVZXDQrm addr:$src)>;
5642 let Predicates = [HasAVX2] in {
5643 let AddedComplexity = 15 in {
5644 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5645 (VPMOVZXDQYrr VR128:$src)>;
5646 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5647 (VPMOVZXWDYrr VR128:$src)>;
5650 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5651 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5654 let Predicates = [HasAVX] in {
5655 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5656 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5659 let Predicates = [UseSSE41] in {
5660 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5661 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5665 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5666 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5667 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5668 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5670 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5671 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5673 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5677 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5679 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5680 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5681 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5683 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5684 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5686 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5690 let Predicates = [HasAVX] in {
5691 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5693 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5695 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5697 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5701 let Predicates = [HasAVX2] in {
5702 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5703 int_x86_avx2_pmovsxbd>, VEX, VEX_L;
5704 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5705 int_x86_avx2_pmovsxwq>, VEX, VEX_L;
5706 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5707 int_x86_avx2_pmovzxbd>, VEX, VEX_L;
5708 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5709 int_x86_avx2_pmovzxwq>, VEX, VEX_L;
5712 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5713 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5714 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5715 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5717 let Predicates = [HasAVX] in {
5718 // Common patterns involving scalar load
5719 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5720 (VPMOVSXBDrm addr:$src)>;
5721 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5722 (VPMOVSXWQrm addr:$src)>;
5724 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5725 (VPMOVZXBDrm addr:$src)>;
5726 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5727 (VPMOVZXWQrm addr:$src)>;
5730 let Predicates = [UseSSE41] in {
5731 // Common patterns involving scalar load
5732 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5733 (PMOVSXBDrm addr:$src)>;
5734 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5735 (PMOVSXWQrm addr:$src)>;
5737 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5738 (PMOVZXBDrm addr:$src)>;
5739 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5740 (PMOVZXWQrm addr:$src)>;
5743 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5744 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5746 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5748 // Expecting a i16 load any extended to i32 value.
5749 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5750 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5751 [(set VR128:$dst, (IntId (bitconvert
5752 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5756 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5758 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5760 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5762 // Expecting a i16 load any extended to i32 value.
5763 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5765 [(set VR256:$dst, (IntId (bitconvert
5766 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5770 let Predicates = [HasAVX] in {
5771 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5773 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5776 let Predicates = [HasAVX2] in {
5777 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5778 int_x86_avx2_pmovsxbq>, VEX, VEX_L;
5779 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5780 int_x86_avx2_pmovzxbq>, VEX, VEX_L;
5782 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5783 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5785 let Predicates = [HasAVX2] in {
5786 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
5787 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
5788 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
5790 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5791 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
5793 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5795 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
5796 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5797 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
5798 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5799 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
5800 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5802 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
5803 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5804 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
5805 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5807 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
5808 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5810 def : Pat<(v8i32 (X86vsmovl (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
5811 (VPMOVSXWDYrm addr:$src)>;
5812 def : Pat<(v4i64 (X86vsmovl (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
5813 (VPMOVSXDQYrm addr:$src)>;
5815 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
5816 (scalar_to_vector (loadi64 addr:$src))))))),
5817 (VPMOVSXBDYrm addr:$src)>;
5818 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
5819 (scalar_to_vector (loadf64 addr:$src))))))),
5820 (VPMOVSXBDYrm addr:$src)>;
5822 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
5823 (scalar_to_vector (loadi64 addr:$src))))))),
5824 (VPMOVSXWQYrm addr:$src)>;
5825 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
5826 (scalar_to_vector (loadf64 addr:$src))))))),
5827 (VPMOVSXWQYrm addr:$src)>;
5829 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
5830 (scalar_to_vector (loadi32 addr:$src))))))),
5831 (VPMOVSXBQYrm addr:$src)>;
5834 let Predicates = [HasAVX] in {
5835 // Common patterns involving scalar load
5836 def : Pat<(int_x86_sse41_pmovsxbq
5837 (bitconvert (v4i32 (X86vzmovl
5838 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5839 (VPMOVSXBQrm addr:$src)>;
5841 def : Pat<(int_x86_sse41_pmovzxbq
5842 (bitconvert (v4i32 (X86vzmovl
5843 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5844 (VPMOVZXBQrm addr:$src)>;
5847 let Predicates = [UseSSE41] in {
5848 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
5849 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
5850 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
5852 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5853 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
5855 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5857 // Common patterns involving scalar load
5858 def : Pat<(int_x86_sse41_pmovsxbq
5859 (bitconvert (v4i32 (X86vzmovl
5860 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5861 (PMOVSXBQrm addr:$src)>;
5863 def : Pat<(int_x86_sse41_pmovzxbq
5864 (bitconvert (v4i32 (X86vzmovl
5865 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5866 (PMOVZXBQrm addr:$src)>;
5868 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5869 (scalar_to_vector (loadi64 addr:$src))))))),
5870 (PMOVSXWDrm addr:$src)>;
5871 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5872 (scalar_to_vector (loadf64 addr:$src))))))),
5873 (PMOVSXWDrm addr:$src)>;
5874 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5875 (scalar_to_vector (loadi32 addr:$src))))))),
5876 (PMOVSXBDrm addr:$src)>;
5877 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5878 (scalar_to_vector (loadi32 addr:$src))))))),
5879 (PMOVSXWQrm addr:$src)>;
5880 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5881 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5882 (PMOVSXBQrm addr:$src)>;
5883 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5884 (scalar_to_vector (loadi64 addr:$src))))))),
5885 (PMOVSXDQrm addr:$src)>;
5886 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5887 (scalar_to_vector (loadf64 addr:$src))))))),
5888 (PMOVSXDQrm addr:$src)>;
5889 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5890 (scalar_to_vector (loadi64 addr:$src))))))),
5891 (PMOVSXBWrm addr:$src)>;
5892 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5893 (scalar_to_vector (loadf64 addr:$src))))))),
5894 (PMOVSXBWrm addr:$src)>;
5897 let Predicates = [HasAVX2] in {
5898 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
5899 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
5900 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
5902 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
5903 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
5905 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
5907 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
5908 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5909 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
5910 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5911 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
5912 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5914 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
5915 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5916 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
5917 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5919 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
5920 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5923 let Predicates = [HasAVX] in {
5924 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
5925 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
5926 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
5928 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
5929 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
5931 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
5933 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5934 (VPMOVZXBWrm addr:$src)>;
5935 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5936 (VPMOVZXBWrm addr:$src)>;
5937 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5938 (VPMOVZXBDrm addr:$src)>;
5939 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
5940 (VPMOVZXBQrm addr:$src)>;
5942 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5943 (VPMOVZXWDrm addr:$src)>;
5944 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5945 (VPMOVZXWDrm addr:$src)>;
5946 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5947 (VPMOVZXWQrm addr:$src)>;
5949 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
5950 (VPMOVZXDQrm addr:$src)>;
5951 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
5952 (VPMOVZXDQrm addr:$src)>;
5953 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
5954 (VPMOVZXDQrm addr:$src)>;
5956 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
5957 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
5958 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
5960 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5961 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
5963 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5965 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
5966 (scalar_to_vector (loadi64 addr:$src))))))),
5967 (VPMOVSXWDrm addr:$src)>;
5968 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
5969 (scalar_to_vector (loadi64 addr:$src))))))),
5970 (VPMOVSXDQrm addr:$src)>;
5971 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
5972 (scalar_to_vector (loadf64 addr:$src))))))),
5973 (VPMOVSXWDrm addr:$src)>;
5974 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
5975 (scalar_to_vector (loadf64 addr:$src))))))),
5976 (VPMOVSXDQrm addr:$src)>;
5977 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
5978 (scalar_to_vector (loadi64 addr:$src))))))),
5979 (VPMOVSXBWrm addr:$src)>;
5980 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
5981 (scalar_to_vector (loadf64 addr:$src))))))),
5982 (VPMOVSXBWrm addr:$src)>;
5984 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
5985 (scalar_to_vector (loadi32 addr:$src))))))),
5986 (VPMOVSXBDrm addr:$src)>;
5987 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
5988 (scalar_to_vector (loadi32 addr:$src))))))),
5989 (VPMOVSXWQrm addr:$src)>;
5990 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
5991 (scalar_to_vector (extloadi32i16 addr:$src))))))),
5992 (VPMOVSXBQrm addr:$src)>;
5995 let Predicates = [UseSSE41] in {
5996 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
5997 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
5998 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6000 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6001 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6003 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6005 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6006 (PMOVZXBWrm addr:$src)>;
6007 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6008 (PMOVZXBWrm addr:$src)>;
6009 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6010 (PMOVZXBDrm addr:$src)>;
6011 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6012 (PMOVZXBQrm addr:$src)>;
6014 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6015 (PMOVZXWDrm addr:$src)>;
6016 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6017 (PMOVZXWDrm addr:$src)>;
6018 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6019 (PMOVZXWQrm addr:$src)>;
6021 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6022 (PMOVZXDQrm addr:$src)>;
6023 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6024 (PMOVZXDQrm addr:$src)>;
6025 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6026 (PMOVZXDQrm addr:$src)>;
6029 //===----------------------------------------------------------------------===//
6030 // SSE4.1 - Extract Instructions
6031 //===----------------------------------------------------------------------===//
6033 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6034 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6035 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6036 (ins VR128:$src1, i32i8imm:$src2),
6037 !strconcat(OpcodeStr,
6038 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6039 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
6041 let neverHasSideEffects = 1, mayStore = 1 in
6042 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6043 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6044 !strconcat(OpcodeStr,
6045 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6048 // There's an AssertZext in the way of writing the store pattern
6049 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6052 let Predicates = [HasAVX] in {
6053 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6054 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
6055 (ins VR128:$src1, i32i8imm:$src2),
6056 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
6059 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6062 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6063 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6064 let neverHasSideEffects = 1, mayStore = 1 in
6065 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6066 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6067 !strconcat(OpcodeStr,
6068 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6071 // There's an AssertZext in the way of writing the store pattern
6072 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
6075 let Predicates = [HasAVX] in
6076 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6078 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6081 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6082 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6083 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6084 (ins VR128:$src1, i32i8imm:$src2),
6085 !strconcat(OpcodeStr,
6086 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6088 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
6089 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6090 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6091 !strconcat(OpcodeStr,
6092 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6093 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6094 addr:$dst)]>, OpSize;
6097 let Predicates = [HasAVX] in
6098 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6100 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6102 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6103 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6104 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6105 (ins VR128:$src1, i32i8imm:$src2),
6106 !strconcat(OpcodeStr,
6107 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6109 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
6110 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6111 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6112 !strconcat(OpcodeStr,
6113 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6114 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6115 addr:$dst)]>, OpSize, REX_W;
6118 let Predicates = [HasAVX] in
6119 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6121 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6123 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6125 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
6126 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6127 (ins VR128:$src1, i32i8imm:$src2),
6128 !strconcat(OpcodeStr,
6129 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6131 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
6133 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6134 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6135 !strconcat(OpcodeStr,
6136 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6137 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6138 addr:$dst)]>, OpSize;
6141 let ExeDomain = SSEPackedSingle in {
6142 let Predicates = [UseAVX] in {
6143 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6144 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6145 (ins VR128:$src1, i32i8imm:$src2),
6146 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
6149 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6152 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6153 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6156 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6158 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6161 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6162 Requires<[UseSSE41]>;
6164 //===----------------------------------------------------------------------===//
6165 // SSE4.1 - Insert Instructions
6166 //===----------------------------------------------------------------------===//
6168 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6169 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6170 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6172 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6174 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6176 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6177 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6178 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6180 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6182 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6184 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6185 imm:$src3))]>, OpSize;
6188 let Predicates = [HasAVX] in
6189 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6190 let Constraints = "$src1 = $dst" in
6191 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6193 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6194 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6195 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6197 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6199 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6201 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6203 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6204 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6206 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6208 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6210 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6211 imm:$src3)))]>, OpSize;
6214 let Predicates = [HasAVX] in
6215 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6216 let Constraints = "$src1 = $dst" in
6217 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6219 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6220 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6221 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6223 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6227 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6229 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6230 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6232 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6234 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6236 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6237 imm:$src3)))]>, OpSize;
6240 let Predicates = [HasAVX] in
6241 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6242 let Constraints = "$src1 = $dst" in
6243 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6245 // insertps has a few different modes, there's the first two here below which
6246 // are optimized inserts that won't zero arbitrary elements in the destination
6247 // vector. The next one matches the intrinsic and could zero arbitrary elements
6248 // in the target vector.
6249 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6250 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6251 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6253 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6255 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6257 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6259 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6260 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6262 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6264 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6266 (X86insrtps VR128:$src1,
6267 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6268 imm:$src3))]>, OpSize;
6271 let ExeDomain = SSEPackedSingle in {
6272 let Predicates = [HasAVX] in
6273 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6274 let Constraints = "$src1 = $dst" in
6275 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6278 //===----------------------------------------------------------------------===//
6279 // SSE4.1 - Round Instructions
6280 //===----------------------------------------------------------------------===//
6282 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6283 X86MemOperand x86memop, RegisterClass RC,
6284 PatFrag mem_frag32, PatFrag mem_frag64,
6285 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6286 let ExeDomain = SSEPackedSingle in {
6287 // Intrinsic operation, reg.
6288 // Vector intrinsic operation, reg
6289 def PSr : SS4AIi8<opcps, MRMSrcReg,
6290 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6291 !strconcat(OpcodeStr,
6292 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6293 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6296 // Vector intrinsic operation, mem
6297 def PSm : SS4AIi8<opcps, MRMSrcMem,
6298 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6299 !strconcat(OpcodeStr,
6300 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6302 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6304 } // ExeDomain = SSEPackedSingle
6306 let ExeDomain = SSEPackedDouble in {
6307 // Vector intrinsic operation, reg
6308 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6309 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6310 !strconcat(OpcodeStr,
6311 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6312 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6315 // Vector intrinsic operation, mem
6316 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6317 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6318 !strconcat(OpcodeStr,
6319 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6321 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6323 } // ExeDomain = SSEPackedDouble
6326 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6329 Intrinsic F64Int, bit Is2Addr = 1> {
6330 let ExeDomain = GenericDomain in {
6332 let hasSideEffects = 0 in
6333 def SSr : SS4AIi8<opcss, MRMSrcReg,
6334 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6336 !strconcat(OpcodeStr,
6337 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6338 !strconcat(OpcodeStr,
6339 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6342 // Intrinsic operation, reg.
6343 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6344 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6346 !strconcat(OpcodeStr,
6347 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6348 !strconcat(OpcodeStr,
6349 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6350 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6353 // Intrinsic operation, mem.
6354 def SSm : SS4AIi8<opcss, MRMSrcMem,
6355 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6357 !strconcat(OpcodeStr,
6358 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6359 !strconcat(OpcodeStr,
6360 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6362 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6366 let hasSideEffects = 0 in
6367 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6368 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6370 !strconcat(OpcodeStr,
6371 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6372 !strconcat(OpcodeStr,
6373 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6376 // Intrinsic operation, reg.
6377 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6378 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6380 !strconcat(OpcodeStr,
6381 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6382 !strconcat(OpcodeStr,
6383 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6384 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6387 // Intrinsic operation, mem.
6388 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6389 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6391 !strconcat(OpcodeStr,
6392 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6393 !strconcat(OpcodeStr,
6394 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6396 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6398 } // ExeDomain = GenericDomain
6401 // FP round - roundss, roundps, roundsd, roundpd
6402 let Predicates = [HasAVX] in {
6404 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6405 memopv4f32, memopv2f64,
6406 int_x86_sse41_round_ps,
6407 int_x86_sse41_round_pd>, VEX;
6408 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6409 memopv8f32, memopv4f64,
6410 int_x86_avx_round_ps_256,
6411 int_x86_avx_round_pd_256>, VEX, VEX_L;
6412 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6413 int_x86_sse41_round_ss,
6414 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6416 def : Pat<(ffloor FR32:$src),
6417 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6418 def : Pat<(f64 (ffloor FR64:$src)),
6419 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6420 def : Pat<(f32 (fnearbyint FR32:$src)),
6421 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6422 def : Pat<(f64 (fnearbyint FR64:$src)),
6423 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6424 def : Pat<(f32 (fceil FR32:$src)),
6425 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6426 def : Pat<(f64 (fceil FR64:$src)),
6427 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6428 def : Pat<(f32 (frint FR32:$src)),
6429 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6430 def : Pat<(f64 (frint FR64:$src)),
6431 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6432 def : Pat<(f32 (ftrunc FR32:$src)),
6433 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6434 def : Pat<(f64 (ftrunc FR64:$src)),
6435 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6437 def : Pat<(v4f32 (ffloor VR128:$src)),
6438 (VROUNDPSr VR128:$src, (i32 0x1))>;
6439 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6440 (VROUNDPSr VR128:$src, (i32 0xC))>;
6441 def : Pat<(v4f32 (fceil VR128:$src)),
6442 (VROUNDPSr VR128:$src, (i32 0x2))>;
6443 def : Pat<(v4f32 (frint VR128:$src)),
6444 (VROUNDPSr VR128:$src, (i32 0x4))>;
6445 def : Pat<(v4f32 (ftrunc VR128:$src)),
6446 (VROUNDPSr VR128:$src, (i32 0x3))>;
6448 def : Pat<(v2f64 (ffloor VR128:$src)),
6449 (VROUNDPDr VR128:$src, (i32 0x1))>;
6450 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6451 (VROUNDPDr VR128:$src, (i32 0xC))>;
6452 def : Pat<(v2f64 (fceil VR128:$src)),
6453 (VROUNDPDr VR128:$src, (i32 0x2))>;
6454 def : Pat<(v2f64 (frint VR128:$src)),
6455 (VROUNDPDr VR128:$src, (i32 0x4))>;
6456 def : Pat<(v2f64 (ftrunc VR128:$src)),
6457 (VROUNDPDr VR128:$src, (i32 0x3))>;
6459 def : Pat<(v8f32 (ffloor VR256:$src)),
6460 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6461 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6462 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6463 def : Pat<(v8f32 (fceil VR256:$src)),
6464 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6465 def : Pat<(v8f32 (frint VR256:$src)),
6466 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6467 def : Pat<(v8f32 (ftrunc VR256:$src)),
6468 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6470 def : Pat<(v4f64 (ffloor VR256:$src)),
6471 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6472 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6473 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6474 def : Pat<(v4f64 (fceil VR256:$src)),
6475 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6476 def : Pat<(v4f64 (frint VR256:$src)),
6477 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6478 def : Pat<(v4f64 (ftrunc VR256:$src)),
6479 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6482 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6483 memopv4f32, memopv2f64,
6484 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6485 let Constraints = "$src1 = $dst" in
6486 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6487 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6489 let Predicates = [UseSSE41] in {
6490 def : Pat<(ffloor FR32:$src),
6491 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6492 def : Pat<(f64 (ffloor FR64:$src)),
6493 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6494 def : Pat<(f32 (fnearbyint FR32:$src)),
6495 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6496 def : Pat<(f64 (fnearbyint FR64:$src)),
6497 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6498 def : Pat<(f32 (fceil FR32:$src)),
6499 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6500 def : Pat<(f64 (fceil FR64:$src)),
6501 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6502 def : Pat<(f32 (frint FR32:$src)),
6503 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6504 def : Pat<(f64 (frint FR64:$src)),
6505 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6506 def : Pat<(f32 (ftrunc FR32:$src)),
6507 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6508 def : Pat<(f64 (ftrunc FR64:$src)),
6509 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6511 def : Pat<(v4f32 (ffloor VR128:$src)),
6512 (ROUNDPSr VR128:$src, (i32 0x1))>;
6513 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6514 (ROUNDPSr VR128:$src, (i32 0xC))>;
6515 def : Pat<(v4f32 (fceil VR128:$src)),
6516 (ROUNDPSr VR128:$src, (i32 0x2))>;
6517 def : Pat<(v4f32 (frint VR128:$src)),
6518 (ROUNDPSr VR128:$src, (i32 0x4))>;
6519 def : Pat<(v4f32 (ftrunc VR128:$src)),
6520 (ROUNDPSr VR128:$src, (i32 0x3))>;
6522 def : Pat<(v2f64 (ffloor VR128:$src)),
6523 (ROUNDPDr VR128:$src, (i32 0x1))>;
6524 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6525 (ROUNDPDr VR128:$src, (i32 0xC))>;
6526 def : Pat<(v2f64 (fceil VR128:$src)),
6527 (ROUNDPDr VR128:$src, (i32 0x2))>;
6528 def : Pat<(v2f64 (frint VR128:$src)),
6529 (ROUNDPDr VR128:$src, (i32 0x4))>;
6530 def : Pat<(v2f64 (ftrunc VR128:$src)),
6531 (ROUNDPDr VR128:$src, (i32 0x3))>;
6534 //===----------------------------------------------------------------------===//
6535 // SSE4.1 - Packed Bit Test
6536 //===----------------------------------------------------------------------===//
6538 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6539 // the intel intrinsic that corresponds to this.
6540 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6541 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6542 "vptest\t{$src2, $src1|$src1, $src2}",
6543 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6545 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6546 "vptest\t{$src2, $src1|$src1, $src2}",
6547 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6550 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6551 "vptest\t{$src2, $src1|$src1, $src2}",
6552 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6554 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6555 "vptest\t{$src2, $src1|$src1, $src2}",
6556 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6560 let Defs = [EFLAGS] in {
6561 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6562 "ptest\t{$src2, $src1|$src1, $src2}",
6563 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6565 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6566 "ptest\t{$src2, $src1|$src1, $src2}",
6567 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6571 // The bit test instructions below are AVX only
6572 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6573 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6574 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6575 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6576 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6577 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6578 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6579 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6583 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6584 let ExeDomain = SSEPackedSingle in {
6585 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6586 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>,
6589 let ExeDomain = SSEPackedDouble in {
6590 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6591 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>,
6596 //===----------------------------------------------------------------------===//
6597 // SSE4.1 - Misc Instructions
6598 //===----------------------------------------------------------------------===//
6600 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6601 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6602 "popcnt{w}\t{$src, $dst|$dst, $src}",
6603 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6605 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6606 "popcnt{w}\t{$src, $dst|$dst, $src}",
6607 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6608 (implicit EFLAGS)]>, OpSize, XS;
6610 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6611 "popcnt{l}\t{$src, $dst|$dst, $src}",
6612 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6614 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6615 "popcnt{l}\t{$src, $dst|$dst, $src}",
6616 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6617 (implicit EFLAGS)]>, XS;
6619 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6620 "popcnt{q}\t{$src, $dst|$dst, $src}",
6621 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6623 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6624 "popcnt{q}\t{$src, $dst|$dst, $src}",
6625 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6626 (implicit EFLAGS)]>, XS;
6631 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6632 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6633 Intrinsic IntId128> {
6634 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6636 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6637 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6638 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6640 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6643 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6646 let Predicates = [HasAVX] in
6647 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6648 int_x86_sse41_phminposuw>, VEX;
6649 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6650 int_x86_sse41_phminposuw>;
6652 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6653 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6654 Intrinsic IntId128, bit Is2Addr = 1> {
6655 let isCommutable = 1 in
6656 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6657 (ins VR128:$src1, VR128:$src2),
6659 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6660 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6661 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6662 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6663 (ins VR128:$src1, i128mem:$src2),
6665 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6666 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6668 (IntId128 VR128:$src1,
6669 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6672 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
6673 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6674 Intrinsic IntId256> {
6675 let isCommutable = 1 in
6676 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6677 (ins VR256:$src1, VR256:$src2),
6678 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6679 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6680 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6681 (ins VR256:$src1, i256mem:$src2),
6682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6684 (IntId256 VR256:$src1,
6685 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6689 /// SS48I_binop_rm - Simple SSE41 binary operator.
6690 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6691 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6692 X86MemOperand x86memop, bit Is2Addr = 1> {
6693 let isCommutable = 1 in
6694 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6695 (ins RC:$src1, RC:$src2),
6697 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6698 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6699 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6700 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6701 (ins RC:$src1, x86memop:$src2),
6703 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6704 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6706 (OpVT (OpNode RC:$src1,
6707 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6710 let Predicates = [HasAVX] in {
6711 let isCommutable = 0 in
6712 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6714 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6715 memopv2i64, i128mem, 0>, VEX_4V;
6716 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6717 memopv2i64, i128mem, 0>, VEX_4V;
6718 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6719 memopv2i64, i128mem, 0>, VEX_4V;
6720 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6721 memopv2i64, i128mem, 0>, VEX_4V;
6722 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6723 memopv2i64, i128mem, 0>, VEX_4V;
6724 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6725 memopv2i64, i128mem, 0>, VEX_4V;
6726 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6727 memopv2i64, i128mem, 0>, VEX_4V;
6728 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6729 memopv2i64, i128mem, 0>, VEX_4V;
6730 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6734 let Predicates = [HasAVX2] in {
6735 let isCommutable = 0 in
6736 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6737 int_x86_avx2_packusdw>, VEX_4V, VEX_L;
6738 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6739 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6740 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6741 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6742 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6743 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6744 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6745 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6746 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6747 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6748 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6749 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6750 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6751 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6752 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6753 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6754 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6755 int_x86_avx2_pmul_dq>, VEX_4V, VEX_L;
6758 let Constraints = "$src1 = $dst" in {
6759 let isCommutable = 0 in
6760 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6761 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6762 memopv2i64, i128mem>;
6763 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6764 memopv2i64, i128mem>;
6765 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6766 memopv2i64, i128mem>;
6767 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6768 memopv2i64, i128mem>;
6769 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6770 memopv2i64, i128mem>;
6771 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6772 memopv2i64, i128mem>;
6773 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6774 memopv2i64, i128mem>;
6775 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6776 memopv2i64, i128mem>;
6777 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6780 let Predicates = [HasAVX] in {
6781 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6782 memopv2i64, i128mem, 0>, VEX_4V;
6783 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6784 memopv2i64, i128mem, 0>, VEX_4V;
6786 let Predicates = [HasAVX2] in {
6787 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6788 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6789 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6790 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6793 let Constraints = "$src1 = $dst" in {
6794 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6795 memopv2i64, i128mem>;
6796 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6797 memopv2i64, i128mem>;
6800 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6801 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6802 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6803 X86MemOperand x86memop, bit Is2Addr = 1> {
6804 let isCommutable = 1 in
6805 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6806 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6808 !strconcat(OpcodeStr,
6809 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6810 !strconcat(OpcodeStr,
6811 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6812 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6814 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6815 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6817 !strconcat(OpcodeStr,
6818 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6819 !strconcat(OpcodeStr,
6820 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6823 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6827 let Predicates = [HasAVX] in {
6828 let isCommutable = 0 in {
6829 let ExeDomain = SSEPackedSingle in {
6830 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6831 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6832 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6833 int_x86_avx_blend_ps_256, VR256, memopv8f32,
6834 f256mem, 0>, VEX_4V, VEX_L;
6836 let ExeDomain = SSEPackedDouble in {
6837 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6838 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6839 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6840 int_x86_avx_blend_pd_256,VR256, memopv4f64,
6841 f256mem, 0>, VEX_4V, VEX_L;
6843 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6844 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6845 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6846 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6848 let ExeDomain = SSEPackedSingle in
6849 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6850 VR128, memopv4f32, f128mem, 0>, VEX_4V;
6851 let ExeDomain = SSEPackedDouble in
6852 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6853 VR128, memopv2f64, f128mem, 0>, VEX_4V;
6854 let ExeDomain = SSEPackedSingle in
6855 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6856 VR256, memopv8f32, i256mem, 0>, VEX_4V, VEX_L;
6859 let Predicates = [HasAVX2] in {
6860 let isCommutable = 0 in {
6861 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6862 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6863 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6864 VR256, memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
6868 let Constraints = "$src1 = $dst" in {
6869 let isCommutable = 0 in {
6870 let ExeDomain = SSEPackedSingle in
6871 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6872 VR128, memopv4f32, f128mem>;
6873 let ExeDomain = SSEPackedDouble in
6874 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6875 VR128, memopv2f64, f128mem>;
6876 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6877 VR128, memopv2i64, i128mem>;
6878 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6879 VR128, memopv2i64, i128mem>;
6881 let ExeDomain = SSEPackedSingle in
6882 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6883 VR128, memopv4f32, f128mem>;
6884 let ExeDomain = SSEPackedDouble in
6885 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6886 VR128, memopv2f64, f128mem>;
6889 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6890 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6891 RegisterClass RC, X86MemOperand x86memop,
6892 PatFrag mem_frag, Intrinsic IntId> {
6893 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6894 (ins RC:$src1, RC:$src2, RC:$src3),
6895 !strconcat(OpcodeStr,
6896 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6897 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6898 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6900 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6901 (ins RC:$src1, x86memop:$src2, RC:$src3),
6902 !strconcat(OpcodeStr,
6903 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6905 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6907 NoItinerary, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6910 let Predicates = [HasAVX] in {
6911 let ExeDomain = SSEPackedDouble in {
6912 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
6913 memopv2f64, int_x86_sse41_blendvpd>;
6914 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
6915 memopv4f64, int_x86_avx_blendv_pd_256>, VEX_L;
6916 } // ExeDomain = SSEPackedDouble
6917 let ExeDomain = SSEPackedSingle in {
6918 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
6919 memopv4f32, int_x86_sse41_blendvps>;
6920 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
6921 memopv8f32, int_x86_avx_blendv_ps_256>, VEX_L;
6922 } // ExeDomain = SSEPackedSingle
6923 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6924 memopv2i64, int_x86_sse41_pblendvb>;
6927 let Predicates = [HasAVX2] in {
6928 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6929 memopv4i64, int_x86_avx2_pblendvb>, VEX_L;
6932 let Predicates = [HasAVX] in {
6933 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6934 (v16i8 VR128:$src2))),
6935 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6936 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6937 (v4i32 VR128:$src2))),
6938 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6939 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6940 (v4f32 VR128:$src2))),
6941 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6942 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6943 (v2i64 VR128:$src2))),
6944 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6945 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6946 (v2f64 VR128:$src2))),
6947 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6948 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6949 (v8i32 VR256:$src2))),
6950 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6951 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6952 (v8f32 VR256:$src2))),
6953 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6954 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6955 (v4i64 VR256:$src2))),
6956 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6957 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6958 (v4f64 VR256:$src2))),
6959 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6961 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6963 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6964 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6966 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6968 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6970 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
6971 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6973 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
6974 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6976 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
6979 let Predicates = [HasAVX2] in {
6980 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6981 (v32i8 VR256:$src2))),
6982 (VPBLENDVBYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
6983 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6985 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
6988 /// SS41I_ternary_int - SSE 4.1 ternary operator
6989 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6990 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6991 X86MemOperand x86memop, Intrinsic IntId> {
6992 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6993 (ins VR128:$src1, VR128:$src2),
6994 !strconcat(OpcodeStr,
6995 "\t{$src2, $dst|$dst, $src2}"),
6996 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6999 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7000 (ins VR128:$src1, x86memop:$src2),
7001 !strconcat(OpcodeStr,
7002 "\t{$src2, $dst|$dst, $src2}"),
7005 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
7009 let ExeDomain = SSEPackedDouble in
7010 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7011 int_x86_sse41_blendvpd>;
7012 let ExeDomain = SSEPackedSingle in
7013 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7014 int_x86_sse41_blendvps>;
7015 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7016 int_x86_sse41_pblendvb>;
7018 // Aliases with the implicit xmm0 argument
7019 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7020 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7021 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7022 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7023 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7024 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7025 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7026 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7027 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7028 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7029 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7030 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7032 let Predicates = [UseSSE41] in {
7033 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7034 (v16i8 VR128:$src2))),
7035 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7036 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7037 (v4i32 VR128:$src2))),
7038 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7039 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7040 (v4f32 VR128:$src2))),
7041 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7042 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7043 (v2i64 VR128:$src2))),
7044 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7045 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7046 (v2f64 VR128:$src2))),
7047 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7049 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7051 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7052 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7054 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7055 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7057 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7061 let Predicates = [HasAVX] in
7062 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7063 "vmovntdqa\t{$src, $dst|$dst, $src}",
7064 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7066 let Predicates = [HasAVX2] in
7067 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7068 "vmovntdqa\t{$src, $dst|$dst, $src}",
7069 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7071 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7072 "movntdqa\t{$src, $dst|$dst, $src}",
7073 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7076 //===----------------------------------------------------------------------===//
7077 // SSE4.2 - Compare Instructions
7078 //===----------------------------------------------------------------------===//
7080 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7081 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7082 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7083 X86MemOperand x86memop, bit Is2Addr = 1> {
7084 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7085 (ins RC:$src1, RC:$src2),
7087 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7088 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7089 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7091 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7092 (ins RC:$src1, x86memop:$src2),
7094 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7095 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7097 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
7100 let Predicates = [HasAVX] in
7101 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7102 memopv2i64, i128mem, 0>, VEX_4V;
7104 let Predicates = [HasAVX2] in
7105 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7106 memopv4i64, i256mem, 0>, VEX_4V, VEX_L;
7108 let Constraints = "$src1 = $dst" in
7109 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7110 memopv2i64, i128mem>;
7112 //===----------------------------------------------------------------------===//
7113 // SSE4.2 - String/text Processing Instructions
7114 //===----------------------------------------------------------------------===//
7116 // Packed Compare Implicit Length Strings, Return Mask
7117 multiclass pseudo_pcmpistrm<string asm> {
7118 def REG : PseudoI<(outs VR128:$dst),
7119 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7120 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7122 def MEM : PseudoI<(outs VR128:$dst),
7123 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7124 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7125 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7128 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7129 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7130 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7133 multiclass pcmpistrm_SS42AI<string asm> {
7134 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7135 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7136 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7139 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7140 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7141 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7145 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7146 let Predicates = [HasAVX] in
7147 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7148 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7151 // Packed Compare Explicit Length Strings, Return Mask
7152 multiclass pseudo_pcmpestrm<string asm> {
7153 def REG : PseudoI<(outs VR128:$dst),
7154 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7155 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7156 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7157 def MEM : PseudoI<(outs VR128:$dst),
7158 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7159 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7160 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7163 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7164 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7165 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7168 multiclass SS42AI_pcmpestrm<string asm> {
7169 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7170 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7171 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7174 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7175 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7176 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7180 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7181 let Predicates = [HasAVX] in
7182 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7183 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7186 // Packed Compare Implicit Length Strings, Return Index
7187 multiclass pseudo_pcmpistri<string asm> {
7188 def REG : PseudoI<(outs GR32:$dst),
7189 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7190 [(set GR32:$dst, EFLAGS,
7191 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7192 def MEM : PseudoI<(outs GR32:$dst),
7193 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7194 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7195 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7198 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7199 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7200 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7203 multiclass SS42AI_pcmpistri<string asm> {
7204 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7205 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7206 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7209 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7210 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7211 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7215 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7216 let Predicates = [HasAVX] in
7217 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7218 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7221 // Packed Compare Explicit Length Strings, Return Index
7222 multiclass pseudo_pcmpestri<string asm> {
7223 def REG : PseudoI<(outs GR32:$dst),
7224 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7225 [(set GR32:$dst, EFLAGS,
7226 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7227 def MEM : PseudoI<(outs GR32:$dst),
7228 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7229 [(set GR32:$dst, EFLAGS,
7230 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7234 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7235 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7236 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7239 multiclass SS42AI_pcmpestri<string asm> {
7240 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7241 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7242 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7245 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7246 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7247 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7251 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7252 let Predicates = [HasAVX] in
7253 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7254 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7257 //===----------------------------------------------------------------------===//
7258 // SSE4.2 - CRC Instructions
7259 //===----------------------------------------------------------------------===//
7261 // No CRC instructions have AVX equivalents
7263 // crc intrinsic instruction
7264 // This set of instructions are only rm, the only difference is the size
7266 let Constraints = "$src1 = $dst" in {
7267 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7268 (ins GR32:$src1, i8mem:$src2),
7269 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7271 (int_x86_sse42_crc32_32_8 GR32:$src1,
7272 (load addr:$src2)))]>;
7273 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7274 (ins GR32:$src1, GR8:$src2),
7275 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7277 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7278 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7279 (ins GR32:$src1, i16mem:$src2),
7280 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7282 (int_x86_sse42_crc32_32_16 GR32:$src1,
7283 (load addr:$src2)))]>,
7285 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7286 (ins GR32:$src1, GR16:$src2),
7287 "crc32{w}\t{$src2, $src1|$src1, $src2}",
7289 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7291 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7292 (ins GR32:$src1, i32mem:$src2),
7293 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7295 (int_x86_sse42_crc32_32_32 GR32:$src1,
7296 (load addr:$src2)))]>;
7297 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7298 (ins GR32:$src1, GR32:$src2),
7299 "crc32{l}\t{$src2, $src1|$src1, $src2}",
7301 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7302 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7303 (ins GR64:$src1, i8mem:$src2),
7304 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7306 (int_x86_sse42_crc32_64_8 GR64:$src1,
7307 (load addr:$src2)))]>,
7309 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7310 (ins GR64:$src1, GR8:$src2),
7311 "crc32{b}\t{$src2, $src1|$src1, $src2}",
7313 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7315 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7316 (ins GR64:$src1, i64mem:$src2),
7317 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7319 (int_x86_sse42_crc32_64_64 GR64:$src1,
7320 (load addr:$src2)))]>,
7322 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7323 (ins GR64:$src1, GR64:$src2),
7324 "crc32{q}\t{$src2, $src1|$src1, $src2}",
7326 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7330 //===----------------------------------------------------------------------===//
7331 // AES-NI Instructions
7332 //===----------------------------------------------------------------------===//
7334 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7335 Intrinsic IntId128, bit Is2Addr = 1> {
7336 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7337 (ins VR128:$src1, VR128:$src2),
7339 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7341 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7343 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7344 (ins VR128:$src1, i128mem:$src2),
7346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7349 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7352 // Perform One Round of an AES Encryption/Decryption Flow
7353 let Predicates = [HasAVX, HasAES] in {
7354 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7355 int_x86_aesni_aesenc, 0>, VEX_4V;
7356 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7357 int_x86_aesni_aesenclast, 0>, VEX_4V;
7358 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7359 int_x86_aesni_aesdec, 0>, VEX_4V;
7360 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7361 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7364 let Constraints = "$src1 = $dst" in {
7365 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7366 int_x86_aesni_aesenc>;
7367 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7368 int_x86_aesni_aesenclast>;
7369 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7370 int_x86_aesni_aesdec>;
7371 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7372 int_x86_aesni_aesdeclast>;
7375 // Perform the AES InvMixColumn Transformation
7376 let Predicates = [HasAVX, HasAES] in {
7377 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7379 "vaesimc\t{$src1, $dst|$dst, $src1}",
7381 (int_x86_aesni_aesimc VR128:$src1))]>,
7383 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7384 (ins i128mem:$src1),
7385 "vaesimc\t{$src1, $dst|$dst, $src1}",
7386 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7389 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7391 "aesimc\t{$src1, $dst|$dst, $src1}",
7393 (int_x86_aesni_aesimc VR128:$src1))]>,
7395 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7396 (ins i128mem:$src1),
7397 "aesimc\t{$src1, $dst|$dst, $src1}",
7398 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7401 // AES Round Key Generation Assist
7402 let Predicates = [HasAVX, HasAES] in {
7403 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7404 (ins VR128:$src1, i8imm:$src2),
7405 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7407 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7409 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7410 (ins i128mem:$src1, i8imm:$src2),
7411 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7413 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7416 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7417 (ins VR128:$src1, i8imm:$src2),
7418 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7420 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7422 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7423 (ins i128mem:$src1, i8imm:$src2),
7424 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7426 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7429 //===----------------------------------------------------------------------===//
7430 // PCLMUL Instructions
7431 //===----------------------------------------------------------------------===//
7433 // AVX carry-less Multiplication instructions
7434 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7435 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7436 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7438 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7440 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7441 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7442 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7443 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7444 (memopv2i64 addr:$src2), imm:$src3))]>;
7446 // Carry-less Multiplication instructions
7447 let Constraints = "$src1 = $dst" in {
7448 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7449 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7450 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7452 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7454 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7455 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7456 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7457 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7458 (memopv2i64 addr:$src2), imm:$src3))]>;
7459 } // Constraints = "$src1 = $dst"
7462 multiclass pclmul_alias<string asm, int immop> {
7463 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7464 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7466 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7467 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7469 def : InstAlias<!strconcat("vpclmul", asm,
7470 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7471 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7473 def : InstAlias<!strconcat("vpclmul", asm,
7474 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7475 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7477 defm : pclmul_alias<"hqhq", 0x11>;
7478 defm : pclmul_alias<"hqlq", 0x01>;
7479 defm : pclmul_alias<"lqhq", 0x10>;
7480 defm : pclmul_alias<"lqlq", 0x00>;
7482 //===----------------------------------------------------------------------===//
7483 // SSE4A Instructions
7484 //===----------------------------------------------------------------------===//
7486 let Predicates = [HasSSE4A] in {
7488 let Constraints = "$src = $dst" in {
7489 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7490 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7491 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7492 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7493 imm:$idx))]>, TB, OpSize;
7494 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7495 (ins VR128:$src, VR128:$mask),
7496 "extrq\t{$mask, $src|$src, $mask}",
7497 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7498 VR128:$mask))]>, TB, OpSize;
7500 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7501 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7502 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7503 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7504 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7505 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7506 (ins VR128:$src, VR128:$mask),
7507 "insertq\t{$mask, $src|$src, $mask}",
7508 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7509 VR128:$mask))]>, XD;
7512 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7513 "movntss\t{$src, $dst|$dst, $src}",
7514 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7516 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7517 "movntsd\t{$src, $dst|$dst, $src}",
7518 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7521 //===----------------------------------------------------------------------===//
7523 //===----------------------------------------------------------------------===//
7525 //===----------------------------------------------------------------------===//
7526 // VBROADCAST - Load from memory and broadcast to all elements of the
7527 // destination operand
7529 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7530 X86MemOperand x86memop, Intrinsic Int> :
7531 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7532 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7533 [(set RC:$dst, (Int addr:$src))]>, VEX;
7535 // AVX2 adds register forms
7536 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7538 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7540 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7542 let ExeDomain = SSEPackedSingle in {
7543 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7544 int_x86_avx_vbroadcast_ss>;
7545 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7546 int_x86_avx_vbroadcast_ss_256>, VEX_L;
7548 let ExeDomain = SSEPackedDouble in
7549 def VBROADCASTSDYrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7550 int_x86_avx_vbroadcast_sd_256>, VEX_L;
7551 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7552 int_x86_avx_vbroadcastf128_pd_256>, VEX_L;
7554 let ExeDomain = SSEPackedSingle in {
7555 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7556 int_x86_avx2_vbroadcast_ss_ps>;
7557 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7558 int_x86_avx2_vbroadcast_ss_ps_256>, VEX_L;
7560 let ExeDomain = SSEPackedDouble in
7561 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7562 int_x86_avx2_vbroadcast_sd_pd_256>, VEX_L;
7564 let Predicates = [HasAVX2] in
7565 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7566 int_x86_avx2_vbroadcasti128>, VEX_L;
7568 let Predicates = [HasAVX] in
7569 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7570 (VBROADCASTF128 addr:$src)>;
7573 //===----------------------------------------------------------------------===//
7574 // VINSERTF128 - Insert packed floating-point values
7576 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7577 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7578 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7579 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7582 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7583 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7584 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7588 let Predicates = [HasAVX] in {
7589 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7591 (VINSERTF128rr VR256:$src1, VR128:$src2,
7592 (INSERT_get_vinsert128_imm VR256:$ins))>;
7593 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7595 (VINSERTF128rr VR256:$src1, VR128:$src2,
7596 (INSERT_get_vinsert128_imm VR256:$ins))>;
7598 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (memopv4f32 addr:$src2),
7600 (VINSERTF128rm VR256:$src1, addr:$src2,
7601 (INSERT_get_vinsert128_imm VR256:$ins))>;
7602 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (memopv2f64 addr:$src2),
7604 (VINSERTF128rm VR256:$src1, addr:$src2,
7605 (INSERT_get_vinsert128_imm VR256:$ins))>;
7608 let Predicates = [HasAVX1Only] in {
7609 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7611 (VINSERTF128rr VR256:$src1, VR128:$src2,
7612 (INSERT_get_vinsert128_imm VR256:$ins))>;
7613 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7615 (VINSERTF128rr VR256:$src1, VR128:$src2,
7616 (INSERT_get_vinsert128_imm VR256:$ins))>;
7617 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7619 (VINSERTF128rr VR256:$src1, VR128:$src2,
7620 (INSERT_get_vinsert128_imm VR256:$ins))>;
7621 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7623 (VINSERTF128rr VR256:$src1, VR128:$src2,
7624 (INSERT_get_vinsert128_imm VR256:$ins))>;
7626 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
7628 (VINSERTF128rm VR256:$src1, addr:$src2,
7629 (INSERT_get_vinsert128_imm VR256:$ins))>;
7630 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7631 (bc_v4i32 (memopv2i64 addr:$src2)),
7633 (VINSERTF128rm VR256:$src1, addr:$src2,
7634 (INSERT_get_vinsert128_imm VR256:$ins))>;
7635 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7636 (bc_v16i8 (memopv2i64 addr:$src2)),
7638 (VINSERTF128rm VR256:$src1, addr:$src2,
7639 (INSERT_get_vinsert128_imm VR256:$ins))>;
7640 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7641 (bc_v8i16 (memopv2i64 addr:$src2)),
7643 (VINSERTF128rm VR256:$src1, addr:$src2,
7644 (INSERT_get_vinsert128_imm VR256:$ins))>;
7647 //===----------------------------------------------------------------------===//
7648 // VEXTRACTF128 - Extract packed floating-point values
7650 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7651 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7652 (ins VR256:$src1, i8imm:$src2),
7653 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7656 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7657 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7658 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7663 let Predicates = [HasAVX] in {
7664 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7665 (v4f32 (VEXTRACTF128rr
7666 (v8f32 VR256:$src1),
7667 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7668 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7669 (v2f64 (VEXTRACTF128rr
7670 (v4f64 VR256:$src1),
7671 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7673 def : Pat<(alignedstore (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7674 (iPTR imm))), addr:$dst),
7675 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7676 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7677 def : Pat<(alignedstore (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7678 (iPTR imm))), addr:$dst),
7679 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7680 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7683 let Predicates = [HasAVX1Only] in {
7684 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7685 (v2i64 (VEXTRACTF128rr
7686 (v4i64 VR256:$src1),
7687 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7688 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7689 (v4i32 (VEXTRACTF128rr
7690 (v8i32 VR256:$src1),
7691 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7692 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7693 (v8i16 (VEXTRACTF128rr
7694 (v16i16 VR256:$src1),
7695 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7696 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7697 (v16i8 (VEXTRACTF128rr
7698 (v32i8 VR256:$src1),
7699 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7701 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7702 (iPTR imm))), addr:$dst),
7703 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7704 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7705 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7706 (iPTR imm))), addr:$dst),
7707 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7708 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7709 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
7710 (iPTR imm))), addr:$dst),
7711 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7712 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7713 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
7714 (iPTR imm))), addr:$dst),
7715 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7716 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7719 //===----------------------------------------------------------------------===//
7720 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7722 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7723 Intrinsic IntLd, Intrinsic IntLd256,
7724 Intrinsic IntSt, Intrinsic IntSt256> {
7725 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7726 (ins VR128:$src1, f128mem:$src2),
7727 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7728 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7730 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7731 (ins VR256:$src1, f256mem:$src2),
7732 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7733 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7735 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7736 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7737 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7738 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7739 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7740 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7741 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7742 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
7745 let ExeDomain = SSEPackedSingle in
7746 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7747 int_x86_avx_maskload_ps,
7748 int_x86_avx_maskload_ps_256,
7749 int_x86_avx_maskstore_ps,
7750 int_x86_avx_maskstore_ps_256>;
7751 let ExeDomain = SSEPackedDouble in
7752 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7753 int_x86_avx_maskload_pd,
7754 int_x86_avx_maskload_pd_256,
7755 int_x86_avx_maskstore_pd,
7756 int_x86_avx_maskstore_pd_256>;
7758 //===----------------------------------------------------------------------===//
7759 // VPERMIL - Permute Single and Double Floating-Point Values
7761 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7762 RegisterClass RC, X86MemOperand x86memop_f,
7763 X86MemOperand x86memop_i, PatFrag i_frag,
7764 Intrinsic IntVar, ValueType vt> {
7765 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7766 (ins RC:$src1, RC:$src2),
7767 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7768 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7769 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7770 (ins RC:$src1, x86memop_i:$src2),
7771 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7772 [(set RC:$dst, (IntVar RC:$src1,
7773 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7775 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7776 (ins RC:$src1, i8imm:$src2),
7777 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7778 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7779 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7780 (ins x86memop_f:$src1, i8imm:$src2),
7781 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7783 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7786 let ExeDomain = SSEPackedSingle in {
7787 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7788 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7789 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7790 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
7792 let ExeDomain = SSEPackedDouble in {
7793 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7794 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7795 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7796 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
7799 let Predicates = [HasAVX] in {
7800 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7801 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7802 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7803 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7804 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7806 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7807 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7808 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7810 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7811 (VPERMILPDri VR128:$src1, imm:$imm)>;
7812 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7813 (VPERMILPDmi addr:$src1, imm:$imm)>;
7816 //===----------------------------------------------------------------------===//
7817 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7819 let ExeDomain = SSEPackedSingle in {
7820 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7821 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7822 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7823 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7824 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
7825 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7826 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7827 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7828 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7829 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
7832 let Predicates = [HasAVX] in {
7833 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7834 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7835 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7836 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7837 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7840 let Predicates = [HasAVX1Only] in {
7841 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7842 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7843 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7844 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7845 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7846 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7847 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7848 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7850 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7851 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7852 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7853 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7854 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7855 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7856 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7857 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7858 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7859 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7860 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7861 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7864 //===----------------------------------------------------------------------===//
7865 // VZERO - Zero YMM registers
7867 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7868 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7869 // Zero All YMM registers
7870 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7871 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7873 // Zero Upper bits of YMM registers
7874 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7875 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7878 //===----------------------------------------------------------------------===//
7879 // Half precision conversion instructions
7880 //===----------------------------------------------------------------------===//
7881 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7882 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7883 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7884 [(set RC:$dst, (Int VR128:$src))]>,
7886 let neverHasSideEffects = 1, mayLoad = 1 in
7887 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7888 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7891 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7892 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7893 (ins RC:$src1, i32i8imm:$src2),
7894 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7895 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7897 let neverHasSideEffects = 1, mayStore = 1 in
7898 def mr : Ii8<0x1D, MRMDestMem, (outs),
7899 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7900 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7904 let Predicates = [HasAVX, HasF16C] in {
7905 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7906 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
7907 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7908 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
7911 //===----------------------------------------------------------------------===//
7912 // AVX2 Instructions
7913 //===----------------------------------------------------------------------===//
7915 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7916 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7917 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7918 X86MemOperand x86memop> {
7919 let isCommutable = 1 in
7920 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7921 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7922 !strconcat(OpcodeStr,
7923 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7924 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7926 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7927 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7928 !strconcat(OpcodeStr,
7929 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7932 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7936 let isCommutable = 0 in {
7937 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7938 VR128, memopv2i64, i128mem>;
7939 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7940 VR256, memopv4i64, i256mem>, VEX_L;
7943 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
7945 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7946 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
7948 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7950 //===----------------------------------------------------------------------===//
7951 // VPBROADCAST - Load from memory and broadcast to all elements of the
7952 // destination operand
7954 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7955 X86MemOperand x86memop, PatFrag ld_frag,
7956 Intrinsic Int128, Intrinsic Int256> {
7957 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7958 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7959 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7960 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7961 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7963 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7964 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7965 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7966 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX, VEX_L;
7967 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7968 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7970 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
7974 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7975 int_x86_avx2_pbroadcastb_128,
7976 int_x86_avx2_pbroadcastb_256>;
7977 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7978 int_x86_avx2_pbroadcastw_128,
7979 int_x86_avx2_pbroadcastw_256>;
7980 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7981 int_x86_avx2_pbroadcastd_128,
7982 int_x86_avx2_pbroadcastd_256>;
7983 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7984 int_x86_avx2_pbroadcastq_128,
7985 int_x86_avx2_pbroadcastq_256>;
7987 let Predicates = [HasAVX2] in {
7988 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7989 (VPBROADCASTBrm addr:$src)>;
7990 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7991 (VPBROADCASTBYrm addr:$src)>;
7992 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7993 (VPBROADCASTWrm addr:$src)>;
7994 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7995 (VPBROADCASTWYrm addr:$src)>;
7996 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7997 (VPBROADCASTDrm addr:$src)>;
7998 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7999 (VPBROADCASTDYrm addr:$src)>;
8000 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8001 (VPBROADCASTQrm addr:$src)>;
8002 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8003 (VPBROADCASTQYrm addr:$src)>;
8005 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8006 (VPBROADCASTBrr VR128:$src)>;
8007 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8008 (VPBROADCASTBYrr VR128:$src)>;
8009 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8010 (VPBROADCASTWrr VR128:$src)>;
8011 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8012 (VPBROADCASTWYrr VR128:$src)>;
8013 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8014 (VPBROADCASTDrr VR128:$src)>;
8015 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8016 (VPBROADCASTDYrr VR128:$src)>;
8017 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8018 (VPBROADCASTQrr VR128:$src)>;
8019 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8020 (VPBROADCASTQYrr VR128:$src)>;
8021 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8022 (VBROADCASTSSrr VR128:$src)>;
8023 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8024 (VBROADCASTSSYrr VR128:$src)>;
8025 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8026 (VPBROADCASTQrr VR128:$src)>;
8027 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8028 (VBROADCASTSDYrr VR128:$src)>;
8030 // Provide fallback in case the load node that is used in the patterns above
8031 // is used by additional users, which prevents the pattern selection.
8032 let AddedComplexity = 20 in {
8033 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8034 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8035 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8036 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8037 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8038 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8040 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8041 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8042 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8043 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8044 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8045 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8049 // AVX1 broadcast patterns
8050 let Predicates = [HasAVX1Only] in {
8051 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8052 (VBROADCASTSSYrm addr:$src)>;
8053 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8054 (VBROADCASTSDYrm addr:$src)>;
8055 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8056 (VBROADCASTSSrm addr:$src)>;
8059 let Predicates = [HasAVX] in {
8060 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
8061 (VBROADCASTSSYrm addr:$src)>;
8062 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
8063 (VBROADCASTSDYrm addr:$src)>;
8064 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
8065 (VBROADCASTSSrm addr:$src)>;
8067 // Provide fallback in case the load node that is used in the patterns above
8068 // is used by additional users, which prevents the pattern selection.
8069 let AddedComplexity = 20 in {
8070 // 128bit broadcasts:
8071 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8072 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8073 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8074 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8075 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8076 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8077 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8078 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8079 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8080 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8082 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8083 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8084 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8085 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8086 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8087 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8088 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8089 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8090 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8091 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8095 //===----------------------------------------------------------------------===//
8096 // VPERM - Permute instructions
8099 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8101 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8102 (ins VR256:$src1, VR256:$src2),
8103 !strconcat(OpcodeStr,
8104 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8106 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8108 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8109 (ins VR256:$src1, i256mem:$src2),
8110 !strconcat(OpcodeStr,
8111 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8113 (OpVT (X86VPermv VR256:$src1,
8114 (bitconvert (mem_frag addr:$src2)))))]>,
8118 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
8119 let ExeDomain = SSEPackedSingle in
8120 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
8122 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8124 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8125 (ins VR256:$src1, i8imm:$src2),
8126 !strconcat(OpcodeStr,
8127 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8129 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8131 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8132 (ins i256mem:$src1, i8imm:$src2),
8133 !strconcat(OpcodeStr,
8134 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8136 (OpVT (X86VPermi (mem_frag addr:$src1),
8137 (i8 imm:$src2))))]>, VEX, VEX_L;
8140 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
8141 let ExeDomain = SSEPackedDouble in
8142 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
8144 //===----------------------------------------------------------------------===//
8145 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8147 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8148 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8149 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8150 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8151 (i8 imm:$src3))))]>, VEX_4V, VEX_L;
8152 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8153 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8154 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8155 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
8156 (i8 imm:$src3)))]>, VEX_4V, VEX_L;
8158 let Predicates = [HasAVX2] in {
8159 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8160 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8161 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8162 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8163 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8164 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8166 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
8168 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8169 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8170 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
8171 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8172 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
8174 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8178 //===----------------------------------------------------------------------===//
8179 // VINSERTI128 - Insert packed integer values
8181 let neverHasSideEffects = 1 in {
8182 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8183 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8184 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8187 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8188 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8189 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8193 let Predicates = [HasAVX2] in {
8194 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8196 (VINSERTI128rr VR256:$src1, VR128:$src2,
8197 (INSERT_get_vinsert128_imm VR256:$ins))>;
8198 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8200 (VINSERTI128rr VR256:$src1, VR128:$src2,
8201 (INSERT_get_vinsert128_imm VR256:$ins))>;
8202 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8204 (VINSERTI128rr VR256:$src1, VR128:$src2,
8205 (INSERT_get_vinsert128_imm VR256:$ins))>;
8206 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8208 (VINSERTI128rr VR256:$src1, VR128:$src2,
8209 (INSERT_get_vinsert128_imm VR256:$ins))>;
8211 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (memopv2i64 addr:$src2),
8213 (VINSERTI128rm VR256:$src1, addr:$src2,
8214 (INSERT_get_vinsert128_imm VR256:$ins))>;
8215 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8216 (bc_v4i32 (memopv2i64 addr:$src2)),
8218 (VINSERTI128rm VR256:$src1, addr:$src2,
8219 (INSERT_get_vinsert128_imm VR256:$ins))>;
8220 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8221 (bc_v16i8 (memopv2i64 addr:$src2)),
8223 (VINSERTI128rm VR256:$src1, addr:$src2,
8224 (INSERT_get_vinsert128_imm VR256:$ins))>;
8225 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8226 (bc_v8i16 (memopv2i64 addr:$src2)),
8228 (VINSERTI128rm VR256:$src1, addr:$src2,
8229 (INSERT_get_vinsert128_imm VR256:$ins))>;
8232 //===----------------------------------------------------------------------===//
8233 // VEXTRACTI128 - Extract packed integer values
8235 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8236 (ins VR256:$src1, i8imm:$src2),
8237 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8239 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8241 let neverHasSideEffects = 1, mayStore = 1 in
8242 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8243 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8244 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8247 let Predicates = [HasAVX2] in {
8248 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8249 (v2i64 (VEXTRACTI128rr
8250 (v4i64 VR256:$src1),
8251 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8252 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8253 (v4i32 (VEXTRACTI128rr
8254 (v8i32 VR256:$src1),
8255 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8256 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8257 (v8i16 (VEXTRACTI128rr
8258 (v16i16 VR256:$src1),
8259 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8260 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8261 (v16i8 (VEXTRACTI128rr
8262 (v32i8 VR256:$src1),
8263 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8265 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8266 (iPTR imm))), addr:$dst),
8267 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8268 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8269 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8270 (iPTR imm))), addr:$dst),
8271 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8272 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8273 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8274 (iPTR imm))), addr:$dst),
8275 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8276 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8277 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8278 (iPTR imm))), addr:$dst),
8279 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8280 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8283 //===----------------------------------------------------------------------===//
8284 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8286 multiclass avx2_pmovmask<string OpcodeStr,
8287 Intrinsic IntLd128, Intrinsic IntLd256,
8288 Intrinsic IntSt128, Intrinsic IntSt256> {
8289 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8290 (ins VR128:$src1, i128mem:$src2),
8291 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8292 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8293 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8294 (ins VR256:$src1, i256mem:$src2),
8295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8296 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8298 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8299 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8300 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8301 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8302 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8303 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8305 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8308 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8309 int_x86_avx2_maskload_d,
8310 int_x86_avx2_maskload_d_256,
8311 int_x86_avx2_maskstore_d,
8312 int_x86_avx2_maskstore_d_256>;
8313 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8314 int_x86_avx2_maskload_q,
8315 int_x86_avx2_maskload_q_256,
8316 int_x86_avx2_maskstore_q,
8317 int_x86_avx2_maskstore_q_256>, VEX_W;
8320 //===----------------------------------------------------------------------===//
8321 // Variable Bit Shifts
8323 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8324 ValueType vt128, ValueType vt256> {
8325 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8326 (ins VR128:$src1, VR128:$src2),
8327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8329 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8331 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8332 (ins VR128:$src1, i128mem:$src2),
8333 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8335 (vt128 (OpNode VR128:$src1,
8336 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8338 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8339 (ins VR256:$src1, VR256:$src2),
8340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8342 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8344 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8345 (ins VR256:$src1, i256mem:$src2),
8346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8348 (vt256 (OpNode VR256:$src1,
8349 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8353 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8354 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8355 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8356 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8357 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8359 //===----------------------------------------------------------------------===//
8360 // VGATHER - GATHER Operations
8361 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8362 X86MemOperand memop128, X86MemOperand memop256> {
8363 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8364 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8365 !strconcat(OpcodeStr,
8366 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8368 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8369 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8370 !strconcat(OpcodeStr,
8371 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8372 []>, VEX_4VOp3, VEX_L;
8375 let mayLoad = 1, Constraints
8376 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8378 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8379 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8380 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8381 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;
8382 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8383 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8384 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8385 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;