1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE scalar FP Instructions
19 //===----------------------------------------------------------------------===//
21 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
22 // instruction selection into a branch sequence.
23 let Uses = [EFLAGS], usesCustomInserter = 1 in {
24 def CMOV_FR32 : I<0, Pseudo,
25 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
27 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
29 def CMOV_FR64 : I<0, Pseudo,
30 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
32 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
34 def CMOV_V4F32 : I<0, Pseudo,
35 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
36 "#CMOV_V4F32 PSEUDO!",
38 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
40 def CMOV_V2F64 : I<0, Pseudo,
41 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
42 "#CMOV_V2F64 PSEUDO!",
44 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
46 def CMOV_V2I64 : I<0, Pseudo,
47 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
48 "#CMOV_V2I64 PSEUDO!",
50 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
54 //===----------------------------------------------------------------------===//
55 // SSE 1 & 2 Instructions Classes
56 //===----------------------------------------------------------------------===//
58 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
59 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 RegisterClass RC, X86MemOperand x86memop,
62 let isCommutable = 1 in {
63 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
65 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
66 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
67 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
69 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
71 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
72 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
73 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
76 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
77 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
78 string asm, string SSEVer, string FPSizeStr,
79 Operand memopr, ComplexPattern mem_cpat,
81 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
83 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
84 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
85 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
86 !strconcat(SSEVer, !strconcat("_",
87 !strconcat(OpcodeStr, FPSizeStr))))
88 RC:$src1, RC:$src2))]>;
89 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
91 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
92 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
93 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
94 !strconcat(SSEVer, !strconcat("_",
95 !strconcat(OpcodeStr, FPSizeStr))))
96 RC:$src1, mem_cpat:$src2))]>;
99 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
100 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
101 RegisterClass RC, ValueType vt,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 let isCommutable = 1 in
105 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
109 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
111 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
118 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
119 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
120 string OpcodeStr, X86MemOperand x86memop,
121 list<dag> pat_rr, list<dag> pat_rm,
123 let isCommutable = 1 in
124 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
129 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
131 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
132 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
136 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
137 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
138 string asm, string SSEVer, string FPSizeStr,
139 X86MemOperand x86memop, PatFrag mem_frag,
140 Domain d, bit Is2Addr = 1> {
141 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
143 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
144 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
145 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
146 !strconcat(SSEVer, !strconcat("_",
147 !strconcat(OpcodeStr, FPSizeStr))))
148 RC:$src1, RC:$src2))], d>;
149 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
151 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
152 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
153 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
154 !strconcat(SSEVer, !strconcat("_",
155 !strconcat(OpcodeStr, FPSizeStr))))
156 RC:$src1, (mem_frag addr:$src2)))], d>;
159 //===----------------------------------------------------------------------===//
160 // SSE 1 & 2 - Move Instructions
161 //===----------------------------------------------------------------------===//
163 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
164 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
165 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
167 // Loading from memory automatically zeroing upper bits.
168 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
169 PatFrag mem_pat, string OpcodeStr> :
170 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
172 [(set RC:$dst, (mem_pat addr:$src))]>;
174 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
175 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
176 // is used instead. Register-to-register movss/movsd is not modeled as an
177 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
178 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
179 let isAsmParserOnly = 1 in {
180 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
181 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
182 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
183 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
185 let canFoldAsLoad = 1, isReMaterializable = 1 in {
186 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
188 let AddedComplexity = 20 in
189 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
193 let Constraints = "$src1 = $dst" in {
194 def MOVSSrr : sse12_move_rr<FR32, v4f32,
195 "movss\t{$src2, $dst|$dst, $src2}">, XS;
196 def MOVSDrr : sse12_move_rr<FR64, v2f64,
197 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
200 let canFoldAsLoad = 1, isReMaterializable = 1 in {
201 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
203 let AddedComplexity = 20 in
204 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
207 let AddedComplexity = 15 in {
208 // Extract the low 32-bit value from one vector and insert it into another.
209 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
210 (MOVSSrr (v4f32 VR128:$src1),
211 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
212 // Extract the low 64-bit value from one vector and insert it into another.
213 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
214 (MOVSDrr (v2f64 VR128:$src1),
215 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
218 // Implicitly promote a 32-bit scalar to a vector.
219 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
220 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
221 // Implicitly promote a 64-bit scalar to a vector.
222 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
223 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
225 let AddedComplexity = 20 in {
226 // MOVSSrm zeros the high parts of the register; represent this
227 // with SUBREG_TO_REG.
228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
229 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
231 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
233 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
234 // MOVSDrm zeros the high parts of the register; represent this
235 // with SUBREG_TO_REG.
236 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
237 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
238 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
239 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
240 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
241 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
242 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
243 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
244 def : Pat<(v2f64 (X86vzload addr:$src)),
245 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
248 // Store scalar value to memory.
249 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
250 "movss\t{$src, $dst|$dst, $src}",
251 [(store FR32:$src, addr:$dst)]>;
252 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
253 "movsd\t{$src, $dst|$dst, $src}",
254 [(store FR64:$src, addr:$dst)]>;
256 let isAsmParserOnly = 1 in {
257 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
258 "movss\t{$src, $dst|$dst, $src}",
259 [(store FR32:$src, addr:$dst)]>, XS, VEX;
260 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
261 "movsd\t{$src, $dst|$dst, $src}",
262 [(store FR64:$src, addr:$dst)]>, XD, VEX;
265 // Extract and store.
266 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
270 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
273 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
275 // Move Aligned/Unaligned floating point values
276 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
277 X86MemOperand x86memop, PatFrag ld_frag,
278 string asm, Domain d,
279 bit IsReMaterializable = 1> {
280 let neverHasSideEffects = 1 in
281 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
282 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
283 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
284 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
285 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
286 [(set RC:$dst, (ld_frag addr:$src))], d>;
289 let isAsmParserOnly = 1 in {
290 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
291 "movaps", SSEPackedSingle>, VEX;
292 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
293 "movapd", SSEPackedDouble>, OpSize, VEX;
294 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
295 "movups", SSEPackedSingle>, VEX;
296 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
297 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
299 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
300 "movaps", SSEPackedSingle>, VEX;
301 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
302 "movapd", SSEPackedDouble>, OpSize, VEX;
303 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
304 "movups", SSEPackedSingle>, VEX;
305 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
306 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
308 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
309 "movaps", SSEPackedSingle>, TB;
310 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
311 "movapd", SSEPackedDouble>, TB, OpSize;
312 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
313 "movups", SSEPackedSingle>, TB;
314 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
315 "movupd", SSEPackedDouble, 0>, TB, OpSize;
317 let isAsmParserOnly = 1 in {
318 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movaps\t{$src, $dst|$dst, $src}",
320 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
321 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
322 "movapd\t{$src, $dst|$dst, $src}",
323 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
324 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
327 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
328 "movupd\t{$src, $dst|$dst, $src}",
329 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
330 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
331 "movaps\t{$src, $dst|$dst, $src}",
332 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
333 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
334 "movapd\t{$src, $dst|$dst, $src}",
335 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
337 "movups\t{$src, $dst|$dst, $src}",
338 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
339 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
340 "movupd\t{$src, $dst|$dst, $src}",
341 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
343 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
344 "movaps\t{$src, $dst|$dst, $src}",
345 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
346 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
347 "movapd\t{$src, $dst|$dst, $src}",
348 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
349 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
350 "movups\t{$src, $dst|$dst, $src}",
351 [(store (v4f32 VR128:$src), addr:$dst)]>;
352 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
353 "movupd\t{$src, $dst|$dst, $src}",
354 [(store (v2f64 VR128:$src), addr:$dst)]>;
356 // Intrinsic forms of MOVUPS/D load and store
357 let isAsmParserOnly = 1 in {
358 let canFoldAsLoad = 1, isReMaterializable = 1 in
359 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
361 "movups\t{$src, $dst|$dst, $src}",
362 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
363 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
365 "movupd\t{$src, $dst|$dst, $src}",
366 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
367 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
368 (ins f128mem:$dst, VR128:$src),
369 "movups\t{$src, $dst|$dst, $src}",
370 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
371 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
372 (ins f128mem:$dst, VR128:$src),
373 "movupd\t{$src, $dst|$dst, $src}",
374 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
376 let canFoldAsLoad = 1, isReMaterializable = 1 in
377 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
378 "movups\t{$src, $dst|$dst, $src}",
379 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
380 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
381 "movupd\t{$src, $dst|$dst, $src}",
382 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
384 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
385 "movups\t{$src, $dst|$dst, $src}",
386 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
387 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
388 "movupd\t{$src, $dst|$dst, $src}",
389 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
391 // Move Low/High packed floating point values
392 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
393 PatFrag mov_frag, string base_opc,
395 def PSrm : PI<opc, MRMSrcMem,
396 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
397 !strconcat(!strconcat(base_opc,"s"), asm_opr),
400 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
401 SSEPackedSingle>, TB;
403 def PDrm : PI<opc, MRMSrcMem,
404 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
405 !strconcat(!strconcat(base_opc,"d"), asm_opr),
406 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
407 (scalar_to_vector (loadf64 addr:$src2)))))],
408 SSEPackedDouble>, TB, OpSize;
411 let isAsmParserOnly = 1, AddedComplexity = 20 in {
412 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
413 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
414 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
417 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
418 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
419 "\t{$src2, $dst|$dst, $src2}">;
420 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
421 "\t{$src2, $dst|$dst, $src2}">;
424 let isAsmParserOnly = 1 in {
425 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
426 "movlps\t{$src, $dst|$dst, $src}",
427 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
428 (iPTR 0))), addr:$dst)]>, VEX;
429 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
430 "movlpd\t{$src, $dst|$dst, $src}",
431 [(store (f64 (vector_extract (v2f64 VR128:$src),
432 (iPTR 0))), addr:$dst)]>, VEX;
434 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
435 "movlps\t{$src, $dst|$dst, $src}",
436 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
437 (iPTR 0))), addr:$dst)]>;
438 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movlpd\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract (v2f64 VR128:$src),
441 (iPTR 0))), addr:$dst)]>;
443 // v2f64 extract element 1 is always custom lowered to unpack high to low
444 // and extract element 0 so the non-store version isn't too horrible.
445 let isAsmParserOnly = 1 in {
446 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
447 "movhps\t{$src, $dst|$dst, $src}",
448 [(store (f64 (vector_extract
449 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
450 (undef)), (iPTR 0))), addr:$dst)]>,
452 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
453 "movhpd\t{$src, $dst|$dst, $src}",
454 [(store (f64 (vector_extract
455 (v2f64 (unpckh VR128:$src, (undef))),
456 (iPTR 0))), addr:$dst)]>,
459 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
460 "movhps\t{$src, $dst|$dst, $src}",
461 [(store (f64 (vector_extract
462 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
463 (undef)), (iPTR 0))), addr:$dst)]>;
464 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
465 "movhpd\t{$src, $dst|$dst, $src}",
466 [(store (f64 (vector_extract
467 (v2f64 (unpckh VR128:$src, (undef))),
468 (iPTR 0))), addr:$dst)]>;
470 let isAsmParserOnly = 1, AddedComplexity = 20 in {
471 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
472 (ins VR128:$src1, VR128:$src2),
473 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
475 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
477 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
478 (ins VR128:$src1, VR128:$src2),
479 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
481 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
484 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
485 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
486 (ins VR128:$src1, VR128:$src2),
487 "movlhps\t{$src2, $dst|$dst, $src2}",
489 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
490 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
491 (ins VR128:$src1, VR128:$src2),
492 "movhlps\t{$src2, $dst|$dst, $src2}",
494 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
497 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
498 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
499 let AddedComplexity = 20 in {
500 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
501 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
502 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
503 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
506 //===----------------------------------------------------------------------===//
507 // SSE 1 & 2 - Conversion Instructions
508 //===----------------------------------------------------------------------===//
510 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
511 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
513 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
514 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
515 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
516 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
519 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
520 X86MemOperand x86memop, string asm> {
521 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
523 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
527 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
528 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
529 string asm, Domain d> {
530 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
531 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
532 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
533 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
536 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
537 X86MemOperand x86memop, string asm> {
538 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
539 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
540 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
541 (ins DstRC:$src1, x86memop:$src),
542 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
545 let isAsmParserOnly = 1 in {
546 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
547 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
548 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
549 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
551 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
552 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
553 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
554 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
557 // The assembler can recognize rr 64-bit instructions by seeing a rxx
558 // register, but the same isn't true when only using memory operands,
559 // provide other assembly "l" and "q" forms to address this explicitly
560 // where appropriate to do so.
561 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
563 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
565 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
567 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
569 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
573 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
574 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
575 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
576 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
577 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
578 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
579 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
580 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
581 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
582 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
583 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
584 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
585 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
586 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
587 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
588 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
590 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
591 // and/or XMM operand(s).
592 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
593 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
594 string asm, Domain d> {
595 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
596 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
597 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
598 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
601 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
602 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
605 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
606 [(set DstRC:$dst, (Int SrcRC:$src))]>;
607 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
608 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
609 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
612 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
613 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
614 PatFrag ld_frag, string asm, Domain d> {
615 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
616 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
617 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
618 (ins DstRC:$src1, x86memop:$src2), asm,
619 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
622 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
623 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
624 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
625 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
627 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
628 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
629 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
630 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
631 (ins DstRC:$src1, x86memop:$src2),
633 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
634 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
635 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
638 let isAsmParserOnly = 1 in {
639 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
640 f32mem, load, "cvtss2si">, XS, VEX;
641 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
642 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
644 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
645 f128mem, load, "cvtsd2si">, XD, VEX;
646 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
647 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
650 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
651 // Get rid of this hack or rename the intrinsics, there are several
652 // intructions that only match with the intrinsic form, why create duplicates
653 // to let them be recognized by the assembler?
654 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
655 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
656 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
657 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
659 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
660 f32mem, load, "cvtss2si">, XS;
661 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
662 f32mem, load, "cvtss2si{q}">, XS, REX_W;
663 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
664 f128mem, load, "cvtsd2si">, XD;
665 defm Int_CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
666 f128mem, load, "cvtsd2si">, XD, REX_W;
668 defm CVTSD2SI64 : sse12_cvt_s_np<0x2D, VR128, GR64, f64mem, "cvtsd2si{q}">, XD,
671 let isAsmParserOnly = 1 in {
672 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
673 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
674 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
675 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
677 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
678 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
679 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
680 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
684 let Constraints = "$src1 = $dst" in {
685 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
686 int_x86_sse_cvtsi2ss, i32mem, loadi32,
688 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
689 int_x86_sse_cvtsi642ss, i64mem, loadi64,
690 "cvtsi2ss{q}">, XS, REX_W;
691 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
692 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
694 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
695 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
696 "cvtsi2sd">, XD, REX_W;
699 // Instructions below don't have an AVX form.
700 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
701 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
702 SSEPackedSingle>, TB;
703 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
704 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
705 SSEPackedDouble>, TB, OpSize;
706 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
707 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
708 SSEPackedSingle>, TB;
709 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
710 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
711 SSEPackedDouble>, TB, OpSize;
712 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
713 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
714 SSEPackedDouble>, TB, OpSize;
715 let Constraints = "$src1 = $dst" in {
716 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
717 int_x86_sse_cvtpi2ps,
718 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
719 SSEPackedSingle>, TB;
724 // Aliases for intrinsics
725 let isAsmParserOnly = 1 in {
726 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
727 f32mem, load, "cvttss2si">, XS, VEX;
728 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
729 int_x86_sse_cvttss2si64, f32mem, load,
730 "cvttss2si">, XS, VEX, VEX_W;
731 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
732 f128mem, load, "cvttss2si">, XD, VEX;
733 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
734 int_x86_sse2_cvttsd2si64, f128mem, load,
735 "cvttss2si">, XD, VEX, VEX_W;
737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
738 f32mem, load, "cvttss2si">, XS;
739 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
740 int_x86_sse_cvttss2si64, f32mem, load,
741 "cvttss2si{q}">, XS, REX_W;
742 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
743 f128mem, load, "cvttss2si">, XD;
744 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
745 int_x86_sse2_cvttsd2si64, f128mem, load,
746 "cvttss2si{q}">, XD, REX_W;
748 let isAsmParserOnly = 1, Pattern = []<dag> in {
749 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
750 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
751 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
752 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
754 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
755 "cvtdq2ps\t{$src, $dst|$dst, $src}",
756 SSEPackedSingle>, TB, VEX;
757 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, f256mem, load,
758 "cvtdq2ps\t{$src, $dst|$dst, $src}",
759 SSEPackedSingle>, TB, VEX;
761 let Pattern = []<dag> in {
762 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
763 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
764 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
765 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
766 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
767 "cvtdq2ps\t{$src, $dst|$dst, $src}",
768 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
773 // Convert scalar double to scalar single
774 let isAsmParserOnly = 1 in {
775 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
776 (ins FR64:$src1, FR64:$src2),
777 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
779 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
780 (ins FR64:$src1, f64mem:$src2),
781 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
782 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
784 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
785 "cvtsd2ss\t{$src, $dst|$dst, $src}",
786 [(set FR32:$dst, (fround FR64:$src))]>;
787 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
788 "cvtsd2ss\t{$src, $dst|$dst, $src}",
789 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
790 Requires<[HasSSE2, OptForSize]>;
792 let isAsmParserOnly = 1 in
793 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
794 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
796 let Constraints = "$src1 = $dst" in
797 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
798 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
800 // Convert scalar single to scalar double
801 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
802 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
803 (ins FR32:$src1, FR32:$src2),
804 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
805 []>, XS, Requires<[HasAVX]>, VEX_4V;
806 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
807 (ins FR32:$src1, f32mem:$src2),
808 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
809 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
811 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
812 "cvtss2sd\t{$src, $dst|$dst, $src}",
813 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
815 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
816 "cvtss2sd\t{$src, $dst|$dst, $src}",
817 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
818 Requires<[HasSSE2, OptForSize]>;
820 let isAsmParserOnly = 1 in {
821 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
822 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
823 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
824 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
825 VR128:$src2))]>, XS, VEX_4V,
827 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
828 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
829 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
830 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
831 (load addr:$src2)))]>, XS, VEX_4V,
834 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
835 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
836 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
837 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
838 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
841 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
842 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
843 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
844 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
845 (load addr:$src2)))]>, XS,
849 def : Pat<(extloadf32 addr:$src),
850 (CVTSS2SDrr (MOVSSrm addr:$src))>,
851 Requires<[HasSSE2, OptForSpeed]>;
853 // Convert doubleword to packed single/double fp
854 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
855 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
856 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
857 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
858 TB, VEX, Requires<[HasAVX]>;
859 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
860 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
861 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
862 (bitconvert (memopv2i64 addr:$src))))]>,
863 TB, VEX, Requires<[HasAVX]>;
865 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
866 "cvtdq2ps\t{$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
868 TB, Requires<[HasSSE2]>;
869 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
870 "cvtdq2ps\t{$src, $dst|$dst, $src}",
871 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
872 (bitconvert (memopv2i64 addr:$src))))]>,
873 TB, Requires<[HasSSE2]>;
875 // FIXME: why the non-intrinsic version is described as SSE3?
876 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
877 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
878 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
880 XS, VEX, Requires<[HasAVX]>;
881 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
882 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
884 (bitconvert (memopv2i64 addr:$src))))]>,
885 XS, VEX, Requires<[HasAVX]>;
887 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
888 "cvtdq2pd\t{$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
890 XS, Requires<[HasSSE2]>;
891 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
892 "cvtdq2pd\t{$src, $dst|$dst, $src}",
893 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
894 (bitconvert (memopv2i64 addr:$src))))]>,
895 XS, Requires<[HasSSE2]>;
897 // Convert packed single/double fp to doubleword
898 let isAsmParserOnly = 1 in {
899 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
900 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
901 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
903 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
904 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
905 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
906 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
908 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
909 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
910 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
913 let isAsmParserOnly = 1 in {
914 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
915 "cvtps2dq\t{$src, $dst|$dst, $src}",
916 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
918 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
920 "cvtps2dq\t{$src, $dst|$dst, $src}",
921 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
922 (memop addr:$src)))]>, VEX;
924 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
925 "cvtps2dq\t{$src, $dst|$dst, $src}",
926 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
927 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
928 "cvtps2dq\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
930 (memop addr:$src)))]>;
932 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
933 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
934 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
936 XD, VEX, Requires<[HasAVX]>;
937 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
938 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
939 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
940 (memop addr:$src)))]>,
941 XD, VEX, Requires<[HasAVX]>;
943 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
944 "cvtpd2dq\t{$src, $dst|$dst, $src}",
945 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
946 XD, Requires<[HasSSE2]>;
947 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
948 "cvtpd2dq\t{$src, $dst|$dst, $src}",
949 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
950 (memop addr:$src)))]>,
951 XD, Requires<[HasSSE2]>;
954 // Convert with truncation packed single/double fp to doubleword
955 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
956 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
960 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
961 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
963 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
965 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
966 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
967 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
968 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
971 let isAsmParserOnly = 1 in {
972 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "vcvttps2dq\t{$src, $dst|$dst, $src}",
975 (int_x86_sse2_cvttps2dq VR128:$src))]>,
976 XS, VEX, Requires<[HasAVX]>;
977 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
978 "vcvttps2dq\t{$src, $dst|$dst, $src}",
979 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
980 (memop addr:$src)))]>,
981 XS, VEX, Requires<[HasAVX]>;
983 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
984 "cvttps2dq\t{$src, $dst|$dst, $src}",
986 (int_x86_sse2_cvttps2dq VR128:$src))]>,
987 XS, Requires<[HasSSE2]>;
988 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
989 "cvttps2dq\t{$src, $dst|$dst, $src}",
990 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
991 (memop addr:$src)))]>,
992 XS, Requires<[HasSSE2]>;
994 let isAsmParserOnly = 1 in {
995 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
997 "cvttpd2dq\t{$src, $dst|$dst, $src}",
998 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1000 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1002 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1003 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1004 (memop addr:$src)))]>, VEX;
1006 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1007 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1008 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1009 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1010 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1011 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1012 (memop addr:$src)))]>;
1014 let isAsmParserOnly = 1 in {
1015 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1016 // register, but the same isn't true when using memory operands instead.
1017 // Provide other assembly rr and rm forms to address this explicitly.
1018 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1019 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1020 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1021 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1024 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1025 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1026 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1027 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1030 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1031 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1032 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1033 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1036 // Convert packed single to packed double
1037 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1038 // SSE2 instructions without OpSize prefix
1039 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1040 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1041 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1042 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1043 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1044 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1045 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1046 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1048 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1049 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1050 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1051 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1053 let isAsmParserOnly = 1 in {
1054 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1055 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1056 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1057 VEX, Requires<[HasAVX]>;
1058 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1059 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1060 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1061 (load addr:$src)))]>,
1062 VEX, Requires<[HasAVX]>;
1064 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1065 "cvtps2pd\t{$src, $dst|$dst, $src}",
1066 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1067 TB, Requires<[HasSSE2]>;
1068 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1069 "cvtps2pd\t{$src, $dst|$dst, $src}",
1070 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1071 (load addr:$src)))]>,
1072 TB, Requires<[HasSSE2]>;
1074 // Convert packed double to packed single
1075 let isAsmParserOnly = 1 in {
1076 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1077 // register, but the same isn't true when using memory operands instead.
1078 // Provide other assembly rr and rm forms to address this explicitly.
1079 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1080 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1081 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1082 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1085 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1086 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1087 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1088 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1091 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1092 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1093 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1094 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1096 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1097 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1098 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1099 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1102 let isAsmParserOnly = 1 in {
1103 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1104 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1105 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1106 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1110 (memop addr:$src)))]>;
1112 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1113 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1114 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1115 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1116 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1117 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1118 (memop addr:$src)))]>;
1120 //===----------------------------------------------------------------------===//
1121 // SSE 1 & 2 - Compare Instructions
1122 //===----------------------------------------------------------------------===//
1124 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1125 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1126 string asm, string asm_alt> {
1127 def rr : SIi8<0xC2, MRMSrcReg,
1128 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1131 def rm : SIi8<0xC2, MRMSrcMem,
1132 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1134 // Accept explicit immediate argument form instead of comparison code.
1135 let isAsmParserOnly = 1 in {
1136 def rr_alt : SIi8<0xC2, MRMSrcReg,
1137 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1140 def rm_alt : SIi8<0xC2, MRMSrcMem,
1141 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1146 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1147 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1148 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1149 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1151 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1152 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1153 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1157 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1158 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1159 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1160 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1161 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1162 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1163 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1166 multiclass sse12_cmp_scalar_int<RegisterClass RC, Operand memopr,
1167 ComplexPattern mem_cpat, Intrinsic Int, string asm> {
1168 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1169 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1170 [(set VR128:$dst, (Int VR128:$src1,
1171 VR128:$src, imm:$cc))]>;
1172 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1173 (ins VR128:$src1, memopr:$src, SSECC:$cc), asm,
1174 [(set VR128:$dst, (Int VR128:$src1,
1175 mem_cpat:$src, imm:$cc))]>;
1178 // Aliases to match intrinsics which expect XMM operand(s).
1180 let isAsmParserOnly = 1 in {
1181 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, ssmem, sse_load_f32,
1183 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1185 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, sdmem, sse_load_f64,
1186 int_x86_sse2_cmp_sd,
1187 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1190 let Constraints = "$src1 = $dst" in {
1191 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, ssmem, sse_load_f32,
1193 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1194 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, sdmem, sse_load_f64,
1195 int_x86_sse2_cmp_sd,
1196 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1200 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1201 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1202 ValueType vt, X86MemOperand x86memop,
1203 PatFrag ld_frag, string OpcodeStr, Domain d> {
1204 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1205 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1206 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1207 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1208 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1209 [(set EFLAGS, (OpNode (vt RC:$src1),
1210 (ld_frag addr:$src2)))], d>;
1213 let Defs = [EFLAGS] in {
1214 let isAsmParserOnly = 1 in {
1215 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1216 "ucomiss", SSEPackedSingle>, VEX;
1217 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1218 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1219 let Pattern = []<dag> in {
1220 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1221 "comiss", SSEPackedSingle>, VEX;
1222 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1223 "comisd", SSEPackedDouble>, OpSize, VEX;
1226 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1227 load, "ucomiss", SSEPackedSingle>, VEX;
1228 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1229 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1231 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1232 load, "comiss", SSEPackedSingle>, VEX;
1233 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1234 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1236 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1237 "ucomiss", SSEPackedSingle>, TB;
1238 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1239 "ucomisd", SSEPackedDouble>, TB, OpSize;
1241 let Pattern = []<dag> in {
1242 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1243 "comiss", SSEPackedSingle>, TB;
1244 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1245 "comisd", SSEPackedDouble>, TB, OpSize;
1248 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1249 load, "ucomiss", SSEPackedSingle>, TB;
1250 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1251 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1253 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1254 "comiss", SSEPackedSingle>, TB;
1255 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1256 "comisd", SSEPackedDouble>, TB, OpSize;
1257 } // Defs = [EFLAGS]
1259 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1260 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1261 Intrinsic Int, string asm, string asm_alt,
1263 def rri : PIi8<0xC2, MRMSrcReg,
1264 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1265 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1266 def rmi : PIi8<0xC2, MRMSrcMem,
1267 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1268 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1269 // Accept explicit immediate argument form instead of comparison code.
1270 let isAsmParserOnly = 1 in {
1271 def rri_alt : PIi8<0xC2, MRMSrcReg,
1272 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1274 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1275 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1280 let isAsmParserOnly = 1 in {
1281 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1282 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1283 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1284 SSEPackedSingle>, VEX_4V;
1285 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1286 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1287 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1288 SSEPackedDouble>, OpSize, VEX_4V;
1289 let Pattern = []<dag> in {
1290 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_sse_cmp_ps,
1291 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1292 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1293 SSEPackedSingle>, VEX_4V;
1294 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_sse2_cmp_pd,
1295 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1296 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1297 SSEPackedDouble>, OpSize, VEX_4V;
1300 let Constraints = "$src1 = $dst" in {
1301 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1302 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1303 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1304 SSEPackedSingle>, TB;
1305 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1306 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1307 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1308 SSEPackedDouble>, TB, OpSize;
1311 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1312 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1313 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1314 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1315 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1316 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1317 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1318 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Shuffle Instructions
1322 //===----------------------------------------------------------------------===//
1324 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1325 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1326 ValueType vt, string asm, PatFrag mem_frag,
1327 Domain d, bit IsConvertibleToThreeAddress = 0> {
1328 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1329 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1330 [(set RC:$dst, (vt (shufp:$src3
1331 RC:$src1, (mem_frag addr:$src2))))], d>;
1332 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1333 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1334 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1336 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1339 let isAsmParserOnly = 1 in {
1340 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1341 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1342 memopv4f32, SSEPackedSingle>, VEX_4V;
1343 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1344 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1345 memopv8f32, SSEPackedSingle>, VEX_4V;
1346 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1347 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1348 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1349 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1350 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1351 memopv4f64, SSEPackedDouble>, OpSize, VEX_4V;
1354 let Constraints = "$src1 = $dst" in {
1355 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1356 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1357 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1359 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1360 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1361 memopv2f64, SSEPackedDouble>, TB, OpSize;
1364 //===----------------------------------------------------------------------===//
1365 // SSE 1 & 2 - Unpack Instructions
1366 //===----------------------------------------------------------------------===//
1368 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1369 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1370 PatFrag mem_frag, RegisterClass RC,
1371 X86MemOperand x86memop, string asm,
1373 def rr : PI<opc, MRMSrcReg,
1374 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1376 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1377 def rm : PI<opc, MRMSrcMem,
1378 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1380 (vt (OpNode RC:$src1,
1381 (mem_frag addr:$src2))))], d>;
1384 let AddedComplexity = 10 in {
1385 let isAsmParserOnly = 1 in {
1386 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1387 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1388 SSEPackedSingle>, VEX_4V;
1389 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1390 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1391 SSEPackedDouble>, OpSize, VEX_4V;
1392 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1393 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1394 SSEPackedSingle>, VEX_4V;
1395 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1396 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1397 SSEPackedDouble>, OpSize, VEX_4V;
1399 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1400 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1401 SSEPackedSingle>, VEX_4V;
1402 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1403 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1404 SSEPackedDouble>, OpSize, VEX_4V;
1405 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1406 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1407 SSEPackedSingle>, VEX_4V;
1408 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1409 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1410 SSEPackedDouble>, OpSize, VEX_4V;
1413 let Constraints = "$src1 = $dst" in {
1414 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1415 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1416 SSEPackedSingle>, TB;
1417 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1418 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1419 SSEPackedDouble>, TB, OpSize;
1420 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1421 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1422 SSEPackedSingle>, TB;
1423 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1424 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1425 SSEPackedDouble>, TB, OpSize;
1426 } // Constraints = "$src1 = $dst"
1427 } // AddedComplexity
1429 //===----------------------------------------------------------------------===//
1430 // SSE 1 & 2 - Extract Floating-Point Sign mask
1431 //===----------------------------------------------------------------------===//
1433 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1434 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1436 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1437 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1438 [(set GR32:$dst, (Int RC:$src))], d>;
1442 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1443 SSEPackedSingle>, TB;
1444 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1445 SSEPackedDouble>, TB, OpSize;
1447 let isAsmParserOnly = 1 in {
1448 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1449 "movmskps", SSEPackedSingle>, VEX;
1450 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1451 "movmskpd", SSEPackedDouble>, OpSize,
1454 // FIXME: merge with multiclass above when the intrinsics come.
1455 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1456 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1457 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1458 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1461 def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1462 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1463 def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1464 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1467 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1468 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1469 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1470 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1474 //===----------------------------------------------------------------------===//
1475 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1476 //===----------------------------------------------------------------------===//
1478 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1479 // names that start with 'Fs'.
1481 // Alias instructions that map fld0 to pxor for sse.
1482 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1483 canFoldAsLoad = 1 in {
1484 // FIXME: Set encoding to pseudo!
1485 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1486 [(set FR32:$dst, fp32imm0)]>,
1487 Requires<[HasSSE1]>, TB, OpSize;
1488 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1489 [(set FR64:$dst, fpimm0)]>,
1490 Requires<[HasSSE2]>, TB, OpSize;
1493 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1494 // bits are disregarded.
1495 let neverHasSideEffects = 1 in {
1496 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1497 "movaps\t{$src, $dst|$dst, $src}", []>;
1498 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1499 "movapd\t{$src, $dst|$dst, $src}", []>;
1502 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1503 // bits are disregarded.
1504 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1505 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1506 "movaps\t{$src, $dst|$dst, $src}",
1507 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1508 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1509 "movapd\t{$src, $dst|$dst, $src}",
1510 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1513 //===----------------------------------------------------------------------===//
1514 // SSE 1 & 2 - Logical Instructions
1515 //===----------------------------------------------------------------------===//
1517 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1519 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1521 let isAsmParserOnly = 1 in {
1522 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1523 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1525 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1526 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1529 let Constraints = "$src1 = $dst" in {
1530 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1531 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1533 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1534 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1538 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1539 let mayLoad = 0 in {
1540 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1541 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1542 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1545 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1546 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1548 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1550 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1551 SDNode OpNode, int HasPat = 0,
1552 list<list<dag>> Pattern = []> {
1553 let isAsmParserOnly = 1, Pattern = []<dag> in {
1554 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1555 !strconcat(OpcodeStr, "ps"), f128mem,
1556 !if(HasPat, Pattern[0], // rr
1557 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1559 !if(HasPat, Pattern[2], // rm
1560 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1561 (memopv2i64 addr:$src2)))]), 0>,
1564 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1565 !strconcat(OpcodeStr, "pd"), f128mem,
1566 !if(HasPat, Pattern[1], // rr
1567 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1570 !if(HasPat, Pattern[3], // rm
1571 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1572 (memopv2i64 addr:$src2)))]), 0>,
1575 let Constraints = "$src1 = $dst" in {
1576 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1577 !strconcat(OpcodeStr, "ps"), f128mem,
1578 !if(HasPat, Pattern[0], // rr
1579 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1581 !if(HasPat, Pattern[2], // rm
1582 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1583 (memopv2i64 addr:$src2)))])>, TB;
1585 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1586 !strconcat(OpcodeStr, "pd"), f128mem,
1587 !if(HasPat, Pattern[1], // rr
1588 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1591 !if(HasPat, Pattern[3], // rm
1592 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1593 (memopv2i64 addr:$src2)))])>,
1598 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1600 let isAsmParserOnly = 1 in {
1601 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1602 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1603 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1605 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1606 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1610 // AVX 256-bit packed logical ops forms
1611 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1612 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1613 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1614 let isCommutable = 0 in
1615 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1617 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1618 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1619 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1620 let isCommutable = 0 in
1621 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1623 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1624 (bc_v2i64 (v4i32 immAllOnesV))),
1627 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1628 (bc_v2i64 (v2f64 VR128:$src2))))],
1630 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1631 (bc_v2i64 (v4i32 immAllOnesV))),
1632 (memopv2i64 addr:$src2))))],
1634 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1635 (memopv2i64 addr:$src2)))]]>;
1637 //===----------------------------------------------------------------------===//
1638 // SSE 1 & 2 - Arithmetic Instructions
1639 //===----------------------------------------------------------------------===//
1641 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1644 /// In addition, we also have a special variant of the scalar form here to
1645 /// represent the associated intrinsic operation. This form is unlike the
1646 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1647 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1649 /// These three forms can each be reg+reg or reg+mem.
1652 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1654 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1656 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1657 OpNode, FR32, f32mem, Is2Addr>, XS;
1658 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1659 OpNode, FR64, f64mem, Is2Addr>, XD;
1662 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1664 let mayLoad = 0 in {
1665 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1666 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1667 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1668 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1672 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1674 let mayLoad = 0 in {
1675 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1676 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1677 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1678 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1682 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1684 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1685 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1686 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1687 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1690 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1692 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1693 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1694 SSEPackedSingle, Is2Addr>, TB;
1696 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1697 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1698 SSEPackedDouble, Is2Addr>, TB, OpSize;
1701 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1702 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1703 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1704 SSEPackedSingle, 0>, TB;
1706 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1707 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1708 SSEPackedDouble, 0>, TB, OpSize;
1711 // Binary Arithmetic instructions
1712 let isAsmParserOnly = 1 in {
1713 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1714 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1715 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1716 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1717 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1718 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1719 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1720 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1722 let isCommutable = 0 in {
1723 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1724 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1725 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1726 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1727 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1728 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1729 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1730 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1731 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1732 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1733 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1734 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1735 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1736 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1737 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1738 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1739 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1740 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1741 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1742 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1746 let Constraints = "$src1 = $dst" in {
1747 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1748 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1749 basic_sse12_fp_binop_s_int<0x58, "add">;
1750 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1751 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1752 basic_sse12_fp_binop_s_int<0x59, "mul">;
1754 let isCommutable = 0 in {
1755 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1756 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1757 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1758 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1759 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1760 basic_sse12_fp_binop_s_int<0x5E, "div">;
1761 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1762 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1763 basic_sse12_fp_binop_s_int<0x5F, "max">,
1764 basic_sse12_fp_binop_p_int<0x5F, "max">;
1765 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1766 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1767 basic_sse12_fp_binop_s_int<0x5D, "min">,
1768 basic_sse12_fp_binop_p_int<0x5D, "min">;
1773 /// In addition, we also have a special variant of the scalar form here to
1774 /// represent the associated intrinsic operation. This form is unlike the
1775 /// plain scalar form, in that it takes an entire vector (instead of a
1776 /// scalar) and leaves the top elements undefined.
1778 /// And, we have a special variant form for a full-vector intrinsic form.
1780 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1781 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1782 SDNode OpNode, Intrinsic F32Int> {
1783 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1784 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1785 [(set FR32:$dst, (OpNode FR32:$src))]>;
1786 // For scalar unary operations, fold a load into the operation
1787 // only in OptForSize mode. It eliminates an instruction, but it also
1788 // eliminates a whole-register clobber (the load), so it introduces a
1789 // partial register update condition.
1790 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1791 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1792 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1793 Requires<[HasSSE1, OptForSize]>;
1794 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1795 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1796 [(set VR128:$dst, (F32Int VR128:$src))]>;
1797 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1798 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1799 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1802 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1803 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1804 SDNode OpNode, Intrinsic F32Int> {
1805 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1806 !strconcat(OpcodeStr,
1807 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1808 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1809 !strconcat(OpcodeStr,
1810 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1811 []>, XS, Requires<[HasAVX, OptForSize]>;
1812 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1813 !strconcat(OpcodeStr,
1814 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1815 [(set VR128:$dst, (F32Int VR128:$src))]>;
1816 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1817 !strconcat(OpcodeStr,
1818 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1819 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1822 /// sse1_fp_unop_p - SSE1 unops in packed form.
1823 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1824 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1825 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1826 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1827 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1828 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1829 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1832 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1833 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1834 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1835 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1836 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1837 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1838 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1839 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1842 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1843 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1844 Intrinsic V4F32Int> {
1845 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1846 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1847 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1848 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1849 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1850 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1853 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1854 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1855 Intrinsic V4F32Int> {
1856 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1857 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1858 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1859 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1860 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1861 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1864 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1865 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1866 SDNode OpNode, Intrinsic F64Int> {
1867 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1868 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1869 [(set FR64:$dst, (OpNode FR64:$src))]>;
1870 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1871 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1872 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1873 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1874 Requires<[HasSSE2, OptForSize]>;
1875 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1876 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1877 [(set VR128:$dst, (F64Int VR128:$src))]>;
1878 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1879 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1880 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1883 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1884 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1885 SDNode OpNode, Intrinsic F64Int> {
1886 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1887 !strconcat(OpcodeStr,
1888 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1889 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1890 (ins FR64:$src1, f64mem:$src2),
1891 !strconcat(OpcodeStr,
1892 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1893 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1894 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1895 [(set VR128:$dst, (F64Int VR128:$src))]>;
1896 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1897 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1898 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1901 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1902 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1904 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1905 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1906 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1907 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1908 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1909 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1912 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1913 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1914 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1915 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1916 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1917 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1918 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1919 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1922 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1923 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1924 Intrinsic V2F64Int> {
1925 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1926 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1927 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1928 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1929 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1930 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1933 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1934 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1935 Intrinsic V2F64Int> {
1936 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1937 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1938 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1939 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1940 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1941 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1944 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1946 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1947 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1950 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1951 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1952 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1953 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1954 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1955 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1956 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1957 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1960 // Reciprocal approximations. Note that these typically require refinement
1961 // in order to obtain suitable precision.
1962 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1963 int_x86_sse_rsqrt_ss>, VEX_4V;
1964 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1965 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1966 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1967 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1969 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1971 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1972 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1973 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1974 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1978 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1979 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1980 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1981 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1982 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1983 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1985 // Reciprocal approximations. Note that these typically require refinement
1986 // in order to obtain suitable precision.
1987 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1988 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1989 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1990 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1991 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1992 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1994 // There is no f64 version of the reciprocal approximation instructions.
1996 //===----------------------------------------------------------------------===//
1997 // SSE 1 & 2 - Non-temporal stores
1998 //===----------------------------------------------------------------------===//
2000 let isAsmParserOnly = 1 in {
2001 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
2002 (ins i128mem:$dst, VR128:$src),
2003 "movntps\t{$src, $dst|$dst, $src}",
2004 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
2005 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
2006 (ins i128mem:$dst, VR128:$src),
2007 "movntpd\t{$src, $dst|$dst, $src}",
2008 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
2010 let ExeDomain = SSEPackedInt in
2011 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
2012 (ins f128mem:$dst, VR128:$src),
2013 "movntdq\t{$src, $dst|$dst, $src}",
2014 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
2016 let AddedComplexity = 400 in { // Prefer non-temporal versions
2017 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2018 (ins f128mem:$dst, VR128:$src),
2019 "movntps\t{$src, $dst|$dst, $src}",
2020 [(alignednontemporalstore (v4f32 VR128:$src),
2022 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2023 (ins f128mem:$dst, VR128:$src),
2024 "movntpd\t{$src, $dst|$dst, $src}",
2025 [(alignednontemporalstore (v2f64 VR128:$src),
2027 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2028 (ins f128mem:$dst, VR128:$src),
2029 "movntdq\t{$src, $dst|$dst, $src}",
2030 [(alignednontemporalstore (v2f64 VR128:$src),
2032 let ExeDomain = SSEPackedInt in
2033 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2034 (ins f128mem:$dst, VR128:$src),
2035 "movntdq\t{$src, $dst|$dst, $src}",
2036 [(alignednontemporalstore (v4f32 VR128:$src),
2039 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2040 (ins f256mem:$dst, VR256:$src),
2041 "movntps\t{$src, $dst|$dst, $src}",
2042 [(alignednontemporalstore (v8f32 VR256:$src),
2044 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2045 (ins f256mem:$dst, VR256:$src),
2046 "movntpd\t{$src, $dst|$dst, $src}",
2047 [(alignednontemporalstore (v4f64 VR256:$src),
2049 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2050 (ins f256mem:$dst, VR256:$src),
2051 "movntdq\t{$src, $dst|$dst, $src}",
2052 [(alignednontemporalstore (v4f64 VR256:$src),
2054 let ExeDomain = SSEPackedInt in
2055 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2056 (ins f256mem:$dst, VR256:$src),
2057 "movntdq\t{$src, $dst|$dst, $src}",
2058 [(alignednontemporalstore (v8f32 VR256:$src),
2063 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2064 "movntps\t{$src, $dst|$dst, $src}",
2065 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2066 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2067 "movntpd\t{$src, $dst|$dst, $src}",
2068 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2070 let ExeDomain = SSEPackedInt in
2071 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2072 "movntdq\t{$src, $dst|$dst, $src}",
2073 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2075 let AddedComplexity = 400 in { // Prefer non-temporal versions
2076 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2077 "movntps\t{$src, $dst|$dst, $src}",
2078 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2079 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2080 "movntpd\t{$src, $dst|$dst, $src}",
2081 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2083 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2084 "movntdq\t{$src, $dst|$dst, $src}",
2085 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2087 let ExeDomain = SSEPackedInt in
2088 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2089 "movntdq\t{$src, $dst|$dst, $src}",
2090 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2092 // There is no AVX form for instructions below this point
2093 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2094 "movnti\t{$src, $dst|$dst, $src}",
2095 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2096 TB, Requires<[HasSSE2]>;
2098 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2099 "movnti\t{$src, $dst|$dst, $src}",
2100 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2101 TB, Requires<[HasSSE2]>;
2104 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2105 "movnti\t{$src, $dst|$dst, $src}",
2106 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2107 TB, Requires<[HasSSE2]>;
2109 //===----------------------------------------------------------------------===//
2110 // SSE 1 & 2 - Misc Instructions (No AVX form)
2111 //===----------------------------------------------------------------------===//
2113 // Prefetch intrinsic.
2114 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2115 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2116 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2117 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2118 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2119 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2120 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2121 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2123 // Load, store, and memory fence
2124 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2125 TB, Requires<[HasSSE1]>;
2126 def : Pat<(X86SFence), (SFENCE)>;
2128 // Alias instructions that map zero vector to pxor / xorp* for sse.
2129 // We set canFoldAsLoad because this can be converted to a constant-pool
2130 // load of an all-zeros value if folding it would be beneficial.
2131 // FIXME: Change encoding to pseudo!
2132 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2133 isCodeGenOnly = 1 in {
2134 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2135 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2136 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2137 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2138 let ExeDomain = SSEPackedInt in
2139 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2140 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2143 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2144 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2145 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2147 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2148 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2150 //===----------------------------------------------------------------------===//
2151 // SSE 1 & 2 - Load/Store XCSR register
2152 //===----------------------------------------------------------------------===//
2154 let isAsmParserOnly = 1 in {
2155 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2156 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2157 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2158 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2161 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2162 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2163 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2164 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2166 //===---------------------------------------------------------------------===//
2167 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2168 //===---------------------------------------------------------------------===//
2170 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2172 let isAsmParserOnly = 1 in {
2173 let neverHasSideEffects = 1 in {
2174 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2175 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2176 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2177 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2179 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2180 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2181 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2182 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2184 let canFoldAsLoad = 1, mayLoad = 1 in {
2185 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2186 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2187 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2188 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2189 let Predicates = [HasAVX] in {
2190 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2191 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2192 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2193 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2197 let mayStore = 1 in {
2198 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2199 (ins i128mem:$dst, VR128:$src),
2200 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2201 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2202 (ins i256mem:$dst, VR256:$src),
2203 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2204 let Predicates = [HasAVX] in {
2205 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2206 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2207 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2208 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2213 let neverHasSideEffects = 1 in
2214 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2215 "movdqa\t{$src, $dst|$dst, $src}", []>;
2217 let canFoldAsLoad = 1, mayLoad = 1 in {
2218 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2219 "movdqa\t{$src, $dst|$dst, $src}",
2220 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2221 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2222 "movdqu\t{$src, $dst|$dst, $src}",
2223 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2224 XS, Requires<[HasSSE2]>;
2227 let mayStore = 1 in {
2228 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2229 "movdqa\t{$src, $dst|$dst, $src}",
2230 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2231 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2232 "movdqu\t{$src, $dst|$dst, $src}",
2233 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2234 XS, Requires<[HasSSE2]>;
2237 // Intrinsic forms of MOVDQU load and store
2238 let isAsmParserOnly = 1 in {
2239 let canFoldAsLoad = 1 in
2240 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2241 "vmovdqu\t{$src, $dst|$dst, $src}",
2242 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2243 XS, VEX, Requires<[HasAVX]>;
2244 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2245 "vmovdqu\t{$src, $dst|$dst, $src}",
2246 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2247 XS, VEX, Requires<[HasAVX]>;
2250 let canFoldAsLoad = 1 in
2251 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2252 "movdqu\t{$src, $dst|$dst, $src}",
2253 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2254 XS, Requires<[HasSSE2]>;
2255 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2256 "movdqu\t{$src, $dst|$dst, $src}",
2257 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2258 XS, Requires<[HasSSE2]>;
2260 } // ExeDomain = SSEPackedInt
2262 //===---------------------------------------------------------------------===//
2263 // SSE2 - Packed Integer Arithmetic Instructions
2264 //===---------------------------------------------------------------------===//
2266 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2268 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2269 bit IsCommutable = 0, bit Is2Addr = 1> {
2270 let isCommutable = IsCommutable in
2271 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2272 (ins VR128:$src1, VR128:$src2),
2274 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2275 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2276 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2277 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2278 (ins VR128:$src1, i128mem:$src2),
2280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2282 [(set VR128:$dst, (IntId VR128:$src1,
2283 (bitconvert (memopv2i64 addr:$src2))))]>;
2286 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2287 string OpcodeStr, Intrinsic IntId,
2288 Intrinsic IntId2, bit Is2Addr = 1> {
2289 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2290 (ins VR128:$src1, VR128:$src2),
2292 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2293 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2294 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2295 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2296 (ins VR128:$src1, i128mem:$src2),
2298 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2299 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2300 [(set VR128:$dst, (IntId VR128:$src1,
2301 (bitconvert (memopv2i64 addr:$src2))))]>;
2302 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2303 (ins VR128:$src1, i32i8imm:$src2),
2305 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2306 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2307 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2310 /// PDI_binop_rm - Simple SSE2 binary operator.
2311 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2312 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2313 let isCommutable = IsCommutable in
2314 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2315 (ins VR128:$src1, VR128:$src2),
2317 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2318 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2319 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2320 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2321 (ins VR128:$src1, i128mem:$src2),
2323 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2324 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2325 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2326 (bitconvert (memopv2i64 addr:$src2)))))]>;
2329 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2331 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2332 /// to collapse (bitconvert VT to VT) into its operand.
2334 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2335 bit IsCommutable = 0, bit Is2Addr = 1> {
2336 let isCommutable = IsCommutable in
2337 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2338 (ins VR128:$src1, VR128:$src2),
2340 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2342 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2343 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2344 (ins VR128:$src1, i128mem:$src2),
2346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2347 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2348 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2351 } // ExeDomain = SSEPackedInt
2353 // 128-bit Integer Arithmetic
2355 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2356 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2357 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2358 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2359 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2360 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2361 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2362 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2363 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2364 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2367 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2369 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2371 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2373 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2375 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2377 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2379 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2381 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2383 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2385 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2387 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2389 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2391 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2393 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2395 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2397 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2399 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2401 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2403 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2407 let Constraints = "$src1 = $dst" in {
2408 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2409 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2410 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2411 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2412 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2413 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2414 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2415 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2416 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2419 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2420 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2421 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2422 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2423 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2424 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2425 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2426 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2427 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2428 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2429 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2430 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2431 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2432 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2433 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2434 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2435 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2436 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2437 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2439 } // Constraints = "$src1 = $dst"
2441 //===---------------------------------------------------------------------===//
2442 // SSE2 - Packed Integer Logical Instructions
2443 //===---------------------------------------------------------------------===//
2445 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2446 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2447 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2449 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2450 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2452 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2453 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2456 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2457 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2459 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2460 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2462 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2463 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2466 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2467 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2469 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2470 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2473 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2474 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2475 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2477 let ExeDomain = SSEPackedInt in {
2478 let neverHasSideEffects = 1 in {
2479 // 128-bit logical shifts.
2480 def VPSLLDQri : PDIi8<0x73, MRM7r,
2481 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2482 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2484 def VPSRLDQri : PDIi8<0x73, MRM3r,
2485 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2486 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2488 // PSRADQri doesn't exist in SSE[1-3].
2490 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2491 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2492 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2493 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2494 VR128:$src2)))]>, VEX_4V;
2496 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2497 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2498 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2499 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2500 (memopv2i64 addr:$src2))))]>,
2505 let Constraints = "$src1 = $dst" in {
2506 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2507 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2508 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2509 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2510 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2511 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2513 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2514 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2515 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2516 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2517 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2518 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2520 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2521 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2522 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2523 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2525 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2526 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2527 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2529 let ExeDomain = SSEPackedInt in {
2530 let neverHasSideEffects = 1 in {
2531 // 128-bit logical shifts.
2532 def PSLLDQri : PDIi8<0x73, MRM7r,
2533 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2534 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2535 def PSRLDQri : PDIi8<0x73, MRM3r,
2536 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2537 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2538 // PSRADQri doesn't exist in SSE[1-3].
2540 def PANDNrr : PDI<0xDF, MRMSrcReg,
2541 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2542 "pandn\t{$src2, $dst|$dst, $src2}",
2543 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2546 def PANDNrm : PDI<0xDF, MRMSrcMem,
2547 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2548 "pandn\t{$src2, $dst|$dst, $src2}",
2549 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2550 (memopv2i64 addr:$src2))))]>;
2552 } // Constraints = "$src1 = $dst"
2554 let Predicates = [HasAVX] in {
2555 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2556 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2557 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2558 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2559 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2560 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2561 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2562 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2563 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2564 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2566 // Shift up / down and insert zero's.
2567 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2568 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2569 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2570 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2573 let Predicates = [HasSSE2] in {
2574 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2575 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2576 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2577 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2578 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2579 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2580 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2581 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2582 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2583 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2585 // Shift up / down and insert zero's.
2586 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2587 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2588 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2589 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2592 //===---------------------------------------------------------------------===//
2593 // SSE2 - Packed Integer Comparison Instructions
2594 //===---------------------------------------------------------------------===//
2596 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2597 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2599 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2601 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2603 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2605 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2607 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2611 let Constraints = "$src1 = $dst" in {
2612 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2613 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2614 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2615 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2616 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2617 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2618 } // Constraints = "$src1 = $dst"
2620 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2621 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2622 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2623 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2624 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2625 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2626 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2627 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2628 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2629 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2630 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2631 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2633 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2634 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2635 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2636 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2637 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2638 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2639 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2640 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2641 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2642 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2643 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2644 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2646 //===---------------------------------------------------------------------===//
2647 // SSE2 - Packed Integer Pack Instructions
2648 //===---------------------------------------------------------------------===//
2650 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2651 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2653 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2655 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2659 let Constraints = "$src1 = $dst" in {
2660 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2661 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2662 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2663 } // Constraints = "$src1 = $dst"
2665 //===---------------------------------------------------------------------===//
2666 // SSE2 - Packed Integer Shuffle Instructions
2667 //===---------------------------------------------------------------------===//
2669 let ExeDomain = SSEPackedInt in {
2670 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2672 def ri : Ii8<0x70, MRMSrcReg,
2673 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2674 !strconcat(OpcodeStr,
2675 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2676 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2678 def mi : Ii8<0x70, MRMSrcMem,
2679 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2680 !strconcat(OpcodeStr,
2681 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2682 [(set VR128:$dst, (vt (pshuf_frag:$src2
2683 (bc_frag (memopv2i64 addr:$src1)),
2686 } // ExeDomain = SSEPackedInt
2688 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2689 let AddedComplexity = 5 in
2690 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2693 // SSE2 with ImmT == Imm8 and XS prefix.
2694 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2697 // SSE2 with ImmT == Imm8 and XD prefix.
2698 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2702 let Predicates = [HasSSE2] in {
2703 let AddedComplexity = 5 in
2704 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2706 // SSE2 with ImmT == Imm8 and XS prefix.
2707 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2709 // SSE2 with ImmT == Imm8 and XD prefix.
2710 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2713 //===---------------------------------------------------------------------===//
2714 // SSE2 - Packed Integer Unpack Instructions
2715 //===---------------------------------------------------------------------===//
2717 let ExeDomain = SSEPackedInt in {
2718 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2719 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2720 def rr : PDI<opc, MRMSrcReg,
2721 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2723 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2724 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2725 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2726 def rm : PDI<opc, MRMSrcMem,
2727 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2729 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2730 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2731 [(set VR128:$dst, (unp_frag VR128:$src1,
2732 (bc_frag (memopv2i64
2736 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2737 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2739 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2741 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2744 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2745 /// knew to collapse (bitconvert VT to VT) into its operand.
2746 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2747 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2748 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2750 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2751 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2752 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2753 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2755 (v2i64 (unpckl VR128:$src1,
2756 (memopv2i64 addr:$src2))))]>, VEX_4V;
2758 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2760 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2762 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2765 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2766 /// knew to collapse (bitconvert VT to VT) into its operand.
2767 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2768 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2769 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2771 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2772 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2773 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2774 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2776 (v2i64 (unpckh VR128:$src1,
2777 (memopv2i64 addr:$src2))))]>, VEX_4V;
2780 let Constraints = "$src1 = $dst" in {
2781 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2782 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2783 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2785 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2786 /// knew to collapse (bitconvert VT to VT) into its operand.
2787 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2788 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2789 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2791 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2792 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2793 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2794 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2796 (v2i64 (unpckl VR128:$src1,
2797 (memopv2i64 addr:$src2))))]>;
2799 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2800 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2801 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2803 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2804 /// knew to collapse (bitconvert VT to VT) into its operand.
2805 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2806 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2807 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2809 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2810 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2811 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2812 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2814 (v2i64 (unpckh VR128:$src1,
2815 (memopv2i64 addr:$src2))))]>;
2818 } // ExeDomain = SSEPackedInt
2820 //===---------------------------------------------------------------------===//
2821 // SSE2 - Packed Integer Extract and Insert
2822 //===---------------------------------------------------------------------===//
2824 let ExeDomain = SSEPackedInt in {
2825 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2826 def rri : Ii8<0xC4, MRMSrcReg,
2827 (outs VR128:$dst), (ins VR128:$src1,
2828 GR32:$src2, i32i8imm:$src3),
2830 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2831 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2833 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2834 def rmi : Ii8<0xC4, MRMSrcMem,
2835 (outs VR128:$dst), (ins VR128:$src1,
2836 i16mem:$src2, i32i8imm:$src3),
2838 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2839 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2841 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2846 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2847 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2848 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2849 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2850 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2851 imm:$src2))]>, OpSize, VEX;
2852 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2853 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2854 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2855 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2859 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2860 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2861 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2862 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2863 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2864 []>, OpSize, VEX_4V;
2867 let Constraints = "$src1 = $dst" in
2868 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2870 } // ExeDomain = SSEPackedInt
2872 //===---------------------------------------------------------------------===//
2873 // SSE2 - Packed Mask Creation
2874 //===---------------------------------------------------------------------===//
2876 let ExeDomain = SSEPackedInt in {
2878 let isAsmParserOnly = 1 in {
2879 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2880 "pmovmskb\t{$src, $dst|$dst, $src}",
2881 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2882 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2883 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2885 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2886 "pmovmskb\t{$src, $dst|$dst, $src}",
2887 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2889 } // ExeDomain = SSEPackedInt
2891 //===---------------------------------------------------------------------===//
2892 // SSE2 - Conditional Store
2893 //===---------------------------------------------------------------------===//
2895 let ExeDomain = SSEPackedInt in {
2897 let isAsmParserOnly = 1 in {
2899 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2900 (ins VR128:$src, VR128:$mask),
2901 "maskmovdqu\t{$mask, $src|$src, $mask}",
2902 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2904 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2905 (ins VR128:$src, VR128:$mask),
2906 "maskmovdqu\t{$mask, $src|$src, $mask}",
2907 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2911 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2912 "maskmovdqu\t{$mask, $src|$src, $mask}",
2913 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2915 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2916 "maskmovdqu\t{$mask, $src|$src, $mask}",
2917 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2919 } // ExeDomain = SSEPackedInt
2921 //===---------------------------------------------------------------------===//
2922 // SSE2 - Move Doubleword
2923 //===---------------------------------------------------------------------===//
2925 // Move Int Doubleword to Packed Double Int
2926 let isAsmParserOnly = 1 in {
2927 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2928 "movd\t{$src, $dst|$dst, $src}",
2930 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2931 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2932 "movd\t{$src, $dst|$dst, $src}",
2934 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2937 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2938 "movd\t{$src, $dst|$dst, $src}",
2940 (v4i32 (scalar_to_vector GR32:$src)))]>;
2941 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2942 "movd\t{$src, $dst|$dst, $src}",
2944 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2947 // Move Int Doubleword to Single Scalar
2948 let isAsmParserOnly = 1 in {
2949 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2950 "movd\t{$src, $dst|$dst, $src}",
2951 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2953 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2954 "movd\t{$src, $dst|$dst, $src}",
2955 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2958 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2959 "movd\t{$src, $dst|$dst, $src}",
2960 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2962 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2963 "movd\t{$src, $dst|$dst, $src}",
2964 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2966 // Move Packed Doubleword Int to Packed Double Int
2967 let isAsmParserOnly = 1 in {
2968 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2969 "movd\t{$src, $dst|$dst, $src}",
2970 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2972 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2973 (ins i32mem:$dst, VR128:$src),
2974 "movd\t{$src, $dst|$dst, $src}",
2975 [(store (i32 (vector_extract (v4i32 VR128:$src),
2976 (iPTR 0))), addr:$dst)]>, VEX;
2978 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2979 "movd\t{$src, $dst|$dst, $src}",
2980 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2982 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2983 "movd\t{$src, $dst|$dst, $src}",
2984 [(store (i32 (vector_extract (v4i32 VR128:$src),
2985 (iPTR 0))), addr:$dst)]>;
2987 // Move Scalar Single to Double Int
2988 let isAsmParserOnly = 1 in {
2989 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2990 "movd\t{$src, $dst|$dst, $src}",
2991 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2992 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2993 "movd\t{$src, $dst|$dst, $src}",
2994 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2996 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2997 "movd\t{$src, $dst|$dst, $src}",
2998 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2999 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3000 "movd\t{$src, $dst|$dst, $src}",
3001 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3003 // movd / movq to XMM register zero-extends
3004 let AddedComplexity = 15, isAsmParserOnly = 1 in {
3005 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3006 "movd\t{$src, $dst|$dst, $src}",
3007 [(set VR128:$dst, (v4i32 (X86vzmovl
3008 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3010 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3011 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3012 [(set VR128:$dst, (v2i64 (X86vzmovl
3013 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3016 let AddedComplexity = 15 in {
3017 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3018 "movd\t{$src, $dst|$dst, $src}",
3019 [(set VR128:$dst, (v4i32 (X86vzmovl
3020 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3021 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3022 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3023 [(set VR128:$dst, (v2i64 (X86vzmovl
3024 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3027 let AddedComplexity = 20 in {
3028 let isAsmParserOnly = 1 in
3029 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3030 "movd\t{$src, $dst|$dst, $src}",
3032 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3033 (loadi32 addr:$src))))))]>,
3035 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3036 "movd\t{$src, $dst|$dst, $src}",
3038 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3039 (loadi32 addr:$src))))))]>;
3041 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3042 (MOVZDI2PDIrm addr:$src)>;
3043 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3044 (MOVZDI2PDIrm addr:$src)>;
3045 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3046 (MOVZDI2PDIrm addr:$src)>;
3049 //===---------------------------------------------------------------------===//
3050 // SSE2 - Move Quadword
3051 //===---------------------------------------------------------------------===//
3053 // Move Quadword Int to Packed Quadword Int
3054 let isAsmParserOnly = 1 in
3055 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3056 "vmovq\t{$src, $dst|$dst, $src}",
3058 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3059 VEX, Requires<[HasAVX]>;
3060 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3061 "movq\t{$src, $dst|$dst, $src}",
3063 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3064 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3066 // Move Packed Quadword Int to Quadword Int
3067 let isAsmParserOnly = 1 in
3068 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3069 "movq\t{$src, $dst|$dst, $src}",
3070 [(store (i64 (vector_extract (v2i64 VR128:$src),
3071 (iPTR 0))), addr:$dst)]>, VEX;
3072 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3073 "movq\t{$src, $dst|$dst, $src}",
3074 [(store (i64 (vector_extract (v2i64 VR128:$src),
3075 (iPTR 0))), addr:$dst)]>;
3077 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3078 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3080 // Store / copy lower 64-bits of a XMM register.
3081 let isAsmParserOnly = 1 in
3082 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3083 "movq\t{$src, $dst|$dst, $src}",
3084 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3085 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3086 "movq\t{$src, $dst|$dst, $src}",
3087 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3089 let AddedComplexity = 20, isAsmParserOnly = 1 in
3090 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3091 "vmovq\t{$src, $dst|$dst, $src}",
3093 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3094 (loadi64 addr:$src))))))]>,
3095 XS, VEX, Requires<[HasAVX]>;
3097 let AddedComplexity = 20 in {
3098 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3099 "movq\t{$src, $dst|$dst, $src}",
3101 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3102 (loadi64 addr:$src))))))]>,
3103 XS, Requires<[HasSSE2]>;
3105 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3106 (MOVZQI2PQIrm addr:$src)>;
3107 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3108 (MOVZQI2PQIrm addr:$src)>;
3109 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3112 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3113 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3114 let isAsmParserOnly = 1, AddedComplexity = 15 in
3115 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3116 "vmovq\t{$src, $dst|$dst, $src}",
3117 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3118 XS, VEX, Requires<[HasAVX]>;
3119 let AddedComplexity = 15 in
3120 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3121 "movq\t{$src, $dst|$dst, $src}",
3122 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3123 XS, Requires<[HasSSE2]>;
3125 let AddedComplexity = 20, isAsmParserOnly = 1 in
3126 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3127 "vmovq\t{$src, $dst|$dst, $src}",
3128 [(set VR128:$dst, (v2i64 (X86vzmovl
3129 (loadv2i64 addr:$src))))]>,
3130 XS, VEX, Requires<[HasAVX]>;
3131 let AddedComplexity = 20 in {
3132 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3133 "movq\t{$src, $dst|$dst, $src}",
3134 [(set VR128:$dst, (v2i64 (X86vzmovl
3135 (loadv2i64 addr:$src))))]>,
3136 XS, Requires<[HasSSE2]>;
3138 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3139 (MOVZPQILo2PQIrm addr:$src)>;
3142 // Instructions to match in the assembler
3143 let isAsmParserOnly = 1 in {
3144 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3145 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3146 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3147 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3148 // Recognize "movd" with GR64 destination, but encode as a "movq"
3149 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3150 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3153 // Instructions for the disassembler
3154 // xr = XMM register
3157 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3158 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3159 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3160 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3161 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3163 //===---------------------------------------------------------------------===//
3164 // SSE2 - Misc Instructions
3165 //===---------------------------------------------------------------------===//
3168 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3169 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3170 TB, Requires<[HasSSE2]>;
3172 // Load, store, and memory fence
3173 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3174 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3175 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3176 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3177 def : Pat<(X86LFence), (LFENCE)>;
3178 def : Pat<(X86MFence), (MFENCE)>;
3181 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3182 // was introduced with SSE2, it's backward compatible.
3183 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3185 // Alias instructions that map zero vector to pxor / xorp* for sse.
3186 // We set canFoldAsLoad because this can be converted to a constant-pool
3187 // load of an all-ones value if folding it would be beneficial.
3188 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3189 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3190 // FIXME: Change encoding to pseudo.
3191 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3192 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3194 //===---------------------------------------------------------------------===//
3195 // SSE3 - Conversion Instructions
3196 //===---------------------------------------------------------------------===//
3198 // Convert Packed Double FP to Packed DW Integers
3199 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3200 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3201 // register, but the same isn't true when using memory operands instead.
3202 // Provide other assembly rr and rm forms to address this explicitly.
3203 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3204 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3205 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3206 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3209 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3210 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3211 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3212 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3215 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3216 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3217 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3218 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3221 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3222 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3223 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3224 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3226 // Convert Packed DW Integers to Packed Double FP
3227 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3228 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3229 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3230 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3231 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3232 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3233 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3234 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3235 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3238 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3239 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3240 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3241 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3243 //===---------------------------------------------------------------------===//
3244 // SSE3 - Move Instructions
3245 //===---------------------------------------------------------------------===//
3247 // Replicate Single FP
3248 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3249 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3250 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3251 [(set VR128:$dst, (v4f32 (rep_frag
3252 VR128:$src, (undef))))]>;
3253 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3254 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3255 [(set VR128:$dst, (rep_frag
3256 (memopv4f32 addr:$src), (undef)))]>;
3259 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3261 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3262 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3263 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3264 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3267 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3268 // FIXME: Merge above classes when we have patterns for the ymm version
3269 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3270 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3271 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3272 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3274 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3275 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3277 // Replicate Double FP
3278 multiclass sse3_replicate_dfp<string OpcodeStr> {
3279 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3280 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3281 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3282 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3283 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3285 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3289 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3290 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3291 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3293 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3294 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3298 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3299 // FIXME: Merge above classes when we have patterns for the ymm version
3300 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3301 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3303 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3305 // Move Unaligned Integer
3306 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3307 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3308 "vlddqu\t{$src, $dst|$dst, $src}",
3309 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3310 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3311 "vlddqu\t{$src, $dst|$dst, $src}", []>, VEX;
3313 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3314 "lddqu\t{$src, $dst|$dst, $src}",
3315 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3317 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3319 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3321 // Several Move patterns
3322 let AddedComplexity = 5 in {
3323 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3324 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3325 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3326 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3327 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3328 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3329 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3330 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3333 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3334 let AddedComplexity = 15 in
3335 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3336 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3337 let AddedComplexity = 20 in
3338 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3339 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3341 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3342 let AddedComplexity = 15 in
3343 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3344 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3345 let AddedComplexity = 20 in
3346 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3347 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3349 //===---------------------------------------------------------------------===//
3350 // SSE3 - Arithmetic
3351 //===---------------------------------------------------------------------===//
3353 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3354 X86MemOperand x86memop, bit Is2Addr = 1> {
3355 def rr : I<0xD0, MRMSrcReg,
3356 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3358 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3360 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3361 def rm : I<0xD0, MRMSrcMem,
3362 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3364 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3365 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3366 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3369 let isAsmParserOnly = 1, Predicates = [HasAVX],
3370 ExeDomain = SSEPackedDouble in {
3371 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3372 f128mem, 0>, XD, VEX_4V;
3373 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3374 f128mem, 0>, OpSize, VEX_4V;
3375 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3376 f256mem, 0>, XD, VEX_4V;
3377 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3378 f256mem, 0>, OpSize, VEX_4V;
3380 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3381 ExeDomain = SSEPackedDouble in {
3382 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3384 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3385 f128mem>, TB, OpSize;
3388 //===---------------------------------------------------------------------===//
3389 // SSE3 Instructions
3390 //===---------------------------------------------------------------------===//
3393 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3394 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3395 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3397 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3398 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3399 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3401 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3403 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3404 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3405 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3407 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3408 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3409 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3411 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3412 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3413 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3415 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3417 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3418 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3419 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3422 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3423 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3424 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3425 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3426 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3427 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3428 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3429 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3430 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3431 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3432 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3433 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3434 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3435 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3436 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3437 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3438 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3441 let Constraints = "$src1 = $dst" in {
3442 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3443 int_x86_sse3_hadd_ps>;
3444 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3445 int_x86_sse3_hadd_pd>;
3446 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3447 int_x86_sse3_hsub_ps>;
3448 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3449 int_x86_sse3_hsub_pd>;
3452 //===---------------------------------------------------------------------===//
3453 // SSSE3 - Packed Absolute Instructions
3454 //===---------------------------------------------------------------------===//
3456 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3457 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3458 PatFrag mem_frag64, PatFrag mem_frag128,
3459 Intrinsic IntId64, Intrinsic IntId128> {
3460 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3461 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3462 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3464 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3465 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3467 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3469 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3471 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3472 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3475 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3477 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3480 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3483 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3484 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3485 int_x86_ssse3_pabs_b,
3486 int_x86_ssse3_pabs_b_128>, VEX;
3487 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3488 int_x86_ssse3_pabs_w,
3489 int_x86_ssse3_pabs_w_128>, VEX;
3490 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3491 int_x86_ssse3_pabs_d,
3492 int_x86_ssse3_pabs_d_128>, VEX;
3495 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3496 int_x86_ssse3_pabs_b,
3497 int_x86_ssse3_pabs_b_128>;
3498 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3499 int_x86_ssse3_pabs_w,
3500 int_x86_ssse3_pabs_w_128>;
3501 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3502 int_x86_ssse3_pabs_d,
3503 int_x86_ssse3_pabs_d_128>;
3505 //===---------------------------------------------------------------------===//
3506 // SSSE3 - Packed Binary Operator Instructions
3507 //===---------------------------------------------------------------------===//
3509 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3510 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3511 PatFrag mem_frag64, PatFrag mem_frag128,
3512 Intrinsic IntId64, Intrinsic IntId128,
3514 let isCommutable = 1 in
3515 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3516 (ins VR64:$src1, VR64:$src2),
3518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3519 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3520 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3521 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3522 (ins VR64:$src1, i64mem:$src2),
3524 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3527 (IntId64 VR64:$src1,
3528 (bitconvert (memopv8i8 addr:$src2))))]>;
3530 let isCommutable = 1 in
3531 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3532 (ins VR128:$src1, VR128:$src2),
3534 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3535 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3536 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3538 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3539 (ins VR128:$src1, i128mem:$src2),
3541 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3542 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3544 (IntId128 VR128:$src1,
3545 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3548 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3549 let isCommutable = 0 in {
3550 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3551 int_x86_ssse3_phadd_w,
3552 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3553 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3554 int_x86_ssse3_phadd_d,
3555 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3556 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3557 int_x86_ssse3_phadd_sw,
3558 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3559 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3560 int_x86_ssse3_phsub_w,
3561 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3562 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3563 int_x86_ssse3_phsub_d,
3564 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3565 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3566 int_x86_ssse3_phsub_sw,
3567 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3568 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3569 int_x86_ssse3_pmadd_ub_sw,
3570 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3571 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3572 int_x86_ssse3_pshuf_b,
3573 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3574 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3575 int_x86_ssse3_psign_b,
3576 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3577 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3578 int_x86_ssse3_psign_w,
3579 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3580 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3581 int_x86_ssse3_psign_d,
3582 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3584 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3585 int_x86_ssse3_pmul_hr_sw,
3586 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3589 // None of these have i8 immediate fields.
3590 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3591 let isCommutable = 0 in {
3592 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3593 int_x86_ssse3_phadd_w,
3594 int_x86_ssse3_phadd_w_128>;
3595 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3596 int_x86_ssse3_phadd_d,
3597 int_x86_ssse3_phadd_d_128>;
3598 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3599 int_x86_ssse3_phadd_sw,
3600 int_x86_ssse3_phadd_sw_128>;
3601 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3602 int_x86_ssse3_phsub_w,
3603 int_x86_ssse3_phsub_w_128>;
3604 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3605 int_x86_ssse3_phsub_d,
3606 int_x86_ssse3_phsub_d_128>;
3607 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3608 int_x86_ssse3_phsub_sw,
3609 int_x86_ssse3_phsub_sw_128>;
3610 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3611 int_x86_ssse3_pmadd_ub_sw,
3612 int_x86_ssse3_pmadd_ub_sw_128>;
3613 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3614 int_x86_ssse3_pshuf_b,
3615 int_x86_ssse3_pshuf_b_128>;
3616 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3617 int_x86_ssse3_psign_b,
3618 int_x86_ssse3_psign_b_128>;
3619 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3620 int_x86_ssse3_psign_w,
3621 int_x86_ssse3_psign_w_128>;
3622 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3623 int_x86_ssse3_psign_d,
3624 int_x86_ssse3_psign_d_128>;
3626 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3627 int_x86_ssse3_pmul_hr_sw,
3628 int_x86_ssse3_pmul_hr_sw_128>;
3631 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3632 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3633 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3634 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3636 //===---------------------------------------------------------------------===//
3637 // SSSE3 - Packed Align Instruction Patterns
3638 //===---------------------------------------------------------------------===//
3640 multiclass sse3_palign<string asm, bit Is2Addr = 1> {
3641 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3642 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3644 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3646 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3648 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3649 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3651 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3653 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3656 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3657 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3659 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3661 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3663 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3664 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3666 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3668 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3672 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3673 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3674 let Constraints = "$src1 = $dst" in
3675 defm PALIGN : sse3_palign<"palignr">;
3677 let AddedComplexity = 5 in {
3679 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3680 (PALIGNR64rr VR64:$src2, VR64:$src1,
3681 (SHUFFLE_get_palign_imm VR64:$src3))>,
3682 Requires<[HasSSSE3]>;
3683 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3684 (PALIGNR64rr VR64:$src2, VR64:$src1,
3685 (SHUFFLE_get_palign_imm VR64:$src3))>,
3686 Requires<[HasSSSE3]>;
3687 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3688 (PALIGNR64rr VR64:$src2, VR64:$src1,
3689 (SHUFFLE_get_palign_imm VR64:$src3))>,
3690 Requires<[HasSSSE3]>;
3691 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3692 (PALIGNR64rr VR64:$src2, VR64:$src1,
3693 (SHUFFLE_get_palign_imm VR64:$src3))>,
3694 Requires<[HasSSSE3]>;
3696 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3697 (PALIGNR128rr VR128:$src2, VR128:$src1,
3698 (SHUFFLE_get_palign_imm VR128:$src3))>,
3699 Requires<[HasSSSE3]>;
3700 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3701 (PALIGNR128rr VR128:$src2, VR128:$src1,
3702 (SHUFFLE_get_palign_imm VR128:$src3))>,
3703 Requires<[HasSSSE3]>;
3704 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3705 (PALIGNR128rr VR128:$src2, VR128:$src1,
3706 (SHUFFLE_get_palign_imm VR128:$src3))>,
3707 Requires<[HasSSSE3]>;
3708 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3709 (PALIGNR128rr VR128:$src2, VR128:$src1,
3710 (SHUFFLE_get_palign_imm VR128:$src3))>,
3711 Requires<[HasSSSE3]>;
3714 //===---------------------------------------------------------------------===//
3715 // SSSE3 Misc Instructions
3716 //===---------------------------------------------------------------------===//
3718 // Thread synchronization
3719 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3720 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3721 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3722 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3724 //===---------------------------------------------------------------------===//
3725 // Non-Instruction Patterns
3726 //===---------------------------------------------------------------------===//
3728 // extload f32 -> f64. This matches load+fextend because we have a hack in
3729 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3731 // Since these loads aren't folded into the fextend, we have to match it
3733 let Predicates = [HasSSE2] in
3734 def : Pat<(fextend (loadf32 addr:$src)),
3735 (CVTSS2SDrm addr:$src)>;
3738 let Predicates = [HasSSE2] in {
3739 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3740 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3741 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3742 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3743 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3744 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3745 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3746 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3747 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3748 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3749 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3750 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3751 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3752 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3753 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3754 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3755 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3756 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3757 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3758 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3759 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3760 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3761 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3762 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3763 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3764 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3765 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3766 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3767 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3768 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3771 // Move scalar to XMM zero-extended
3772 // movd to XMM register zero-extends
3773 let AddedComplexity = 15 in {
3774 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3775 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3776 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3777 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3778 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3779 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3780 (MOVSSrr (v4f32 (V_SET0PS)),
3781 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3782 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3783 (MOVSSrr (v4i32 (V_SET0PI)),
3784 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3787 // Splat v2f64 / v2i64
3788 let AddedComplexity = 10 in {
3789 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3790 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3791 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3792 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3793 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3794 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3795 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3796 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3799 // Special unary SHUFPSrri case.
3800 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3801 (SHUFPSrri VR128:$src1, VR128:$src1,
3802 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3803 let AddedComplexity = 5 in
3804 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3805 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3806 Requires<[HasSSE2]>;
3807 // Special unary SHUFPDrri case.
3808 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3809 (SHUFPDrri VR128:$src1, VR128:$src1,
3810 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3811 Requires<[HasSSE2]>;
3812 // Special unary SHUFPDrri case.
3813 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3814 (SHUFPDrri VR128:$src1, VR128:$src1,
3815 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3816 Requires<[HasSSE2]>;
3817 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3818 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3819 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3820 Requires<[HasSSE2]>;
3822 // Special binary v4i32 shuffle cases with SHUFPS.
3823 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3824 (SHUFPSrri VR128:$src1, VR128:$src2,
3825 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3826 Requires<[HasSSE2]>;
3827 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3828 (SHUFPSrmi VR128:$src1, addr:$src2,
3829 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3830 Requires<[HasSSE2]>;
3831 // Special binary v2i64 shuffle cases using SHUFPDrri.
3832 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3833 (SHUFPDrri VR128:$src1, VR128:$src2,
3834 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3835 Requires<[HasSSE2]>;
3837 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3838 let AddedComplexity = 15 in {
3839 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3840 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3841 Requires<[OptForSpeed, HasSSE2]>;
3842 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3843 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3844 Requires<[OptForSpeed, HasSSE2]>;
3846 let AddedComplexity = 10 in {
3847 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3848 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3849 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3850 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3851 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3852 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3853 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3854 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3857 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3858 let AddedComplexity = 15 in {
3859 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3860 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3861 Requires<[OptForSpeed, HasSSE2]>;
3862 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3863 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3864 Requires<[OptForSpeed, HasSSE2]>;
3866 let AddedComplexity = 10 in {
3867 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3868 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3869 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3870 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3871 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3872 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3873 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3874 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3877 let AddedComplexity = 20 in {
3878 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3879 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3880 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3882 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3883 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3884 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3886 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3887 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3888 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3889 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3890 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3893 let AddedComplexity = 20 in {
3894 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3895 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3896 (MOVLPSrm VR128:$src1, addr:$src2)>;
3897 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3898 (MOVLPDrm VR128:$src1, addr:$src2)>;
3899 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3900 (MOVLPSrm VR128:$src1, addr:$src2)>;
3901 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3902 (MOVLPDrm VR128:$src1, addr:$src2)>;
3905 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3906 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3907 (MOVLPSmr addr:$src1, VR128:$src2)>;
3908 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3909 (MOVLPDmr addr:$src1, VR128:$src2)>;
3910 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3912 (MOVLPSmr addr:$src1, VR128:$src2)>;
3913 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3914 (MOVLPDmr addr:$src1, VR128:$src2)>;
3916 let AddedComplexity = 15 in {
3917 // Setting the lowest element in the vector.
3918 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3919 (MOVSSrr (v4i32 VR128:$src1),
3920 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3921 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3922 (MOVSDrr (v2i64 VR128:$src1),
3923 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3925 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3926 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3927 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3928 Requires<[HasSSE2]>;
3929 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3930 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3931 Requires<[HasSSE2]>;
3934 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3935 // fall back to this for SSE1)
3936 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3937 (SHUFPSrri VR128:$src2, VR128:$src1,
3938 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3940 // Set lowest element and zero upper elements.
3941 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3942 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3944 // Some special case pandn patterns.
3945 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3947 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3948 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3950 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3951 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3953 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3955 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3956 (memop addr:$src2))),
3957 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3958 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3959 (memop addr:$src2))),
3960 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3961 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3962 (memop addr:$src2))),
3963 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3965 // vector -> vector casts
3966 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3967 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3968 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3969 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3970 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3971 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3972 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3973 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3975 // Use movaps / movups for SSE integer load / store (one byte shorter).
3976 def : Pat<(alignedloadv4i32 addr:$src),
3977 (MOVAPSrm addr:$src)>;
3978 def : Pat<(loadv4i32 addr:$src),
3979 (MOVUPSrm addr:$src)>;
3980 def : Pat<(alignedloadv2i64 addr:$src),
3981 (MOVAPSrm addr:$src)>;
3982 def : Pat<(loadv2i64 addr:$src),
3983 (MOVUPSrm addr:$src)>;
3985 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3986 (MOVAPSmr addr:$dst, VR128:$src)>;
3987 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3988 (MOVAPSmr addr:$dst, VR128:$src)>;
3989 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3990 (MOVAPSmr addr:$dst, VR128:$src)>;
3991 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3992 (MOVAPSmr addr:$dst, VR128:$src)>;
3993 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3994 (MOVUPSmr addr:$dst, VR128:$src)>;
3995 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3996 (MOVUPSmr addr:$dst, VR128:$src)>;
3997 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3998 (MOVUPSmr addr:$dst, VR128:$src)>;
3999 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
4000 (MOVUPSmr addr:$dst, VR128:$src)>;
4002 //===----------------------------------------------------------------------===//
4003 // SSE4.1 - Packed Move with Sign/Zero Extend
4004 //===----------------------------------------------------------------------===//
4006 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4007 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4008 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4009 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4011 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4012 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4014 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4018 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4019 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4021 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4023 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4025 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4027 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4029 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4033 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4034 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4035 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4036 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4037 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4038 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4040 // Common patterns involving scalar load.
4041 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4042 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4043 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4044 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4046 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4047 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4048 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4049 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4051 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4052 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4053 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4054 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4056 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4057 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4058 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4059 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4061 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4062 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4063 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4064 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4066 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4067 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4068 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4069 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4072 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4073 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4074 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4075 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4077 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4078 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4080 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4084 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4085 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4087 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4089 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4091 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4095 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4096 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4097 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4098 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4100 // Common patterns involving scalar load
4101 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4102 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4103 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4104 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4106 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4107 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4108 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4109 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4112 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4113 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4115 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4117 // Expecting a i16 load any extended to i32 value.
4118 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4120 [(set VR128:$dst, (IntId (bitconvert
4121 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4125 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4126 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4128 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4131 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4132 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4134 // Common patterns involving scalar load
4135 def : Pat<(int_x86_sse41_pmovsxbq
4136 (bitconvert (v4i32 (X86vzmovl
4137 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4138 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4140 def : Pat<(int_x86_sse41_pmovzxbq
4141 (bitconvert (v4i32 (X86vzmovl
4142 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4143 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4145 //===----------------------------------------------------------------------===//
4146 // SSE4.1 - Extract Instructions
4147 //===----------------------------------------------------------------------===//
4149 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4150 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4151 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4152 (ins VR128:$src1, i32i8imm:$src2),
4153 !strconcat(OpcodeStr,
4154 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4155 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4157 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4158 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4159 !strconcat(OpcodeStr,
4160 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4163 // There's an AssertZext in the way of writing the store pattern
4164 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4167 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4168 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4169 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4170 (ins VR128:$src1, i32i8imm:$src2),
4171 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4174 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4177 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4178 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4179 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4180 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4181 !strconcat(OpcodeStr,
4182 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4185 // There's an AssertZext in the way of writing the store pattern
4186 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4189 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4190 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4192 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4195 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4196 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4197 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4198 (ins VR128:$src1, i32i8imm:$src2),
4199 !strconcat(OpcodeStr,
4200 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4202 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4203 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4204 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4205 !strconcat(OpcodeStr,
4206 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4207 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4208 addr:$dst)]>, OpSize;
4211 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4212 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4214 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4216 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4217 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4218 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4219 (ins VR128:$src1, i32i8imm:$src2),
4220 !strconcat(OpcodeStr,
4221 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4223 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4224 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4225 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4226 !strconcat(OpcodeStr,
4227 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4228 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4229 addr:$dst)]>, OpSize, REX_W;
4232 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4233 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4235 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4237 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4239 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4240 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4241 (ins VR128:$src1, i32i8imm:$src2),
4242 !strconcat(OpcodeStr,
4243 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4245 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4247 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4248 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4249 !strconcat(OpcodeStr,
4250 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4251 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4252 addr:$dst)]>, OpSize;
4255 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4256 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4257 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4258 (ins VR128:$src1, i32i8imm:$src2),
4259 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4262 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4264 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4265 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4268 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4269 Requires<[HasSSE41]>;
4271 //===----------------------------------------------------------------------===//
4272 // SSE4.1 - Insert Instructions
4273 //===----------------------------------------------------------------------===//
4275 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4276 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4277 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4279 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4281 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4283 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4284 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4285 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4287 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4289 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4291 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4292 imm:$src3))]>, OpSize;
4295 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4296 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4297 let Constraints = "$src1 = $dst" in
4298 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4300 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4301 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4302 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4304 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4306 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4308 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4310 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4311 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4313 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4315 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4317 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4318 imm:$src3)))]>, OpSize;
4321 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4322 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4323 let Constraints = "$src1 = $dst" in
4324 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4326 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4327 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4328 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4330 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4334 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4336 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4337 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4339 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4341 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4343 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4344 imm:$src3)))]>, OpSize;
4347 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4348 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4349 let Constraints = "$src1 = $dst" in
4350 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4352 // insertps has a few different modes, there's the first two here below which
4353 // are optimized inserts that won't zero arbitrary elements in the destination
4354 // vector. The next one matches the intrinsic and could zero arbitrary elements
4355 // in the target vector.
4356 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4357 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4358 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4360 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4362 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4364 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4366 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4367 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4369 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4371 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4373 (X86insrtps VR128:$src1,
4374 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4375 imm:$src3))]>, OpSize;
4378 let Constraints = "$src1 = $dst" in
4379 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4380 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4381 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4383 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4384 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4386 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4387 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4388 Requires<[HasSSE41]>;
4390 //===----------------------------------------------------------------------===//
4391 // SSE4.1 - Round Instructions
4392 //===----------------------------------------------------------------------===//
4394 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4395 X86MemOperand x86memop, RegisterClass RC,
4396 PatFrag mem_frag32, PatFrag mem_frag64,
4397 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4398 // Intrinsic operation, reg.
4399 // Vector intrinsic operation, reg
4400 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
4401 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4402 !strconcat(OpcodeStr,
4403 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4404 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4407 // Vector intrinsic operation, mem
4408 def PSm_Int : Ii8<opcps, MRMSrcMem,
4409 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4410 !strconcat(OpcodeStr,
4411 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4413 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4415 Requires<[HasSSE41]>;
4417 // Vector intrinsic operation, reg
4418 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
4419 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4420 !strconcat(OpcodeStr,
4421 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4422 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4425 // Vector intrinsic operation, mem
4426 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
4427 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4428 !strconcat(OpcodeStr,
4429 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4431 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4435 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4436 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4437 // Intrinsic operation, reg.
4438 // Vector intrinsic operation, reg
4439 def PSr : SS4AIi8<opcps, MRMSrcReg,
4440 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4441 !strconcat(OpcodeStr,
4442 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4445 // Vector intrinsic operation, mem
4446 def PSm : Ii8<opcps, MRMSrcMem,
4447 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4448 !strconcat(OpcodeStr,
4449 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4450 []>, TA, OpSize, Requires<[HasSSE41]>;
4452 // Vector intrinsic operation, reg
4453 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4454 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4455 !strconcat(OpcodeStr,
4456 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4459 // Vector intrinsic operation, mem
4460 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4461 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4462 !strconcat(OpcodeStr,
4463 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4467 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4470 Intrinsic F64Int, bit Is2Addr = 1> {
4471 // Intrinsic operation, reg.
4472 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
4473 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4475 !strconcat(OpcodeStr,
4476 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4477 !strconcat(OpcodeStr,
4478 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4479 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4482 // Intrinsic operation, mem.
4483 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
4484 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4486 !strconcat(OpcodeStr,
4487 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4488 !strconcat(OpcodeStr,
4489 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4491 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4494 // Intrinsic operation, reg.
4495 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
4496 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4498 !strconcat(OpcodeStr,
4499 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4500 !strconcat(OpcodeStr,
4501 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4502 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4505 // Intrinsic operation, mem.
4506 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
4507 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4509 !strconcat(OpcodeStr,
4510 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4511 !strconcat(OpcodeStr,
4512 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4514 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4518 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4520 // Intrinsic operation, reg.
4521 def SSr : SS4AIi8<opcss, MRMSrcReg,
4522 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4523 !strconcat(OpcodeStr,
4524 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4527 // Intrinsic operation, mem.
4528 def SSm : SS4AIi8<opcss, MRMSrcMem,
4529 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4530 !strconcat(OpcodeStr,
4531 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4534 // Intrinsic operation, reg.
4535 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4536 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4537 !strconcat(OpcodeStr,
4538 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4541 // Intrinsic operation, mem.
4542 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4543 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4544 !strconcat(OpcodeStr,
4545 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4549 // FP round - roundss, roundps, roundsd, roundpd
4550 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4552 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4553 memopv4f32, memopv2f64,
4554 int_x86_sse41_round_ps,
4555 int_x86_sse41_round_pd>, VEX;
4556 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4557 memopv8f32, memopv4f64,
4558 int_x86_avx_round_ps_256,
4559 int_x86_avx_round_pd_256>, VEX;
4560 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4561 int_x86_sse41_round_ss,
4562 int_x86_sse41_round_sd, 0>, VEX_4V;
4564 // Instructions for the assembler
4565 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4567 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4569 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4572 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4573 memopv4f32, memopv2f64,
4574 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4575 let Constraints = "$src1 = $dst" in
4576 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4577 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4579 //===----------------------------------------------------------------------===//
4580 // SSE4.1 - Packed Bit Test
4581 //===----------------------------------------------------------------------===//
4583 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4584 // the intel intrinsic that corresponds to this.
4585 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4586 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4587 "vptest\t{$src2, $src1|$src1, $src2}",
4588 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4590 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4591 "vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
4593 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4594 "vptest\t{$src2, $src1|$src1, $src2}",
4595 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4597 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4598 "vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
4601 let Defs = [EFLAGS] in {
4602 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4603 "ptest \t{$src2, $src1|$src1, $src2}",
4604 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4606 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4607 "ptest \t{$src2, $src1|$src1, $src2}",
4608 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4612 // The bit test instructions below are AVX only
4613 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4614 X86MemOperand x86memop> {
4615 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4618 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4623 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4624 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem>;
4625 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem>;
4626 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem>;
4627 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem>;
4630 //===----------------------------------------------------------------------===//
4631 // SSE4.1 - Misc Instructions
4632 //===----------------------------------------------------------------------===//
4634 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4635 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4636 Intrinsic IntId128> {
4637 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4639 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4640 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4641 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4643 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4646 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4649 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4650 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4651 int_x86_sse41_phminposuw>, VEX;
4652 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4653 int_x86_sse41_phminposuw>;
4655 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4656 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4657 Intrinsic IntId128, bit Is2Addr = 1> {
4658 let isCommutable = 1 in
4659 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4660 (ins VR128:$src1, VR128:$src2),
4662 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4663 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4664 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4665 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4666 (ins VR128:$src1, i128mem:$src2),
4668 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4669 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4671 (IntId128 VR128:$src1,
4672 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4675 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4676 let isCommutable = 0 in
4677 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4679 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4681 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4683 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4685 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4687 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4689 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4691 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4693 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4695 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4697 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4701 let Constraints = "$src1 = $dst" in {
4702 let isCommutable = 0 in
4703 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4704 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4705 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4706 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4707 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4708 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4709 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4710 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4711 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4712 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4713 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4716 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4717 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4718 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4719 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4721 /// SS48I_binop_rm - Simple SSE41 binary operator.
4722 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4723 ValueType OpVT, bit Is2Addr = 1> {
4724 let isCommutable = 1 in
4725 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4726 (ins VR128:$src1, VR128:$src2),
4728 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4729 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4730 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4732 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4733 (ins VR128:$src1, i128mem:$src2),
4735 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4736 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4737 [(set VR128:$dst, (OpNode VR128:$src1,
4738 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4742 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4743 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4744 let Constraints = "$src1 = $dst" in
4745 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4747 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4748 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4749 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4750 X86MemOperand x86memop, bit Is2Addr = 1> {
4751 let isCommutable = 1 in
4752 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4753 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4755 !strconcat(OpcodeStr,
4756 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4757 !strconcat(OpcodeStr,
4758 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4759 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4761 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4762 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4764 !strconcat(OpcodeStr,
4765 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4766 !strconcat(OpcodeStr,
4767 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4770 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4774 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4775 let isCommutable = 0 in {
4776 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4777 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4778 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4779 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4780 let Pattern = []<dag> in {
4781 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4782 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4783 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4784 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4786 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4787 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4788 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4789 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4791 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4792 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4793 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4794 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4795 let Pattern = []<dag> in
4796 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4797 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4800 let Constraints = "$src1 = $dst" in {
4801 let isCommutable = 0 in {
4802 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4803 VR128, memopv16i8, i128mem>;
4804 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4805 VR128, memopv16i8, i128mem>;
4806 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4807 VR128, memopv16i8, i128mem>;
4808 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4809 VR128, memopv16i8, i128mem>;
4811 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4812 VR128, memopv16i8, i128mem>;
4813 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4814 VR128, memopv16i8, i128mem>;
4817 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4818 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4819 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4820 RegisterClass RC, X86MemOperand x86memop,
4821 PatFrag mem_frag, Intrinsic IntId> {
4822 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4823 (ins RC:$src1, RC:$src2, RC:$src3),
4824 !strconcat(OpcodeStr,
4825 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4826 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4827 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4829 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4830 (ins RC:$src1, x86memop:$src2, RC:$src3),
4831 !strconcat(OpcodeStr,
4832 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4834 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4836 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4840 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4841 memopv16i8, int_x86_sse41_blendvpd>;
4842 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4843 memopv16i8, int_x86_sse41_blendvps>;
4844 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4845 memopv16i8, int_x86_sse41_pblendvb>;
4847 let Pattern = []<dag> in { // FIXME: implement 256 intrinsics here.
4848 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4849 memopv32i8, int_x86_sse41_blendvpd>;
4850 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4851 memopv32i8, int_x86_sse41_blendvps>;
4854 /// SS41I_ternary_int - SSE 4.1 ternary operator
4855 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4856 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4857 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4858 (ins VR128:$src1, VR128:$src2),
4859 !strconcat(OpcodeStr,
4860 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4861 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4864 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4865 (ins VR128:$src1, i128mem:$src2),
4866 !strconcat(OpcodeStr,
4867 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4870 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4874 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4875 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4876 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4878 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4879 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4880 "vmovntdqa\t{$src, $dst|$dst, $src}",
4881 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4883 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4884 "movntdqa\t{$src, $dst|$dst, $src}",
4885 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4888 //===----------------------------------------------------------------------===//
4889 // SSE4.2 - Compare Instructions
4890 //===----------------------------------------------------------------------===//
4892 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4893 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4894 Intrinsic IntId128, bit Is2Addr = 1> {
4895 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4896 (ins VR128:$src1, VR128:$src2),
4898 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4899 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4900 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4902 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4903 (ins VR128:$src1, i128mem:$src2),
4905 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4906 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4908 (IntId128 VR128:$src1,
4909 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4912 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4913 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4915 let Constraints = "$src1 = $dst" in
4916 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4918 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4919 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4920 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4921 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4923 //===----------------------------------------------------------------------===//
4924 // SSE4.2 - String/text Processing Instructions
4925 //===----------------------------------------------------------------------===//
4927 // Packed Compare Implicit Length Strings, Return Mask
4928 multiclass pseudo_pcmpistrm<string asm> {
4929 def REG : Ii8<0, Pseudo, (outs VR128:$dst),
4930 (ins VR128:$src1, VR128:$src2, i8imm:$src3), !strconcat(asm, "rr PSEUDO"),
4931 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4933 def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
4934 (ins VR128:$src1, i128mem:$src2, i8imm:$src3), !strconcat(asm, "rm PSEUDO"),
4935 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4936 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4939 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4940 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4941 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4944 let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
4945 Predicates = [HasAVX] in {
4946 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4947 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4948 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4949 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4950 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4951 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4954 let Defs = [XMM0, EFLAGS] in {
4955 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4956 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4957 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4958 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4959 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4960 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4963 // Packed Compare Explicit Length Strings, Return Mask
4964 multiclass pseudo_pcmpestrm<string asm> {
4965 def REG : Ii8<0, Pseudo, (outs VR128:$dst),
4966 (ins VR128:$src1, VR128:$src3, i8imm:$src5), !strconcat(asm, "rr PSEUDO"),
4967 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4968 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4969 def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
4970 (ins VR128:$src1, i128mem:$src3, i8imm:$src5), !strconcat(asm, "rm PSEUDO"),
4971 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4972 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4975 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4976 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4977 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4980 let isAsmParserOnly = 1, Predicates = [HasAVX],
4981 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4982 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4983 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4984 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4985 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4986 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4987 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4990 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4991 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4992 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4993 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4994 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4995 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4996 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4999 // Packed Compare Implicit Length Strings, Return Index
5000 let Defs = [ECX, EFLAGS] in {
5001 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
5002 def rr : SS42AI<0x63, MRMSrcReg, (outs),
5003 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5004 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5005 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5006 (implicit EFLAGS)]>, OpSize;
5007 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5008 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5009 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5010 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5011 (implicit EFLAGS)]>, OpSize;
5015 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5016 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5018 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5020 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5022 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5024 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5026 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5030 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5031 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5032 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5033 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5034 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5035 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5037 // Packed Compare Explicit Length Strings, Return Index
5038 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5039 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5040 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5041 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5042 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5043 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5044 (implicit EFLAGS)]>, OpSize;
5045 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5046 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5047 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5049 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5050 (implicit EFLAGS)]>, OpSize;
5054 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5055 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5057 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5059 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5061 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5063 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5065 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5069 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5070 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5071 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5072 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5073 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5074 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5076 //===----------------------------------------------------------------------===//
5077 // SSE4.2 - CRC Instructions
5078 //===----------------------------------------------------------------------===//
5080 // No CRC instructions have AVX equivalents
5082 // crc intrinsic instruction
5083 // This set of instructions are only rm, the only difference is the size
5085 let Constraints = "$src1 = $dst" in {
5086 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5087 (ins GR32:$src1, i8mem:$src2),
5088 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5090 (int_x86_sse42_crc32_8 GR32:$src1,
5091 (load addr:$src2)))]>;
5092 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5093 (ins GR32:$src1, GR8:$src2),
5094 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5096 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
5097 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5098 (ins GR32:$src1, i16mem:$src2),
5099 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5101 (int_x86_sse42_crc32_16 GR32:$src1,
5102 (load addr:$src2)))]>,
5104 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5105 (ins GR32:$src1, GR16:$src2),
5106 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5108 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
5110 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5111 (ins GR32:$src1, i32mem:$src2),
5112 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5114 (int_x86_sse42_crc32_32 GR32:$src1,
5115 (load addr:$src2)))]>;
5116 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5117 (ins GR32:$src1, GR32:$src2),
5118 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5120 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
5121 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5122 (ins GR64:$src1, i8mem:$src2),
5123 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5125 (int_x86_sse42_crc64_8 GR64:$src1,
5126 (load addr:$src2)))]>,
5128 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5129 (ins GR64:$src1, GR8:$src2),
5130 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5132 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
5134 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5135 (ins GR64:$src1, i64mem:$src2),
5136 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5138 (int_x86_sse42_crc64_64 GR64:$src1,
5139 (load addr:$src2)))]>,
5141 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5142 (ins GR64:$src1, GR64:$src2),
5143 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5145 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
5149 //===----------------------------------------------------------------------===//
5150 // AES-NI Instructions
5151 //===----------------------------------------------------------------------===//
5153 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5154 Intrinsic IntId128, bit Is2Addr = 1> {
5155 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5156 (ins VR128:$src1, VR128:$src2),
5158 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5159 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5160 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5162 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5163 (ins VR128:$src1, i128mem:$src2),
5165 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5166 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5168 (IntId128 VR128:$src1,
5169 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5172 // Perform One Round of an AES Encryption/Decryption Flow
5173 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5174 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5175 int_x86_aesni_aesenc, 0>, VEX_4V;
5176 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5177 int_x86_aesni_aesenclast, 0>, VEX_4V;
5178 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5179 int_x86_aesni_aesdec, 0>, VEX_4V;
5180 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5181 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5184 let Constraints = "$src1 = $dst" in {
5185 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5186 int_x86_aesni_aesenc>;
5187 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5188 int_x86_aesni_aesenclast>;
5189 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5190 int_x86_aesni_aesdec>;
5191 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5192 int_x86_aesni_aesdeclast>;
5195 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5196 (AESENCrr VR128:$src1, VR128:$src2)>;
5197 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5198 (AESENCrm VR128:$src1, addr:$src2)>;
5199 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5200 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5201 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5202 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5203 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5204 (AESDECrr VR128:$src1, VR128:$src2)>;
5205 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5206 (AESDECrm VR128:$src1, addr:$src2)>;
5207 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5208 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5209 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5210 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5212 // Perform the AES InvMixColumn Transformation
5213 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5214 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5216 "vaesimc\t{$src1, $dst|$dst, $src1}",
5218 (int_x86_aesni_aesimc VR128:$src1))]>,
5220 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5221 (ins i128mem:$src1),
5222 "vaesimc\t{$src1, $dst|$dst, $src1}",
5224 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5227 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5229 "aesimc\t{$src1, $dst|$dst, $src1}",
5231 (int_x86_aesni_aesimc VR128:$src1))]>,
5233 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5234 (ins i128mem:$src1),
5235 "aesimc\t{$src1, $dst|$dst, $src1}",
5237 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5240 // AES Round Key Generation Assist
5241 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5242 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5243 (ins VR128:$src1, i8imm:$src2),
5244 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5246 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5248 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5249 (ins i128mem:$src1, i8imm:$src2),
5250 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5252 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5256 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5257 (ins VR128:$src1, i8imm:$src2),
5258 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5260 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5262 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5263 (ins i128mem:$src1, i8imm:$src2),
5264 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5266 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5270 //===----------------------------------------------------------------------===//
5271 // CLMUL Instructions
5272 //===----------------------------------------------------------------------===//
5274 // Only the AVX version of CLMUL instructions are described here.
5276 // Carry-less Multiplication instructions
5277 let isAsmParserOnly = 1 in {
5278 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5279 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5280 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5283 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5284 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5285 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5289 multiclass avx_vpclmul<string asm> {
5290 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5291 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5294 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5295 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5298 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5299 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5300 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5301 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5303 } // isAsmParserOnly
5305 //===----------------------------------------------------------------------===//
5307 //===----------------------------------------------------------------------===//
5309 let isAsmParserOnly = 1 in {
5311 // Load from memory and broadcast to all elements of the destination operand
5312 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5313 X86MemOperand x86memop> :
5314 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>, VEX;
5317 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem>;
5318 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem>;
5319 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem>;
5320 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem>;
5322 // Insert packed floating-point values
5323 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5324 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5325 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5327 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5328 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5329 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5332 // Extract packed floating-point values
5333 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5334 (ins VR256:$src1, i8imm:$src2),
5335 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5337 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5338 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5339 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5342 // Conditional SIMD Packed Loads and Stores
5343 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr> {
5344 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5345 (ins VR128:$src1, f128mem:$src2),
5346 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5348 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5349 (ins VR256:$src1, f256mem:$src2),
5350 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5352 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5353 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5356 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5357 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5358 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5362 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps">;
5363 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd">;
5365 // Permute Floating-Point Values
5366 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5367 RegisterClass RC, X86MemOperand x86memop_f,
5368 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5369 Intrinsic IntVar, Intrinsic IntImm> {
5370 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5371 (ins RC:$src1, RC:$src2),
5372 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5373 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5374 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5375 (ins RC:$src1, x86memop_i:$src2),
5376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5377 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5379 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5380 (ins RC:$src1, i8imm:$src2),
5381 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5382 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5383 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5384 (ins x86memop_f:$src1, i8imm:$src2),
5385 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5386 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5389 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5390 memopv4f32, memopv4i32,
5391 int_x86_avx_vpermilvar_ps,
5392 int_x86_avx_vpermil_ps>;
5393 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5394 memopv8f32, memopv8i32,
5395 int_x86_avx_vpermilvar_ps_256,
5396 int_x86_avx_vpermil_ps_256>;
5397 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5398 memopv2f64, memopv2i64,
5399 int_x86_avx_vpermilvar_pd,
5400 int_x86_avx_vpermil_pd>;
5401 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5402 memopv4f64, memopv4i64,
5403 int_x86_avx_vpermilvar_pd_256,
5404 int_x86_avx_vpermil_pd_256>;
5406 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5407 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5408 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5410 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5411 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5412 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5415 // Zero All YMM registers
5416 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5417 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5419 // Zero Upper bits of YMM registers
5420 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5421 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5423 } // isAsmParserOnly
5425 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5426 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5427 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5428 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5429 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5430 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5432 def : Pat<(int_x86_avx_vperm2f128_ps_256
5433 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5434 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5435 def : Pat<(int_x86_avx_vperm2f128_pd_256
5436 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5437 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5438 def : Pat<(int_x86_avx_vperm2f128_si_256
5439 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5440 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;