1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Move Instructions. Register-to-register movss is not used for FR32
375 // register copies because it's a partial register update; FsMOVAPSrr is
376 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
377 // because INSERT_SUBREG requires that the insert be implementable in terms of
378 // a copy, and just mentioned, we don't use movss for copies.
379 let Constraints = "$src1 = $dst" in
380 def MOVSSrr : SSI<0x10, MRMSrcReg,
381 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
382 "movss\t{$src2, $dst|$dst, $src2}",
383 [(set (v4f32 VR128:$dst),
384 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
386 // Extract the low 32-bit value from one vector and insert it into another.
387 let AddedComplexity = 15 in
388 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
389 (MOVSSrr (v4f32 VR128:$src1),
390 (EXTRACT_SUBREG (v4f32 VR128:$src2), x86_subreg_ss))>;
392 // Implicitly promote a 32-bit scalar to a vector.
393 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
394 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, x86_subreg_ss)>;
396 // Loading from memory automatically zeroing upper bits.
397 let canFoldAsLoad = 1, isReMaterializable = 1 in
398 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
399 "movss\t{$src, $dst|$dst, $src}",
400 [(set FR32:$dst, (loadf32 addr:$src))]>;
402 // MOVSSrm zeros the high parts of the register; represent this
403 // with SUBREG_TO_REG.
404 let AddedComplexity = 20 in {
405 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
406 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
407 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
408 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
409 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
410 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
413 // Store scalar value to memory.
414 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
415 "movss\t{$src, $dst|$dst, $src}",
416 [(store FR32:$src, addr:$dst)]>;
418 // Extract and store.
419 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
422 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
424 // Conversion instructions
425 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
426 "cvttss2si\t{$src, $dst|$dst, $src}",
427 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
428 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
429 "cvttss2si\t{$src, $dst|$dst, $src}",
430 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
431 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
432 "cvtsi2ss\t{$src, $dst|$dst, $src}",
433 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
434 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
435 "cvtsi2ss\t{$src, $dst|$dst, $src}",
436 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
438 // Match intrinsics which expect XMM operand(s).
439 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
440 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
441 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
442 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
444 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
445 "cvtss2si\t{$src, $dst|$dst, $src}",
446 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
447 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (int_x86_sse_cvtss2si
450 (load addr:$src)))]>;
452 // Match intrinisics which expect MM and XMM operand(s).
453 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
454 "cvtps2pi\t{$src, $dst|$dst, $src}",
455 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
456 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
457 "cvtps2pi\t{$src, $dst|$dst, $src}",
458 [(set VR64:$dst, (int_x86_sse_cvtps2pi
459 (load addr:$src)))]>;
460 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttps2pi\t{$src, $dst|$dst, $src}",
462 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
463 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
464 "cvttps2pi\t{$src, $dst|$dst, $src}",
465 [(set VR64:$dst, (int_x86_sse_cvttps2pi
466 (load addr:$src)))]>;
467 let Constraints = "$src1 = $dst" in {
468 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
469 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
470 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
471 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
473 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
474 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
477 (load addr:$src2)))]>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
505 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
506 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
509 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
510 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
514 let Defs = [EFLAGS] in {
515 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
516 "ucomiss\t{$src2, $src1|$src1, $src2}",
517 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
518 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
519 "ucomiss\t{$src2, $src1|$src1, $src2}",
520 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
522 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
523 "comiss\t{$src2, $src1|$src1, $src2}", []>;
524 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
525 "comiss\t{$src2, $src1|$src1, $src2}", []>;
529 // Aliases to match intrinsics which expect XMM operand(s).
530 let Constraints = "$src1 = $dst" in {
531 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
533 (ins VR128:$src1, VR128:$src, SSECC:$cc),
534 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
535 [(set VR128:$dst, (int_x86_sse_cmp_ss
537 VR128:$src, imm:$cc))]>;
538 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
540 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
541 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
542 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
543 (load addr:$src), imm:$cc))]>;
546 let Defs = [EFLAGS] in {
547 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
548 "ucomiss\t{$src2, $src1|$src1, $src2}",
549 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
551 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
552 "ucomiss\t{$src2, $src1|$src1, $src2}",
553 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
554 (load addr:$src2)))]>;
556 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
557 "comiss\t{$src2, $src1|$src1, $src2}",
558 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
560 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
561 "comiss\t{$src2, $src1|$src1, $src2}",
562 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
563 (load addr:$src2)))]>;
566 // Aliases of packed SSE1 instructions for scalar use. These all have names
567 // that start with 'Fs'.
569 // Alias instructions that map fld0 to pxor for sse.
570 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
572 // FIXME: Set encoding to pseudo!
573 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
574 [(set FR32:$dst, fp32imm0)]>,
575 Requires<[HasSSE1]>, TB, OpSize;
577 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
579 let neverHasSideEffects = 1 in
580 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
581 "movaps\t{$src, $dst|$dst, $src}", []>;
583 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
585 let canFoldAsLoad = 1, isReMaterializable = 1 in
586 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
587 "movaps\t{$src, $dst|$dst, $src}",
588 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
590 // Alias bitwise logical operations using SSE logical ops on packed FP values.
591 let Constraints = "$src1 = $dst" in {
592 let isCommutable = 1 in {
593 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
594 (ins FR32:$src1, FR32:$src2),
595 "andps\t{$src2, $dst|$dst, $src2}",
596 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
597 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
598 (ins FR32:$src1, FR32:$src2),
599 "orps\t{$src2, $dst|$dst, $src2}",
600 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
601 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
602 (ins FR32:$src1, FR32:$src2),
603 "xorps\t{$src2, $dst|$dst, $src2}",
604 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
607 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
608 (ins FR32:$src1, f128mem:$src2),
609 "andps\t{$src2, $dst|$dst, $src2}",
610 [(set FR32:$dst, (X86fand FR32:$src1,
611 (memopfsf32 addr:$src2)))]>;
612 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
613 (ins FR32:$src1, f128mem:$src2),
614 "orps\t{$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86for FR32:$src1,
616 (memopfsf32 addr:$src2)))]>;
617 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
618 (ins FR32:$src1, f128mem:$src2),
619 "xorps\t{$src2, $dst|$dst, $src2}",
620 [(set FR32:$dst, (X86fxor FR32:$src1,
621 (memopfsf32 addr:$src2)))]>;
623 let neverHasSideEffects = 1 in {
624 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
625 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
626 "andnps\t{$src2, $dst|$dst, $src2}", []>;
628 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
629 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
630 "andnps\t{$src2, $dst|$dst, $src2}", []>;
634 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
636 /// In addition, we also have a special variant of the scalar form here to
637 /// represent the associated intrinsic operation. This form is unlike the
638 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
639 /// and leaves the top elements unmodified (therefore these cannot be commuted).
641 /// These three forms can each be reg+reg or reg+mem, so there are a total of
642 /// six "instructions".
644 let Constraints = "$src1 = $dst" in {
645 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
646 SDNode OpNode, Intrinsic F32Int,
647 bit Commutable = 0> {
648 // Scalar operation, reg+reg.
649 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
650 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
651 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
652 let isCommutable = Commutable;
655 // Scalar operation, reg+mem.
656 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
657 (ins FR32:$src1, f32mem:$src2),
658 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
659 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
661 // Vector operation, reg+reg.
662 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
663 (ins VR128:$src1, VR128:$src2),
664 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
665 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
666 let isCommutable = Commutable;
669 // Vector operation, reg+mem.
670 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
671 (ins VR128:$src1, f128mem:$src2),
672 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
673 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
675 // Intrinsic operation, reg+reg.
676 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
677 (ins VR128:$src1, VR128:$src2),
678 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
679 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
681 // Intrinsic operation, reg+mem.
682 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
683 (ins VR128:$src1, ssmem:$src2),
684 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
685 [(set VR128:$dst, (F32Int VR128:$src1,
686 sse_load_f32:$src2))]>;
690 // Arithmetic instructions
691 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
692 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
693 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
694 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
696 /// sse1_fp_binop_rm - Other SSE1 binops
698 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
699 /// instructions for a full-vector intrinsic form. Operations that map
700 /// onto C operators don't use this form since they just use the plain
701 /// vector form instead of having a separate vector intrinsic form.
703 /// This provides a total of eight "instructions".
705 let Constraints = "$src1 = $dst" in {
706 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
710 bit Commutable = 0> {
712 // Scalar operation, reg+reg.
713 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
714 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
715 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
716 let isCommutable = Commutable;
719 // Scalar operation, reg+mem.
720 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
721 (ins FR32:$src1, f32mem:$src2),
722 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
723 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
725 // Vector operation, reg+reg.
726 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
727 (ins VR128:$src1, VR128:$src2),
728 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
729 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
730 let isCommutable = Commutable;
733 // Vector operation, reg+mem.
734 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
735 (ins VR128:$src1, f128mem:$src2),
736 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
737 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
739 // Intrinsic operation, reg+reg.
740 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
741 (ins VR128:$src1, VR128:$src2),
742 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
743 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
744 let isCommutable = Commutable;
747 // Intrinsic operation, reg+mem.
748 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
749 (ins VR128:$src1, ssmem:$src2),
750 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
751 [(set VR128:$dst, (F32Int VR128:$src1,
752 sse_load_f32:$src2))]>;
754 // Vector intrinsic operation, reg+reg.
755 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
756 (ins VR128:$src1, VR128:$src2),
757 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
758 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
759 let isCommutable = Commutable;
762 // Vector intrinsic operation, reg+mem.
763 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
764 (ins VR128:$src1, f128mem:$src2),
765 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
766 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
770 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
771 int_x86_sse_max_ss, int_x86_sse_max_ps>;
772 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
773 int_x86_sse_min_ss, int_x86_sse_min_ps>;
775 //===----------------------------------------------------------------------===//
776 // SSE packed FP Instructions
779 let neverHasSideEffects = 1 in
780 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
781 "movaps\t{$src, $dst|$dst, $src}", []>;
782 let canFoldAsLoad = 1, isReMaterializable = 1 in
783 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
784 "movaps\t{$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
787 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
788 "movaps\t{$src, $dst|$dst, $src}",
789 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
791 let neverHasSideEffects = 1 in
792 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
793 "movups\t{$src, $dst|$dst, $src}", []>;
794 let canFoldAsLoad = 1, isReMaterializable = 1 in
795 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
796 "movups\t{$src, $dst|$dst, $src}",
797 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
798 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
799 "movups\t{$src, $dst|$dst, $src}",
800 [(store (v4f32 VR128:$src), addr:$dst)]>;
802 // Intrinsic forms of MOVUPS load and store
803 let canFoldAsLoad = 1, isReMaterializable = 1 in
804 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
805 "movups\t{$src, $dst|$dst, $src}",
806 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
807 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
808 "movups\t{$src, $dst|$dst, $src}",
809 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
811 let Constraints = "$src1 = $dst" in {
812 let AddedComplexity = 20 in {
813 def MOVLPSrm : PSI<0x12, MRMSrcMem,
814 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
815 "movlps\t{$src2, $dst|$dst, $src2}",
818 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
819 def MOVHPSrm : PSI<0x16, MRMSrcMem,
820 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
821 "movhps\t{$src2, $dst|$dst, $src2}",
823 (movlhps VR128:$src1,
824 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
826 } // Constraints = "$src1 = $dst"
829 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
830 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
832 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
833 "movlps\t{$src, $dst|$dst, $src}",
834 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
835 (iPTR 0))), addr:$dst)]>;
837 // v2f64 extract element 1 is always custom lowered to unpack high to low
838 // and extract element 0 so the non-store version isn't too horrible.
839 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
840 "movhps\t{$src, $dst|$dst, $src}",
841 [(store (f64 (vector_extract
842 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
843 (undef)), (iPTR 0))), addr:$dst)]>;
845 let Constraints = "$src1 = $dst" in {
846 let AddedComplexity = 20 in {
847 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
848 (ins VR128:$src1, VR128:$src2),
849 "movlhps\t{$src2, $dst|$dst, $src2}",
851 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
853 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
854 (ins VR128:$src1, VR128:$src2),
855 "movhlps\t{$src2, $dst|$dst, $src2}",
857 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
859 } // Constraints = "$src1 = $dst"
861 let AddedComplexity = 20 in {
862 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
863 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
864 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
865 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
872 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
874 /// In addition, we also have a special variant of the scalar form here to
875 /// represent the associated intrinsic operation. This form is unlike the
876 /// plain scalar form, in that it takes an entire vector (instead of a
877 /// scalar) and leaves the top elements undefined.
879 /// And, we have a special variant form for a full-vector intrinsic form.
881 /// These four forms can each have a reg or a mem operand, so there are a
882 /// total of eight "instructions".
884 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
888 bit Commutable = 0> {
889 // Scalar operation, reg.
890 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
891 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
892 [(set FR32:$dst, (OpNode FR32:$src))]> {
893 let isCommutable = Commutable;
896 // Scalar operation, mem.
897 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
898 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
899 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
900 Requires<[HasSSE1, OptForSize]>;
902 // Vector operation, reg.
903 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
904 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
905 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
906 let isCommutable = Commutable;
909 // Vector operation, mem.
910 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
912 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
914 // Intrinsic operation, reg.
915 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
916 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
917 [(set VR128:$dst, (F32Int VR128:$src))]> {
918 let isCommutable = Commutable;
921 // Intrinsic operation, mem.
922 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
923 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
924 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
926 // Vector intrinsic operation, reg
927 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
929 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
930 let isCommutable = Commutable;
933 // Vector intrinsic operation, mem
934 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
935 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
936 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
940 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
941 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
943 // Reciprocal approximations. Note that these typically require refinement
944 // in order to obtain suitable precision.
945 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
946 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
947 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
948 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
951 let Constraints = "$src1 = $dst" in {
952 let isCommutable = 1 in {
953 def ANDPSrr : PSI<0x54, MRMSrcReg,
954 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
955 "andps\t{$src2, $dst|$dst, $src2}",
956 [(set VR128:$dst, (v2i64
957 (and VR128:$src1, VR128:$src2)))]>;
958 def ORPSrr : PSI<0x56, MRMSrcReg,
959 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
960 "orps\t{$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v2i64
962 (or VR128:$src1, VR128:$src2)))]>;
963 def XORPSrr : PSI<0x57, MRMSrcReg,
964 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
965 "xorps\t{$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (v2i64
967 (xor VR128:$src1, VR128:$src2)))]>;
970 def ANDPSrm : PSI<0x54, MRMSrcMem,
971 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
972 "andps\t{$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
974 (memopv2i64 addr:$src2)))]>;
975 def ORPSrm : PSI<0x56, MRMSrcMem,
976 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
977 "orps\t{$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
979 (memopv2i64 addr:$src2)))]>;
980 def XORPSrm : PSI<0x57, MRMSrcMem,
981 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
982 "xorps\t{$src2, $dst|$dst, $src2}",
983 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
984 (memopv2i64 addr:$src2)))]>;
985 def ANDNPSrr : PSI<0x55, MRMSrcReg,
986 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
987 "andnps\t{$src2, $dst|$dst, $src2}",
989 (v2i64 (and (xor VR128:$src1,
990 (bc_v2i64 (v4i32 immAllOnesV))),
992 def ANDNPSrm : PSI<0x55, MRMSrcMem,
993 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
994 "andnps\t{$src2, $dst|$dst, $src2}",
996 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
997 (bc_v2i64 (v4i32 immAllOnesV))),
998 (memopv2i64 addr:$src2))))]>;
1001 let Constraints = "$src1 = $dst" in {
1002 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1003 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1004 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1006 VR128:$src, imm:$cc))]>;
1007 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1008 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1009 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1011 (memop addr:$src), imm:$cc))]>;
1013 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1014 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1015 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1016 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1018 // Shuffle and unpack instructions
1019 let Constraints = "$src1 = $dst" in {
1020 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1021 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1022 (outs VR128:$dst), (ins VR128:$src1,
1023 VR128:$src2, i8imm:$src3),
1024 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1026 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1027 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1028 (outs VR128:$dst), (ins VR128:$src1,
1029 f128mem:$src2, i8imm:$src3),
1030 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1033 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1035 let AddedComplexity = 10 in {
1036 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1037 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1038 "unpckhps\t{$src2, $dst|$dst, $src2}",
1040 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1041 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1042 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1043 "unpckhps\t{$src2, $dst|$dst, $src2}",
1045 (v4f32 (unpckh VR128:$src1,
1046 (memopv4f32 addr:$src2))))]>;
1048 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1049 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1050 "unpcklps\t{$src2, $dst|$dst, $src2}",
1052 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1053 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1054 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1055 "unpcklps\t{$src2, $dst|$dst, $src2}",
1057 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1058 } // AddedComplexity
1059 } // Constraints = "$src1 = $dst"
1062 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1063 "movmskps\t{$src, $dst|$dst, $src}",
1064 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1065 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1066 "movmskpd\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1069 // Prefetch intrinsic.
1070 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1071 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1072 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1073 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1074 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1075 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1076 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1077 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1079 // Non-temporal stores
1080 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1081 "movntps\t{$src, $dst|$dst, $src}",
1082 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1084 let AddedComplexity = 400 in { // Prefer non-temporal versions
1085 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1086 "movntps\t{$src, $dst|$dst, $src}",
1087 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1090 "movntdq\t{$src, $dst|$dst, $src}",
1091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1093 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1094 "movnti\t{$src, $dst|$dst, $src}",
1095 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1096 TB, Requires<[HasSSE2]>;
1098 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1099 "movnti\t{$src, $dst|$dst, $src}",
1100 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1101 TB, Requires<[HasSSE2]>;
1104 // Load, store, and memory fence
1105 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1108 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1109 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1110 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1111 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1113 // Alias instructions that map zero vector to pxor / xorp* for sse.
1114 // We set canFoldAsLoad because this can be converted to a constant-pool
1115 // load of an all-zeros value if folding it would be beneficial.
1116 // FIXME: Change encoding to pseudo!
1117 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1118 isCodeGenOnly = 1 in
1119 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1120 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1122 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1123 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1124 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1125 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1126 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1128 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1129 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
1131 //===---------------------------------------------------------------------===//
1132 // SSE2 Instructions
1133 //===---------------------------------------------------------------------===//
1135 // Move Instructions. Register-to-register movsd is not used for FR64
1136 // register copies because it's a partial register update; FsMOVAPDrr is
1137 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1138 // because INSERT_SUBREG requires that the insert be implementable in terms of
1139 // a copy, and just mentioned, we don't use movsd for copies.
1140 let Constraints = "$src1 = $dst" in
1141 def MOVSDrr : SDI<0x10, MRMSrcReg,
1142 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1143 "movsd\t{$src2, $dst|$dst, $src2}",
1144 [(set (v2f64 VR128:$dst),
1145 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1147 // Extract the low 64-bit value from one vector and insert it into another.
1148 let AddedComplexity = 15 in
1149 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1150 (MOVSDrr (v2f64 VR128:$src1),
1151 (EXTRACT_SUBREG (v2f64 VR128:$src2), x86_subreg_sd))>;
1153 // Implicitly promote a 64-bit scalar to a vector.
1154 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1155 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, x86_subreg_sd)>;
1157 // Loading from memory automatically zeroing upper bits.
1158 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1159 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1160 "movsd\t{$src, $dst|$dst, $src}",
1161 [(set FR64:$dst, (loadf64 addr:$src))]>;
1163 // MOVSDrm zeros the high parts of the register; represent this
1164 // with SUBREG_TO_REG.
1165 let AddedComplexity = 20 in {
1166 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1167 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1168 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1169 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1170 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1171 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1172 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1173 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1174 def : Pat<(v2f64 (X86vzload addr:$src)),
1175 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1178 // Store scalar value to memory.
1179 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1180 "movsd\t{$src, $dst|$dst, $src}",
1181 [(store FR64:$src, addr:$dst)]>;
1183 // Extract and store.
1184 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1187 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
1189 // Conversion instructions
1190 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1191 "cvttsd2si\t{$src, $dst|$dst, $src}",
1192 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1193 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1194 "cvttsd2si\t{$src, $dst|$dst, $src}",
1195 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1196 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1197 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1198 [(set FR32:$dst, (fround FR64:$src))]>;
1199 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1200 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1201 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1202 Requires<[HasSSE2, OptForSize]>;
1203 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1204 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1205 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1206 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1207 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1208 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1210 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1211 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1212 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1213 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1214 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1215 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1216 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1217 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1218 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1219 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1220 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1221 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1222 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1223 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1224 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1225 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1226 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1227 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1228 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1229 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1231 // SSE2 instructions with XS prefix
1232 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1233 "cvtss2sd\t{$src, $dst|$dst, $src}",
1234 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1235 Requires<[HasSSE2]>;
1236 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1237 "cvtss2sd\t{$src, $dst|$dst, $src}",
1238 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1239 Requires<[HasSSE2, OptForSize]>;
1241 def : Pat<(extloadf32 addr:$src),
1242 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1243 Requires<[HasSSE2, OptForSpeed]>;
1245 // Match intrinsics which expect XMM operand(s).
1246 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1247 "cvtsd2si\t{$src, $dst|$dst, $src}",
1248 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1249 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1250 "cvtsd2si\t{$src, $dst|$dst, $src}",
1251 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1252 (load addr:$src)))]>;
1254 // Match intrinisics which expect MM and XMM operand(s).
1255 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1256 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1257 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1258 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1259 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1260 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1261 (memop addr:$src)))]>;
1262 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1263 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1264 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1265 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1266 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1267 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1268 (memop addr:$src)))]>;
1269 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1270 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1271 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1272 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1273 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1274 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1275 (load addr:$src)))]>;
1277 // Aliases for intrinsics
1278 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1279 "cvttsd2si\t{$src, $dst|$dst, $src}",
1281 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1282 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1283 "cvttsd2si\t{$src, $dst|$dst, $src}",
1284 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1285 (load addr:$src)))]>;
1287 // Comparison instructions
1288 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1289 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1290 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1291 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1293 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1294 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1295 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1298 let Defs = [EFLAGS] in {
1299 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1300 "ucomisd\t{$src2, $src1|$src1, $src2}",
1301 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1302 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1303 "ucomisd\t{$src2, $src1|$src1, $src2}",
1304 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1305 } // Defs = [EFLAGS]
1307 // Aliases to match intrinsics which expect XMM operand(s).
1308 let Constraints = "$src1 = $dst" in {
1309 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1311 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1312 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1313 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1314 VR128:$src, imm:$cc))]>;
1315 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1317 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1318 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1319 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1320 (load addr:$src), imm:$cc))]>;
1323 let Defs = [EFLAGS] in {
1324 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1325 "ucomisd\t{$src2, $src1|$src1, $src2}",
1326 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1328 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1329 "ucomisd\t{$src2, $src1|$src1, $src2}",
1330 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1331 (load addr:$src2)))]>;
1333 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1334 "comisd\t{$src2, $src1|$src1, $src2}",
1335 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1337 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1338 "comisd\t{$src2, $src1|$src1, $src2}",
1339 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1340 (load addr:$src2)))]>;
1341 } // Defs = [EFLAGS]
1343 // Aliases of packed SSE2 instructions for scalar use. These all have names
1344 // that start with 'Fs'.
1346 // Alias instructions that map fld0 to pxor for sse.
1347 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1348 canFoldAsLoad = 1 in
1349 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1350 [(set FR64:$dst, fpimm0)]>,
1351 Requires<[HasSSE2]>, TB, OpSize;
1353 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1355 let neverHasSideEffects = 1 in
1356 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1357 "movapd\t{$src, $dst|$dst, $src}", []>;
1359 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1361 let canFoldAsLoad = 1, isReMaterializable = 1 in
1362 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1363 "movapd\t{$src, $dst|$dst, $src}",
1364 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1366 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1367 let Constraints = "$src1 = $dst" in {
1368 let isCommutable = 1 in {
1369 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1370 (ins FR64:$src1, FR64:$src2),
1371 "andpd\t{$src2, $dst|$dst, $src2}",
1372 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1373 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1374 (ins FR64:$src1, FR64:$src2),
1375 "orpd\t{$src2, $dst|$dst, $src2}",
1376 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1377 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1378 (ins FR64:$src1, FR64:$src2),
1379 "xorpd\t{$src2, $dst|$dst, $src2}",
1380 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1383 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1384 (ins FR64:$src1, f128mem:$src2),
1385 "andpd\t{$src2, $dst|$dst, $src2}",
1386 [(set FR64:$dst, (X86fand FR64:$src1,
1387 (memopfsf64 addr:$src2)))]>;
1388 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1389 (ins FR64:$src1, f128mem:$src2),
1390 "orpd\t{$src2, $dst|$dst, $src2}",
1391 [(set FR64:$dst, (X86for FR64:$src1,
1392 (memopfsf64 addr:$src2)))]>;
1393 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1394 (ins FR64:$src1, f128mem:$src2),
1395 "xorpd\t{$src2, $dst|$dst, $src2}",
1396 [(set FR64:$dst, (X86fxor FR64:$src1,
1397 (memopfsf64 addr:$src2)))]>;
1399 let neverHasSideEffects = 1 in {
1400 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1401 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1402 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1404 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1405 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1406 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1410 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1412 /// In addition, we also have a special variant of the scalar form here to
1413 /// represent the associated intrinsic operation. This form is unlike the
1414 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1415 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1417 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1418 /// six "instructions".
1420 let Constraints = "$src1 = $dst" in {
1421 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1422 SDNode OpNode, Intrinsic F64Int,
1423 bit Commutable = 0> {
1424 // Scalar operation, reg+reg.
1425 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1426 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1427 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1428 let isCommutable = Commutable;
1431 // Scalar operation, reg+mem.
1432 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1433 (ins FR64:$src1, f64mem:$src2),
1434 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1435 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1437 // Vector operation, reg+reg.
1438 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1439 (ins VR128:$src1, VR128:$src2),
1440 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1441 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1442 let isCommutable = Commutable;
1445 // Vector operation, reg+mem.
1446 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1447 (ins VR128:$src1, f128mem:$src2),
1448 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1449 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1451 // Intrinsic operation, reg+reg.
1452 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1453 (ins VR128:$src1, VR128:$src2),
1454 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1455 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1457 // Intrinsic operation, reg+mem.
1458 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1459 (ins VR128:$src1, sdmem:$src2),
1460 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1461 [(set VR128:$dst, (F64Int VR128:$src1,
1462 sse_load_f64:$src2))]>;
1466 // Arithmetic instructions
1467 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1468 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1469 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1470 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1472 /// sse2_fp_binop_rm - Other SSE2 binops
1474 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1475 /// instructions for a full-vector intrinsic form. Operations that map
1476 /// onto C operators don't use this form since they just use the plain
1477 /// vector form instead of having a separate vector intrinsic form.
1479 /// This provides a total of eight "instructions".
1481 let Constraints = "$src1 = $dst" in {
1482 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1486 bit Commutable = 0> {
1488 // Scalar operation, reg+reg.
1489 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1490 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1491 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1492 let isCommutable = Commutable;
1495 // Scalar operation, reg+mem.
1496 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1497 (ins FR64:$src1, f64mem:$src2),
1498 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1499 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1501 // Vector operation, reg+reg.
1502 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1503 (ins VR128:$src1, VR128:$src2),
1504 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1505 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1506 let isCommutable = Commutable;
1509 // Vector operation, reg+mem.
1510 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1511 (ins VR128:$src1, f128mem:$src2),
1512 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1513 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1515 // Intrinsic operation, reg+reg.
1516 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1517 (ins VR128:$src1, VR128:$src2),
1518 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1519 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1520 let isCommutable = Commutable;
1523 // Intrinsic operation, reg+mem.
1524 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1525 (ins VR128:$src1, sdmem:$src2),
1526 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1527 [(set VR128:$dst, (F64Int VR128:$src1,
1528 sse_load_f64:$src2))]>;
1530 // Vector intrinsic operation, reg+reg.
1531 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1532 (ins VR128:$src1, VR128:$src2),
1533 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1534 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1535 let isCommutable = Commutable;
1538 // Vector intrinsic operation, reg+mem.
1539 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1540 (ins VR128:$src1, f128mem:$src2),
1541 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1542 [(set VR128:$dst, (V2F64Int VR128:$src1,
1543 (memopv2f64 addr:$src2)))]>;
1547 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1548 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1549 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1550 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1552 //===---------------------------------------------------------------------===//
1553 // SSE packed FP Instructions
1555 // Move Instructions
1556 let neverHasSideEffects = 1 in
1557 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1558 "movapd\t{$src, $dst|$dst, $src}", []>;
1559 let canFoldAsLoad = 1, isReMaterializable = 1 in
1560 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1561 "movapd\t{$src, $dst|$dst, $src}",
1562 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1564 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1565 "movapd\t{$src, $dst|$dst, $src}",
1566 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1568 let neverHasSideEffects = 1 in
1569 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1570 "movupd\t{$src, $dst|$dst, $src}", []>;
1571 let canFoldAsLoad = 1 in
1572 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1573 "movupd\t{$src, $dst|$dst, $src}",
1574 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1575 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1576 "movupd\t{$src, $dst|$dst, $src}",
1577 [(store (v2f64 VR128:$src), addr:$dst)]>;
1579 // Intrinsic forms of MOVUPD load and store
1580 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1581 "movupd\t{$src, $dst|$dst, $src}",
1582 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1583 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1584 "movupd\t{$src, $dst|$dst, $src}",
1585 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1587 let Constraints = "$src1 = $dst" in {
1588 let AddedComplexity = 20 in {
1589 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1590 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1591 "movlpd\t{$src2, $dst|$dst, $src2}",
1593 (v2f64 (movlp VR128:$src1,
1594 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1595 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1596 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1597 "movhpd\t{$src2, $dst|$dst, $src2}",
1599 (v2f64 (movlhps VR128:$src1,
1600 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1601 } // AddedComplexity
1602 } // Constraints = "$src1 = $dst"
1604 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1605 "movlpd\t{$src, $dst|$dst, $src}",
1606 [(store (f64 (vector_extract (v2f64 VR128:$src),
1607 (iPTR 0))), addr:$dst)]>;
1609 // v2f64 extract element 1 is always custom lowered to unpack high to low
1610 // and extract element 0 so the non-store version isn't too horrible.
1611 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1612 "movhpd\t{$src, $dst|$dst, $src}",
1613 [(store (f64 (vector_extract
1614 (v2f64 (unpckh VR128:$src, (undef))),
1615 (iPTR 0))), addr:$dst)]>;
1617 // SSE2 instructions without OpSize prefix
1618 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1619 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1620 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1621 TB, Requires<[HasSSE2]>;
1622 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1623 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1624 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1625 (bitconvert (memopv2i64 addr:$src))))]>,
1626 TB, Requires<[HasSSE2]>;
1628 // SSE2 instructions with XS prefix
1629 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1630 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1631 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1632 XS, Requires<[HasSSE2]>;
1633 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1634 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1635 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1636 (bitconvert (memopv2i64 addr:$src))))]>,
1637 XS, Requires<[HasSSE2]>;
1639 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1640 "cvtps2dq\t{$src, $dst|$dst, $src}",
1641 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1642 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1643 "cvtps2dq\t{$src, $dst|$dst, $src}",
1644 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1645 (memop addr:$src)))]>;
1646 // SSE2 packed instructions with XS prefix
1647 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1648 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1649 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1650 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1652 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1653 "cvttps2dq\t{$src, $dst|$dst, $src}",
1655 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1656 XS, Requires<[HasSSE2]>;
1657 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1658 "cvttps2dq\t{$src, $dst|$dst, $src}",
1659 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1660 (memop addr:$src)))]>,
1661 XS, Requires<[HasSSE2]>;
1663 // SSE2 packed instructions with XD prefix
1664 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1665 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1666 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1667 XD, Requires<[HasSSE2]>;
1668 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1669 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1670 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1671 (memop addr:$src)))]>,
1672 XD, Requires<[HasSSE2]>;
1674 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1675 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1676 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1677 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1678 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1679 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1680 (memop addr:$src)))]>;
1682 // SSE2 instructions without OpSize prefix
1683 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1684 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1685 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1686 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1688 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1689 "cvtps2pd\t{$src, $dst|$dst, $src}",
1690 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1691 TB, Requires<[HasSSE2]>;
1692 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1693 "cvtps2pd\t{$src, $dst|$dst, $src}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1695 (load addr:$src)))]>,
1696 TB, Requires<[HasSSE2]>;
1698 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1699 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1700 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1701 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1704 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1705 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1706 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1707 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1708 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1709 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1710 (memop addr:$src)))]>;
1712 // Match intrinsics which expect XMM operand(s).
1713 // Aliases for intrinsics
1714 let Constraints = "$src1 = $dst" in {
1715 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1716 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1717 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1718 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1720 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1721 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1722 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1724 (loadi32 addr:$src2)))]>;
1725 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1726 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1727 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1728 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1730 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1731 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1732 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1733 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1734 (load addr:$src2)))]>;
1735 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1736 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1737 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1738 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1739 VR128:$src2))]>, XS,
1740 Requires<[HasSSE2]>;
1741 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1742 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1743 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1744 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1745 (load addr:$src2)))]>, XS,
1746 Requires<[HasSSE2]>;
1751 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1753 /// In addition, we also have a special variant of the scalar form here to
1754 /// represent the associated intrinsic operation. This form is unlike the
1755 /// plain scalar form, in that it takes an entire vector (instead of a
1756 /// scalar) and leaves the top elements undefined.
1758 /// And, we have a special variant form for a full-vector intrinsic form.
1760 /// These four forms can each have a reg or a mem operand, so there are a
1761 /// total of eight "instructions".
1763 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1767 bit Commutable = 0> {
1768 // Scalar operation, reg.
1769 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1770 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1771 [(set FR64:$dst, (OpNode FR64:$src))]> {
1772 let isCommutable = Commutable;
1775 // Scalar operation, mem.
1776 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1777 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1778 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1780 // Vector operation, reg.
1781 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1782 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1783 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1784 let isCommutable = Commutable;
1787 // Vector operation, mem.
1788 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1789 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1790 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1792 // Intrinsic operation, reg.
1793 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1794 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1795 [(set VR128:$dst, (F64Int VR128:$src))]> {
1796 let isCommutable = Commutable;
1799 // Intrinsic operation, mem.
1800 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1801 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1802 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1804 // Vector intrinsic operation, reg
1805 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1806 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1807 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1808 let isCommutable = Commutable;
1811 // Vector intrinsic operation, mem
1812 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1813 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1814 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1818 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1819 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1821 // There is no f64 version of the reciprocal approximation instructions.
1824 let Constraints = "$src1 = $dst" in {
1825 let isCommutable = 1 in {
1826 def ANDPDrr : PDI<0x54, MRMSrcReg,
1827 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1828 "andpd\t{$src2, $dst|$dst, $src2}",
1830 (and (bc_v2i64 (v2f64 VR128:$src1)),
1831 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1832 def ORPDrr : PDI<0x56, MRMSrcReg,
1833 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1834 "orpd\t{$src2, $dst|$dst, $src2}",
1836 (or (bc_v2i64 (v2f64 VR128:$src1)),
1837 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1838 def XORPDrr : PDI<0x57, MRMSrcReg,
1839 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1840 "xorpd\t{$src2, $dst|$dst, $src2}",
1842 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1843 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1846 def ANDPDrm : PDI<0x54, MRMSrcMem,
1847 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1848 "andpd\t{$src2, $dst|$dst, $src2}",
1850 (and (bc_v2i64 (v2f64 VR128:$src1)),
1851 (memopv2i64 addr:$src2)))]>;
1852 def ORPDrm : PDI<0x56, MRMSrcMem,
1853 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1854 "orpd\t{$src2, $dst|$dst, $src2}",
1856 (or (bc_v2i64 (v2f64 VR128:$src1)),
1857 (memopv2i64 addr:$src2)))]>;
1858 def XORPDrm : PDI<0x57, MRMSrcMem,
1859 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1860 "xorpd\t{$src2, $dst|$dst, $src2}",
1862 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1863 (memopv2i64 addr:$src2)))]>;
1864 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1865 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1866 "andnpd\t{$src2, $dst|$dst, $src2}",
1868 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1869 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1870 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1871 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1872 "andnpd\t{$src2, $dst|$dst, $src2}",
1874 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1875 (memopv2i64 addr:$src2)))]>;
1878 let Constraints = "$src1 = $dst" in {
1879 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1880 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1881 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1882 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1883 VR128:$src, imm:$cc))]>;
1884 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1885 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1886 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1887 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1888 (memop addr:$src), imm:$cc))]>;
1890 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1891 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1892 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1893 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1895 // Shuffle and unpack instructions
1896 let Constraints = "$src1 = $dst" in {
1897 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1898 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1899 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1901 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1902 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1903 (outs VR128:$dst), (ins VR128:$src1,
1904 f128mem:$src2, i8imm:$src3),
1905 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1908 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1910 let AddedComplexity = 10 in {
1911 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1912 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1913 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1915 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1916 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1917 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1918 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1920 (v2f64 (unpckh VR128:$src1,
1921 (memopv2f64 addr:$src2))))]>;
1923 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1924 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1925 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1927 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1928 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1929 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1930 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1932 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1933 } // AddedComplexity
1934 } // Constraints = "$src1 = $dst"
1937 //===---------------------------------------------------------------------===//
1938 // SSE integer instructions
1939 let ExeDomain = SSEPackedInt in {
1941 // Move Instructions
1942 let neverHasSideEffects = 1 in
1943 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1944 "movdqa\t{$src, $dst|$dst, $src}", []>;
1945 let canFoldAsLoad = 1, mayLoad = 1 in
1946 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1947 "movdqa\t{$src, $dst|$dst, $src}",
1948 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1950 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1951 "movdqa\t{$src, $dst|$dst, $src}",
1952 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1953 let canFoldAsLoad = 1, mayLoad = 1 in
1954 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1955 "movdqu\t{$src, $dst|$dst, $src}",
1956 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1957 XS, Requires<[HasSSE2]>;
1959 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1960 "movdqu\t{$src, $dst|$dst, $src}",
1961 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1962 XS, Requires<[HasSSE2]>;
1964 // Intrinsic forms of MOVDQU load and store
1965 let canFoldAsLoad = 1 in
1966 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1967 "movdqu\t{$src, $dst|$dst, $src}",
1968 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1969 XS, Requires<[HasSSE2]>;
1970 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1971 "movdqu\t{$src, $dst|$dst, $src}",
1972 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1973 XS, Requires<[HasSSE2]>;
1975 let Constraints = "$src1 = $dst" in {
1977 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1978 bit Commutable = 0> {
1979 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1980 (ins VR128:$src1, VR128:$src2),
1981 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1982 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1983 let isCommutable = Commutable;
1985 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1986 (ins VR128:$src1, i128mem:$src2),
1987 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1988 [(set VR128:$dst, (IntId VR128:$src1,
1989 (bitconvert (memopv2i64
1993 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1995 Intrinsic IntId, Intrinsic IntId2> {
1996 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1997 (ins VR128:$src1, VR128:$src2),
1998 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1999 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2000 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2001 (ins VR128:$src1, i128mem:$src2),
2002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2003 [(set VR128:$dst, (IntId VR128:$src1,
2004 (bitconvert (memopv2i64 addr:$src2))))]>;
2005 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2006 (ins VR128:$src1, i32i8imm:$src2),
2007 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2008 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2011 /// PDI_binop_rm - Simple SSE2 binary operator.
2012 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2013 ValueType OpVT, bit Commutable = 0> {
2014 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2015 (ins VR128:$src1, VR128:$src2),
2016 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2017 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2018 let isCommutable = Commutable;
2020 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2021 (ins VR128:$src1, i128mem:$src2),
2022 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2023 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2024 (bitconvert (memopv2i64 addr:$src2)))))]>;
2027 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2029 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2030 /// to collapse (bitconvert VT to VT) into its operand.
2032 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2033 bit Commutable = 0> {
2034 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2035 (ins VR128:$src1, VR128:$src2),
2036 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2037 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2038 let isCommutable = Commutable;
2040 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2041 (ins VR128:$src1, i128mem:$src2),
2042 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2043 [(set VR128:$dst, (OpNode VR128:$src1,
2044 (memopv2i64 addr:$src2)))]>;
2047 } // Constraints = "$src1 = $dst"
2048 } // ExeDomain = SSEPackedInt
2050 // 128-bit Integer Arithmetic
2052 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2053 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2054 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2055 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2057 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2058 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2059 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2060 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2062 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2063 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2064 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2065 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2067 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2068 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2069 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2070 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2072 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2074 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2075 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2076 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2078 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2080 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2081 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2084 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2085 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2086 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2087 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2088 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2091 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2092 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2093 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2094 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2095 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2096 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2098 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2099 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2100 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2101 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2102 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2103 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2105 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2106 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2107 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2108 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2110 // 128-bit logical shifts.
2111 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2112 ExeDomain = SSEPackedInt in {
2113 def PSLLDQri : PDIi8<0x73, MRM7r,
2114 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2115 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2116 def PSRLDQri : PDIi8<0x73, MRM3r,
2117 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2118 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2119 // PSRADQri doesn't exist in SSE[1-3].
2122 let Predicates = [HasSSE2] in {
2123 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2124 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2125 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2126 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2127 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2128 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2129 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2130 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2131 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2132 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2134 // Shift up / down and insert zero's.
2135 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2136 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2137 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2138 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2142 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2143 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2144 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2146 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2147 def PANDNrr : PDI<0xDF, MRMSrcReg,
2148 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2149 "pandn\t{$src2, $dst|$dst, $src2}",
2150 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2153 def PANDNrm : PDI<0xDF, MRMSrcMem,
2154 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2155 "pandn\t{$src2, $dst|$dst, $src2}",
2156 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2157 (memopv2i64 addr:$src2))))]>;
2160 // SSE2 Integer comparison
2161 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2162 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2163 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2164 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2165 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2166 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2168 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2169 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2170 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2171 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2172 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2173 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2174 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2175 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2176 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2177 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2178 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2179 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2181 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2182 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2183 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2184 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2185 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2186 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2187 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2188 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2189 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2190 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2191 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2192 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2195 // Pack instructions
2196 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2197 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2198 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2200 let ExeDomain = SSEPackedInt in {
2202 // Shuffle and unpack instructions
2203 let AddedComplexity = 5 in {
2204 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2205 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2206 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2207 [(set VR128:$dst, (v4i32 (pshufd:$src2
2208 VR128:$src1, (undef))))]>;
2209 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2210 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2211 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2212 [(set VR128:$dst, (v4i32 (pshufd:$src2
2213 (bc_v4i32 (memopv2i64 addr:$src1)),
2217 // SSE2 with ImmT == Imm8 and XS prefix.
2218 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2219 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2220 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2221 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2223 XS, Requires<[HasSSE2]>;
2224 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2225 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2226 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2227 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2228 (bc_v8i16 (memopv2i64 addr:$src1)),
2230 XS, Requires<[HasSSE2]>;
2232 // SSE2 with ImmT == Imm8 and XD prefix.
2233 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2234 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2235 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2236 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2238 XD, Requires<[HasSSE2]>;
2239 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2240 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2241 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2242 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2243 (bc_v8i16 (memopv2i64 addr:$src1)),
2245 XD, Requires<[HasSSE2]>;
2248 let Constraints = "$src1 = $dst" in {
2249 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2250 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2251 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2253 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2254 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2255 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2256 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2258 (unpckl VR128:$src1,
2259 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2260 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2261 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2262 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2264 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2265 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2266 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2267 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2269 (unpckl VR128:$src1,
2270 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2271 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2272 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2273 "punpckldq\t{$src2, $dst|$dst, $src2}",
2275 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2276 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2277 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2278 "punpckldq\t{$src2, $dst|$dst, $src2}",
2280 (unpckl VR128:$src1,
2281 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2282 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2283 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2284 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2286 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2287 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2288 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2289 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2291 (v2i64 (unpckl VR128:$src1,
2292 (memopv2i64 addr:$src2))))]>;
2294 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2295 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2296 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2298 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2299 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2300 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2301 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2303 (unpckh VR128:$src1,
2304 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2305 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2306 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2307 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2309 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2310 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2311 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2312 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2314 (unpckh VR128:$src1,
2315 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2316 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2317 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2318 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2320 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2321 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2322 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2323 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2325 (unpckh VR128:$src1,
2326 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2327 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2328 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2329 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2331 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2332 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2333 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2334 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2336 (v2i64 (unpckh VR128:$src1,
2337 (memopv2i64 addr:$src2))))]>;
2341 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2342 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2343 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2346 let Constraints = "$src1 = $dst" in {
2347 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2348 (outs VR128:$dst), (ins VR128:$src1,
2349 GR32:$src2, i32i8imm:$src3),
2350 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2352 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2353 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2354 (outs VR128:$dst), (ins VR128:$src1,
2355 i16mem:$src2, i32i8imm:$src3),
2356 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2358 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2363 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2364 "pmovmskb\t{$src, $dst|$dst, $src}",
2365 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2367 // Conditional store
2369 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2370 "maskmovdqu\t{$mask, $src|$src, $mask}",
2371 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2374 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2375 "maskmovdqu\t{$mask, $src|$src, $mask}",
2376 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2378 } // ExeDomain = SSEPackedInt
2380 // Non-temporal stores
2381 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2382 "movntpd\t{$src, $dst|$dst, $src}",
2383 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2384 let ExeDomain = SSEPackedInt in
2385 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2386 "movntdq\t{$src, $dst|$dst, $src}",
2387 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2388 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2389 "movnti\t{$src, $dst|$dst, $src}",
2390 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2391 TB, Requires<[HasSSE2]>;
2393 let AddedComplexity = 400 in { // Prefer non-temporal versions
2394 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2395 "movntpd\t{$src, $dst|$dst, $src}",
2396 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2398 let ExeDomain = SSEPackedInt in
2399 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2400 "movntdq\t{$src, $dst|$dst, $src}",
2401 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2405 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2406 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2407 TB, Requires<[HasSSE2]>;
2409 // Load, store, and memory fence
2410 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2411 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2412 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2413 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2415 //TODO: custom lower this so as to never even generate the noop
2416 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2418 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2419 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2420 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2423 // Alias instructions that map zero vector to pxor / xorp* for sse.
2424 // We set canFoldAsLoad because this can be converted to a constant-pool
2425 // load of an all-ones value if folding it would be beneficial.
2426 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2427 isCodeGenOnly = 1 in
2428 // FIXME: Change encoding to pseudo.
2429 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2430 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2432 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2433 "movd\t{$src, $dst|$dst, $src}",
2435 (v4i32 (scalar_to_vector GR32:$src)))]>;
2436 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2437 "movd\t{$src, $dst|$dst, $src}",
2439 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2441 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2442 "movd\t{$src, $dst|$dst, $src}",
2443 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2445 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2446 "movd\t{$src, $dst|$dst, $src}",
2447 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2449 // SSE2 instructions with XS prefix
2450 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2451 "movq\t{$src, $dst|$dst, $src}",
2453 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2454 Requires<[HasSSE2]>;
2455 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2456 "movq\t{$src, $dst|$dst, $src}",
2457 [(store (i64 (vector_extract (v2i64 VR128:$src),
2458 (iPTR 0))), addr:$dst)]>;
2460 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2461 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
2463 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2464 "movd\t{$src, $dst|$dst, $src}",
2465 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2467 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2468 "movd\t{$src, $dst|$dst, $src}",
2469 [(store (i32 (vector_extract (v4i32 VR128:$src),
2470 (iPTR 0))), addr:$dst)]>;
2472 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2473 "movd\t{$src, $dst|$dst, $src}",
2474 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2475 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2476 "movd\t{$src, $dst|$dst, $src}",
2477 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2479 // Store / copy lower 64-bits of a XMM register.
2480 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2481 "movq\t{$src, $dst|$dst, $src}",
2482 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2484 // movd / movq to XMM register zero-extends
2485 let AddedComplexity = 15 in {
2486 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2487 "movd\t{$src, $dst|$dst, $src}",
2488 [(set VR128:$dst, (v4i32 (X86vzmovl
2489 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2490 // This is X86-64 only.
2491 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2492 "mov{d|q}\t{$src, $dst|$dst, $src}",
2493 [(set VR128:$dst, (v2i64 (X86vzmovl
2494 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2497 let AddedComplexity = 20 in {
2498 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2499 "movd\t{$src, $dst|$dst, $src}",
2501 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2502 (loadi32 addr:$src))))))]>;
2504 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2505 (MOVZDI2PDIrm addr:$src)>;
2506 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2507 (MOVZDI2PDIrm addr:$src)>;
2508 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2509 (MOVZDI2PDIrm addr:$src)>;
2511 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2512 "movq\t{$src, $dst|$dst, $src}",
2514 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2515 (loadi64 addr:$src))))))]>, XS,
2516 Requires<[HasSSE2]>;
2518 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2519 (MOVZQI2PQIrm addr:$src)>;
2520 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2521 (MOVZQI2PQIrm addr:$src)>;
2522 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2525 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2526 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2527 let AddedComplexity = 15 in
2528 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2529 "movq\t{$src, $dst|$dst, $src}",
2530 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2531 XS, Requires<[HasSSE2]>;
2533 let AddedComplexity = 20 in {
2534 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2535 "movq\t{$src, $dst|$dst, $src}",
2536 [(set VR128:$dst, (v2i64 (X86vzmovl
2537 (loadv2i64 addr:$src))))]>,
2538 XS, Requires<[HasSSE2]>;
2540 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2541 (MOVZPQILo2PQIrm addr:$src)>;
2544 // Instructions for the disassembler
2545 // xr = XMM register
2548 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2549 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2551 //===---------------------------------------------------------------------===//
2552 // SSE3 Instructions
2553 //===---------------------------------------------------------------------===//
2555 // Move Instructions
2556 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2557 "movshdup\t{$src, $dst|$dst, $src}",
2558 [(set VR128:$dst, (v4f32 (movshdup
2559 VR128:$src, (undef))))]>;
2560 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2561 "movshdup\t{$src, $dst|$dst, $src}",
2562 [(set VR128:$dst, (movshdup
2563 (memopv4f32 addr:$src), (undef)))]>;
2565 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2566 "movsldup\t{$src, $dst|$dst, $src}",
2567 [(set VR128:$dst, (v4f32 (movsldup
2568 VR128:$src, (undef))))]>;
2569 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2570 "movsldup\t{$src, $dst|$dst, $src}",
2571 [(set VR128:$dst, (movsldup
2572 (memopv4f32 addr:$src), (undef)))]>;
2574 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2575 "movddup\t{$src, $dst|$dst, $src}",
2576 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2577 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2578 "movddup\t{$src, $dst|$dst, $src}",
2580 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2583 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2585 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2587 let AddedComplexity = 5 in {
2588 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2589 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2590 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2591 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2592 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2593 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2594 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2595 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2599 let Constraints = "$src1 = $dst" in {
2600 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2601 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2602 "addsubps\t{$src2, $dst|$dst, $src2}",
2603 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2605 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2606 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2607 "addsubps\t{$src2, $dst|$dst, $src2}",
2608 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2609 (memop addr:$src2)))]>;
2610 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2611 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2612 "addsubpd\t{$src2, $dst|$dst, $src2}",
2613 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2615 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2616 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2617 "addsubpd\t{$src2, $dst|$dst, $src2}",
2618 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2619 (memop addr:$src2)))]>;
2622 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2623 "lddqu\t{$src, $dst|$dst, $src}",
2624 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2627 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2628 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2629 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2630 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2631 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2632 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2634 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2635 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2636 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2638 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2639 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2640 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2641 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2642 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2644 let Constraints = "$src1 = $dst" in {
2645 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2646 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2647 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2648 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2649 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2650 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2651 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2652 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2655 // Thread synchronization
2656 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2657 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2658 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2659 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2661 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2662 let AddedComplexity = 15 in
2663 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2664 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2665 let AddedComplexity = 20 in
2666 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2667 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2669 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2670 let AddedComplexity = 15 in
2671 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2672 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2673 let AddedComplexity = 20 in
2674 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2675 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2677 //===---------------------------------------------------------------------===//
2678 // SSSE3 Instructions
2679 //===---------------------------------------------------------------------===//
2681 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2682 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2683 Intrinsic IntId64, Intrinsic IntId128> {
2684 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2685 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2686 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2688 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2689 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2691 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2693 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2695 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2696 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2699 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2701 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2704 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2707 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2708 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2709 Intrinsic IntId64, Intrinsic IntId128> {
2710 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2712 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2713 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2715 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2720 (bitconvert (memopv4i16 addr:$src))))]>;
2722 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2724 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2725 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2728 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2730 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2733 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2736 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2737 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2738 Intrinsic IntId64, Intrinsic IntId128> {
2739 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2741 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2742 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2744 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2746 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2749 (bitconvert (memopv2i32 addr:$src))))]>;
2751 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2753 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2754 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2757 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2759 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2762 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2765 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2766 int_x86_ssse3_pabs_b,
2767 int_x86_ssse3_pabs_b_128>;
2768 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2769 int_x86_ssse3_pabs_w,
2770 int_x86_ssse3_pabs_w_128>;
2771 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2772 int_x86_ssse3_pabs_d,
2773 int_x86_ssse3_pabs_d_128>;
2775 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2776 let Constraints = "$src1 = $dst" in {
2777 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2778 Intrinsic IntId64, Intrinsic IntId128,
2779 bit Commutable = 0> {
2780 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2781 (ins VR64:$src1, VR64:$src2),
2782 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2783 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2784 let isCommutable = Commutable;
2786 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2787 (ins VR64:$src1, i64mem:$src2),
2788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2790 (IntId64 VR64:$src1,
2791 (bitconvert (memopv8i8 addr:$src2))))]>;
2793 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2794 (ins VR128:$src1, VR128:$src2),
2795 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2796 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2798 let isCommutable = Commutable;
2800 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2801 (ins VR128:$src1, i128mem:$src2),
2802 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2804 (IntId128 VR128:$src1,
2805 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2809 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2810 let Constraints = "$src1 = $dst" in {
2811 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2812 Intrinsic IntId64, Intrinsic IntId128,
2813 bit Commutable = 0> {
2814 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2815 (ins VR64:$src1, VR64:$src2),
2816 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2817 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2818 let isCommutable = Commutable;
2820 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2821 (ins VR64:$src1, i64mem:$src2),
2822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2824 (IntId64 VR64:$src1,
2825 (bitconvert (memopv4i16 addr:$src2))))]>;
2827 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2828 (ins VR128:$src1, VR128:$src2),
2829 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2830 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2832 let isCommutable = Commutable;
2834 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2835 (ins VR128:$src1, i128mem:$src2),
2836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2838 (IntId128 VR128:$src1,
2839 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2843 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2844 let Constraints = "$src1 = $dst" in {
2845 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2846 Intrinsic IntId64, Intrinsic IntId128,
2847 bit Commutable = 0> {
2848 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2849 (ins VR64:$src1, VR64:$src2),
2850 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2851 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2852 let isCommutable = Commutable;
2854 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2855 (ins VR64:$src1, i64mem:$src2),
2856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2858 (IntId64 VR64:$src1,
2859 (bitconvert (memopv2i32 addr:$src2))))]>;
2861 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2862 (ins VR128:$src1, VR128:$src2),
2863 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2864 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2866 let isCommutable = Commutable;
2868 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2869 (ins VR128:$src1, i128mem:$src2),
2870 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2872 (IntId128 VR128:$src1,
2873 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2877 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2878 int_x86_ssse3_phadd_w,
2879 int_x86_ssse3_phadd_w_128>;
2880 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2881 int_x86_ssse3_phadd_d,
2882 int_x86_ssse3_phadd_d_128>;
2883 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2884 int_x86_ssse3_phadd_sw,
2885 int_x86_ssse3_phadd_sw_128>;
2886 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2887 int_x86_ssse3_phsub_w,
2888 int_x86_ssse3_phsub_w_128>;
2889 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2890 int_x86_ssse3_phsub_d,
2891 int_x86_ssse3_phsub_d_128>;
2892 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2893 int_x86_ssse3_phsub_sw,
2894 int_x86_ssse3_phsub_sw_128>;
2895 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2896 int_x86_ssse3_pmadd_ub_sw,
2897 int_x86_ssse3_pmadd_ub_sw_128>;
2898 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2899 int_x86_ssse3_pmul_hr_sw,
2900 int_x86_ssse3_pmul_hr_sw_128, 1>;
2901 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2902 int_x86_ssse3_pshuf_b,
2903 int_x86_ssse3_pshuf_b_128>;
2904 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2905 int_x86_ssse3_psign_b,
2906 int_x86_ssse3_psign_b_128>;
2907 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2908 int_x86_ssse3_psign_w,
2909 int_x86_ssse3_psign_w_128>;
2910 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2911 int_x86_ssse3_psign_d,
2912 int_x86_ssse3_psign_d_128>;
2914 let Constraints = "$src1 = $dst" in {
2915 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2916 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2917 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2919 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2920 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2921 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2924 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2925 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2926 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2928 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2929 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2930 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2934 // palignr patterns.
2935 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
2936 (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
2937 Requires<[HasSSSE3]>;
2938 def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
2939 (memop64 addr:$src2),
2941 (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2942 Requires<[HasSSSE3]>;
2944 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
2945 (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
2946 Requires<[HasSSSE3]>;
2947 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
2948 (memopv2i64 addr:$src2),
2950 (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2951 Requires<[HasSSSE3]>;
2953 let AddedComplexity = 5 in {
2954 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2955 (PALIGNR128rr VR128:$src2, VR128:$src1,
2956 (SHUFFLE_get_palign_imm VR128:$src3))>,
2957 Requires<[HasSSSE3]>;
2958 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2959 (PALIGNR128rr VR128:$src2, VR128:$src1,
2960 (SHUFFLE_get_palign_imm VR128:$src3))>,
2961 Requires<[HasSSSE3]>;
2962 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2963 (PALIGNR128rr VR128:$src2, VR128:$src1,
2964 (SHUFFLE_get_palign_imm VR128:$src3))>,
2965 Requires<[HasSSSE3]>;
2966 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2967 (PALIGNR128rr VR128:$src2, VR128:$src1,
2968 (SHUFFLE_get_palign_imm VR128:$src3))>,
2969 Requires<[HasSSSE3]>;
2972 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2973 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2974 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2975 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2977 //===---------------------------------------------------------------------===//
2978 // Non-Instruction Patterns
2979 //===---------------------------------------------------------------------===//
2981 // extload f32 -> f64. This matches load+fextend because we have a hack in
2982 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2984 // Since these loads aren't folded into the fextend, we have to match it
2986 let Predicates = [HasSSE2] in
2987 def : Pat<(fextend (loadf32 addr:$src)),
2988 (CVTSS2SDrm addr:$src)>;
2991 let Predicates = [HasSSE2] in {
2992 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2993 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2994 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2995 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2996 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2997 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2998 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2999 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3000 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3001 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3002 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3003 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3004 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3005 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3006 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3007 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3008 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3009 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3010 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3011 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3012 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3013 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3014 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3015 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3016 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3017 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3018 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3019 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3020 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3021 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3024 // Move scalar to XMM zero-extended
3025 // movd to XMM register zero-extends
3026 let AddedComplexity = 15 in {
3027 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3028 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3029 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
3030 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3031 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
3032 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3033 (MOVSSrr (v4f32 (V_SET0)),
3034 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
3035 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3036 (MOVSSrr (v4i32 (V_SET0)),
3037 (EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
3040 // Splat v2f64 / v2i64
3041 let AddedComplexity = 10 in {
3042 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3043 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3044 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3045 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3046 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3047 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3048 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3049 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3052 // Special unary SHUFPSrri case.
3053 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3054 (SHUFPSrri VR128:$src1, VR128:$src1,
3055 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3056 let AddedComplexity = 5 in
3057 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3058 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3059 Requires<[HasSSE2]>;
3060 // Special unary SHUFPDrri case.
3061 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3062 (SHUFPDrri VR128:$src1, VR128:$src1,
3063 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3064 Requires<[HasSSE2]>;
3065 // Special unary SHUFPDrri case.
3066 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3067 (SHUFPDrri VR128:$src1, VR128:$src1,
3068 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3069 Requires<[HasSSE2]>;
3070 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3071 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3072 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3073 Requires<[HasSSE2]>;
3075 // Special binary v4i32 shuffle cases with SHUFPS.
3076 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3077 (SHUFPSrri VR128:$src1, VR128:$src2,
3078 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3079 Requires<[HasSSE2]>;
3080 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3081 (SHUFPSrmi VR128:$src1, addr:$src2,
3082 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3083 Requires<[HasSSE2]>;
3084 // Special binary v2i64 shuffle cases using SHUFPDrri.
3085 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3086 (SHUFPDrri VR128:$src1, VR128:$src2,
3087 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3088 Requires<[HasSSE2]>;
3090 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3091 let AddedComplexity = 15 in {
3092 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3093 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3094 Requires<[OptForSpeed, HasSSE2]>;
3095 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3096 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3097 Requires<[OptForSpeed, HasSSE2]>;
3099 let AddedComplexity = 10 in {
3100 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3101 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3102 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3103 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3104 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3105 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3106 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3107 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3110 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3111 let AddedComplexity = 15 in {
3112 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3113 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3114 Requires<[OptForSpeed, HasSSE2]>;
3115 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3116 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3117 Requires<[OptForSpeed, HasSSE2]>;
3119 let AddedComplexity = 10 in {
3120 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3121 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3122 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3123 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3124 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3125 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3126 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3127 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3130 let AddedComplexity = 20 in {
3131 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3132 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3133 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3135 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3136 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3137 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3139 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3140 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3141 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3142 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3143 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3146 let AddedComplexity = 20 in {
3147 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3148 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3149 (MOVLPSrm VR128:$src1, addr:$src2)>;
3150 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3151 (MOVLPDrm VR128:$src1, addr:$src2)>;
3152 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3153 (MOVLPSrm VR128:$src1, addr:$src2)>;
3154 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3155 (MOVLPDrm VR128:$src1, addr:$src2)>;
3158 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3159 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3160 (MOVLPSmr addr:$src1, VR128:$src2)>;
3161 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3162 (MOVLPDmr addr:$src1, VR128:$src2)>;
3163 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3165 (MOVLPSmr addr:$src1, VR128:$src2)>;
3166 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3167 (MOVLPDmr addr:$src1, VR128:$src2)>;
3169 let AddedComplexity = 15 in {
3170 // Setting the lowest element in the vector.
3171 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3172 (MOVSSrr (v4i32 VR128:$src1),
3173 (EXTRACT_SUBREG (v4i32 VR128:$src2), x86_subreg_ss))>;
3174 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3175 (MOVSDrr (v2i64 VR128:$src1),
3176 (EXTRACT_SUBREG (v2i64 VR128:$src2), x86_subreg_sd))>;
3178 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3179 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3180 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3181 Requires<[HasSSE2]>;
3182 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3183 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3184 Requires<[HasSSE2]>;
3187 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3188 // fall back to this for SSE1)
3189 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3190 (SHUFPSrri VR128:$src2, VR128:$src1,
3191 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3193 // Set lowest element and zero upper elements.
3194 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3195 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3197 // Some special case pandn patterns.
3198 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3200 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3201 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3203 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3204 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3206 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3208 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3209 (memop addr:$src2))),
3210 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3211 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3212 (memop addr:$src2))),
3213 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3214 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3215 (memop addr:$src2))),
3216 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3218 // vector -> vector casts
3219 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3220 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3221 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3222 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3223 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3224 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3225 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3226 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3228 // Use movaps / movups for SSE integer load / store (one byte shorter).
3229 def : Pat<(alignedloadv4i32 addr:$src),
3230 (MOVAPSrm addr:$src)>;
3231 def : Pat<(loadv4i32 addr:$src),
3232 (MOVUPSrm addr:$src)>;
3233 def : Pat<(alignedloadv2i64 addr:$src),
3234 (MOVAPSrm addr:$src)>;
3235 def : Pat<(loadv2i64 addr:$src),
3236 (MOVUPSrm addr:$src)>;
3238 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3239 (MOVAPSmr addr:$dst, VR128:$src)>;
3240 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3241 (MOVAPSmr addr:$dst, VR128:$src)>;
3242 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3243 (MOVAPSmr addr:$dst, VR128:$src)>;
3244 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3245 (MOVAPSmr addr:$dst, VR128:$src)>;
3246 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3247 (MOVUPSmr addr:$dst, VR128:$src)>;
3248 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3249 (MOVUPSmr addr:$dst, VR128:$src)>;
3250 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3251 (MOVUPSmr addr:$dst, VR128:$src)>;
3252 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3253 (MOVUPSmr addr:$dst, VR128:$src)>;
3255 //===----------------------------------------------------------------------===//
3256 // SSE4.1 Instructions
3257 //===----------------------------------------------------------------------===//
3259 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3262 Intrinsic V2F64Int> {
3263 // Intrinsic operation, reg.
3264 // Vector intrinsic operation, reg
3265 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3266 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3267 !strconcat(OpcodeStr,
3268 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3269 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3272 // Vector intrinsic operation, mem
3273 def PSm_Int : Ii8<opcps, MRMSrcMem,
3274 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3275 !strconcat(OpcodeStr,
3276 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3278 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3280 Requires<[HasSSE41]>;
3282 // Vector intrinsic operation, reg
3283 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3284 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3285 !strconcat(OpcodeStr,
3286 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3287 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3290 // Vector intrinsic operation, mem
3291 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3292 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3293 !strconcat(OpcodeStr,
3294 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3296 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3300 let Constraints = "$src1 = $dst" in {
3301 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3305 // Intrinsic operation, reg.
3306 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3308 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3309 !strconcat(OpcodeStr,
3310 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3312 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3315 // Intrinsic operation, mem.
3316 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3318 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3319 !strconcat(OpcodeStr,
3320 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3322 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3325 // Intrinsic operation, reg.
3326 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3328 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3329 !strconcat(OpcodeStr,
3330 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3332 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3335 // Intrinsic operation, mem.
3336 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3338 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3339 !strconcat(OpcodeStr,
3340 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3342 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3347 // FP round - roundss, roundps, roundsd, roundpd
3348 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3349 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3350 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3351 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3353 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3354 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3355 Intrinsic IntId128> {
3356 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3358 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3359 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3360 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3362 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3365 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3368 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3369 int_x86_sse41_phminposuw>;
3371 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3372 let Constraints = "$src1 = $dst" in {
3373 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3374 Intrinsic IntId128, bit Commutable = 0> {
3375 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3376 (ins VR128:$src1, VR128:$src2),
3377 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3378 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3380 let isCommutable = Commutable;
3382 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3383 (ins VR128:$src1, i128mem:$src2),
3384 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3386 (IntId128 VR128:$src1,
3387 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3391 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3392 int_x86_sse41_pcmpeqq, 1>;
3393 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3394 int_x86_sse41_packusdw, 0>;
3395 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3396 int_x86_sse41_pminsb, 1>;
3397 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3398 int_x86_sse41_pminsd, 1>;
3399 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3400 int_x86_sse41_pminud, 1>;
3401 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3402 int_x86_sse41_pminuw, 1>;
3403 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3404 int_x86_sse41_pmaxsb, 1>;
3405 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3406 int_x86_sse41_pmaxsd, 1>;
3407 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3408 int_x86_sse41_pmaxud, 1>;
3409 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3410 int_x86_sse41_pmaxuw, 1>;
3412 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3414 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3415 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3416 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3417 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3419 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3420 let Constraints = "$src1 = $dst" in {
3421 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3422 SDNode OpNode, Intrinsic IntId128,
3423 bit Commutable = 0> {
3424 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3425 (ins VR128:$src1, VR128:$src2),
3426 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3427 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3428 VR128:$src2))]>, OpSize {
3429 let isCommutable = Commutable;
3431 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3432 (ins VR128:$src1, VR128:$src2),
3433 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3434 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3436 let isCommutable = Commutable;
3438 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3439 (ins VR128:$src1, i128mem:$src2),
3440 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3442 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3443 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3444 (ins VR128:$src1, i128mem:$src2),
3445 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3447 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3452 /// SS48I_binop_rm - Simple SSE41 binary operator.
3453 let Constraints = "$src1 = $dst" in {
3454 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3455 ValueType OpVT, bit Commutable = 0> {
3456 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3457 (ins VR128:$src1, VR128:$src2),
3458 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3459 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3461 let isCommutable = Commutable;
3463 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3464 (ins VR128:$src1, i128mem:$src2),
3465 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3466 [(set VR128:$dst, (OpNode VR128:$src1,
3467 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3472 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3474 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3475 let Constraints = "$src1 = $dst" in {
3476 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3477 Intrinsic IntId128, bit Commutable = 0> {
3478 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3479 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3480 !strconcat(OpcodeStr,
3481 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3483 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3485 let isCommutable = Commutable;
3487 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3488 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3489 !strconcat(OpcodeStr,
3490 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3492 (IntId128 VR128:$src1,
3493 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3498 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3499 int_x86_sse41_blendps, 0>;
3500 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3501 int_x86_sse41_blendpd, 0>;
3502 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3503 int_x86_sse41_pblendw, 0>;
3504 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3505 int_x86_sse41_dpps, 1>;
3506 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3507 int_x86_sse41_dppd, 1>;
3508 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3509 int_x86_sse41_mpsadbw, 1>;
3512 /// SS41I_ternary_int - SSE 4.1 ternary operator
3513 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3514 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3515 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3516 (ins VR128:$src1, VR128:$src2),
3517 !strconcat(OpcodeStr,
3518 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3519 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3522 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3523 (ins VR128:$src1, i128mem:$src2),
3524 !strconcat(OpcodeStr,
3525 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3528 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3532 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3533 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3534 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3537 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3538 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3539 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3540 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3542 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3545 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3549 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3550 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3551 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3552 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3553 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3554 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3556 // Common patterns involving scalar load.
3557 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3558 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3559 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3560 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3562 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3563 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3564 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3565 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3567 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3568 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3569 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3570 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3572 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3573 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3574 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3575 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3577 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3578 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3579 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3580 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3582 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3583 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3584 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3585 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3588 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3589 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3590 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3591 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3593 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3596 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3600 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3601 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3602 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3603 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3605 // Common patterns involving scalar load
3606 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3607 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3608 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3609 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3611 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3612 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3613 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3614 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3617 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3618 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3620 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3622 // Expecting a i16 load any extended to i32 value.
3623 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3625 [(set VR128:$dst, (IntId (bitconvert
3626 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3630 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3631 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3633 // Common patterns involving scalar load
3634 def : Pat<(int_x86_sse41_pmovsxbq
3635 (bitconvert (v4i32 (X86vzmovl
3636 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3637 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3639 def : Pat<(int_x86_sse41_pmovzxbq
3640 (bitconvert (v4i32 (X86vzmovl
3641 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3642 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3645 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3646 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3647 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3648 (ins VR128:$src1, i32i8imm:$src2),
3649 !strconcat(OpcodeStr,
3650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3651 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3653 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3654 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3655 !strconcat(OpcodeStr,
3656 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3659 // There's an AssertZext in the way of writing the store pattern
3660 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3663 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3666 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3667 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3668 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3669 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3670 !strconcat(OpcodeStr,
3671 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3674 // There's an AssertZext in the way of writing the store pattern
3675 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3678 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3681 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3682 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3683 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3684 (ins VR128:$src1, i32i8imm:$src2),
3685 !strconcat(OpcodeStr,
3686 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3688 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3689 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3690 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3691 !strconcat(OpcodeStr,
3692 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3693 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3694 addr:$dst)]>, OpSize;
3697 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3700 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3702 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3703 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3704 (ins VR128:$src1, i32i8imm:$src2),
3705 !strconcat(OpcodeStr,
3706 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3708 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3710 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3711 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3712 !strconcat(OpcodeStr,
3713 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3714 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3715 addr:$dst)]>, OpSize;
3718 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3720 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3721 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3724 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3725 Requires<[HasSSE41]>;
3727 let Constraints = "$src1 = $dst" in {
3728 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3729 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3730 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3731 !strconcat(OpcodeStr,
3732 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3734 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3735 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3736 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3737 !strconcat(OpcodeStr,
3738 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3740 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3741 imm:$src3))]>, OpSize;
3745 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3747 let Constraints = "$src1 = $dst" in {
3748 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3749 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3750 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3751 !strconcat(OpcodeStr,
3752 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3754 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3756 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3757 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3758 !strconcat(OpcodeStr,
3759 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3761 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3762 imm:$src3)))]>, OpSize;
3766 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3768 // insertps has a few different modes, there's the first two here below which
3769 // are optimized inserts that won't zero arbitrary elements in the destination
3770 // vector. The next one matches the intrinsic and could zero arbitrary elements
3771 // in the target vector.
3772 let Constraints = "$src1 = $dst" in {
3773 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3774 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3775 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3776 !strconcat(OpcodeStr,
3777 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3779 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3781 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3782 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3783 !strconcat(OpcodeStr,
3784 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3786 (X86insrtps VR128:$src1,
3787 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3788 imm:$src3))]>, OpSize;
3792 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3794 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3795 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3797 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3798 // the intel intrinsic that corresponds to this.
3799 let Defs = [EFLAGS] in {
3800 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3801 "ptest \t{$src2, $src1|$src1, $src2}",
3802 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3804 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3805 "ptest \t{$src2, $src1|$src1, $src2}",
3806 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3810 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3811 "movntdqa\t{$src, $dst|$dst, $src}",
3812 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3816 //===----------------------------------------------------------------------===//
3817 // SSE4.2 Instructions
3818 //===----------------------------------------------------------------------===//
3820 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3821 let Constraints = "$src1 = $dst" in {
3822 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3823 Intrinsic IntId128, bit Commutable = 0> {
3824 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3825 (ins VR128:$src1, VR128:$src2),
3826 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3827 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3829 let isCommutable = Commutable;
3831 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3832 (ins VR128:$src1, i128mem:$src2),
3833 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3835 (IntId128 VR128:$src1,
3836 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3840 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3842 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3843 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3844 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3845 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3847 defm AESIMC : SS42I_binop_rm_int<0xDB, "aesimc",
3848 int_x86_sse42_aesimc>;
3849 defm AESENC : SS42I_binop_rm_int<0xDC, "aesenc",
3850 int_x86_sse42_aesenc>;
3851 defm AESENCLAST : SS42I_binop_rm_int<0xDD, "aesenclast",
3852 int_x86_sse42_aesenclast>;
3853 defm AESDEC : SS42I_binop_rm_int<0xDE, "aesdec",
3854 int_x86_sse42_aesdec>;
3855 defm AESDECLAST : SS42I_binop_rm_int<0xDF, "aesdeclast",
3856 int_x86_sse42_aesdeclast>;
3858 def : Pat<(v2i64 (int_x86_sse42_aesimc VR128:$src1, VR128:$src2)),
3859 (AESIMCrr VR128:$src1, VR128:$src2)>;
3860 def : Pat<(v2i64 (int_x86_sse42_aesimc VR128:$src1, (memop addr:$src2))),
3861 (AESIMCrm VR128:$src1, addr:$src2)>;
3862 def : Pat<(v2i64 (int_x86_sse42_aesenc VR128:$src1, VR128:$src2)),
3863 (AESENCrr VR128:$src1, VR128:$src2)>;
3864 def : Pat<(v2i64 (int_x86_sse42_aesenc VR128:$src1, (memop addr:$src2))),
3865 (AESENCrm VR128:$src1, addr:$src2)>;
3866 def : Pat<(v2i64 (int_x86_sse42_aesenclast VR128:$src1, VR128:$src2)),
3867 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3868 def : Pat<(v2i64 (int_x86_sse42_aesenclast VR128:$src1, (memop addr:$src2))),
3869 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3870 def : Pat<(v2i64 (int_x86_sse42_aesdec VR128:$src1, VR128:$src2)),
3871 (AESDECrr VR128:$src1, VR128:$src2)>;
3872 def : Pat<(v2i64 (int_x86_sse42_aesdec VR128:$src1, (memop addr:$src2))),
3873 (AESDECrm VR128:$src1, addr:$src2)>;
3874 def : Pat<(v2i64 (int_x86_sse42_aesdeclast VR128:$src1, VR128:$src2)),
3875 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3876 def : Pat<(v2i64 (int_x86_sse42_aesdeclast VR128:$src1, (memop addr:$src2))),
3877 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3879 def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
3880 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3881 "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3882 def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
3883 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3884 "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3886 // crc intrinsic instruction
3887 // This set of instructions are only rm, the only difference is the size
3889 let Constraints = "$src1 = $dst" in {
3890 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3891 (ins GR32:$src1, i8mem:$src2),
3892 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3894 (int_x86_sse42_crc32_8 GR32:$src1,
3895 (load addr:$src2)))]>;
3896 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3897 (ins GR32:$src1, GR8:$src2),
3898 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3900 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3901 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3902 (ins GR32:$src1, i16mem:$src2),
3903 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3905 (int_x86_sse42_crc32_16 GR32:$src1,
3906 (load addr:$src2)))]>,
3908 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3909 (ins GR32:$src1, GR16:$src2),
3910 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3912 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3914 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3915 (ins GR32:$src1, i32mem:$src2),
3916 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3918 (int_x86_sse42_crc32_32 GR32:$src1,
3919 (load addr:$src2)))]>;
3920 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3921 (ins GR32:$src1, GR32:$src2),
3922 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3924 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3925 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3926 (ins GR64:$src1, i8mem:$src2),
3927 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3929 (int_x86_sse42_crc64_8 GR64:$src1,
3930 (load addr:$src2)))]>,
3932 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3933 (ins GR64:$src1, GR8:$src2),
3934 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3936 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3938 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3939 (ins GR64:$src1, i64mem:$src2),
3940 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3942 (int_x86_sse42_crc64_64 GR64:$src1,
3943 (load addr:$src2)))]>,
3945 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3946 (ins GR64:$src1, GR64:$src2),
3947 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3949 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3953 // String/text processing instructions.
3954 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3955 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3956 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3957 "#PCMPISTRM128rr PSEUDO!",
3958 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3959 imm:$src3))]>, OpSize;
3960 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3961 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3962 "#PCMPISTRM128rm PSEUDO!",
3963 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3964 imm:$src3))]>, OpSize;
3967 let Defs = [XMM0, EFLAGS] in {
3968 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3969 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3970 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3971 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3972 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3973 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3976 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3977 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3978 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3979 "#PCMPESTRM128rr PSEUDO!",
3981 (int_x86_sse42_pcmpestrm128
3982 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3984 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3985 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3986 "#PCMPESTRM128rm PSEUDO!",
3987 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3988 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3992 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3993 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3994 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3995 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3996 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3997 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3998 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4001 let Defs = [ECX, EFLAGS] in {
4002 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
4003 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4004 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4005 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4006 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4007 (implicit EFLAGS)]>, OpSize;
4008 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4009 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4010 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4011 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4012 (implicit EFLAGS)]>, OpSize;
4016 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4017 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4018 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4019 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4020 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4021 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4023 let Defs = [ECX, EFLAGS] in {
4024 let Uses = [EAX, EDX] in {
4025 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
4026 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4027 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4028 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4029 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4030 (implicit EFLAGS)]>, OpSize;
4031 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4032 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4033 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4035 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4036 (implicit EFLAGS)]>, OpSize;
4041 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4042 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4043 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4044 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4045 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4046 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;