1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the University
6 // of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>;
25 def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad, [SDNPHasChain]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
36 [SDNPHasChain, SDNPOutFlag]>;
37 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
38 [SDNPHasChain, SDNPOutFlag]>;
39 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
40 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
41 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
43 //===----------------------------------------------------------------------===//
44 // SSE 'Special' Instructions
45 //===----------------------------------------------------------------------===//
47 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
49 [(set VR128:$dst, (v4f32 (undef)))]>,
51 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
53 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
54 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
56 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
58 //===----------------------------------------------------------------------===//
59 // SSE Complex Patterns
60 //===----------------------------------------------------------------------===//
62 // These are 'extloads' from a scalar to the low element of a vector, zeroing
63 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
65 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
67 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
70 def ssmem : Operand<v4f32> {
71 let PrintMethod = "printf32mem";
72 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
74 def sdmem : Operand<v2f64> {
75 let PrintMethod = "printf64mem";
76 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79 //===----------------------------------------------------------------------===//
80 // SSE pattern fragments
81 //===----------------------------------------------------------------------===//
83 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
84 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
86 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
87 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
88 def loadv2i32 : PatFrag<(ops node:$ptr), (v2i32 (load node:$ptr))>;
89 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
91 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
92 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
93 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
94 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
95 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
96 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
98 def fp32imm0 : PatLeaf<(f32 fpimm), [{
99 return N->isExactlyValue(+0.0);
102 def PSxLDQ_imm : SDNodeXForm<imm, [{
103 // Transformation function: imm >> 3
104 return getI32Imm(N->getValue() >> 3);
107 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
109 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
110 return getI8Imm(X86::getShuffleSHUFImmediate(N));
113 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
115 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
116 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
119 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
121 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
122 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
125 def SSE_splat_mask : PatLeaf<(build_vector), [{
126 return X86::isSplatMask(N);
127 }], SHUFFLE_get_shuf_imm>;
129 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
130 return X86::isSplatLoMask(N);
133 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
134 return X86::isMOVHLPSMask(N);
137 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
138 return X86::isMOVHLPS_v_undef_Mask(N);
141 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
142 return X86::isMOVHPMask(N);
145 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
146 return X86::isMOVLPMask(N);
149 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
150 return X86::isMOVLMask(N);
153 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
154 return X86::isMOVSHDUPMask(N);
157 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
158 return X86::isMOVSLDUPMask(N);
161 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
162 return X86::isUNPCKLMask(N);
165 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
166 return X86::isUNPCKHMask(N);
169 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
170 return X86::isUNPCKL_v_undef_Mask(N);
173 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
174 return X86::isUNPCKH_v_undef_Mask(N);
177 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
178 return X86::isPSHUFDMask(N);
179 }], SHUFFLE_get_shuf_imm>;
181 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
182 return X86::isPSHUFHWMask(N);
183 }], SHUFFLE_get_pshufhw_imm>;
185 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
186 return X86::isPSHUFLWMask(N);
187 }], SHUFFLE_get_pshuflw_imm>;
189 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
190 return X86::isPSHUFDMask(N);
191 }], SHUFFLE_get_shuf_imm>;
193 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
194 return X86::isSHUFPMask(N);
195 }], SHUFFLE_get_shuf_imm>;
197 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
198 return X86::isSHUFPMask(N);
199 }], SHUFFLE_get_shuf_imm>;
201 //===----------------------------------------------------------------------===//
202 // SSE scalar FP Instructions
203 //===----------------------------------------------------------------------===//
205 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
206 // scheduler into a branch sequence.
207 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
208 def CMOV_FR32 : I<0, Pseudo,
209 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
210 "#CMOV_FR32 PSEUDO!",
211 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
212 def CMOV_FR64 : I<0, Pseudo,
213 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
214 "#CMOV_FR64 PSEUDO!",
215 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
216 def CMOV_V4F32 : I<0, Pseudo,
217 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
218 "#CMOV_V4F32 PSEUDO!",
220 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
221 def CMOV_V2F64 : I<0, Pseudo,
222 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
223 "#CMOV_V2F64 PSEUDO!",
225 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
226 def CMOV_V2I64 : I<0, Pseudo,
227 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
228 "#CMOV_V2I64 PSEUDO!",
230 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
233 //===----------------------------------------------------------------------===//
235 //===----------------------------------------------------------------------===//
237 // SSE1 Instruction Templates:
239 // SSI - SSE1 instructions with XS prefix.
240 // PSI - SSE1 instructions with TB prefix.
241 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
243 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
244 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
245 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
246 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
247 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
248 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
250 // Helpers for defining instructions that directly correspond to intrinsics.
251 multiclass SS_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
252 def r : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
253 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
254 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
255 def m : SSI<o, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
256 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
257 [(set VR128:$dst, (v4f32 (IntId sse_load_f32:$src)))]>;
261 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
262 "movss {$src, $dst|$dst, $src}", []>;
263 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
264 "movss {$src, $dst|$dst, $src}",
265 [(set FR32:$dst, (loadf32 addr:$src))]>;
266 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
267 "movss {$src, $dst|$dst, $src}",
268 [(store FR32:$src, addr:$dst)]>;
270 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
271 "sqrtss {$src, $dst|$dst, $src}",
272 [(set FR32:$dst, (fsqrt FR32:$src))]>;
273 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
274 "sqrtss {$src, $dst|$dst, $src}",
275 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
277 // Aliases to match intrinsics which expect XMM operand(s).
278 defm SQRTSS_Int : SS_IntUnary<0x51, "sqrtss" , int_x86_sse_sqrt_ss>;
279 defm RSQRTSS_Int : SS_IntUnary<0x52, "rsqrtss", int_x86_sse_rsqrt_ss>;
280 defm RCPSS_Int : SS_IntUnary<0x53, "rcpss" , int_x86_sse_rcp_ss>;
282 // Conversion instructions
283 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
284 "cvttss2si {$src, $dst|$dst, $src}",
285 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
286 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
287 "cvttss2si {$src, $dst|$dst, $src}",
288 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
289 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
290 "cvtsi2ss {$src, $dst|$dst, $src}",
291 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
292 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
293 "cvtsi2ss {$src, $dst|$dst, $src}",
294 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
296 // Match intrinsics which expect XMM operand(s).
297 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
298 "cvtss2si {$src, $dst|$dst, $src}",
299 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
300 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
301 "cvtss2si {$src, $dst|$dst, $src}",
302 [(set GR32:$dst, (int_x86_sse_cvtss2si
303 (load addr:$src)))]>;
305 // Aliases for intrinsics
306 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
307 "cvttss2si {$src, $dst|$dst, $src}",
309 (int_x86_sse_cvttss2si VR128:$src))]>;
310 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
311 "cvttss2si {$src, $dst|$dst, $src}",
313 (int_x86_sse_cvttss2si(load addr:$src)))]>;
315 let isTwoAddress = 1 in {
316 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
317 (ops VR128:$dst, VR128:$src1, GR32:$src2),
318 "cvtsi2ss {$src2, $dst|$dst, $src2}",
319 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
321 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
322 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
323 "cvtsi2ss {$src2, $dst|$dst, $src2}",
324 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
325 (loadi32 addr:$src2)))]>;
328 // Comparison instructions
329 let isTwoAddress = 1 in {
330 def CMPSSrr : SSI<0xC2, MRMSrcReg,
331 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
332 "cmp${cc}ss {$src, $dst|$dst, $src}",
334 def CMPSSrm : SSI<0xC2, MRMSrcMem,
335 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
336 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
339 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
340 "ucomiss {$src2, $src1|$src1, $src2}",
341 [(X86cmp FR32:$src1, FR32:$src2)]>;
342 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
343 "ucomiss {$src2, $src1|$src1, $src2}",
344 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
346 // Aliases to match intrinsics which expect XMM operand(s).
347 let isTwoAddress = 1 in {
348 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
349 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
350 "cmp${cc}ss {$src, $dst|$dst, $src}",
351 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
352 VR128:$src, imm:$cc))]>;
353 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
354 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
355 "cmp${cc}ss {$src, $dst|$dst, $src}",
356 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
357 (load addr:$src), imm:$cc))]>;
360 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
361 "ucomiss {$src2, $src1|$src1, $src2}",
362 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
363 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
364 "ucomiss {$src2, $src1|$src1, $src2}",
365 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
367 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
368 "comiss {$src2, $src1|$src1, $src2}",
369 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
370 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
371 "comiss {$src2, $src1|$src1, $src2}",
372 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
374 // Aliases of packed SSE1 instructions for scalar use. These all have names that
377 // Alias instructions that map fld0 to pxor for sse.
378 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
379 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
380 Requires<[HasSSE1]>, TB, OpSize;
382 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
384 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
385 "movaps {$src, $dst|$dst, $src}", []>;
387 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
389 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
390 "movaps {$src, $dst|$dst, $src}",
391 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
393 // Alias bitwise logical operations using SSE logical ops on packed FP values.
394 let isTwoAddress = 1 in {
396 let isCommutable = 1 in {
397 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
398 "andps {$src2, $dst|$dst, $src2}",
399 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
400 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
401 "orps {$src2, $dst|$dst, $src2}",
402 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
403 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
404 "xorps {$src2, $dst|$dst, $src2}",
405 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
408 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
409 "andps {$src2, $dst|$dst, $src2}",
410 [(set FR32:$dst, (X86fand FR32:$src1,
411 (X86loadpf32 addr:$src2)))]>;
412 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
413 "orps {$src2, $dst|$dst, $src2}",
414 [(set FR32:$dst, (X86for FR32:$src1,
415 (X86loadpf32 addr:$src2)))]>;
416 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
417 "xorps {$src2, $dst|$dst, $src2}",
418 [(set FR32:$dst, (X86fxor FR32:$src1,
419 (X86loadpf32 addr:$src2)))]>;
421 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
422 "andnps {$src2, $dst|$dst, $src2}", []>;
423 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
424 "andnps {$src2, $dst|$dst, $src2}", []>;
427 /// scalar_sse1_fp_binop_rm - Scalar SSE1 binops come in three basic forms:
429 /// 1. f32 - This comes in SSE1 form for floats.
430 /// 2. rr vs rm - They include a reg+reg form and a reg+mem form.
432 /// In addition, scalar SSE ops have an intrinsic form. This form is unlike the
433 /// normal form, in that they take an entire vector (instead of a scalar) and
434 /// leave the top elements undefined. This adds another two variants of the
435 /// above permutations, giving us 8 forms for 'instruction'.
437 let isTwoAddress = 1 in {
438 multiclass scalar_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
439 SDNode OpNode, Intrinsic F32Int,
440 bit Commutable = 0> {
441 // Scalar operation, reg+reg.
442 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
443 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
444 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
445 let isCommutable = Commutable;
448 // Scalar operation, reg+mem.
449 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
450 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
451 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
453 // Vector intrinsic operation, reg+reg.
454 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
455 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
456 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
457 let isCommutable = Commutable;
460 // Vector intrinsic operation, reg+mem.
461 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
462 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2}"),
463 [(set VR128:$dst, (F32Int VR128:$src1,
464 sse_load_f32:$src2))]>;
468 // Arithmetic instructions
469 defm ADD : scalar_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
470 defm MUL : scalar_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
471 defm SUB : scalar_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
472 defm DIV : scalar_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
474 defm MAX : scalar_sse1_fp_binop_rm<0x5F, "max", X86fmax, int_x86_sse_max_ss>;
475 defm MIN : scalar_sse1_fp_binop_rm<0x5D, "min", X86fmin, int_x86_sse_min_ss>;
477 //===----------------------------------------------------------------------===//
478 // SSE packed FP Instructions
481 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
482 "movaps {$src, $dst|$dst, $src}", []>;
483 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
484 "movaps {$src, $dst|$dst, $src}",
485 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
487 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
488 "movaps {$src, $dst|$dst, $src}",
489 [(store (v4f32 VR128:$src), addr:$dst)]>;
491 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
492 "movups {$src, $dst|$dst, $src}", []>;
493 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
494 "movups {$src, $dst|$dst, $src}",
495 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
496 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
497 "movups {$src, $dst|$dst, $src}",
498 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
500 let isTwoAddress = 1 in {
501 let AddedComplexity = 20 in {
502 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
503 "movlps {$src2, $dst|$dst, $src2}",
505 (v4f32 (vector_shuffle VR128:$src1,
506 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
507 MOVLP_shuffle_mask)))]>;
508 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
509 "movhps {$src2, $dst|$dst, $src2}",
511 (v4f32 (vector_shuffle VR128:$src1,
512 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
513 MOVHP_shuffle_mask)))]>;
517 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
518 "movlps {$src, $dst|$dst, $src}",
519 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
520 (iPTR 0))), addr:$dst)]>;
522 // v2f64 extract element 1 is always custom lowered to unpack high to low
523 // and extract element 0 so the non-store version isn't too horrible.
524 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
525 "movhps {$src, $dst|$dst, $src}",
526 [(store (f64 (vector_extract
527 (v2f64 (vector_shuffle
528 (bc_v2f64 (v4f32 VR128:$src)), (undef),
529 UNPCKH_shuffle_mask)), (iPTR 0))),
532 let isTwoAddress = 1 in {
533 let AddedComplexity = 15 in {
534 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
535 "movlhps {$src2, $dst|$dst, $src2}",
537 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
538 MOVHP_shuffle_mask)))]>;
540 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
541 "movhlps {$src2, $dst|$dst, $src2}",
543 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
544 MOVHLPS_shuffle_mask)))]>;
550 /// packed_sse1_fp_binop_rm - Packed SSE binops come in three basic forms:
551 /// 1. v4f32 - This comes in SSE1 form for float.
552 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
554 let isTwoAddress = 1 in {
555 multiclass packed_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
556 SDNode OpNode, bit Commutable = 0> {
557 // Packed operation, reg+reg.
558 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
559 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
561 let isCommutable = Commutable;
564 // Packed operation, reg+mem.
565 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
566 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2}"),
567 [(set VR128:$dst, (OpNode VR128:$src1, (loadv4f32 addr:$src2)))]>;
571 defm ADD : packed_sse1_fp_binop_rm<0x58, "add", fadd, 1>;
572 defm MUL : packed_sse1_fp_binop_rm<0x59, "mul", fmul, 1>;
573 defm DIV : packed_sse1_fp_binop_rm<0x5E, "div", fdiv>;
574 defm SUB : packed_sse1_fp_binop_rm<0x5C, "sub", fsub>;
578 class PS_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
579 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
580 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
581 [(set VR128:$dst, (IntId VR128:$src))]>;
582 class PS_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
583 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
584 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
585 [(set VR128:$dst, (IntId (load addr:$src)))]>;
587 class PS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
588 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
589 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
590 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
591 class PS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
592 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
593 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
594 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
596 def SQRTPSr : PS_Intr<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
597 def SQRTPSm : PS_Intm<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
599 def RSQRTPSr : PS_Intr<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
600 def RSQRTPSm : PS_Intm<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
601 def RCPPSr : PS_Intr<0x53, "rcpps", int_x86_sse_rcp_ps>;
602 def RCPPSm : PS_Intm<0x53, "rcpps", int_x86_sse_rcp_ps>;
604 let isTwoAddress = 1 in {
605 let isCommutable = 1 in {
606 def MAXPSrr : PS_Intrr<0x5F, "maxps", int_x86_sse_max_ps>;
607 def MINPSrr : PS_Intrr<0x5D, "minps", int_x86_sse_min_ps>;
610 def MAXPSrm : PS_Intrm<0x5F, "maxps", int_x86_sse_max_ps>;
611 def MINPSrm : PS_Intrm<0x5D, "minps", int_x86_sse_min_ps>;
615 let isTwoAddress = 1 in {
616 let isCommutable = 1 in {
617 def ANDPSrr : PSI<0x54, MRMSrcReg,
618 (ops VR128:$dst, VR128:$src1, VR128:$src2),
619 "andps {$src2, $dst|$dst, $src2}",
620 [(set VR128:$dst, (v2i64
621 (and VR128:$src1, VR128:$src2)))]>;
622 def ORPSrr : PSI<0x56, MRMSrcReg,
623 (ops VR128:$dst, VR128:$src1, VR128:$src2),
624 "orps {$src2, $dst|$dst, $src2}",
625 [(set VR128:$dst, (v2i64
626 (or VR128:$src1, VR128:$src2)))]>;
627 def XORPSrr : PSI<0x57, MRMSrcReg,
628 (ops VR128:$dst, VR128:$src1, VR128:$src2),
629 "xorps {$src2, $dst|$dst, $src2}",
630 [(set VR128:$dst, (v2i64
631 (xor VR128:$src1, VR128:$src2)))]>;
634 def ANDPSrm : PSI<0x54, MRMSrcMem,
635 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
636 "andps {$src2, $dst|$dst, $src2}",
637 [(set VR128:$dst, (and VR128:$src1,
638 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
639 def ORPSrm : PSI<0x56, MRMSrcMem,
640 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
641 "orps {$src2, $dst|$dst, $src2}",
642 [(set VR128:$dst, (or VR128:$src1,
643 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
644 def XORPSrm : PSI<0x57, MRMSrcMem,
645 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
646 "xorps {$src2, $dst|$dst, $src2}",
647 [(set VR128:$dst, (xor VR128:$src1,
648 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
649 def ANDNPSrr : PSI<0x55, MRMSrcReg,
650 (ops VR128:$dst, VR128:$src1, VR128:$src2),
651 "andnps {$src2, $dst|$dst, $src2}",
653 (v2i64 (and (xor VR128:$src1,
654 (bc_v2i64 (v4i32 immAllOnesV))),
656 def ANDNPSrm : PSI<0x55, MRMSrcMem,
657 (ops VR128:$dst, VR128:$src1,f128mem:$src2),
658 "andnps {$src2, $dst|$dst, $src2}",
660 (v2i64 (and (xor VR128:$src1,
661 (bc_v2i64 (v4i32 immAllOnesV))),
662 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
665 let isTwoAddress = 1 in {
666 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
667 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
668 "cmp${cc}ps {$src, $dst|$dst, $src}",
669 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
670 VR128:$src, imm:$cc))]>;
671 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
672 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
673 "cmp${cc}ps {$src, $dst|$dst, $src}",
674 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
675 (load addr:$src), imm:$cc))]>;
678 // Shuffle and unpack instructions
679 let isTwoAddress = 1 in {
680 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
681 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
682 (ops VR128:$dst, VR128:$src1,
683 VR128:$src2, i32i8imm:$src3),
684 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
686 (v4f32 (vector_shuffle
687 VR128:$src1, VR128:$src2,
688 SHUFP_shuffle_mask:$src3)))]>;
689 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
690 (ops VR128:$dst, VR128:$src1,
691 f128mem:$src2, i32i8imm:$src3),
692 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
694 (v4f32 (vector_shuffle
695 VR128:$src1, (load addr:$src2),
696 SHUFP_shuffle_mask:$src3)))]>;
698 let AddedComplexity = 10 in {
699 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
700 (ops VR128:$dst, VR128:$src1, VR128:$src2),
701 "unpckhps {$src2, $dst|$dst, $src2}",
703 (v4f32 (vector_shuffle
704 VR128:$src1, VR128:$src2,
705 UNPCKH_shuffle_mask)))]>;
706 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
707 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
708 "unpckhps {$src2, $dst|$dst, $src2}",
710 (v4f32 (vector_shuffle
711 VR128:$src1, (load addr:$src2),
712 UNPCKH_shuffle_mask)))]>;
714 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
715 (ops VR128:$dst, VR128:$src1, VR128:$src2),
716 "unpcklps {$src2, $dst|$dst, $src2}",
718 (v4f32 (vector_shuffle
719 VR128:$src1, VR128:$src2,
720 UNPCKL_shuffle_mask)))]>;
721 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
722 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
723 "unpcklps {$src2, $dst|$dst, $src2}",
725 (v4f32 (vector_shuffle
726 VR128:$src1, (load addr:$src2),
727 UNPCKL_shuffle_mask)))]>;
732 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
733 "movmskps {$src, $dst|$dst, $src}",
734 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
735 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
736 "movmskpd {$src, $dst|$dst, $src}",
737 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
739 // Prefetching loads.
740 // TODO: no intrinsics for these?
741 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>;
742 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>;
743 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>;
744 def PREFETCHNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchnta $src", []>;
746 // Non-temporal stores
747 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
748 "movntps {$src, $dst|$dst, $src}",
749 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
751 // Load, store, and memory fence
752 def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>;
755 def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
756 "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
757 def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
758 "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
760 // Alias instructions that map zero vector to pxor / xorp* for sse.
761 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
762 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
764 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
766 // FR32 to 128-bit vector conversion.
767 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
768 "movss {$src, $dst|$dst, $src}",
770 (v4f32 (scalar_to_vector FR32:$src)))]>;
771 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
772 "movss {$src, $dst|$dst, $src}",
774 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
776 // FIXME: may not be able to eliminate this movss with coalescing the src and
777 // dest register classes are different. We really want to write this pattern
779 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
781 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
782 "movss {$src, $dst|$dst, $src}",
783 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
785 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
786 "movss {$src, $dst|$dst, $src}",
787 [(store (f32 (vector_extract (v4f32 VR128:$src),
788 (iPTR 0))), addr:$dst)]>;
791 // Move to lower bits of a VR128, leaving upper bits alone.
792 // Three operand (but two address) aliases.
793 let isTwoAddress = 1 in {
794 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
795 (ops VR128:$dst, VR128:$src1, FR32:$src2),
796 "movss {$src2, $dst|$dst, $src2}", []>;
798 let AddedComplexity = 15 in
799 def MOVLPSrr : SSI<0x10, MRMSrcReg,
800 (ops VR128:$dst, VR128:$src1, VR128:$src2),
801 "movss {$src2, $dst|$dst, $src2}",
803 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
804 MOVL_shuffle_mask)))]>;
807 // Move to lower bits of a VR128 and zeroing upper bits.
808 // Loading from memory automatically zeroing upper bits.
809 let AddedComplexity = 20 in
810 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
811 "movss {$src, $dst|$dst, $src}",
812 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
813 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
814 MOVL_shuffle_mask)))]>;
817 //===----------------------------------------------------------------------===//
819 //===----------------------------------------------------------------------===//
821 // SSE2 Instruction Templates:
823 // SDI - SSE2 instructions with XD prefix.
824 // PDI - SSE2 instructions with TB and OpSize prefixes.
825 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
827 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
828 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
829 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
830 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
831 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
832 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
834 // Helpers for defining instructions that directly correspond to intrinsics.
835 multiclass SD_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
836 def r : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
837 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
838 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
839 def m : SDI<o, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
840 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
841 [(set VR128:$dst, (v2f64 (IntId sse_load_f64:$src)))]>;
845 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
846 "movsd {$src, $dst|$dst, $src}", []>;
847 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
848 "movsd {$src, $dst|$dst, $src}",
849 [(set FR64:$dst, (loadf64 addr:$src))]>;
850 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
851 "movsd {$src, $dst|$dst, $src}",
852 [(store FR64:$src, addr:$dst)]>;
854 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
855 "sqrtsd {$src, $dst|$dst, $src}",
856 [(set FR64:$dst, (fsqrt FR64:$src))]>;
857 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
858 "sqrtsd {$src, $dst|$dst, $src}",
859 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
861 // Aliases to match intrinsics which expect XMM operand(s).
862 defm SQRTSD_Int : SD_IntUnary<0x51, "sqrtsd" , int_x86_sse2_sqrt_sd>;
864 // Conversion instructions
865 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
866 "cvttsd2si {$src, $dst|$dst, $src}",
867 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
868 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
869 "cvttsd2si {$src, $dst|$dst, $src}",
870 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
871 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
872 "cvtsd2ss {$src, $dst|$dst, $src}",
873 [(set FR32:$dst, (fround FR64:$src))]>;
874 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
875 "cvtsd2ss {$src, $dst|$dst, $src}",
876 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
877 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
878 "cvtsi2sd {$src, $dst|$dst, $src}",
879 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
880 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
881 "cvtsi2sd {$src, $dst|$dst, $src}",
882 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
884 // SSE2 instructions with XS prefix
885 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
886 "cvtss2sd {$src, $dst|$dst, $src}",
887 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
889 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
890 "cvtss2sd {$src, $dst|$dst, $src}",
891 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
894 // Match intrinsics which expect XMM operand(s).
895 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
896 "cvtsd2si {$src, $dst|$dst, $src}",
897 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
898 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
899 "cvtsd2si {$src, $dst|$dst, $src}",
900 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
901 (load addr:$src)))]>;
903 // Aliases for intrinsics
904 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
905 "cvttsd2si {$src, $dst|$dst, $src}",
907 (int_x86_sse2_cvttsd2si VR128:$src))]>;
908 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
909 "cvttsd2si {$src, $dst|$dst, $src}",
910 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
911 (load addr:$src)))]>;
913 // Comparison instructions
914 let isTwoAddress = 1 in {
915 def CMPSDrr : SDI<0xC2, MRMSrcReg,
916 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
917 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
918 def CMPSDrm : SDI<0xC2, MRMSrcMem,
919 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
920 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
923 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
924 "ucomisd {$src2, $src1|$src1, $src2}",
925 [(X86cmp FR64:$src1, FR64:$src2)]>;
926 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
927 "ucomisd {$src2, $src1|$src1, $src2}",
928 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
930 // Aliases to match intrinsics which expect XMM operand(s).
931 let isTwoAddress = 1 in {
932 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
933 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
934 "cmp${cc}sd {$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
936 VR128:$src, imm:$cc))]>;
937 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
938 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
939 "cmp${cc}sd {$src, $dst|$dst, $src}",
940 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
941 (load addr:$src), imm:$cc))]>;
944 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
945 "ucomisd {$src2, $src1|$src1, $src2}",
946 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
947 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
948 "ucomisd {$src2, $src1|$src1, $src2}",
949 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
951 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
952 "comisd {$src2, $src1|$src1, $src2}",
953 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
954 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
955 "comisd {$src2, $src1|$src1, $src2}",
956 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
958 // Aliases of packed instructions for scalar use. These all have names that
961 // Alias instructions that map fld0 to pxor for sse.
962 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
963 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
964 Requires<[HasSSE2]>, TB, OpSize;
966 // Alias instructions to do FR64 reg-to-reg copy using movapd. Upper bits are
968 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
969 "movapd {$src, $dst|$dst, $src}", []>;
971 // Alias instructions to load FR64 from f128mem using movapd. Upper bits are
973 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
974 "movapd {$src, $dst|$dst, $src}",
975 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
977 // Alias bitwise logical operations using SSE logical ops on packed FP values.
978 let isTwoAddress = 1 in {
979 let isCommutable = 1 in {
980 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
981 "andpd {$src2, $dst|$dst, $src2}",
982 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
983 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
984 "orpd {$src2, $dst|$dst, $src2}",
985 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
986 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
987 "xorpd {$src2, $dst|$dst, $src2}",
988 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
991 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
992 "andpd {$src2, $dst|$dst, $src2}",
993 [(set FR64:$dst, (X86fand FR64:$src1,
994 (X86loadpf64 addr:$src2)))]>;
995 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
996 "orpd {$src2, $dst|$dst, $src2}",
997 [(set FR64:$dst, (X86for FR64:$src1,
998 (X86loadpf64 addr:$src2)))]>;
999 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1000 "xorpd {$src2, $dst|$dst, $src2}",
1001 [(set FR64:$dst, (X86fxor FR64:$src1,
1002 (X86loadpf64 addr:$src2)))]>;
1004 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1005 (ops FR64:$dst, FR64:$src1, FR64:$src2),
1006 "andnpd {$src2, $dst|$dst, $src2}", []>;
1007 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1008 (ops FR64:$dst, FR64:$src1, f128mem:$src2),
1009 "andnpd {$src2, $dst|$dst, $src2}", []>;
1012 /// scalar_sse2_fp_binop_rm - Scalar SSE2 binops come in three basic forms:
1014 /// 1. f64 - This comes in SSE2 form for doubles.
1015 /// 2. rr vs rm - They include a reg+reg form and a reg+mem form.
1017 /// In addition, scalar SSE ops have an intrinsic form. This form is unlike the
1018 /// normal form, in that they take an entire vector (instead of a scalar) and
1019 /// leave the top elements undefined. This adds another two variants of the
1020 /// above permutations, giving us 8 forms for 'instruction'.
1022 let isTwoAddress = 1 in {
1023 multiclass scalar_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1024 SDNode OpNode, Intrinsic F64Int,
1025 bit Commutable = 0> {
1026 // Scalar operation, reg+reg.
1027 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
1028 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1029 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1030 let isCommutable = Commutable;
1033 // Scalar operation, reg+mem.
1034 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
1035 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1036 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1038 // Vector intrinsic operation, reg+reg.
1039 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1040 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1041 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1042 let isCommutable = Commutable;
1045 // Vector intrinsic operation, reg+mem.
1046 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
1047 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2}"),
1048 [(set VR128:$dst, (F64Int VR128:$src1,
1049 sse_load_f64:$src2))]>;
1053 // Arithmetic instructions
1054 defm ADD : scalar_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1055 defm MUL : scalar_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1056 defm SUB : scalar_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1057 defm DIV : scalar_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1059 defm MAX : scalar_sse2_fp_binop_rm<0x5F, "max", X86fmax, int_x86_sse2_max_sd>;
1060 defm MIN : scalar_sse2_fp_binop_rm<0x5D, "min", X86fmin, int_x86_sse2_min_sd>;
1062 //===----------------------------------------------------------------------===//
1063 // SSE packed FP Instructions
1065 // Move Instructions
1066 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1067 "movapd {$src, $dst|$dst, $src}", []>;
1068 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1069 "movapd {$src, $dst|$dst, $src}",
1070 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1072 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1073 "movapd {$src, $dst|$dst, $src}",
1074 [(store (v2f64 VR128:$src), addr:$dst)]>;
1076 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1077 "movupd {$src, $dst|$dst, $src}", []>;
1078 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1079 "movupd {$src, $dst|$dst, $src}",
1080 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1081 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1082 "movupd {$src, $dst|$dst, $src}",
1083 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1085 let isTwoAddress = 1 in {
1086 let AddedComplexity = 20 in {
1087 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1088 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1089 "movlpd {$src2, $dst|$dst, $src2}",
1091 (v2f64 (vector_shuffle VR128:$src1,
1092 (scalar_to_vector (loadf64 addr:$src2)),
1093 MOVLP_shuffle_mask)))]>;
1094 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1095 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1096 "movhpd {$src2, $dst|$dst, $src2}",
1098 (v2f64 (vector_shuffle VR128:$src1,
1099 (scalar_to_vector (loadf64 addr:$src2)),
1100 MOVHP_shuffle_mask)))]>;
1101 } // AddedComplexity
1104 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1105 "movlpd {$src, $dst|$dst, $src}",
1106 [(store (f64 (vector_extract (v2f64 VR128:$src),
1107 (iPTR 0))), addr:$dst)]>;
1109 // v2f64 extract element 1 is always custom lowered to unpack high to low
1110 // and extract element 0 so the non-store version isn't too horrible.
1111 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1112 "movhpd {$src, $dst|$dst, $src}",
1113 [(store (f64 (vector_extract
1114 (v2f64 (vector_shuffle VR128:$src, (undef),
1115 UNPCKH_shuffle_mask)), (iPTR 0))),
1118 // SSE2 instructions without OpSize prefix
1119 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1120 "cvtdq2ps {$src, $dst|$dst, $src}",
1121 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1122 TB, Requires<[HasSSE2]>;
1123 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1124 "cvtdq2ps {$src, $dst|$dst, $src}",
1125 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1126 (bitconvert (loadv2i64 addr:$src))))]>,
1127 TB, Requires<[HasSSE2]>;
1129 // SSE2 instructions with XS prefix
1130 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1131 "cvtdq2pd {$src, $dst|$dst, $src}",
1132 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1133 XS, Requires<[HasSSE2]>;
1134 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1135 "cvtdq2pd {$src, $dst|$dst, $src}",
1136 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1137 (bitconvert (loadv2i64 addr:$src))))]>,
1138 XS, Requires<[HasSSE2]>;
1140 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1141 "cvtps2dq {$src, $dst|$dst, $src}",
1142 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1143 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1144 "cvtps2dq {$src, $dst|$dst, $src}",
1145 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1146 (load addr:$src)))]>;
1147 // SSE2 packed instructions with XS prefix
1148 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1149 "cvttps2dq {$src, $dst|$dst, $src}",
1150 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1151 XS, Requires<[HasSSE2]>;
1152 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1153 "cvttps2dq {$src, $dst|$dst, $src}",
1154 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1155 (load addr:$src)))]>,
1156 XS, Requires<[HasSSE2]>;
1158 // SSE2 packed instructions with XD prefix
1159 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1160 "cvtpd2dq {$src, $dst|$dst, $src}",
1161 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1162 XD, Requires<[HasSSE2]>;
1163 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1164 "cvtpd2dq {$src, $dst|$dst, $src}",
1165 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1166 (load addr:$src)))]>,
1167 XD, Requires<[HasSSE2]>;
1169 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1170 "cvttpd2dq {$src, $dst|$dst, $src}",
1171 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1172 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1173 "cvttpd2dq {$src, $dst|$dst, $src}",
1174 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1175 (load addr:$src)))]>;
1177 // SSE2 instructions without OpSize prefix
1178 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1179 "cvtps2pd {$src, $dst|$dst, $src}",
1180 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1181 TB, Requires<[HasSSE2]>;
1182 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
1183 "cvtps2pd {$src, $dst|$dst, $src}",
1184 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1185 (load addr:$src)))]>,
1186 TB, Requires<[HasSSE2]>;
1188 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1189 "cvtpd2ps {$src, $dst|$dst, $src}",
1190 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1191 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
1192 "cvtpd2ps {$src, $dst|$dst, $src}",
1193 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1194 (load addr:$src)))]>;
1196 // Match intrinsics which expect XMM operand(s).
1197 // Aliases for intrinsics
1198 let isTwoAddress = 1 in {
1199 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1200 (ops VR128:$dst, VR128:$src1, GR32:$src2),
1201 "cvtsi2sd {$src2, $dst|$dst, $src2}",
1202 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1204 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1205 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
1206 "cvtsi2sd {$src2, $dst|$dst, $src2}",
1207 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1208 (loadi32 addr:$src2)))]>;
1209 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1210 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1211 "cvtsd2ss {$src2, $dst|$dst, $src2}",
1212 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1214 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1215 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1216 "cvtsd2ss {$src2, $dst|$dst, $src2}",
1217 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1218 (load addr:$src2)))]>;
1219 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1220 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1221 "cvtss2sd {$src2, $dst|$dst, $src2}",
1222 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1223 VR128:$src2))]>, XS,
1224 Requires<[HasSSE2]>;
1225 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1226 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
1227 "cvtss2sd {$src2, $dst|$dst, $src2}",
1228 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1229 (load addr:$src2)))]>, XS,
1230 Requires<[HasSSE2]>;
1233 /// packed_sse2_fp_binop_rm - Packed SSE binops come in three basic forms:
1234 /// 1. v2f64 - This comes in SSE2 form for doubles.
1235 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
1237 let isTwoAddress = 1 in {
1238 multiclass packed_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1239 SDNode OpNode, bit Commutable = 0> {
1240 // Packed operation, reg+reg.
1241 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1242 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1243 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1244 let isCommutable = Commutable;
1247 // Packed operation, reg+mem.
1248 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1249 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2}"),
1250 [(set VR128:$dst, (OpNode VR128:$src1, (loadv2f64 addr:$src2)))]>;
1254 defm ADD : packed_sse2_fp_binop_rm<0x58, "add", fadd, 1>;
1255 defm MUL : packed_sse2_fp_binop_rm<0x59, "mul", fmul, 1>;
1256 defm DIV : packed_sse2_fp_binop_rm<0x5E, "div", fdiv>;
1257 defm SUB : packed_sse2_fp_binop_rm<0x5C, "sub", fsub>;
1261 class PD_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1262 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1263 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
1264 [(set VR128:$dst, (IntId VR128:$src))]>;
1265 class PD_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1266 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1267 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
1268 [(set VR128:$dst, (IntId (load addr:$src)))]>;
1270 class PD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1271 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1272 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1273 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1274 class PD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1275 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
1276 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1277 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
1279 def SQRTPDr : PD_Intr<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
1280 def SQRTPDm : PD_Intm<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
1282 let isTwoAddress = 1 in {
1283 let isCommutable = 1 in {
1284 def MAXPDrr : PD_Intrr<0x5F, "maxpd", int_x86_sse2_max_pd>;
1285 def MINPDrr : PD_Intrr<0x5D, "minpd", int_x86_sse2_min_pd>;
1288 def MAXPDrm : PD_Intrm<0x5F, "maxpd", int_x86_sse2_max_pd>;
1289 def MINPDrm : PD_Intrm<0x5D, "minpd", int_x86_sse2_min_pd>;
1293 let isTwoAddress = 1 in {
1294 let isCommutable = 1 in {
1295 def ANDPDrr : PDI<0x54, MRMSrcReg,
1296 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1297 "andpd {$src2, $dst|$dst, $src2}",
1299 (and (bc_v2i64 (v2f64 VR128:$src1)),
1300 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1301 def ORPDrr : PDI<0x56, MRMSrcReg,
1302 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1303 "orpd {$src2, $dst|$dst, $src2}",
1305 (or (bc_v2i64 (v2f64 VR128:$src1)),
1306 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1307 def XORPDrr : PDI<0x57, MRMSrcReg,
1308 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1309 "xorpd {$src2, $dst|$dst, $src2}",
1311 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1312 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1315 def ANDPDrm : PDI<0x54, MRMSrcMem,
1316 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1317 "andpd {$src2, $dst|$dst, $src2}",
1319 (and (bc_v2i64 (v2f64 VR128:$src1)),
1320 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1321 def ORPDrm : PDI<0x56, MRMSrcMem,
1322 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1323 "orpd {$src2, $dst|$dst, $src2}",
1325 (or (bc_v2i64 (v2f64 VR128:$src1)),
1326 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1327 def XORPDrm : PDI<0x57, MRMSrcMem,
1328 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1329 "xorpd {$src2, $dst|$dst, $src2}",
1331 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1332 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1333 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1334 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1335 "andnpd {$src2, $dst|$dst, $src2}",
1337 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1338 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1339 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1340 (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1341 "andnpd {$src2, $dst|$dst, $src2}",
1343 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1344 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1347 let isTwoAddress = 1 in {
1348 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1349 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1350 "cmp${cc}pd {$src, $dst|$dst, $src}",
1351 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1352 VR128:$src, imm:$cc))]>;
1353 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1354 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1355 "cmp${cc}pd {$src, $dst|$dst, $src}",
1356 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1357 (load addr:$src), imm:$cc))]>;
1360 // Shuffle and unpack instructions
1361 let isTwoAddress = 1 in {
1362 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1363 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1364 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1365 [(set VR128:$dst, (v2f64 (vector_shuffle
1366 VR128:$src1, VR128:$src2,
1367 SHUFP_shuffle_mask:$src3)))]>;
1368 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1369 (ops VR128:$dst, VR128:$src1,
1370 f128mem:$src2, i8imm:$src3),
1371 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1373 (v2f64 (vector_shuffle
1374 VR128:$src1, (load addr:$src2),
1375 SHUFP_shuffle_mask:$src3)))]>;
1377 let AddedComplexity = 10 in {
1378 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1379 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1380 "unpckhpd {$src2, $dst|$dst, $src2}",
1382 (v2f64 (vector_shuffle
1383 VR128:$src1, VR128:$src2,
1384 UNPCKH_shuffle_mask)))]>;
1385 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1386 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1387 "unpckhpd {$src2, $dst|$dst, $src2}",
1389 (v2f64 (vector_shuffle
1390 VR128:$src1, (load addr:$src2),
1391 UNPCKH_shuffle_mask)))]>;
1393 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1394 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1395 "unpcklpd {$src2, $dst|$dst, $src2}",
1397 (v2f64 (vector_shuffle
1398 VR128:$src1, VR128:$src2,
1399 UNPCKL_shuffle_mask)))]>;
1400 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1401 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1402 "unpcklpd {$src2, $dst|$dst, $src2}",
1404 (v2f64 (vector_shuffle
1405 VR128:$src1, (load addr:$src2),
1406 UNPCKL_shuffle_mask)))]>;
1407 } // AddedComplexity
1411 //===----------------------------------------------------------------------===//
1412 // SSE integer instructions
1414 // Move Instructions
1415 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1416 "movdqa {$src, $dst|$dst, $src}", []>;
1417 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1418 "movdqa {$src, $dst|$dst, $src}",
1419 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1420 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1421 "movdqa {$src, $dst|$dst, $src}",
1422 [(store (v2i64 VR128:$src), addr:$dst)]>;
1423 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1424 "movdqu {$src, $dst|$dst, $src}",
1425 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1426 XS, Requires<[HasSSE2]>;
1427 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1428 "movdqu {$src, $dst|$dst, $src}",
1429 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1430 XS, Requires<[HasSSE2]>;
1433 let isTwoAddress = 1 in {
1435 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1436 bit Commutable = 0> {
1437 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1438 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1439 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1440 let isCommutable = Commutable;
1442 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1443 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1444 [(set VR128:$dst, (IntId VR128:$src1,
1445 (bitconvert (loadv2i64 addr:$src2))))]>;
1448 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1449 string OpcodeStr, Intrinsic IntId> {
1450 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1451 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1452 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1453 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1454 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1455 [(set VR128:$dst, (IntId VR128:$src1,
1456 (bitconvert (loadv2i64 addr:$src2))))]>;
1457 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1458 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1459 [(set VR128:$dst, (IntId VR128:$src1,
1460 (scalar_to_vector (i32 imm:$src2))))]>;
1464 /// PDI_binop_rm - Simple SSE2 binary operator.
1465 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1466 ValueType OpVT, bit Commutable = 0> {
1467 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1468 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1469 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1470 let isCommutable = Commutable;
1472 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1473 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1474 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1475 (bitconvert (loadv2i64 addr:$src2)))))]>;
1478 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1480 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1481 /// to collapse (bitconvert VT to VT) into its operand.
1483 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1484 bit Commutable = 0> {
1485 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1486 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1487 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1488 let isCommutable = Commutable;
1490 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1491 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1492 [(set VR128:$dst, (OpNode VR128:$src1,(loadv2i64 addr:$src2)))]>;
1497 // 128-bit Integer Arithmetic
1499 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1500 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1501 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1502 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1504 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1505 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1506 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1507 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1509 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1510 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1511 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1512 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1514 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1515 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1516 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1517 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1519 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1521 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1522 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1523 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1525 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1527 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1528 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1531 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1532 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1533 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1534 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1535 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1538 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1539 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1540 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1542 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1543 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1544 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1546 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1547 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1548 // PSRAQ doesn't exist in SSE[1-3].
1550 // 128-bit logical shifts.
1551 let isTwoAddress = 1 in {
1552 def PSLLDQri : PDIi8<0x73, MRM7r,
1553 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1554 "pslldq {$src2, $dst|$dst, $src2}", []>;
1555 def PSRLDQri : PDIi8<0x73, MRM3r,
1556 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1557 "psrldq {$src2, $dst|$dst, $src2}", []>;
1558 // PSRADQri doesn't exist in SSE[1-3].
1561 let Predicates = [HasSSE2] in {
1562 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1563 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1564 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1565 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1566 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1567 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1571 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1572 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1573 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1575 let isTwoAddress = 1 in {
1576 def PANDNrr : PDI<0xDF, MRMSrcReg,
1577 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1578 "pandn {$src2, $dst|$dst, $src2}",
1579 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1582 def PANDNrm : PDI<0xDF, MRMSrcMem,
1583 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1584 "pandn {$src2, $dst|$dst, $src2}",
1585 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1586 (load addr:$src2))))]>;
1589 // SSE2 Integer comparison
1590 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1591 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1592 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1593 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1594 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1595 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1597 // Pack instructions
1598 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1599 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1600 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1602 // Shuffle and unpack instructions
1603 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1604 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1605 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1606 [(set VR128:$dst, (v4i32 (vector_shuffle
1607 VR128:$src1, (undef),
1608 PSHUFD_shuffle_mask:$src2)))]>;
1609 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1610 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1611 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1612 [(set VR128:$dst, (v4i32 (vector_shuffle
1613 (bc_v4i32(loadv2i64 addr:$src1)),
1615 PSHUFD_shuffle_mask:$src2)))]>;
1617 // SSE2 with ImmT == Imm8 and XS prefix.
1618 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1619 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1620 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1621 [(set VR128:$dst, (v8i16 (vector_shuffle
1622 VR128:$src1, (undef),
1623 PSHUFHW_shuffle_mask:$src2)))]>,
1624 XS, Requires<[HasSSE2]>;
1625 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1626 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1627 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1628 [(set VR128:$dst, (v8i16 (vector_shuffle
1629 (bc_v8i16 (loadv2i64 addr:$src1)),
1631 PSHUFHW_shuffle_mask:$src2)))]>,
1632 XS, Requires<[HasSSE2]>;
1634 // SSE2 with ImmT == Imm8 and XD prefix.
1635 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1636 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1637 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1638 [(set VR128:$dst, (v8i16 (vector_shuffle
1639 VR128:$src1, (undef),
1640 PSHUFLW_shuffle_mask:$src2)))]>,
1641 XD, Requires<[HasSSE2]>;
1642 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1643 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1644 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1645 [(set VR128:$dst, (v8i16 (vector_shuffle
1646 (bc_v8i16 (loadv2i64 addr:$src1)),
1648 PSHUFLW_shuffle_mask:$src2)))]>,
1649 XD, Requires<[HasSSE2]>;
1652 let isTwoAddress = 1 in {
1653 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1654 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1655 "punpcklbw {$src2, $dst|$dst, $src2}",
1657 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1658 UNPCKL_shuffle_mask)))]>;
1659 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1660 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1661 "punpcklbw {$src2, $dst|$dst, $src2}",
1663 (v16i8 (vector_shuffle VR128:$src1,
1664 (bc_v16i8 (loadv2i64 addr:$src2)),
1665 UNPCKL_shuffle_mask)))]>;
1666 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1667 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1668 "punpcklwd {$src2, $dst|$dst, $src2}",
1670 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1671 UNPCKL_shuffle_mask)))]>;
1672 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1673 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1674 "punpcklwd {$src2, $dst|$dst, $src2}",
1676 (v8i16 (vector_shuffle VR128:$src1,
1677 (bc_v8i16 (loadv2i64 addr:$src2)),
1678 UNPCKL_shuffle_mask)))]>;
1679 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1680 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1681 "punpckldq {$src2, $dst|$dst, $src2}",
1683 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1684 UNPCKL_shuffle_mask)))]>;
1685 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1686 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1687 "punpckldq {$src2, $dst|$dst, $src2}",
1689 (v4i32 (vector_shuffle VR128:$src1,
1690 (bc_v4i32 (loadv2i64 addr:$src2)),
1691 UNPCKL_shuffle_mask)))]>;
1692 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1693 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1694 "punpcklqdq {$src2, $dst|$dst, $src2}",
1696 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1697 UNPCKL_shuffle_mask)))]>;
1698 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1699 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1700 "punpcklqdq {$src2, $dst|$dst, $src2}",
1702 (v2i64 (vector_shuffle VR128:$src1,
1703 (loadv2i64 addr:$src2),
1704 UNPCKL_shuffle_mask)))]>;
1706 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1707 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1708 "punpckhbw {$src2, $dst|$dst, $src2}",
1710 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1711 UNPCKH_shuffle_mask)))]>;
1712 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1713 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1714 "punpckhbw {$src2, $dst|$dst, $src2}",
1716 (v16i8 (vector_shuffle VR128:$src1,
1717 (bc_v16i8 (loadv2i64 addr:$src2)),
1718 UNPCKH_shuffle_mask)))]>;
1719 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1720 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1721 "punpckhwd {$src2, $dst|$dst, $src2}",
1723 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1724 UNPCKH_shuffle_mask)))]>;
1725 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1726 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1727 "punpckhwd {$src2, $dst|$dst, $src2}",
1729 (v8i16 (vector_shuffle VR128:$src1,
1730 (bc_v8i16 (loadv2i64 addr:$src2)),
1731 UNPCKH_shuffle_mask)))]>;
1732 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1733 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1734 "punpckhdq {$src2, $dst|$dst, $src2}",
1736 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1737 UNPCKH_shuffle_mask)))]>;
1738 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1739 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1740 "punpckhdq {$src2, $dst|$dst, $src2}",
1742 (v4i32 (vector_shuffle VR128:$src1,
1743 (bc_v4i32 (loadv2i64 addr:$src2)),
1744 UNPCKH_shuffle_mask)))]>;
1745 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1746 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1747 "punpckhqdq {$src2, $dst|$dst, $src2}",
1749 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1750 UNPCKH_shuffle_mask)))]>;
1751 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1752 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1753 "punpckhqdq {$src2, $dst|$dst, $src2}",
1755 (v2i64 (vector_shuffle VR128:$src1,
1756 (loadv2i64 addr:$src2),
1757 UNPCKH_shuffle_mask)))]>;
1761 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1762 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1763 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1764 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1765 (iPTR imm:$src2)))]>;
1766 let isTwoAddress = 1 in {
1767 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1768 (ops VR128:$dst, VR128:$src1,
1769 GR32:$src2, i32i8imm:$src3),
1770 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1772 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1773 GR32:$src2, (iPTR imm:$src3))))]>;
1774 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1775 (ops VR128:$dst, VR128:$src1,
1776 i16mem:$src2, i32i8imm:$src3),
1777 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1779 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1780 (i32 (anyext (loadi16 addr:$src2))),
1781 (iPTR imm:$src3))))]>;
1785 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1786 "pmovmskb {$src, $dst|$dst, $src}",
1787 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1789 // Conditional store
1790 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1791 "maskmovdqu {$mask, $src|$src, $mask}",
1792 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1795 // Non-temporal stores
1796 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1797 "movntpd {$src, $dst|$dst, $src}",
1798 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1799 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1800 "movntdq {$src, $dst|$dst, $src}",
1801 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1802 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1803 "movnti {$src, $dst|$dst, $src}",
1804 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1805 TB, Requires<[HasSSE2]>;
1808 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
1809 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
1810 TB, Requires<[HasSSE2]>;
1812 // Load, store, and memory fence
1813 def LFENCE : I<0xAE, MRM5m, (ops),
1814 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
1815 def MFENCE : I<0xAE, MRM6m, (ops),
1816 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
1819 // Alias instructions that map zero vector to pxor / xorp* for sse.
1820 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1821 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1822 "pcmpeqd $dst, $dst",
1823 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1825 // FR64 to 128-bit vector conversion.
1826 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1827 "movsd {$src, $dst|$dst, $src}",
1829 (v2f64 (scalar_to_vector FR64:$src)))]>;
1830 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1831 "movsd {$src, $dst|$dst, $src}",
1833 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1835 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1836 "movd {$src, $dst|$dst, $src}",
1838 (v4i32 (scalar_to_vector GR32:$src)))]>;
1839 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1840 "movd {$src, $dst|$dst, $src}",
1842 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1844 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (ops FR32:$dst, GR32:$src),
1845 "movd {$src, $dst|$dst, $src}",
1846 [(set FR32:$dst, (bitconvert GR32:$src))]>;
1848 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
1849 "movd {$src, $dst|$dst, $src}",
1850 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
1852 // SSE2 instructions with XS prefix
1853 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1854 "movq {$src, $dst|$dst, $src}",
1856 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1857 Requires<[HasSSE2]>;
1858 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1859 "movq {$src, $dst|$dst, $src}",
1860 [(store (i64 (vector_extract (v2i64 VR128:$src),
1861 (iPTR 0))), addr:$dst)]>;
1863 // FIXME: may not be able to eliminate this movss with coalescing the src and
1864 // dest register classes are different. We really want to write this pattern
1866 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1867 // (f32 FR32:$src)>;
1868 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1869 "movsd {$src, $dst|$dst, $src}",
1870 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1872 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1873 "movsd {$src, $dst|$dst, $src}",
1874 [(store (f64 (vector_extract (v2f64 VR128:$src),
1875 (iPTR 0))), addr:$dst)]>;
1876 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
1877 "movd {$src, $dst|$dst, $src}",
1878 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
1880 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1881 "movd {$src, $dst|$dst, $src}",
1882 [(store (i32 (vector_extract (v4i32 VR128:$src),
1883 (iPTR 0))), addr:$dst)]>;
1885 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, FR32:$src),
1886 "movd {$src, $dst|$dst, $src}",
1887 [(set GR32:$dst, (bitconvert FR32:$src))]>;
1888 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, FR32:$src),
1889 "movd {$src, $dst|$dst, $src}",
1890 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
1893 // Move to lower bits of a VR128, leaving upper bits alone.
1894 // Three operand (but two address) aliases.
1895 let isTwoAddress = 1 in {
1896 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
1897 (ops VR128:$dst, VR128:$src1, FR64:$src2),
1898 "movsd {$src2, $dst|$dst, $src2}", []>;
1900 let AddedComplexity = 15 in
1901 def MOVLPDrr : SDI<0x10, MRMSrcReg,
1902 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1903 "movsd {$src2, $dst|$dst, $src2}",
1905 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1906 MOVL_shuffle_mask)))]>;
1909 // Store / copy lower 64-bits of a XMM register.
1910 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1911 "movq {$src, $dst|$dst, $src}",
1912 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1914 // Move to lower bits of a VR128 and zeroing upper bits.
1915 // Loading from memory automatically zeroing upper bits.
1916 let AddedComplexity = 20 in
1917 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1918 "movsd {$src, $dst|$dst, $src}",
1920 (v2f64 (vector_shuffle immAllZerosV,
1921 (v2f64 (scalar_to_vector
1922 (loadf64 addr:$src))),
1923 MOVL_shuffle_mask)))]>;
1925 let AddedComplexity = 15 in
1926 // movd / movq to XMM register zero-extends
1927 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1928 "movd {$src, $dst|$dst, $src}",
1930 (v4i32 (vector_shuffle immAllZerosV,
1931 (v4i32 (scalar_to_vector GR32:$src)),
1932 MOVL_shuffle_mask)))]>;
1933 let AddedComplexity = 20 in
1934 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1935 "movd {$src, $dst|$dst, $src}",
1937 (v4i32 (vector_shuffle immAllZerosV,
1938 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
1939 MOVL_shuffle_mask)))]>;
1941 // Moving from XMM to XMM but still clear upper 64 bits.
1942 let AddedComplexity = 15 in
1943 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1944 "movq {$src, $dst|$dst, $src}",
1945 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
1946 XS, Requires<[HasSSE2]>;
1947 let AddedComplexity = 20 in
1948 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1949 "movq {$src, $dst|$dst, $src}",
1950 [(set VR128:$dst, (int_x86_sse2_movl_dq
1951 (bitconvert (loadv2i64 addr:$src))))]>,
1952 XS, Requires<[HasSSE2]>;
1955 //===----------------------------------------------------------------------===//
1956 // SSE3 Instructions
1957 //===----------------------------------------------------------------------===//
1959 // SSE3 Instruction Templates:
1961 // S3I - SSE3 instructions with TB and OpSize prefixes.
1962 // S3SI - SSE3 instructions with XS prefix.
1963 // S3DI - SSE3 instructions with XD prefix.
1965 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
1966 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
1967 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
1968 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
1969 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
1970 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
1972 // Move Instructions
1973 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1974 "movshdup {$src, $dst|$dst, $src}",
1975 [(set VR128:$dst, (v4f32 (vector_shuffle
1976 VR128:$src, (undef),
1977 MOVSHDUP_shuffle_mask)))]>;
1978 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1979 "movshdup {$src, $dst|$dst, $src}",
1980 [(set VR128:$dst, (v4f32 (vector_shuffle
1981 (loadv4f32 addr:$src), (undef),
1982 MOVSHDUP_shuffle_mask)))]>;
1984 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1985 "movsldup {$src, $dst|$dst, $src}",
1986 [(set VR128:$dst, (v4f32 (vector_shuffle
1987 VR128:$src, (undef),
1988 MOVSLDUP_shuffle_mask)))]>;
1989 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
1990 "movsldup {$src, $dst|$dst, $src}",
1991 [(set VR128:$dst, (v4f32 (vector_shuffle
1992 (loadv4f32 addr:$src), (undef),
1993 MOVSLDUP_shuffle_mask)))]>;
1995 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1996 "movddup {$src, $dst|$dst, $src}",
1997 [(set VR128:$dst, (v2f64 (vector_shuffle
1998 VR128:$src, (undef),
1999 SSE_splat_lo_mask)))]>;
2000 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2001 "movddup {$src, $dst|$dst, $src}",
2003 (v2f64 (vector_shuffle
2004 (scalar_to_vector (loadf64 addr:$src)),
2006 SSE_splat_lo_mask)))]>;
2009 let isTwoAddress = 1 in {
2010 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2011 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2012 "addsubps {$src2, $dst|$dst, $src2}",
2013 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2015 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2016 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2017 "addsubps {$src2, $dst|$dst, $src2}",
2018 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2019 (load addr:$src2)))]>;
2020 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2021 (ops VR128:$dst, VR128:$src1, VR128:$src2),
2022 "addsubpd {$src2, $dst|$dst, $src2}",
2023 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2025 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2026 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2027 "addsubpd {$src2, $dst|$dst, $src2}",
2028 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2029 (load addr:$src2)))]>;
2032 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
2033 "lddqu {$src, $dst|$dst, $src}",
2034 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2037 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2038 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2039 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2040 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2041 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2042 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2043 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2044 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2045 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2046 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2047 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2048 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2049 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2050 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
2051 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2052 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2054 let isTwoAddress = 1 in {
2055 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2056 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2057 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2058 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2059 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2060 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2061 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2062 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2065 // Thread synchronization
2066 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2067 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2068 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2069 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2071 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2072 let AddedComplexity = 15 in
2073 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2074 MOVSHDUP_shuffle_mask)),
2075 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2076 let AddedComplexity = 20 in
2077 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2078 MOVSHDUP_shuffle_mask)),
2079 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2081 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2082 let AddedComplexity = 15 in
2083 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2084 MOVSLDUP_shuffle_mask)),
2085 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2086 let AddedComplexity = 20 in
2087 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2088 MOVSLDUP_shuffle_mask)),
2089 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2091 //===----------------------------------------------------------------------===//
2092 // SSSE3 Instructions
2093 //===----------------------------------------------------------------------===//
2095 // SSE3 Instruction Templates:
2097 // SS38I - SSSE3 instructions with T8 and OpSize prefixes.
2098 // SS3AI - SSSE3 instructions with TA and OpSize prefixes.
2100 class SS38I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2101 : I<o, F, ops, asm, pattern>, T8, OpSize, Requires<[HasSSSE3]>;
2102 class SS3AI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
2103 : I<o, F, ops, asm, pattern>, TA, OpSize, Requires<[HasSSSE3]>;
2105 /// SS3I_binop_rm_int - Simple SSSE3 binary operatr whose type is v2i64.
2106 let isTwoAddress = 1 in {
2107 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2108 bit Commutable = 0> {
2109 def rr : SS38I<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2110 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2111 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
2112 let isCommutable = Commutable;
2114 def rm : SS38I<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
2115 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
2118 (bitconvert (loadv2i64 addr:$src2))))]>;
2122 defm PMULHRSW128 : SS3I_binop_rm_int<0x0B, "pmulhrsw",
2123 int_x86_ssse3_pmulhrsw_128, 1>;
2125 //===----------------------------------------------------------------------===//
2126 // Non-Instruction Patterns
2127 //===----------------------------------------------------------------------===//
2129 // 128-bit vector undef's.
2130 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2131 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2132 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2133 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2134 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2136 // 128-bit vector all zero's.
2137 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2138 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2139 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2140 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2141 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2143 // 128-bit vector all one's.
2144 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2145 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2146 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2147 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2148 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2150 // Store 128-bit integer vector values.
2151 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2152 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2153 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2154 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2155 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2156 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2158 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2160 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2161 Requires<[HasSSE2]>;
2162 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2163 Requires<[HasSSE2]>;
2166 let Predicates = [HasSSE2] in {
2167 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2168 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2169 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2170 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2171 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2172 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2173 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2174 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2175 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2176 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2177 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2178 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2179 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2180 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2181 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2182 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2183 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2184 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2185 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2186 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2187 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2188 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2189 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2190 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2191 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2192 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2193 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2194 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2195 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2196 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2199 // Move scalar to XMM zero-extended
2200 // movd to XMM register zero-extends
2201 let AddedComplexity = 15 in {
2202 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2203 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2204 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2205 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2206 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2207 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2208 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2209 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2210 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2211 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2212 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2213 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2214 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2217 // Splat v2f64 / v2i64
2218 let AddedComplexity = 10 in {
2219 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2220 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2221 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2222 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2223 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2224 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2225 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2226 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2230 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2231 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2232 Requires<[HasSSE1]>;
2234 // Special unary SHUFPSrri case.
2235 // FIXME: when we want non two-address code, then we should use PSHUFD?
2236 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2237 SHUFP_unary_shuffle_mask:$sm),
2238 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2239 Requires<[HasSSE1]>;
2240 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2241 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2242 SHUFP_unary_shuffle_mask:$sm),
2243 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2244 Requires<[HasSSE2]>;
2245 // Special binary v4i32 shuffle cases with SHUFPS.
2246 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2247 PSHUFD_binary_shuffle_mask:$sm),
2248 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2249 Requires<[HasSSE2]>;
2250 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2251 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2252 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2253 Requires<[HasSSE2]>;
2255 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2256 let AddedComplexity = 10 in {
2257 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2258 UNPCKL_v_undef_shuffle_mask)),
2259 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2260 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2261 UNPCKL_v_undef_shuffle_mask)),
2262 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2263 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2264 UNPCKL_v_undef_shuffle_mask)),
2265 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2266 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2267 UNPCKL_v_undef_shuffle_mask)),
2268 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2271 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2272 let AddedComplexity = 10 in {
2273 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2274 UNPCKH_v_undef_shuffle_mask)),
2275 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2276 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2277 UNPCKH_v_undef_shuffle_mask)),
2278 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2279 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2280 UNPCKH_v_undef_shuffle_mask)),
2281 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2282 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2283 UNPCKH_v_undef_shuffle_mask)),
2284 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2287 let AddedComplexity = 15 in {
2288 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2289 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2290 MOVHP_shuffle_mask)),
2291 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2293 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2294 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2295 MOVHLPS_shuffle_mask)),
2296 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2298 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2299 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2300 MOVHLPS_v_undef_shuffle_mask)),
2301 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2302 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2303 MOVHLPS_v_undef_shuffle_mask)),
2304 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2307 let AddedComplexity = 20 in {
2308 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2309 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2310 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2311 MOVLP_shuffle_mask)),
2312 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2313 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2314 MOVLP_shuffle_mask)),
2315 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2316 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2317 MOVHP_shuffle_mask)),
2318 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2319 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2320 MOVHP_shuffle_mask)),
2321 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2323 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2324 MOVLP_shuffle_mask)),
2325 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2326 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2327 MOVLP_shuffle_mask)),
2328 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2329 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2330 MOVHP_shuffle_mask)),
2331 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2332 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2333 MOVLP_shuffle_mask)),
2334 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2337 let AddedComplexity = 15 in {
2338 // Setting the lowest element in the vector.
2339 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2340 MOVL_shuffle_mask)),
2341 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2342 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2343 MOVL_shuffle_mask)),
2344 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2346 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2347 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2348 MOVLP_shuffle_mask)),
2349 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2350 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2351 MOVLP_shuffle_mask)),
2352 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2355 // Set lowest element and zero upper elements.
2356 let AddedComplexity = 20 in
2357 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2358 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2359 MOVL_shuffle_mask)),
2360 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2362 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2363 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2364 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2365 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2366 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2367 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2368 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2369 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2370 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2371 Requires<[HasSSE2]>;
2372 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2373 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2374 Requires<[HasSSE2]>;
2375 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2376 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2377 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2378 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2379 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2380 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2381 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2382 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2383 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2384 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2385 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2386 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2387 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2388 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2389 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2390 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2392 // Some special case pandn patterns.
2393 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2395 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2396 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2398 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2399 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2401 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2403 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2404 (load addr:$src2))),
2405 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2406 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2407 (load addr:$src2))),
2408 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2409 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2410 (load addr:$src2))),
2411 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2414 def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2415 Requires<[HasSSE1]>;