1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def X86aesimc : SDNode<"X86ISD::AESIMC", SDTIntBinOp>;
73 def X86aesenc : SDNode<"X86ISD::AESENC", SDTIntBinOp>;
74 def X86aesenclast : SDNode<"X86ISD::AESENCLAST", SDTIntBinOp>;
75 def X86aesdec : SDNode<"X86ISD::AESDEC", SDTIntBinOp>;
76 def X86aesdeclast : SDNode<"X86ISD::AESDECLAST", SDTIntBinOp>;
78 def SDTX86CmpPTest : SDTypeProfile<0, 2, [SDTCisVT<0, v4f32>,
80 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
82 //===----------------------------------------------------------------------===//
83 // SSE Complex Patterns
84 //===----------------------------------------------------------------------===//
86 // These are 'extloads' from a scalar to the low element of a vector, zeroing
87 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
89 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
90 [SDNPHasChain, SDNPMayLoad]>;
91 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
92 [SDNPHasChain, SDNPMayLoad]>;
94 def ssmem : Operand<v4f32> {
95 let PrintMethod = "printf32mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
99 def sdmem : Operand<v2f64> {
100 let PrintMethod = "printf64mem";
101 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
102 let ParserMatchClass = X86MemAsmOperand;
105 //===----------------------------------------------------------------------===//
106 // SSE pattern fragments
107 //===----------------------------------------------------------------------===//
109 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
110 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
111 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
112 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
114 // Like 'store', but always requires vector alignment.
115 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
116 (store node:$val, node:$ptr), [{
117 return cast<StoreSDNode>(N)->getAlignment() >= 16;
120 // Like 'load', but always requires vector alignment.
121 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
122 return cast<LoadSDNode>(N)->getAlignment() >= 16;
125 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
126 (f32 (alignedload node:$ptr))>;
127 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
128 (f64 (alignedload node:$ptr))>;
129 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
130 (v4f32 (alignedload node:$ptr))>;
131 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
132 (v2f64 (alignedload node:$ptr))>;
133 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
134 (v4i32 (alignedload node:$ptr))>;
135 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
136 (v2i64 (alignedload node:$ptr))>;
138 // Like 'load', but uses special alignment checks suitable for use in
139 // memory operands in most SSE instructions, which are required to
140 // be naturally aligned on some targets but not on others. If the subtarget
141 // allows unaligned accesses, match any load, though this may require
142 // setting a feature bit in the processor (on startup, for example).
143 // Opteron 10h and later implement such a feature.
144 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
145 return Subtarget->hasVectorUAMem()
146 || cast<LoadSDNode>(N)->getAlignment() >= 16;
149 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
150 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
151 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
152 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
153 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
154 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
155 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
157 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
159 // FIXME: 8 byte alignment for mmx reads is not required
160 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
161 return cast<LoadSDNode>(N)->getAlignment() >= 8;
164 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
165 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
166 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
167 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
170 // Like 'store', but requires the non-temporal bit to be set
171 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
172 (st node:$val, node:$ptr), [{
173 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
174 return ST->isNonTemporal();
178 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
179 (st node:$val, node:$ptr), [{
180 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
181 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
182 ST->getAddressingMode() == ISD::UNINDEXED &&
183 ST->getAlignment() >= 16;
187 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
188 (st node:$val, node:$ptr), [{
189 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
190 return ST->isNonTemporal() &&
191 ST->getAlignment() < 16;
195 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
196 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
197 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
198 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
199 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
200 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
202 def vzmovl_v2i64 : PatFrag<(ops node:$src),
203 (bitconvert (v2i64 (X86vzmovl
204 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
205 def vzmovl_v4i32 : PatFrag<(ops node:$src),
206 (bitconvert (v4i32 (X86vzmovl
207 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
209 def vzload_v2i64 : PatFrag<(ops node:$src),
210 (bitconvert (v2i64 (X86vzload node:$src)))>;
213 def fp32imm0 : PatLeaf<(f32 fpimm), [{
214 return N->isExactlyValue(+0.0);
217 // BYTE_imm - Transform bit immediates into byte immediates.
218 def BYTE_imm : SDNodeXForm<imm, [{
219 // Transformation function: imm >> 3
220 return getI32Imm(N->getZExtValue() >> 3);
223 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
225 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
226 return getI8Imm(X86::getShuffleSHUFImmediate(N));
229 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
231 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
232 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
235 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
237 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
238 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
241 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
243 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
244 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
247 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
248 (vector_shuffle node:$lhs, node:$rhs), [{
249 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
250 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
253 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
263 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
268 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
273 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
278 def movl : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
283 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
288 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
293 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
298 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
303 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
313 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_shuf_imm>;
323 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshufhw_imm>;
328 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_pshuflw_imm>;
333 def palign : PatFrag<(ops node:$lhs, node:$rhs),
334 (vector_shuffle node:$lhs, node:$rhs), [{
335 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
336 }], SHUFFLE_get_palign_imm>;
338 //===----------------------------------------------------------------------===//
339 // SSE scalar FP Instructions
340 //===----------------------------------------------------------------------===//
342 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
343 // instruction selection into a branch sequence.
344 let Uses = [EFLAGS], usesCustomInserter = 1 in {
345 def CMOV_FR32 : I<0, Pseudo,
346 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
347 "#CMOV_FR32 PSEUDO!",
348 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
350 def CMOV_FR64 : I<0, Pseudo,
351 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
352 "#CMOV_FR64 PSEUDO!",
353 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
355 def CMOV_V4F32 : I<0, Pseudo,
356 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
357 "#CMOV_V4F32 PSEUDO!",
359 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
361 def CMOV_V2F64 : I<0, Pseudo,
362 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
363 "#CMOV_V2F64 PSEUDO!",
365 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
367 def CMOV_V2I64 : I<0, Pseudo,
368 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
369 "#CMOV_V2I64 PSEUDO!",
371 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
379 // Move Instructions. Register-to-register movss is not used for FR32
380 // register copies because it's a partial register update; FsMOVAPSrr is
381 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
382 // because INSERT_SUBREG requires that the insert be implementable in terms of
383 // a copy, and just mentioned, we don't use movss for copies.
384 let Constraints = "$src1 = $dst" in
385 def MOVSSrr : SSI<0x10, MRMSrcReg,
386 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
387 "movss\t{$src2, $dst|$dst, $src2}",
388 [(set (v4f32 VR128:$dst),
389 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
391 // Extract the low 32-bit value from one vector and insert it into another.
392 let AddedComplexity = 15 in
393 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
394 (MOVSSrr (v4f32 VR128:$src1),
395 (EXTRACT_SUBREG (v4f32 VR128:$src2), x86_subreg_ss))>;
397 // Implicitly promote a 32-bit scalar to a vector.
398 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
399 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, x86_subreg_ss)>;
401 // Loading from memory automatically zeroing upper bits.
402 let canFoldAsLoad = 1, isReMaterializable = 1 in
403 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
404 "movss\t{$src, $dst|$dst, $src}",
405 [(set FR32:$dst, (loadf32 addr:$src))]>;
407 // MOVSSrm zeros the high parts of the register; represent this
408 // with SUBREG_TO_REG.
409 let AddedComplexity = 20 in {
410 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
411 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
412 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
413 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
414 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
415 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
418 // Store scalar value to memory.
419 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
420 "movss\t{$src, $dst|$dst, $src}",
421 [(store FR32:$src, addr:$dst)]>;
423 // Extract and store.
424 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
427 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
429 // Conversion instructions
430 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
431 "cvttss2si\t{$src, $dst|$dst, $src}",
432 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
433 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
434 "cvttss2si\t{$src, $dst|$dst, $src}",
435 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
436 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
437 "cvtsi2ss\t{$src, $dst|$dst, $src}",
438 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
439 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
440 "cvtsi2ss\t{$src, $dst|$dst, $src}",
441 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
443 // Match intrinsics which expect XMM operand(s).
444 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
445 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
446 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
447 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
449 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
450 "cvtss2si\t{$src, $dst|$dst, $src}",
451 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
452 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
453 "cvtss2si\t{$src, $dst|$dst, $src}",
454 [(set GR32:$dst, (int_x86_sse_cvtss2si
455 (load addr:$src)))]>;
457 // Match intrinisics which expect MM and XMM operand(s).
458 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
459 "cvtps2pi\t{$src, $dst|$dst, $src}",
460 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
461 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
462 "cvtps2pi\t{$src, $dst|$dst, $src}",
463 [(set VR64:$dst, (int_x86_sse_cvtps2pi
464 (load addr:$src)))]>;
465 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
466 "cvttps2pi\t{$src, $dst|$dst, $src}",
467 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
468 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
469 "cvttps2pi\t{$src, $dst|$dst, $src}",
470 [(set VR64:$dst, (int_x86_sse_cvttps2pi
471 (load addr:$src)))]>;
472 let Constraints = "$src1 = $dst" in {
473 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
474 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
478 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
479 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
480 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
481 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
482 (load addr:$src2)))]>;
485 // Aliases for intrinsics
486 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
487 "cvttss2si\t{$src, $dst|$dst, $src}",
489 (int_x86_sse_cvttss2si VR128:$src))]>;
490 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
491 "cvttss2si\t{$src, $dst|$dst, $src}",
493 (int_x86_sse_cvttss2si(load addr:$src)))]>;
495 let Constraints = "$src1 = $dst" in {
496 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
497 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
501 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
502 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
503 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
504 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
505 (loadi32 addr:$src2)))]>;
508 // Comparison instructions
509 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
510 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
511 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
512 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
514 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
515 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
516 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
519 let Defs = [EFLAGS] in {
520 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
521 "ucomiss\t{$src2, $src1|$src1, $src2}",
522 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
523 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
524 "ucomiss\t{$src2, $src1|$src1, $src2}",
525 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
527 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
528 "comiss\t{$src2, $src1|$src1, $src2}", []>;
529 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
530 "comiss\t{$src2, $src1|$src1, $src2}", []>;
534 // Aliases to match intrinsics which expect XMM operand(s).
535 let Constraints = "$src1 = $dst" in {
536 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
538 (ins VR128:$src1, VR128:$src, SSECC:$cc),
539 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
540 [(set VR128:$dst, (int_x86_sse_cmp_ss
542 VR128:$src, imm:$cc))]>;
543 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
545 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
546 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
547 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
548 (load addr:$src), imm:$cc))]>;
551 let Defs = [EFLAGS] in {
552 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
553 "ucomiss\t{$src2, $src1|$src1, $src2}",
554 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
556 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
557 "ucomiss\t{$src2, $src1|$src1, $src2}",
558 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
559 (load addr:$src2)))]>;
561 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
562 "comiss\t{$src2, $src1|$src1, $src2}",
563 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
565 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
566 "comiss\t{$src2, $src1|$src1, $src2}",
567 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
568 (load addr:$src2)))]>;
571 // Aliases of packed SSE1 instructions for scalar use. These all have names
572 // that start with 'Fs'.
574 // Alias instructions that map fld0 to pxor for sse.
575 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
577 // FIXME: Set encoding to pseudo!
578 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
579 [(set FR32:$dst, fp32imm0)]>,
580 Requires<[HasSSE1]>, TB, OpSize;
582 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
584 let neverHasSideEffects = 1 in
585 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
586 "movaps\t{$src, $dst|$dst, $src}", []>;
588 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
590 let canFoldAsLoad = 1, isReMaterializable = 1 in
591 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
592 "movaps\t{$src, $dst|$dst, $src}",
593 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
595 // Alias bitwise logical operations using SSE logical ops on packed FP values.
596 let Constraints = "$src1 = $dst" in {
597 let isCommutable = 1 in {
598 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
599 (ins FR32:$src1, FR32:$src2),
600 "andps\t{$src2, $dst|$dst, $src2}",
601 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
602 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
603 (ins FR32:$src1, FR32:$src2),
604 "orps\t{$src2, $dst|$dst, $src2}",
605 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
606 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
607 (ins FR32:$src1, FR32:$src2),
608 "xorps\t{$src2, $dst|$dst, $src2}",
609 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
612 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
613 (ins FR32:$src1, f128mem:$src2),
614 "andps\t{$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86fand FR32:$src1,
616 (memopfsf32 addr:$src2)))]>;
617 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
618 (ins FR32:$src1, f128mem:$src2),
619 "orps\t{$src2, $dst|$dst, $src2}",
620 [(set FR32:$dst, (X86for FR32:$src1,
621 (memopfsf32 addr:$src2)))]>;
622 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
623 (ins FR32:$src1, f128mem:$src2),
624 "xorps\t{$src2, $dst|$dst, $src2}",
625 [(set FR32:$dst, (X86fxor FR32:$src1,
626 (memopfsf32 addr:$src2)))]>;
628 let neverHasSideEffects = 1 in {
629 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
630 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
631 "andnps\t{$src2, $dst|$dst, $src2}", []>;
633 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
634 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
635 "andnps\t{$src2, $dst|$dst, $src2}", []>;
639 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
641 /// In addition, we also have a special variant of the scalar form here to
642 /// represent the associated intrinsic operation. This form is unlike the
643 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
644 /// and leaves the top elements unmodified (therefore these cannot be commuted).
646 /// These three forms can each be reg+reg or reg+mem, so there are a total of
647 /// six "instructions".
649 let Constraints = "$src1 = $dst" in {
650 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
651 SDNode OpNode, Intrinsic F32Int,
652 bit Commutable = 0> {
653 // Scalar operation, reg+reg.
654 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
655 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
656 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
657 let isCommutable = Commutable;
660 // Scalar operation, reg+mem.
661 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
662 (ins FR32:$src1, f32mem:$src2),
663 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
664 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
666 // Vector operation, reg+reg.
667 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
668 (ins VR128:$src1, VR128:$src2),
669 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
670 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
671 let isCommutable = Commutable;
674 // Vector operation, reg+mem.
675 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
676 (ins VR128:$src1, f128mem:$src2),
677 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
678 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
680 // Intrinsic operation, reg+reg.
681 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
682 (ins VR128:$src1, VR128:$src2),
683 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
684 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
686 // Intrinsic operation, reg+mem.
687 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
688 (ins VR128:$src1, ssmem:$src2),
689 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
690 [(set VR128:$dst, (F32Int VR128:$src1,
691 sse_load_f32:$src2))]>;
695 // Arithmetic instructions
696 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
697 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
698 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
699 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
701 /// sse1_fp_binop_rm - Other SSE1 binops
703 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
704 /// instructions for a full-vector intrinsic form. Operations that map
705 /// onto C operators don't use this form since they just use the plain
706 /// vector form instead of having a separate vector intrinsic form.
708 /// This provides a total of eight "instructions".
710 let Constraints = "$src1 = $dst" in {
711 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
715 bit Commutable = 0> {
717 // Scalar operation, reg+reg.
718 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
719 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
720 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
721 let isCommutable = Commutable;
724 // Scalar operation, reg+mem.
725 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
726 (ins FR32:$src1, f32mem:$src2),
727 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
728 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
730 // Vector operation, reg+reg.
731 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
732 (ins VR128:$src1, VR128:$src2),
733 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
734 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
735 let isCommutable = Commutable;
738 // Vector operation, reg+mem.
739 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
740 (ins VR128:$src1, f128mem:$src2),
741 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
742 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
744 // Intrinsic operation, reg+reg.
745 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
746 (ins VR128:$src1, VR128:$src2),
747 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
748 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
749 let isCommutable = Commutable;
752 // Intrinsic operation, reg+mem.
753 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
754 (ins VR128:$src1, ssmem:$src2),
755 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
756 [(set VR128:$dst, (F32Int VR128:$src1,
757 sse_load_f32:$src2))]>;
759 // Vector intrinsic operation, reg+reg.
760 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
761 (ins VR128:$src1, VR128:$src2),
762 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
763 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
764 let isCommutable = Commutable;
767 // Vector intrinsic operation, reg+mem.
768 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
769 (ins VR128:$src1, f128mem:$src2),
770 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
771 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
775 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
776 int_x86_sse_max_ss, int_x86_sse_max_ps>;
777 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
778 int_x86_sse_min_ss, int_x86_sse_min_ps>;
780 //===----------------------------------------------------------------------===//
781 // SSE packed FP Instructions
784 let neverHasSideEffects = 1 in
785 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
786 "movaps\t{$src, $dst|$dst, $src}", []>;
787 let canFoldAsLoad = 1, isReMaterializable = 1 in
788 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
789 "movaps\t{$src, $dst|$dst, $src}",
790 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
792 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
793 "movaps\t{$src, $dst|$dst, $src}",
794 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
796 let neverHasSideEffects = 1 in
797 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
798 "movups\t{$src, $dst|$dst, $src}", []>;
799 let canFoldAsLoad = 1, isReMaterializable = 1 in
800 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
801 "movups\t{$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
803 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
804 "movups\t{$src, $dst|$dst, $src}",
805 [(store (v4f32 VR128:$src), addr:$dst)]>;
807 // Intrinsic forms of MOVUPS load and store
808 let canFoldAsLoad = 1, isReMaterializable = 1 in
809 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
810 "movups\t{$src, $dst|$dst, $src}",
811 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
812 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
813 "movups\t{$src, $dst|$dst, $src}",
814 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
816 let Constraints = "$src1 = $dst" in {
817 let AddedComplexity = 20 in {
818 def MOVLPSrm : PSI<0x12, MRMSrcMem,
819 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
820 "movlps\t{$src2, $dst|$dst, $src2}",
823 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
824 def MOVHPSrm : PSI<0x16, MRMSrcMem,
825 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
826 "movhps\t{$src2, $dst|$dst, $src2}",
828 (movlhps VR128:$src1,
829 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
831 } // Constraints = "$src1 = $dst"
834 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
835 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
837 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
838 "movlps\t{$src, $dst|$dst, $src}",
839 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
840 (iPTR 0))), addr:$dst)]>;
842 // v2f64 extract element 1 is always custom lowered to unpack high to low
843 // and extract element 0 so the non-store version isn't too horrible.
844 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
845 "movhps\t{$src, $dst|$dst, $src}",
846 [(store (f64 (vector_extract
847 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
848 (undef)), (iPTR 0))), addr:$dst)]>;
850 let Constraints = "$src1 = $dst" in {
851 let AddedComplexity = 20 in {
852 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
853 (ins VR128:$src1, VR128:$src2),
854 "movlhps\t{$src2, $dst|$dst, $src2}",
856 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
858 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
859 (ins VR128:$src1, VR128:$src2),
860 "movhlps\t{$src2, $dst|$dst, $src2}",
862 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
864 } // Constraints = "$src1 = $dst"
866 let AddedComplexity = 20 in {
867 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
868 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
869 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
870 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
877 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
879 /// In addition, we also have a special variant of the scalar form here to
880 /// represent the associated intrinsic operation. This form is unlike the
881 /// plain scalar form, in that it takes an entire vector (instead of a
882 /// scalar) and leaves the top elements undefined.
884 /// And, we have a special variant form for a full-vector intrinsic form.
886 /// These four forms can each have a reg or a mem operand, so there are a
887 /// total of eight "instructions".
889 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
893 bit Commutable = 0> {
894 // Scalar operation, reg.
895 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
896 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
897 [(set FR32:$dst, (OpNode FR32:$src))]> {
898 let isCommutable = Commutable;
901 // Scalar operation, mem.
902 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
903 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
904 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
905 Requires<[HasSSE1, OptForSize]>;
907 // Vector operation, reg.
908 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
909 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
910 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
911 let isCommutable = Commutable;
914 // Vector operation, mem.
915 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
916 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
917 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
919 // Intrinsic operation, reg.
920 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
921 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
922 [(set VR128:$dst, (F32Int VR128:$src))]> {
923 let isCommutable = Commutable;
926 // Intrinsic operation, mem.
927 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
928 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
929 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
931 // Vector intrinsic operation, reg
932 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
933 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
934 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
935 let isCommutable = Commutable;
938 // Vector intrinsic operation, mem
939 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
940 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
941 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
945 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
946 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
948 // Reciprocal approximations. Note that these typically require refinement
949 // in order to obtain suitable precision.
950 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
951 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
952 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
953 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
956 let Constraints = "$src1 = $dst" in {
957 let isCommutable = 1 in {
958 def ANDPSrr : PSI<0x54, MRMSrcReg,
959 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
960 "andps\t{$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v2i64
962 (and VR128:$src1, VR128:$src2)))]>;
963 def ORPSrr : PSI<0x56, MRMSrcReg,
964 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
965 "orps\t{$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (v2i64
967 (or VR128:$src1, VR128:$src2)))]>;
968 def XORPSrr : PSI<0x57, MRMSrcReg,
969 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
970 "xorps\t{$src2, $dst|$dst, $src2}",
971 [(set VR128:$dst, (v2i64
972 (xor VR128:$src1, VR128:$src2)))]>;
975 def ANDPSrm : PSI<0x54, MRMSrcMem,
976 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
977 "andps\t{$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
979 (memopv2i64 addr:$src2)))]>;
980 def ORPSrm : PSI<0x56, MRMSrcMem,
981 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
982 "orps\t{$src2, $dst|$dst, $src2}",
983 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
984 (memopv2i64 addr:$src2)))]>;
985 def XORPSrm : PSI<0x57, MRMSrcMem,
986 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
987 "xorps\t{$src2, $dst|$dst, $src2}",
988 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
989 (memopv2i64 addr:$src2)))]>;
990 def ANDNPSrr : PSI<0x55, MRMSrcReg,
991 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
992 "andnps\t{$src2, $dst|$dst, $src2}",
994 (v2i64 (and (xor VR128:$src1,
995 (bc_v2i64 (v4i32 immAllOnesV))),
997 def ANDNPSrm : PSI<0x55, MRMSrcMem,
998 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
999 "andnps\t{$src2, $dst|$dst, $src2}",
1001 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1002 (bc_v2i64 (v4i32 immAllOnesV))),
1003 (memopv2i64 addr:$src2))))]>;
1006 let Constraints = "$src1 = $dst" in {
1007 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1008 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1009 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1011 VR128:$src, imm:$cc))]>;
1012 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1013 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1014 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1015 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1016 (memop addr:$src), imm:$cc))]>;
1018 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1019 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1020 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1021 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1023 // Shuffle and unpack instructions
1024 let Constraints = "$src1 = $dst" in {
1025 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1026 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1027 (outs VR128:$dst), (ins VR128:$src1,
1028 VR128:$src2, i8imm:$src3),
1029 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1031 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1032 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1033 (outs VR128:$dst), (ins VR128:$src1,
1034 f128mem:$src2, i8imm:$src3),
1035 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1038 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1040 let AddedComplexity = 10 in {
1041 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1042 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1043 "unpckhps\t{$src2, $dst|$dst, $src2}",
1045 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1046 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1047 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1048 "unpckhps\t{$src2, $dst|$dst, $src2}",
1050 (v4f32 (unpckh VR128:$src1,
1051 (memopv4f32 addr:$src2))))]>;
1053 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1054 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1055 "unpcklps\t{$src2, $dst|$dst, $src2}",
1057 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1058 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1059 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1060 "unpcklps\t{$src2, $dst|$dst, $src2}",
1062 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1063 } // AddedComplexity
1064 } // Constraints = "$src1 = $dst"
1067 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1068 "movmskps\t{$src, $dst|$dst, $src}",
1069 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1070 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1071 "movmskpd\t{$src, $dst|$dst, $src}",
1072 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1074 // Prefetch intrinsic.
1075 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1076 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1077 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1078 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1079 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1080 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1081 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1082 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1084 // Non-temporal stores
1085 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1086 "movntps\t{$src, $dst|$dst, $src}",
1087 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1089 let AddedComplexity = 400 in { // Prefer non-temporal versions
1090 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1091 "movntps\t{$src, $dst|$dst, $src}",
1092 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1094 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1095 "movntdq\t{$src, $dst|$dst, $src}",
1096 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1098 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1099 "movnti\t{$src, $dst|$dst, $src}",
1100 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1101 TB, Requires<[HasSSE2]>;
1103 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1104 "movnti\t{$src, $dst|$dst, $src}",
1105 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1106 TB, Requires<[HasSSE2]>;
1109 // Load, store, and memory fence
1110 def SFENCE : PSI<0xAE, MRM7r, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
1113 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1114 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1115 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1116 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1118 // Alias instructions that map zero vector to pxor / xorp* for sse.
1119 // We set canFoldAsLoad because this can be converted to a constant-pool
1120 // load of an all-zeros value if folding it would be beneficial.
1121 // FIXME: Change encoding to pseudo!
1122 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1123 isCodeGenOnly = 1 in
1124 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1125 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1127 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1128 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1129 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1130 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1131 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1133 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1134 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
1136 //===---------------------------------------------------------------------===//
1137 // SSE2 Instructions
1138 //===---------------------------------------------------------------------===//
1140 // Move Instructions. Register-to-register movsd is not used for FR64
1141 // register copies because it's a partial register update; FsMOVAPDrr is
1142 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1143 // because INSERT_SUBREG requires that the insert be implementable in terms of
1144 // a copy, and just mentioned, we don't use movsd for copies.
1145 let Constraints = "$src1 = $dst" in
1146 def MOVSDrr : SDI<0x10, MRMSrcReg,
1147 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1148 "movsd\t{$src2, $dst|$dst, $src2}",
1149 [(set (v2f64 VR128:$dst),
1150 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1152 // Extract the low 64-bit value from one vector and insert it into another.
1153 let AddedComplexity = 15 in
1154 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1155 (MOVSDrr (v2f64 VR128:$src1),
1156 (EXTRACT_SUBREG (v2f64 VR128:$src2), x86_subreg_sd))>;
1158 // Implicitly promote a 64-bit scalar to a vector.
1159 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1160 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, x86_subreg_sd)>;
1162 // Loading from memory automatically zeroing upper bits.
1163 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1164 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1165 "movsd\t{$src, $dst|$dst, $src}",
1166 [(set FR64:$dst, (loadf64 addr:$src))]>;
1168 // MOVSDrm zeros the high parts of the register; represent this
1169 // with SUBREG_TO_REG.
1170 let AddedComplexity = 20 in {
1171 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1172 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1173 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1174 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1175 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1176 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1177 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1178 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1179 def : Pat<(v2f64 (X86vzload addr:$src)),
1180 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1183 // Store scalar value to memory.
1184 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1185 "movsd\t{$src, $dst|$dst, $src}",
1186 [(store FR64:$src, addr:$dst)]>;
1188 // Extract and store.
1189 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1192 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
1194 // Conversion instructions
1195 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1196 "cvttsd2si\t{$src, $dst|$dst, $src}",
1197 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1198 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1199 "cvttsd2si\t{$src, $dst|$dst, $src}",
1200 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1201 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1202 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1203 [(set FR32:$dst, (fround FR64:$src))]>;
1204 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1205 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1206 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1207 Requires<[HasSSE2, OptForSize]>;
1208 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1209 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1210 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1211 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1212 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1213 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1215 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1216 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1217 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1218 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1219 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1220 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1221 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1222 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1223 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1224 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1225 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1226 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1227 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1228 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1229 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1230 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1231 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1232 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1233 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1234 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1236 // SSE2 instructions with XS prefix
1237 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1238 "cvtss2sd\t{$src, $dst|$dst, $src}",
1239 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1240 Requires<[HasSSE2]>;
1241 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1242 "cvtss2sd\t{$src, $dst|$dst, $src}",
1243 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1244 Requires<[HasSSE2, OptForSize]>;
1246 def : Pat<(extloadf32 addr:$src),
1247 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1248 Requires<[HasSSE2, OptForSpeed]>;
1250 // Match intrinsics which expect XMM operand(s).
1251 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1252 "cvtsd2si\t{$src, $dst|$dst, $src}",
1253 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1254 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1255 "cvtsd2si\t{$src, $dst|$dst, $src}",
1256 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1257 (load addr:$src)))]>;
1259 // Match intrinisics which expect MM and XMM operand(s).
1260 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1261 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1262 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1263 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1264 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1265 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1266 (memop addr:$src)))]>;
1267 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1268 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1269 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1270 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1271 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1272 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1273 (memop addr:$src)))]>;
1274 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1275 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1276 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1277 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1278 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1279 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1280 (load addr:$src)))]>;
1282 // Aliases for intrinsics
1283 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1284 "cvttsd2si\t{$src, $dst|$dst, $src}",
1286 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1287 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1288 "cvttsd2si\t{$src, $dst|$dst, $src}",
1289 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1290 (load addr:$src)))]>;
1292 // Comparison instructions
1293 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1294 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1295 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1296 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1298 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1299 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1300 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1303 let Defs = [EFLAGS] in {
1304 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1305 "ucomisd\t{$src2, $src1|$src1, $src2}",
1306 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1307 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1308 "ucomisd\t{$src2, $src1|$src1, $src2}",
1309 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1310 } // Defs = [EFLAGS]
1312 // Aliases to match intrinsics which expect XMM operand(s).
1313 let Constraints = "$src1 = $dst" in {
1314 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1316 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1317 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1318 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1319 VR128:$src, imm:$cc))]>;
1320 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1322 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1323 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1324 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1325 (load addr:$src), imm:$cc))]>;
1328 let Defs = [EFLAGS] in {
1329 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1330 "ucomisd\t{$src2, $src1|$src1, $src2}",
1331 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1333 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1334 "ucomisd\t{$src2, $src1|$src1, $src2}",
1335 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1336 (load addr:$src2)))]>;
1338 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1339 "comisd\t{$src2, $src1|$src1, $src2}",
1340 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1342 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1343 "comisd\t{$src2, $src1|$src1, $src2}",
1344 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1345 (load addr:$src2)))]>;
1346 } // Defs = [EFLAGS]
1348 // Aliases of packed SSE2 instructions for scalar use. These all have names
1349 // that start with 'Fs'.
1351 // Alias instructions that map fld0 to pxor for sse.
1352 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1353 canFoldAsLoad = 1 in
1354 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1355 [(set FR64:$dst, fpimm0)]>,
1356 Requires<[HasSSE2]>, TB, OpSize;
1358 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1360 let neverHasSideEffects = 1 in
1361 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1362 "movapd\t{$src, $dst|$dst, $src}", []>;
1364 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1366 let canFoldAsLoad = 1, isReMaterializable = 1 in
1367 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1368 "movapd\t{$src, $dst|$dst, $src}",
1369 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1371 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1372 let Constraints = "$src1 = $dst" in {
1373 let isCommutable = 1 in {
1374 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1375 (ins FR64:$src1, FR64:$src2),
1376 "andpd\t{$src2, $dst|$dst, $src2}",
1377 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1378 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1379 (ins FR64:$src1, FR64:$src2),
1380 "orpd\t{$src2, $dst|$dst, $src2}",
1381 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1382 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1383 (ins FR64:$src1, FR64:$src2),
1384 "xorpd\t{$src2, $dst|$dst, $src2}",
1385 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1388 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1389 (ins FR64:$src1, f128mem:$src2),
1390 "andpd\t{$src2, $dst|$dst, $src2}",
1391 [(set FR64:$dst, (X86fand FR64:$src1,
1392 (memopfsf64 addr:$src2)))]>;
1393 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1394 (ins FR64:$src1, f128mem:$src2),
1395 "orpd\t{$src2, $dst|$dst, $src2}",
1396 [(set FR64:$dst, (X86for FR64:$src1,
1397 (memopfsf64 addr:$src2)))]>;
1398 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1399 (ins FR64:$src1, f128mem:$src2),
1400 "xorpd\t{$src2, $dst|$dst, $src2}",
1401 [(set FR64:$dst, (X86fxor FR64:$src1,
1402 (memopfsf64 addr:$src2)))]>;
1404 let neverHasSideEffects = 1 in {
1405 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1406 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1407 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1409 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1410 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1411 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1415 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1417 /// In addition, we also have a special variant of the scalar form here to
1418 /// represent the associated intrinsic operation. This form is unlike the
1419 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1420 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1422 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1423 /// six "instructions".
1425 let Constraints = "$src1 = $dst" in {
1426 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1427 SDNode OpNode, Intrinsic F64Int,
1428 bit Commutable = 0> {
1429 // Scalar operation, reg+reg.
1430 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1431 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1432 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1433 let isCommutable = Commutable;
1436 // Scalar operation, reg+mem.
1437 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1438 (ins FR64:$src1, f64mem:$src2),
1439 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1440 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1442 // Vector operation, reg+reg.
1443 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1444 (ins VR128:$src1, VR128:$src2),
1445 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1446 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1447 let isCommutable = Commutable;
1450 // Vector operation, reg+mem.
1451 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1452 (ins VR128:$src1, f128mem:$src2),
1453 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1454 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1456 // Intrinsic operation, reg+reg.
1457 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1458 (ins VR128:$src1, VR128:$src2),
1459 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1460 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1462 // Intrinsic operation, reg+mem.
1463 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1464 (ins VR128:$src1, sdmem:$src2),
1465 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1466 [(set VR128:$dst, (F64Int VR128:$src1,
1467 sse_load_f64:$src2))]>;
1471 // Arithmetic instructions
1472 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1473 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1474 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1475 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1477 /// sse2_fp_binop_rm - Other SSE2 binops
1479 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1480 /// instructions for a full-vector intrinsic form. Operations that map
1481 /// onto C operators don't use this form since they just use the plain
1482 /// vector form instead of having a separate vector intrinsic form.
1484 /// This provides a total of eight "instructions".
1486 let Constraints = "$src1 = $dst" in {
1487 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1491 bit Commutable = 0> {
1493 // Scalar operation, reg+reg.
1494 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1495 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1496 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1497 let isCommutable = Commutable;
1500 // Scalar operation, reg+mem.
1501 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1502 (ins FR64:$src1, f64mem:$src2),
1503 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1504 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1506 // Vector operation, reg+reg.
1507 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1508 (ins VR128:$src1, VR128:$src2),
1509 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1510 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1511 let isCommutable = Commutable;
1514 // Vector operation, reg+mem.
1515 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1516 (ins VR128:$src1, f128mem:$src2),
1517 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1518 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1520 // Intrinsic operation, reg+reg.
1521 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1522 (ins VR128:$src1, VR128:$src2),
1523 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1524 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1525 let isCommutable = Commutable;
1528 // Intrinsic operation, reg+mem.
1529 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1530 (ins VR128:$src1, sdmem:$src2),
1531 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1532 [(set VR128:$dst, (F64Int VR128:$src1,
1533 sse_load_f64:$src2))]>;
1535 // Vector intrinsic operation, reg+reg.
1536 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1537 (ins VR128:$src1, VR128:$src2),
1538 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1539 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1540 let isCommutable = Commutable;
1543 // Vector intrinsic operation, reg+mem.
1544 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1545 (ins VR128:$src1, f128mem:$src2),
1546 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1547 [(set VR128:$dst, (V2F64Int VR128:$src1,
1548 (memopv2f64 addr:$src2)))]>;
1552 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1553 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1554 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1555 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1557 //===---------------------------------------------------------------------===//
1558 // SSE packed FP Instructions
1560 // Move Instructions
1561 let neverHasSideEffects = 1 in
1562 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1563 "movapd\t{$src, $dst|$dst, $src}", []>;
1564 let canFoldAsLoad = 1, isReMaterializable = 1 in
1565 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1566 "movapd\t{$src, $dst|$dst, $src}",
1567 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1569 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1570 "movapd\t{$src, $dst|$dst, $src}",
1571 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1573 let neverHasSideEffects = 1 in
1574 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1575 "movupd\t{$src, $dst|$dst, $src}", []>;
1576 let canFoldAsLoad = 1 in
1577 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1578 "movupd\t{$src, $dst|$dst, $src}",
1579 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1580 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1581 "movupd\t{$src, $dst|$dst, $src}",
1582 [(store (v2f64 VR128:$src), addr:$dst)]>;
1584 // Intrinsic forms of MOVUPD load and store
1585 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1586 "movupd\t{$src, $dst|$dst, $src}",
1587 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1588 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1589 "movupd\t{$src, $dst|$dst, $src}",
1590 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1592 let Constraints = "$src1 = $dst" in {
1593 let AddedComplexity = 20 in {
1594 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1595 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1596 "movlpd\t{$src2, $dst|$dst, $src2}",
1598 (v2f64 (movlp VR128:$src1,
1599 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1600 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1601 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1602 "movhpd\t{$src2, $dst|$dst, $src2}",
1604 (v2f64 (movlhps VR128:$src1,
1605 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1606 } // AddedComplexity
1607 } // Constraints = "$src1 = $dst"
1609 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1610 "movlpd\t{$src, $dst|$dst, $src}",
1611 [(store (f64 (vector_extract (v2f64 VR128:$src),
1612 (iPTR 0))), addr:$dst)]>;
1614 // v2f64 extract element 1 is always custom lowered to unpack high to low
1615 // and extract element 0 so the non-store version isn't too horrible.
1616 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1617 "movhpd\t{$src, $dst|$dst, $src}",
1618 [(store (f64 (vector_extract
1619 (v2f64 (unpckh VR128:$src, (undef))),
1620 (iPTR 0))), addr:$dst)]>;
1622 // SSE2 instructions without OpSize prefix
1623 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1624 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1625 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1626 TB, Requires<[HasSSE2]>;
1627 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1628 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1629 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1630 (bitconvert (memopv2i64 addr:$src))))]>,
1631 TB, Requires<[HasSSE2]>;
1633 // SSE2 instructions with XS prefix
1634 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1635 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1636 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1637 XS, Requires<[HasSSE2]>;
1638 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1639 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1640 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1641 (bitconvert (memopv2i64 addr:$src))))]>,
1642 XS, Requires<[HasSSE2]>;
1644 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1645 "cvtps2dq\t{$src, $dst|$dst, $src}",
1646 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1647 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1648 "cvtps2dq\t{$src, $dst|$dst, $src}",
1649 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1650 (memop addr:$src)))]>;
1651 // SSE2 packed instructions with XS prefix
1652 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1653 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1654 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1655 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1657 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1658 "cvttps2dq\t{$src, $dst|$dst, $src}",
1660 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1661 XS, Requires<[HasSSE2]>;
1662 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1663 "cvttps2dq\t{$src, $dst|$dst, $src}",
1664 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1665 (memop addr:$src)))]>,
1666 XS, Requires<[HasSSE2]>;
1668 // SSE2 packed instructions with XD prefix
1669 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1670 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1672 XD, Requires<[HasSSE2]>;
1673 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1674 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1675 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1676 (memop addr:$src)))]>,
1677 XD, Requires<[HasSSE2]>;
1679 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1680 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1681 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1682 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1683 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1684 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1685 (memop addr:$src)))]>;
1687 // SSE2 instructions without OpSize prefix
1688 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1689 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1690 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1691 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1693 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1694 "cvtps2pd\t{$src, $dst|$dst, $src}",
1695 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1696 TB, Requires<[HasSSE2]>;
1697 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1698 "cvtps2pd\t{$src, $dst|$dst, $src}",
1699 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1700 (load addr:$src)))]>,
1701 TB, Requires<[HasSSE2]>;
1703 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1705 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1706 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1709 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1710 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1711 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1712 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1713 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1714 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1715 (memop addr:$src)))]>;
1717 // Match intrinsics which expect XMM operand(s).
1718 // Aliases for intrinsics
1719 let Constraints = "$src1 = $dst" in {
1720 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1721 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1722 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1725 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1726 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1727 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1728 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1729 (loadi32 addr:$src2)))]>;
1730 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1731 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1732 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1733 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1735 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1736 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1737 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1738 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1739 (load addr:$src2)))]>;
1740 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1741 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1742 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1743 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1744 VR128:$src2))]>, XS,
1745 Requires<[HasSSE2]>;
1746 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1747 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1748 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1750 (load addr:$src2)))]>, XS,
1751 Requires<[HasSSE2]>;
1756 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1758 /// In addition, we also have a special variant of the scalar form here to
1759 /// represent the associated intrinsic operation. This form is unlike the
1760 /// plain scalar form, in that it takes an entire vector (instead of a
1761 /// scalar) and leaves the top elements undefined.
1763 /// And, we have a special variant form for a full-vector intrinsic form.
1765 /// These four forms can each have a reg or a mem operand, so there are a
1766 /// total of eight "instructions".
1768 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1772 bit Commutable = 0> {
1773 // Scalar operation, reg.
1774 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1775 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1776 [(set FR64:$dst, (OpNode FR64:$src))]> {
1777 let isCommutable = Commutable;
1780 // Scalar operation, mem.
1781 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1782 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1783 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1785 // Vector operation, reg.
1786 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1787 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1788 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1789 let isCommutable = Commutable;
1792 // Vector operation, mem.
1793 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1794 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1795 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1797 // Intrinsic operation, reg.
1798 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1799 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1800 [(set VR128:$dst, (F64Int VR128:$src))]> {
1801 let isCommutable = Commutable;
1804 // Intrinsic operation, mem.
1805 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1806 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1807 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1809 // Vector intrinsic operation, reg
1810 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1811 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1812 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1813 let isCommutable = Commutable;
1816 // Vector intrinsic operation, mem
1817 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1818 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1819 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1823 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1824 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1826 // There is no f64 version of the reciprocal approximation instructions.
1829 let Constraints = "$src1 = $dst" in {
1830 let isCommutable = 1 in {
1831 def ANDPDrr : PDI<0x54, MRMSrcReg,
1832 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1833 "andpd\t{$src2, $dst|$dst, $src2}",
1835 (and (bc_v2i64 (v2f64 VR128:$src1)),
1836 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1837 def ORPDrr : PDI<0x56, MRMSrcReg,
1838 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1839 "orpd\t{$src2, $dst|$dst, $src2}",
1841 (or (bc_v2i64 (v2f64 VR128:$src1)),
1842 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1843 def XORPDrr : PDI<0x57, MRMSrcReg,
1844 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1845 "xorpd\t{$src2, $dst|$dst, $src2}",
1847 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1848 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1851 def ANDPDrm : PDI<0x54, MRMSrcMem,
1852 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1853 "andpd\t{$src2, $dst|$dst, $src2}",
1855 (and (bc_v2i64 (v2f64 VR128:$src1)),
1856 (memopv2i64 addr:$src2)))]>;
1857 def ORPDrm : PDI<0x56, MRMSrcMem,
1858 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1859 "orpd\t{$src2, $dst|$dst, $src2}",
1861 (or (bc_v2i64 (v2f64 VR128:$src1)),
1862 (memopv2i64 addr:$src2)))]>;
1863 def XORPDrm : PDI<0x57, MRMSrcMem,
1864 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1865 "xorpd\t{$src2, $dst|$dst, $src2}",
1867 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1868 (memopv2i64 addr:$src2)))]>;
1869 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1870 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1871 "andnpd\t{$src2, $dst|$dst, $src2}",
1873 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1874 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1875 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1876 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1877 "andnpd\t{$src2, $dst|$dst, $src2}",
1879 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1880 (memopv2i64 addr:$src2)))]>;
1883 let Constraints = "$src1 = $dst" in {
1884 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1885 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1886 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1887 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1888 VR128:$src, imm:$cc))]>;
1889 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1890 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1891 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1892 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1893 (memop addr:$src), imm:$cc))]>;
1895 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1896 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1897 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1898 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1900 // Shuffle and unpack instructions
1901 let Constraints = "$src1 = $dst" in {
1902 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1903 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1904 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1906 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1907 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1908 (outs VR128:$dst), (ins VR128:$src1,
1909 f128mem:$src2, i8imm:$src3),
1910 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1913 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1915 let AddedComplexity = 10 in {
1916 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1917 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1918 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1920 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1921 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1922 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1923 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1925 (v2f64 (unpckh VR128:$src1,
1926 (memopv2f64 addr:$src2))))]>;
1928 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1929 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1930 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1932 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1933 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1934 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1935 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1937 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1938 } // AddedComplexity
1939 } // Constraints = "$src1 = $dst"
1942 //===---------------------------------------------------------------------===//
1943 // SSE integer instructions
1945 // Move Instructions
1946 let neverHasSideEffects = 1 in
1947 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1948 "movdqa\t{$src, $dst|$dst, $src}", []>;
1949 let canFoldAsLoad = 1, mayLoad = 1 in
1950 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1951 "movdqa\t{$src, $dst|$dst, $src}",
1952 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1954 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1955 "movdqa\t{$src, $dst|$dst, $src}",
1956 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1957 let canFoldAsLoad = 1, mayLoad = 1 in
1958 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1959 "movdqu\t{$src, $dst|$dst, $src}",
1960 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1961 XS, Requires<[HasSSE2]>;
1963 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1964 "movdqu\t{$src, $dst|$dst, $src}",
1965 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1966 XS, Requires<[HasSSE2]>;
1968 // Intrinsic forms of MOVDQU load and store
1969 let canFoldAsLoad = 1 in
1970 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1971 "movdqu\t{$src, $dst|$dst, $src}",
1972 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1973 XS, Requires<[HasSSE2]>;
1974 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1975 "movdqu\t{$src, $dst|$dst, $src}",
1976 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1977 XS, Requires<[HasSSE2]>;
1979 let Constraints = "$src1 = $dst" in {
1981 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1982 bit Commutable = 0> {
1983 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1984 (ins VR128:$src1, VR128:$src2),
1985 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1986 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1987 let isCommutable = Commutable;
1989 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1990 (ins VR128:$src1, i128mem:$src2),
1991 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1992 [(set VR128:$dst, (IntId VR128:$src1,
1993 (bitconvert (memopv2i64
1997 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1999 Intrinsic IntId, Intrinsic IntId2> {
2000 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2001 (ins VR128:$src1, VR128:$src2),
2002 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2003 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2004 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2005 (ins VR128:$src1, i128mem:$src2),
2006 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2007 [(set VR128:$dst, (IntId VR128:$src1,
2008 (bitconvert (memopv2i64 addr:$src2))))]>;
2009 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2010 (ins VR128:$src1, i32i8imm:$src2),
2011 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2012 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2015 /// PDI_binop_rm - Simple SSE2 binary operator.
2016 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2017 ValueType OpVT, bit Commutable = 0> {
2018 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2019 (ins VR128:$src1, VR128:$src2),
2020 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2021 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2022 let isCommutable = Commutable;
2024 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2025 (ins VR128:$src1, i128mem:$src2),
2026 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2027 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2028 (bitconvert (memopv2i64 addr:$src2)))))]>;
2031 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2033 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2034 /// to collapse (bitconvert VT to VT) into its operand.
2036 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2037 bit Commutable = 0> {
2038 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2039 (ins VR128:$src1, VR128:$src2),
2040 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2041 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2042 let isCommutable = Commutable;
2044 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2045 (ins VR128:$src1, i128mem:$src2),
2046 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2047 [(set VR128:$dst, (OpNode VR128:$src1,
2048 (memopv2i64 addr:$src2)))]>;
2051 } // Constraints = "$src1 = $dst"
2053 // 128-bit Integer Arithmetic
2055 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2056 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2057 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2058 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2060 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2061 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2062 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2063 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2065 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2066 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2067 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2068 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2070 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2071 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2072 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2073 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2075 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2077 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2078 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2079 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2081 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2083 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2084 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2087 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2088 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2089 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2090 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2091 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2094 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2095 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2096 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2097 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2098 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2099 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2101 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2102 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2103 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2104 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2105 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2106 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2108 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2109 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2110 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2111 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2113 // 128-bit logical shifts.
2114 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
2115 def PSLLDQri : PDIi8<0x73, MRM7r,
2116 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2117 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2118 def PSRLDQri : PDIi8<0x73, MRM3r,
2119 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2120 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2121 // PSRADQri doesn't exist in SSE[1-3].
2124 let Predicates = [HasSSE2] in {
2125 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2126 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2127 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2128 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2129 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2130 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2131 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2132 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2133 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2134 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2136 // Shift up / down and insert zero's.
2137 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2138 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2139 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2140 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2144 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2145 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2146 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2148 let Constraints = "$src1 = $dst" in {
2149 def PANDNrr : PDI<0xDF, MRMSrcReg,
2150 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2151 "pandn\t{$src2, $dst|$dst, $src2}",
2152 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2155 def PANDNrm : PDI<0xDF, MRMSrcMem,
2156 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2157 "pandn\t{$src2, $dst|$dst, $src2}",
2158 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2159 (memopv2i64 addr:$src2))))]>;
2162 // SSE2 Integer comparison
2163 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2164 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2165 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2166 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2167 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2168 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2170 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2171 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2172 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2173 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2174 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2175 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2176 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2177 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2178 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2179 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2180 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2181 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2183 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2184 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2185 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2186 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2187 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2188 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2189 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2190 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2191 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2192 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2193 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2194 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2197 // Pack instructions
2198 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2199 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2200 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2202 // Shuffle and unpack instructions
2203 let AddedComplexity = 5 in {
2204 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2205 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2206 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2207 [(set VR128:$dst, (v4i32 (pshufd:$src2
2208 VR128:$src1, (undef))))]>;
2209 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2210 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2211 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2212 [(set VR128:$dst, (v4i32 (pshufd:$src2
2213 (bc_v4i32 (memopv2i64 addr:$src1)),
2217 // SSE2 with ImmT == Imm8 and XS prefix.
2218 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2219 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2220 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2221 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2223 XS, Requires<[HasSSE2]>;
2224 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2225 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2226 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2227 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2228 (bc_v8i16 (memopv2i64 addr:$src1)),
2230 XS, Requires<[HasSSE2]>;
2232 // SSE2 with ImmT == Imm8 and XD prefix.
2233 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2234 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2235 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2236 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2238 XD, Requires<[HasSSE2]>;
2239 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2240 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2241 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2242 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2243 (bc_v8i16 (memopv2i64 addr:$src1)),
2245 XD, Requires<[HasSSE2]>;
2248 let Constraints = "$src1 = $dst" in {
2249 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2250 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2251 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2253 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2254 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2255 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2256 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2258 (unpckl VR128:$src1,
2259 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2260 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2261 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2262 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2264 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2265 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2266 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2267 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2269 (unpckl VR128:$src1,
2270 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2271 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2272 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2273 "punpckldq\t{$src2, $dst|$dst, $src2}",
2275 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2276 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2277 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2278 "punpckldq\t{$src2, $dst|$dst, $src2}",
2280 (unpckl VR128:$src1,
2281 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2282 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2283 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2284 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2286 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2287 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2288 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2289 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2291 (v2i64 (unpckl VR128:$src1,
2292 (memopv2i64 addr:$src2))))]>;
2294 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2295 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2296 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2298 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2299 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2300 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2301 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2303 (unpckh VR128:$src1,
2304 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2305 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2306 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2307 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2309 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2310 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2311 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2312 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2314 (unpckh VR128:$src1,
2315 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2316 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2317 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2318 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2320 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2321 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2322 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2323 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2325 (unpckh VR128:$src1,
2326 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2327 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2328 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2329 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2331 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2332 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2333 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2334 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2336 (v2i64 (unpckh VR128:$src1,
2337 (memopv2i64 addr:$src2))))]>;
2341 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2342 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2343 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2344 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2346 let Constraints = "$src1 = $dst" in {
2347 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2348 (outs VR128:$dst), (ins VR128:$src1,
2349 GR32:$src2, i32i8imm:$src3),
2350 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2352 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2353 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2354 (outs VR128:$dst), (ins VR128:$src1,
2355 i16mem:$src2, i32i8imm:$src3),
2356 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2358 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2363 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2364 "pmovmskb\t{$src, $dst|$dst, $src}",
2365 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2367 // Conditional store
2369 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2370 "maskmovdqu\t{$mask, $src|$src, $mask}",
2371 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2374 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2375 "maskmovdqu\t{$mask, $src|$src, $mask}",
2376 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2378 // Non-temporal stores
2379 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2380 "movntpd\t{$src, $dst|$dst, $src}",
2381 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2382 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2383 "movntdq\t{$src, $dst|$dst, $src}",
2384 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2385 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2386 "movnti\t{$src, $dst|$dst, $src}",
2387 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2388 TB, Requires<[HasSSE2]>;
2390 let AddedComplexity = 400 in { // Prefer non-temporal versions
2391 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2392 "movntpd\t{$src, $dst|$dst, $src}",
2393 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2395 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2396 "movntdq\t{$src, $dst|$dst, $src}",
2397 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2401 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2402 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2403 TB, Requires<[HasSSE2]>;
2405 // Load, store, and memory fence
2406 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2407 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2408 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2409 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2411 //TODO: custom lower this so as to never even generate the noop
2412 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2414 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2415 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2416 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2419 // Alias instructions that map zero vector to pxor / xorp* for sse.
2420 // We set canFoldAsLoad because this can be converted to a constant-pool
2421 // load of an all-ones value if folding it would be beneficial.
2422 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2423 isCodeGenOnly = 1 in
2424 // FIXME: Change encoding to pseudo.
2425 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2426 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2428 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2429 "movd\t{$src, $dst|$dst, $src}",
2431 (v4i32 (scalar_to_vector GR32:$src)))]>;
2432 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2433 "movd\t{$src, $dst|$dst, $src}",
2435 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2437 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2438 "movd\t{$src, $dst|$dst, $src}",
2439 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2441 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2442 "movd\t{$src, $dst|$dst, $src}",
2443 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2445 // SSE2 instructions with XS prefix
2446 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2447 "movq\t{$src, $dst|$dst, $src}",
2449 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2450 Requires<[HasSSE2]>;
2451 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2452 "movq\t{$src, $dst|$dst, $src}",
2453 [(store (i64 (vector_extract (v2i64 VR128:$src),
2454 (iPTR 0))), addr:$dst)]>;
2456 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2457 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
2459 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2460 "movd\t{$src, $dst|$dst, $src}",
2461 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2463 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2464 "movd\t{$src, $dst|$dst, $src}",
2465 [(store (i32 (vector_extract (v4i32 VR128:$src),
2466 (iPTR 0))), addr:$dst)]>;
2468 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2469 "movd\t{$src, $dst|$dst, $src}",
2470 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2471 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2472 "movd\t{$src, $dst|$dst, $src}",
2473 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2475 // Store / copy lower 64-bits of a XMM register.
2476 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2477 "movq\t{$src, $dst|$dst, $src}",
2478 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2480 // movd / movq to XMM register zero-extends
2481 let AddedComplexity = 15 in {
2482 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2483 "movd\t{$src, $dst|$dst, $src}",
2484 [(set VR128:$dst, (v4i32 (X86vzmovl
2485 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2486 // This is X86-64 only.
2487 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2488 "mov{d|q}\t{$src, $dst|$dst, $src}",
2489 [(set VR128:$dst, (v2i64 (X86vzmovl
2490 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2493 let AddedComplexity = 20 in {
2494 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2495 "movd\t{$src, $dst|$dst, $src}",
2497 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2498 (loadi32 addr:$src))))))]>;
2500 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2501 (MOVZDI2PDIrm addr:$src)>;
2502 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2503 (MOVZDI2PDIrm addr:$src)>;
2504 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2505 (MOVZDI2PDIrm addr:$src)>;
2507 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2508 "movq\t{$src, $dst|$dst, $src}",
2510 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2511 (loadi64 addr:$src))))))]>, XS,
2512 Requires<[HasSSE2]>;
2514 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2515 (MOVZQI2PQIrm addr:$src)>;
2516 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2517 (MOVZQI2PQIrm addr:$src)>;
2518 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2521 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2522 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2523 let AddedComplexity = 15 in
2524 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2525 "movq\t{$src, $dst|$dst, $src}",
2526 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2527 XS, Requires<[HasSSE2]>;
2529 let AddedComplexity = 20 in {
2530 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2531 "movq\t{$src, $dst|$dst, $src}",
2532 [(set VR128:$dst, (v2i64 (X86vzmovl
2533 (loadv2i64 addr:$src))))]>,
2534 XS, Requires<[HasSSE2]>;
2536 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2537 (MOVZPQILo2PQIrm addr:$src)>;
2540 // Instructions for the disassembler
2541 // xr = XMM register
2544 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2545 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2547 //===---------------------------------------------------------------------===//
2548 // SSE3 Instructions
2549 //===---------------------------------------------------------------------===//
2551 // Move Instructions
2552 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2553 "movshdup\t{$src, $dst|$dst, $src}",
2554 [(set VR128:$dst, (v4f32 (movshdup
2555 VR128:$src, (undef))))]>;
2556 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2557 "movshdup\t{$src, $dst|$dst, $src}",
2558 [(set VR128:$dst, (movshdup
2559 (memopv4f32 addr:$src), (undef)))]>;
2561 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2562 "movsldup\t{$src, $dst|$dst, $src}",
2563 [(set VR128:$dst, (v4f32 (movsldup
2564 VR128:$src, (undef))))]>;
2565 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2566 "movsldup\t{$src, $dst|$dst, $src}",
2567 [(set VR128:$dst, (movsldup
2568 (memopv4f32 addr:$src), (undef)))]>;
2570 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2571 "movddup\t{$src, $dst|$dst, $src}",
2572 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2573 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2574 "movddup\t{$src, $dst|$dst, $src}",
2576 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2579 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2581 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2583 let AddedComplexity = 5 in {
2584 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2585 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2586 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2587 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2588 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2589 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2590 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2591 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2595 let Constraints = "$src1 = $dst" in {
2596 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2597 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2598 "addsubps\t{$src2, $dst|$dst, $src2}",
2599 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2601 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2602 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2603 "addsubps\t{$src2, $dst|$dst, $src2}",
2604 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2605 (memop addr:$src2)))]>;
2606 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2607 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2608 "addsubpd\t{$src2, $dst|$dst, $src2}",
2609 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2611 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2612 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2613 "addsubpd\t{$src2, $dst|$dst, $src2}",
2614 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2615 (memop addr:$src2)))]>;
2618 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2619 "lddqu\t{$src, $dst|$dst, $src}",
2620 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2623 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2624 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2625 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2626 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2627 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2628 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2629 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2630 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2631 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2632 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2634 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2635 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2636 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2637 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2638 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2640 let Constraints = "$src1 = $dst" in {
2641 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2642 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2643 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2644 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2645 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2646 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2647 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2648 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2651 // Thread synchronization
2652 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2653 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2654 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2655 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2657 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2658 let AddedComplexity = 15 in
2659 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2660 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2661 let AddedComplexity = 20 in
2662 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2663 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2665 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2666 let AddedComplexity = 15 in
2667 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2668 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2669 let AddedComplexity = 20 in
2670 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2671 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2673 //===---------------------------------------------------------------------===//
2674 // SSSE3 Instructions
2675 //===---------------------------------------------------------------------===//
2677 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2678 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2679 Intrinsic IntId64, Intrinsic IntId128> {
2680 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2681 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2682 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2684 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2685 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2687 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2689 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2691 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2692 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2695 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2697 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2700 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2703 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2704 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2705 Intrinsic IntId64, Intrinsic IntId128> {
2706 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2708 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2709 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2711 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2713 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2716 (bitconvert (memopv4i16 addr:$src))))]>;
2718 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2720 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2721 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2724 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2726 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2729 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2732 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2733 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2734 Intrinsic IntId64, Intrinsic IntId128> {
2735 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2737 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2738 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2740 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2742 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2745 (bitconvert (memopv2i32 addr:$src))))]>;
2747 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2749 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2750 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2753 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2755 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2758 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2761 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2762 int_x86_ssse3_pabs_b,
2763 int_x86_ssse3_pabs_b_128>;
2764 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2765 int_x86_ssse3_pabs_w,
2766 int_x86_ssse3_pabs_w_128>;
2767 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2768 int_x86_ssse3_pabs_d,
2769 int_x86_ssse3_pabs_d_128>;
2771 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2772 let Constraints = "$src1 = $dst" in {
2773 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2774 Intrinsic IntId64, Intrinsic IntId128,
2775 bit Commutable = 0> {
2776 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2777 (ins VR64:$src1, VR64:$src2),
2778 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2779 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2780 let isCommutable = Commutable;
2782 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2783 (ins VR64:$src1, i64mem:$src2),
2784 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2786 (IntId64 VR64:$src1,
2787 (bitconvert (memopv8i8 addr:$src2))))]>;
2789 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2790 (ins VR128:$src1, VR128:$src2),
2791 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2792 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2794 let isCommutable = Commutable;
2796 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2797 (ins VR128:$src1, i128mem:$src2),
2798 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2800 (IntId128 VR128:$src1,
2801 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2805 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2806 let Constraints = "$src1 = $dst" in {
2807 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2808 Intrinsic IntId64, Intrinsic IntId128,
2809 bit Commutable = 0> {
2810 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2811 (ins VR64:$src1, VR64:$src2),
2812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2813 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2814 let isCommutable = Commutable;
2816 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2817 (ins VR64:$src1, i64mem:$src2),
2818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2820 (IntId64 VR64:$src1,
2821 (bitconvert (memopv4i16 addr:$src2))))]>;
2823 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2824 (ins VR128:$src1, VR128:$src2),
2825 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2826 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2828 let isCommutable = Commutable;
2830 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2831 (ins VR128:$src1, i128mem:$src2),
2832 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2834 (IntId128 VR128:$src1,
2835 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2839 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2840 let Constraints = "$src1 = $dst" in {
2841 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2842 Intrinsic IntId64, Intrinsic IntId128,
2843 bit Commutable = 0> {
2844 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2845 (ins VR64:$src1, VR64:$src2),
2846 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2847 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2848 let isCommutable = Commutable;
2850 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2851 (ins VR64:$src1, i64mem:$src2),
2852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2854 (IntId64 VR64:$src1,
2855 (bitconvert (memopv2i32 addr:$src2))))]>;
2857 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2858 (ins VR128:$src1, VR128:$src2),
2859 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2860 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2862 let isCommutable = Commutable;
2864 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2865 (ins VR128:$src1, i128mem:$src2),
2866 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2868 (IntId128 VR128:$src1,
2869 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2873 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2874 int_x86_ssse3_phadd_w,
2875 int_x86_ssse3_phadd_w_128>;
2876 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2877 int_x86_ssse3_phadd_d,
2878 int_x86_ssse3_phadd_d_128>;
2879 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2880 int_x86_ssse3_phadd_sw,
2881 int_x86_ssse3_phadd_sw_128>;
2882 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2883 int_x86_ssse3_phsub_w,
2884 int_x86_ssse3_phsub_w_128>;
2885 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2886 int_x86_ssse3_phsub_d,
2887 int_x86_ssse3_phsub_d_128>;
2888 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2889 int_x86_ssse3_phsub_sw,
2890 int_x86_ssse3_phsub_sw_128>;
2891 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2892 int_x86_ssse3_pmadd_ub_sw,
2893 int_x86_ssse3_pmadd_ub_sw_128>;
2894 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2895 int_x86_ssse3_pmul_hr_sw,
2896 int_x86_ssse3_pmul_hr_sw_128, 1>;
2897 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2898 int_x86_ssse3_pshuf_b,
2899 int_x86_ssse3_pshuf_b_128>;
2900 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2901 int_x86_ssse3_psign_b,
2902 int_x86_ssse3_psign_b_128>;
2903 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2904 int_x86_ssse3_psign_w,
2905 int_x86_ssse3_psign_w_128>;
2906 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2907 int_x86_ssse3_psign_d,
2908 int_x86_ssse3_psign_d_128>;
2910 let Constraints = "$src1 = $dst" in {
2911 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2912 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2913 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2915 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2916 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2917 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2920 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2921 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2922 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2924 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2925 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2926 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2930 // palignr patterns.
2931 def : Pat<(int_x86_ssse3_palign_r VR64:$src1, VR64:$src2, (i8 imm:$src3)),
2932 (PALIGNR64rr VR64:$src1, VR64:$src2, (BYTE_imm imm:$src3))>,
2933 Requires<[HasSSSE3]>;
2934 def : Pat<(int_x86_ssse3_palign_r VR64:$src1,
2935 (memop64 addr:$src2),
2937 (PALIGNR64rm VR64:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2938 Requires<[HasSSSE3]>;
2940 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1, VR128:$src2, (i8 imm:$src3)),
2941 (PALIGNR128rr VR128:$src1, VR128:$src2, (BYTE_imm imm:$src3))>,
2942 Requires<[HasSSSE3]>;
2943 def : Pat<(int_x86_ssse3_palign_r_128 VR128:$src1,
2944 (memopv2i64 addr:$src2),
2946 (PALIGNR128rm VR128:$src1, addr:$src2, (BYTE_imm imm:$src3))>,
2947 Requires<[HasSSSE3]>;
2949 let AddedComplexity = 5 in {
2950 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2951 (PALIGNR128rr VR128:$src2, VR128:$src1,
2952 (SHUFFLE_get_palign_imm VR128:$src3))>,
2953 Requires<[HasSSSE3]>;
2954 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2955 (PALIGNR128rr VR128:$src2, VR128:$src1,
2956 (SHUFFLE_get_palign_imm VR128:$src3))>,
2957 Requires<[HasSSSE3]>;
2958 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2959 (PALIGNR128rr VR128:$src2, VR128:$src1,
2960 (SHUFFLE_get_palign_imm VR128:$src3))>,
2961 Requires<[HasSSSE3]>;
2962 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2963 (PALIGNR128rr VR128:$src2, VR128:$src1,
2964 (SHUFFLE_get_palign_imm VR128:$src3))>,
2965 Requires<[HasSSSE3]>;
2968 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2969 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2970 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2971 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2973 //===---------------------------------------------------------------------===//
2974 // Non-Instruction Patterns
2975 //===---------------------------------------------------------------------===//
2977 // extload f32 -> f64. This matches load+fextend because we have a hack in
2978 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2980 // Since these loads aren't folded into the fextend, we have to match it
2982 let Predicates = [HasSSE2] in
2983 def : Pat<(fextend (loadf32 addr:$src)),
2984 (CVTSS2SDrm addr:$src)>;
2987 let Predicates = [HasSSE2] in {
2988 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2989 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2990 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2991 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2992 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2993 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2994 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2995 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2996 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2997 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2998 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2999 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3000 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3001 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3002 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3003 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3004 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3005 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3006 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3007 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3008 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3009 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3010 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3011 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3012 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3013 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3014 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3015 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3016 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3017 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3020 // Move scalar to XMM zero-extended
3021 // movd to XMM register zero-extends
3022 let AddedComplexity = 15 in {
3023 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3024 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3025 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
3026 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3027 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
3028 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3029 (MOVSSrr (v4f32 (V_SET0)),
3030 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
3031 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3032 (MOVSSrr (v4i32 (V_SET0)),
3033 (EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
3036 // Splat v2f64 / v2i64
3037 let AddedComplexity = 10 in {
3038 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3039 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3040 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3041 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3042 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3043 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3044 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3045 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3048 // Special unary SHUFPSrri case.
3049 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3050 (SHUFPSrri VR128:$src1, VR128:$src1,
3051 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3052 let AddedComplexity = 5 in
3053 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3054 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3055 Requires<[HasSSE2]>;
3056 // Special unary SHUFPDrri case.
3057 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3058 (SHUFPDrri VR128:$src1, VR128:$src1,
3059 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3060 Requires<[HasSSE2]>;
3061 // Special unary SHUFPDrri case.
3062 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3063 (SHUFPDrri VR128:$src1, VR128:$src1,
3064 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3065 Requires<[HasSSE2]>;
3066 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3067 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3068 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3069 Requires<[HasSSE2]>;
3071 // Special binary v4i32 shuffle cases with SHUFPS.
3072 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3073 (SHUFPSrri VR128:$src1, VR128:$src2,
3074 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3075 Requires<[HasSSE2]>;
3076 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3077 (SHUFPSrmi VR128:$src1, addr:$src2,
3078 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3079 Requires<[HasSSE2]>;
3080 // Special binary v2i64 shuffle cases using SHUFPDrri.
3081 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3082 (SHUFPDrri VR128:$src1, VR128:$src2,
3083 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3084 Requires<[HasSSE2]>;
3086 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3087 let AddedComplexity = 15 in {
3088 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3089 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3090 Requires<[OptForSpeed, HasSSE2]>;
3091 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3092 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3093 Requires<[OptForSpeed, HasSSE2]>;
3095 let AddedComplexity = 10 in {
3096 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3097 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3098 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3099 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3100 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3101 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3102 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3103 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3106 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3107 let AddedComplexity = 15 in {
3108 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3109 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3110 Requires<[OptForSpeed, HasSSE2]>;
3111 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3112 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3113 Requires<[OptForSpeed, HasSSE2]>;
3115 let AddedComplexity = 10 in {
3116 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3117 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3118 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3119 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3120 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3121 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3122 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3123 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3126 let AddedComplexity = 20 in {
3127 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3128 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3129 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3131 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3132 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3133 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3135 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3136 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3137 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3138 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3139 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3142 let AddedComplexity = 20 in {
3143 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3144 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3145 (MOVLPSrm VR128:$src1, addr:$src2)>;
3146 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3147 (MOVLPDrm VR128:$src1, addr:$src2)>;
3148 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3149 (MOVLPSrm VR128:$src1, addr:$src2)>;
3150 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3151 (MOVLPDrm VR128:$src1, addr:$src2)>;
3154 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3155 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3156 (MOVLPSmr addr:$src1, VR128:$src2)>;
3157 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3158 (MOVLPDmr addr:$src1, VR128:$src2)>;
3159 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3161 (MOVLPSmr addr:$src1, VR128:$src2)>;
3162 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3163 (MOVLPDmr addr:$src1, VR128:$src2)>;
3165 let AddedComplexity = 15 in {
3166 // Setting the lowest element in the vector.
3167 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3168 (MOVSSrr (v4i32 VR128:$src1),
3169 (EXTRACT_SUBREG (v4i32 VR128:$src2), x86_subreg_ss))>;
3170 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3171 (MOVSDrr (v2i64 VR128:$src1),
3172 (EXTRACT_SUBREG (v2i64 VR128:$src2), x86_subreg_sd))>;
3174 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3175 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3176 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3177 Requires<[HasSSE2]>;
3178 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3179 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3180 Requires<[HasSSE2]>;
3183 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3184 // fall back to this for SSE1)
3185 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3186 (SHUFPSrri VR128:$src2, VR128:$src1,
3187 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3189 // Set lowest element and zero upper elements.
3190 let AddedComplexity = 15 in
3191 def : Pat<(v2f64 (movl immAllZerosV_bc, VR128:$src)),
3192 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3193 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3194 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3196 // Some special case pandn patterns.
3197 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3199 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3200 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3202 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3203 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3205 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3207 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3208 (memop addr:$src2))),
3209 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3210 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3211 (memop addr:$src2))),
3212 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3213 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3214 (memop addr:$src2))),
3215 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3217 // vector -> vector casts
3218 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3219 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3220 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3221 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3222 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3223 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3224 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3225 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3227 // Use movaps / movups for SSE integer load / store (one byte shorter).
3228 def : Pat<(alignedloadv4i32 addr:$src),
3229 (MOVAPSrm addr:$src)>;
3230 def : Pat<(loadv4i32 addr:$src),
3231 (MOVUPSrm addr:$src)>;
3232 def : Pat<(alignedloadv2i64 addr:$src),
3233 (MOVAPSrm addr:$src)>;
3234 def : Pat<(loadv2i64 addr:$src),
3235 (MOVUPSrm addr:$src)>;
3237 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3238 (MOVAPSmr addr:$dst, VR128:$src)>;
3239 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3240 (MOVAPSmr addr:$dst, VR128:$src)>;
3241 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3242 (MOVAPSmr addr:$dst, VR128:$src)>;
3243 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3244 (MOVAPSmr addr:$dst, VR128:$src)>;
3245 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3246 (MOVUPSmr addr:$dst, VR128:$src)>;
3247 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3248 (MOVUPSmr addr:$dst, VR128:$src)>;
3249 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3250 (MOVUPSmr addr:$dst, VR128:$src)>;
3251 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3252 (MOVUPSmr addr:$dst, VR128:$src)>;
3254 //===----------------------------------------------------------------------===//
3255 // SSE4.1 Instructions
3256 //===----------------------------------------------------------------------===//
3258 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3261 Intrinsic V2F64Int> {
3262 // Intrinsic operation, reg.
3263 // Vector intrinsic operation, reg
3264 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3265 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3266 !strconcat(OpcodeStr,
3267 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3268 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3271 // Vector intrinsic operation, mem
3272 def PSm_Int : Ii8<opcps, MRMSrcMem,
3273 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3274 !strconcat(OpcodeStr,
3275 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3277 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3279 Requires<[HasSSE41]>;
3281 // Vector intrinsic operation, reg
3282 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3283 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3284 !strconcat(OpcodeStr,
3285 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3286 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3289 // Vector intrinsic operation, mem
3290 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3291 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3292 !strconcat(OpcodeStr,
3293 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3295 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3299 let Constraints = "$src1 = $dst" in {
3300 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3304 // Intrinsic operation, reg.
3305 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3307 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3308 !strconcat(OpcodeStr,
3309 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3311 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3314 // Intrinsic operation, mem.
3315 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3317 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3318 !strconcat(OpcodeStr,
3319 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3321 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3324 // Intrinsic operation, reg.
3325 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3327 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3328 !strconcat(OpcodeStr,
3329 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3331 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3334 // Intrinsic operation, mem.
3335 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3337 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3338 !strconcat(OpcodeStr,
3339 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3341 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3346 // FP round - roundss, roundps, roundsd, roundpd
3347 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3348 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3349 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3350 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3352 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3353 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3354 Intrinsic IntId128> {
3355 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3357 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3358 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3359 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3364 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3367 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3368 int_x86_sse41_phminposuw>;
3370 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3371 let Constraints = "$src1 = $dst" in {
3372 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3373 Intrinsic IntId128, bit Commutable = 0> {
3374 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3375 (ins VR128:$src1, VR128:$src2),
3376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3377 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3379 let isCommutable = Commutable;
3381 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3382 (ins VR128:$src1, i128mem:$src2),
3383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3385 (IntId128 VR128:$src1,
3386 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3390 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3391 int_x86_sse41_pcmpeqq, 1>;
3392 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3393 int_x86_sse41_packusdw, 0>;
3394 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3395 int_x86_sse41_pminsb, 1>;
3396 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3397 int_x86_sse41_pminsd, 1>;
3398 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3399 int_x86_sse41_pminud, 1>;
3400 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3401 int_x86_sse41_pminuw, 1>;
3402 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3403 int_x86_sse41_pmaxsb, 1>;
3404 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3405 int_x86_sse41_pmaxsd, 1>;
3406 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3407 int_x86_sse41_pmaxud, 1>;
3408 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3409 int_x86_sse41_pmaxuw, 1>;
3411 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3413 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3414 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3415 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3416 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3418 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3419 let Constraints = "$src1 = $dst" in {
3420 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3421 SDNode OpNode, Intrinsic IntId128,
3422 bit Commutable = 0> {
3423 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3424 (ins VR128:$src1, VR128:$src2),
3425 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3426 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3427 VR128:$src2))]>, OpSize {
3428 let isCommutable = Commutable;
3430 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3431 (ins VR128:$src1, VR128:$src2),
3432 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3433 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3435 let isCommutable = Commutable;
3437 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3438 (ins VR128:$src1, i128mem:$src2),
3439 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3441 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3442 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3443 (ins VR128:$src1, i128mem:$src2),
3444 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3446 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3450 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3451 int_x86_sse41_pmulld, 1>;
3453 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3454 let Constraints = "$src1 = $dst" in {
3455 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3456 Intrinsic IntId128, bit Commutable = 0> {
3457 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3458 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3459 !strconcat(OpcodeStr,
3460 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3462 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3464 let isCommutable = Commutable;
3466 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3467 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3468 !strconcat(OpcodeStr,
3469 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3471 (IntId128 VR128:$src1,
3472 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3477 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3478 int_x86_sse41_blendps, 0>;
3479 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3480 int_x86_sse41_blendpd, 0>;
3481 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3482 int_x86_sse41_pblendw, 0>;
3483 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3484 int_x86_sse41_dpps, 1>;
3485 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3486 int_x86_sse41_dppd, 1>;
3487 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3488 int_x86_sse41_mpsadbw, 1>;
3491 /// SS41I_ternary_int - SSE 4.1 ternary operator
3492 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3493 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3494 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3495 (ins VR128:$src1, VR128:$src2),
3496 !strconcat(OpcodeStr,
3497 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3498 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3501 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3502 (ins VR128:$src1, i128mem:$src2),
3503 !strconcat(OpcodeStr,
3504 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3507 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3511 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3512 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3513 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3516 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3517 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3518 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3519 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3521 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3522 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3524 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3528 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3529 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3530 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3531 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3532 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3533 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3535 // Common patterns involving scalar load.
3536 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3537 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3538 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3539 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3541 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3542 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3543 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3544 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3546 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3547 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3548 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3549 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3551 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3552 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3553 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3554 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3556 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3557 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3558 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3559 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3561 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3562 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3563 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3564 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3567 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3568 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3569 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3570 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3572 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3573 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3575 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3579 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3580 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3581 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3582 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3584 // Common patterns involving scalar load
3585 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3586 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3587 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3588 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3590 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3591 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3592 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3593 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3596 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3597 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3599 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3601 // Expecting a i16 load any extended to i32 value.
3602 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3603 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3604 [(set VR128:$dst, (IntId (bitconvert
3605 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3609 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3610 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3612 // Common patterns involving scalar load
3613 def : Pat<(int_x86_sse41_pmovsxbq
3614 (bitconvert (v4i32 (X86vzmovl
3615 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3616 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3618 def : Pat<(int_x86_sse41_pmovzxbq
3619 (bitconvert (v4i32 (X86vzmovl
3620 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3621 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3624 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3625 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3626 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3627 (ins VR128:$src1, i32i8imm:$src2),
3628 !strconcat(OpcodeStr,
3629 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3630 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3632 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3633 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3634 !strconcat(OpcodeStr,
3635 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3638 // There's an AssertZext in the way of writing the store pattern
3639 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3642 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3645 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3646 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3647 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3648 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3649 !strconcat(OpcodeStr,
3650 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3653 // There's an AssertZext in the way of writing the store pattern
3654 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3657 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3660 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3661 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3662 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3663 (ins VR128:$src1, i32i8imm:$src2),
3664 !strconcat(OpcodeStr,
3665 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3667 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3668 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3669 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3670 !strconcat(OpcodeStr,
3671 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3672 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3673 addr:$dst)]>, OpSize;
3676 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3679 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3681 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3682 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3683 (ins VR128:$src1, i32i8imm:$src2),
3684 !strconcat(OpcodeStr,
3685 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3687 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3689 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3690 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3691 !strconcat(OpcodeStr,
3692 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3693 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3694 addr:$dst)]>, OpSize;
3697 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3699 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3700 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3703 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3704 Requires<[HasSSE41]>;
3706 let Constraints = "$src1 = $dst" in {
3707 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3708 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3709 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3710 !strconcat(OpcodeStr,
3711 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3713 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3714 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3715 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3716 !strconcat(OpcodeStr,
3717 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3719 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3720 imm:$src3))]>, OpSize;
3724 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3726 let Constraints = "$src1 = $dst" in {
3727 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3728 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3729 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3730 !strconcat(OpcodeStr,
3731 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3733 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3735 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3736 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3737 !strconcat(OpcodeStr,
3738 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3740 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3741 imm:$src3)))]>, OpSize;
3745 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3747 // insertps has a few different modes, there's the first two here below which
3748 // are optimized inserts that won't zero arbitrary elements in the destination
3749 // vector. The next one matches the intrinsic and could zero arbitrary elements
3750 // in the target vector.
3751 let Constraints = "$src1 = $dst" in {
3752 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3753 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3754 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3755 !strconcat(OpcodeStr,
3756 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3758 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3760 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3761 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3762 !strconcat(OpcodeStr,
3763 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3765 (X86insrtps VR128:$src1,
3766 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3767 imm:$src3))]>, OpSize;
3771 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3773 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3774 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3776 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3777 // the intel intrinsic that corresponds to this.
3778 let Defs = [EFLAGS] in {
3779 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3780 "ptest \t{$src2, $src1|$src1, $src2}",
3781 [(X86ptest VR128:$src1, VR128:$src2),
3782 (implicit EFLAGS)]>, OpSize;
3783 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3784 "ptest \t{$src2, $src1|$src1, $src2}",
3785 [(X86ptest VR128:$src1, (load addr:$src2)),
3786 (implicit EFLAGS)]>, OpSize;
3789 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3790 "movntdqa\t{$src, $dst|$dst, $src}",
3791 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3795 //===----------------------------------------------------------------------===//
3796 // SSE4.2 Instructions
3797 //===----------------------------------------------------------------------===//
3799 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3800 let Constraints = "$src1 = $dst" in {
3801 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3802 Intrinsic IntId128, bit Commutable = 0> {
3803 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3804 (ins VR128:$src1, VR128:$src2),
3805 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3806 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3808 let isCommutable = Commutable;
3810 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3811 (ins VR128:$src1, i128mem:$src2),
3812 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3814 (IntId128 VR128:$src1,
3815 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3819 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3821 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3822 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3823 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3824 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3826 defm AESIMC : SS42I_binop_rm_int<0xDB, "aesimc",
3827 int_x86_sse42_aesimc>;
3828 defm AESENC : SS42I_binop_rm_int<0xDC, "aesenc",
3829 int_x86_sse42_aesenc>;
3830 defm AESENCLAST : SS42I_binop_rm_int<0xDD, "aesenclast",
3831 int_x86_sse42_aesenclast>;
3832 defm AESDEC : SS42I_binop_rm_int<0xDE, "aesdec",
3833 int_x86_sse42_aesdec>;
3834 defm AESDECLAST : SS42I_binop_rm_int<0xDF, "aesdeclast",
3835 int_x86_sse42_aesdeclast>;
3837 def : Pat<(v2i64 (X86aesimc VR128:$src1, VR128:$src2)),
3838 (AESIMCrr VR128:$src1, VR128:$src2)>;
3839 def : Pat<(v2i64 (X86aesimc VR128:$src1, (memop addr:$src2))),
3840 (AESIMCrm VR128:$src1, addr:$src2)>;
3841 def : Pat<(v2i64 (X86aesenc VR128:$src1, VR128:$src2)),
3842 (AESENCrr VR128:$src1, VR128:$src2)>;
3843 def : Pat<(v2i64 (X86aesenc VR128:$src1, (memop addr:$src2))),
3844 (AESENCrm VR128:$src1, addr:$src2)>;
3845 def : Pat<(v2i64 (X86aesenclast VR128:$src1, VR128:$src2)),
3846 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3847 def : Pat<(v2i64 (X86aesenclast VR128:$src1, (memop addr:$src2))),
3848 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3849 def : Pat<(v2i64 (X86aesdec VR128:$src1, VR128:$src2)),
3850 (AESDECrr VR128:$src1, VR128:$src2)>;
3851 def : Pat<(v2i64 (X86aesdec VR128:$src1, (memop addr:$src2))),
3852 (AESDECrm VR128:$src1, addr:$src2)>;
3853 def : Pat<(v2i64 (X86aesdeclast VR128:$src1, VR128:$src2)),
3854 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3855 def : Pat<(v2i64 (X86aesdeclast VR128:$src1, (memop addr:$src2))),
3856 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3858 def AESKEYGENASSIST128rr : SS42AI<0xDF, MRMSrcReg, (outs),
3859 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3860 "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3861 def AESKEYGENASSIST128rm : SS42AI<0xDF, MRMSrcMem, (outs),
3862 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3863 "aeskeygenassist\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3865 // crc intrinsic instruction
3866 // This set of instructions are only rm, the only difference is the size
3868 let Constraints = "$src1 = $dst" in {
3869 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3870 (ins GR32:$src1, i8mem:$src2),
3871 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3873 (int_x86_sse42_crc32_8 GR32:$src1,
3874 (load addr:$src2)))]>;
3875 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3876 (ins GR32:$src1, GR8:$src2),
3877 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3879 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3880 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3881 (ins GR32:$src1, i16mem:$src2),
3882 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3884 (int_x86_sse42_crc32_16 GR32:$src1,
3885 (load addr:$src2)))]>,
3887 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3888 (ins GR32:$src1, GR16:$src2),
3889 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3891 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3893 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3894 (ins GR32:$src1, i32mem:$src2),
3895 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3897 (int_x86_sse42_crc32_32 GR32:$src1,
3898 (load addr:$src2)))]>;
3899 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3900 (ins GR32:$src1, GR32:$src2),
3901 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3903 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3904 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3905 (ins GR64:$src1, i8mem:$src2),
3906 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3908 (int_x86_sse42_crc64_8 GR64:$src1,
3909 (load addr:$src2)))]>,
3911 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3912 (ins GR64:$src1, GR8:$src2),
3913 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3915 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3917 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3918 (ins GR64:$src1, i64mem:$src2),
3919 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3921 (int_x86_sse42_crc64_64 GR64:$src1,
3922 (load addr:$src2)))]>,
3924 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3925 (ins GR64:$src1, GR64:$src2),
3926 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3928 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3932 // String/text processing instructions.
3933 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3934 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3935 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3936 "#PCMPISTRM128rr PSEUDO!",
3937 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3938 imm:$src3))]>, OpSize;
3939 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3940 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3941 "#PCMPISTRM128rm PSEUDO!",
3942 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3943 imm:$src3))]>, OpSize;
3946 let Defs = [XMM0, EFLAGS] in {
3947 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3948 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3949 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3950 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3951 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3952 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3955 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3956 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3957 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3958 "#PCMPESTRM128rr PSEUDO!",
3960 (int_x86_sse42_pcmpestrm128
3961 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3963 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3964 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3965 "#PCMPESTRM128rm PSEUDO!",
3966 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3967 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3971 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3972 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3973 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3974 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3975 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3976 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3977 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3980 let Defs = [ECX, EFLAGS] in {
3981 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3982 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3983 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3984 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3985 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3986 (implicit EFLAGS)]>, OpSize;
3987 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3988 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3989 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3990 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3991 (implicit EFLAGS)]>, OpSize;
3995 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3996 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3997 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3998 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3999 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4000 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4002 let Defs = [ECX, EFLAGS] in {
4003 let Uses = [EAX, EDX] in {
4004 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
4005 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4006 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4007 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4008 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4009 (implicit EFLAGS)]>, OpSize;
4010 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4011 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4012 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4014 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4015 (implicit EFLAGS)]>, OpSize;
4020 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4021 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4022 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4023 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4024 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4025 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;