1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 // MOVSSrm zeros the high parts of the register; represent this
190 // with SUBREG_TO_REG.
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
192 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 // MOVSDrm zeros the high parts of the register; represent this
198 // with SUBREG_TO_REG.
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
200 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
201 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzload addr:$src)),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
211 // Store scalar value to memory.
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
226 // Extract and store.
227 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
230 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
231 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
236 // Move Aligned/Unaligned floating point values
237 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
238 X86MemOperand x86memop, PatFrag ld_frag,
239 string asm, Domain d,
240 bit IsReMaterializable = 1> {
241 let neverHasSideEffects = 1 in
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
244 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
250 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
251 "movaps", SSEPackedSingle>, VEX;
252 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
253 "movapd", SSEPackedDouble>, OpSize, VEX;
254 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
255 "movups", SSEPackedSingle>, VEX;
256 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
259 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
260 "movaps", SSEPackedSingle>, VEX;
261 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
262 "movapd", SSEPackedDouble>, OpSize, VEX;
263 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
264 "movups", SSEPackedSingle>, VEX;
265 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
267 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
268 "movaps", SSEPackedSingle>, TB;
269 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
270 "movapd", SSEPackedDouble>, TB, OpSize;
271 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
272 "movups", SSEPackedSingle>, TB;
273 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
305 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
322 // Intrinsic forms of MOVUPS/D load and store
323 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
327 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
339 // Move Low/High packed floating point values
340 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
341 PatFrag mov_frag, string base_opc,
343 def PSrm : PI<opc, MRMSrcMem,
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
345 !strconcat(base_opc, "s", asm_opr),
348 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
349 SSEPackedSingle>, TB;
351 def PDrm : PI<opc, MRMSrcMem,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
353 !strconcat(base_opc, "d", asm_opr),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
355 (scalar_to_vector (loadf64 addr:$src2)))))],
356 SSEPackedDouble>, TB, OpSize;
359 let AddedComplexity = 20 in {
360 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
362 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
366 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
367 "\t{$src2, $dst|$dst, $src2}">;
368 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
374 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
378 [(store (f64 (vector_extract (v2f64 VR128:$src),
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
382 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
386 [(store (f64 (vector_extract (v2f64 VR128:$src),
387 (iPTR 0))), addr:$dst)]>;
389 // v2f64 extract element 1 is always custom lowered to unpack high to low
390 // and extract element 0 so the non-store version isn't too horrible.
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
393 [(store (f64 (vector_extract
394 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
399 [(store (f64 (vector_extract
400 (v2f64 (unpckh VR128:$src, (undef))),
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract
406 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract
411 (v2f64 (unpckh VR128:$src, (undef))),
412 (iPTR 0))), addr:$dst)]>;
414 let AddedComplexity = 20 in {
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
416 (ins VR128:$src1, VR128:$src2),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
422 (ins VR128:$src1, VR128:$src2),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
425 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
433 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
435 (ins VR128:$src1, VR128:$src2),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
438 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
441 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
442 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
443 let AddedComplexity = 20 in {
444 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
445 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
446 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
447 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Conversion Instructions
452 //===----------------------------------------------------------------------===//
454 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
455 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
463 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
464 X86MemOperand x86memop, string asm> {
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
471 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
472 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
473 string asm, Domain d> {
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
480 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
481 X86MemOperand x86memop, string asm> {
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
485 (ins DstRC:$src1, x86memop:$src),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
489 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
491 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
494 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
500 // The assembler can recognize rr 64-bit instructions by seeing a rxx
501 // register, but the same isn't true when only using memory operands,
502 // provide other assembly "l" and "q" forms to address this explicitly
503 // where appropriate to do so.
504 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
506 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
508 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
510 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
512 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
515 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
516 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
517 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
518 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
519 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
520 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
521 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
522 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
523 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
524 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
527 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
528 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
529 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
530 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
532 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
533 // and/or XMM operand(s).
535 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
536 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
538 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
539 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
540 [(set DstRC:$dst, (Int SrcRC:$src))]>;
541 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
543 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
546 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
547 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
548 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
549 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
551 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
552 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
553 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
554 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
555 (ins DstRC:$src1, x86memop:$src2),
557 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
558 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
559 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
562 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
563 f32mem, load, "cvtss2si">, XS, VEX;
564 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
565 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
567 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
568 f128mem, load, "cvtsd2si">, XD, VEX;
569 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
570 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
573 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
574 // Get rid of this hack or rename the intrinsics, there are several
575 // intructions that only match with the intrinsic form, why create duplicates
576 // to let them be recognized by the assembler?
577 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
578 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
579 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
580 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
581 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
582 f32mem, load, "cvtss2si">, XS;
583 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
584 f32mem, load, "cvtss2si{q}">, XS, REX_W;
585 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
586 f128mem, load, "cvtsd2si{l}">, XD;
587 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
588 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
591 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
592 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
593 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
594 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
596 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
597 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
598 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
599 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
602 let Constraints = "$src1 = $dst" in {
603 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
604 int_x86_sse_cvtsi2ss, i32mem, loadi32,
606 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
607 int_x86_sse_cvtsi642ss, i64mem, loadi64,
608 "cvtsi2ss{q}">, XS, REX_W;
609 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
610 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
612 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
613 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
614 "cvtsi2sd">, XD, REX_W;
619 // Aliases for intrinsics
620 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
621 f32mem, load, "cvttss2si">, XS, VEX;
622 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
623 int_x86_sse_cvttss2si64, f32mem, load,
624 "cvttss2si">, XS, VEX, VEX_W;
625 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
626 f128mem, load, "cvttsd2si">, XD, VEX;
627 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
628 int_x86_sse2_cvttsd2si64, f128mem, load,
629 "cvttsd2si">, XD, VEX, VEX_W;
630 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
631 f32mem, load, "cvttss2si">, XS;
632 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
633 int_x86_sse_cvttss2si64, f32mem, load,
634 "cvttss2si{q}">, XS, REX_W;
635 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
636 f128mem, load, "cvttsd2si">, XD;
637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
638 int_x86_sse2_cvttsd2si64, f128mem, load,
639 "cvttsd2si{q}">, XD, REX_W;
641 let Pattern = []<dag> in {
642 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
643 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
644 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
645 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
647 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
649 SSEPackedSingle>, TB, VEX;
650 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
651 "cvtdq2ps\t{$src, $dst|$dst, $src}",
652 SSEPackedSingle>, TB, VEX;
654 let Pattern = []<dag> in {
655 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
656 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
657 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
658 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
659 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
660 "cvtdq2ps\t{$src, $dst|$dst, $src}",
661 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
666 // Convert scalar double to scalar single
667 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
668 (ins FR64:$src1, FR64:$src2),
669 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
671 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
672 (ins FR64:$src1, f64mem:$src2),
673 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
674 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
675 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
678 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
679 "cvtsd2ss\t{$src, $dst|$dst, $src}",
680 [(set FR32:$dst, (fround FR64:$src))]>;
681 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
682 "cvtsd2ss\t{$src, $dst|$dst, $src}",
683 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
684 Requires<[HasSSE2, OptForSize]>;
686 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
687 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
689 let Constraints = "$src1 = $dst" in
690 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
691 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
693 // Convert scalar single to scalar double
694 // SSE2 instructions with XS prefix
695 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
696 (ins FR32:$src1, FR32:$src2),
697 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 []>, XS, Requires<[HasAVX]>, VEX_4V;
699 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
700 (ins FR32:$src1, f32mem:$src2),
701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
702 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
703 def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>,
706 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
707 "cvtss2sd\t{$src, $dst|$dst, $src}",
708 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
710 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
711 "cvtss2sd\t{$src, $dst|$dst, $src}",
712 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
713 Requires<[HasSSE2, OptForSize]>;
715 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
719 VR128:$src2))]>, XS, VEX_4V,
721 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
722 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
723 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
724 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
725 (load addr:$src2)))]>, XS, VEX_4V,
727 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
728 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
729 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
730 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
731 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
734 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
735 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
736 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
737 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
738 (load addr:$src2)))]>, XS,
742 def : Pat<(extloadf32 addr:$src),
743 (CVTSS2SDrr (MOVSSrm addr:$src))>,
744 Requires<[HasSSE2, OptForSpeed]>;
746 // Convert doubleword to packed single/double fp
747 // SSE2 instructions without OpSize prefix
748 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
749 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
750 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
751 TB, VEX, Requires<[HasAVX]>;
752 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
753 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
754 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
755 (bitconvert (memopv2i64 addr:$src))))]>,
756 TB, VEX, Requires<[HasAVX]>;
757 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
758 "cvtdq2ps\t{$src, $dst|$dst, $src}",
759 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
760 TB, Requires<[HasSSE2]>;
761 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
762 "cvtdq2ps\t{$src, $dst|$dst, $src}",
763 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
764 (bitconvert (memopv2i64 addr:$src))))]>,
765 TB, Requires<[HasSSE2]>;
767 // FIXME: why the non-intrinsic version is described as SSE3?
768 // SSE2 instructions with XS prefix
769 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
770 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
772 XS, VEX, Requires<[HasAVX]>;
773 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
774 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
775 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
776 (bitconvert (memopv2i64 addr:$src))))]>,
777 XS, VEX, Requires<[HasAVX]>;
778 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
779 "cvtdq2pd\t{$src, $dst|$dst, $src}",
780 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
781 XS, Requires<[HasSSE2]>;
782 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
783 "cvtdq2pd\t{$src, $dst|$dst, $src}",
784 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
785 (bitconvert (memopv2i64 addr:$src))))]>,
786 XS, Requires<[HasSSE2]>;
789 // Convert packed single/double fp to doubleword
790 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
791 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
792 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
793 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
794 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
795 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
796 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
797 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
798 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
799 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
800 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
801 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
803 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
804 "cvtps2dq\t{$src, $dst|$dst, $src}",
805 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
807 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
809 "cvtps2dq\t{$src, $dst|$dst, $src}",
810 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
811 (memop addr:$src)))]>, VEX;
812 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
813 "cvtps2dq\t{$src, $dst|$dst, $src}",
814 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
815 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
816 "cvtps2dq\t{$src, $dst|$dst, $src}",
817 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
818 (memop addr:$src)))]>;
820 // SSE2 packed instructions with XD prefix
821 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
822 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
823 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
824 XD, VEX, Requires<[HasAVX]>;
825 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
826 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
827 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
828 (memop addr:$src)))]>,
829 XD, VEX, Requires<[HasAVX]>;
830 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtpd2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
833 XD, Requires<[HasSSE2]>;
834 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
835 "cvtpd2dq\t{$src, $dst|$dst, $src}",
836 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
837 (memop addr:$src)))]>,
838 XD, Requires<[HasSSE2]>;
841 // Convert with truncation packed single/double fp to doubleword
842 // SSE2 packed instructions with XS prefix
843 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
844 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
845 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
846 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
847 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
848 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
849 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
850 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
851 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
852 "cvttps2dq\t{$src, $dst|$dst, $src}",
854 (int_x86_sse2_cvttps2dq VR128:$src))]>;
855 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
856 "cvttps2dq\t{$src, $dst|$dst, $src}",
858 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
861 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
862 "vcvttps2dq\t{$src, $dst|$dst, $src}",
864 (int_x86_sse2_cvttps2dq VR128:$src))]>,
865 XS, VEX, Requires<[HasAVX]>;
866 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
867 "vcvttps2dq\t{$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
869 (memop addr:$src)))]>,
870 XS, VEX, Requires<[HasAVX]>;
872 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
874 "cvttpd2dq\t{$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
877 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
879 "cvttpd2dq\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
881 (memop addr:$src)))]>, VEX;
882 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
883 "cvttpd2dq\t{$src, $dst|$dst, $src}",
884 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
885 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
886 "cvttpd2dq\t{$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
888 (memop addr:$src)))]>;
890 // The assembler can recognize rr 256-bit instructions by seeing a ymm
891 // register, but the same isn't true when using memory operands instead.
892 // Provide other assembly rr and rm forms to address this explicitly.
893 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
894 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
895 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
896 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
899 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
900 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
901 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
905 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
906 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
907 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
908 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
910 // Convert packed single to packed double
911 let Predicates = [HasAVX] in {
912 // SSE2 instructions without OpSize prefix
913 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
914 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
915 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
916 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
917 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
918 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
919 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
920 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
922 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
924 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
925 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
927 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 "vcvtps2pd\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
930 VEX, Requires<[HasAVX]>;
931 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
932 "vcvtps2pd\t{$src, $dst|$dst, $src}",
933 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
934 (load addr:$src)))]>,
935 VEX, Requires<[HasAVX]>;
936 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "cvtps2pd\t{$src, $dst|$dst, $src}",
938 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
939 TB, Requires<[HasSSE2]>;
940 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
941 "cvtps2pd\t{$src, $dst|$dst, $src}",
942 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
943 (load addr:$src)))]>,
944 TB, Requires<[HasSSE2]>;
946 // Convert packed double to packed single
947 // The assembler can recognize rr 256-bit instructions by seeing a ymm
948 // register, but the same isn't true when using memory operands instead.
949 // Provide other assembly rr and rm forms to address this explicitly.
950 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
951 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
952 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
953 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
956 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
963 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
964 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
965 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
966 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
967 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
968 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
969 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
972 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "cvtpd2ps\t{$src, $dst|$dst, $src}",
974 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
975 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
977 "cvtpd2ps\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
979 (memop addr:$src)))]>;
980 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
981 "cvtpd2ps\t{$src, $dst|$dst, $src}",
982 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
983 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
984 "cvtpd2ps\t{$src, $dst|$dst, $src}",
985 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
986 (memop addr:$src)))]>;
988 // AVX 256-bit register conversion intrinsics
989 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
990 // whenever possible to avoid declaring two versions of each one.
991 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
992 (VCVTDQ2PSYrr VR256:$src)>;
993 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
994 (VCVTDQ2PSYrm addr:$src)>;
996 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
997 (VCVTPD2PSYrr VR256:$src)>;
998 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
999 (VCVTPD2PSYrm addr:$src)>;
1001 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1002 (VCVTPS2DQYrr VR256:$src)>;
1003 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1004 (VCVTPS2DQYrm addr:$src)>;
1006 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1007 (VCVTPS2PDYrr VR128:$src)>;
1008 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1009 (VCVTPS2PDYrm addr:$src)>;
1011 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1012 (VCVTTPD2DQYrr VR256:$src)>;
1013 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1014 (VCVTTPD2DQYrm addr:$src)>;
1016 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1017 (VCVTTPS2DQYrr VR256:$src)>;
1018 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1019 (VCVTTPS2DQYrm addr:$src)>;
1021 //===----------------------------------------------------------------------===//
1022 // SSE 1 & 2 - Compare Instructions
1023 //===----------------------------------------------------------------------===//
1025 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1026 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1027 string asm, string asm_alt> {
1028 let isAsmParserOnly = 1 in {
1029 def rr : SIi8<0xC2, MRMSrcReg,
1030 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1033 def rm : SIi8<0xC2, MRMSrcMem,
1034 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1038 // Accept explicit immediate argument form instead of comparison code.
1039 def rr_alt : SIi8<0xC2, MRMSrcReg,
1040 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1043 def rm_alt : SIi8<0xC2, MRMSrcMem,
1044 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1048 let neverHasSideEffects = 1 in {
1049 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1050 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1051 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1053 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1054 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1055 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1059 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1060 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1061 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1062 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1063 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1064 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1065 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1068 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1069 Intrinsic Int, string asm> {
1070 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1071 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1072 [(set VR128:$dst, (Int VR128:$src1,
1073 VR128:$src, imm:$cc))]>;
1074 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1075 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1076 [(set VR128:$dst, (Int VR128:$src1,
1077 (load addr:$src), imm:$cc))]>;
1080 // Aliases to match intrinsics which expect XMM operand(s).
1081 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1082 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1084 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1085 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1087 let Constraints = "$src1 = $dst" in {
1088 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1089 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1090 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1091 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1095 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1096 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1097 ValueType vt, X86MemOperand x86memop,
1098 PatFrag ld_frag, string OpcodeStr, Domain d> {
1099 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1100 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1101 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1102 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1103 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1104 [(set EFLAGS, (OpNode (vt RC:$src1),
1105 (ld_frag addr:$src2)))], d>;
1108 let Defs = [EFLAGS] in {
1109 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1110 "ucomiss", SSEPackedSingle>, VEX;
1111 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1112 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1113 let Pattern = []<dag> in {
1114 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1115 "comiss", SSEPackedSingle>, VEX;
1116 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1117 "comisd", SSEPackedDouble>, OpSize, VEX;
1120 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1121 load, "ucomiss", SSEPackedSingle>, VEX;
1122 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1123 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1125 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1126 load, "comiss", SSEPackedSingle>, VEX;
1127 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1128 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1129 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1130 "ucomiss", SSEPackedSingle>, TB;
1131 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1132 "ucomisd", SSEPackedDouble>, TB, OpSize;
1134 let Pattern = []<dag> in {
1135 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1136 "comiss", SSEPackedSingle>, TB;
1137 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1138 "comisd", SSEPackedDouble>, TB, OpSize;
1141 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1142 load, "ucomiss", SSEPackedSingle>, TB;
1143 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1144 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1146 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1147 "comiss", SSEPackedSingle>, TB;
1148 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1149 "comisd", SSEPackedDouble>, TB, OpSize;
1150 } // Defs = [EFLAGS]
1152 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1153 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1154 Intrinsic Int, string asm, string asm_alt,
1156 let isAsmParserOnly = 1 in {
1157 def rri : PIi8<0xC2, MRMSrcReg,
1158 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1159 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1160 def rmi : PIi8<0xC2, MRMSrcMem,
1161 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1162 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1165 // Accept explicit immediate argument form instead of comparison code.
1166 def rri_alt : PIi8<0xC2, MRMSrcReg,
1167 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1169 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1170 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1174 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1175 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1176 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1177 SSEPackedSingle>, VEX_4V;
1178 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1179 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1180 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1181 SSEPackedDouble>, OpSize, VEX_4V;
1182 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1183 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1184 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1185 SSEPackedSingle>, VEX_4V;
1186 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1187 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1188 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1189 SSEPackedDouble>, OpSize, VEX_4V;
1190 let Constraints = "$src1 = $dst" in {
1191 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1192 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1193 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1194 SSEPackedSingle>, TB;
1195 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1196 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1197 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1198 SSEPackedDouble>, TB, OpSize;
1201 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1202 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1203 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1204 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1205 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1206 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1207 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1208 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1210 //===----------------------------------------------------------------------===//
1211 // SSE 1 & 2 - Shuffle Instructions
1212 //===----------------------------------------------------------------------===//
1214 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1215 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1216 ValueType vt, string asm, PatFrag mem_frag,
1217 Domain d, bit IsConvertibleToThreeAddress = 0> {
1218 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1219 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1220 [(set RC:$dst, (vt (shufp:$src3
1221 RC:$src1, (mem_frag addr:$src2))))], d>;
1222 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1223 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1224 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1226 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1229 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1230 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1231 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1232 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1233 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1234 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1235 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1236 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1237 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1238 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1239 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1240 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1242 let Constraints = "$src1 = $dst" in {
1243 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1244 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1245 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1247 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1248 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1249 memopv2f64, SSEPackedDouble>, TB, OpSize;
1252 //===----------------------------------------------------------------------===//
1253 // SSE 1 & 2 - Unpack Instructions
1254 //===----------------------------------------------------------------------===//
1256 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1257 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1258 PatFrag mem_frag, RegisterClass RC,
1259 X86MemOperand x86memop, string asm,
1261 def rr : PI<opc, MRMSrcReg,
1262 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1264 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1265 def rm : PI<opc, MRMSrcMem,
1266 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1268 (vt (OpNode RC:$src1,
1269 (mem_frag addr:$src2))))], d>;
1272 let AddedComplexity = 10 in {
1273 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1274 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1275 SSEPackedSingle>, VEX_4V;
1276 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1277 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1278 SSEPackedDouble>, OpSize, VEX_4V;
1279 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1280 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1281 SSEPackedSingle>, VEX_4V;
1282 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1283 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1284 SSEPackedDouble>, OpSize, VEX_4V;
1286 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1287 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1288 SSEPackedSingle>, VEX_4V;
1289 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1290 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1291 SSEPackedDouble>, OpSize, VEX_4V;
1292 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1293 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1294 SSEPackedSingle>, VEX_4V;
1295 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1296 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1297 SSEPackedDouble>, OpSize, VEX_4V;
1299 let Constraints = "$src1 = $dst" in {
1300 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1301 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1302 SSEPackedSingle>, TB;
1303 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1304 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1305 SSEPackedDouble>, TB, OpSize;
1306 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1307 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1308 SSEPackedSingle>, TB;
1309 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1310 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1311 SSEPackedDouble>, TB, OpSize;
1312 } // Constraints = "$src1 = $dst"
1313 } // AddedComplexity
1315 //===----------------------------------------------------------------------===//
1316 // SSE 1 & 2 - Extract Floating-Point Sign mask
1317 //===----------------------------------------------------------------------===//
1319 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1320 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1322 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1323 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1324 [(set GR32:$dst, (Int RC:$src))], d>;
1325 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1326 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1330 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1331 SSEPackedSingle>, TB;
1332 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1333 SSEPackedDouble>, TB, OpSize;
1335 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1336 "movmskps", SSEPackedSingle>, VEX;
1337 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1338 "movmskpd", SSEPackedDouble>, OpSize,
1340 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1341 "movmskps", SSEPackedSingle>, VEX;
1342 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1343 "movmskpd", SSEPackedDouble>, OpSize,
1347 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1348 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1349 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1350 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1352 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1353 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1354 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1355 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1358 //===----------------------------------------------------------------------===//
1359 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1360 //===----------------------------------------------------------------------===//
1362 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1363 // names that start with 'Fs'.
1365 // Alias instructions that map fld0 to pxor for sse.
1366 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1367 canFoldAsLoad = 1 in {
1368 // FIXME: Set encoding to pseudo!
1369 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1370 [(set FR32:$dst, fp32imm0)]>,
1371 Requires<[HasSSE1]>, TB, OpSize;
1372 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1373 [(set FR64:$dst, fpimm0)]>,
1374 Requires<[HasSSE2]>, TB, OpSize;
1375 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1376 [(set FR32:$dst, fp32imm0)]>,
1377 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1378 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1379 [(set FR64:$dst, fpimm0)]>,
1380 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1383 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1384 // bits are disregarded.
1385 let neverHasSideEffects = 1 in {
1386 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1387 "movaps\t{$src, $dst|$dst, $src}", []>;
1388 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1389 "movapd\t{$src, $dst|$dst, $src}", []>;
1392 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1393 // bits are disregarded.
1394 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1395 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1396 "movaps\t{$src, $dst|$dst, $src}",
1397 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1398 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1399 "movapd\t{$src, $dst|$dst, $src}",
1400 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1403 //===----------------------------------------------------------------------===//
1404 // SSE 1 & 2 - Logical Instructions
1405 //===----------------------------------------------------------------------===//
1407 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1409 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1411 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1412 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1414 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1415 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1417 let Constraints = "$src1 = $dst" in {
1418 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1419 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1421 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1422 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1426 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1427 let mayLoad = 0 in {
1428 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1429 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1430 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1433 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1434 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1436 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1438 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1439 SDNode OpNode, int HasPat = 0,
1440 list<list<dag>> Pattern = []> {
1441 let Pattern = []<dag> in {
1442 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1443 !strconcat(OpcodeStr, "ps"), f128mem,
1444 !if(HasPat, Pattern[0], // rr
1445 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1447 !if(HasPat, Pattern[2], // rm
1448 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1449 (memopv2i64 addr:$src2)))]), 0>,
1452 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1453 !strconcat(OpcodeStr, "pd"), f128mem,
1454 !if(HasPat, Pattern[1], // rr
1455 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1458 !if(HasPat, Pattern[3], // rm
1459 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1460 (memopv2i64 addr:$src2)))]), 0>,
1463 let Constraints = "$src1 = $dst" in {
1464 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1465 !strconcat(OpcodeStr, "ps"), f128mem,
1466 !if(HasPat, Pattern[0], // rr
1467 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1469 !if(HasPat, Pattern[2], // rm
1470 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1471 (memopv2i64 addr:$src2)))])>, TB;
1473 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1474 !strconcat(OpcodeStr, "pd"), f128mem,
1475 !if(HasPat, Pattern[1], // rr
1476 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1479 !if(HasPat, Pattern[3], // rm
1480 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1481 (memopv2i64 addr:$src2)))])>,
1486 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1488 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1489 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1490 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1492 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1493 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1496 // AVX 256-bit packed logical ops forms
1497 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1498 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1499 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1500 let isCommutable = 0 in
1501 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1503 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1504 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1505 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1506 let isCommutable = 0 in
1507 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1509 [(set VR128:$dst, (X86pandn VR128:$src1, VR128:$src2))],
1513 [(set VR128:$dst, (X86pandn VR128:$src1, (memopv2i64 addr:$src2)))],
1517 //===----------------------------------------------------------------------===//
1518 // SSE 1 & 2 - Arithmetic Instructions
1519 //===----------------------------------------------------------------------===//
1521 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1524 /// In addition, we also have a special variant of the scalar form here to
1525 /// represent the associated intrinsic operation. This form is unlike the
1526 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1527 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1529 /// These three forms can each be reg+reg or reg+mem.
1532 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1534 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1536 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1537 OpNode, FR32, f32mem, Is2Addr>, XS;
1538 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1539 OpNode, FR64, f64mem, Is2Addr>, XD;
1542 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1544 let mayLoad = 0 in {
1545 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1546 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1547 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1548 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1552 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1554 let mayLoad = 0 in {
1555 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1556 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1557 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1558 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1562 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1564 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1565 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1566 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1567 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1570 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1572 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1573 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1574 SSEPackedSingle, Is2Addr>, TB;
1576 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1577 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1578 SSEPackedDouble, Is2Addr>, TB, OpSize;
1581 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1582 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1583 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1584 SSEPackedSingle, 0>, TB;
1586 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1587 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1588 SSEPackedDouble, 0>, TB, OpSize;
1591 // Binary Arithmetic instructions
1592 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1593 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1594 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1595 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1596 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1597 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1598 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1599 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1601 let isCommutable = 0 in {
1602 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1603 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1604 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1605 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1606 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1607 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1608 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1609 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1610 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1611 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1612 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1613 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1614 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1615 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1616 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1617 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1618 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1619 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1620 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1621 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1624 let Constraints = "$src1 = $dst" in {
1625 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1626 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1627 basic_sse12_fp_binop_s_int<0x58, "add">;
1628 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1629 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1630 basic_sse12_fp_binop_s_int<0x59, "mul">;
1632 let isCommutable = 0 in {
1633 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1634 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1635 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1636 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1637 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1638 basic_sse12_fp_binop_s_int<0x5E, "div">;
1639 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1640 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1641 basic_sse12_fp_binop_s_int<0x5F, "max">,
1642 basic_sse12_fp_binop_p_int<0x5F, "max">;
1643 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1644 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1645 basic_sse12_fp_binop_s_int<0x5D, "min">,
1646 basic_sse12_fp_binop_p_int<0x5D, "min">;
1651 /// In addition, we also have a special variant of the scalar form here to
1652 /// represent the associated intrinsic operation. This form is unlike the
1653 /// plain scalar form, in that it takes an entire vector (instead of a
1654 /// scalar) and leaves the top elements undefined.
1656 /// And, we have a special variant form for a full-vector intrinsic form.
1658 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1659 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1660 SDNode OpNode, Intrinsic F32Int> {
1661 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1662 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1663 [(set FR32:$dst, (OpNode FR32:$src))]>;
1664 // For scalar unary operations, fold a load into the operation
1665 // only in OptForSize mode. It eliminates an instruction, but it also
1666 // eliminates a whole-register clobber (the load), so it introduces a
1667 // partial register update condition.
1668 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1669 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1670 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1671 Requires<[HasSSE1, OptForSize]>;
1672 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1673 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1674 [(set VR128:$dst, (F32Int VR128:$src))]>;
1675 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1676 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1677 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1680 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1681 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1682 SDNode OpNode, Intrinsic F32Int> {
1683 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1684 !strconcat(OpcodeStr,
1685 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1686 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1687 !strconcat(OpcodeStr,
1688 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1689 []>, XS, Requires<[HasAVX, OptForSize]>;
1690 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1691 !strconcat(OpcodeStr,
1692 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1693 [(set VR128:$dst, (F32Int VR128:$src))]>;
1694 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1695 !strconcat(OpcodeStr,
1696 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1697 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1700 /// sse1_fp_unop_p - SSE1 unops in packed form.
1701 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1702 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1703 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1704 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1705 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1706 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1707 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1710 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1711 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1712 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1713 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1714 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1715 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1716 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1717 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1720 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1721 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1722 Intrinsic V4F32Int> {
1723 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1724 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1725 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1726 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1727 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1728 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1731 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1732 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1733 Intrinsic V4F32Int> {
1734 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1735 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1736 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1737 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1738 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1739 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1742 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1743 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1744 SDNode OpNode, Intrinsic F64Int> {
1745 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1746 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1747 [(set FR64:$dst, (OpNode FR64:$src))]>;
1748 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1749 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1750 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1751 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1752 Requires<[HasSSE2, OptForSize]>;
1753 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1754 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1755 [(set VR128:$dst, (F64Int VR128:$src))]>;
1756 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1757 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1758 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1761 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1762 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1763 SDNode OpNode, Intrinsic F64Int> {
1764 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1765 !strconcat(OpcodeStr,
1766 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1767 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1768 (ins FR64:$src1, f64mem:$src2),
1769 !strconcat(OpcodeStr,
1770 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1771 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1772 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1773 [(set VR128:$dst, (F64Int VR128:$src))]>;
1774 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1775 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1776 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1779 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1780 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1782 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1783 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1784 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1785 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1786 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1787 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1790 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1791 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1792 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1793 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1794 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1795 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1796 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1797 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1800 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1801 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1802 Intrinsic V2F64Int> {
1803 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1804 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1805 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1806 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1807 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1808 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1811 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1812 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1813 Intrinsic V2F64Int> {
1814 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1815 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1816 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1817 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1818 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1819 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1822 let Predicates = [HasAVX] in {
1824 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1825 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1828 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1829 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1830 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1831 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1832 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1833 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1834 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1835 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1838 // Reciprocal approximations. Note that these typically require refinement
1839 // in order to obtain suitable precision.
1840 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1841 int_x86_sse_rsqrt_ss>, VEX_4V;
1842 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1843 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1844 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1845 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1847 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1849 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1850 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1851 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1852 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1856 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1857 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1858 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1859 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1860 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1861 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1863 // Reciprocal approximations. Note that these typically require refinement
1864 // in order to obtain suitable precision.
1865 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1866 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1867 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1868 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1869 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1870 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1872 // There is no f64 version of the reciprocal approximation instructions.
1874 //===----------------------------------------------------------------------===//
1875 // SSE 1 & 2 - Non-temporal stores
1876 //===----------------------------------------------------------------------===//
1878 let AddedComplexity = 400 in { // Prefer non-temporal versions
1879 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1880 (ins f128mem:$dst, VR128:$src),
1881 "movntps\t{$src, $dst|$dst, $src}",
1882 [(alignednontemporalstore (v4f32 VR128:$src),
1884 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1885 (ins f128mem:$dst, VR128:$src),
1886 "movntpd\t{$src, $dst|$dst, $src}",
1887 [(alignednontemporalstore (v2f64 VR128:$src),
1889 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1890 (ins f128mem:$dst, VR128:$src),
1891 "movntdq\t{$src, $dst|$dst, $src}",
1892 [(alignednontemporalstore (v2f64 VR128:$src),
1895 let ExeDomain = SSEPackedInt in
1896 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1897 (ins f128mem:$dst, VR128:$src),
1898 "movntdq\t{$src, $dst|$dst, $src}",
1899 [(alignednontemporalstore (v4f32 VR128:$src),
1902 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1903 (VMOVNTDQmr addr:$dst, VR128:$src)>;
1905 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1906 (ins f256mem:$dst, VR256:$src),
1907 "movntps\t{$src, $dst|$dst, $src}",
1908 [(alignednontemporalstore (v8f32 VR256:$src),
1910 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1911 (ins f256mem:$dst, VR256:$src),
1912 "movntpd\t{$src, $dst|$dst, $src}",
1913 [(alignednontemporalstore (v4f64 VR256:$src),
1915 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1916 (ins f256mem:$dst, VR256:$src),
1917 "movntdq\t{$src, $dst|$dst, $src}",
1918 [(alignednontemporalstore (v4f64 VR256:$src),
1920 let ExeDomain = SSEPackedInt in
1921 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1922 (ins f256mem:$dst, VR256:$src),
1923 "movntdq\t{$src, $dst|$dst, $src}",
1924 [(alignednontemporalstore (v8f32 VR256:$src),
1928 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1929 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1930 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
1931 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
1932 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
1933 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
1935 let AddedComplexity = 400 in { // Prefer non-temporal versions
1936 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1937 "movntps\t{$src, $dst|$dst, $src}",
1938 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1939 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1940 "movntpd\t{$src, $dst|$dst, $src}",
1941 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
1943 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1944 "movntdq\t{$src, $dst|$dst, $src}",
1945 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1947 let ExeDomain = SSEPackedInt in
1948 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1949 "movntdq\t{$src, $dst|$dst, $src}",
1950 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1952 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1953 (MOVNTDQmr addr:$dst, VR128:$src)>;
1955 // There is no AVX form for instructions below this point
1956 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1957 "movnti\t{$src, $dst|$dst, $src}",
1958 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1959 TB, Requires<[HasSSE2]>;
1960 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1961 "movnti\t{$src, $dst|$dst, $src}",
1962 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1963 TB, Requires<[HasSSE2]>;
1966 //===----------------------------------------------------------------------===//
1967 // SSE 1 & 2 - Misc Instructions (No AVX form)
1968 //===----------------------------------------------------------------------===//
1970 // Prefetch intrinsic.
1971 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1972 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1973 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1974 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1975 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1976 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1977 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1978 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1980 // Load, store, and memory fence
1981 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1982 TB, Requires<[HasSSE1]>;
1983 def : Pat<(X86SFence), (SFENCE)>;
1985 // Alias instructions that map zero vector to pxor / xorp* for sse.
1986 // We set canFoldAsLoad because this can be converted to a constant-pool
1987 // load of an all-zeros value if folding it would be beneficial.
1988 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
1989 // JIT implementation, it does not expand the instructions below like
1990 // X86MCInstLower does.
1991 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1992 isCodeGenOnly = 1 in {
1993 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1994 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1995 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1996 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1997 let ExeDomain = SSEPackedInt in
1998 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1999 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2002 // The same as done above but for AVX. The 128-bit versions are the
2003 // same, but re-encoded. The 256-bit does not support PI version.
2004 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2005 // JIT implementatioan, it does not expand the instructions below like
2006 // X86MCInstLower does.
2007 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2008 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2009 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2010 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2011 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2012 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2013 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2014 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2015 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2016 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2017 let ExeDomain = SSEPackedInt in
2018 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2019 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2022 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2023 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2024 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2026 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2027 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2029 //===----------------------------------------------------------------------===//
2030 // SSE 1 & 2 - Load/Store XCSR register
2031 //===----------------------------------------------------------------------===//
2033 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2034 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2035 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2036 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2038 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2039 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2040 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2041 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2043 //===---------------------------------------------------------------------===//
2044 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2045 //===---------------------------------------------------------------------===//
2047 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2049 let neverHasSideEffects = 1 in {
2050 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2051 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2052 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2053 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2055 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2056 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2057 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2058 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2060 let canFoldAsLoad = 1, mayLoad = 1 in {
2061 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2062 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2063 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2064 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2065 let Predicates = [HasAVX] in {
2066 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2067 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2068 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2069 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2073 let mayStore = 1 in {
2074 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2075 (ins i128mem:$dst, VR128:$src),
2076 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2077 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2078 (ins i256mem:$dst, VR256:$src),
2079 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2080 let Predicates = [HasAVX] in {
2081 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2082 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2083 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2084 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2088 let neverHasSideEffects = 1 in
2089 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2090 "movdqa\t{$src, $dst|$dst, $src}", []>;
2092 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2093 "movdqu\t{$src, $dst|$dst, $src}",
2094 []>, XS, Requires<[HasSSE2]>;
2096 let canFoldAsLoad = 1, mayLoad = 1 in {
2097 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2098 "movdqa\t{$src, $dst|$dst, $src}",
2099 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2100 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2101 "movdqu\t{$src, $dst|$dst, $src}",
2102 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2103 XS, Requires<[HasSSE2]>;
2106 let mayStore = 1 in {
2107 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2108 "movdqa\t{$src, $dst|$dst, $src}",
2109 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2110 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2111 "movdqu\t{$src, $dst|$dst, $src}",
2112 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2113 XS, Requires<[HasSSE2]>;
2116 // Intrinsic forms of MOVDQU load and store
2117 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2118 "vmovdqu\t{$src, $dst|$dst, $src}",
2119 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2120 XS, VEX, Requires<[HasAVX]>;
2122 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2123 "movdqu\t{$src, $dst|$dst, $src}",
2124 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2125 XS, Requires<[HasSSE2]>;
2127 } // ExeDomain = SSEPackedInt
2129 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2130 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2131 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2133 //===---------------------------------------------------------------------===//
2134 // SSE2 - Packed Integer Arithmetic Instructions
2135 //===---------------------------------------------------------------------===//
2137 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2139 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2140 bit IsCommutable = 0, bit Is2Addr = 1> {
2141 let isCommutable = IsCommutable in
2142 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2143 (ins VR128:$src1, VR128:$src2),
2145 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2146 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2147 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2148 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2149 (ins VR128:$src1, i128mem:$src2),
2151 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2152 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2153 [(set VR128:$dst, (IntId VR128:$src1,
2154 (bitconvert (memopv2i64 addr:$src2))))]>;
2157 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2158 string OpcodeStr, Intrinsic IntId,
2159 Intrinsic IntId2, bit Is2Addr = 1> {
2160 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2161 (ins VR128:$src1, VR128:$src2),
2163 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2164 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2165 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2166 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2167 (ins VR128:$src1, i128mem:$src2),
2169 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2170 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2171 [(set VR128:$dst, (IntId VR128:$src1,
2172 (bitconvert (memopv2i64 addr:$src2))))]>;
2173 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2174 (ins VR128:$src1, i32i8imm:$src2),
2176 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2177 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2178 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2181 /// PDI_binop_rm - Simple SSE2 binary operator.
2182 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2183 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2184 let isCommutable = IsCommutable in
2185 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2186 (ins VR128:$src1, VR128:$src2),
2188 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2189 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2190 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2191 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2192 (ins VR128:$src1, i128mem:$src2),
2194 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2195 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2196 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2197 (bitconvert (memopv2i64 addr:$src2)))))]>;
2200 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2202 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2203 /// to collapse (bitconvert VT to VT) into its operand.
2205 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2206 bit IsCommutable = 0, bit Is2Addr = 1> {
2207 let isCommutable = IsCommutable in
2208 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2209 (ins VR128:$src1, VR128:$src2),
2211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2213 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2214 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2215 (ins VR128:$src1, i128mem:$src2),
2217 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2218 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2219 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2222 } // ExeDomain = SSEPackedInt
2224 // 128-bit Integer Arithmetic
2226 let Predicates = [HasAVX] in {
2227 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2228 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2229 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2230 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2231 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2232 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2233 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2234 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2235 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2238 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2240 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2242 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2244 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2246 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2248 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2250 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2252 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2254 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2256 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2258 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2260 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2262 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2264 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2266 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2268 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2270 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2272 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2274 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2278 let Constraints = "$src1 = $dst" in {
2279 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2280 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2281 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2282 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2283 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2284 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2285 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2286 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2287 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2290 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2291 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2292 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2293 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2294 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2295 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2296 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2297 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2298 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2299 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2300 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2301 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2302 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2303 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2304 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2305 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2306 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2307 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2308 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2310 } // Constraints = "$src1 = $dst"
2312 //===---------------------------------------------------------------------===//
2313 // SSE2 - Packed Integer Logical Instructions
2314 //===---------------------------------------------------------------------===//
2316 let Predicates = [HasAVX] in {
2317 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2318 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2320 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2321 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2323 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2324 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2327 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2328 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2330 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2331 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2333 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2334 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2337 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2338 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2340 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2341 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2344 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2345 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2346 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2348 let ExeDomain = SSEPackedInt in {
2349 let neverHasSideEffects = 1 in {
2350 // 128-bit logical shifts.
2351 def VPSLLDQri : PDIi8<0x73, MRM7r,
2352 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2353 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2355 def VPSRLDQri : PDIi8<0x73, MRM3r,
2356 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2357 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2359 // PSRADQri doesn't exist in SSE[1-3].
2361 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2362 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2363 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2364 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2365 VR128:$src2)))]>, VEX_4V;
2367 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2368 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2369 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2370 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2371 (memopv2i64 addr:$src2))))]>,
2376 let Constraints = "$src1 = $dst" in {
2377 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2378 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2379 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2380 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2381 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2382 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2384 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2385 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2386 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2387 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2388 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2389 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2391 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2392 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2393 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2394 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2396 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2397 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2398 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2400 let ExeDomain = SSEPackedInt in {
2401 let neverHasSideEffects = 1 in {
2402 // 128-bit logical shifts.
2403 def PSLLDQri : PDIi8<0x73, MRM7r,
2404 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2405 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2406 def PSRLDQri : PDIi8<0x73, MRM3r,
2407 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2408 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2409 // PSRADQri doesn't exist in SSE[1-3].
2411 def PANDNrr : PDI<0xDF, MRMSrcReg,
2412 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2413 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2415 def PANDNrm : PDI<0xDF, MRMSrcMem,
2416 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2417 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2419 } // Constraints = "$src1 = $dst"
2421 let Predicates = [HasAVX] in {
2422 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2423 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2424 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2425 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2426 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2427 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2428 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2429 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2430 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2431 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2433 // Shift up / down and insert zero's.
2434 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2435 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2436 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2437 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2440 let Predicates = [HasSSE2] in {
2441 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2442 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2443 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2444 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2445 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2446 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2447 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2448 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2449 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2450 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2452 // Shift up / down and insert zero's.
2453 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2454 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2455 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2456 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2459 //===---------------------------------------------------------------------===//
2460 // SSE2 - Packed Integer Comparison Instructions
2461 //===---------------------------------------------------------------------===//
2463 let Predicates = [HasAVX] in {
2464 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2466 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2468 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2470 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2472 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2474 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2478 let Constraints = "$src1 = $dst" in {
2479 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2480 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2481 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2482 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2483 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2484 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2485 } // Constraints = "$src1 = $dst"
2487 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2488 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2489 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2490 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2491 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2492 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2493 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2494 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2495 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2496 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2497 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2498 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2500 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2501 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2502 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2503 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2504 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2505 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2506 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2507 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2508 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2509 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2510 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2511 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2513 //===---------------------------------------------------------------------===//
2514 // SSE2 - Packed Integer Pack Instructions
2515 //===---------------------------------------------------------------------===//
2517 let Predicates = [HasAVX] in {
2518 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2520 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2522 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2526 let Constraints = "$src1 = $dst" in {
2527 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2528 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2529 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2530 } // Constraints = "$src1 = $dst"
2532 //===---------------------------------------------------------------------===//
2533 // SSE2 - Packed Integer Shuffle Instructions
2534 //===---------------------------------------------------------------------===//
2536 let ExeDomain = SSEPackedInt in {
2537 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2539 def ri : Ii8<0x70, MRMSrcReg,
2540 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2541 !strconcat(OpcodeStr,
2542 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2543 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2545 def mi : Ii8<0x70, MRMSrcMem,
2546 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2547 !strconcat(OpcodeStr,
2548 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2549 [(set VR128:$dst, (vt (pshuf_frag:$src2
2550 (bc_frag (memopv2i64 addr:$src1)),
2553 } // ExeDomain = SSEPackedInt
2555 let Predicates = [HasAVX] in {
2556 let AddedComplexity = 5 in
2557 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2560 // SSE2 with ImmT == Imm8 and XS prefix.
2561 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2564 // SSE2 with ImmT == Imm8 and XD prefix.
2565 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2569 let Predicates = [HasSSE2] in {
2570 let AddedComplexity = 5 in
2571 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2573 // SSE2 with ImmT == Imm8 and XS prefix.
2574 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2576 // SSE2 with ImmT == Imm8 and XD prefix.
2577 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2580 //===---------------------------------------------------------------------===//
2581 // SSE2 - Packed Integer Unpack Instructions
2582 //===---------------------------------------------------------------------===//
2584 let ExeDomain = SSEPackedInt in {
2585 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2586 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2587 def rr : PDI<opc, MRMSrcReg,
2588 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2590 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2591 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2592 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2593 def rm : PDI<opc, MRMSrcMem,
2594 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2596 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2597 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2598 [(set VR128:$dst, (unp_frag VR128:$src1,
2599 (bc_frag (memopv2i64
2603 let Predicates = [HasAVX] in {
2604 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2606 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2608 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2611 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2612 /// knew to collapse (bitconvert VT to VT) into its operand.
2613 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2614 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2615 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2617 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2618 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2619 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2620 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2622 (v2i64 (unpckl VR128:$src1,
2623 (memopv2i64 addr:$src2))))]>, VEX_4V;
2625 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2627 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2629 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2632 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2633 /// knew to collapse (bitconvert VT to VT) into its operand.
2634 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2635 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2636 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2638 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2639 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2640 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2641 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2643 (v2i64 (unpckh VR128:$src1,
2644 (memopv2i64 addr:$src2))))]>, VEX_4V;
2647 let Constraints = "$src1 = $dst" in {
2648 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2649 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2650 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2652 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2653 /// knew to collapse (bitconvert VT to VT) into its operand.
2654 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2655 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2656 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2658 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2659 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2660 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2661 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2663 (v2i64 (unpckl VR128:$src1,
2664 (memopv2i64 addr:$src2))))]>;
2666 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2667 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2668 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2670 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2671 /// knew to collapse (bitconvert VT to VT) into its operand.
2672 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2673 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2674 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2676 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2677 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2678 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2679 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2681 (v2i64 (unpckh VR128:$src1,
2682 (memopv2i64 addr:$src2))))]>;
2685 } // ExeDomain = SSEPackedInt
2687 //===---------------------------------------------------------------------===//
2688 // SSE2 - Packed Integer Extract and Insert
2689 //===---------------------------------------------------------------------===//
2691 let ExeDomain = SSEPackedInt in {
2692 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2693 def rri : Ii8<0xC4, MRMSrcReg,
2694 (outs VR128:$dst), (ins VR128:$src1,
2695 GR32:$src2, i32i8imm:$src3),
2697 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2698 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2700 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2701 def rmi : Ii8<0xC4, MRMSrcMem,
2702 (outs VR128:$dst), (ins VR128:$src1,
2703 i16mem:$src2, i32i8imm:$src3),
2705 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2706 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2708 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2713 let Predicates = [HasAVX] in
2714 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2715 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2716 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2717 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2718 imm:$src2))]>, OpSize, VEX;
2719 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2720 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2721 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2722 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2726 let Predicates = [HasAVX] in {
2727 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2728 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2729 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2730 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2731 []>, OpSize, VEX_4V;
2734 let Constraints = "$src1 = $dst" in
2735 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2737 } // ExeDomain = SSEPackedInt
2739 //===---------------------------------------------------------------------===//
2740 // SSE2 - Packed Mask Creation
2741 //===---------------------------------------------------------------------===//
2743 let ExeDomain = SSEPackedInt in {
2745 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2746 "pmovmskb\t{$src, $dst|$dst, $src}",
2747 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2748 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2749 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2750 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2751 "pmovmskb\t{$src, $dst|$dst, $src}",
2752 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2754 } // ExeDomain = SSEPackedInt
2756 //===---------------------------------------------------------------------===//
2757 // SSE2 - Conditional Store
2758 //===---------------------------------------------------------------------===//
2760 let ExeDomain = SSEPackedInt in {
2763 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2764 (ins VR128:$src, VR128:$mask),
2765 "maskmovdqu\t{$mask, $src|$src, $mask}",
2766 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2768 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2769 (ins VR128:$src, VR128:$mask),
2770 "maskmovdqu\t{$mask, $src|$src, $mask}",
2771 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2774 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2775 "maskmovdqu\t{$mask, $src|$src, $mask}",
2776 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2778 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2779 "maskmovdqu\t{$mask, $src|$src, $mask}",
2780 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2782 } // ExeDomain = SSEPackedInt
2784 //===---------------------------------------------------------------------===//
2785 // SSE2 - Move Doubleword
2786 //===---------------------------------------------------------------------===//
2788 // Move Int Doubleword to Packed Double Int
2789 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2790 "movd\t{$src, $dst|$dst, $src}",
2792 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2793 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2794 "movd\t{$src, $dst|$dst, $src}",
2796 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2798 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2799 "movd\t{$src, $dst|$dst, $src}",
2801 (v4i32 (scalar_to_vector GR32:$src)))]>;
2802 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2803 "movd\t{$src, $dst|$dst, $src}",
2805 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2806 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2807 "mov{d|q}\t{$src, $dst|$dst, $src}",
2809 (v2i64 (scalar_to_vector GR64:$src)))]>;
2810 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2811 "mov{d|q}\t{$src, $dst|$dst, $src}",
2812 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2815 // Move Int Doubleword to Single Scalar
2816 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2817 "movd\t{$src, $dst|$dst, $src}",
2818 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2820 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2821 "movd\t{$src, $dst|$dst, $src}",
2822 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2824 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2825 "movd\t{$src, $dst|$dst, $src}",
2826 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2828 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2829 "movd\t{$src, $dst|$dst, $src}",
2830 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2832 // Move Packed Doubleword Int to Packed Double Int
2833 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2834 "movd\t{$src, $dst|$dst, $src}",
2835 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2837 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2838 (ins i32mem:$dst, VR128:$src),
2839 "movd\t{$src, $dst|$dst, $src}",
2840 [(store (i32 (vector_extract (v4i32 VR128:$src),
2841 (iPTR 0))), addr:$dst)]>, VEX;
2842 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2843 "movd\t{$src, $dst|$dst, $src}",
2844 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2846 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2847 "movd\t{$src, $dst|$dst, $src}",
2848 [(store (i32 (vector_extract (v4i32 VR128:$src),
2849 (iPTR 0))), addr:$dst)]>;
2851 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2852 "mov{d|q}\t{$src, $dst|$dst, $src}",
2853 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2855 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2856 "movq\t{$src, $dst|$dst, $src}",
2857 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2859 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2860 "mov{d|q}\t{$src, $dst|$dst, $src}",
2861 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2862 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2863 "movq\t{$src, $dst|$dst, $src}",
2864 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2866 // Move Scalar Single to Double Int
2867 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2868 "movd\t{$src, $dst|$dst, $src}",
2869 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2870 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2871 "movd\t{$src, $dst|$dst, $src}",
2872 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2873 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2874 "movd\t{$src, $dst|$dst, $src}",
2875 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2876 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2877 "movd\t{$src, $dst|$dst, $src}",
2878 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2880 // movd / movq to XMM register zero-extends
2881 let AddedComplexity = 15 in {
2882 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2883 "movd\t{$src, $dst|$dst, $src}",
2884 [(set VR128:$dst, (v4i32 (X86vzmovl
2885 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2887 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2888 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2889 [(set VR128:$dst, (v2i64 (X86vzmovl
2890 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2893 let AddedComplexity = 15 in {
2894 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2895 "movd\t{$src, $dst|$dst, $src}",
2896 [(set VR128:$dst, (v4i32 (X86vzmovl
2897 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2898 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2899 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2900 [(set VR128:$dst, (v2i64 (X86vzmovl
2901 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2904 let AddedComplexity = 20 in {
2905 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2906 "movd\t{$src, $dst|$dst, $src}",
2908 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2909 (loadi32 addr:$src))))))]>,
2911 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2912 "movd\t{$src, $dst|$dst, $src}",
2914 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2915 (loadi32 addr:$src))))))]>;
2917 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2918 (MOVZDI2PDIrm addr:$src)>;
2919 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2920 (MOVZDI2PDIrm addr:$src)>;
2921 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2922 (MOVZDI2PDIrm addr:$src)>;
2925 //===---------------------------------------------------------------------===//
2926 // SSE2 - Move Quadword
2927 //===---------------------------------------------------------------------===//
2929 // Move Quadword Int to Packed Quadword Int
2930 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2931 "vmovq\t{$src, $dst|$dst, $src}",
2933 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2934 VEX, Requires<[HasAVX]>;
2935 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2936 "movq\t{$src, $dst|$dst, $src}",
2938 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2939 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
2941 // Move Packed Quadword Int to Quadword Int
2942 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2943 "movq\t{$src, $dst|$dst, $src}",
2944 [(store (i64 (vector_extract (v2i64 VR128:$src),
2945 (iPTR 0))), addr:$dst)]>, VEX;
2946 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2947 "movq\t{$src, $dst|$dst, $src}",
2948 [(store (i64 (vector_extract (v2i64 VR128:$src),
2949 (iPTR 0))), addr:$dst)]>;
2951 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2952 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2954 // Store / copy lower 64-bits of a XMM register.
2955 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2956 "movq\t{$src, $dst|$dst, $src}",
2957 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
2958 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2959 "movq\t{$src, $dst|$dst, $src}",
2960 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2962 let AddedComplexity = 20 in
2963 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2964 "vmovq\t{$src, $dst|$dst, $src}",
2966 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2967 (loadi64 addr:$src))))))]>,
2968 XS, VEX, Requires<[HasAVX]>;
2970 let AddedComplexity = 20 in {
2971 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2972 "movq\t{$src, $dst|$dst, $src}",
2974 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2975 (loadi64 addr:$src))))))]>,
2976 XS, Requires<[HasSSE2]>;
2978 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2979 (MOVZQI2PQIrm addr:$src)>;
2980 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2981 (MOVZQI2PQIrm addr:$src)>;
2982 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2985 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2986 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2987 let AddedComplexity = 15 in
2988 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2989 "vmovq\t{$src, $dst|$dst, $src}",
2990 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2991 XS, VEX, Requires<[HasAVX]>;
2992 let AddedComplexity = 15 in
2993 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2994 "movq\t{$src, $dst|$dst, $src}",
2995 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2996 XS, Requires<[HasSSE2]>;
2998 let AddedComplexity = 20 in
2999 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3000 "vmovq\t{$src, $dst|$dst, $src}",
3001 [(set VR128:$dst, (v2i64 (X86vzmovl
3002 (loadv2i64 addr:$src))))]>,
3003 XS, VEX, Requires<[HasAVX]>;
3004 let AddedComplexity = 20 in {
3005 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3006 "movq\t{$src, $dst|$dst, $src}",
3007 [(set VR128:$dst, (v2i64 (X86vzmovl
3008 (loadv2i64 addr:$src))))]>,
3009 XS, Requires<[HasSSE2]>;
3011 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3012 (MOVZPQILo2PQIrm addr:$src)>;
3015 // Instructions to match in the assembler
3016 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3017 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3018 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3019 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3020 // Recognize "movd" with GR64 destination, but encode as a "movq"
3021 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3022 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3024 // Instructions for the disassembler
3025 // xr = XMM register
3028 let Predicates = [HasAVX] in
3029 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3030 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3031 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3032 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3034 //===---------------------------------------------------------------------===//
3035 // SSE2 - Misc Instructions
3036 //===---------------------------------------------------------------------===//
3039 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3040 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3041 TB, Requires<[HasSSE2]>;
3043 // Load, store, and memory fence
3044 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3045 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3046 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3047 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3048 def : Pat<(X86LFence), (LFENCE)>;
3049 def : Pat<(X86MFence), (MFENCE)>;
3052 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3053 // was introduced with SSE2, it's backward compatible.
3054 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3056 // Alias instructions that map zero vector to pxor / xorp* for sse.
3057 // We set canFoldAsLoad because this can be converted to a constant-pool
3058 // load of an all-ones value if folding it would be beneficial.
3059 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3060 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3061 // FIXME: Change encoding to pseudo.
3062 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3063 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3065 //===---------------------------------------------------------------------===//
3066 // SSE3 - Conversion Instructions
3067 //===---------------------------------------------------------------------===//
3069 // Convert Packed Double FP to Packed DW Integers
3070 let Predicates = [HasAVX] in {
3071 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3072 // register, but the same isn't true when using memory operands instead.
3073 // Provide other assembly rr and rm forms to address this explicitly.
3074 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3075 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3076 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3077 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3080 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3081 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3082 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3083 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3086 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3087 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3088 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3089 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3092 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3093 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3094 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3095 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3097 // Convert Packed DW Integers to Packed Double FP
3098 let Predicates = [HasAVX] in {
3099 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3100 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3101 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3102 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3103 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3104 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3105 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3106 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3109 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3110 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3111 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3112 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3114 // AVX 256-bit register conversion intrinsics
3115 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3116 (VCVTDQ2PDYrr VR128:$src)>;
3117 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3118 (VCVTDQ2PDYrm addr:$src)>;
3120 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3121 (VCVTPD2DQYrr VR256:$src)>;
3122 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3123 (VCVTPD2DQYrm addr:$src)>;
3125 //===---------------------------------------------------------------------===//
3126 // SSE3 - Move Instructions
3127 //===---------------------------------------------------------------------===//
3129 // Replicate Single FP
3130 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3131 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3132 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3133 [(set VR128:$dst, (v4f32 (rep_frag
3134 VR128:$src, (undef))))]>;
3135 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3136 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3137 [(set VR128:$dst, (rep_frag
3138 (memopv4f32 addr:$src), (undef)))]>;
3141 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3143 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3144 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3145 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3146 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3149 let Predicates = [HasAVX] in {
3150 // FIXME: Merge above classes when we have patterns for the ymm version
3151 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3152 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3153 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3154 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3156 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3157 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3159 // Replicate Double FP
3160 multiclass sse3_replicate_dfp<string OpcodeStr> {
3161 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3162 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3163 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3164 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3165 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3167 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3171 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3172 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3175 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3176 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3180 let Predicates = [HasAVX] in {
3181 // FIXME: Merge above classes when we have patterns for the ymm version
3182 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3183 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3185 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3187 // Move Unaligned Integer
3188 let Predicates = [HasAVX] in {
3189 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3190 "vlddqu\t{$src, $dst|$dst, $src}",
3191 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3192 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3193 "vlddqu\t{$src, $dst|$dst, $src}",
3194 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3196 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3197 "lddqu\t{$src, $dst|$dst, $src}",
3198 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3200 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3202 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3204 // Several Move patterns
3205 let AddedComplexity = 5 in {
3206 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3207 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3208 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3209 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3210 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3211 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3212 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3213 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3216 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3217 let AddedComplexity = 15 in
3218 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3219 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3220 let AddedComplexity = 20 in
3221 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3222 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3224 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3225 let AddedComplexity = 15 in
3226 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3227 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3228 let AddedComplexity = 20 in
3229 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3230 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3232 //===---------------------------------------------------------------------===//
3233 // SSE3 - Arithmetic
3234 //===---------------------------------------------------------------------===//
3236 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3237 X86MemOperand x86memop, bit Is2Addr = 1> {
3238 def rr : I<0xD0, MRMSrcReg,
3239 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3241 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3242 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3243 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3244 def rm : I<0xD0, MRMSrcMem,
3245 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3247 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3248 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3249 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3252 let Predicates = [HasAVX],
3253 ExeDomain = SSEPackedDouble in {
3254 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3255 f128mem, 0>, TB, XD, VEX_4V;
3256 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3257 f128mem, 0>, TB, OpSize, VEX_4V;
3258 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3259 f256mem, 0>, TB, XD, VEX_4V;
3260 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3261 f256mem, 0>, TB, OpSize, VEX_4V;
3263 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3264 ExeDomain = SSEPackedDouble in {
3265 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3267 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3268 f128mem>, TB, OpSize;
3271 //===---------------------------------------------------------------------===//
3272 // SSE3 Instructions
3273 //===---------------------------------------------------------------------===//
3276 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3277 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3278 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3282 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3284 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3286 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3287 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3288 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3290 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3291 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3292 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3296 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3298 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3302 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3305 let Predicates = [HasAVX] in {
3306 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3307 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3308 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3309 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3310 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3311 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3312 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3313 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3314 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3315 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3316 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3317 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3318 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3319 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3320 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3321 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3324 let Constraints = "$src1 = $dst" in {
3325 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3326 int_x86_sse3_hadd_ps>;
3327 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3328 int_x86_sse3_hadd_pd>;
3329 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3330 int_x86_sse3_hsub_ps>;
3331 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3332 int_x86_sse3_hsub_pd>;
3335 //===---------------------------------------------------------------------===//
3336 // SSSE3 - Packed Absolute Instructions
3337 //===---------------------------------------------------------------------===//
3340 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3341 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3342 PatFrag mem_frag128, Intrinsic IntId128> {
3343 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3346 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3349 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3351 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3354 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3357 let Predicates = [HasAVX] in {
3358 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3359 int_x86_ssse3_pabs_b_128>, VEX;
3360 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3361 int_x86_ssse3_pabs_w_128>, VEX;
3362 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3363 int_x86_ssse3_pabs_d_128>, VEX;
3366 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3367 int_x86_ssse3_pabs_b_128>;
3368 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3369 int_x86_ssse3_pabs_w_128>;
3370 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3371 int_x86_ssse3_pabs_d_128>;
3373 //===---------------------------------------------------------------------===//
3374 // SSSE3 - Packed Binary Operator Instructions
3375 //===---------------------------------------------------------------------===//
3377 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3378 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3379 PatFrag mem_frag128, Intrinsic IntId128,
3381 let isCommutable = 1 in
3382 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3383 (ins VR128:$src1, VR128:$src2),
3385 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3387 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3389 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3390 (ins VR128:$src1, i128mem:$src2),
3392 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3393 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3395 (IntId128 VR128:$src1,
3396 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3399 let Predicates = [HasAVX] in {
3400 let isCommutable = 0 in {
3401 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3402 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3403 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3404 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3405 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3406 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3407 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3408 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3409 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3410 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3411 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3412 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3413 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3414 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3415 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3416 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3417 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3418 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3419 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3420 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3421 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3422 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3424 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3425 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3428 // None of these have i8 immediate fields.
3429 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3430 let isCommutable = 0 in {
3431 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3432 int_x86_ssse3_phadd_w_128>;
3433 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3434 int_x86_ssse3_phadd_d_128>;
3435 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3436 int_x86_ssse3_phadd_sw_128>;
3437 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3438 int_x86_ssse3_phsub_w_128>;
3439 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3440 int_x86_ssse3_phsub_d_128>;
3441 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3442 int_x86_ssse3_phsub_sw_128>;
3443 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3444 int_x86_ssse3_pmadd_ub_sw_128>;
3445 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3446 int_x86_ssse3_pshuf_b_128>;
3447 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3448 int_x86_ssse3_psign_b_128>;
3449 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3450 int_x86_ssse3_psign_w_128>;
3451 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3452 int_x86_ssse3_psign_d_128>;
3454 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3455 int_x86_ssse3_pmul_hr_sw_128>;
3458 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3459 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3460 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3461 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3463 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3464 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3465 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3466 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3467 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3468 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3470 //===---------------------------------------------------------------------===//
3471 // SSSE3 - Packed Align Instruction Patterns
3472 //===---------------------------------------------------------------------===//
3474 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3475 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3476 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3478 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3480 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3482 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3483 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3485 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3487 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3491 let Predicates = [HasAVX] in
3492 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3493 let Constraints = "$src1 = $dst" in
3494 defm PALIGN : ssse3_palign<"palignr">;
3496 let AddedComplexity = 5 in {
3497 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3498 (PALIGNR128rr VR128:$src2, VR128:$src1,
3499 (SHUFFLE_get_palign_imm VR128:$src3))>,
3500 Requires<[HasSSSE3]>;
3501 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3502 (PALIGNR128rr VR128:$src2, VR128:$src1,
3503 (SHUFFLE_get_palign_imm VR128:$src3))>,
3504 Requires<[HasSSSE3]>;
3505 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3506 (PALIGNR128rr VR128:$src2, VR128:$src1,
3507 (SHUFFLE_get_palign_imm VR128:$src3))>,
3508 Requires<[HasSSSE3]>;
3509 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3510 (PALIGNR128rr VR128:$src2, VR128:$src1,
3511 (SHUFFLE_get_palign_imm VR128:$src3))>,
3512 Requires<[HasSSSE3]>;
3515 //===---------------------------------------------------------------------===//
3516 // SSSE3 Misc Instructions
3517 //===---------------------------------------------------------------------===//
3519 // Thread synchronization
3520 let usesCustomInserter = 1 in {
3521 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3522 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3523 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3524 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3527 let Uses = [EAX, ECX, EDX] in
3528 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3529 Requires<[HasSSE3]>;
3530 let Uses = [ECX, EAX] in
3531 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3532 Requires<[HasSSE3]>;
3534 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3535 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3537 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3538 Requires<[In32BitMode]>;
3539 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3540 Requires<[In64BitMode]>;
3542 //===---------------------------------------------------------------------===//
3543 // Non-Instruction Patterns
3544 //===---------------------------------------------------------------------===//
3546 // extload f32 -> f64. This matches load+fextend because we have a hack in
3547 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3549 // Since these loads aren't folded into the fextend, we have to match it
3551 let Predicates = [HasSSE2] in
3552 def : Pat<(fextend (loadf32 addr:$src)),
3553 (CVTSS2SDrm addr:$src)>;
3556 let Predicates = [HasXMMInt] in {
3557 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3558 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3559 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3560 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3561 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3562 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3563 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3564 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3565 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3566 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3567 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3568 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3569 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3570 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3571 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3572 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3573 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3574 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3575 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3576 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3577 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3578 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3579 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3580 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3581 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3582 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3583 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3584 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3585 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3586 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3589 let Predicates = [HasAVX] in {
3590 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3593 // Move scalar to XMM zero-extended
3594 // movd to XMM register zero-extends
3595 let AddedComplexity = 15 in {
3596 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3597 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3598 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3599 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3600 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3601 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3602 (MOVSSrr (v4f32 (V_SET0PS)),
3603 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3604 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3605 (MOVSSrr (v4i32 (V_SET0PI)),
3606 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3609 // Splat v2f64 / v2i64
3610 let AddedComplexity = 10 in {
3611 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3612 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3613 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3614 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3615 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3616 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3617 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3618 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3621 // Special unary SHUFPSrri case.
3622 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3623 (SHUFPSrri VR128:$src1, VR128:$src1,
3624 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3625 let AddedComplexity = 5 in
3626 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3627 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3628 Requires<[HasSSE2]>;
3629 // Special unary SHUFPDrri case.
3630 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3631 (SHUFPDrri VR128:$src1, VR128:$src1,
3632 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3633 Requires<[HasSSE2]>;
3634 // Special unary SHUFPDrri case.
3635 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3636 (SHUFPDrri VR128:$src1, VR128:$src1,
3637 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3638 Requires<[HasSSE2]>;
3639 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3640 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3641 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3642 Requires<[HasSSE2]>;
3644 // Special binary v4i32 shuffle cases with SHUFPS.
3645 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3646 (SHUFPSrri VR128:$src1, VR128:$src2,
3647 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3648 Requires<[HasSSE2]>;
3649 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3650 (SHUFPSrmi VR128:$src1, addr:$src2,
3651 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3652 Requires<[HasSSE2]>;
3653 // Special binary v2i64 shuffle cases using SHUFPDrri.
3654 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3655 (SHUFPDrri VR128:$src1, VR128:$src2,
3656 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3657 Requires<[HasSSE2]>;
3659 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3660 let AddedComplexity = 15 in {
3661 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3662 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3663 Requires<[OptForSpeed, HasSSE2]>;
3664 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3665 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3666 Requires<[OptForSpeed, HasSSE2]>;
3668 let AddedComplexity = 10 in {
3669 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3670 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3671 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3672 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3673 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3674 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3675 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3676 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3679 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3680 let AddedComplexity = 15 in {
3681 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3682 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3683 Requires<[OptForSpeed, HasSSE2]>;
3684 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3685 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3686 Requires<[OptForSpeed, HasSSE2]>;
3688 let AddedComplexity = 10 in {
3689 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3690 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3691 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3692 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3693 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3694 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3695 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3696 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3699 let AddedComplexity = 20 in {
3700 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3701 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3702 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3704 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3705 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3706 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3708 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3709 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3710 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3711 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3712 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3715 let AddedComplexity = 20 in {
3716 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3717 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3718 (MOVLPSrm VR128:$src1, addr:$src2)>;
3719 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3720 (MOVLPDrm VR128:$src1, addr:$src2)>;
3721 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3722 (MOVLPSrm VR128:$src1, addr:$src2)>;
3723 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3724 (MOVLPDrm VR128:$src1, addr:$src2)>;
3727 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3728 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3729 (MOVLPSmr addr:$src1, VR128:$src2)>;
3730 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3731 (MOVLPDmr addr:$src1, VR128:$src2)>;
3732 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3734 (MOVLPSmr addr:$src1, VR128:$src2)>;
3735 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3736 (MOVLPDmr addr:$src1, VR128:$src2)>;
3738 let AddedComplexity = 15 in {
3739 // Setting the lowest element in the vector.
3740 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3741 (MOVSSrr (v4i32 VR128:$src1),
3742 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3743 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3744 (MOVSDrr (v2i64 VR128:$src1),
3745 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3747 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3748 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3749 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3750 Requires<[HasSSE2]>;
3751 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3752 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3753 Requires<[HasSSE2]>;
3756 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3757 // fall back to this for SSE1)
3758 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3759 (SHUFPSrri VR128:$src2, VR128:$src1,
3760 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3762 // Set lowest element and zero upper elements.
3763 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3764 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3766 // vector -> vector casts
3767 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3768 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3769 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3770 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3772 // Use movaps / movups for SSE integer load / store (one byte shorter).
3773 let Predicates = [HasSSE1] in {
3774 def : Pat<(alignedloadv4i32 addr:$src),
3775 (MOVAPSrm addr:$src)>;
3776 def : Pat<(loadv4i32 addr:$src),
3777 (MOVUPSrm addr:$src)>;
3778 def : Pat<(alignedloadv2i64 addr:$src),
3779 (MOVAPSrm addr:$src)>;
3780 def : Pat<(loadv2i64 addr:$src),
3781 (MOVUPSrm addr:$src)>;
3783 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3784 (MOVAPSmr addr:$dst, VR128:$src)>;
3785 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3786 (MOVAPSmr addr:$dst, VR128:$src)>;
3787 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3788 (MOVAPSmr addr:$dst, VR128:$src)>;
3789 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3790 (MOVAPSmr addr:$dst, VR128:$src)>;
3791 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3792 (MOVUPSmr addr:$dst, VR128:$src)>;
3793 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3794 (MOVUPSmr addr:$dst, VR128:$src)>;
3795 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3796 (MOVUPSmr addr:$dst, VR128:$src)>;
3797 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3798 (MOVUPSmr addr:$dst, VR128:$src)>;
3801 // Use vmovaps/vmovups for AVX 128-bit integer load/store (one byte shorter).
3802 let Predicates = [HasAVX] in {
3803 def : Pat<(alignedloadv4i32 addr:$src),
3804 (VMOVAPSrm addr:$src)>;
3805 def : Pat<(loadv4i32 addr:$src),
3806 (VMOVUPSrm addr:$src)>;
3807 def : Pat<(alignedloadv2i64 addr:$src),
3808 (VMOVAPSrm addr:$src)>;
3809 def : Pat<(loadv2i64 addr:$src),
3810 (VMOVUPSrm addr:$src)>;
3812 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3813 (VMOVAPSmr addr:$dst, VR128:$src)>;
3814 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3815 (VMOVAPSmr addr:$dst, VR128:$src)>;
3816 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3817 (VMOVAPSmr addr:$dst, VR128:$src)>;
3818 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3819 (VMOVAPSmr addr:$dst, VR128:$src)>;
3820 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3821 (VMOVUPSmr addr:$dst, VR128:$src)>;
3822 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3823 (VMOVUPSmr addr:$dst, VR128:$src)>;
3824 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3825 (VMOVUPSmr addr:$dst, VR128:$src)>;
3826 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3827 (VMOVUPSmr addr:$dst, VR128:$src)>;
3830 //===----------------------------------------------------------------------===//
3831 // SSE4.1 - Packed Move with Sign/Zero Extend
3832 //===----------------------------------------------------------------------===//
3834 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3835 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3836 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3837 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3839 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3840 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3842 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3846 let Predicates = [HasAVX] in {
3847 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3849 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3851 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3853 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3855 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3857 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3861 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3862 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3863 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3864 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3865 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3866 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3868 // Common patterns involving scalar load.
3869 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3870 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3871 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3872 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3874 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3875 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3876 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3877 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3879 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3880 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3881 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3882 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3884 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3885 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3886 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3887 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3889 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3890 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3891 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3892 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3894 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3895 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3896 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3897 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3900 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3901 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3902 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3903 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3905 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3906 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3908 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3912 let Predicates = [HasAVX] in {
3913 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
3915 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
3917 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
3919 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
3923 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3924 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3925 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3926 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3928 // Common patterns involving scalar load
3929 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3930 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3931 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3932 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3934 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3935 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3936 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3937 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3940 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3941 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3942 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3943 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3945 // Expecting a i16 load any extended to i32 value.
3946 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3947 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3948 [(set VR128:$dst, (IntId (bitconvert
3949 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3953 let Predicates = [HasAVX] in {
3954 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
3956 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
3959 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3960 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3962 // Common patterns involving scalar load
3963 def : Pat<(int_x86_sse41_pmovsxbq
3964 (bitconvert (v4i32 (X86vzmovl
3965 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3966 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3968 def : Pat<(int_x86_sse41_pmovzxbq
3969 (bitconvert (v4i32 (X86vzmovl
3970 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3971 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3973 //===----------------------------------------------------------------------===//
3974 // SSE4.1 - Extract Instructions
3975 //===----------------------------------------------------------------------===//
3977 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3978 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3979 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3980 (ins VR128:$src1, i32i8imm:$src2),
3981 !strconcat(OpcodeStr,
3982 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3983 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3985 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3986 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3987 !strconcat(OpcodeStr,
3988 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3991 // There's an AssertZext in the way of writing the store pattern
3992 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3995 let Predicates = [HasAVX] in {
3996 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
3997 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
3998 (ins VR128:$src1, i32i8imm:$src2),
3999 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4002 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4005 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4006 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4007 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4008 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4009 !strconcat(OpcodeStr,
4010 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4013 // There's an AssertZext in the way of writing the store pattern
4014 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4017 let Predicates = [HasAVX] in
4018 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4020 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4023 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4024 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4025 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4026 (ins VR128:$src1, i32i8imm:$src2),
4027 !strconcat(OpcodeStr,
4028 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4030 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4031 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4032 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4033 !strconcat(OpcodeStr,
4034 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4035 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4036 addr:$dst)]>, OpSize;
4039 let Predicates = [HasAVX] in
4040 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4042 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4044 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4045 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4046 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4047 (ins VR128:$src1, i32i8imm:$src2),
4048 !strconcat(OpcodeStr,
4049 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4051 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4052 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4053 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4054 !strconcat(OpcodeStr,
4055 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4056 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4057 addr:$dst)]>, OpSize, REX_W;
4060 let Predicates = [HasAVX] in
4061 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4063 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4065 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4067 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4068 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4069 (ins VR128:$src1, i32i8imm:$src2),
4070 !strconcat(OpcodeStr,
4071 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4073 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4075 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4076 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4077 !strconcat(OpcodeStr,
4078 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4079 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4080 addr:$dst)]>, OpSize;
4083 let Predicates = [HasAVX] in {
4084 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4085 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4086 (ins VR128:$src1, i32i8imm:$src2),
4087 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4090 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4092 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4093 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4096 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4097 Requires<[HasSSE41]>;
4099 //===----------------------------------------------------------------------===//
4100 // SSE4.1 - Insert Instructions
4101 //===----------------------------------------------------------------------===//
4103 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4104 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4105 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4107 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4109 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4111 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4112 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4113 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4115 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4117 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4119 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4120 imm:$src3))]>, OpSize;
4123 let Predicates = [HasAVX] in
4124 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4125 let Constraints = "$src1 = $dst" in
4126 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4128 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4129 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4130 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4132 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4134 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4136 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4138 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4139 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4141 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4143 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4145 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4146 imm:$src3)))]>, OpSize;
4149 let Predicates = [HasAVX] in
4150 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4151 let Constraints = "$src1 = $dst" in
4152 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4154 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4155 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4156 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4158 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4160 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4162 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4164 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4165 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4167 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4169 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4171 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4172 imm:$src3)))]>, OpSize;
4175 let Predicates = [HasAVX] in
4176 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4177 let Constraints = "$src1 = $dst" in
4178 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4180 // insertps has a few different modes, there's the first two here below which
4181 // are optimized inserts that won't zero arbitrary elements in the destination
4182 // vector. The next one matches the intrinsic and could zero arbitrary elements
4183 // in the target vector.
4184 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4185 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4186 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4188 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4190 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4192 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4194 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4195 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4197 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4199 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4201 (X86insrtps VR128:$src1,
4202 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4203 imm:$src3))]>, OpSize;
4206 let Constraints = "$src1 = $dst" in
4207 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4208 let Predicates = [HasAVX] in
4209 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4211 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4212 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4214 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4215 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4216 Requires<[HasSSE41]>;
4218 //===----------------------------------------------------------------------===//
4219 // SSE4.1 - Round Instructions
4220 //===----------------------------------------------------------------------===//
4222 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4223 X86MemOperand x86memop, RegisterClass RC,
4224 PatFrag mem_frag32, PatFrag mem_frag64,
4225 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4226 // Intrinsic operation, reg.
4227 // Vector intrinsic operation, reg
4228 def PSr : SS4AIi8<opcps, MRMSrcReg,
4229 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4230 !strconcat(OpcodeStr,
4231 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4232 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4235 // Vector intrinsic operation, mem
4236 def PSm : Ii8<opcps, MRMSrcMem,
4237 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4238 !strconcat(OpcodeStr,
4239 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4241 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4243 Requires<[HasSSE41]>;
4245 // Vector intrinsic operation, reg
4246 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4247 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4248 !strconcat(OpcodeStr,
4249 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4250 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4253 // Vector intrinsic operation, mem
4254 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4255 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4256 !strconcat(OpcodeStr,
4257 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4259 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4263 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4264 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4265 // Intrinsic operation, reg.
4266 // Vector intrinsic operation, reg
4267 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4268 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4269 !strconcat(OpcodeStr,
4270 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4273 // Vector intrinsic operation, mem
4274 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4275 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4276 !strconcat(OpcodeStr,
4277 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4278 []>, TA, OpSize, Requires<[HasSSE41]>;
4280 // Vector intrinsic operation, reg
4281 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4282 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4283 !strconcat(OpcodeStr,
4284 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4287 // Vector intrinsic operation, mem
4288 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4289 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4290 !strconcat(OpcodeStr,
4291 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4295 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4298 Intrinsic F64Int, bit Is2Addr = 1> {
4299 // Intrinsic operation, reg.
4300 def SSr : SS4AIi8<opcss, MRMSrcReg,
4301 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4303 !strconcat(OpcodeStr,
4304 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4305 !strconcat(OpcodeStr,
4306 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4307 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4310 // Intrinsic operation, mem.
4311 def SSm : SS4AIi8<opcss, MRMSrcMem,
4312 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4314 !strconcat(OpcodeStr,
4315 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4316 !strconcat(OpcodeStr,
4317 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4319 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4322 // Intrinsic operation, reg.
4323 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4324 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4326 !strconcat(OpcodeStr,
4327 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4328 !strconcat(OpcodeStr,
4329 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4330 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4333 // Intrinsic operation, mem.
4334 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4335 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4337 !strconcat(OpcodeStr,
4338 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4339 !strconcat(OpcodeStr,
4340 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4342 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4346 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4348 // Intrinsic operation, reg.
4349 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4350 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4351 !strconcat(OpcodeStr,
4352 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4355 // Intrinsic operation, mem.
4356 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4357 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4358 !strconcat(OpcodeStr,
4359 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4362 // Intrinsic operation, reg.
4363 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4364 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4365 !strconcat(OpcodeStr,
4366 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4369 // Intrinsic operation, mem.
4370 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4371 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4372 !strconcat(OpcodeStr,
4373 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4377 // FP round - roundss, roundps, roundsd, roundpd
4378 let Predicates = [HasAVX] in {
4380 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4381 memopv4f32, memopv2f64,
4382 int_x86_sse41_round_ps,
4383 int_x86_sse41_round_pd>, VEX;
4384 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4385 memopv8f32, memopv4f64,
4386 int_x86_avx_round_ps_256,
4387 int_x86_avx_round_pd_256>, VEX;
4388 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4389 int_x86_sse41_round_ss,
4390 int_x86_sse41_round_sd, 0>, VEX_4V;
4392 // Instructions for the assembler
4393 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4395 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4397 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4400 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4401 memopv4f32, memopv2f64,
4402 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4403 let Constraints = "$src1 = $dst" in
4404 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4405 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4407 //===----------------------------------------------------------------------===//
4408 // SSE4.1 - Packed Bit Test
4409 //===----------------------------------------------------------------------===//
4411 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4412 // the intel intrinsic that corresponds to this.
4413 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4414 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4415 "vptest\t{$src2, $src1|$src1, $src2}",
4416 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4418 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4419 "vptest\t{$src2, $src1|$src1, $src2}",
4420 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4423 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4424 "vptest\t{$src2, $src1|$src1, $src2}",
4425 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4427 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4428 "vptest\t{$src2, $src1|$src1, $src2}",
4429 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4433 let Defs = [EFLAGS] in {
4434 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4435 "ptest \t{$src2, $src1|$src1, $src2}",
4436 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4438 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4439 "ptest \t{$src2, $src1|$src1, $src2}",
4440 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4444 // The bit test instructions below are AVX only
4445 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4446 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4447 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4448 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4449 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4450 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4451 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4452 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4456 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4457 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4458 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4459 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4460 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4463 //===----------------------------------------------------------------------===//
4464 // SSE4.1 - Misc Instructions
4465 //===----------------------------------------------------------------------===//
4467 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4468 "popcnt{w}\t{$src, $dst|$dst, $src}",
4469 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4470 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4471 "popcnt{w}\t{$src, $dst|$dst, $src}",
4472 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4474 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4475 "popcnt{l}\t{$src, $dst|$dst, $src}",
4476 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4477 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4478 "popcnt{l}\t{$src, $dst|$dst, $src}",
4479 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4481 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4482 "popcnt{q}\t{$src, $dst|$dst, $src}",
4483 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4484 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4485 "popcnt{q}\t{$src, $dst|$dst, $src}",
4486 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4490 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4491 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4492 Intrinsic IntId128> {
4493 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4495 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4496 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4497 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4499 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4502 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4505 let Predicates = [HasAVX] in
4506 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4507 int_x86_sse41_phminposuw>, VEX;
4508 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4509 int_x86_sse41_phminposuw>;
4511 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4512 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4513 Intrinsic IntId128, bit Is2Addr = 1> {
4514 let isCommutable = 1 in
4515 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4516 (ins VR128:$src1, VR128:$src2),
4518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4519 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4520 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4521 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4522 (ins VR128:$src1, i128mem:$src2),
4524 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4527 (IntId128 VR128:$src1,
4528 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4531 let Predicates = [HasAVX] in {
4532 let isCommutable = 0 in
4533 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4535 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4537 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4539 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4541 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4543 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4545 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4547 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4549 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4551 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4553 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4557 let Constraints = "$src1 = $dst" in {
4558 let isCommutable = 0 in
4559 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4560 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4561 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4562 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4563 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4564 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4565 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4566 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4567 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4568 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4569 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4572 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4573 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4574 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4575 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4577 /// SS48I_binop_rm - Simple SSE41 binary operator.
4578 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4579 ValueType OpVT, bit Is2Addr = 1> {
4580 let isCommutable = 1 in
4581 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4582 (ins VR128:$src1, VR128:$src2),
4584 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4585 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4586 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4588 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4589 (ins VR128:$src1, i128mem:$src2),
4591 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4592 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4593 [(set VR128:$dst, (OpNode VR128:$src1,
4594 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4598 let Predicates = [HasAVX] in
4599 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4600 let Constraints = "$src1 = $dst" in
4601 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4603 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4604 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4605 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4606 X86MemOperand x86memop, bit Is2Addr = 1> {
4607 let isCommutable = 1 in
4608 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4609 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4611 !strconcat(OpcodeStr,
4612 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4613 !strconcat(OpcodeStr,
4614 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4615 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4617 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4618 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4620 !strconcat(OpcodeStr,
4621 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4622 !strconcat(OpcodeStr,
4623 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4626 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4630 let Predicates = [HasAVX] in {
4631 let isCommutable = 0 in {
4632 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4633 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4634 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4635 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4636 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4637 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4638 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4639 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4640 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4641 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4642 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4643 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4645 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4646 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4647 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4648 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4649 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4650 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4653 let Constraints = "$src1 = $dst" in {
4654 let isCommutable = 0 in {
4655 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4656 VR128, memopv16i8, i128mem>;
4657 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4658 VR128, memopv16i8, i128mem>;
4659 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4660 VR128, memopv16i8, i128mem>;
4661 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4662 VR128, memopv16i8, i128mem>;
4664 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4665 VR128, memopv16i8, i128mem>;
4666 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4667 VR128, memopv16i8, i128mem>;
4670 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4671 let Predicates = [HasAVX] in {
4672 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4673 RegisterClass RC, X86MemOperand x86memop,
4674 PatFrag mem_frag, Intrinsic IntId> {
4675 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4676 (ins RC:$src1, RC:$src2, RC:$src3),
4677 !strconcat(OpcodeStr,
4678 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4679 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4680 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4682 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4683 (ins RC:$src1, x86memop:$src2, RC:$src3),
4684 !strconcat(OpcodeStr,
4685 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4687 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4689 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4693 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4694 memopv16i8, int_x86_sse41_blendvpd>;
4695 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4696 memopv16i8, int_x86_sse41_blendvps>;
4697 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4698 memopv16i8, int_x86_sse41_pblendvb>;
4699 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4700 memopv32i8, int_x86_avx_blendv_pd_256>;
4701 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4702 memopv32i8, int_x86_avx_blendv_ps_256>;
4704 /// SS41I_ternary_int - SSE 4.1 ternary operator
4705 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4706 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4707 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4708 (ins VR128:$src1, VR128:$src2),
4709 !strconcat(OpcodeStr,
4710 "\t{$src2, $dst|$dst, $src2}"),
4711 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4714 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4715 (ins VR128:$src1, i128mem:$src2),
4716 !strconcat(OpcodeStr,
4717 "\t{$src2, $dst|$dst, $src2}"),
4720 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4724 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4725 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4726 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4728 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4729 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4731 let Predicates = [HasAVX] in
4732 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4733 "vmovntdqa\t{$src, $dst|$dst, $src}",
4734 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4736 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4737 "movntdqa\t{$src, $dst|$dst, $src}",
4738 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4741 //===----------------------------------------------------------------------===//
4742 // SSE4.2 - Compare Instructions
4743 //===----------------------------------------------------------------------===//
4745 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4746 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4747 Intrinsic IntId128, bit Is2Addr = 1> {
4748 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4749 (ins VR128:$src1, VR128:$src2),
4751 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4752 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4753 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4755 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4756 (ins VR128:$src1, i128mem:$src2),
4758 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4759 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4761 (IntId128 VR128:$src1,
4762 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4765 let Predicates = [HasAVX] in
4766 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4768 let Constraints = "$src1 = $dst" in
4769 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4771 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4772 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4773 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4774 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4776 //===----------------------------------------------------------------------===//
4777 // SSE4.2 - String/text Processing Instructions
4778 //===----------------------------------------------------------------------===//
4780 // Packed Compare Implicit Length Strings, Return Mask
4781 multiclass pseudo_pcmpistrm<string asm> {
4782 def REG : PseudoI<(outs VR128:$dst),
4783 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4784 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4786 def MEM : PseudoI<(outs VR128:$dst),
4787 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4788 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4789 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4792 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4793 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4794 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4797 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
4798 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4799 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4800 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4801 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4802 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4803 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4806 let Defs = [XMM0, EFLAGS] in {
4807 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4808 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4809 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4810 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4811 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4812 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4815 // Packed Compare Explicit Length Strings, Return Mask
4816 multiclass pseudo_pcmpestrm<string asm> {
4817 def REG : PseudoI<(outs VR128:$dst),
4818 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4819 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4820 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4821 def MEM : PseudoI<(outs VR128:$dst),
4822 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4823 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4824 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4827 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4828 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4829 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4832 let Predicates = [HasAVX],
4833 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4834 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4835 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4836 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4837 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4838 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4839 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4842 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4843 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4844 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4845 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4846 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4847 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4848 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4851 // Packed Compare Implicit Length Strings, Return Index
4852 let Defs = [ECX, EFLAGS] in {
4853 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4854 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4855 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4856 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4857 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4858 (implicit EFLAGS)]>, OpSize;
4859 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4860 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4861 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4862 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4863 (implicit EFLAGS)]>, OpSize;
4867 let Predicates = [HasAVX] in {
4868 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4870 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4872 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4874 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4876 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4878 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4882 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4883 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4884 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4885 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4886 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4887 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4889 // Packed Compare Explicit Length Strings, Return Index
4890 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
4891 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
4892 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4893 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4894 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4895 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4896 (implicit EFLAGS)]>, OpSize;
4897 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4898 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4899 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4901 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4902 (implicit EFLAGS)]>, OpSize;
4906 let Predicates = [HasAVX] in {
4907 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
4909 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
4911 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
4913 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
4915 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
4917 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
4921 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4922 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4923 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4924 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4925 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4926 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4928 //===----------------------------------------------------------------------===//
4929 // SSE4.2 - CRC Instructions
4930 //===----------------------------------------------------------------------===//
4932 // No CRC instructions have AVX equivalents
4934 // crc intrinsic instruction
4935 // This set of instructions are only rm, the only difference is the size
4937 let Constraints = "$src1 = $dst" in {
4938 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4939 (ins GR32:$src1, i8mem:$src2),
4940 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4942 (int_x86_sse42_crc32_8 GR32:$src1,
4943 (load addr:$src2)))]>;
4944 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4945 (ins GR32:$src1, GR8:$src2),
4946 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4948 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
4949 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4950 (ins GR32:$src1, i16mem:$src2),
4951 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4953 (int_x86_sse42_crc32_16 GR32:$src1,
4954 (load addr:$src2)))]>,
4956 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4957 (ins GR32:$src1, GR16:$src2),
4958 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4960 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
4962 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4963 (ins GR32:$src1, i32mem:$src2),
4964 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4966 (int_x86_sse42_crc32_32 GR32:$src1,
4967 (load addr:$src2)))]>;
4968 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4969 (ins GR32:$src1, GR32:$src2),
4970 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4972 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
4973 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4974 (ins GR64:$src1, i8mem:$src2),
4975 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4977 (int_x86_sse42_crc64_8 GR64:$src1,
4978 (load addr:$src2)))]>,
4980 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4981 (ins GR64:$src1, GR8:$src2),
4982 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4984 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
4986 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
4987 (ins GR64:$src1, i64mem:$src2),
4988 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4990 (int_x86_sse42_crc64_64 GR64:$src1,
4991 (load addr:$src2)))]>,
4993 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
4994 (ins GR64:$src1, GR64:$src2),
4995 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4997 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
5001 //===----------------------------------------------------------------------===//
5002 // AES-NI Instructions
5003 //===----------------------------------------------------------------------===//
5005 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5006 Intrinsic IntId128, bit Is2Addr = 1> {
5007 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5008 (ins VR128:$src1, VR128:$src2),
5010 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5012 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5014 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5015 (ins VR128:$src1, i128mem:$src2),
5017 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5020 (IntId128 VR128:$src1,
5021 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5024 // Perform One Round of an AES Encryption/Decryption Flow
5025 let Predicates = [HasAVX, HasAES] in {
5026 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5027 int_x86_aesni_aesenc, 0>, VEX_4V;
5028 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5029 int_x86_aesni_aesenclast, 0>, VEX_4V;
5030 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5031 int_x86_aesni_aesdec, 0>, VEX_4V;
5032 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5033 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5036 let Constraints = "$src1 = $dst" in {
5037 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5038 int_x86_aesni_aesenc>;
5039 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5040 int_x86_aesni_aesenclast>;
5041 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5042 int_x86_aesni_aesdec>;
5043 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5044 int_x86_aesni_aesdeclast>;
5047 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5048 (AESENCrr VR128:$src1, VR128:$src2)>;
5049 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5050 (AESENCrm VR128:$src1, addr:$src2)>;
5051 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5052 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5053 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5054 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5055 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5056 (AESDECrr VR128:$src1, VR128:$src2)>;
5057 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5058 (AESDECrm VR128:$src1, addr:$src2)>;
5059 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5060 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5061 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5062 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5064 // Perform the AES InvMixColumn Transformation
5065 let Predicates = [HasAVX, HasAES] in {
5066 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5068 "vaesimc\t{$src1, $dst|$dst, $src1}",
5070 (int_x86_aesni_aesimc VR128:$src1))]>,
5072 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5073 (ins i128mem:$src1),
5074 "vaesimc\t{$src1, $dst|$dst, $src1}",
5076 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5079 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5081 "aesimc\t{$src1, $dst|$dst, $src1}",
5083 (int_x86_aesni_aesimc VR128:$src1))]>,
5085 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5086 (ins i128mem:$src1),
5087 "aesimc\t{$src1, $dst|$dst, $src1}",
5089 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5092 // AES Round Key Generation Assist
5093 let Predicates = [HasAVX, HasAES] in {
5094 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5095 (ins VR128:$src1, i8imm:$src2),
5096 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5098 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5100 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5101 (ins i128mem:$src1, i8imm:$src2),
5102 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5104 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5108 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5109 (ins VR128:$src1, i8imm:$src2),
5110 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5112 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5114 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5115 (ins i128mem:$src1, i8imm:$src2),
5116 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5118 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5122 //===----------------------------------------------------------------------===//
5123 // CLMUL Instructions
5124 //===----------------------------------------------------------------------===//
5126 // Only the AVX version of CLMUL instructions are described here.
5128 // Carry-less Multiplication instructions
5129 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5130 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5131 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5134 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5135 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5136 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5140 multiclass avx_vpclmul<string asm> {
5141 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5142 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5145 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5146 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5149 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5150 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5151 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5152 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5154 //===----------------------------------------------------------------------===//
5156 //===----------------------------------------------------------------------===//
5159 // Load from memory and broadcast to all elements of the destination operand
5160 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5161 X86MemOperand x86memop, Intrinsic Int> :
5162 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5163 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5164 [(set RC:$dst, (Int addr:$src))]>, VEX;
5166 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5167 int_x86_avx_vbroadcastss>;
5168 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5169 int_x86_avx_vbroadcastss_256>;
5170 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5171 int_x86_avx_vbroadcast_sd_256>;
5172 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5173 int_x86_avx_vbroadcastf128_pd_256>;
5175 // Insert packed floating-point values
5176 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5177 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5178 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5180 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5181 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5182 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5185 // Extract packed floating-point values
5186 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5187 (ins VR256:$src1, i8imm:$src2),
5188 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5190 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5191 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5192 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5195 // Conditional SIMD Packed Loads and Stores
5196 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5197 Intrinsic IntLd, Intrinsic IntLd256,
5198 Intrinsic IntSt, Intrinsic IntSt256,
5199 PatFrag pf128, PatFrag pf256> {
5200 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5201 (ins VR128:$src1, f128mem:$src2),
5202 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5203 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5205 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5206 (ins VR256:$src1, f256mem:$src2),
5207 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5208 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5210 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5211 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5213 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5214 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5215 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5216 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5217 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5220 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5221 int_x86_avx_maskload_ps,
5222 int_x86_avx_maskload_ps_256,
5223 int_x86_avx_maskstore_ps,
5224 int_x86_avx_maskstore_ps_256,
5225 memopv4f32, memopv8f32>;
5226 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5227 int_x86_avx_maskload_pd,
5228 int_x86_avx_maskload_pd_256,
5229 int_x86_avx_maskstore_pd,
5230 int_x86_avx_maskstore_pd_256,
5231 memopv2f64, memopv4f64>;
5233 // Permute Floating-Point Values
5234 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5235 RegisterClass RC, X86MemOperand x86memop_f,
5236 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5237 Intrinsic IntVar, Intrinsic IntImm> {
5238 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5239 (ins RC:$src1, RC:$src2),
5240 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5241 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5242 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5243 (ins RC:$src1, x86memop_i:$src2),
5244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5245 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5247 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5248 (ins RC:$src1, i8imm:$src2),
5249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5250 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5251 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5252 (ins x86memop_f:$src1, i8imm:$src2),
5253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5254 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5257 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5258 memopv4f32, memopv4i32,
5259 int_x86_avx_vpermilvar_ps,
5260 int_x86_avx_vpermil_ps>;
5261 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5262 memopv8f32, memopv8i32,
5263 int_x86_avx_vpermilvar_ps_256,
5264 int_x86_avx_vpermil_ps_256>;
5265 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5266 memopv2f64, memopv2i64,
5267 int_x86_avx_vpermilvar_pd,
5268 int_x86_avx_vpermil_pd>;
5269 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5270 memopv4f64, memopv4i64,
5271 int_x86_avx_vpermilvar_pd_256,
5272 int_x86_avx_vpermil_pd_256>;
5274 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5275 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5276 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5278 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5279 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5280 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5283 // Zero All YMM registers
5284 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5285 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5287 // Zero Upper bits of YMM registers
5288 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5289 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5291 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5292 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5293 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5294 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5295 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5296 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5298 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5300 (VINSERTF128rr VR256:$src1, VR128:$src2,
5301 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5302 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5304 (VINSERTF128rr VR256:$src1, VR128:$src2,
5305 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5306 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5308 (VINSERTF128rr VR256:$src1, VR128:$src2,
5309 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5310 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5312 (VINSERTF128rr VR256:$src1, VR128:$src2,
5313 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5315 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5316 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5317 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5318 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5319 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5320 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5322 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5323 (v4f32 (VEXTRACTF128rr
5324 (v8f32 VR256:$src1),
5325 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5326 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5327 (v2f64 (VEXTRACTF128rr
5328 (v4f64 VR256:$src1),
5329 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5330 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5331 (v4i32 (VEXTRACTF128rr
5332 (v8i32 VR256:$src1),
5333 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5334 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5335 (v2i64 (VEXTRACTF128rr
5336 (v4i64 VR256:$src1),
5337 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5339 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5340 (VBROADCASTF128 addr:$src)>;
5342 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5343 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5344 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5345 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5346 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5347 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5349 def : Pat<(int_x86_avx_vperm2f128_ps_256
5350 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5351 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5352 def : Pat<(int_x86_avx_vperm2f128_pd_256
5353 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5354 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5355 def : Pat<(int_x86_avx_vperm2f128_si_256
5356 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5357 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5359 //===----------------------------------------------------------------------===//
5360 // SSE Shuffle pattern fragments
5361 //===----------------------------------------------------------------------===//
5363 // This is part of a "work in progress" refactoring. The idea is that all
5364 // vector shuffles are going to be translated into target specific nodes and
5365 // directly matched by the patterns below (which can be changed along the way)
5366 // The AVX version of some but not all of them are described here, and more
5367 // should come in a near future.
5369 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5370 // SSE2 loads, which are always promoted to v2i64. The last one should match
5371 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5372 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5373 // we investigate further.
5374 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5376 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5377 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5379 (PSHUFDmi addr:$src1, imm:$imm)>;
5380 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5382 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5384 // Shuffle with PSHUFD instruction.
5385 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5386 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5387 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5388 (PSHUFDri VR128:$src1, imm:$imm)>;
5390 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5391 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5392 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5393 (PSHUFDri VR128:$src1, imm:$imm)>;
5395 // Shuffle with SHUFPD instruction.
5396 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5397 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5398 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5399 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5400 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5401 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5403 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5404 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5405 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5406 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5408 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5409 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5410 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5411 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5413 // Shuffle with SHUFPS instruction.
5414 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5415 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5416 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5417 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5418 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5419 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5421 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5422 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5423 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5424 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5426 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5427 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5428 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5429 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5430 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5431 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5433 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5434 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5435 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5436 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5438 // Shuffle with MOVHLPS instruction
5439 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5440 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5444 // Shuffle with MOVDDUP instruction
5445 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5446 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5447 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5448 (MOVDDUPrm addr:$src)>;
5450 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5451 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5452 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5453 (MOVDDUPrm addr:$src)>;
5455 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5456 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5457 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5458 (MOVDDUPrm addr:$src)>;
5460 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5461 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5462 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5463 (MOVDDUPrm addr:$src)>;
5465 def : Pat<(X86Movddup (bc_v2f64
5466 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5467 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5468 def : Pat<(X86Movddup (bc_v2f64
5469 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5470 (MOVDDUPrm addr:$src)>;
5473 // Shuffle with UNPCKLPS
5474 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5475 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5476 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5477 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5478 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5479 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5481 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5482 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5483 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5484 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5485 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5486 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5488 // Shuffle with UNPCKHPS
5489 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5490 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5491 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5492 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5494 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5495 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5496 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5497 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5499 // Shuffle with UNPCKLPD
5500 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5501 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5502 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5503 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5504 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5505 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5507 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5508 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5509 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5510 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5511 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5512 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5514 // Shuffle with UNPCKHPD
5515 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5516 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5517 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5518 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5520 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5521 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5522 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5523 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5525 // Shuffle with PUNPCKLBW
5526 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1,
5527 (bc_v16i8 (memopv2i64 addr:$src2)))),
5528 (PUNPCKLBWrm VR128:$src1, addr:$src2)>;
5529 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)),
5530 (PUNPCKLBWrr VR128:$src1, VR128:$src2)>;
5532 // Shuffle with PUNPCKLWD
5533 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1,
5534 (bc_v8i16 (memopv2i64 addr:$src2)))),
5535 (PUNPCKLWDrm VR128:$src1, addr:$src2)>;
5536 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)),
5537 (PUNPCKLWDrr VR128:$src1, VR128:$src2)>;
5539 // Shuffle with PUNPCKLDQ
5540 def : Pat<(v4i32 (X86Punpckldq VR128:$src1,
5541 (bc_v4i32 (memopv2i64 addr:$src2)))),
5542 (PUNPCKLDQrm VR128:$src1, addr:$src2)>;
5543 def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)),
5544 (PUNPCKLDQrr VR128:$src1, VR128:$src2)>;
5546 // Shuffle with PUNPCKLQDQ
5547 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))),
5548 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>;
5549 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)),
5550 (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>;
5552 // Shuffle with PUNPCKHBW
5553 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1,
5554 (bc_v16i8 (memopv2i64 addr:$src2)))),
5555 (PUNPCKHBWrm VR128:$src1, addr:$src2)>;
5556 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)),
5557 (PUNPCKHBWrr VR128:$src1, VR128:$src2)>;
5559 // Shuffle with PUNPCKHWD
5560 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1,
5561 (bc_v8i16 (memopv2i64 addr:$src2)))),
5562 (PUNPCKHWDrm VR128:$src1, addr:$src2)>;
5563 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)),
5564 (PUNPCKHWDrr VR128:$src1, VR128:$src2)>;
5566 // Shuffle with PUNPCKHDQ
5567 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1,
5568 (bc_v4i32 (memopv2i64 addr:$src2)))),
5569 (PUNPCKHDQrm VR128:$src1, addr:$src2)>;
5570 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)),
5571 (PUNPCKHDQrr VR128:$src1, VR128:$src2)>;
5573 // Shuffle with PUNPCKHQDQ
5574 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))),
5575 (PUNPCKHQDQrm VR128:$src1, addr:$src2)>;
5576 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)),
5577 (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>;
5579 // Shuffle with MOVLHPS
5580 def : Pat<(X86Movlhps VR128:$src1,
5581 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5582 (MOVHPSrm VR128:$src1, addr:$src2)>;
5583 def : Pat<(X86Movlhps VR128:$src1,
5584 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5585 (MOVHPSrm VR128:$src1, addr:$src2)>;
5586 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5587 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5588 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5589 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5590 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5591 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5593 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5594 // is during lowering, where it's not possible to recognize the load fold cause
5595 // it has two uses through a bitcast. One use disappears at isel time and the
5596 // fold opportunity reappears.
5597 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5598 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5600 // Shuffle with MOVLHPD
5601 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5602 (scalar_to_vector (loadf64 addr:$src2)))),
5603 (MOVHPDrm VR128:$src1, addr:$src2)>;
5605 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5606 // is during lowering, where it's not possible to recognize the load fold cause
5607 // it has two uses through a bitcast. One use disappears at isel time and the
5608 // fold opportunity reappears.
5609 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5610 (scalar_to_vector (loadf64 addr:$src2)))),
5611 (MOVHPDrm VR128:$src1, addr:$src2)>;
5613 // Shuffle with MOVSS
5614 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5615 (MOVSSrr VR128:$src1, FR32:$src2)>;
5616 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5617 (MOVSSrr (v4i32 VR128:$src1),
5618 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5619 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5620 (MOVSSrr (v4f32 VR128:$src1),
5621 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5622 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5623 // is during lowering, where it's not possible to recognize the load fold cause
5624 // it has two uses through a bitcast. One use disappears at isel time and the
5625 // fold opportunity reappears.
5626 def : Pat<(X86Movss VR128:$src1,
5627 (bc_v4i32 (v2i64 (load addr:$src2)))),
5628 (MOVLPSrm VR128:$src1, addr:$src2)>;
5630 // Shuffle with MOVSD
5631 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5632 (MOVSDrr VR128:$src1, FR64:$src2)>;
5633 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5634 (MOVSDrr (v2i64 VR128:$src1),
5635 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5636 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5637 (MOVSDrr (v2f64 VR128:$src1),
5638 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5639 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5640 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5641 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5642 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5644 // Shuffle with MOVSHDUP
5645 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5646 (MOVSHDUPrr VR128:$src)>;
5647 def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))),
5648 (MOVSHDUPrm addr:$src)>;
5650 def : Pat<(v4f32 (X86Movshdup VR128:$src)),
5651 (MOVSHDUPrr VR128:$src)>;
5652 def : Pat<(X86Movshdup (memopv4f32 addr:$src)),
5653 (MOVSHDUPrm addr:$src)>;
5655 // Shuffle with MOVSLDUP
5656 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5657 (MOVSLDUPrr VR128:$src)>;
5658 def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))),
5659 (MOVSLDUPrm addr:$src)>;
5661 def : Pat<(v4f32 (X86Movsldup VR128:$src)),
5662 (MOVSLDUPrr VR128:$src)>;
5663 def : Pat<(X86Movsldup (memopv4f32 addr:$src)),
5664 (MOVSLDUPrm addr:$src)>;
5666 // Shuffle with PSHUFHW
5667 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5668 (PSHUFHWri VR128:$src, imm:$imm)>;
5669 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5670 (PSHUFHWmi addr:$src, imm:$imm)>;
5672 // Shuffle with PSHUFLW
5673 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5674 (PSHUFLWri VR128:$src, imm:$imm)>;
5675 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5676 (PSHUFLWmi addr:$src, imm:$imm)>;
5678 // Shuffle with PALIGN
5679 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5680 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5681 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5682 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5683 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5684 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5685 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5686 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5688 // Shuffle with MOVLPS
5689 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5690 (MOVLPSrm VR128:$src1, addr:$src2)>;
5691 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5692 (MOVLPSrm VR128:$src1, addr:$src2)>;
5693 def : Pat<(X86Movlps VR128:$src1,
5694 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5695 (MOVLPSrm VR128:$src1, addr:$src2)>;
5696 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5697 // is during lowering, where it's not possible to recognize the load fold cause
5698 // it has two uses through a bitcast. One use disappears at isel time and the
5699 // fold opportunity reappears.
5700 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5701 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5703 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5704 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5706 // Shuffle with MOVLPD
5707 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5708 (MOVLPDrm VR128:$src1, addr:$src2)>;
5709 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5710 (MOVLPDrm VR128:$src1, addr:$src2)>;
5711 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5712 (scalar_to_vector (loadf64 addr:$src2)))),
5713 (MOVLPDrm VR128:$src1, addr:$src2)>;
5715 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5716 def : Pat<(store (f64 (vector_extract
5717 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5718 (MOVHPSmr addr:$dst, VR128:$src)>;
5719 def : Pat<(store (f64 (vector_extract
5720 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5721 (MOVHPDmr addr:$dst, VR128:$src)>;
5723 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5724 (MOVLPSmr addr:$src1, VR128:$src2)>;
5725 def : Pat<(store (v4i32 (X86Movlps
5726 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5727 (MOVLPSmr addr:$src1, VR128:$src2)>;
5729 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5730 (MOVLPDmr addr:$src1, VR128:$src2)>;
5731 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5732 (MOVLPDmr addr:$src1, VR128:$src2)>;