1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 let isAsmParserOnly = 1 in {
139 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
140 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
141 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
142 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
144 let canFoldAsLoad = 1, isReMaterializable = 1 in {
145 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
147 let AddedComplexity = 20 in
148 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
152 let Constraints = "$src1 = $dst" in {
153 def MOVSSrr : sse12_move_rr<FR32, v4f32,
154 "movss\t{$src2, $dst|$dst, $src2}">, XS;
155 def MOVSDrr : sse12_move_rr<FR64, v2f64,
156 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
159 let canFoldAsLoad = 1, isReMaterializable = 1 in {
160 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
162 let AddedComplexity = 20 in
163 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
166 let AddedComplexity = 15 in {
167 // Extract the low 32-bit value from one vector and insert it into another.
168 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
169 (MOVSSrr (v4f32 VR128:$src1),
170 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
171 // Extract the low 64-bit value from one vector and insert it into another.
172 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
173 (MOVSDrr (v2f64 VR128:$src1),
174 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
177 // Implicitly promote a 32-bit scalar to a vector.
178 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
179 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
180 // Implicitly promote a 64-bit scalar to a vector.
181 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
182 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
183 // Implicitly promote a 32-bit scalar to a vector.
184 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
185 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
186 // Implicitly promote a 64-bit scalar to a vector.
187 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
188 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
190 let AddedComplexity = 20 in {
191 // MOVSSrm zeros the high parts of the register; represent this
192 // with SUBREG_TO_REG.
193 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
198 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
199 // MOVSDrm zeros the high parts of the register; represent this
200 // with SUBREG_TO_REG.
201 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
209 def : Pat<(v2f64 (X86vzload addr:$src)),
210 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
213 // Store scalar value to memory.
214 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
215 "movss\t{$src, $dst|$dst, $src}",
216 [(store FR32:$src, addr:$dst)]>;
217 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
218 "movsd\t{$src, $dst|$dst, $src}",
219 [(store FR64:$src, addr:$dst)]>;
221 let isAsmParserOnly = 1 in {
222 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
223 "movss\t{$src, $dst|$dst, $src}",
224 [(store FR32:$src, addr:$dst)]>, XS, VEX;
225 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
226 "movsd\t{$src, $dst|$dst, $src}",
227 [(store FR64:$src, addr:$dst)]>, XD, VEX;
230 // Extract and store.
231 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
235 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
238 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
240 // Move Aligned/Unaligned floating point values
241 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
242 X86MemOperand x86memop, PatFrag ld_frag,
243 string asm, Domain d,
244 bit IsReMaterializable = 1> {
245 let neverHasSideEffects = 1 in
246 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
247 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
248 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
249 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
250 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
251 [(set RC:$dst, (ld_frag addr:$src))], d>;
254 let isAsmParserOnly = 1 in {
255 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
256 "movaps", SSEPackedSingle>, VEX;
257 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
258 "movapd", SSEPackedDouble>, OpSize, VEX;
259 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
260 "movups", SSEPackedSingle>, VEX;
261 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
262 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
264 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
265 "movaps", SSEPackedSingle>, VEX;
266 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
267 "movapd", SSEPackedDouble>, OpSize, VEX;
268 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
269 "movups", SSEPackedSingle>, VEX;
270 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
271 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
273 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
274 "movaps", SSEPackedSingle>, TB;
275 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
276 "movapd", SSEPackedDouble>, TB, OpSize;
277 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
278 "movups", SSEPackedSingle>, TB;
279 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
280 "movupd", SSEPackedDouble, 0>, TB, OpSize;
282 let isAsmParserOnly = 1 in {
283 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
284 "movaps\t{$src, $dst|$dst, $src}",
285 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
286 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
287 "movapd\t{$src, $dst|$dst, $src}",
288 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
289 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
290 "movups\t{$src, $dst|$dst, $src}",
291 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
292 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
293 "movupd\t{$src, $dst|$dst, $src}",
294 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
295 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
296 "movaps\t{$src, $dst|$dst, $src}",
297 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
298 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
299 "movapd\t{$src, $dst|$dst, $src}",
300 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
302 "movups\t{$src, $dst|$dst, $src}",
303 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
304 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
305 "movupd\t{$src, $dst|$dst, $src}",
306 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
309 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
310 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
311 (VMOVUPSYmr addr:$dst, VR256:$src)>;
313 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
314 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
315 (VMOVUPDYmr addr:$dst, VR256:$src)>;
317 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
318 "movaps\t{$src, $dst|$dst, $src}",
319 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
320 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
321 "movapd\t{$src, $dst|$dst, $src}",
322 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
323 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
324 "movups\t{$src, $dst|$dst, $src}",
325 [(store (v4f32 VR128:$src), addr:$dst)]>;
326 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
327 "movupd\t{$src, $dst|$dst, $src}",
328 [(store (v2f64 VR128:$src), addr:$dst)]>;
330 // Intrinsic forms of MOVUPS/D load and store
331 let isAsmParserOnly = 1 in {
332 let canFoldAsLoad = 1, isReMaterializable = 1 in
333 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
335 "movups\t{$src, $dst|$dst, $src}",
336 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
337 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
339 "movupd\t{$src, $dst|$dst, $src}",
340 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
341 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
342 (ins f128mem:$dst, VR128:$src),
343 "movups\t{$src, $dst|$dst, $src}",
344 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
345 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
346 (ins f128mem:$dst, VR128:$src),
347 "movupd\t{$src, $dst|$dst, $src}",
348 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
350 let canFoldAsLoad = 1, isReMaterializable = 1 in
351 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
352 "movups\t{$src, $dst|$dst, $src}",
353 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
354 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
355 "movupd\t{$src, $dst|$dst, $src}",
356 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
358 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
359 "movups\t{$src, $dst|$dst, $src}",
360 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
361 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
362 "movupd\t{$src, $dst|$dst, $src}",
363 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
365 // Move Low/High packed floating point values
366 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
367 PatFrag mov_frag, string base_opc,
369 def PSrm : PI<opc, MRMSrcMem,
370 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
371 !strconcat(base_opc, "s", asm_opr),
374 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
375 SSEPackedSingle>, TB;
377 def PDrm : PI<opc, MRMSrcMem,
378 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
379 !strconcat(base_opc, "d", asm_opr),
380 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
381 (scalar_to_vector (loadf64 addr:$src2)))))],
382 SSEPackedDouble>, TB, OpSize;
385 let isAsmParserOnly = 1, AddedComplexity = 20 in {
386 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
387 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
388 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
389 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
391 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
392 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
393 "\t{$src2, $dst|$dst, $src2}">;
394 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
395 "\t{$src2, $dst|$dst, $src2}">;
398 let isAsmParserOnly = 1 in {
399 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
400 "movlps\t{$src, $dst|$dst, $src}",
401 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
402 (iPTR 0))), addr:$dst)]>, VEX;
403 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movlpd\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract (v2f64 VR128:$src),
406 (iPTR 0))), addr:$dst)]>, VEX;
408 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movlps\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
411 (iPTR 0))), addr:$dst)]>;
412 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
413 "movlpd\t{$src, $dst|$dst, $src}",
414 [(store (f64 (vector_extract (v2f64 VR128:$src),
415 (iPTR 0))), addr:$dst)]>;
417 // v2f64 extract element 1 is always custom lowered to unpack high to low
418 // and extract element 0 so the non-store version isn't too horrible.
419 let isAsmParserOnly = 1 in {
420 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
421 "movhps\t{$src, $dst|$dst, $src}",
422 [(store (f64 (vector_extract
423 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
424 (undef)), (iPTR 0))), addr:$dst)]>,
426 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
427 "movhpd\t{$src, $dst|$dst, $src}",
428 [(store (f64 (vector_extract
429 (v2f64 (unpckh VR128:$src, (undef))),
430 (iPTR 0))), addr:$dst)]>,
433 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
434 "movhps\t{$src, $dst|$dst, $src}",
435 [(store (f64 (vector_extract
436 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
437 (undef)), (iPTR 0))), addr:$dst)]>;
438 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movhpd\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract
441 (v2f64 (unpckh VR128:$src, (undef))),
442 (iPTR 0))), addr:$dst)]>;
444 let isAsmParserOnly = 1, AddedComplexity = 20 in {
445 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
446 (ins VR128:$src1, VR128:$src2),
447 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
449 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
451 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
452 (ins VR128:$src1, VR128:$src2),
453 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
455 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
458 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
459 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
460 (ins VR128:$src1, VR128:$src2),
461 "movlhps\t{$src2, $dst|$dst, $src2}",
463 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
464 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
465 (ins VR128:$src1, VR128:$src2),
466 "movhlps\t{$src2, $dst|$dst, $src2}",
468 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
471 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
472 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
473 let AddedComplexity = 20 in {
474 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
475 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
476 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
477 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
480 //===----------------------------------------------------------------------===//
481 // SSE 1 & 2 - Conversion Instructions
482 //===----------------------------------------------------------------------===//
484 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
485 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
487 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
488 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
489 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
490 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
493 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
494 X86MemOperand x86memop, string asm> {
495 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
497 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
501 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
502 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
503 string asm, Domain d> {
504 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
505 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
506 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
507 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
510 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
511 X86MemOperand x86memop, string asm> {
512 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
513 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
514 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
515 (ins DstRC:$src1, x86memop:$src),
516 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
519 let isAsmParserOnly = 1 in {
520 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
521 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
522 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
523 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
525 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
526 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
527 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
528 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
531 // The assembler can recognize rr 64-bit instructions by seeing a rxx
532 // register, but the same isn't true when only using memory operands,
533 // provide other assembly "l" and "q" forms to address this explicitly
534 // where appropriate to do so.
535 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
537 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
539 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
541 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
543 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
547 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
548 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
549 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
550 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
551 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
552 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
553 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
554 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
555 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
556 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
557 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
558 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
559 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
560 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
561 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
562 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
564 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
565 // and/or XMM operand(s).
567 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
568 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
570 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
571 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
572 [(set DstRC:$dst, (Int SrcRC:$src))]>;
573 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
574 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
575 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
578 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
579 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
580 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
581 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
583 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
584 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
585 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
586 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
587 (ins DstRC:$src1, x86memop:$src2),
589 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
590 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
591 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
594 let isAsmParserOnly = 1 in {
595 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
596 f32mem, load, "cvtss2si">, XS, VEX;
597 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
598 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
600 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
601 f128mem, load, "cvtsd2si">, XD, VEX;
602 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
603 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
606 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
607 // Get rid of this hack or rename the intrinsics, there are several
608 // intructions that only match with the intrinsic form, why create duplicates
609 // to let them be recognized by the assembler?
610 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
611 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
612 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
613 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
615 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
616 f32mem, load, "cvtss2si">, XS;
617 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
618 f32mem, load, "cvtss2si{q}">, XS, REX_W;
619 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
620 f128mem, load, "cvtsd2si{l}">, XD;
621 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
622 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
625 let isAsmParserOnly = 1 in {
626 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
627 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
628 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
629 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
631 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
632 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
633 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
634 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
638 let Constraints = "$src1 = $dst" in {
639 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
640 int_x86_sse_cvtsi2ss, i32mem, loadi32,
642 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
643 int_x86_sse_cvtsi642ss, i64mem, loadi64,
644 "cvtsi2ss{q}">, XS, REX_W;
645 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
646 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
648 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
649 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
650 "cvtsi2sd">, XD, REX_W;
655 // Aliases for intrinsics
656 let isAsmParserOnly = 1 in {
657 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
658 f32mem, load, "cvttss2si">, XS, VEX;
659 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
660 int_x86_sse_cvttss2si64, f32mem, load,
661 "cvttss2si">, XS, VEX, VEX_W;
662 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
663 f128mem, load, "cvttsd2si">, XD, VEX;
664 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
665 int_x86_sse2_cvttsd2si64, f128mem, load,
666 "cvttsd2si">, XD, VEX, VEX_W;
668 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
669 f32mem, load, "cvttss2si">, XS;
670 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
671 int_x86_sse_cvttss2si64, f32mem, load,
672 "cvttss2si{q}">, XS, REX_W;
673 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
674 f128mem, load, "cvttsd2si">, XD;
675 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
676 int_x86_sse2_cvttsd2si64, f128mem, load,
677 "cvttsd2si{q}">, XD, REX_W;
679 let isAsmParserOnly = 1, Pattern = []<dag> in {
680 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
681 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
682 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
683 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
685 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
686 "cvtdq2ps\t{$src, $dst|$dst, $src}",
687 SSEPackedSingle>, TB, VEX;
688 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
689 "cvtdq2ps\t{$src, $dst|$dst, $src}",
690 SSEPackedSingle>, TB, VEX;
692 let Pattern = []<dag> in {
693 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
694 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
695 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
696 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
697 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
698 "cvtdq2ps\t{$src, $dst|$dst, $src}",
699 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
704 // Convert scalar double to scalar single
705 let isAsmParserOnly = 1 in {
706 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
707 (ins FR64:$src1, FR64:$src2),
708 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
710 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
711 (ins FR64:$src1, f64mem:$src2),
712 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
713 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
715 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
718 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
719 "cvtsd2ss\t{$src, $dst|$dst, $src}",
720 [(set FR32:$dst, (fround FR64:$src))]>;
721 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
722 "cvtsd2ss\t{$src, $dst|$dst, $src}",
723 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
724 Requires<[HasSSE2, OptForSize]>;
726 let isAsmParserOnly = 1 in
727 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
728 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
730 let Constraints = "$src1 = $dst" in
731 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
732 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
734 // Convert scalar single to scalar double
735 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
736 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
737 (ins FR32:$src1, FR32:$src2),
738 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
739 []>, XS, Requires<[HasAVX]>, VEX_4V;
740 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
741 (ins FR32:$src1, f32mem:$src2),
742 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
743 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
745 def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>,
748 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
749 "cvtss2sd\t{$src, $dst|$dst, $src}",
750 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
752 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
753 "cvtss2sd\t{$src, $dst|$dst, $src}",
754 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
755 Requires<[HasSSE2, OptForSize]>;
757 let isAsmParserOnly = 1 in {
758 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
759 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
760 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
761 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
762 VR128:$src2))]>, XS, VEX_4V,
764 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
765 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
766 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
767 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
768 (load addr:$src2)))]>, XS, VEX_4V,
771 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
772 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
773 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
774 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
775 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
778 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
779 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
780 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
781 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
782 (load addr:$src2)))]>, XS,
786 def : Pat<(extloadf32 addr:$src),
787 (CVTSS2SDrr (MOVSSrm addr:$src))>,
788 Requires<[HasSSE2, OptForSpeed]>;
790 // Convert doubleword to packed single/double fp
791 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
792 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
793 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
794 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
795 TB, VEX, Requires<[HasAVX]>;
796 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
797 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
798 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
799 (bitconvert (memopv2i64 addr:$src))))]>,
800 TB, VEX, Requires<[HasAVX]>;
802 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
803 "cvtdq2ps\t{$src, $dst|$dst, $src}",
804 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
805 TB, Requires<[HasSSE2]>;
806 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
807 "cvtdq2ps\t{$src, $dst|$dst, $src}",
808 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
809 (bitconvert (memopv2i64 addr:$src))))]>,
810 TB, Requires<[HasSSE2]>;
812 // FIXME: why the non-intrinsic version is described as SSE3?
813 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
814 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
815 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
816 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
817 XS, VEX, Requires<[HasAVX]>;
818 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
819 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
820 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
821 (bitconvert (memopv2i64 addr:$src))))]>,
822 XS, VEX, Requires<[HasAVX]>;
824 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
825 "cvtdq2pd\t{$src, $dst|$dst, $src}",
826 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
827 XS, Requires<[HasSSE2]>;
828 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
829 "cvtdq2pd\t{$src, $dst|$dst, $src}",
830 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
831 (bitconvert (memopv2i64 addr:$src))))]>,
832 XS, Requires<[HasSSE2]>;
835 // Convert packed single/double fp to doubleword
836 let isAsmParserOnly = 1 in {
837 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
838 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
839 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
840 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
841 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
842 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
843 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
844 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
846 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
847 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
848 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
849 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
851 let isAsmParserOnly = 1 in {
852 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
853 "cvtps2dq\t{$src, $dst|$dst, $src}",
854 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
856 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
858 "cvtps2dq\t{$src, $dst|$dst, $src}",
859 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
860 (memop addr:$src)))]>, VEX;
862 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
863 "cvtps2dq\t{$src, $dst|$dst, $src}",
864 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
865 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
866 "cvtps2dq\t{$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
868 (memop addr:$src)))]>;
870 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
871 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
872 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
873 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
874 XD, VEX, Requires<[HasAVX]>;
875 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
876 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
877 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
878 (memop addr:$src)))]>,
879 XD, VEX, Requires<[HasAVX]>;
881 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
882 "cvtpd2dq\t{$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
884 XD, Requires<[HasSSE2]>;
885 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
886 "cvtpd2dq\t{$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
888 (memop addr:$src)))]>,
889 XD, Requires<[HasSSE2]>;
892 // Convert with truncation packed single/double fp to doubleword
893 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
894 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
895 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
896 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
897 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
898 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
899 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
900 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
901 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
903 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
904 "cvttps2dq\t{$src, $dst|$dst, $src}",
906 (int_x86_sse2_cvttps2dq VR128:$src))]>;
907 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
908 "cvttps2dq\t{$src, $dst|$dst, $src}",
910 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
913 let isAsmParserOnly = 1 in {
914 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
915 "vcvttps2dq\t{$src, $dst|$dst, $src}",
917 (int_x86_sse2_cvttps2dq VR128:$src))]>,
918 XS, VEX, Requires<[HasAVX]>;
919 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
920 "vcvttps2dq\t{$src, $dst|$dst, $src}",
921 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
922 (memop addr:$src)))]>,
923 XS, VEX, Requires<[HasAVX]>;
926 let isAsmParserOnly = 1 in {
927 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
929 "cvttpd2dq\t{$src, $dst|$dst, $src}",
930 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
932 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
934 "cvttpd2dq\t{$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
936 (memop addr:$src)))]>, VEX;
938 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
939 "cvttpd2dq\t{$src, $dst|$dst, $src}",
940 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
941 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
942 "cvttpd2dq\t{$src, $dst|$dst, $src}",
943 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
944 (memop addr:$src)))]>;
946 let isAsmParserOnly = 1 in {
947 // The assembler can recognize rr 256-bit instructions by seeing a ymm
948 // register, but the same isn't true when using memory operands instead.
949 // Provide other assembly rr and rm forms to address this explicitly.
950 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
951 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
952 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
953 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
956 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
963 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
964 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
965 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
968 // Convert packed single to packed double
969 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
970 // SSE2 instructions without OpSize prefix
971 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
972 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
973 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
974 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
975 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
976 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
977 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
978 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
980 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
981 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
982 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
983 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
985 let isAsmParserOnly = 1 in {
986 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
987 "vcvtps2pd\t{$src, $dst|$dst, $src}",
988 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
989 VEX, Requires<[HasAVX]>;
990 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
991 "vcvtps2pd\t{$src, $dst|$dst, $src}",
992 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
993 (load addr:$src)))]>,
994 VEX, Requires<[HasAVX]>;
996 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
997 "cvtps2pd\t{$src, $dst|$dst, $src}",
998 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
999 TB, Requires<[HasSSE2]>;
1000 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1001 "cvtps2pd\t{$src, $dst|$dst, $src}",
1002 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1003 (load addr:$src)))]>,
1004 TB, Requires<[HasSSE2]>;
1006 // Convert packed double to packed single
1007 let isAsmParserOnly = 1 in {
1008 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1009 // register, but the same isn't true when using memory operands instead.
1010 // Provide other assembly rr and rm forms to address this explicitly.
1011 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1012 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1013 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1014 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1017 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1018 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1019 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1020 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1023 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1024 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1025 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1026 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1028 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1029 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1030 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1031 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1034 let isAsmParserOnly = 1 in {
1035 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1036 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1037 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1038 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1040 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1041 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1042 (memop addr:$src)))]>;
1044 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1045 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1046 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1047 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1048 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1049 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1050 (memop addr:$src)))]>;
1052 // AVX 256-bit register conversion intrinsics
1053 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
1054 // whenever possible to avoid declaring two versions of each one.
1055 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
1056 (VCVTDQ2PSYrr VR256:$src)>;
1057 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
1058 (VCVTDQ2PSYrm addr:$src)>;
1060 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
1061 (VCVTPD2PSYrr VR256:$src)>;
1062 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
1063 (VCVTPD2PSYrm addr:$src)>;
1065 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1066 (VCVTPS2DQYrr VR256:$src)>;
1067 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1068 (VCVTPS2DQYrm addr:$src)>;
1070 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1071 (VCVTPS2PDYrr VR128:$src)>;
1072 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1073 (VCVTPS2PDYrm addr:$src)>;
1075 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1076 (VCVTTPD2DQYrr VR256:$src)>;
1077 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1078 (VCVTTPD2DQYrm addr:$src)>;
1080 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1081 (VCVTTPS2DQYrr VR256:$src)>;
1082 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1083 (VCVTTPS2DQYrm addr:$src)>;
1085 //===----------------------------------------------------------------------===//
1086 // SSE 1 & 2 - Compare Instructions
1087 //===----------------------------------------------------------------------===//
1089 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1090 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1091 string asm, string asm_alt> {
1092 def rr : SIi8<0xC2, MRMSrcReg,
1093 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1096 def rm : SIi8<0xC2, MRMSrcMem,
1097 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1099 // Accept explicit immediate argument form instead of comparison code.
1100 let isAsmParserOnly = 1 in {
1101 def rr_alt : SIi8<0xC2, MRMSrcReg,
1102 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1105 def rm_alt : SIi8<0xC2, MRMSrcMem,
1106 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1111 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1112 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1113 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1114 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1116 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1117 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1118 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1122 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1123 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1124 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1125 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1126 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1127 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1128 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1131 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1132 Intrinsic Int, string asm> {
1133 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1134 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1135 [(set VR128:$dst, (Int VR128:$src1,
1136 VR128:$src, imm:$cc))]>;
1137 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1138 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1139 [(set VR128:$dst, (Int VR128:$src1,
1140 (load addr:$src), imm:$cc))]>;
1143 // Aliases to match intrinsics which expect XMM operand(s).
1144 let isAsmParserOnly = 1 in {
1145 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1146 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1148 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1149 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1152 let Constraints = "$src1 = $dst" in {
1153 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1154 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1155 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1156 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1160 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1161 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1162 ValueType vt, X86MemOperand x86memop,
1163 PatFrag ld_frag, string OpcodeStr, Domain d> {
1164 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1165 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1166 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1167 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1168 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1169 [(set EFLAGS, (OpNode (vt RC:$src1),
1170 (ld_frag addr:$src2)))], d>;
1173 let Defs = [EFLAGS] in {
1174 let isAsmParserOnly = 1 in {
1175 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1176 "ucomiss", SSEPackedSingle>, VEX;
1177 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1178 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1179 let Pattern = []<dag> in {
1180 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1181 "comiss", SSEPackedSingle>, VEX;
1182 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1183 "comisd", SSEPackedDouble>, OpSize, VEX;
1186 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1187 load, "ucomiss", SSEPackedSingle>, VEX;
1188 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1189 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1191 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1192 load, "comiss", SSEPackedSingle>, VEX;
1193 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1194 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1196 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1197 "ucomiss", SSEPackedSingle>, TB;
1198 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1199 "ucomisd", SSEPackedDouble>, TB, OpSize;
1201 let Pattern = []<dag> in {
1202 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1203 "comiss", SSEPackedSingle>, TB;
1204 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1205 "comisd", SSEPackedDouble>, TB, OpSize;
1208 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1209 load, "ucomiss", SSEPackedSingle>, TB;
1210 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1211 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1213 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1214 "comiss", SSEPackedSingle>, TB;
1215 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1216 "comisd", SSEPackedDouble>, TB, OpSize;
1217 } // Defs = [EFLAGS]
1219 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1220 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1221 Intrinsic Int, string asm, string asm_alt,
1223 def rri : PIi8<0xC2, MRMSrcReg,
1224 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1225 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1226 def rmi : PIi8<0xC2, MRMSrcMem,
1227 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1228 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1229 // Accept explicit immediate argument form instead of comparison code.
1230 let isAsmParserOnly = 1 in {
1231 def rri_alt : PIi8<0xC2, MRMSrcReg,
1232 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1234 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1235 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1240 let isAsmParserOnly = 1 in {
1241 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1242 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1243 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1244 SSEPackedSingle>, VEX_4V;
1245 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1246 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1247 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1248 SSEPackedDouble>, OpSize, VEX_4V;
1249 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1250 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1251 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1252 SSEPackedSingle>, VEX_4V;
1253 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1254 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1255 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1256 SSEPackedDouble>, OpSize, VEX_4V;
1258 let Constraints = "$src1 = $dst" in {
1259 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1260 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1261 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1262 SSEPackedSingle>, TB;
1263 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1264 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1265 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1266 SSEPackedDouble>, TB, OpSize;
1269 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1270 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1271 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1272 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1273 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1274 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1275 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1276 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1278 //===----------------------------------------------------------------------===//
1279 // SSE 1 & 2 - Shuffle Instructions
1280 //===----------------------------------------------------------------------===//
1282 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1283 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1284 ValueType vt, string asm, PatFrag mem_frag,
1285 Domain d, bit IsConvertibleToThreeAddress = 0> {
1286 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1287 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1288 [(set RC:$dst, (vt (shufp:$src3
1289 RC:$src1, (mem_frag addr:$src2))))], d>;
1290 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1291 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1292 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1294 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1297 let isAsmParserOnly = 1 in {
1298 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1299 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1300 memopv4f32, SSEPackedSingle>, VEX_4V;
1301 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1302 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1303 memopv8f32, SSEPackedSingle>, VEX_4V;
1304 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1305 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1306 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1307 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1308 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1309 memopv4f64, SSEPackedDouble>, OpSize, VEX_4V;
1312 let Constraints = "$src1 = $dst" in {
1313 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1314 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1315 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1317 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1318 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1319 memopv2f64, SSEPackedDouble>, TB, OpSize;
1322 //===----------------------------------------------------------------------===//
1323 // SSE 1 & 2 - Unpack Instructions
1324 //===----------------------------------------------------------------------===//
1326 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1327 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1328 PatFrag mem_frag, RegisterClass RC,
1329 X86MemOperand x86memop, string asm,
1331 def rr : PI<opc, MRMSrcReg,
1332 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1334 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1335 def rm : PI<opc, MRMSrcMem,
1336 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1338 (vt (OpNode RC:$src1,
1339 (mem_frag addr:$src2))))], d>;
1342 let AddedComplexity = 10 in {
1343 let isAsmParserOnly = 1 in {
1344 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1345 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1346 SSEPackedSingle>, VEX_4V;
1347 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1348 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1349 SSEPackedDouble>, OpSize, VEX_4V;
1350 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1351 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1352 SSEPackedSingle>, VEX_4V;
1353 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1354 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1355 SSEPackedDouble>, OpSize, VEX_4V;
1357 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1358 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1359 SSEPackedSingle>, VEX_4V;
1360 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1361 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1362 SSEPackedDouble>, OpSize, VEX_4V;
1363 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1364 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1365 SSEPackedSingle>, VEX_4V;
1366 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1367 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1368 SSEPackedDouble>, OpSize, VEX_4V;
1371 let Constraints = "$src1 = $dst" in {
1372 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1373 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1374 SSEPackedSingle>, TB;
1375 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1376 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1377 SSEPackedDouble>, TB, OpSize;
1378 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1379 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1380 SSEPackedSingle>, TB;
1381 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1382 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1383 SSEPackedDouble>, TB, OpSize;
1384 } // Constraints = "$src1 = $dst"
1385 } // AddedComplexity
1387 //===----------------------------------------------------------------------===//
1388 // SSE 1 & 2 - Extract Floating-Point Sign mask
1389 //===----------------------------------------------------------------------===//
1391 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1392 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1394 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1395 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1396 [(set GR32:$dst, (Int RC:$src))], d>;
1397 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1398 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1402 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1403 SSEPackedSingle>, TB;
1404 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1405 SSEPackedDouble>, TB, OpSize;
1407 let isAsmParserOnly = 1 in {
1408 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1409 "movmskps", SSEPackedSingle>, VEX;
1410 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1411 "movmskpd", SSEPackedDouble>, OpSize,
1413 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1414 "movmskps", SSEPackedSingle>, VEX;
1415 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1416 "movmskpd", SSEPackedDouble>, OpSize,
1420 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1421 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1422 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1423 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1425 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1426 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1427 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1428 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1432 //===----------------------------------------------------------------------===//
1433 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1434 //===----------------------------------------------------------------------===//
1436 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1437 // names that start with 'Fs'.
1439 // Alias instructions that map fld0 to pxor for sse.
1440 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1441 canFoldAsLoad = 1 in {
1442 // FIXME: Set encoding to pseudo!
1443 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1444 [(set FR32:$dst, fp32imm0)]>,
1445 Requires<[HasSSE1]>, TB, OpSize;
1446 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1447 [(set FR64:$dst, fpimm0)]>,
1448 Requires<[HasSSE2]>, TB, OpSize;
1449 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1450 [(set FR32:$dst, fp32imm0)]>,
1451 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1452 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1453 [(set FR64:$dst, fpimm0)]>,
1454 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1457 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1458 // bits are disregarded.
1459 let neverHasSideEffects = 1 in {
1460 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1461 "movaps\t{$src, $dst|$dst, $src}", []>;
1462 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1463 "movapd\t{$src, $dst|$dst, $src}", []>;
1466 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1467 // bits are disregarded.
1468 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1469 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1470 "movaps\t{$src, $dst|$dst, $src}",
1471 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1472 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1473 "movapd\t{$src, $dst|$dst, $src}",
1474 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1477 //===----------------------------------------------------------------------===//
1478 // SSE 1 & 2 - Logical Instructions
1479 //===----------------------------------------------------------------------===//
1481 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1483 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1485 let isAsmParserOnly = 1 in {
1486 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1487 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1489 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1490 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1493 let Constraints = "$src1 = $dst" in {
1494 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1495 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1497 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1498 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1502 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1503 let mayLoad = 0 in {
1504 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1505 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1506 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1509 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1510 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1512 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1514 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1515 SDNode OpNode, int HasPat = 0,
1516 list<list<dag>> Pattern = []> {
1517 let isAsmParserOnly = 1, Pattern = []<dag> in {
1518 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1519 !strconcat(OpcodeStr, "ps"), f128mem,
1520 !if(HasPat, Pattern[0], // rr
1521 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1523 !if(HasPat, Pattern[2], // rm
1524 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1525 (memopv2i64 addr:$src2)))]), 0>,
1528 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1529 !strconcat(OpcodeStr, "pd"), f128mem,
1530 !if(HasPat, Pattern[1], // rr
1531 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1534 !if(HasPat, Pattern[3], // rm
1535 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1536 (memopv2i64 addr:$src2)))]), 0>,
1539 let Constraints = "$src1 = $dst" in {
1540 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1541 !strconcat(OpcodeStr, "ps"), f128mem,
1542 !if(HasPat, Pattern[0], // rr
1543 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1545 !if(HasPat, Pattern[2], // rm
1546 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1547 (memopv2i64 addr:$src2)))])>, TB;
1549 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1550 !strconcat(OpcodeStr, "pd"), f128mem,
1551 !if(HasPat, Pattern[1], // rr
1552 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1555 !if(HasPat, Pattern[3], // rm
1556 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1557 (memopv2i64 addr:$src2)))])>,
1562 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1564 let isAsmParserOnly = 1 in {
1565 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1566 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1567 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1569 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1570 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1574 // AVX 256-bit packed logical ops forms
1575 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1576 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1577 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1578 let isCommutable = 0 in
1579 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1581 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1582 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1583 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1584 let isCommutable = 0 in
1585 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1587 [(set VR128:$dst, (X86pandn VR128:$src1, VR128:$src2))],
1591 [(set VR128:$dst, (X86pandn VR128:$src1, (memopv2i64 addr:$src2)))],
1595 //===----------------------------------------------------------------------===//
1596 // SSE 1 & 2 - Arithmetic Instructions
1597 //===----------------------------------------------------------------------===//
1599 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1602 /// In addition, we also have a special variant of the scalar form here to
1603 /// represent the associated intrinsic operation. This form is unlike the
1604 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1605 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1607 /// These three forms can each be reg+reg or reg+mem.
1610 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1612 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1614 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1615 OpNode, FR32, f32mem, Is2Addr>, XS;
1616 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1617 OpNode, FR64, f64mem, Is2Addr>, XD;
1620 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1622 let mayLoad = 0 in {
1623 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1624 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1625 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1626 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1630 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1632 let mayLoad = 0 in {
1633 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1634 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1635 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1636 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1640 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1642 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1643 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1644 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1645 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1648 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1650 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1651 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1652 SSEPackedSingle, Is2Addr>, TB;
1654 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1655 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1656 SSEPackedDouble, Is2Addr>, TB, OpSize;
1659 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1660 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1661 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1662 SSEPackedSingle, 0>, TB;
1664 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1665 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1666 SSEPackedDouble, 0>, TB, OpSize;
1669 // Binary Arithmetic instructions
1670 let isAsmParserOnly = 1 in {
1671 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1672 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1673 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1674 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1675 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1676 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1677 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1678 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1680 let isCommutable = 0 in {
1681 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1682 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1683 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1684 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1685 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1686 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1687 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1688 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1689 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1690 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1691 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1692 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1693 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1694 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1695 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1696 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1697 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1698 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1699 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1700 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1704 let Constraints = "$src1 = $dst" in {
1705 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1706 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1707 basic_sse12_fp_binop_s_int<0x58, "add">;
1708 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1709 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1710 basic_sse12_fp_binop_s_int<0x59, "mul">;
1712 let isCommutable = 0 in {
1713 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1714 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1715 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1716 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1717 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1718 basic_sse12_fp_binop_s_int<0x5E, "div">;
1719 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1720 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1721 basic_sse12_fp_binop_s_int<0x5F, "max">,
1722 basic_sse12_fp_binop_p_int<0x5F, "max">;
1723 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1724 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1725 basic_sse12_fp_binop_s_int<0x5D, "min">,
1726 basic_sse12_fp_binop_p_int<0x5D, "min">;
1731 /// In addition, we also have a special variant of the scalar form here to
1732 /// represent the associated intrinsic operation. This form is unlike the
1733 /// plain scalar form, in that it takes an entire vector (instead of a
1734 /// scalar) and leaves the top elements undefined.
1736 /// And, we have a special variant form for a full-vector intrinsic form.
1738 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1739 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1740 SDNode OpNode, Intrinsic F32Int> {
1741 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1742 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1743 [(set FR32:$dst, (OpNode FR32:$src))]>;
1744 // For scalar unary operations, fold a load into the operation
1745 // only in OptForSize mode. It eliminates an instruction, but it also
1746 // eliminates a whole-register clobber (the load), so it introduces a
1747 // partial register update condition.
1748 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1749 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1750 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1751 Requires<[HasSSE1, OptForSize]>;
1752 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1753 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1754 [(set VR128:$dst, (F32Int VR128:$src))]>;
1755 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1756 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1757 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1760 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1761 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1762 SDNode OpNode, Intrinsic F32Int> {
1763 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1764 !strconcat(OpcodeStr,
1765 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1766 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1767 !strconcat(OpcodeStr,
1768 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1769 []>, XS, Requires<[HasAVX, OptForSize]>;
1770 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1771 !strconcat(OpcodeStr,
1772 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1773 [(set VR128:$dst, (F32Int VR128:$src))]>;
1774 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1775 !strconcat(OpcodeStr,
1776 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1777 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1780 /// sse1_fp_unop_p - SSE1 unops in packed form.
1781 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1782 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1783 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1784 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1785 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1786 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1787 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1790 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1791 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1792 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1793 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1794 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1795 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1796 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1797 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1800 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1801 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1802 Intrinsic V4F32Int> {
1803 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1804 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1805 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1806 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1807 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1808 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1811 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1812 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1813 Intrinsic V4F32Int> {
1814 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1815 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1816 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1817 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1818 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1819 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1822 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1823 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1824 SDNode OpNode, Intrinsic F64Int> {
1825 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1826 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1827 [(set FR64:$dst, (OpNode FR64:$src))]>;
1828 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1829 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1830 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1831 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1832 Requires<[HasSSE2, OptForSize]>;
1833 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1834 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1835 [(set VR128:$dst, (F64Int VR128:$src))]>;
1836 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1837 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1838 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1841 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1842 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1843 SDNode OpNode, Intrinsic F64Int> {
1844 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1845 !strconcat(OpcodeStr,
1846 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1847 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1848 (ins FR64:$src1, f64mem:$src2),
1849 !strconcat(OpcodeStr,
1850 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1851 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1852 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1853 [(set VR128:$dst, (F64Int VR128:$src))]>;
1854 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1855 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1856 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1859 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1860 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1862 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1863 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1864 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1865 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1866 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1867 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1870 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1871 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1872 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1873 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1874 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1875 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1876 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1877 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1880 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1881 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1882 Intrinsic V2F64Int> {
1883 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1884 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1885 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1886 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1887 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1888 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1891 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1892 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1893 Intrinsic V2F64Int> {
1894 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1895 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1896 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1897 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1898 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1899 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1902 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1904 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1905 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1908 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1909 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1910 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1911 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1912 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1913 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1914 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1915 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1918 // Reciprocal approximations. Note that these typically require refinement
1919 // in order to obtain suitable precision.
1920 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1921 int_x86_sse_rsqrt_ss>, VEX_4V;
1922 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1923 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1924 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1925 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1927 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1929 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1930 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1931 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1932 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1936 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1937 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1938 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1939 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1940 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1941 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1943 // Reciprocal approximations. Note that these typically require refinement
1944 // in order to obtain suitable precision.
1945 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1946 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1947 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1948 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1949 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1950 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1952 // There is no f64 version of the reciprocal approximation instructions.
1954 //===----------------------------------------------------------------------===//
1955 // SSE 1 & 2 - Non-temporal stores
1956 //===----------------------------------------------------------------------===//
1958 let isAsmParserOnly = 1 in {
1959 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
1960 (ins i128mem:$dst, VR128:$src),
1961 "movntps\t{$src, $dst|$dst, $src}",
1962 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
1963 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
1964 (ins i128mem:$dst, VR128:$src),
1965 "movntpd\t{$src, $dst|$dst, $src}",
1966 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
1968 let ExeDomain = SSEPackedInt in
1969 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
1970 (ins f128mem:$dst, VR128:$src),
1971 "movntdq\t{$src, $dst|$dst, $src}",
1972 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
1974 let AddedComplexity = 400 in { // Prefer non-temporal versions
1975 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1976 (ins f128mem:$dst, VR128:$src),
1977 "movntps\t{$src, $dst|$dst, $src}",
1978 [(alignednontemporalstore (v4f32 VR128:$src),
1980 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1981 (ins f128mem:$dst, VR128:$src),
1982 "movntpd\t{$src, $dst|$dst, $src}",
1983 [(alignednontemporalstore (v2f64 VR128:$src),
1985 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1986 (ins f128mem:$dst, VR128:$src),
1987 "movntdq\t{$src, $dst|$dst, $src}",
1988 [(alignednontemporalstore (v2f64 VR128:$src),
1990 let ExeDomain = SSEPackedInt in
1991 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1992 (ins f128mem:$dst, VR128:$src),
1993 "movntdq\t{$src, $dst|$dst, $src}",
1994 [(alignednontemporalstore (v4f32 VR128:$src),
1997 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1998 (ins f256mem:$dst, VR256:$src),
1999 "movntps\t{$src, $dst|$dst, $src}",
2000 [(alignednontemporalstore (v8f32 VR256:$src),
2002 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2003 (ins f256mem:$dst, VR256:$src),
2004 "movntpd\t{$src, $dst|$dst, $src}",
2005 [(alignednontemporalstore (v4f64 VR256:$src),
2007 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2008 (ins f256mem:$dst, VR256:$src),
2009 "movntdq\t{$src, $dst|$dst, $src}",
2010 [(alignednontemporalstore (v4f64 VR256:$src),
2012 let ExeDomain = SSEPackedInt in
2013 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2014 (ins f256mem:$dst, VR256:$src),
2015 "movntdq\t{$src, $dst|$dst, $src}",
2016 [(alignednontemporalstore (v8f32 VR256:$src),
2021 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
2022 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
2023 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
2024 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
2025 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
2026 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
2028 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2029 "movntps\t{$src, $dst|$dst, $src}",
2030 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2031 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2032 "movntpd\t{$src, $dst|$dst, $src}",
2033 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2035 let ExeDomain = SSEPackedInt in
2036 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2037 "movntdq\t{$src, $dst|$dst, $src}",
2038 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2040 let AddedComplexity = 400 in { // Prefer non-temporal versions
2041 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2042 "movntps\t{$src, $dst|$dst, $src}",
2043 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2044 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2045 "movntpd\t{$src, $dst|$dst, $src}",
2046 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2048 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2049 "movntdq\t{$src, $dst|$dst, $src}",
2050 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2052 let ExeDomain = SSEPackedInt in
2053 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2054 "movntdq\t{$src, $dst|$dst, $src}",
2055 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2057 // There is no AVX form for instructions below this point
2058 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2059 "movnti\t{$src, $dst|$dst, $src}",
2060 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2061 TB, Requires<[HasSSE2]>;
2063 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2064 "movnti\t{$src, $dst|$dst, $src}",
2065 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2066 TB, Requires<[HasSSE2]>;
2069 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2070 "movnti\t{$src, $dst|$dst, $src}",
2071 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2072 TB, Requires<[HasSSE2]>;
2074 //===----------------------------------------------------------------------===//
2075 // SSE 1 & 2 - Misc Instructions (No AVX form)
2076 //===----------------------------------------------------------------------===//
2078 // Prefetch intrinsic.
2079 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2080 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2081 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2082 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2083 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2084 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2085 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2086 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2088 // Load, store, and memory fence
2089 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2090 TB, Requires<[HasSSE1]>;
2091 def : Pat<(X86SFence), (SFENCE)>;
2093 // Alias instructions that map zero vector to pxor / xorp* for sse.
2094 // We set canFoldAsLoad because this can be converted to a constant-pool
2095 // load of an all-zeros value if folding it would be beneficial.
2096 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2097 // JIT implementation, it does not expand the instructions below like
2098 // X86MCInstLower does.
2099 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2100 isCodeGenOnly = 1 in {
2101 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2102 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2103 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2104 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2105 let ExeDomain = SSEPackedInt in
2106 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2107 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2110 // The same as done above but for AVX. The 128-bit versions are the
2111 // same, but re-encoded. The 256-bit does not support PI version.
2112 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2113 // JIT implementatioan, it does not expand the instructions below like
2114 // X86MCInstLower does.
2115 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2116 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2117 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2118 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2119 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2120 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2121 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2122 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2123 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2124 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2125 let ExeDomain = SSEPackedInt in
2126 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2127 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2130 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2131 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2132 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2134 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2135 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2137 //===----------------------------------------------------------------------===//
2138 // SSE 1 & 2 - Load/Store XCSR register
2139 //===----------------------------------------------------------------------===//
2141 let isAsmParserOnly = 1 in {
2142 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2143 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2144 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2145 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2148 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2149 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2150 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2151 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2153 //===---------------------------------------------------------------------===//
2154 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2155 //===---------------------------------------------------------------------===//
2157 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2159 let isAsmParserOnly = 1 in {
2160 let neverHasSideEffects = 1 in {
2161 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2162 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2163 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2164 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2166 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2167 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2168 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2169 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2171 let canFoldAsLoad = 1, mayLoad = 1 in {
2172 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2173 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2174 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2175 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2176 let Predicates = [HasAVX] in {
2177 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2178 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2179 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2180 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2184 let mayStore = 1 in {
2185 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2186 (ins i128mem:$dst, VR128:$src),
2187 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2188 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2189 (ins i256mem:$dst, VR256:$src),
2190 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2191 let Predicates = [HasAVX] in {
2192 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2193 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2194 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2195 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2200 let neverHasSideEffects = 1 in
2201 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2202 "movdqa\t{$src, $dst|$dst, $src}", []>;
2204 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2205 "movdqu\t{$src, $dst|$dst, $src}",
2206 []>, XS, Requires<[HasSSE2]>;
2208 let canFoldAsLoad = 1, mayLoad = 1 in {
2209 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2210 "movdqa\t{$src, $dst|$dst, $src}",
2211 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2212 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2213 "movdqu\t{$src, $dst|$dst, $src}",
2214 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2215 XS, Requires<[HasSSE2]>;
2218 let mayStore = 1 in {
2219 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2220 "movdqa\t{$src, $dst|$dst, $src}",
2221 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2222 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2223 "movdqu\t{$src, $dst|$dst, $src}",
2224 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2225 XS, Requires<[HasSSE2]>;
2228 // Intrinsic forms of MOVDQU load and store
2229 let isAsmParserOnly = 1 in {
2230 let canFoldAsLoad = 1 in
2231 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2232 "vmovdqu\t{$src, $dst|$dst, $src}",
2233 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2234 XS, VEX, Requires<[HasAVX]>;
2235 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2236 "vmovdqu\t{$src, $dst|$dst, $src}",
2237 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2238 XS, VEX, Requires<[HasAVX]>;
2241 let canFoldAsLoad = 1 in
2242 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2243 "movdqu\t{$src, $dst|$dst, $src}",
2244 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2245 XS, Requires<[HasSSE2]>;
2246 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2247 "movdqu\t{$src, $dst|$dst, $src}",
2248 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2249 XS, Requires<[HasSSE2]>;
2251 } // ExeDomain = SSEPackedInt
2253 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2254 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2255 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2257 //===---------------------------------------------------------------------===//
2258 // SSE2 - Packed Integer Arithmetic Instructions
2259 //===---------------------------------------------------------------------===//
2261 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2263 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2264 bit IsCommutable = 0, bit Is2Addr = 1> {
2265 let isCommutable = IsCommutable in
2266 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2267 (ins VR128:$src1, VR128:$src2),
2269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2271 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2272 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2273 (ins VR128:$src1, i128mem:$src2),
2275 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2276 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2277 [(set VR128:$dst, (IntId VR128:$src1,
2278 (bitconvert (memopv2i64 addr:$src2))))]>;
2281 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2282 string OpcodeStr, Intrinsic IntId,
2283 Intrinsic IntId2, bit Is2Addr = 1> {
2284 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2285 (ins VR128:$src1, VR128:$src2),
2287 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2289 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2290 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2291 (ins VR128:$src1, i128mem:$src2),
2293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2295 [(set VR128:$dst, (IntId VR128:$src1,
2296 (bitconvert (memopv2i64 addr:$src2))))]>;
2297 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2298 (ins VR128:$src1, i32i8imm:$src2),
2300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2302 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2305 /// PDI_binop_rm - Simple SSE2 binary operator.
2306 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2307 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2308 let isCommutable = IsCommutable in
2309 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2310 (ins VR128:$src1, VR128:$src2),
2312 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2314 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2315 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2316 (ins VR128:$src1, i128mem:$src2),
2318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2320 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2321 (bitconvert (memopv2i64 addr:$src2)))))]>;
2324 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2326 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2327 /// to collapse (bitconvert VT to VT) into its operand.
2329 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2330 bit IsCommutable = 0, bit Is2Addr = 1> {
2331 let isCommutable = IsCommutable in
2332 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2333 (ins VR128:$src1, VR128:$src2),
2335 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2337 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2338 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2339 (ins VR128:$src1, i128mem:$src2),
2341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2343 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2346 } // ExeDomain = SSEPackedInt
2348 // 128-bit Integer Arithmetic
2350 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2351 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2352 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2353 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2354 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2355 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2356 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2357 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2358 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2359 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2362 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2364 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2366 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2368 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2370 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2372 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2374 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2376 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2378 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2380 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2382 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2384 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2386 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2388 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2390 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2392 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2394 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2396 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2398 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2402 let Constraints = "$src1 = $dst" in {
2403 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2404 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2405 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2406 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2407 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2408 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2409 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2410 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2411 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2414 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2415 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2416 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2417 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2418 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2419 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2420 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2421 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2422 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2423 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2424 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2425 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2426 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2427 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2428 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2429 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2430 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2431 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2432 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2434 } // Constraints = "$src1 = $dst"
2436 //===---------------------------------------------------------------------===//
2437 // SSE2 - Packed Integer Logical Instructions
2438 //===---------------------------------------------------------------------===//
2440 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2441 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2442 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2444 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2445 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2447 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2448 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2451 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2452 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2454 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2455 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2457 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2458 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2461 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2462 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2464 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2465 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2468 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2469 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2470 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2472 let ExeDomain = SSEPackedInt in {
2473 let neverHasSideEffects = 1 in {
2474 // 128-bit logical shifts.
2475 def VPSLLDQri : PDIi8<0x73, MRM7r,
2476 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2477 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2479 def VPSRLDQri : PDIi8<0x73, MRM3r,
2480 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2481 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2483 // PSRADQri doesn't exist in SSE[1-3].
2485 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2486 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2487 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2488 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2489 VR128:$src2)))]>, VEX_4V;
2491 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2492 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2493 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2494 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2495 (memopv2i64 addr:$src2))))]>,
2500 let Constraints = "$src1 = $dst" in {
2501 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2502 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2503 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2504 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2505 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2506 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2508 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2509 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2510 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2511 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2512 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2513 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2515 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2516 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2517 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2518 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2520 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2521 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2522 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2524 let ExeDomain = SSEPackedInt in {
2525 let neverHasSideEffects = 1 in {
2526 // 128-bit logical shifts.
2527 def PSLLDQri : PDIi8<0x73, MRM7r,
2528 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2529 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2530 def PSRLDQri : PDIi8<0x73, MRM3r,
2531 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2532 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2533 // PSRADQri doesn't exist in SSE[1-3].
2535 def PANDNrr : PDI<0xDF, MRMSrcReg,
2536 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2537 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2539 def PANDNrm : PDI<0xDF, MRMSrcMem,
2540 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2541 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2543 } // Constraints = "$src1 = $dst"
2545 let Predicates = [HasAVX] in {
2546 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2547 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2548 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2549 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2550 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2551 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2552 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2553 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2554 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2555 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2557 // Shift up / down and insert zero's.
2558 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2559 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2560 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2561 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2564 let Predicates = [HasSSE2] in {
2565 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2566 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2567 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2568 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2569 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2570 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2571 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2572 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2573 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2574 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2576 // Shift up / down and insert zero's.
2577 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2578 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2579 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2580 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2583 //===---------------------------------------------------------------------===//
2584 // SSE2 - Packed Integer Comparison Instructions
2585 //===---------------------------------------------------------------------===//
2587 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2588 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2590 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2592 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2594 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2596 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2598 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2602 let Constraints = "$src1 = $dst" in {
2603 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2604 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2605 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2606 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2607 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2608 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2609 } // Constraints = "$src1 = $dst"
2611 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2612 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2613 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2614 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2615 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2616 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2617 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2618 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2619 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2620 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2621 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2622 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2624 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2625 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2626 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2627 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2628 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2629 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2630 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2631 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2632 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2633 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2634 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2635 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2637 //===---------------------------------------------------------------------===//
2638 // SSE2 - Packed Integer Pack Instructions
2639 //===---------------------------------------------------------------------===//
2641 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2642 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2644 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2646 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2650 let Constraints = "$src1 = $dst" in {
2651 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2652 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2653 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2654 } // Constraints = "$src1 = $dst"
2656 //===---------------------------------------------------------------------===//
2657 // SSE2 - Packed Integer Shuffle Instructions
2658 //===---------------------------------------------------------------------===//
2660 let ExeDomain = SSEPackedInt in {
2661 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2663 def ri : Ii8<0x70, MRMSrcReg,
2664 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2665 !strconcat(OpcodeStr,
2666 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2667 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2669 def mi : Ii8<0x70, MRMSrcMem,
2670 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2671 !strconcat(OpcodeStr,
2672 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2673 [(set VR128:$dst, (vt (pshuf_frag:$src2
2674 (bc_frag (memopv2i64 addr:$src1)),
2677 } // ExeDomain = SSEPackedInt
2679 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2680 let AddedComplexity = 5 in
2681 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2684 // SSE2 with ImmT == Imm8 and XS prefix.
2685 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2688 // SSE2 with ImmT == Imm8 and XD prefix.
2689 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2693 let Predicates = [HasSSE2] in {
2694 let AddedComplexity = 5 in
2695 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2697 // SSE2 with ImmT == Imm8 and XS prefix.
2698 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2700 // SSE2 with ImmT == Imm8 and XD prefix.
2701 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2704 //===---------------------------------------------------------------------===//
2705 // SSE2 - Packed Integer Unpack Instructions
2706 //===---------------------------------------------------------------------===//
2708 let ExeDomain = SSEPackedInt in {
2709 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2710 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2711 def rr : PDI<opc, MRMSrcReg,
2712 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2714 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2715 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2716 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2717 def rm : PDI<opc, MRMSrcMem,
2718 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2720 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2721 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2722 [(set VR128:$dst, (unp_frag VR128:$src1,
2723 (bc_frag (memopv2i64
2727 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2728 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2730 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2732 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2735 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2736 /// knew to collapse (bitconvert VT to VT) into its operand.
2737 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2738 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2739 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2741 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2742 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2743 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2744 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2746 (v2i64 (unpckl VR128:$src1,
2747 (memopv2i64 addr:$src2))))]>, VEX_4V;
2749 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2751 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2753 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2756 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2757 /// knew to collapse (bitconvert VT to VT) into its operand.
2758 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2759 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2760 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2762 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2763 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2764 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2765 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2767 (v2i64 (unpckh VR128:$src1,
2768 (memopv2i64 addr:$src2))))]>, VEX_4V;
2771 let Constraints = "$src1 = $dst" in {
2772 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2773 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2774 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2776 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2777 /// knew to collapse (bitconvert VT to VT) into its operand.
2778 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2779 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2780 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2782 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2783 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2784 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2785 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2787 (v2i64 (unpckl VR128:$src1,
2788 (memopv2i64 addr:$src2))))]>;
2790 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2791 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2792 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2794 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2795 /// knew to collapse (bitconvert VT to VT) into its operand.
2796 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2797 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2798 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2800 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2801 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2802 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2803 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2805 (v2i64 (unpckh VR128:$src1,
2806 (memopv2i64 addr:$src2))))]>;
2809 } // ExeDomain = SSEPackedInt
2811 //===---------------------------------------------------------------------===//
2812 // SSE2 - Packed Integer Extract and Insert
2813 //===---------------------------------------------------------------------===//
2815 let ExeDomain = SSEPackedInt in {
2816 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2817 def rri : Ii8<0xC4, MRMSrcReg,
2818 (outs VR128:$dst), (ins VR128:$src1,
2819 GR32:$src2, i32i8imm:$src3),
2821 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2822 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2824 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2825 def rmi : Ii8<0xC4, MRMSrcMem,
2826 (outs VR128:$dst), (ins VR128:$src1,
2827 i16mem:$src2, i32i8imm:$src3),
2829 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2830 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2832 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2837 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2838 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2839 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2840 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2841 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2842 imm:$src2))]>, OpSize, VEX;
2843 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2844 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2845 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2846 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2850 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2851 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2852 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2853 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2854 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2855 []>, OpSize, VEX_4V;
2858 let Constraints = "$src1 = $dst" in
2859 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2861 } // ExeDomain = SSEPackedInt
2863 //===---------------------------------------------------------------------===//
2864 // SSE2 - Packed Mask Creation
2865 //===---------------------------------------------------------------------===//
2867 let ExeDomain = SSEPackedInt in {
2869 let isAsmParserOnly = 1 in {
2870 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2871 "pmovmskb\t{$src, $dst|$dst, $src}",
2872 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2873 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2874 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2876 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2877 "pmovmskb\t{$src, $dst|$dst, $src}",
2878 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2880 } // ExeDomain = SSEPackedInt
2882 //===---------------------------------------------------------------------===//
2883 // SSE2 - Conditional Store
2884 //===---------------------------------------------------------------------===//
2886 let ExeDomain = SSEPackedInt in {
2888 let isAsmParserOnly = 1 in {
2890 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2891 (ins VR128:$src, VR128:$mask),
2892 "maskmovdqu\t{$mask, $src|$src, $mask}",
2893 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2895 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2896 (ins VR128:$src, VR128:$mask),
2897 "maskmovdqu\t{$mask, $src|$src, $mask}",
2898 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2902 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2903 "maskmovdqu\t{$mask, $src|$src, $mask}",
2904 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2906 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2907 "maskmovdqu\t{$mask, $src|$src, $mask}",
2908 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2910 } // ExeDomain = SSEPackedInt
2912 //===---------------------------------------------------------------------===//
2913 // SSE2 - Move Doubleword
2914 //===---------------------------------------------------------------------===//
2916 // Move Int Doubleword to Packed Double Int
2917 let isAsmParserOnly = 1 in {
2918 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2919 "movd\t{$src, $dst|$dst, $src}",
2921 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2922 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2923 "movd\t{$src, $dst|$dst, $src}",
2925 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2928 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2929 "movd\t{$src, $dst|$dst, $src}",
2931 (v4i32 (scalar_to_vector GR32:$src)))]>;
2932 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2933 "movd\t{$src, $dst|$dst, $src}",
2935 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2936 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2937 "mov{d|q}\t{$src, $dst|$dst, $src}",
2939 (v2i64 (scalar_to_vector GR64:$src)))]>;
2940 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2941 "mov{d|q}\t{$src, $dst|$dst, $src}",
2942 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2945 // Move Int Doubleword to Single Scalar
2946 let isAsmParserOnly = 1 in {
2947 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2948 "movd\t{$src, $dst|$dst, $src}",
2949 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2951 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2952 "movd\t{$src, $dst|$dst, $src}",
2953 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2956 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2957 "movd\t{$src, $dst|$dst, $src}",
2958 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2960 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2961 "movd\t{$src, $dst|$dst, $src}",
2962 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2964 // Move Packed Doubleword Int to Packed Double Int
2965 let isAsmParserOnly = 1 in {
2966 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2967 "movd\t{$src, $dst|$dst, $src}",
2968 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2970 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2971 (ins i32mem:$dst, VR128:$src),
2972 "movd\t{$src, $dst|$dst, $src}",
2973 [(store (i32 (vector_extract (v4i32 VR128:$src),
2974 (iPTR 0))), addr:$dst)]>, VEX;
2976 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2977 "movd\t{$src, $dst|$dst, $src}",
2978 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2980 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2981 "movd\t{$src, $dst|$dst, $src}",
2982 [(store (i32 (vector_extract (v4i32 VR128:$src),
2983 (iPTR 0))), addr:$dst)]>;
2985 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2986 "mov{d|q}\t{$src, $dst|$dst, $src}",
2987 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2989 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2990 "movq\t{$src, $dst|$dst, $src}",
2991 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2993 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2994 "mov{d|q}\t{$src, $dst|$dst, $src}",
2995 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2996 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2997 "movq\t{$src, $dst|$dst, $src}",
2998 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
3000 // Move Scalar Single to Double Int
3001 let isAsmParserOnly = 1 in {
3002 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3003 "movd\t{$src, $dst|$dst, $src}",
3004 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
3005 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3006 "movd\t{$src, $dst|$dst, $src}",
3007 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
3009 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3010 "movd\t{$src, $dst|$dst, $src}",
3011 [(set GR32:$dst, (bitconvert FR32:$src))]>;
3012 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
3013 "movd\t{$src, $dst|$dst, $src}",
3014 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
3016 // movd / movq to XMM register zero-extends
3017 let AddedComplexity = 15, isAsmParserOnly = 1 in {
3018 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3019 "movd\t{$src, $dst|$dst, $src}",
3020 [(set VR128:$dst, (v4i32 (X86vzmovl
3021 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3023 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3024 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3025 [(set VR128:$dst, (v2i64 (X86vzmovl
3026 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3029 let AddedComplexity = 15 in {
3030 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3031 "movd\t{$src, $dst|$dst, $src}",
3032 [(set VR128:$dst, (v4i32 (X86vzmovl
3033 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3034 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3035 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3036 [(set VR128:$dst, (v2i64 (X86vzmovl
3037 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3040 let AddedComplexity = 20 in {
3041 let isAsmParserOnly = 1 in
3042 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3043 "movd\t{$src, $dst|$dst, $src}",
3045 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3046 (loadi32 addr:$src))))))]>,
3048 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3049 "movd\t{$src, $dst|$dst, $src}",
3051 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3052 (loadi32 addr:$src))))))]>;
3054 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3055 (MOVZDI2PDIrm addr:$src)>;
3056 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3057 (MOVZDI2PDIrm addr:$src)>;
3058 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3059 (MOVZDI2PDIrm addr:$src)>;
3062 //===---------------------------------------------------------------------===//
3063 // SSE2 - Move Quadword
3064 //===---------------------------------------------------------------------===//
3066 // Move Quadword Int to Packed Quadword Int
3067 let isAsmParserOnly = 1 in
3068 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3069 "vmovq\t{$src, $dst|$dst, $src}",
3071 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3072 VEX, Requires<[HasAVX]>;
3073 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3074 "movq\t{$src, $dst|$dst, $src}",
3076 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3077 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3079 // Move Packed Quadword Int to Quadword Int
3080 let isAsmParserOnly = 1 in
3081 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3082 "movq\t{$src, $dst|$dst, $src}",
3083 [(store (i64 (vector_extract (v2i64 VR128:$src),
3084 (iPTR 0))), addr:$dst)]>, VEX;
3085 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3086 "movq\t{$src, $dst|$dst, $src}",
3087 [(store (i64 (vector_extract (v2i64 VR128:$src),
3088 (iPTR 0))), addr:$dst)]>;
3090 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3091 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3093 // Store / copy lower 64-bits of a XMM register.
3094 let isAsmParserOnly = 1 in
3095 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3096 "movq\t{$src, $dst|$dst, $src}",
3097 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3098 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3099 "movq\t{$src, $dst|$dst, $src}",
3100 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3102 let AddedComplexity = 20, isAsmParserOnly = 1 in
3103 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3104 "vmovq\t{$src, $dst|$dst, $src}",
3106 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3107 (loadi64 addr:$src))))))]>,
3108 XS, VEX, Requires<[HasAVX]>;
3110 let AddedComplexity = 20 in {
3111 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3112 "movq\t{$src, $dst|$dst, $src}",
3114 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3115 (loadi64 addr:$src))))))]>,
3116 XS, Requires<[HasSSE2]>;
3118 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3119 (MOVZQI2PQIrm addr:$src)>;
3120 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3121 (MOVZQI2PQIrm addr:$src)>;
3122 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3125 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3126 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3127 let isAsmParserOnly = 1, AddedComplexity = 15 in
3128 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3129 "vmovq\t{$src, $dst|$dst, $src}",
3130 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3131 XS, VEX, Requires<[HasAVX]>;
3132 let AddedComplexity = 15 in
3133 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3134 "movq\t{$src, $dst|$dst, $src}",
3135 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3136 XS, Requires<[HasSSE2]>;
3138 let AddedComplexity = 20, isAsmParserOnly = 1 in
3139 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3140 "vmovq\t{$src, $dst|$dst, $src}",
3141 [(set VR128:$dst, (v2i64 (X86vzmovl
3142 (loadv2i64 addr:$src))))]>,
3143 XS, VEX, Requires<[HasAVX]>;
3144 let AddedComplexity = 20 in {
3145 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3146 "movq\t{$src, $dst|$dst, $src}",
3147 [(set VR128:$dst, (v2i64 (X86vzmovl
3148 (loadv2i64 addr:$src))))]>,
3149 XS, Requires<[HasSSE2]>;
3151 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3152 (MOVZPQILo2PQIrm addr:$src)>;
3155 // Instructions to match in the assembler
3156 let isAsmParserOnly = 1 in {
3157 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3158 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3159 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3160 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3161 // Recognize "movd" with GR64 destination, but encode as a "movq"
3162 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3163 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3166 // Instructions for the disassembler
3167 // xr = XMM register
3170 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3171 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3172 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3173 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3174 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3176 //===---------------------------------------------------------------------===//
3177 // SSE2 - Misc Instructions
3178 //===---------------------------------------------------------------------===//
3181 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3182 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3183 TB, Requires<[HasSSE2]>;
3185 // Load, store, and memory fence
3186 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3187 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3188 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3189 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3190 def : Pat<(X86LFence), (LFENCE)>;
3191 def : Pat<(X86MFence), (MFENCE)>;
3194 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3195 // was introduced with SSE2, it's backward compatible.
3196 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3198 // Alias instructions that map zero vector to pxor / xorp* for sse.
3199 // We set canFoldAsLoad because this can be converted to a constant-pool
3200 // load of an all-ones value if folding it would be beneficial.
3201 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3202 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3203 // FIXME: Change encoding to pseudo.
3204 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3205 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3207 //===---------------------------------------------------------------------===//
3208 // SSE3 - Conversion Instructions
3209 //===---------------------------------------------------------------------===//
3211 // Convert Packed Double FP to Packed DW Integers
3212 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3213 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3214 // register, but the same isn't true when using memory operands instead.
3215 // Provide other assembly rr and rm forms to address this explicitly.
3216 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3217 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3218 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3219 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3222 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3223 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3224 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3225 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3228 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3229 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3230 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3231 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3234 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3235 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3236 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3237 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3239 // Convert Packed DW Integers to Packed Double FP
3240 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3241 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3242 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3243 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3244 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3245 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3246 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3247 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3248 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3251 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3252 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3253 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3254 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3256 // AVX 256-bit register conversion intrinsics
3257 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3258 (VCVTDQ2PDYrr VR128:$src)>;
3259 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3260 (VCVTDQ2PDYrm addr:$src)>;
3262 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3263 (VCVTPD2DQYrr VR256:$src)>;
3264 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3265 (VCVTPD2DQYrm addr:$src)>;
3267 //===---------------------------------------------------------------------===//
3268 // SSE3 - Move Instructions
3269 //===---------------------------------------------------------------------===//
3271 // Replicate Single FP
3272 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3273 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3274 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3275 [(set VR128:$dst, (v4f32 (rep_frag
3276 VR128:$src, (undef))))]>;
3277 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3278 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3279 [(set VR128:$dst, (rep_frag
3280 (memopv4f32 addr:$src), (undef)))]>;
3283 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3285 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3286 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3287 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3288 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3291 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3292 // FIXME: Merge above classes when we have patterns for the ymm version
3293 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3294 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3295 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3296 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3298 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3299 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3301 // Replicate Double FP
3302 multiclass sse3_replicate_dfp<string OpcodeStr> {
3303 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3304 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3305 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3306 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3307 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3309 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3313 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3314 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3315 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3317 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3318 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3322 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3323 // FIXME: Merge above classes when we have patterns for the ymm version
3324 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3325 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3327 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3329 // Move Unaligned Integer
3330 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3331 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3332 "vlddqu\t{$src, $dst|$dst, $src}",
3333 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3334 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3335 "vlddqu\t{$src, $dst|$dst, $src}",
3336 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3338 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3339 "lddqu\t{$src, $dst|$dst, $src}",
3340 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3342 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3344 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3346 // Several Move patterns
3347 let AddedComplexity = 5 in {
3348 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3349 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3350 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3351 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3352 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3353 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3354 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3355 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3358 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3359 let AddedComplexity = 15 in
3360 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3361 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3362 let AddedComplexity = 20 in
3363 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3364 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3366 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3367 let AddedComplexity = 15 in
3368 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3369 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3370 let AddedComplexity = 20 in
3371 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3372 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3374 //===---------------------------------------------------------------------===//
3375 // SSE3 - Arithmetic
3376 //===---------------------------------------------------------------------===//
3378 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3379 X86MemOperand x86memop, bit Is2Addr = 1> {
3380 def rr : I<0xD0, MRMSrcReg,
3381 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3383 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3384 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3385 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3386 def rm : I<0xD0, MRMSrcMem,
3387 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3391 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3394 let isAsmParserOnly = 1, Predicates = [HasAVX],
3395 ExeDomain = SSEPackedDouble in {
3396 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3397 f128mem, 0>, XD, VEX_4V;
3398 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3399 f128mem, 0>, OpSize, VEX_4V;
3400 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3401 f256mem, 0>, XD, VEX_4V;
3402 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3403 f256mem, 0>, OpSize, VEX_4V;
3405 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3406 ExeDomain = SSEPackedDouble in {
3407 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3409 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3410 f128mem>, TB, OpSize;
3413 //===---------------------------------------------------------------------===//
3414 // SSE3 Instructions
3415 //===---------------------------------------------------------------------===//
3418 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3419 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3420 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3422 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3423 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3424 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3426 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3428 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3429 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3430 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3432 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3433 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3434 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3436 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3437 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3438 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3440 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3442 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3443 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3444 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3447 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3448 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3449 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3450 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3451 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3452 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3453 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3454 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3455 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3456 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3457 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3458 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3459 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3460 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3461 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3462 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3463 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3466 let Constraints = "$src1 = $dst" in {
3467 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3468 int_x86_sse3_hadd_ps>;
3469 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3470 int_x86_sse3_hadd_pd>;
3471 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3472 int_x86_sse3_hsub_ps>;
3473 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3474 int_x86_sse3_hsub_pd>;
3477 //===---------------------------------------------------------------------===//
3478 // SSSE3 - Packed Absolute Instructions
3479 //===---------------------------------------------------------------------===//
3482 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3483 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3484 PatFrag mem_frag128, Intrinsic IntId128> {
3485 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3488 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3491 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3493 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3496 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3499 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3500 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3501 int_x86_ssse3_pabs_b_128>, VEX;
3502 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3503 int_x86_ssse3_pabs_w_128>, VEX;
3504 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3505 int_x86_ssse3_pabs_d_128>, VEX;
3508 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3509 int_x86_ssse3_pabs_b_128>;
3510 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3511 int_x86_ssse3_pabs_w_128>;
3512 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3513 int_x86_ssse3_pabs_d_128>;
3515 //===---------------------------------------------------------------------===//
3516 // SSSE3 - Packed Binary Operator Instructions
3517 //===---------------------------------------------------------------------===//
3519 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3520 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3521 PatFrag mem_frag128, Intrinsic IntId128,
3523 let isCommutable = 1 in
3524 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3525 (ins VR128:$src1, VR128:$src2),
3527 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3528 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3529 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3531 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3532 (ins VR128:$src1, i128mem:$src2),
3534 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3535 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3537 (IntId128 VR128:$src1,
3538 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3541 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3542 let isCommutable = 0 in {
3543 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3544 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3545 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3546 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3547 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3548 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3549 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3550 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3551 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3552 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3553 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3554 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3555 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3556 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3557 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3558 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3559 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3560 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3561 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3562 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3563 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3564 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3566 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3567 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3570 // None of these have i8 immediate fields.
3571 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3572 let isCommutable = 0 in {
3573 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3574 int_x86_ssse3_phadd_w_128>;
3575 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3576 int_x86_ssse3_phadd_d_128>;
3577 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3578 int_x86_ssse3_phadd_sw_128>;
3579 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3580 int_x86_ssse3_phsub_w_128>;
3581 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3582 int_x86_ssse3_phsub_d_128>;
3583 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3584 int_x86_ssse3_phsub_sw_128>;
3585 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3586 int_x86_ssse3_pmadd_ub_sw_128>;
3587 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3588 int_x86_ssse3_pshuf_b_128>;
3589 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3590 int_x86_ssse3_psign_b_128>;
3591 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3592 int_x86_ssse3_psign_w_128>;
3593 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3594 int_x86_ssse3_psign_d_128>;
3596 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3597 int_x86_ssse3_pmul_hr_sw_128>;
3600 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3601 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3602 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3603 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3605 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3606 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3607 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3608 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3609 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3610 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3612 //===---------------------------------------------------------------------===//
3613 // SSSE3 - Packed Align Instruction Patterns
3614 //===---------------------------------------------------------------------===//
3616 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3617 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3618 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3620 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3622 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3624 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3625 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3627 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3629 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3633 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3634 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3635 let Constraints = "$src1 = $dst" in
3636 defm PALIGN : ssse3_palign<"palignr">;
3638 let AddedComplexity = 5 in {
3639 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3640 (PALIGNR128rr VR128:$src2, VR128:$src1,
3641 (SHUFFLE_get_palign_imm VR128:$src3))>,
3642 Requires<[HasSSSE3]>;
3643 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3644 (PALIGNR128rr VR128:$src2, VR128:$src1,
3645 (SHUFFLE_get_palign_imm VR128:$src3))>,
3646 Requires<[HasSSSE3]>;
3647 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3648 (PALIGNR128rr VR128:$src2, VR128:$src1,
3649 (SHUFFLE_get_palign_imm VR128:$src3))>,
3650 Requires<[HasSSSE3]>;
3651 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3652 (PALIGNR128rr VR128:$src2, VR128:$src1,
3653 (SHUFFLE_get_palign_imm VR128:$src3))>,
3654 Requires<[HasSSSE3]>;
3657 //===---------------------------------------------------------------------===//
3658 // SSSE3 Misc Instructions
3659 //===---------------------------------------------------------------------===//
3661 // Thread synchronization
3662 let usesCustomInserter = 1 in {
3663 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3664 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3665 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3666 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3669 let Uses = [EAX, ECX, EDX] in
3670 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3671 Requires<[HasSSE3]>;
3672 let Uses = [ECX, EAX] in
3673 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3674 Requires<[HasSSE3]>;
3676 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3677 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3679 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3680 Requires<[In32BitMode]>;
3681 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3682 Requires<[In64BitMode]>;
3684 //===---------------------------------------------------------------------===//
3685 // Non-Instruction Patterns
3686 //===---------------------------------------------------------------------===//
3688 // extload f32 -> f64. This matches load+fextend because we have a hack in
3689 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3691 // Since these loads aren't folded into the fextend, we have to match it
3693 let Predicates = [HasSSE2] in
3694 def : Pat<(fextend (loadf32 addr:$src)),
3695 (CVTSS2SDrm addr:$src)>;
3698 let Predicates = [HasXMMInt] in {
3699 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3700 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3701 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3702 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3703 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3704 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3705 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3706 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3707 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3708 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3709 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3710 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3711 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3712 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3713 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3714 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3715 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3716 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3717 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3718 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3719 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3720 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3721 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3722 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3723 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3724 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3725 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3726 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3727 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3728 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3731 let Predicates = [HasAVX] in {
3732 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3735 // Move scalar to XMM zero-extended
3736 // movd to XMM register zero-extends
3737 let AddedComplexity = 15 in {
3738 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3739 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3740 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3741 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3742 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3743 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3744 (MOVSSrr (v4f32 (V_SET0PS)),
3745 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3746 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3747 (MOVSSrr (v4i32 (V_SET0PI)),
3748 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3751 // Splat v2f64 / v2i64
3752 let AddedComplexity = 10 in {
3753 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3754 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3755 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3756 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3757 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3758 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3759 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3760 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3763 // Special unary SHUFPSrri case.
3764 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3765 (SHUFPSrri VR128:$src1, VR128:$src1,
3766 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3767 let AddedComplexity = 5 in
3768 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3769 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3770 Requires<[HasSSE2]>;
3771 // Special unary SHUFPDrri case.
3772 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3773 (SHUFPDrri VR128:$src1, VR128:$src1,
3774 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3775 Requires<[HasSSE2]>;
3776 // Special unary SHUFPDrri case.
3777 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3778 (SHUFPDrri VR128:$src1, VR128:$src1,
3779 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3780 Requires<[HasSSE2]>;
3781 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3782 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3783 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3784 Requires<[HasSSE2]>;
3786 // Special binary v4i32 shuffle cases with SHUFPS.
3787 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3788 (SHUFPSrri VR128:$src1, VR128:$src2,
3789 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3790 Requires<[HasSSE2]>;
3791 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3792 (SHUFPSrmi VR128:$src1, addr:$src2,
3793 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3794 Requires<[HasSSE2]>;
3795 // Special binary v2i64 shuffle cases using SHUFPDrri.
3796 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3797 (SHUFPDrri VR128:$src1, VR128:$src2,
3798 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3799 Requires<[HasSSE2]>;
3801 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3802 let AddedComplexity = 15 in {
3803 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3804 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3805 Requires<[OptForSpeed, HasSSE2]>;
3806 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3807 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3808 Requires<[OptForSpeed, HasSSE2]>;
3810 let AddedComplexity = 10 in {
3811 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3812 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3813 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3814 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3815 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3816 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3817 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3818 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3821 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3822 let AddedComplexity = 15 in {
3823 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3824 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3825 Requires<[OptForSpeed, HasSSE2]>;
3826 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3827 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3828 Requires<[OptForSpeed, HasSSE2]>;
3830 let AddedComplexity = 10 in {
3831 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3832 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3833 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3834 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3835 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3836 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3837 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3838 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3841 let AddedComplexity = 20 in {
3842 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3843 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3844 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3846 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3847 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3848 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3850 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3851 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3852 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3853 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3854 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3857 let AddedComplexity = 20 in {
3858 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3859 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3860 (MOVLPSrm VR128:$src1, addr:$src2)>;
3861 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3862 (MOVLPDrm VR128:$src1, addr:$src2)>;
3863 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3864 (MOVLPSrm VR128:$src1, addr:$src2)>;
3865 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3866 (MOVLPDrm VR128:$src1, addr:$src2)>;
3869 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3870 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3871 (MOVLPSmr addr:$src1, VR128:$src2)>;
3872 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3873 (MOVLPDmr addr:$src1, VR128:$src2)>;
3874 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3876 (MOVLPSmr addr:$src1, VR128:$src2)>;
3877 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3878 (MOVLPDmr addr:$src1, VR128:$src2)>;
3880 let AddedComplexity = 15 in {
3881 // Setting the lowest element in the vector.
3882 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3883 (MOVSSrr (v4i32 VR128:$src1),
3884 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3885 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3886 (MOVSDrr (v2i64 VR128:$src1),
3887 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3889 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3890 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3891 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3892 Requires<[HasSSE2]>;
3893 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3894 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3895 Requires<[HasSSE2]>;
3898 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3899 // fall back to this for SSE1)
3900 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3901 (SHUFPSrri VR128:$src2, VR128:$src1,
3902 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3904 // Set lowest element and zero upper elements.
3905 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3906 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3908 // vector -> vector casts
3909 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3910 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3911 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3912 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3914 // Use movaps / movups for SSE integer load / store (one byte shorter).
3915 let Predicates = [HasSSE1] in {
3916 def : Pat<(alignedloadv4i32 addr:$src),
3917 (MOVAPSrm addr:$src)>;
3918 def : Pat<(loadv4i32 addr:$src),
3919 (MOVUPSrm addr:$src)>;
3920 def : Pat<(alignedloadv2i64 addr:$src),
3921 (MOVAPSrm addr:$src)>;
3922 def : Pat<(loadv2i64 addr:$src),
3923 (MOVUPSrm addr:$src)>;
3925 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3926 (MOVAPSmr addr:$dst, VR128:$src)>;
3927 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3928 (MOVAPSmr addr:$dst, VR128:$src)>;
3929 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3930 (MOVAPSmr addr:$dst, VR128:$src)>;
3931 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3932 (MOVAPSmr addr:$dst, VR128:$src)>;
3933 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3934 (MOVUPSmr addr:$dst, VR128:$src)>;
3935 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3936 (MOVUPSmr addr:$dst, VR128:$src)>;
3937 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3938 (MOVUPSmr addr:$dst, VR128:$src)>;
3939 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3940 (MOVUPSmr addr:$dst, VR128:$src)>;
3943 // Use vmovaps/vmovups for AVX 128-bit integer load/store (one byte shorter).
3944 let Predicates = [HasAVX] in {
3945 def : Pat<(alignedloadv4i32 addr:$src),
3946 (VMOVAPSrm addr:$src)>;
3947 def : Pat<(loadv4i32 addr:$src),
3948 (VMOVUPSrm addr:$src)>;
3949 def : Pat<(alignedloadv2i64 addr:$src),
3950 (VMOVAPSrm addr:$src)>;
3951 def : Pat<(loadv2i64 addr:$src),
3952 (VMOVUPSrm addr:$src)>;
3954 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3955 (VMOVAPSmr addr:$dst, VR128:$src)>;
3956 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3957 (VMOVAPSmr addr:$dst, VR128:$src)>;
3958 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3959 (VMOVAPSmr addr:$dst, VR128:$src)>;
3960 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3961 (VMOVAPSmr addr:$dst, VR128:$src)>;
3962 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3963 (VMOVUPSmr addr:$dst, VR128:$src)>;
3964 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3965 (VMOVUPSmr addr:$dst, VR128:$src)>;
3966 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3967 (VMOVUPSmr addr:$dst, VR128:$src)>;
3968 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3969 (VMOVUPSmr addr:$dst, VR128:$src)>;
3972 //===----------------------------------------------------------------------===//
3973 // SSE4.1 - Packed Move with Sign/Zero Extend
3974 //===----------------------------------------------------------------------===//
3976 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3977 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3978 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3979 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3981 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3984 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3988 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3989 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3991 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3993 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3995 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3997 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3999 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4003 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4004 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4005 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4006 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4007 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4008 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4010 // Common patterns involving scalar load.
4011 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4012 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4013 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4014 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4016 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4017 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4018 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4019 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4021 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4022 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4023 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4024 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4026 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4027 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4028 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4029 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4031 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4032 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4033 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4034 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4036 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4037 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4038 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4039 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4042 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4043 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4044 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4045 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4047 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4048 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4050 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4054 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4055 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4057 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4059 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4061 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4065 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4066 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4067 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4068 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4070 // Common patterns involving scalar load
4071 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4072 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4073 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4074 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4076 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4077 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4078 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4079 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4082 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4083 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4084 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4085 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4087 // Expecting a i16 load any extended to i32 value.
4088 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4089 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4090 [(set VR128:$dst, (IntId (bitconvert
4091 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4095 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4096 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4098 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4101 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4102 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4104 // Common patterns involving scalar load
4105 def : Pat<(int_x86_sse41_pmovsxbq
4106 (bitconvert (v4i32 (X86vzmovl
4107 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4108 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4110 def : Pat<(int_x86_sse41_pmovzxbq
4111 (bitconvert (v4i32 (X86vzmovl
4112 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4113 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4115 //===----------------------------------------------------------------------===//
4116 // SSE4.1 - Extract Instructions
4117 //===----------------------------------------------------------------------===//
4119 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4120 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4121 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4122 (ins VR128:$src1, i32i8imm:$src2),
4123 !strconcat(OpcodeStr,
4124 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4125 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4127 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4128 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4129 !strconcat(OpcodeStr,
4130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4133 // There's an AssertZext in the way of writing the store pattern
4134 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4137 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4138 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4139 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4140 (ins VR128:$src1, i32i8imm:$src2),
4141 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4144 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4147 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4148 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4149 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4150 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4151 !strconcat(OpcodeStr,
4152 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4155 // There's an AssertZext in the way of writing the store pattern
4156 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4159 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4160 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4162 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4165 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4166 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4167 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4168 (ins VR128:$src1, i32i8imm:$src2),
4169 !strconcat(OpcodeStr,
4170 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4172 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4173 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4174 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4175 !strconcat(OpcodeStr,
4176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4177 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4178 addr:$dst)]>, OpSize;
4181 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4182 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4184 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4186 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4187 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4188 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4189 (ins VR128:$src1, i32i8imm:$src2),
4190 !strconcat(OpcodeStr,
4191 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4193 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4194 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4195 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4196 !strconcat(OpcodeStr,
4197 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4198 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4199 addr:$dst)]>, OpSize, REX_W;
4202 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4203 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4205 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4207 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4209 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4210 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4211 (ins VR128:$src1, i32i8imm:$src2),
4212 !strconcat(OpcodeStr,
4213 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4215 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4217 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4218 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4219 !strconcat(OpcodeStr,
4220 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4221 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4222 addr:$dst)]>, OpSize;
4225 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4226 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4227 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4228 (ins VR128:$src1, i32i8imm:$src2),
4229 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4232 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4234 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4235 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4238 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4239 Requires<[HasSSE41]>;
4241 //===----------------------------------------------------------------------===//
4242 // SSE4.1 - Insert Instructions
4243 //===----------------------------------------------------------------------===//
4245 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4246 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4247 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4249 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4251 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4253 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4254 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4255 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4257 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4259 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4261 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4262 imm:$src3))]>, OpSize;
4265 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4266 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4267 let Constraints = "$src1 = $dst" in
4268 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4270 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4271 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4272 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4274 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4276 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4278 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4280 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4281 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4283 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4285 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4287 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4288 imm:$src3)))]>, OpSize;
4291 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4292 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4293 let Constraints = "$src1 = $dst" in
4294 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4296 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4297 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4298 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4300 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4302 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4304 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4306 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4307 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4309 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4311 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4313 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4314 imm:$src3)))]>, OpSize;
4317 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4318 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4319 let Constraints = "$src1 = $dst" in
4320 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4322 // insertps has a few different modes, there's the first two here below which
4323 // are optimized inserts that won't zero arbitrary elements in the destination
4324 // vector. The next one matches the intrinsic and could zero arbitrary elements
4325 // in the target vector.
4326 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4327 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4328 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4330 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4334 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4336 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4337 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4339 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4341 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4343 (X86insrtps VR128:$src1,
4344 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4345 imm:$src3))]>, OpSize;
4348 let Constraints = "$src1 = $dst" in
4349 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4350 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4351 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4353 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4354 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4356 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4357 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4358 Requires<[HasSSE41]>;
4360 //===----------------------------------------------------------------------===//
4361 // SSE4.1 - Round Instructions
4362 //===----------------------------------------------------------------------===//
4364 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4365 X86MemOperand x86memop, RegisterClass RC,
4366 PatFrag mem_frag32, PatFrag mem_frag64,
4367 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4368 // Intrinsic operation, reg.
4369 // Vector intrinsic operation, reg
4370 def PSr : SS4AIi8<opcps, MRMSrcReg,
4371 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4372 !strconcat(OpcodeStr,
4373 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4374 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4377 // Vector intrinsic operation, mem
4378 def PSm : Ii8<opcps, MRMSrcMem,
4379 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4380 !strconcat(OpcodeStr,
4381 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4383 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4385 Requires<[HasSSE41]>;
4387 // Vector intrinsic operation, reg
4388 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4389 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4390 !strconcat(OpcodeStr,
4391 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4392 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4395 // Vector intrinsic operation, mem
4396 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4397 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4398 !strconcat(OpcodeStr,
4399 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4401 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4405 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4406 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4407 // Intrinsic operation, reg.
4408 // Vector intrinsic operation, reg
4409 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4410 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4411 !strconcat(OpcodeStr,
4412 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4415 // Vector intrinsic operation, mem
4416 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4417 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4418 !strconcat(OpcodeStr,
4419 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4420 []>, TA, OpSize, Requires<[HasSSE41]>;
4422 // Vector intrinsic operation, reg
4423 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4424 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4425 !strconcat(OpcodeStr,
4426 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4429 // Vector intrinsic operation, mem
4430 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4431 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4432 !strconcat(OpcodeStr,
4433 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4437 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4440 Intrinsic F64Int, bit Is2Addr = 1> {
4441 // Intrinsic operation, reg.
4442 def SSr : SS4AIi8<opcss, MRMSrcReg,
4443 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4445 !strconcat(OpcodeStr,
4446 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4447 !strconcat(OpcodeStr,
4448 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4449 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4452 // Intrinsic operation, mem.
4453 def SSm : SS4AIi8<opcss, MRMSrcMem,
4454 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4456 !strconcat(OpcodeStr,
4457 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4458 !strconcat(OpcodeStr,
4459 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4461 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4464 // Intrinsic operation, reg.
4465 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4466 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4468 !strconcat(OpcodeStr,
4469 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4470 !strconcat(OpcodeStr,
4471 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4472 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4475 // Intrinsic operation, mem.
4476 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4477 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4479 !strconcat(OpcodeStr,
4480 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4481 !strconcat(OpcodeStr,
4482 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4484 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4488 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4490 // Intrinsic operation, reg.
4491 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4492 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4493 !strconcat(OpcodeStr,
4494 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4497 // Intrinsic operation, mem.
4498 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4499 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4500 !strconcat(OpcodeStr,
4501 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4504 // Intrinsic operation, reg.
4505 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4506 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4507 !strconcat(OpcodeStr,
4508 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4511 // Intrinsic operation, mem.
4512 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4513 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4514 !strconcat(OpcodeStr,
4515 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4519 // FP round - roundss, roundps, roundsd, roundpd
4520 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4522 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4523 memopv4f32, memopv2f64,
4524 int_x86_sse41_round_ps,
4525 int_x86_sse41_round_pd>, VEX;
4526 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4527 memopv8f32, memopv4f64,
4528 int_x86_avx_round_ps_256,
4529 int_x86_avx_round_pd_256>, VEX;
4530 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4531 int_x86_sse41_round_ss,
4532 int_x86_sse41_round_sd, 0>, VEX_4V;
4534 // Instructions for the assembler
4535 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4537 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4539 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4542 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4543 memopv4f32, memopv2f64,
4544 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4545 let Constraints = "$src1 = $dst" in
4546 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4547 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4549 //===----------------------------------------------------------------------===//
4550 // SSE4.1 - Packed Bit Test
4551 //===----------------------------------------------------------------------===//
4553 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4554 // the intel intrinsic that corresponds to this.
4555 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4556 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4557 "vptest\t{$src2, $src1|$src1, $src2}",
4558 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4560 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4561 "vptest\t{$src2, $src1|$src1, $src2}",
4562 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4565 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4566 "vptest\t{$src2, $src1|$src1, $src2}",
4567 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4569 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4570 "vptest\t{$src2, $src1|$src1, $src2}",
4571 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4575 let Defs = [EFLAGS] in {
4576 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4577 "ptest \t{$src2, $src1|$src1, $src2}",
4578 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4580 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4581 "ptest \t{$src2, $src1|$src1, $src2}",
4582 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4586 // The bit test instructions below are AVX only
4587 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4588 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4589 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4590 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4591 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4592 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4593 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4594 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4598 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4599 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4600 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4601 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4602 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4605 //===----------------------------------------------------------------------===//
4606 // SSE4.1 - Misc Instructions
4607 //===----------------------------------------------------------------------===//
4609 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4610 "popcnt{w}\t{$src, $dst|$dst, $src}",
4611 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4612 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4613 "popcnt{w}\t{$src, $dst|$dst, $src}",
4614 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4616 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4617 "popcnt{l}\t{$src, $dst|$dst, $src}",
4618 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4619 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4620 "popcnt{l}\t{$src, $dst|$dst, $src}",
4621 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4623 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4624 "popcnt{q}\t{$src, $dst|$dst, $src}",
4625 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4626 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4627 "popcnt{q}\t{$src, $dst|$dst, $src}",
4628 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4632 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4633 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4634 Intrinsic IntId128> {
4635 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4637 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4638 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4639 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4641 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4644 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4647 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4648 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4649 int_x86_sse41_phminposuw>, VEX;
4650 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4651 int_x86_sse41_phminposuw>;
4653 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4654 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4655 Intrinsic IntId128, bit Is2Addr = 1> {
4656 let isCommutable = 1 in
4657 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4658 (ins VR128:$src1, VR128:$src2),
4660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4662 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4663 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4664 (ins VR128:$src1, i128mem:$src2),
4666 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4667 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4669 (IntId128 VR128:$src1,
4670 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4673 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4674 let isCommutable = 0 in
4675 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4677 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4679 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4681 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4683 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4685 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4687 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4689 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4691 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4693 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4695 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4699 let Constraints = "$src1 = $dst" in {
4700 let isCommutable = 0 in
4701 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4702 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4703 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4704 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4705 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4706 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4707 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4708 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4709 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4710 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4711 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4714 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4715 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4716 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4717 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4719 /// SS48I_binop_rm - Simple SSE41 binary operator.
4720 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4721 ValueType OpVT, bit Is2Addr = 1> {
4722 let isCommutable = 1 in
4723 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4724 (ins VR128:$src1, VR128:$src2),
4726 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4727 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4728 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4730 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4731 (ins VR128:$src1, i128mem:$src2),
4733 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4734 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4735 [(set VR128:$dst, (OpNode VR128:$src1,
4736 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4740 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4741 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4742 let Constraints = "$src1 = $dst" in
4743 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4745 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4746 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4747 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4748 X86MemOperand x86memop, bit Is2Addr = 1> {
4749 let isCommutable = 1 in
4750 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4751 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4753 !strconcat(OpcodeStr,
4754 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4755 !strconcat(OpcodeStr,
4756 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4757 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4759 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4760 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4762 !strconcat(OpcodeStr,
4763 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4764 !strconcat(OpcodeStr,
4765 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4768 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4772 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4773 let isCommutable = 0 in {
4774 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4775 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4776 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4777 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4778 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4779 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4780 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4781 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4782 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4783 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4784 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4785 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4787 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4788 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4789 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4790 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4791 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4792 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4795 let Constraints = "$src1 = $dst" in {
4796 let isCommutable = 0 in {
4797 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4798 VR128, memopv16i8, i128mem>;
4799 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4800 VR128, memopv16i8, i128mem>;
4801 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4802 VR128, memopv16i8, i128mem>;
4803 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4804 VR128, memopv16i8, i128mem>;
4806 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4807 VR128, memopv16i8, i128mem>;
4808 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4809 VR128, memopv16i8, i128mem>;
4812 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4813 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4814 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4815 RegisterClass RC, X86MemOperand x86memop,
4816 PatFrag mem_frag, Intrinsic IntId> {
4817 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4818 (ins RC:$src1, RC:$src2, RC:$src3),
4819 !strconcat(OpcodeStr,
4820 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4821 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4822 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4824 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4825 (ins RC:$src1, x86memop:$src2, RC:$src3),
4826 !strconcat(OpcodeStr,
4827 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4829 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4831 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4835 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4836 memopv16i8, int_x86_sse41_blendvpd>;
4837 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4838 memopv16i8, int_x86_sse41_blendvps>;
4839 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4840 memopv16i8, int_x86_sse41_pblendvb>;
4841 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4842 memopv32i8, int_x86_avx_blendv_pd_256>;
4843 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4844 memopv32i8, int_x86_avx_blendv_ps_256>;
4846 /// SS41I_ternary_int - SSE 4.1 ternary operator
4847 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4848 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4849 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4850 (ins VR128:$src1, VR128:$src2),
4851 !strconcat(OpcodeStr,
4852 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4853 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4856 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4857 (ins VR128:$src1, i128mem:$src2),
4858 !strconcat(OpcodeStr,
4859 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4862 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4866 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4867 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4868 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4870 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4871 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4873 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4874 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4875 "vmovntdqa\t{$src, $dst|$dst, $src}",
4876 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4878 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4879 "movntdqa\t{$src, $dst|$dst, $src}",
4880 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4883 //===----------------------------------------------------------------------===//
4884 // SSE4.2 - Compare Instructions
4885 //===----------------------------------------------------------------------===//
4887 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4888 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4889 Intrinsic IntId128, bit Is2Addr = 1> {
4890 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4891 (ins VR128:$src1, VR128:$src2),
4893 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4894 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4895 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4897 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4898 (ins VR128:$src1, i128mem:$src2),
4900 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4901 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4903 (IntId128 VR128:$src1,
4904 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4907 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4908 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4910 let Constraints = "$src1 = $dst" in
4911 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4913 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4914 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4915 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4916 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4918 //===----------------------------------------------------------------------===//
4919 // SSE4.2 - String/text Processing Instructions
4920 //===----------------------------------------------------------------------===//
4922 // Packed Compare Implicit Length Strings, Return Mask
4923 multiclass pseudo_pcmpistrm<string asm> {
4924 def REG : PseudoI<(outs VR128:$dst),
4925 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4926 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4928 def MEM : PseudoI<(outs VR128:$dst),
4929 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4930 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4931 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4934 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4935 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4936 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4939 let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
4940 Predicates = [HasAVX] in {
4941 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4942 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4943 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4944 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4945 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4946 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4949 let Defs = [XMM0, EFLAGS] in {
4950 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4951 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4952 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4953 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4954 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4955 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4958 // Packed Compare Explicit Length Strings, Return Mask
4959 multiclass pseudo_pcmpestrm<string asm> {
4960 def REG : PseudoI<(outs VR128:$dst),
4961 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4962 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4963 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4964 def MEM : PseudoI<(outs VR128:$dst),
4965 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4966 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4967 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4970 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4971 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4972 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4975 let isAsmParserOnly = 1, Predicates = [HasAVX],
4976 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4977 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4978 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4979 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4980 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4981 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4982 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4985 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4986 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4987 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4988 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4989 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4990 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4991 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4994 // Packed Compare Implicit Length Strings, Return Index
4995 let Defs = [ECX, EFLAGS] in {
4996 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4997 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4998 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4999 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5000 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5001 (implicit EFLAGS)]>, OpSize;
5002 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5003 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5004 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5005 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5006 (implicit EFLAGS)]>, OpSize;
5010 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5011 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5013 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5015 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5017 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5019 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5021 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5025 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5026 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5027 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5028 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5029 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5030 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5032 // Packed Compare Explicit Length Strings, Return Index
5033 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5034 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5035 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5036 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5037 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5038 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5039 (implicit EFLAGS)]>, OpSize;
5040 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5041 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5042 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5044 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5045 (implicit EFLAGS)]>, OpSize;
5049 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5050 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5052 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5054 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5056 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5058 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5060 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5064 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5065 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5066 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5067 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5068 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5069 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5071 //===----------------------------------------------------------------------===//
5072 // SSE4.2 - CRC Instructions
5073 //===----------------------------------------------------------------------===//
5075 // No CRC instructions have AVX equivalents
5077 // crc intrinsic instruction
5078 // This set of instructions are only rm, the only difference is the size
5080 let Constraints = "$src1 = $dst" in {
5081 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5082 (ins GR32:$src1, i8mem:$src2),
5083 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5085 (int_x86_sse42_crc32_8 GR32:$src1,
5086 (load addr:$src2)))]>;
5087 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5088 (ins GR32:$src1, GR8:$src2),
5089 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5091 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
5092 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5093 (ins GR32:$src1, i16mem:$src2),
5094 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5096 (int_x86_sse42_crc32_16 GR32:$src1,
5097 (load addr:$src2)))]>,
5099 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5100 (ins GR32:$src1, GR16:$src2),
5101 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5103 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
5105 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5106 (ins GR32:$src1, i32mem:$src2),
5107 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5109 (int_x86_sse42_crc32_32 GR32:$src1,
5110 (load addr:$src2)))]>;
5111 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5112 (ins GR32:$src1, GR32:$src2),
5113 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5115 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
5116 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5117 (ins GR64:$src1, i8mem:$src2),
5118 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5120 (int_x86_sse42_crc64_8 GR64:$src1,
5121 (load addr:$src2)))]>,
5123 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5124 (ins GR64:$src1, GR8:$src2),
5125 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5127 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
5129 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5130 (ins GR64:$src1, i64mem:$src2),
5131 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5133 (int_x86_sse42_crc64_64 GR64:$src1,
5134 (load addr:$src2)))]>,
5136 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5137 (ins GR64:$src1, GR64:$src2),
5138 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5140 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
5144 //===----------------------------------------------------------------------===//
5145 // AES-NI Instructions
5146 //===----------------------------------------------------------------------===//
5148 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5149 Intrinsic IntId128, bit Is2Addr = 1> {
5150 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5151 (ins VR128:$src1, VR128:$src2),
5153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5155 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5157 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5158 (ins VR128:$src1, i128mem:$src2),
5160 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5161 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5163 (IntId128 VR128:$src1,
5164 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5167 // Perform One Round of an AES Encryption/Decryption Flow
5168 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5169 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5170 int_x86_aesni_aesenc, 0>, VEX_4V;
5171 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5172 int_x86_aesni_aesenclast, 0>, VEX_4V;
5173 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5174 int_x86_aesni_aesdec, 0>, VEX_4V;
5175 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5176 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5179 let Constraints = "$src1 = $dst" in {
5180 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5181 int_x86_aesni_aesenc>;
5182 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5183 int_x86_aesni_aesenclast>;
5184 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5185 int_x86_aesni_aesdec>;
5186 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5187 int_x86_aesni_aesdeclast>;
5190 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5191 (AESENCrr VR128:$src1, VR128:$src2)>;
5192 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5193 (AESENCrm VR128:$src1, addr:$src2)>;
5194 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5195 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5196 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5197 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5198 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5199 (AESDECrr VR128:$src1, VR128:$src2)>;
5200 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5201 (AESDECrm VR128:$src1, addr:$src2)>;
5202 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5203 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5204 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5205 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5207 // Perform the AES InvMixColumn Transformation
5208 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5209 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5211 "vaesimc\t{$src1, $dst|$dst, $src1}",
5213 (int_x86_aesni_aesimc VR128:$src1))]>,
5215 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5216 (ins i128mem:$src1),
5217 "vaesimc\t{$src1, $dst|$dst, $src1}",
5219 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5222 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5224 "aesimc\t{$src1, $dst|$dst, $src1}",
5226 (int_x86_aesni_aesimc VR128:$src1))]>,
5228 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5229 (ins i128mem:$src1),
5230 "aesimc\t{$src1, $dst|$dst, $src1}",
5232 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5235 // AES Round Key Generation Assist
5236 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5237 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5238 (ins VR128:$src1, i8imm:$src2),
5239 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5241 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5243 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5244 (ins i128mem:$src1, i8imm:$src2),
5245 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5247 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5251 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5252 (ins VR128:$src1, i8imm:$src2),
5253 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5255 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5257 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5258 (ins i128mem:$src1, i8imm:$src2),
5259 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5261 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5265 //===----------------------------------------------------------------------===//
5266 // CLMUL Instructions
5267 //===----------------------------------------------------------------------===//
5269 // Only the AVX version of CLMUL instructions are described here.
5271 // Carry-less Multiplication instructions
5272 let isAsmParserOnly = 1 in {
5273 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5274 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5275 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5278 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5279 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5280 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5284 multiclass avx_vpclmul<string asm> {
5285 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5286 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5289 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5290 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5293 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5294 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5295 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5296 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5298 } // isAsmParserOnly
5300 //===----------------------------------------------------------------------===//
5302 //===----------------------------------------------------------------------===//
5304 let isAsmParserOnly = 1 in {
5306 // Load from memory and broadcast to all elements of the destination operand
5307 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5308 X86MemOperand x86memop, Intrinsic Int> :
5309 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5310 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5311 [(set RC:$dst, (Int addr:$src))]>, VEX;
5313 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5314 int_x86_avx_vbroadcastss>;
5315 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5316 int_x86_avx_vbroadcastss_256>;
5317 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5318 int_x86_avx_vbroadcast_sd_256>;
5319 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5320 int_x86_avx_vbroadcastf128_pd_256>;
5322 // Insert packed floating-point values
5323 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5324 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5325 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5327 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5328 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5329 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5332 // Extract packed floating-point values
5333 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5334 (ins VR256:$src1, i8imm:$src2),
5335 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5337 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5338 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5339 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5342 // Conditional SIMD Packed Loads and Stores
5343 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5344 Intrinsic IntLd, Intrinsic IntLd256,
5345 Intrinsic IntSt, Intrinsic IntSt256,
5346 PatFrag pf128, PatFrag pf256> {
5347 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5348 (ins VR128:$src1, f128mem:$src2),
5349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5350 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5352 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5353 (ins VR256:$src1, f256mem:$src2),
5354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5355 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5357 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5358 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5359 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5360 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5361 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5362 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5363 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5364 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5367 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5368 int_x86_avx_maskload_ps,
5369 int_x86_avx_maskload_ps_256,
5370 int_x86_avx_maskstore_ps,
5371 int_x86_avx_maskstore_ps_256,
5372 memopv4f32, memopv8f32>;
5373 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5374 int_x86_avx_maskload_pd,
5375 int_x86_avx_maskload_pd_256,
5376 int_x86_avx_maskstore_pd,
5377 int_x86_avx_maskstore_pd_256,
5378 memopv2f64, memopv4f64>;
5380 // Permute Floating-Point Values
5381 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5382 RegisterClass RC, X86MemOperand x86memop_f,
5383 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5384 Intrinsic IntVar, Intrinsic IntImm> {
5385 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5386 (ins RC:$src1, RC:$src2),
5387 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5388 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5389 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5390 (ins RC:$src1, x86memop_i:$src2),
5391 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5392 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5394 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5395 (ins RC:$src1, i8imm:$src2),
5396 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5397 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5398 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5399 (ins x86memop_f:$src1, i8imm:$src2),
5400 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5401 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5404 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5405 memopv4f32, memopv4i32,
5406 int_x86_avx_vpermilvar_ps,
5407 int_x86_avx_vpermil_ps>;
5408 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5409 memopv8f32, memopv8i32,
5410 int_x86_avx_vpermilvar_ps_256,
5411 int_x86_avx_vpermil_ps_256>;
5412 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5413 memopv2f64, memopv2i64,
5414 int_x86_avx_vpermilvar_pd,
5415 int_x86_avx_vpermil_pd>;
5416 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5417 memopv4f64, memopv4i64,
5418 int_x86_avx_vpermilvar_pd_256,
5419 int_x86_avx_vpermil_pd_256>;
5421 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5422 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5423 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5425 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5426 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5427 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5430 // Zero All YMM registers
5431 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5432 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5434 // Zero Upper bits of YMM registers
5435 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5436 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5438 } // isAsmParserOnly
5440 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5441 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5442 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5443 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5444 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5445 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5447 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5449 (VINSERTF128rr VR256:$src1, VR128:$src2,
5450 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5451 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5453 (VINSERTF128rr VR256:$src1, VR128:$src2,
5454 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5455 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5457 (VINSERTF128rr VR256:$src1, VR128:$src2,
5458 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5459 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5461 (VINSERTF128rr VR256:$src1, VR128:$src2,
5462 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5464 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5465 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5466 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5467 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5468 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5469 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5471 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5472 (v4f32 (VEXTRACTF128rr
5473 (v8f32 VR256:$src1),
5474 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5475 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5476 (v2f64 (VEXTRACTF128rr
5477 (v4f64 VR256:$src1),
5478 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5479 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5480 (v4i32 (VEXTRACTF128rr
5481 (v8i32 VR256:$src1),
5482 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5483 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5484 (v2i64 (VEXTRACTF128rr
5485 (v4i64 VR256:$src1),
5486 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5488 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5489 (VBROADCASTF128 addr:$src)>;
5491 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5492 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5493 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5494 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5495 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5496 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5498 def : Pat<(int_x86_avx_vperm2f128_ps_256
5499 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5500 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5501 def : Pat<(int_x86_avx_vperm2f128_pd_256
5502 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5503 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5504 def : Pat<(int_x86_avx_vperm2f128_si_256
5505 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5506 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5508 //===----------------------------------------------------------------------===//
5509 // SSE Shuffle pattern fragments
5510 //===----------------------------------------------------------------------===//
5512 // This is part of a "work in progress" refactoring. The idea is that all
5513 // vector shuffles are going to be translated into target specific nodes and
5514 // directly matched by the patterns below (which can be changed along the way)
5515 // The AVX version of some but not all of them are described here, and more
5516 // should come in a near future.
5518 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5519 // SSE2 loads, which are always promoted to v2i64. The last one should match
5520 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5521 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5522 // we investigate further.
5523 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5525 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5526 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5528 (PSHUFDmi addr:$src1, imm:$imm)>;
5529 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5531 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5533 // Shuffle with PSHUFD instruction.
5534 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5535 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5536 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5537 (PSHUFDri VR128:$src1, imm:$imm)>;
5539 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5540 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5541 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5542 (PSHUFDri VR128:$src1, imm:$imm)>;
5544 // Shuffle with SHUFPD instruction.
5545 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5546 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5547 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5548 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5549 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5550 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5552 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5553 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5554 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5555 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5557 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5558 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5559 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5560 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5562 // Shuffle with SHUFPS instruction.
5563 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5564 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5565 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5566 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5567 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5568 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5570 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5571 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5572 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5573 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5575 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5576 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5577 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5578 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5579 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5580 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5582 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5583 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5584 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5585 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5587 // Shuffle with MOVHLPS instruction
5588 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5589 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5590 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5591 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5593 // Shuffle with MOVDDUP instruction
5594 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5595 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5596 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5597 (MOVDDUPrm addr:$src)>;
5599 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5600 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5601 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5602 (MOVDDUPrm addr:$src)>;
5604 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5605 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5606 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5607 (MOVDDUPrm addr:$src)>;
5609 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5610 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5611 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5612 (MOVDDUPrm addr:$src)>;
5614 def : Pat<(X86Movddup (bc_v2f64
5615 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5616 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5617 def : Pat<(X86Movddup (bc_v2f64
5618 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5619 (MOVDDUPrm addr:$src)>;
5622 // Shuffle with UNPCKLPS
5623 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5624 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5625 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5626 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5627 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5628 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5630 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5631 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5632 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5633 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5634 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5635 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5637 // Shuffle with UNPCKHPS
5638 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5639 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5640 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5641 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5643 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5644 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5645 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5646 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5648 // Shuffle with UNPCKLPD
5649 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5650 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5651 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5652 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5653 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5654 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5656 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5657 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5658 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5659 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5660 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5661 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5663 // Shuffle with UNPCKHPD
5664 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5665 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5666 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5667 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5669 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5670 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5671 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5672 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5674 // Shuffle with PUNPCKLBW
5675 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1,
5676 (bc_v16i8 (memopv2i64 addr:$src2)))),
5677 (PUNPCKLBWrm VR128:$src1, addr:$src2)>;
5678 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)),
5679 (PUNPCKLBWrr VR128:$src1, VR128:$src2)>;
5681 // Shuffle with PUNPCKLWD
5682 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1,
5683 (bc_v8i16 (memopv2i64 addr:$src2)))),
5684 (PUNPCKLWDrm VR128:$src1, addr:$src2)>;
5685 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)),
5686 (PUNPCKLWDrr VR128:$src1, VR128:$src2)>;
5688 // Shuffle with PUNPCKLDQ
5689 def : Pat<(v4i32 (X86Punpckldq VR128:$src1,
5690 (bc_v4i32 (memopv2i64 addr:$src2)))),
5691 (PUNPCKLDQrm VR128:$src1, addr:$src2)>;
5692 def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)),
5693 (PUNPCKLDQrr VR128:$src1, VR128:$src2)>;
5695 // Shuffle with PUNPCKLQDQ
5696 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))),
5697 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>;
5698 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)),
5699 (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>;
5701 // Shuffle with PUNPCKHBW
5702 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1,
5703 (bc_v16i8 (memopv2i64 addr:$src2)))),
5704 (PUNPCKHBWrm VR128:$src1, addr:$src2)>;
5705 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)),
5706 (PUNPCKHBWrr VR128:$src1, VR128:$src2)>;
5708 // Shuffle with PUNPCKHWD
5709 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1,
5710 (bc_v8i16 (memopv2i64 addr:$src2)))),
5711 (PUNPCKHWDrm VR128:$src1, addr:$src2)>;
5712 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)),
5713 (PUNPCKHWDrr VR128:$src1, VR128:$src2)>;
5715 // Shuffle with PUNPCKHDQ
5716 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1,
5717 (bc_v4i32 (memopv2i64 addr:$src2)))),
5718 (PUNPCKHDQrm VR128:$src1, addr:$src2)>;
5719 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)),
5720 (PUNPCKHDQrr VR128:$src1, VR128:$src2)>;
5722 // Shuffle with PUNPCKHQDQ
5723 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))),
5724 (PUNPCKHQDQrm VR128:$src1, addr:$src2)>;
5725 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)),
5726 (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>;
5728 // Shuffle with MOVLHPS
5729 def : Pat<(X86Movlhps VR128:$src1,
5730 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5731 (MOVHPSrm VR128:$src1, addr:$src2)>;
5732 def : Pat<(X86Movlhps VR128:$src1,
5733 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5734 (MOVHPSrm VR128:$src1, addr:$src2)>;
5735 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5736 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5737 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5738 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5739 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5740 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5742 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5743 // is during lowering, where it's not possible to recognize the load fold cause
5744 // it has two uses through a bitcast. One use disappears at isel time and the
5745 // fold opportunity reappears.
5746 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5747 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5749 // Shuffle with MOVLHPD
5750 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5751 (scalar_to_vector (loadf64 addr:$src2)))),
5752 (MOVHPDrm VR128:$src1, addr:$src2)>;
5754 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5755 // is during lowering, where it's not possible to recognize the load fold cause
5756 // it has two uses through a bitcast. One use disappears at isel time and the
5757 // fold opportunity reappears.
5758 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5759 (scalar_to_vector (loadf64 addr:$src2)))),
5760 (MOVHPDrm VR128:$src1, addr:$src2)>;
5762 // Shuffle with MOVSS
5763 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5764 (MOVSSrr VR128:$src1, FR32:$src2)>;
5765 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5766 (MOVSSrr (v4i32 VR128:$src1),
5767 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5768 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5769 (MOVSSrr (v4f32 VR128:$src1),
5770 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5771 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5772 // is during lowering, where it's not possible to recognize the load fold cause
5773 // it has two uses through a bitcast. One use disappears at isel time and the
5774 // fold opportunity reappears.
5775 def : Pat<(X86Movss VR128:$src1,
5776 (bc_v4i32 (v2i64 (load addr:$src2)))),
5777 (MOVLPSrm VR128:$src1, addr:$src2)>;
5779 // Shuffle with MOVSD
5780 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5781 (MOVSDrr VR128:$src1, FR64:$src2)>;
5782 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5783 (MOVSDrr (v2i64 VR128:$src1),
5784 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5785 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5786 (MOVSDrr (v2f64 VR128:$src1),
5787 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5788 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5789 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5790 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5791 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5793 // Shuffle with MOVSHDUP
5794 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5795 (MOVSHDUPrr VR128:$src)>;
5796 def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))),
5797 (MOVSHDUPrm addr:$src)>;
5799 def : Pat<(v4f32 (X86Movshdup VR128:$src)),
5800 (MOVSHDUPrr VR128:$src)>;
5801 def : Pat<(X86Movshdup (memopv4f32 addr:$src)),
5802 (MOVSHDUPrm addr:$src)>;
5804 // Shuffle with MOVSLDUP
5805 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5806 (MOVSLDUPrr VR128:$src)>;
5807 def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))),
5808 (MOVSLDUPrm addr:$src)>;
5810 def : Pat<(v4f32 (X86Movsldup VR128:$src)),
5811 (MOVSLDUPrr VR128:$src)>;
5812 def : Pat<(X86Movsldup (memopv4f32 addr:$src)),
5813 (MOVSLDUPrm addr:$src)>;
5815 // Shuffle with PSHUFHW
5816 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5817 (PSHUFHWri VR128:$src, imm:$imm)>;
5818 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5819 (PSHUFHWmi addr:$src, imm:$imm)>;
5821 // Shuffle with PSHUFLW
5822 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5823 (PSHUFLWri VR128:$src, imm:$imm)>;
5824 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5825 (PSHUFLWmi addr:$src, imm:$imm)>;
5827 // Shuffle with PALIGN
5828 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5829 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5830 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5831 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5832 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5833 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5834 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5835 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5837 // Shuffle with MOVLPS
5838 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5839 (MOVLPSrm VR128:$src1, addr:$src2)>;
5840 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5841 (MOVLPSrm VR128:$src1, addr:$src2)>;
5842 def : Pat<(X86Movlps VR128:$src1,
5843 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5844 (MOVLPSrm VR128:$src1, addr:$src2)>;
5845 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5846 // is during lowering, where it's not possible to recognize the load fold cause
5847 // it has two uses through a bitcast. One use disappears at isel time and the
5848 // fold opportunity reappears.
5849 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5850 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5852 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5853 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5855 // Shuffle with MOVLPD
5856 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5857 (MOVLPDrm VR128:$src1, addr:$src2)>;
5858 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5859 (MOVLPDrm VR128:$src1, addr:$src2)>;
5860 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5861 (scalar_to_vector (loadf64 addr:$src2)))),
5862 (MOVLPDrm VR128:$src1, addr:$src2)>;
5864 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5865 def : Pat<(store (f64 (vector_extract
5866 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5867 (MOVHPSmr addr:$dst, VR128:$src)>;
5868 def : Pat<(store (f64 (vector_extract
5869 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5870 (MOVHPDmr addr:$dst, VR128:$src)>;
5872 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5873 (MOVLPSmr addr:$src1, VR128:$src2)>;
5874 def : Pat<(store (v4i32 (X86Movlps
5875 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5876 (MOVLPSmr addr:$src1, VR128:$src2)>;
5878 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5879 (MOVLPDmr addr:$src1, VR128:$src2)>;
5880 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5881 (MOVLPDmr addr:$src1, VR128:$src2)>;