1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
371 // SSE 1 & 2 Instructions Classes
372 //===----------------------------------------------------------------------===//
374 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
375 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
376 RegisterClass RC, X86MemOperand x86memop> {
377 let isCommutable = 1 in {
378 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
379 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
381 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
382 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
385 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
386 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
387 string asm, string SSEVer, string FPSizeStr,
388 Operand memopr, ComplexPattern mem_cpat> {
389 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
390 asm, [(set RC:$dst, (
391 !nameconcat<Intrinsic>("int_x86_sse",
392 !strconcat(SSEVer, !strconcat("_",
393 !strconcat(OpcodeStr, FPSizeStr))))
394 RC:$src1, RC:$src2))]>;
395 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
396 asm, [(set RC:$dst, (
397 !nameconcat<Intrinsic>("int_x86_sse",
398 !strconcat(SSEVer, !strconcat("_",
399 !strconcat(OpcodeStr, FPSizeStr))))
400 RC:$src1, mem_cpat:$src2))]>;
403 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
404 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
405 RegisterClass RC, ValueType vt,
406 X86MemOperand x86memop, PatFrag mem_frag,
407 Domain d, bit MayLoad = 0> {
408 let isCommutable = 1 in
409 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
410 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
411 let mayLoad = MayLoad in
412 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
413 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
414 (mem_frag addr:$src2)))],d>;
417 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
418 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
419 string OpcodeStr, X86MemOperand x86memop,
420 list<dag> pat_rr, list<dag> pat_rm> {
421 let isCommutable = 1 in
422 def rr : PI<opc, MRMSrcReg, (outs RC:$dst),
423 (ins RC:$src1, RC:$src2), OpcodeStr, pat_rr, d>;
424 def rm : PI<opc, MRMSrcMem, (outs RC:$dst),
425 (ins RC:$src1, x86memop:$src2), OpcodeStr, pat_rm, d>;
428 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
429 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
430 string asm, string SSEVer, string FPSizeStr,
431 X86MemOperand x86memop, PatFrag mem_frag,
433 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
434 asm, [(set RC:$dst, (
435 !nameconcat<Intrinsic>("int_x86_sse",
436 !strconcat(SSEVer, !strconcat("_",
437 !strconcat(OpcodeStr, FPSizeStr))))
438 RC:$src1, RC:$src2))], d>;
439 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
440 asm, [(set RC:$dst, (
441 !nameconcat<Intrinsic>("int_x86_sse",
442 !strconcat(SSEVer, !strconcat("_",
443 !strconcat(OpcodeStr, FPSizeStr))))
444 RC:$src1, (mem_frag addr:$src2)))], d>;
447 //===----------------------------------------------------------------------===//
448 // SSE 1 & 2 - Move Instructions
449 //===----------------------------------------------------------------------===//
451 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
452 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
453 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
455 // Loading from memory automatically zeroing upper bits.
456 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
457 PatFrag mem_pat, string OpcodeStr> :
458 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
459 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
460 [(set RC:$dst, (mem_pat addr:$src))]>;
462 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
463 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
464 // is used instead. Register-to-register movss/movsd is not modeled as an
465 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
466 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
467 let isAsmParserOnly = 1 in {
468 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
469 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
470 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
471 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
473 let canFoldAsLoad = 1, isReMaterializable = 1 in {
474 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
476 let AddedComplexity = 20 in
477 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
481 let Constraints = "$src1 = $dst" in {
482 def MOVSSrr : sse12_move_rr<FR32, v4f32,
483 "movss\t{$src2, $dst|$dst, $src2}">, XS;
484 def MOVSDrr : sse12_move_rr<FR64, v2f64,
485 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
488 let canFoldAsLoad = 1, isReMaterializable = 1 in {
489 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
491 let AddedComplexity = 20 in
492 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
495 let AddedComplexity = 15 in {
496 // Extract the low 32-bit value from one vector and insert it into another.
497 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
498 (MOVSSrr (v4f32 VR128:$src1),
499 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
500 // Extract the low 64-bit value from one vector and insert it into another.
501 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
502 (MOVSDrr (v2f64 VR128:$src1),
503 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
506 // Implicitly promote a 32-bit scalar to a vector.
507 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
508 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
509 // Implicitly promote a 64-bit scalar to a vector.
510 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
511 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
513 let AddedComplexity = 20 in {
514 // MOVSSrm zeros the high parts of the register; represent this
515 // with SUBREG_TO_REG.
516 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
517 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
518 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
519 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
520 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
521 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
522 // MOVSDrm zeros the high parts of the register; represent this
523 // with SUBREG_TO_REG.
524 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
525 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
526 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
527 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
528 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
529 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
530 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
531 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
532 def : Pat<(v2f64 (X86vzload addr:$src)),
533 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
536 // Store scalar value to memory.
537 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
538 "movss\t{$src, $dst|$dst, $src}",
539 [(store FR32:$src, addr:$dst)]>;
540 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
541 "movsd\t{$src, $dst|$dst, $src}",
542 [(store FR64:$src, addr:$dst)]>;
544 let isAsmParserOnly = 1 in {
545 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
546 "movss\t{$src, $dst|$dst, $src}",
547 [(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
548 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
549 "movsd\t{$src, $dst|$dst, $src}",
550 [(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
553 // Extract and store.
554 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
557 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
558 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
561 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
563 // Move Aligned/Unaligned floating point values
564 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
565 X86MemOperand x86memop, PatFrag ld_frag,
566 string asm, Domain d,
567 bit IsReMaterializable = 1> {
568 let neverHasSideEffects = 1 in
569 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
570 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
571 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
572 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
573 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
574 [(set RC:$dst, (ld_frag addr:$src))], d>;
577 let isAsmParserOnly = 1 in {
578 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
579 "movaps", SSEPackedSingle>, VEX;
580 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
581 "movapd", SSEPackedDouble>, OpSize, VEX;
582 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
583 "movups", SSEPackedSingle>, VEX;
584 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
585 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
587 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
588 "movaps", SSEPackedSingle>, TB;
589 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
590 "movapd", SSEPackedDouble>, TB, OpSize;
591 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
592 "movups", SSEPackedSingle>, TB;
593 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
594 "movupd", SSEPackedDouble, 0>, TB, OpSize;
596 let isAsmParserOnly = 1 in {
597 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
598 "movaps\t{$src, $dst|$dst, $src}",
599 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
600 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
601 "movapd\t{$src, $dst|$dst, $src}",
602 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
603 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
604 "movups\t{$src, $dst|$dst, $src}",
605 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
606 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
607 "movupd\t{$src, $dst|$dst, $src}",
608 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
610 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
611 "movaps\t{$src, $dst|$dst, $src}",
612 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
613 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
614 "movapd\t{$src, $dst|$dst, $src}",
615 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
616 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
617 "movups\t{$src, $dst|$dst, $src}",
618 [(store (v4f32 VR128:$src), addr:$dst)]>;
619 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
620 "movupd\t{$src, $dst|$dst, $src}",
621 [(store (v2f64 VR128:$src), addr:$dst)]>;
623 // Intrinsic forms of MOVUPS/D load and store
624 let isAsmParserOnly = 1 in {
625 let canFoldAsLoad = 1, isReMaterializable = 1 in
626 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
628 "movups\t{$src, $dst|$dst, $src}",
629 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
630 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
632 "movupd\t{$src, $dst|$dst, $src}",
633 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
634 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
635 (ins f128mem:$dst, VR128:$src),
636 "movups\t{$src, $dst|$dst, $src}",
637 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
638 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
639 (ins f128mem:$dst, VR128:$src),
640 "movupd\t{$src, $dst|$dst, $src}",
641 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
643 let canFoldAsLoad = 1, isReMaterializable = 1 in
644 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
645 "movups\t{$src, $dst|$dst, $src}",
646 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
647 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
648 "movupd\t{$src, $dst|$dst, $src}",
649 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
651 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
652 "movups\t{$src, $dst|$dst, $src}",
653 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
654 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
655 "movupd\t{$src, $dst|$dst, $src}",
656 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
658 // Move Low/High packed floating point values
659 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
660 PatFrag mov_frag, string base_opc,
662 def PSrm : PI<opc, MRMSrcMem,
663 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
664 !strconcat(!strconcat(base_opc,"s"), asm_opr),
667 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
668 SSEPackedSingle>, TB;
670 def PDrm : PI<opc, MRMSrcMem,
671 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
672 !strconcat(!strconcat(base_opc,"d"), asm_opr),
673 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
674 (scalar_to_vector (loadf64 addr:$src2)))))],
675 SSEPackedDouble>, TB, OpSize;
678 let isAsmParserOnly = 1, AddedComplexity = 20 in {
679 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
680 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
681 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
682 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
684 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
685 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
686 "\t{$src2, $dst|$dst, $src2}">;
687 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
688 "\t{$src2, $dst|$dst, $src2}">;
691 let isAsmParserOnly = 1 in {
692 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
693 "movlps\t{$src, $dst|$dst, $src}",
694 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
695 (iPTR 0))), addr:$dst)]>, VEX;
696 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
697 "movlpd\t{$src, $dst|$dst, $src}",
698 [(store (f64 (vector_extract (v2f64 VR128:$src),
699 (iPTR 0))), addr:$dst)]>, VEX;
701 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
702 "movlps\t{$src, $dst|$dst, $src}",
703 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
704 (iPTR 0))), addr:$dst)]>;
705 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
706 "movlpd\t{$src, $dst|$dst, $src}",
707 [(store (f64 (vector_extract (v2f64 VR128:$src),
708 (iPTR 0))), addr:$dst)]>;
710 // v2f64 extract element 1 is always custom lowered to unpack high to low
711 // and extract element 0 so the non-store version isn't too horrible.
712 let isAsmParserOnly = 1 in {
713 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
714 "movhps\t{$src, $dst|$dst, $src}",
715 [(store (f64 (vector_extract
716 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
717 (undef)), (iPTR 0))), addr:$dst)]>,
719 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
720 "movhpd\t{$src, $dst|$dst, $src}",
721 [(store (f64 (vector_extract
722 (v2f64 (unpckh VR128:$src, (undef))),
723 (iPTR 0))), addr:$dst)]>,
726 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
727 "movhps\t{$src, $dst|$dst, $src}",
728 [(store (f64 (vector_extract
729 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
730 (undef)), (iPTR 0))), addr:$dst)]>;
731 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movhpd\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract
734 (v2f64 (unpckh VR128:$src, (undef))),
735 (iPTR 0))), addr:$dst)]>;
737 let isAsmParserOnly = 1, AddedComplexity = 20 in {
738 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
739 (ins VR128:$src1, VR128:$src2),
740 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
742 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
744 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
745 (ins VR128:$src1, VR128:$src2),
746 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
748 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
751 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
752 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
753 (ins VR128:$src1, VR128:$src2),
754 "movlhps\t{$src2, $dst|$dst, $src2}",
756 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
757 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
758 (ins VR128:$src1, VR128:$src2),
759 "movhlps\t{$src2, $dst|$dst, $src2}",
761 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
764 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
765 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
766 let AddedComplexity = 20 in {
767 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
768 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
769 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
770 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
773 //===----------------------------------------------------------------------===//
774 // SSE 1 & 2 - Conversion Instructions
775 //===----------------------------------------------------------------------===//
777 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
778 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
780 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
781 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
782 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
783 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
786 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
787 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
788 string asm, Domain d> {
789 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
790 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
791 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
792 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
795 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
796 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
798 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
800 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
801 (ins DstRC:$src1, x86memop:$src), asm, []>;
804 let isAsmParserOnly = 1 in {
805 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
806 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
807 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
808 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
809 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
810 "cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
812 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
813 "cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
817 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
818 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
819 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
820 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
821 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
822 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
823 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
824 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
826 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
827 // and/or XMM operand(s).
828 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
829 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
830 string asm, Domain d> {
831 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
832 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
833 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
834 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
837 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
838 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
840 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
841 [(set DstRC:$dst, (Int SrcRC:$src))]>;
842 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
843 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
846 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
847 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
848 PatFrag ld_frag, string asm, Domain d> {
849 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
850 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
851 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
852 (ins DstRC:$src1, x86memop:$src2), asm,
853 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
856 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
857 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
858 PatFrag ld_frag, string asm> {
859 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
860 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
861 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
862 (ins DstRC:$src1, x86memop:$src2), asm,
863 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
866 let isAsmParserOnly = 1 in {
867 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
868 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
870 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
871 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
874 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
875 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
876 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
877 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
880 let Constraints = "$src1 = $dst" in {
881 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
882 int_x86_sse_cvtsi2ss, i32mem, loadi32,
883 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
884 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
885 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
886 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
889 // Instructions below don't have an AVX form.
890 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
891 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
892 SSEPackedSingle>, TB;
893 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
894 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
895 SSEPackedDouble>, TB, OpSize;
896 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
897 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
898 SSEPackedSingle>, TB;
899 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
900 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
901 SSEPackedDouble>, TB, OpSize;
902 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
903 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
904 SSEPackedDouble>, TB, OpSize;
905 let Constraints = "$src1 = $dst" in {
906 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
907 int_x86_sse_cvtpi2ps,
908 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
909 SSEPackedSingle>, TB;
914 // Aliases for intrinsics
915 let isAsmParserOnly = 1, Pattern = []<dag> in {
916 defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
917 int_x86_sse_cvttss2si, f32mem, load,
918 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
919 defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
920 int_x86_sse2_cvttsd2si, f128mem, load,
921 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
923 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
924 f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
926 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
927 f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
930 let isAsmParserOnly = 1, Pattern = []<dag> in {
931 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
932 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
933 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
934 "cvtdq2ps\t{$src, $dst|$dst, $src}",
935 SSEPackedSingle>, TB, VEX;
937 let Pattern = []<dag> in {
938 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
939 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
940 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
941 "cvtdq2ps\t{$src, $dst|$dst, $src}",
942 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
947 // Convert scalar double to scalar single
948 let isAsmParserOnly = 1 in {
949 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
950 (ins FR64:$src1, FR64:$src2),
951 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
953 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
954 (ins FR64:$src1, f64mem:$src2),
955 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
956 []>, XD, Requires<[HasAVX, HasSSE2, OptForSize]>, VEX_4V;
958 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
959 "cvtsd2ss\t{$src, $dst|$dst, $src}",
960 [(set FR32:$dst, (fround FR64:$src))]>;
961 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
962 "cvtsd2ss\t{$src, $dst|$dst, $src}",
963 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
964 Requires<[HasSSE2, OptForSize]>;
966 let isAsmParserOnly = 1 in
967 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
968 int_x86_sse2_cvtsd2ss, f64mem, load,
969 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
971 let Constraints = "$src1 = $dst" in
972 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
973 int_x86_sse2_cvtsd2ss, f64mem, load,
974 "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
976 // Convert scalar single to scalar double
977 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
978 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
979 (ins FR32:$src1, FR32:$src2),
980 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
981 []>, XS, Requires<[HasAVX, HasSSE2]>, VEX_4V;
982 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
983 (ins FR32:$src1, f32mem:$src2),
984 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
985 []>, XS, VEX_4V, Requires<[HasAVX, HasSSE2, OptForSize]>;
987 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
988 "cvtss2sd\t{$src, $dst|$dst, $src}",
989 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
991 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
992 "cvtss2sd\t{$src, $dst|$dst, $src}",
993 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
994 Requires<[HasSSE2, OptForSize]>;
996 let isAsmParserOnly = 1 in {
997 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
998 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
999 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1000 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1001 VR128:$src2))]>, XS, VEX_4V,
1002 Requires<[HasAVX, HasSSE2]>;
1003 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1004 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1005 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1006 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1007 (load addr:$src2)))]>, XS, VEX_4V,
1008 Requires<[HasAVX, HasSSE2]>;
1010 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1011 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1012 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1013 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1014 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1015 VR128:$src2))]>, XS,
1016 Requires<[HasSSE2]>;
1017 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1018 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1019 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1020 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1021 (load addr:$src2)))]>, XS,
1022 Requires<[HasSSE2]>;
1025 def : Pat<(extloadf32 addr:$src),
1026 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1027 Requires<[HasSSE2, OptForSpeed]>;
1029 // Convert doubleword to packed single/double fp
1030 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
1031 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1032 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1033 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1034 TB, VEX, Requires<[HasAVX, HasSSE2]>;
1035 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1036 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1037 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1038 (bitconvert (memopv2i64 addr:$src))))]>,
1039 TB, VEX, Requires<[HasAVX, HasSSE2]>;
1041 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1042 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1043 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1044 TB, Requires<[HasSSE2]>;
1045 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1046 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1047 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1048 (bitconvert (memopv2i64 addr:$src))))]>,
1049 TB, Requires<[HasSSE2]>;
1051 // FIXME: why the non-intrinsic version is described as SSE3?
1052 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
1053 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1054 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1055 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1056 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1057 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1058 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1059 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1060 (bitconvert (memopv2i64 addr:$src))))]>,
1061 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1063 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1064 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1065 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1066 XS, Requires<[HasSSE2]>;
1067 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1068 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1069 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1070 (bitconvert (memopv2i64 addr:$src))))]>,
1071 XS, Requires<[HasSSE2]>;
1073 // Convert packed single/double fp to doubleword
1074 let isAsmParserOnly = 1 in {
1075 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1076 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1077 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1078 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1080 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1081 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1082 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1083 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1085 let isAsmParserOnly = 1 in {
1086 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1087 "cvtps2dq\t{$src, $dst|$dst, $src}",
1088 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
1090 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1092 "cvtps2dq\t{$src, $dst|$dst, $src}",
1093 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1094 (memop addr:$src)))]>, VEX;
1096 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1097 "cvtps2dq\t{$src, $dst|$dst, $src}",
1098 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1099 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1100 "cvtps2dq\t{$src, $dst|$dst, $src}",
1101 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1102 (memop addr:$src)))]>;
1104 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
1105 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1106 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1107 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1108 XD, VEX, Requires<[HasAVX, HasSSE2]>;
1109 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1110 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1111 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1112 (memop addr:$src)))]>,
1113 XD, VEX, Requires<[HasAVX, HasSSE2]>;
1115 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1116 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1117 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1118 XD, Requires<[HasSSE2]>;
1119 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1120 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1121 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1122 (memop addr:$src)))]>,
1123 XD, Requires<[HasSSE2]>;
1126 // Convert with truncation packed single/double fp to doubleword
1127 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
1128 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1129 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1130 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1131 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1133 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1134 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1135 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1136 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1139 let isAsmParserOnly = 1 in {
1140 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1141 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1143 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1144 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1145 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1146 "vcvttps2dq\t{$src, $dst|$dst, $src}",
1147 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1148 (memop addr:$src)))]>,
1149 XS, VEX, Requires<[HasAVX, HasSSE2]>;
1151 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1152 "cvttps2dq\t{$src, $dst|$dst, $src}",
1154 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1155 XS, Requires<[HasSSE2]>;
1156 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1157 "cvttps2dq\t{$src, $dst|$dst, $src}",
1158 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1159 (memop addr:$src)))]>,
1160 XS, Requires<[HasSSE2]>;
1162 let isAsmParserOnly = 1 in {
1163 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
1165 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1166 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1168 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1170 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1171 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1172 (memop addr:$src)))]>, VEX;
1174 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1175 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1176 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1177 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1178 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1179 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1180 (memop addr:$src)))]>;
1182 // Convert packed single to packed double
1183 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
1184 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1185 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
1187 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1188 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
1191 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1192 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1193 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1194 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1196 let isAsmParserOnly = 1 in {
1197 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1198 "cvtps2pd\t{$src, $dst|$dst, $src}",
1199 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1200 VEX, Requires<[HasAVX, HasSSE2]>;
1201 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1202 "cvtps2pd\t{$src, $dst|$dst, $src}",
1203 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1204 (load addr:$src)))]>,
1205 VEX, Requires<[HasAVX, HasSSE2]>;
1207 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1208 "cvtps2pd\t{$src, $dst|$dst, $src}",
1209 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1210 TB, Requires<[HasSSE2]>;
1211 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1212 "cvtps2pd\t{$src, $dst|$dst, $src}",
1213 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1214 (load addr:$src)))]>,
1215 TB, Requires<[HasSSE2]>;
1217 // Convert packed double to packed single
1218 let isAsmParserOnly = 1 in {
1219 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1220 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1221 // FIXME: the memory form of this instruction should described using
1222 // use extra asm syntax
1224 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1225 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1226 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1227 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1230 let isAsmParserOnly = 1 in {
1231 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1232 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1233 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1234 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1236 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1237 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1238 (memop addr:$src)))]>;
1240 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1241 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1242 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1243 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1244 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1245 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1246 (memop addr:$src)))]>;
1248 //===----------------------------------------------------------------------===//
1249 // SSE 1 & 2 - Compare Instructions
1250 //===----------------------------------------------------------------------===//
1252 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1253 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1254 string asm, string asm_alt> {
1255 def rr : SIi8<0xC2, MRMSrcReg,
1256 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1259 def rm : SIi8<0xC2, MRMSrcMem,
1260 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1262 // Accept explicit immediate argument form instead of comparison code.
1263 let isAsmParserOnly = 1 in {
1264 def rr_alt : SIi8<0xC2, MRMSrcReg,
1265 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1268 def rm_alt : SIi8<0xC2, MRMSrcMem,
1269 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1274 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1275 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1276 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1277 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1279 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1280 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1281 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1285 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1286 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1287 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1288 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1289 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1290 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1291 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1294 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1295 Intrinsic Int, string asm> {
1296 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1297 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1298 [(set VR128:$dst, (Int VR128:$src1,
1299 VR128:$src, imm:$cc))]>;
1300 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1301 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1302 [(set VR128:$dst, (Int VR128:$src1,
1303 (load addr:$src), imm:$cc))]>;
1306 // Aliases to match intrinsics which expect XMM operand(s).
1307 let isAsmParserOnly = 1 in {
1308 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1309 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1311 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1312 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1315 let Constraints = "$src1 = $dst" in {
1316 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1317 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1318 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1319 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1323 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1324 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1325 ValueType vt, X86MemOperand x86memop,
1326 PatFrag ld_frag, string OpcodeStr, Domain d> {
1327 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1328 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1329 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1330 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1331 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1332 [(set EFLAGS, (OpNode (vt RC:$src1),
1333 (ld_frag addr:$src2)))], d>;
1336 let Defs = [EFLAGS] in {
1337 let isAsmParserOnly = 1 in {
1338 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1339 "ucomiss", SSEPackedSingle>, VEX;
1340 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1341 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1342 let Pattern = []<dag> in {
1343 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1344 "comiss", SSEPackedSingle>, VEX;
1345 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1346 "comisd", SSEPackedDouble>, OpSize, VEX;
1349 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1350 load, "ucomiss", SSEPackedSingle>, VEX;
1351 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1352 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1354 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1355 load, "comiss", SSEPackedSingle>, VEX;
1356 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1357 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1359 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1360 "ucomiss", SSEPackedSingle>, TB;
1361 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1362 "ucomisd", SSEPackedDouble>, TB, OpSize;
1364 let Pattern = []<dag> in {
1365 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1366 "comiss", SSEPackedSingle>, TB;
1367 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1368 "comisd", SSEPackedDouble>, TB, OpSize;
1371 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1372 load, "ucomiss", SSEPackedSingle>, TB;
1373 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1374 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1376 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1377 "comiss", SSEPackedSingle>, TB;
1378 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1379 "comisd", SSEPackedDouble>, TB, OpSize;
1380 } // Defs = [EFLAGS]
1382 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1383 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1384 Intrinsic Int, string asm, string asm_alt,
1386 def rri : PIi8<0xC2, MRMSrcReg,
1387 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1388 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1389 def rmi : PIi8<0xC2, MRMSrcMem,
1390 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1391 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1392 // Accept explicit immediate argument form instead of comparison code.
1393 let isAsmParserOnly = 1 in {
1394 def rri_alt : PIi8<0xC2, MRMSrcReg,
1395 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1397 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1398 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1403 let isAsmParserOnly = 1 in {
1404 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1405 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1406 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1407 SSEPackedSingle>, VEX_4V;
1408 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1409 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1410 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1411 SSEPackedDouble>, OpSize, VEX_4V;
1413 let Constraints = "$src1 = $dst" in {
1414 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1415 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1416 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1417 SSEPackedSingle>, TB;
1418 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1419 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1420 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1421 SSEPackedDouble>, TB, OpSize;
1424 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1425 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1426 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1427 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1428 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1429 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1430 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1431 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1433 //===----------------------------------------------------------------------===//
1434 // SSE 1 & 2 - Shuffle Instructions
1435 //===----------------------------------------------------------------------===//
1437 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1438 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1439 ValueType vt, string asm, PatFrag mem_frag,
1440 Domain d, bit IsConvertibleToThreeAddress = 0> {
1441 def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
1442 (ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
1443 [(set VR128:$dst, (vt (shufp:$src3
1444 VR128:$src1, (mem_frag addr:$src2))))], d>;
1445 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1446 def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
1447 (ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
1449 (vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
1452 let isAsmParserOnly = 1 in {
1453 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1454 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1455 memopv4f32, SSEPackedSingle>, VEX_4V;
1456 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1457 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1458 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1461 let Constraints = "$src1 = $dst" in {
1462 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1463 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1464 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1466 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1467 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1468 memopv2f64, SSEPackedDouble>, TB, OpSize;
1471 //===----------------------------------------------------------------------===//
1472 // SSE 1 & 2 - Unpack Instructions
1473 //===----------------------------------------------------------------------===//
1475 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1476 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1477 PatFrag mem_frag, RegisterClass RC,
1478 X86MemOperand x86memop, string asm,
1480 def rr : PI<opc, MRMSrcReg,
1481 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1483 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1484 def rm : PI<opc, MRMSrcMem,
1485 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1487 (vt (OpNode RC:$src1,
1488 (mem_frag addr:$src2))))], d>;
1491 let AddedComplexity = 10 in {
1492 let isAsmParserOnly = 1 in {
1493 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1494 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1495 SSEPackedSingle>, VEX_4V;
1496 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1497 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1498 SSEPackedDouble>, OpSize, VEX_4V;
1499 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1500 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1501 SSEPackedSingle>, VEX_4V;
1502 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1503 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1504 SSEPackedDouble>, OpSize, VEX_4V;
1507 let Constraints = "$src1 = $dst" in {
1508 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1509 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1510 SSEPackedSingle>, TB;
1511 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1512 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1513 SSEPackedDouble>, TB, OpSize;
1514 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1515 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1516 SSEPackedSingle>, TB;
1517 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1518 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1519 SSEPackedDouble>, TB, OpSize;
1520 } // Constraints = "$src1 = $dst"
1521 } // AddedComplexity
1523 //===----------------------------------------------------------------------===//
1524 // SSE 1 & 2 - Extract Floating-Point Sign mask
1525 //===----------------------------------------------------------------------===//
1527 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1528 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1530 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1531 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1532 [(set GR32:$dst, (Int RC:$src))], d>;
1536 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1537 SSEPackedSingle>, TB;
1538 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1539 SSEPackedDouble>, TB, OpSize;
1541 let isAsmParserOnly = 1 in {
1542 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1543 "movmskps", SSEPackedSingle>, VEX;
1544 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1545 "movmskpd", SSEPackedDouble>, OpSize,
1549 //===----------------------------------------------------------------------===//
1550 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1551 //===----------------------------------------------------------------------===//
1553 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1554 // names that start with 'Fs'.
1556 // Alias instructions that map fld0 to pxor for sse.
1557 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1558 canFoldAsLoad = 1 in {
1559 // FIXME: Set encoding to pseudo!
1560 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1561 [(set FR32:$dst, fp32imm0)]>,
1562 Requires<[HasSSE1]>, TB, OpSize;
1563 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1564 [(set FR64:$dst, fpimm0)]>,
1565 Requires<[HasSSE2]>, TB, OpSize;
1568 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1569 // bits are disregarded.
1570 let neverHasSideEffects = 1 in {
1571 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1572 "movaps\t{$src, $dst|$dst, $src}", []>;
1573 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1574 "movapd\t{$src, $dst|$dst, $src}", []>;
1577 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1578 // bits are disregarded.
1579 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1580 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1581 "movaps\t{$src, $dst|$dst, $src}",
1582 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1583 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1584 "movapd\t{$src, $dst|$dst, $src}",
1585 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1588 //===----------------------------------------------------------------------===//
1589 // SSE 1 & 2 - Logical Instructions
1590 //===----------------------------------------------------------------------===//
1592 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1594 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1595 SDNode OpNode, bit MayLoad = 0> {
1596 let isAsmParserOnly = 1 in {
1597 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1598 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR32,
1599 f32, f128mem, memopfsf32, SSEPackedSingle, MayLoad>, VEX_4V;
1601 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1602 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode, FR64,
1603 f64, f128mem, memopfsf64, SSEPackedDouble, MayLoad>, OpSize,
1607 let Constraints = "$src1 = $dst" in {
1608 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1609 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, FR32, f32,
1610 f128mem, memopfsf32, SSEPackedSingle, MayLoad>, TB;
1612 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1613 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, FR64, f64,
1614 f128mem, memopfsf64, SSEPackedDouble, MayLoad>, TB, OpSize;
1618 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1619 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1620 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1621 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1623 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1624 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1>;
1626 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1628 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1629 SDNode OpNode, int HasPat = 0,
1630 list<list<dag>> Pattern = []> {
1631 let isAsmParserOnly = 1 in {
1632 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1633 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1635 !if(HasPat, Pattern[0], // rr
1636 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1638 !if(HasPat, Pattern[2], // rm
1639 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1640 (memopv2i64 addr:$src2)))])>,
1643 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1644 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1646 !if(HasPat, Pattern[1], // rr
1647 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1650 !if(HasPat, Pattern[3], // rm
1651 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1652 (memopv2i64 addr:$src2)))])>,
1655 let Constraints = "$src1 = $dst" in {
1656 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1657 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"), f128mem,
1658 !if(HasPat, Pattern[0], // rr
1659 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1661 !if(HasPat, Pattern[2], // rm
1662 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1663 (memopv2i64 addr:$src2)))])>, TB;
1665 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1666 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"), f128mem,
1667 !if(HasPat, Pattern[1], // rr
1668 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1671 !if(HasPat, Pattern[3], // rm
1672 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1673 (memopv2i64 addr:$src2)))])>,
1678 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1679 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1680 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1681 let isCommutable = 0 in
1682 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1684 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1685 (bc_v2i64 (v4i32 immAllOnesV))),
1688 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1689 (bc_v2i64 (v2f64 VR128:$src2))))],
1691 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1692 (bc_v2i64 (v4i32 immAllOnesV))),
1693 (memopv2i64 addr:$src2))))],
1695 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1696 (memopv2i64 addr:$src2)))]]>;
1698 //===----------------------------------------------------------------------===//
1699 // SSE 1 & 2 - Arithmetic Instructions
1700 //===----------------------------------------------------------------------===//
1702 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
1705 /// In addition, we also have a special variant of the scalar form here to
1706 /// represent the associated intrinsic operation. This form is unlike the
1707 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1708 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1710 /// These three forms can each be reg+reg or reg+mem.
1712 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1715 let isAsmParserOnly = 1 in {
1716 defm V#NAME#SS : sse12_fp_scalar<opc,
1717 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1718 OpNode, FR32, f32mem>, XS, VEX_4V;
1720 defm V#NAME#SD : sse12_fp_scalar<opc,
1721 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1722 OpNode, FR64, f64mem>, XD, VEX_4V;
1724 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1725 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1726 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1729 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1730 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1731 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1734 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1735 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1736 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1738 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1739 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1740 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1743 let Constraints = "$src1 = $dst" in {
1744 defm SS : sse12_fp_scalar<opc,
1745 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1746 OpNode, FR32, f32mem>, XS;
1748 defm SD : sse12_fp_scalar<opc,
1749 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1750 OpNode, FR64, f64mem>, XD;
1752 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1753 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1754 f128mem, memopv4f32, SSEPackedSingle>, TB;
1756 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1757 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1758 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1760 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1761 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1762 "", "_ss", ssmem, sse_load_f32>, XS;
1764 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1765 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1766 "2", "_sd", sdmem, sse_load_f64>, XD;
1770 // Arithmetic instructions
1771 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd>;
1772 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul>;
1774 let isCommutable = 0 in {
1775 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
1776 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
1779 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
1781 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
1782 /// instructions for a full-vector intrinsic form. Operations that map
1783 /// onto C operators don't use this form since they just use the plain
1784 /// vector form instead of having a separate vector intrinsic form.
1786 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
1789 let isAsmParserOnly = 1 in {
1790 // Scalar operation, reg+reg.
1791 defm V#NAME#SS : sse12_fp_scalar<opc,
1792 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1793 OpNode, FR32, f32mem>, XS, VEX_4V;
1795 defm V#NAME#SD : sse12_fp_scalar<opc,
1796 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1797 OpNode, FR64, f64mem>, XD, VEX_4V;
1799 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1800 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1801 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
1804 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1805 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
1806 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
1809 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1810 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1811 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
1813 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1814 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1815 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
1817 defm V#NAME#PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1818 !strconcat(OpcodeStr, "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1819 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, VEX_4V;
1821 defm V#NAME#PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1822 !strconcat(OpcodeStr, "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1823 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, OpSize,
1827 let Constraints = "$src1 = $dst" in {
1828 // Scalar operation, reg+reg.
1829 defm SS : sse12_fp_scalar<opc,
1830 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1831 OpNode, FR32, f32mem>, XS;
1832 defm SD : sse12_fp_scalar<opc,
1833 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1834 OpNode, FR64, f64mem>, XD;
1835 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1836 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
1837 f128mem, memopv4f32, SSEPackedSingle>, TB;
1839 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
1840 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
1841 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1843 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1844 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
1845 "", "_ss", ssmem, sse_load_f32>, XS;
1847 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1848 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1849 "2", "_sd", sdmem, sse_load_f64>, XD;
1851 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1852 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1853 "", "_ps", f128mem, memopv4f32, SSEPackedSingle>, TB;
1855 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1856 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1857 "2", "_pd", f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
1861 let isCommutable = 0 in {
1862 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
1863 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
1867 /// In addition, we also have a special variant of the scalar form here to
1868 /// represent the associated intrinsic operation. This form is unlike the
1869 /// plain scalar form, in that it takes an entire vector (instead of a
1870 /// scalar) and leaves the top elements undefined.
1872 /// And, we have a special variant form for a full-vector intrinsic form.
1874 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1875 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1876 SDNode OpNode, Intrinsic F32Int> {
1877 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1878 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1879 [(set FR32:$dst, (OpNode FR32:$src))]>;
1880 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1881 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1882 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1883 Requires<[HasSSE1, OptForSize]>;
1884 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1886 [(set VR128:$dst, (F32Int VR128:$src))]>;
1887 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1888 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1889 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1892 /// sse1_fp_unop_p - SSE1 unops in scalar form.
1893 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr,
1894 SDNode OpNode, Intrinsic V4F32Int> {
1895 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1896 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1897 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1898 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1899 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1900 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1901 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1902 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1903 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1904 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1905 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1906 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1909 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1910 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1911 SDNode OpNode, Intrinsic F32Int> {
1912 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1913 !strconcat(!strconcat("v", OpcodeStr),
1914 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1915 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1916 !strconcat(!strconcat("v", OpcodeStr),
1917 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1918 []>, XS, Requires<[HasAVX, HasSSE1, OptForSize]>;
1919 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
1920 (ins VR128:$src1, VR128:$src2),
1921 !strconcat(!strconcat("v", OpcodeStr),
1922 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1923 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
1924 (ins VR128:$src1, ssmem:$src2),
1925 !strconcat(!strconcat("v", OpcodeStr),
1926 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1929 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1930 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1931 SDNode OpNode, Intrinsic F64Int> {
1932 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1933 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1934 [(set FR64:$dst, (OpNode FR64:$src))]>;
1935 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1936 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1937 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1938 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1939 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1940 [(set VR128:$dst, (F64Int VR128:$src))]>;
1941 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1942 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1943 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1946 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1947 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1948 SDNode OpNode, Intrinsic V2F64Int> {
1949 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1951 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1952 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1953 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1954 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1955 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1956 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1957 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1958 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1959 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1960 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1963 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1964 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1965 SDNode OpNode, Intrinsic F64Int> {
1966 def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1967 !strconcat(OpcodeStr,
1968 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1969 def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
1970 (ins FR64:$src1, f64mem:$src2),
1971 !strconcat(OpcodeStr,
1972 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1973 def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
1974 (ins VR128:$src1, VR128:$src2),
1975 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1977 def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
1978 (ins VR128:$src1, sdmem:$src2),
1979 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1983 let isAsmParserOnly = 1 in {
1985 let Predicates = [HasAVX, HasSSE2] in {
1986 defm VSQRT : sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1989 defm VSQRT : sse2_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_pd>, VEX;
1992 let Predicates = [HasAVX, HasSSE1] in {
1993 defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1995 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ps>, VEX;
1996 // Reciprocal approximations. Note that these typically require refinement
1997 // in order to obtain suitable precision.
1998 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
1999 int_x86_sse_rsqrt_ss>, VEX_4V;
2000 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>,
2002 defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2004 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ps>,
2010 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
2011 sse1_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ps>,
2012 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
2013 sse2_fp_unop_p<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_pd>;
2015 // Reciprocal approximations. Note that these typically require refinement
2016 // in order to obtain suitable precision.
2017 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
2018 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ps>;
2019 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
2020 sse1_fp_unop_p<0x53, "rcp", X86frcp, int_x86_sse_rcp_ps>;
2022 // There is no f64 version of the reciprocal approximation instructions.
2024 //===----------------------------------------------------------------------===//
2025 // SSE 1 & 2 - Non-temporal stores
2026 //===----------------------------------------------------------------------===//
2028 let isAsmParserOnly = 1 in {
2029 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
2030 (ins i128mem:$dst, VR128:$src),
2031 "movntps\t{$src, $dst|$dst, $src}",
2032 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
2033 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
2034 (ins i128mem:$dst, VR128:$src),
2035 "movntpd\t{$src, $dst|$dst, $src}",
2036 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
2038 let ExeDomain = SSEPackedInt in
2039 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
2040 (ins f128mem:$dst, VR128:$src),
2041 "movntdq\t{$src, $dst|$dst, $src}",
2042 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
2044 let AddedComplexity = 400 in { // Prefer non-temporal versions
2045 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2046 (ins f128mem:$dst, VR128:$src),
2047 "movntps\t{$src, $dst|$dst, $src}",
2048 [(alignednontemporalstore (v4f32 VR128:$src),
2050 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2051 (ins f128mem:$dst, VR128:$src),
2052 "movntpd\t{$src, $dst|$dst, $src}",
2053 [(alignednontemporalstore (v2f64 VR128:$src),
2055 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2056 (ins f128mem:$dst, VR128:$src),
2057 "movntdq\t{$src, $dst|$dst, $src}",
2058 [(alignednontemporalstore (v2f64 VR128:$src),
2060 let ExeDomain = SSEPackedInt in
2061 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2062 (ins f128mem:$dst, VR128:$src),
2063 "movntdq\t{$src, $dst|$dst, $src}",
2064 [(alignednontemporalstore (v4f32 VR128:$src),
2069 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2070 "movntps\t{$src, $dst|$dst, $src}",
2071 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2072 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2073 "movntpd\t{$src, $dst|$dst, $src}",
2074 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2076 let ExeDomain = SSEPackedInt in
2077 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2078 "movntdq\t{$src, $dst|$dst, $src}",
2079 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2081 let AddedComplexity = 400 in { // Prefer non-temporal versions
2082 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2083 "movntps\t{$src, $dst|$dst, $src}",
2084 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2085 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2086 "movntpd\t{$src, $dst|$dst, $src}",
2087 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2090 "movntdq\t{$src, $dst|$dst, $src}",
2091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2093 let ExeDomain = SSEPackedInt in
2094 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2095 "movntdq\t{$src, $dst|$dst, $src}",
2096 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2098 // There is no AVX form for instructions below this point
2099 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2100 "movnti\t{$src, $dst|$dst, $src}",
2101 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2102 TB, Requires<[HasSSE2]>;
2104 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2105 "movnti\t{$src, $dst|$dst, $src}",
2106 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2107 TB, Requires<[HasSSE2]>;
2110 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2111 "movnti\t{$src, $dst|$dst, $src}",
2112 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2113 TB, Requires<[HasSSE2]>;
2115 //===----------------------------------------------------------------------===//
2116 // SSE 1 & 2 - Misc Instructions (No AVX form)
2117 //===----------------------------------------------------------------------===//
2119 // Prefetch intrinsic.
2120 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2121 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2122 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2123 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2124 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2125 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2126 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2127 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2129 // Load, store, and memory fence
2130 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2131 TB, Requires<[HasSSE1]>;
2133 // Alias instructions that map zero vector to pxor / xorp* for sse.
2134 // We set canFoldAsLoad because this can be converted to a constant-pool
2135 // load of an all-zeros value if folding it would be beneficial.
2136 // FIXME: Change encoding to pseudo!
2137 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2138 isCodeGenOnly = 1 in {
2139 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2140 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2141 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2142 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2143 let ExeDomain = SSEPackedInt in
2144 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2145 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2148 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2149 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2150 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2152 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2153 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2155 //===----------------------------------------------------------------------===//
2156 // SSE 1 & 2 - Load/Store XCSR register
2157 //===----------------------------------------------------------------------===//
2159 let isAsmParserOnly = 1 in {
2160 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2161 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2162 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2163 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2166 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2167 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2168 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2169 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2171 //===---------------------------------------------------------------------===//
2172 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2173 //===---------------------------------------------------------------------===//
2174 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2176 let isAsmParserOnly = 1 in {
2177 let neverHasSideEffects = 1 in
2178 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2179 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2180 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2181 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2183 let canFoldAsLoad = 1, mayLoad = 1 in {
2184 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2185 "movdqa\t{$src, $dst|$dst, $src}",
2186 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
2188 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2189 "vmovdqu\t{$src, $dst|$dst, $src}",
2190 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2191 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2194 let mayStore = 1 in {
2195 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2196 (ins i128mem:$dst, VR128:$src),
2197 "movdqa\t{$src, $dst|$dst, $src}",
2198 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
2199 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2200 "vmovdqu\t{$src, $dst|$dst, $src}",
2201 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2202 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2206 let neverHasSideEffects = 1 in
2207 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2208 "movdqa\t{$src, $dst|$dst, $src}", []>;
2210 let canFoldAsLoad = 1, mayLoad = 1 in {
2211 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2212 "movdqa\t{$src, $dst|$dst, $src}",
2213 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2214 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2215 "movdqu\t{$src, $dst|$dst, $src}",
2216 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2217 XS, Requires<[HasSSE2]>;
2220 let mayStore = 1 in {
2221 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2222 "movdqa\t{$src, $dst|$dst, $src}",
2223 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2224 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2225 "movdqu\t{$src, $dst|$dst, $src}",
2226 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2227 XS, Requires<[HasSSE2]>;
2230 // Intrinsic forms of MOVDQU load and store
2231 let isAsmParserOnly = 1 in {
2232 let canFoldAsLoad = 1 in
2233 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2234 "vmovdqu\t{$src, $dst|$dst, $src}",
2235 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2236 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2237 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2238 "vmovdqu\t{$src, $dst|$dst, $src}",
2239 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2240 XS, VEX, Requires<[HasAVX, HasSSE2]>;
2243 let canFoldAsLoad = 1 in
2244 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2245 "movdqu\t{$src, $dst|$dst, $src}",
2246 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2247 XS, Requires<[HasSSE2]>;
2248 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2249 "movdqu\t{$src, $dst|$dst, $src}",
2250 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2251 XS, Requires<[HasSSE2]>;
2253 } // ExeDomain = SSEPackedInt
2255 //===---------------------------------------------------------------------===//
2256 // SSE2 - Packed Integer Arithmetic Instructions
2257 //===---------------------------------------------------------------------===//
2259 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2261 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2262 bit IsCommutable = 0, bit Is2Addr = 1> {
2263 let isCommutable = IsCommutable in
2264 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2265 (ins VR128:$src1, VR128:$src2),
2267 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2268 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2269 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2270 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2271 (ins VR128:$src1, i128mem:$src2),
2273 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2274 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2275 [(set VR128:$dst, (IntId VR128:$src1,
2276 (bitconvert (memopv2i64 addr:$src2))))]>;
2279 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2280 string OpcodeStr, Intrinsic IntId,
2281 Intrinsic IntId2, bit Is2Addr = 1> {
2282 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2283 (ins VR128:$src1, VR128:$src2),
2285 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2287 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2288 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2289 (ins VR128:$src1, i128mem:$src2),
2291 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2292 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2293 [(set VR128:$dst, (IntId VR128:$src1,
2294 (bitconvert (memopv2i64 addr:$src2))))]>;
2295 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2296 (ins VR128:$src1, i32i8imm:$src2),
2298 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2299 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2300 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2303 /// PDI_binop_rm - Simple SSE2 binary operator.
2304 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2305 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2306 let isCommutable = IsCommutable in
2307 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2308 (ins VR128:$src1, VR128:$src2),
2310 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2311 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2312 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2313 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2314 (ins VR128:$src1, i128mem:$src2),
2316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2318 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2319 (bitconvert (memopv2i64 addr:$src2)))))]>;
2322 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2324 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2325 /// to collapse (bitconvert VT to VT) into its operand.
2327 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2328 bit IsCommutable = 0, bit Is2Addr = 1> {
2329 let isCommutable = IsCommutable in
2330 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2331 (ins VR128:$src1, VR128:$src2),
2333 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2334 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2335 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2336 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2337 (ins VR128:$src1, i128mem:$src2),
2339 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2340 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2341 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2344 } // ExeDomain = SSEPackedInt
2346 // 128-bit Integer Arithmetic
2348 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2349 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2350 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2351 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2352 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2353 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2354 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2355 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2356 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2357 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2360 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2362 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2364 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2366 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2368 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2370 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2372 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2374 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2376 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2378 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2380 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2382 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2384 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2386 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2388 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2390 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2392 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2394 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2396 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2400 let Constraints = "$src1 = $dst" in {
2401 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2402 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2403 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2404 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2405 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2406 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2407 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2408 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2409 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2412 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2413 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2414 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2415 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2416 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2417 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2418 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2419 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2420 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2421 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2422 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2423 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2424 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2425 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2426 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2427 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2428 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2429 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2430 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2432 } // Constraints = "$src1 = $dst"
2434 //===---------------------------------------------------------------------===//
2435 // SSE2 - Packed Integer Logical Instructions
2436 //===---------------------------------------------------------------------===//
2438 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2439 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2440 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2442 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2443 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2445 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2446 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2449 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2450 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2452 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2453 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2455 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2456 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2459 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2460 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2462 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2463 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2466 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2467 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2468 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2470 let ExeDomain = SSEPackedInt in {
2471 let neverHasSideEffects = 1 in {
2472 // 128-bit logical shifts.
2473 def VPSLLDQri : PDIi8<0x73, MRM7r,
2474 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2475 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2477 def VPSRLDQri : PDIi8<0x73, MRM3r,
2478 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2479 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2481 // PSRADQri doesn't exist in SSE[1-3].
2483 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2484 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2485 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2486 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2487 VR128:$src2)))]>, VEX_4V;
2489 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2490 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2491 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2492 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2493 (memopv2i64 addr:$src2))))]>,
2498 let Constraints = "$src1 = $dst" in {
2499 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2500 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2501 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2502 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2503 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2504 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2506 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2507 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2508 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2509 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2510 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2511 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2513 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2514 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2515 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2516 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2518 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2519 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2520 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2522 let ExeDomain = SSEPackedInt in {
2523 let neverHasSideEffects = 1 in {
2524 // 128-bit logical shifts.
2525 def PSLLDQri : PDIi8<0x73, MRM7r,
2526 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2527 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2528 def PSRLDQri : PDIi8<0x73, MRM3r,
2529 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2530 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2531 // PSRADQri doesn't exist in SSE[1-3].
2533 def PANDNrr : PDI<0xDF, MRMSrcReg,
2534 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2535 "pandn\t{$src2, $dst|$dst, $src2}",
2536 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2539 def PANDNrm : PDI<0xDF, MRMSrcMem,
2540 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2541 "pandn\t{$src2, $dst|$dst, $src2}",
2542 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2543 (memopv2i64 addr:$src2))))]>;
2545 } // Constraints = "$src1 = $dst"
2547 let Predicates = [HasSSE2] in {
2548 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2549 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2550 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2551 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2552 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2553 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2554 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2555 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2556 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2557 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2559 // Shift up / down and insert zero's.
2560 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2561 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2562 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2563 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2566 //===---------------------------------------------------------------------===//
2567 // SSE2 - Packed Integer Comparison Instructions
2568 //===---------------------------------------------------------------------===//
2570 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2571 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2573 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2575 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2577 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2579 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2581 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2585 let Constraints = "$src1 = $dst" in {
2586 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2587 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2588 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2589 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2590 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2591 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2592 } // Constraints = "$src1 = $dst"
2594 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2595 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2596 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2597 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2598 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2599 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2600 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2601 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2602 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2603 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2604 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2605 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2607 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2608 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2609 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2610 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2611 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2612 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2613 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2614 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2615 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2616 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2617 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2618 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2620 //===---------------------------------------------------------------------===//
2621 // SSE2 - Packed Integer Pack Instructions
2622 //===---------------------------------------------------------------------===//
2624 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2625 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2627 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2629 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2633 let Constraints = "$src1 = $dst" in {
2634 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2635 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2636 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2637 } // Constraints = "$src1 = $dst"
2639 //===---------------------------------------------------------------------===//
2640 // SSE2 - Packed Integer Shuffle Instructions
2641 //===---------------------------------------------------------------------===//
2643 let ExeDomain = SSEPackedInt in {
2644 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2646 def ri : Ii8<0x70, MRMSrcReg,
2647 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2648 !strconcat(OpcodeStr,
2649 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2650 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2652 def mi : Ii8<0x70, MRMSrcMem,
2653 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2654 !strconcat(OpcodeStr,
2655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2656 [(set VR128:$dst, (vt (pshuf_frag:$src2
2657 (bc_frag (memopv2i64 addr:$src1)),
2660 } // ExeDomain = SSEPackedInt
2662 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2663 let AddedComplexity = 5 in
2664 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2667 // SSE2 with ImmT == Imm8 and XS prefix.
2668 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2671 // SSE2 with ImmT == Imm8 and XD prefix.
2672 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2676 let Predicates = [HasSSE2] in {
2677 let AddedComplexity = 5 in
2678 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2680 // SSE2 with ImmT == Imm8 and XS prefix.
2681 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2683 // SSE2 with ImmT == Imm8 and XD prefix.
2684 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2687 //===---------------------------------------------------------------------===//
2688 // SSE2 - Packed Integer Unpack Instructions
2689 //===---------------------------------------------------------------------===//
2691 let ExeDomain = SSEPackedInt in {
2692 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2693 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2694 def rr : PDI<opc, MRMSrcReg,
2695 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2697 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2698 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2699 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2700 def rm : PDI<opc, MRMSrcMem,
2701 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2703 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2704 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2705 [(set VR128:$dst, (unp_frag VR128:$src1,
2706 (bc_frag (memopv2i64
2710 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in {
2711 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2713 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2715 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2718 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2719 /// knew to collapse (bitconvert VT to VT) into its operand.
2720 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2721 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2722 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2724 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2725 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2726 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2727 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2729 (v2i64 (unpckl VR128:$src1,
2730 (memopv2i64 addr:$src2))))]>, VEX_4V;
2732 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2734 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2736 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2739 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2740 /// knew to collapse (bitconvert VT to VT) into its operand.
2741 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2742 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2743 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2745 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2746 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2747 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2748 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2750 (v2i64 (unpckh VR128:$src1,
2751 (memopv2i64 addr:$src2))))]>, VEX_4V;
2754 let Constraints = "$src1 = $dst" in {
2755 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2756 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2757 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2759 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2760 /// knew to collapse (bitconvert VT to VT) into its operand.
2761 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2762 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2763 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2765 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2766 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2767 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2768 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2770 (v2i64 (unpckl VR128:$src1,
2771 (memopv2i64 addr:$src2))))]>;
2773 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2774 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2775 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2777 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2778 /// knew to collapse (bitconvert VT to VT) into its operand.
2779 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2780 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2781 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2783 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2784 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2785 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2786 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2788 (v2i64 (unpckh VR128:$src1,
2789 (memopv2i64 addr:$src2))))]>;
2792 } // ExeDomain = SSEPackedInt
2794 //===---------------------------------------------------------------------===//
2795 // SSE2 - Packed Integer Extract and Insert
2796 //===---------------------------------------------------------------------===//
2798 let ExeDomain = SSEPackedInt in {
2799 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2800 def rri : Ii8<0xC4, MRMSrcReg,
2801 (outs VR128:$dst), (ins VR128:$src1,
2802 GR32:$src2, i32i8imm:$src3),
2804 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2805 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2807 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2808 def rmi : Ii8<0xC4, MRMSrcMem,
2809 (outs VR128:$dst), (ins VR128:$src1,
2810 i16mem:$src2, i32i8imm:$src3),
2812 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2813 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2815 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2820 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in
2821 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2822 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2823 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2824 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2825 imm:$src2))]>, OpSize, VEX;
2826 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2827 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2828 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2829 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2833 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE2] in
2834 defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2836 let Constraints = "$src1 = $dst" in
2837 defm VPINSRW : sse2_pinsrw, TB, OpSize;
2839 } // ExeDomain = SSEPackedInt
2841 //===---------------------------------------------------------------------===//
2842 // SSE2 - Packed Mask Creation
2843 //===---------------------------------------------------------------------===//
2845 let ExeDomain = SSEPackedInt in {
2847 let isAsmParserOnly = 1 in
2848 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2849 "pmovmskb\t{$src, $dst|$dst, $src}",
2850 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2851 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2852 "pmovmskb\t{$src, $dst|$dst, $src}",
2853 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2855 } // ExeDomain = SSEPackedInt
2857 //===---------------------------------------------------------------------===//
2858 // SSE2 - Conditional Store
2859 //===---------------------------------------------------------------------===//
2861 let ExeDomain = SSEPackedInt in {
2863 let isAsmParserOnly = 1 in {
2865 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2866 (ins VR128:$src, VR128:$mask),
2867 "maskmovdqu\t{$mask, $src|$src, $mask}",
2868 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2870 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2871 (ins VR128:$src, VR128:$mask),
2872 "maskmovdqu\t{$mask, $src|$src, $mask}",
2873 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2877 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2878 "maskmovdqu\t{$mask, $src|$src, $mask}",
2879 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2881 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2882 "maskmovdqu\t{$mask, $src|$src, $mask}",
2883 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2885 } // ExeDomain = SSEPackedInt
2887 //===---------------------------------------------------------------------===//
2888 // SSE2 - Move Doubleword
2889 //===---------------------------------------------------------------------===//
2891 // Move Int Doubleword to Packed Double Int
2892 let isAsmParserOnly = 1 in {
2893 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2894 "movd\t{$src, $dst|$dst, $src}",
2896 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2897 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2898 "movd\t{$src, $dst|$dst, $src}",
2900 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2903 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2904 "movd\t{$src, $dst|$dst, $src}",
2906 (v4i32 (scalar_to_vector GR32:$src)))]>;
2907 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2908 "movd\t{$src, $dst|$dst, $src}",
2910 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2913 // Move Int Doubleword to Single Scalar
2914 let isAsmParserOnly = 1 in {
2915 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2916 "movd\t{$src, $dst|$dst, $src}",
2917 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2919 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2920 "movd\t{$src, $dst|$dst, $src}",
2921 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2924 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2925 "movd\t{$src, $dst|$dst, $src}",
2926 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2928 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2929 "movd\t{$src, $dst|$dst, $src}",
2930 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2932 // Move Packed Doubleword Int to Packed Double Int
2933 let isAsmParserOnly = 1 in {
2934 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2935 "movd\t{$src, $dst|$dst, $src}",
2936 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2938 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2939 (ins i32mem:$dst, VR128:$src),
2940 "movd\t{$src, $dst|$dst, $src}",
2941 [(store (i32 (vector_extract (v4i32 VR128:$src),
2942 (iPTR 0))), addr:$dst)]>, VEX;
2944 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2945 "movd\t{$src, $dst|$dst, $src}",
2946 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2948 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2949 "movd\t{$src, $dst|$dst, $src}",
2950 [(store (i32 (vector_extract (v4i32 VR128:$src),
2951 (iPTR 0))), addr:$dst)]>;
2953 // Move Scalar Single to Double Int
2954 let isAsmParserOnly = 1 in {
2955 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2956 "movd\t{$src, $dst|$dst, $src}",
2957 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2958 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2959 "movd\t{$src, $dst|$dst, $src}",
2960 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2962 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2963 "movd\t{$src, $dst|$dst, $src}",
2964 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2965 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2966 "movd\t{$src, $dst|$dst, $src}",
2967 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2969 // movd / movq to XMM register zero-extends
2970 let AddedComplexity = 15, isAsmParserOnly = 1 in {
2971 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2972 "movd\t{$src, $dst|$dst, $src}",
2973 [(set VR128:$dst, (v4i32 (X86vzmovl
2974 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2976 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2977 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2978 [(set VR128:$dst, (v2i64 (X86vzmovl
2979 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2982 let AddedComplexity = 15 in {
2983 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2984 "movd\t{$src, $dst|$dst, $src}",
2985 [(set VR128:$dst, (v4i32 (X86vzmovl
2986 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2987 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2988 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2989 [(set VR128:$dst, (v2i64 (X86vzmovl
2990 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2993 let AddedComplexity = 20 in {
2994 let isAsmParserOnly = 1 in
2995 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2996 "movd\t{$src, $dst|$dst, $src}",
2998 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2999 (loadi32 addr:$src))))))]>,
3001 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3002 "movd\t{$src, $dst|$dst, $src}",
3004 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3005 (loadi32 addr:$src))))))]>;
3007 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3008 (MOVZDI2PDIrm addr:$src)>;
3009 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3010 (MOVZDI2PDIrm addr:$src)>;
3011 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3012 (MOVZDI2PDIrm addr:$src)>;
3015 //===---------------------------------------------------------------------===//
3016 // SSE2 - Move Quadword
3017 //===---------------------------------------------------------------------===//
3019 // Move Quadword Int to Packed Quadword Int
3020 let isAsmParserOnly = 1 in
3021 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3022 "vmovq\t{$src, $dst|$dst, $src}",
3024 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3025 VEX, Requires<[HasAVX, HasSSE2]>;
3026 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3027 "movq\t{$src, $dst|$dst, $src}",
3029 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3030 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3032 // Move Packed Quadword Int to Quadword Int
3033 let isAsmParserOnly = 1 in
3034 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3035 "movq\t{$src, $dst|$dst, $src}",
3036 [(store (i64 (vector_extract (v2i64 VR128:$src),
3037 (iPTR 0))), addr:$dst)]>, VEX;
3038 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3039 "movq\t{$src, $dst|$dst, $src}",
3040 [(store (i64 (vector_extract (v2i64 VR128:$src),
3041 (iPTR 0))), addr:$dst)]>;
3043 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3044 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3046 // Store / copy lower 64-bits of a XMM register.
3047 let isAsmParserOnly = 1 in
3048 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3049 "movq\t{$src, $dst|$dst, $src}",
3050 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3051 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3052 "movq\t{$src, $dst|$dst, $src}",
3053 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3055 let AddedComplexity = 20, isAsmParserOnly = 1 in
3056 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3057 "vmovq\t{$src, $dst|$dst, $src}",
3059 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3060 (loadi64 addr:$src))))))]>,
3061 XS, VEX, Requires<[HasAVX, HasSSE2]>;
3063 let AddedComplexity = 20 in {
3064 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3065 "movq\t{$src, $dst|$dst, $src}",
3067 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3068 (loadi64 addr:$src))))))]>,
3069 XS, Requires<[HasSSE2]>;
3071 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3072 (MOVZQI2PQIrm addr:$src)>;
3073 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3074 (MOVZQI2PQIrm addr:$src)>;
3075 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3078 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3079 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3080 let isAsmParserOnly = 1, AddedComplexity = 15 in
3081 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3082 "vmovq\t{$src, $dst|$dst, $src}",
3083 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3084 XS, VEX, Requires<[HasAVX, HasSSE2]>;
3085 let AddedComplexity = 15 in
3086 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3087 "movq\t{$src, $dst|$dst, $src}",
3088 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3089 XS, Requires<[HasSSE2]>;
3091 let AddedComplexity = 20, isAsmParserOnly = 1 in
3092 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3093 "vmovq\t{$src, $dst|$dst, $src}",
3094 [(set VR128:$dst, (v2i64 (X86vzmovl
3095 (loadv2i64 addr:$src))))]>,
3096 XS, VEX, Requires<[HasAVX, HasSSE2]>;
3097 let AddedComplexity = 20 in {
3098 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3099 "movq\t{$src, $dst|$dst, $src}",
3100 [(set VR128:$dst, (v2i64 (X86vzmovl
3101 (loadv2i64 addr:$src))))]>,
3102 XS, Requires<[HasSSE2]>;
3104 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3105 (MOVZPQILo2PQIrm addr:$src)>;
3108 // Instructions to match in the assembler
3109 let isAsmParserOnly = 1 in {
3110 // This instructions is in fact an alias to movd with 64 bit dst
3111 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3112 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3113 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3114 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3117 // Instructions for the disassembler
3118 // xr = XMM register
3121 let isAsmParserOnly = 1 in
3122 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3123 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3124 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3125 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3127 //===---------------------------------------------------------------------===//
3128 // SSE2 - Misc Instructions
3129 //===---------------------------------------------------------------------===//
3132 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3133 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3134 TB, Requires<[HasSSE2]>;
3136 // Load, store, and memory fence
3137 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3138 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3139 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3140 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3142 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3143 // was introduced with SSE2, it's backward compatible.
3144 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3146 //TODO: custom lower this so as to never even generate the noop
3147 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
3149 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
3150 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
3151 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
3154 // Alias instructions that map zero vector to pxor / xorp* for sse.
3155 // We set canFoldAsLoad because this can be converted to a constant-pool
3156 // load of an all-ones value if folding it would be beneficial.
3157 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3158 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3159 // FIXME: Change encoding to pseudo.
3160 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3161 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3163 //===---------------------------------------------------------------------===//
3164 // SSE3 - Conversion Instructions
3165 //===---------------------------------------------------------------------===//
3167 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
3168 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3169 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3170 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3171 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3172 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3173 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3176 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3177 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3178 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3179 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3180 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3181 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3182 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3183 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3185 //===---------------------------------------------------------------------===//
3186 // SSE3 - Move Instructions
3187 //===---------------------------------------------------------------------===//
3189 // Replicate Single FP
3190 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3191 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3192 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3193 [(set VR128:$dst, (v4f32 (rep_frag
3194 VR128:$src, (undef))))]>;
3195 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3196 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3197 [(set VR128:$dst, (rep_frag
3198 (memopv4f32 addr:$src), (undef)))]>;
3201 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
3202 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3203 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3205 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3206 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3208 // Replicate Double FP
3209 multiclass sse3_replicate_dfp<string OpcodeStr> {
3210 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3211 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3212 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3213 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3214 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3216 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3220 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
3221 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3222 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3224 // Move Unaligned Integer
3225 let isAsmParserOnly = 1 in
3226 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3227 "vlddqu\t{$src, $dst|$dst, $src}",
3228 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3229 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3230 "lddqu\t{$src, $dst|$dst, $src}",
3231 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3233 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3235 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3237 // Several Move patterns
3238 let AddedComplexity = 5 in {
3239 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3240 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3241 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3242 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3243 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3244 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3245 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3246 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3249 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3250 let AddedComplexity = 15 in
3251 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3252 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3253 let AddedComplexity = 20 in
3254 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3255 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3257 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3258 let AddedComplexity = 15 in
3259 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3260 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3261 let AddedComplexity = 20 in
3262 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3263 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3265 //===---------------------------------------------------------------------===//
3266 // SSE3 - Arithmetic
3267 //===---------------------------------------------------------------------===//
3269 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, bit Is2Addr = 1> {
3270 def rr : I<0xD0, MRMSrcReg,
3271 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3273 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3274 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3275 [(set VR128:$dst, (Int VR128:$src1,
3277 def rm : I<0xD0, MRMSrcMem,
3278 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3280 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3282 [(set VR128:$dst, (Int VR128:$src1,
3283 (memop addr:$src2)))]>;
3287 let isAsmParserOnly = 1, Predicates = [HasSSE3, HasAVX],
3288 ExeDomain = SSEPackedDouble in {
3289 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", 0>, XD,
3291 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", 0>, OpSize,
3294 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3295 ExeDomain = SSEPackedDouble in {
3296 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps">, XD;
3297 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd">, TB, OpSize;
3300 //===---------------------------------------------------------------------===//
3301 // SSE3 Instructions
3302 //===---------------------------------------------------------------------===//
3305 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3306 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3308 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3309 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3310 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
3311 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3312 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3314 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3315 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3316 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
3317 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3318 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3320 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3321 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3322 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
3323 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3324 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3326 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3327 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3328 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
3330 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
3331 def VHADDPSrr : S3D_Intrr<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
3332 def VHADDPSrm : S3D_Intrm<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
3333 def VHADDPDrr : S3_Intrr <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
3334 def VHADDPDrm : S3_Intrm <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
3335 def VHSUBPSrr : S3D_Intrr<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
3336 def VHSUBPSrm : S3D_Intrm<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
3337 def VHSUBPDrr : S3_Intrr <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
3338 def VHSUBPDrm : S3_Intrm <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
3341 let Constraints = "$src1 = $dst" in {
3342 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
3343 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
3344 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
3345 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
3346 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
3347 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
3348 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
3349 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
3352 //===---------------------------------------------------------------------===//
3353 // SSSE3 - Packed Absolute Instructions
3354 //===---------------------------------------------------------------------===//
3356 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3357 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3358 PatFrag mem_frag64, PatFrag mem_frag128,
3359 Intrinsic IntId64, Intrinsic IntId128> {
3360 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3362 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3364 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3365 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3367 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3369 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3371 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3372 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3375 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3377 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3380 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3383 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
3384 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3385 int_x86_ssse3_pabs_b,
3386 int_x86_ssse3_pabs_b_128>, VEX;
3387 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3388 int_x86_ssse3_pabs_w,
3389 int_x86_ssse3_pabs_w_128>, VEX;
3390 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3391 int_x86_ssse3_pabs_d,
3392 int_x86_ssse3_pabs_d_128>, VEX;
3395 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3396 int_x86_ssse3_pabs_b,
3397 int_x86_ssse3_pabs_b_128>;
3398 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3399 int_x86_ssse3_pabs_w,
3400 int_x86_ssse3_pabs_w_128>;
3401 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3402 int_x86_ssse3_pabs_d,
3403 int_x86_ssse3_pabs_d_128>;
3405 //===---------------------------------------------------------------------===//
3406 // SSSE3 - Packed Binary Operator Instructions
3407 //===---------------------------------------------------------------------===//
3409 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3410 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3411 PatFrag mem_frag64, PatFrag mem_frag128,
3412 Intrinsic IntId64, Intrinsic IntId128,
3414 let isCommutable = 1 in
3415 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3416 (ins VR64:$src1, VR64:$src2),
3418 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3419 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3420 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3421 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3422 (ins VR64:$src1, i64mem:$src2),
3424 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3425 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3427 (IntId64 VR64:$src1,
3428 (bitconvert (memopv8i8 addr:$src2))))]>;
3430 let isCommutable = 1 in
3431 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3432 (ins VR128:$src1, VR128:$src2),
3434 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3435 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3436 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3438 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3439 (ins VR128:$src1, i128mem:$src2),
3441 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3442 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3444 (IntId128 VR128:$src1,
3445 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3448 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in {
3449 let isCommutable = 0 in {
3450 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3451 int_x86_ssse3_phadd_w,
3452 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3453 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3454 int_x86_ssse3_phadd_d,
3455 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3456 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3457 int_x86_ssse3_phadd_sw,
3458 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3459 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3460 int_x86_ssse3_phsub_w,
3461 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3462 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3463 int_x86_ssse3_phsub_d,
3464 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3465 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3466 int_x86_ssse3_phsub_sw,
3467 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3468 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3469 int_x86_ssse3_pmadd_ub_sw,
3470 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3471 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3472 int_x86_ssse3_pshuf_b,
3473 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3474 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3475 int_x86_ssse3_psign_b,
3476 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3477 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3478 int_x86_ssse3_psign_w,
3479 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3480 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3481 int_x86_ssse3_psign_d,
3482 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3484 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3485 int_x86_ssse3_pmul_hr_sw,
3486 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3489 // None of these have i8 immediate fields.
3490 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3491 let isCommutable = 0 in {
3492 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3493 int_x86_ssse3_phadd_w,
3494 int_x86_ssse3_phadd_w_128>;
3495 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3496 int_x86_ssse3_phadd_d,
3497 int_x86_ssse3_phadd_d_128>;
3498 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3499 int_x86_ssse3_phadd_sw,
3500 int_x86_ssse3_phadd_sw_128>;
3501 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3502 int_x86_ssse3_phsub_w,
3503 int_x86_ssse3_phsub_w_128>;
3504 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3505 int_x86_ssse3_phsub_d,
3506 int_x86_ssse3_phsub_d_128>;
3507 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3508 int_x86_ssse3_phsub_sw,
3509 int_x86_ssse3_phsub_sw_128>;
3510 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3511 int_x86_ssse3_pmadd_ub_sw,
3512 int_x86_ssse3_pmadd_ub_sw_128>;
3513 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3514 int_x86_ssse3_pshuf_b,
3515 int_x86_ssse3_pshuf_b_128>;
3516 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3517 int_x86_ssse3_psign_b,
3518 int_x86_ssse3_psign_b_128>;
3519 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3520 int_x86_ssse3_psign_w,
3521 int_x86_ssse3_psign_w_128>;
3522 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3523 int_x86_ssse3_psign_d,
3524 int_x86_ssse3_psign_d_128>;
3526 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3527 int_x86_ssse3_pmul_hr_sw,
3528 int_x86_ssse3_pmul_hr_sw_128>;
3531 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3532 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3533 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3534 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3536 //===---------------------------------------------------------------------===//
3537 // SSSE3 - Packed Align Instruction Patterns
3538 //===---------------------------------------------------------------------===//
3540 multiclass sse3_palign<string asm, bit Is2Addr = 1> {
3541 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3542 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3544 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3546 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3548 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3549 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3551 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3553 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3556 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3557 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3559 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3561 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3563 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3564 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3566 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3568 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3572 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE3] in
3573 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3574 let Constraints = "$src1 = $dst" in
3575 defm PALIGN : sse3_palign<"palignr">;
3577 let AddedComplexity = 5 in {
3579 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3580 (PALIGNR64rr VR64:$src2, VR64:$src1,
3581 (SHUFFLE_get_palign_imm VR64:$src3))>,
3582 Requires<[HasSSSE3]>;
3583 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3584 (PALIGNR64rr VR64:$src2, VR64:$src1,
3585 (SHUFFLE_get_palign_imm VR64:$src3))>,
3586 Requires<[HasSSSE3]>;
3587 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3588 (PALIGNR64rr VR64:$src2, VR64:$src1,
3589 (SHUFFLE_get_palign_imm VR64:$src3))>,
3590 Requires<[HasSSSE3]>;
3591 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3592 (PALIGNR64rr VR64:$src2, VR64:$src1,
3593 (SHUFFLE_get_palign_imm VR64:$src3))>,
3594 Requires<[HasSSSE3]>;
3596 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3597 (PALIGNR128rr VR128:$src2, VR128:$src1,
3598 (SHUFFLE_get_palign_imm VR128:$src3))>,
3599 Requires<[HasSSSE3]>;
3600 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3601 (PALIGNR128rr VR128:$src2, VR128:$src1,
3602 (SHUFFLE_get_palign_imm VR128:$src3))>,
3603 Requires<[HasSSSE3]>;
3604 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3605 (PALIGNR128rr VR128:$src2, VR128:$src1,
3606 (SHUFFLE_get_palign_imm VR128:$src3))>,
3607 Requires<[HasSSSE3]>;
3608 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3609 (PALIGNR128rr VR128:$src2, VR128:$src1,
3610 (SHUFFLE_get_palign_imm VR128:$src3))>,
3611 Requires<[HasSSSE3]>;
3614 //===---------------------------------------------------------------------===//
3615 // SSSE3 Misc Instructions
3616 //===---------------------------------------------------------------------===//
3618 // Thread synchronization
3619 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3620 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3621 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3622 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3624 //===---------------------------------------------------------------------===//
3625 // Non-Instruction Patterns
3626 //===---------------------------------------------------------------------===//
3628 // extload f32 -> f64. This matches load+fextend because we have a hack in
3629 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3631 // Since these loads aren't folded into the fextend, we have to match it
3633 let Predicates = [HasSSE2] in
3634 def : Pat<(fextend (loadf32 addr:$src)),
3635 (CVTSS2SDrm addr:$src)>;
3638 let Predicates = [HasSSE2] in {
3639 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3640 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3641 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3642 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3643 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3644 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3645 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3646 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3647 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3648 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3649 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3650 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3651 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3652 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3653 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3654 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3655 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3656 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3657 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3658 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3659 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3660 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3661 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3662 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3663 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3664 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3665 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3666 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3667 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3668 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3671 // Move scalar to XMM zero-extended
3672 // movd to XMM register zero-extends
3673 let AddedComplexity = 15 in {
3674 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3675 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3676 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3677 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3678 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3679 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3680 (MOVSSrr (v4f32 (V_SET0PS)),
3681 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3682 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3683 (MOVSSrr (v4i32 (V_SET0PI)),
3684 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3687 // Splat v2f64 / v2i64
3688 let AddedComplexity = 10 in {
3689 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3690 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3691 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3692 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3693 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3694 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3695 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3696 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3699 // Special unary SHUFPSrri case.
3700 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3701 (SHUFPSrri VR128:$src1, VR128:$src1,
3702 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3703 let AddedComplexity = 5 in
3704 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3705 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3706 Requires<[HasSSE2]>;
3707 // Special unary SHUFPDrri case.
3708 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3709 (SHUFPDrri VR128:$src1, VR128:$src1,
3710 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3711 Requires<[HasSSE2]>;
3712 // Special unary SHUFPDrri case.
3713 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3714 (SHUFPDrri VR128:$src1, VR128:$src1,
3715 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3716 Requires<[HasSSE2]>;
3717 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3718 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3719 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3720 Requires<[HasSSE2]>;
3722 // Special binary v4i32 shuffle cases with SHUFPS.
3723 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3724 (SHUFPSrri VR128:$src1, VR128:$src2,
3725 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3726 Requires<[HasSSE2]>;
3727 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3728 (SHUFPSrmi VR128:$src1, addr:$src2,
3729 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3730 Requires<[HasSSE2]>;
3731 // Special binary v2i64 shuffle cases using SHUFPDrri.
3732 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3733 (SHUFPDrri VR128:$src1, VR128:$src2,
3734 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3735 Requires<[HasSSE2]>;
3737 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3738 let AddedComplexity = 15 in {
3739 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3740 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3741 Requires<[OptForSpeed, HasSSE2]>;
3742 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3743 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3744 Requires<[OptForSpeed, HasSSE2]>;
3746 let AddedComplexity = 10 in {
3747 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3748 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3749 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3750 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3751 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3752 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3753 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3754 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3757 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3758 let AddedComplexity = 15 in {
3759 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3760 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3761 Requires<[OptForSpeed, HasSSE2]>;
3762 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3763 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3764 Requires<[OptForSpeed, HasSSE2]>;
3766 let AddedComplexity = 10 in {
3767 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3768 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3769 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3770 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3771 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3772 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3773 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3774 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3777 let AddedComplexity = 20 in {
3778 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3779 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3780 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3782 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3783 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3784 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3786 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3787 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3788 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3789 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3790 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3793 let AddedComplexity = 20 in {
3794 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3795 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3796 (MOVLPSrm VR128:$src1, addr:$src2)>;
3797 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3798 (MOVLPDrm VR128:$src1, addr:$src2)>;
3799 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3800 (MOVLPSrm VR128:$src1, addr:$src2)>;
3801 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3802 (MOVLPDrm VR128:$src1, addr:$src2)>;
3805 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3806 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3807 (MOVLPSmr addr:$src1, VR128:$src2)>;
3808 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3809 (MOVLPDmr addr:$src1, VR128:$src2)>;
3810 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3812 (MOVLPSmr addr:$src1, VR128:$src2)>;
3813 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3814 (MOVLPDmr addr:$src1, VR128:$src2)>;
3816 let AddedComplexity = 15 in {
3817 // Setting the lowest element in the vector.
3818 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3819 (MOVSSrr (v4i32 VR128:$src1),
3820 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3821 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3822 (MOVSDrr (v2i64 VR128:$src1),
3823 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3825 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3826 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3827 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3828 Requires<[HasSSE2]>;
3829 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3830 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3831 Requires<[HasSSE2]>;
3834 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3835 // fall back to this for SSE1)
3836 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3837 (SHUFPSrri VR128:$src2, VR128:$src1,
3838 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3840 // Set lowest element and zero upper elements.
3841 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3842 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3844 // Some special case pandn patterns.
3845 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3847 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3848 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3850 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3851 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3853 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3855 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3856 (memop addr:$src2))),
3857 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3858 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3859 (memop addr:$src2))),
3860 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3861 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3862 (memop addr:$src2))),
3863 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3865 // vector -> vector casts
3866 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3867 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3868 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3869 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3870 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3871 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3872 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3873 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3875 // Use movaps / movups for SSE integer load / store (one byte shorter).
3876 def : Pat<(alignedloadv4i32 addr:$src),
3877 (MOVAPSrm addr:$src)>;
3878 def : Pat<(loadv4i32 addr:$src),
3879 (MOVUPSrm addr:$src)>;
3880 def : Pat<(alignedloadv2i64 addr:$src),
3881 (MOVAPSrm addr:$src)>;
3882 def : Pat<(loadv2i64 addr:$src),
3883 (MOVUPSrm addr:$src)>;
3885 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3886 (MOVAPSmr addr:$dst, VR128:$src)>;
3887 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3888 (MOVAPSmr addr:$dst, VR128:$src)>;
3889 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3890 (MOVAPSmr addr:$dst, VR128:$src)>;
3891 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3892 (MOVAPSmr addr:$dst, VR128:$src)>;
3893 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3894 (MOVUPSmr addr:$dst, VR128:$src)>;
3895 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3896 (MOVUPSmr addr:$dst, VR128:$src)>;
3897 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3898 (MOVUPSmr addr:$dst, VR128:$src)>;
3899 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3900 (MOVUPSmr addr:$dst, VR128:$src)>;
3902 //===----------------------------------------------------------------------===//
3903 // SSE4.1 - Misc Instructions
3904 //===----------------------------------------------------------------------===//
3906 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3909 Intrinsic V2F64Int> {
3910 // Intrinsic operation, reg.
3911 // Vector intrinsic operation, reg
3912 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3913 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3914 !strconcat(OpcodeStr,
3915 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3916 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3919 // Vector intrinsic operation, mem
3920 def PSm_Int : Ii8<opcps, MRMSrcMem,
3921 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3922 !strconcat(OpcodeStr,
3923 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3925 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3927 Requires<[HasSSE41]>;
3929 // Vector intrinsic operation, reg
3930 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3931 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3932 !strconcat(OpcodeStr,
3933 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3934 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3937 // Vector intrinsic operation, mem
3938 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3939 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3940 !strconcat(OpcodeStr,
3941 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3943 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3947 multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
3949 // Intrinsic operation, reg.
3950 // Vector intrinsic operation, reg
3951 def PSr : SS4AIi8<opcps, MRMSrcReg,
3952 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3953 !strconcat(OpcodeStr,
3954 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3957 // Vector intrinsic operation, mem
3958 def PSm : Ii8<opcps, MRMSrcMem,
3959 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3960 !strconcat(OpcodeStr,
3961 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3962 []>, TA, OpSize, Requires<[HasSSE41]>;
3964 // Vector intrinsic operation, reg
3965 def PDr : SS4AIi8<opcpd, MRMSrcReg,
3966 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3967 !strconcat(OpcodeStr,
3968 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3971 // Vector intrinsic operation, mem
3972 def PDm : SS4AIi8<opcpd, MRMSrcMem,
3973 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3974 !strconcat(OpcodeStr,
3975 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3979 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3982 Intrinsic F64Int, bit Is2Addr = 1> {
3983 // Intrinsic operation, reg.
3984 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3985 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3987 !strconcat(OpcodeStr,
3988 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3989 !strconcat(OpcodeStr,
3990 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3991 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3994 // Intrinsic operation, mem.
3995 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3996 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3998 !strconcat(OpcodeStr,
3999 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4000 !strconcat(OpcodeStr,
4001 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4003 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4006 // Intrinsic operation, reg.
4007 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
4008 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4010 !strconcat(OpcodeStr,
4011 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4012 !strconcat(OpcodeStr,
4013 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4014 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4017 // Intrinsic operation, mem.
4018 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
4019 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4021 !strconcat(OpcodeStr,
4022 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4023 !strconcat(OpcodeStr,
4024 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4026 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4030 multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
4032 // Intrinsic operation, reg.
4033 def SSr : SS4AIi8<opcss, MRMSrcReg,
4034 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4035 !strconcat(OpcodeStr,
4036 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4039 // Intrinsic operation, mem.
4040 def SSm : SS4AIi8<opcss, MRMSrcMem,
4041 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4042 !strconcat(OpcodeStr,
4043 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4046 // Intrinsic operation, reg.
4047 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4048 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4049 !strconcat(OpcodeStr,
4050 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4053 // Intrinsic operation, mem.
4054 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4055 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4056 !strconcat(OpcodeStr,
4057 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4061 // FP round - roundss, roundps, roundsd, roundpd
4062 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
4064 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
4065 int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
4067 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4068 int_x86_sse41_round_ss, int_x86_sse41_round_sd,
4070 // Instructions for the assembler
4071 defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
4072 defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
4075 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
4076 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4077 let Constraints = "$src1 = $dst" in
4078 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4079 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4081 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4082 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4083 Intrinsic IntId128> {
4084 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4086 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4087 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4088 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4090 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4093 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4096 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
4097 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4098 int_x86_sse41_phminposuw>, VEX;
4099 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4100 int_x86_sse41_phminposuw>;
4102 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4103 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4104 Intrinsic IntId128, bit Is2Addr = 1> {
4105 let isCommutable = 1 in
4106 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4107 (ins VR128:$src1, VR128:$src2),
4109 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4110 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4111 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4112 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4113 (ins VR128:$src1, i128mem:$src2),
4115 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4116 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4118 (IntId128 VR128:$src1,
4119 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4122 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
4123 let isCommutable = 0 in
4124 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4126 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4128 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4130 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4132 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4134 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4136 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4138 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4140 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4142 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4144 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4148 let Constraints = "$src1 = $dst" in {
4149 let isCommutable = 0 in
4150 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4151 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4152 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4153 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4154 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4155 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4156 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4157 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4158 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4159 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4160 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4163 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4164 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4165 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4166 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4168 /// SS48I_binop_rm - Simple SSE41 binary operator.
4169 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4170 ValueType OpVT, bit Is2Addr = 1> {
4171 let isCommutable = 1 in
4172 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4173 (ins VR128:$src1, VR128:$src2),
4175 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4176 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4177 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4179 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4180 (ins VR128:$src1, i128mem:$src2),
4182 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4184 [(set VR128:$dst, (OpNode VR128:$src1,
4185 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4189 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in
4190 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4191 let Constraints = "$src1 = $dst" in
4192 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4194 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4195 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4196 Intrinsic IntId128, bit Is2Addr = 1> {
4197 let isCommutable = 1 in
4198 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4199 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4201 !strconcat(OpcodeStr,
4202 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4203 !strconcat(OpcodeStr,
4204 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4206 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
4208 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4209 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
4211 !strconcat(OpcodeStr,
4212 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4213 !strconcat(OpcodeStr,
4214 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4216 (IntId128 VR128:$src1,
4217 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
4221 let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE41] in {
4222 let isCommutable = 0 in {
4223 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4225 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4227 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4229 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4232 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4234 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4238 let Constraints = "$src1 = $dst" in {
4239 let isCommutable = 0 in {
4240 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;
4241 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd>;
4242 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw>;
4243 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw>;
4245 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps>;
4246 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
4249 /// SS41I_ternary_int - SSE 4.1 ternary operator
4250 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4251 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4252 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4253 (ins VR128:$src1, VR128:$src2),
4254 !strconcat(OpcodeStr,
4255 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4256 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4259 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4260 (ins VR128:$src1, i128mem:$src2),
4261 !strconcat(OpcodeStr,
4262 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4265 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4269 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4270 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4271 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4274 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4275 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4276 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4277 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4279 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4280 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4282 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4286 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4287 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4288 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4289 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4290 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4291 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4293 // Common patterns involving scalar load.
4294 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4295 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4296 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4297 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4299 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4300 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4301 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4302 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4304 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4305 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4306 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4307 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4309 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4310 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4311 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4312 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4314 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4315 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4316 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4317 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4319 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4320 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4321 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4322 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4325 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4326 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4327 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4328 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4330 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4331 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4333 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4337 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4338 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4339 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4340 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4342 // Common patterns involving scalar load
4343 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4344 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4345 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4346 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4348 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4349 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4350 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4351 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4354 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4355 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4356 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4357 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4359 // Expecting a i16 load any extended to i32 value.
4360 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4361 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4362 [(set VR128:$dst, (IntId (bitconvert
4363 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4367 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4368 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4370 // Common patterns involving scalar load
4371 def : Pat<(int_x86_sse41_pmovsxbq
4372 (bitconvert (v4i32 (X86vzmovl
4373 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4374 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4376 def : Pat<(int_x86_sse41_pmovzxbq
4377 (bitconvert (v4i32 (X86vzmovl
4378 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4379 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4382 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4383 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4384 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4385 (ins VR128:$src1, i32i8imm:$src2),
4386 !strconcat(OpcodeStr,
4387 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4388 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4390 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4391 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4392 !strconcat(OpcodeStr,
4393 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4396 // There's an AssertZext in the way of writing the store pattern
4397 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4400 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4403 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4404 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4405 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4406 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4407 !strconcat(OpcodeStr,
4408 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4411 // There's an AssertZext in the way of writing the store pattern
4412 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4415 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4418 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4419 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4420 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4421 (ins VR128:$src1, i32i8imm:$src2),
4422 !strconcat(OpcodeStr,
4423 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4425 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4426 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4427 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4428 !strconcat(OpcodeStr,
4429 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4430 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4431 addr:$dst)]>, OpSize;
4434 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4437 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4439 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4440 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4441 (ins VR128:$src1, i32i8imm:$src2),
4442 !strconcat(OpcodeStr,
4443 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4445 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4447 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4448 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4449 !strconcat(OpcodeStr,
4450 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4451 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4452 addr:$dst)]>, OpSize;
4455 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4457 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4458 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4461 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4462 Requires<[HasSSE41]>;
4464 let Constraints = "$src1 = $dst" in {
4465 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
4466 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4467 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4468 !strconcat(OpcodeStr,
4469 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4471 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4472 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4473 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4474 !strconcat(OpcodeStr,
4475 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4477 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4478 imm:$src3))]>, OpSize;
4482 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4484 let Constraints = "$src1 = $dst" in {
4485 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
4486 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4487 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4488 !strconcat(OpcodeStr,
4489 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4491 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4493 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4494 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4495 !strconcat(OpcodeStr,
4496 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4498 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4499 imm:$src3)))]>, OpSize;
4503 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4505 // insertps has a few different modes, there's the first two here below which
4506 // are optimized inserts that won't zero arbitrary elements in the destination
4507 // vector. The next one matches the intrinsic and could zero arbitrary elements
4508 // in the target vector.
4509 let Constraints = "$src1 = $dst" in {
4510 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
4511 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4512 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4513 !strconcat(OpcodeStr,
4514 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4516 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4518 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4519 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4520 !strconcat(OpcodeStr,
4521 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4523 (X86insrtps VR128:$src1,
4524 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4525 imm:$src3))]>, OpSize;
4529 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4531 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4532 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
4534 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4535 // the intel intrinsic that corresponds to this.
4536 let Defs = [EFLAGS] in {
4537 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4538 "ptest \t{$src2, $src1|$src1, $src2}",
4539 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4541 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4542 "ptest \t{$src2, $src1|$src1, $src2}",
4543 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4547 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4548 "movntdqa\t{$src, $dst|$dst, $src}",
4549 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4553 //===----------------------------------------------------------------------===//
4554 // SSE4.2 Instructions
4555 //===----------------------------------------------------------------------===//
4557 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4558 let Constraints = "$src1 = $dst" in {
4559 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4560 Intrinsic IntId128, bit Commutable = 0> {
4561 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4562 (ins VR128:$src1, VR128:$src2),
4563 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4564 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4566 let isCommutable = Commutable;
4568 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4569 (ins VR128:$src1, i128mem:$src2),
4570 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4572 (IntId128 VR128:$src1,
4573 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4577 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4579 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4580 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4581 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4582 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4584 // crc intrinsic instruction
4585 // This set of instructions are only rm, the only difference is the size
4587 let Constraints = "$src1 = $dst" in {
4588 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4589 (ins GR32:$src1, i8mem:$src2),
4590 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4592 (int_x86_sse42_crc32_8 GR32:$src1,
4593 (load addr:$src2)))]>;
4594 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4595 (ins GR32:$src1, GR8:$src2),
4596 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4598 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
4599 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4600 (ins GR32:$src1, i16mem:$src2),
4601 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4603 (int_x86_sse42_crc32_16 GR32:$src1,
4604 (load addr:$src2)))]>,
4606 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4607 (ins GR32:$src1, GR16:$src2),
4608 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4610 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
4612 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4613 (ins GR32:$src1, i32mem:$src2),
4614 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4616 (int_x86_sse42_crc32_32 GR32:$src1,
4617 (load addr:$src2)))]>;
4618 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4619 (ins GR32:$src1, GR32:$src2),
4620 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4622 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
4623 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4624 (ins GR64:$src1, i8mem:$src2),
4625 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4627 (int_x86_sse42_crc64_8 GR64:$src1,
4628 (load addr:$src2)))]>,
4630 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4631 (ins GR64:$src1, GR8:$src2),
4632 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4634 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
4636 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
4637 (ins GR64:$src1, i64mem:$src2),
4638 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4640 (int_x86_sse42_crc64_64 GR64:$src1,
4641 (load addr:$src2)))]>,
4643 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
4644 (ins GR64:$src1, GR64:$src2),
4645 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4647 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
4651 // String/text processing instructions.
4652 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4653 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4654 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4655 "#PCMPISTRM128rr PSEUDO!",
4656 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4657 imm:$src3))]>, OpSize;
4658 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4659 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4660 "#PCMPISTRM128rm PSEUDO!",
4661 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
4662 imm:$src3))]>, OpSize;
4665 let Defs = [XMM0, EFLAGS] in {
4666 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4667 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4668 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4669 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4670 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4671 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4674 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4675 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4676 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4677 "#PCMPESTRM128rr PSEUDO!",
4679 (int_x86_sse42_pcmpestrm128
4680 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
4682 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4683 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4684 "#PCMPESTRM128rm PSEUDO!",
4685 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4686 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
4690 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4691 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4692 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4693 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4694 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4695 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4696 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4699 let Defs = [ECX, EFLAGS] in {
4700 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
4701 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4702 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4703 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4704 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4705 (implicit EFLAGS)]>, OpSize;
4706 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4707 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4708 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
4709 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4710 (implicit EFLAGS)]>, OpSize;
4714 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4715 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4716 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4717 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4718 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4719 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4721 let Defs = [ECX, EFLAGS] in {
4722 let Uses = [EAX, EDX] in {
4723 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
4724 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4725 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4726 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4727 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4728 (implicit EFLAGS)]>, OpSize;
4729 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4730 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4731 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4733 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4734 (implicit EFLAGS)]>, OpSize;
4739 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4740 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4741 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4742 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4743 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4744 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4746 //===----------------------------------------------------------------------===//
4747 // AES-NI Instructions
4748 //===----------------------------------------------------------------------===//
4750 let Constraints = "$src1 = $dst" in {
4751 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4752 Intrinsic IntId128, bit Commutable = 0> {
4753 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4754 (ins VR128:$src1, VR128:$src2),
4755 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4756 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4758 let isCommutable = Commutable;
4760 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4761 (ins VR128:$src1, i128mem:$src2),
4762 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4764 (IntId128 VR128:$src1,
4765 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4769 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4770 int_x86_aesni_aesenc>;
4771 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4772 int_x86_aesni_aesenclast>;
4773 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4774 int_x86_aesni_aesdec>;
4775 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4776 int_x86_aesni_aesdeclast>;
4778 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4779 (AESENCrr VR128:$src1, VR128:$src2)>;
4780 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4781 (AESENCrm VR128:$src1, addr:$src2)>;
4782 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4783 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4784 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4785 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4786 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4787 (AESDECrr VR128:$src1, VR128:$src2)>;
4788 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4789 (AESDECrm VR128:$src1, addr:$src2)>;
4790 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4791 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4792 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4793 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4795 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4797 "aesimc\t{$src1, $dst|$dst, $src1}",
4799 (int_x86_aesni_aesimc VR128:$src1))]>,
4802 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4803 (ins i128mem:$src1),
4804 "aesimc\t{$src1, $dst|$dst, $src1}",
4806 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4809 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4810 (ins VR128:$src1, i8imm:$src2),
4811 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4813 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4815 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4816 (ins i128mem:$src1, i8imm:$src2),
4817 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4819 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),