1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE scalar FP Instructions
19 //===----------------------------------------------------------------------===//
21 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
22 // instruction selection into a branch sequence.
23 let Uses = [EFLAGS], usesCustomInserter = 1 in {
24 def CMOV_FR32 : I<0, Pseudo,
25 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
27 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
29 def CMOV_FR64 : I<0, Pseudo,
30 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
32 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
34 def CMOV_V4F32 : I<0, Pseudo,
35 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
36 "#CMOV_V4F32 PSEUDO!",
38 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
40 def CMOV_V2F64 : I<0, Pseudo,
41 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
42 "#CMOV_V2F64 PSEUDO!",
44 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
46 def CMOV_V2I64 : I<0, Pseudo,
47 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
48 "#CMOV_V2I64 PSEUDO!",
50 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
54 //===----------------------------------------------------------------------===//
55 // SSE 1 & 2 Instructions Classes
56 //===----------------------------------------------------------------------===//
58 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
59 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 RegisterClass RC, X86MemOperand x86memop,
62 let isCommutable = 1 in {
63 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
65 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
66 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
67 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
69 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
71 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
72 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
73 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
76 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
77 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
78 string asm, string SSEVer, string FPSizeStr,
79 Operand memopr, ComplexPattern mem_cpat,
81 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
83 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
84 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
85 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
86 !strconcat(SSEVer, !strconcat("_",
87 !strconcat(OpcodeStr, FPSizeStr))))
88 RC:$src1, RC:$src2))]>;
89 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
91 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
92 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
93 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
94 !strconcat(SSEVer, !strconcat("_",
95 !strconcat(OpcodeStr, FPSizeStr))))
96 RC:$src1, mem_cpat:$src2))]>;
99 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
100 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
101 RegisterClass RC, ValueType vt,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 let isCommutable = 1 in
105 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
109 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
111 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
118 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
119 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
120 string OpcodeStr, X86MemOperand x86memop,
121 list<dag> pat_rr, list<dag> pat_rm,
123 let isCommutable = 1 in
124 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
129 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
131 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
132 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
136 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
137 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
138 string asm, string SSEVer, string FPSizeStr,
139 X86MemOperand x86memop, PatFrag mem_frag,
140 Domain d, bit Is2Addr = 1> {
141 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
143 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
144 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
145 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
146 !strconcat(SSEVer, !strconcat("_",
147 !strconcat(OpcodeStr, FPSizeStr))))
148 RC:$src1, RC:$src2))], d>;
149 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
151 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
152 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
153 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_",
154 !strconcat(SSEVer, !strconcat("_",
155 !strconcat(OpcodeStr, FPSizeStr))))
156 RC:$src1, (mem_frag addr:$src2)))], d>;
159 //===----------------------------------------------------------------------===//
160 // SSE 1 & 2 - Move Instructions
161 //===----------------------------------------------------------------------===//
163 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
164 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
165 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
167 // Loading from memory automatically zeroing upper bits.
168 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
169 PatFrag mem_pat, string OpcodeStr> :
170 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
172 [(set RC:$dst, (mem_pat addr:$src))]>;
174 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
175 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
176 // is used instead. Register-to-register movss/movsd is not modeled as an
177 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
178 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
179 let isAsmParserOnly = 1 in {
180 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
181 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
182 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
183 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
185 let canFoldAsLoad = 1, isReMaterializable = 1 in {
186 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
188 let AddedComplexity = 20 in
189 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
193 let Constraints = "$src1 = $dst" in {
194 def MOVSSrr : sse12_move_rr<FR32, v4f32,
195 "movss\t{$src2, $dst|$dst, $src2}">, XS;
196 def MOVSDrr : sse12_move_rr<FR64, v2f64,
197 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
200 let canFoldAsLoad = 1, isReMaterializable = 1 in {
201 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
203 let AddedComplexity = 20 in
204 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
207 let AddedComplexity = 15 in {
208 // Extract the low 32-bit value from one vector and insert it into another.
209 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
210 (MOVSSrr (v4f32 VR128:$src1),
211 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
212 // Extract the low 64-bit value from one vector and insert it into another.
213 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
214 (MOVSDrr (v2f64 VR128:$src1),
215 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
218 // Implicitly promote a 32-bit scalar to a vector.
219 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
220 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
221 // Implicitly promote a 64-bit scalar to a vector.
222 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
223 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
225 let AddedComplexity = 20 in {
226 // MOVSSrm zeros the high parts of the register; represent this
227 // with SUBREG_TO_REG.
228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
229 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
231 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
233 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
234 // MOVSDrm zeros the high parts of the register; represent this
235 // with SUBREG_TO_REG.
236 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
237 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
238 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
239 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
240 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
241 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
242 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
243 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
244 def : Pat<(v2f64 (X86vzload addr:$src)),
245 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
248 // Store scalar value to memory.
249 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
250 "movss\t{$src, $dst|$dst, $src}",
251 [(store FR32:$src, addr:$dst)]>;
252 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
253 "movsd\t{$src, $dst|$dst, $src}",
254 [(store FR64:$src, addr:$dst)]>;
256 let isAsmParserOnly = 1 in {
257 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
258 "movss\t{$src, $dst|$dst, $src}",
259 [(store FR32:$src, addr:$dst)]>, XS, VEX;
260 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
261 "movsd\t{$src, $dst|$dst, $src}",
262 [(store FR64:$src, addr:$dst)]>, XD, VEX;
265 // Extract and store.
266 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
270 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
273 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
275 // Move Aligned/Unaligned floating point values
276 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
277 X86MemOperand x86memop, PatFrag ld_frag,
278 string asm, Domain d,
279 bit IsReMaterializable = 1> {
280 let neverHasSideEffects = 1 in
281 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
282 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
283 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
284 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
285 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
286 [(set RC:$dst, (ld_frag addr:$src))], d>;
289 let isAsmParserOnly = 1 in {
290 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
291 "movaps", SSEPackedSingle>, VEX;
292 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
293 "movapd", SSEPackedDouble>, OpSize, VEX;
294 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
295 "movups", SSEPackedSingle>, VEX;
296 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
297 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
299 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
300 "movaps", SSEPackedSingle>, VEX;
301 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
302 "movapd", SSEPackedDouble>, OpSize, VEX;
303 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
304 "movups", SSEPackedSingle>, VEX;
305 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
306 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
308 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
309 "movaps", SSEPackedSingle>, TB;
310 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
311 "movapd", SSEPackedDouble>, TB, OpSize;
312 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
313 "movups", SSEPackedSingle>, TB;
314 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
315 "movupd", SSEPackedDouble, 0>, TB, OpSize;
317 let isAsmParserOnly = 1 in {
318 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movaps\t{$src, $dst|$dst, $src}",
320 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
321 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
322 "movapd\t{$src, $dst|$dst, $src}",
323 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
324 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
327 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
328 "movupd\t{$src, $dst|$dst, $src}",
329 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
330 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
331 "movaps\t{$src, $dst|$dst, $src}",
332 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
333 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
334 "movapd\t{$src, $dst|$dst, $src}",
335 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
337 "movups\t{$src, $dst|$dst, $src}",
338 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
339 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
340 "movupd\t{$src, $dst|$dst, $src}",
341 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
343 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
344 "movaps\t{$src, $dst|$dst, $src}",
345 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
346 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
347 "movapd\t{$src, $dst|$dst, $src}",
348 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
349 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
350 "movups\t{$src, $dst|$dst, $src}",
351 [(store (v4f32 VR128:$src), addr:$dst)]>;
352 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
353 "movupd\t{$src, $dst|$dst, $src}",
354 [(store (v2f64 VR128:$src), addr:$dst)]>;
356 // Intrinsic forms of MOVUPS/D load and store
357 let isAsmParserOnly = 1 in {
358 let canFoldAsLoad = 1, isReMaterializable = 1 in
359 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
361 "movups\t{$src, $dst|$dst, $src}",
362 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
363 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
365 "movupd\t{$src, $dst|$dst, $src}",
366 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
367 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
368 (ins f128mem:$dst, VR128:$src),
369 "movups\t{$src, $dst|$dst, $src}",
370 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
371 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
372 (ins f128mem:$dst, VR128:$src),
373 "movupd\t{$src, $dst|$dst, $src}",
374 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
376 let canFoldAsLoad = 1, isReMaterializable = 1 in
377 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
378 "movups\t{$src, $dst|$dst, $src}",
379 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
380 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
381 "movupd\t{$src, $dst|$dst, $src}",
382 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
384 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
385 "movups\t{$src, $dst|$dst, $src}",
386 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
387 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
388 "movupd\t{$src, $dst|$dst, $src}",
389 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
391 // Move Low/High packed floating point values
392 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
393 PatFrag mov_frag, string base_opc,
395 def PSrm : PI<opc, MRMSrcMem,
396 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
397 !strconcat(!strconcat(base_opc,"s"), asm_opr),
400 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
401 SSEPackedSingle>, TB;
403 def PDrm : PI<opc, MRMSrcMem,
404 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
405 !strconcat(!strconcat(base_opc,"d"), asm_opr),
406 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
407 (scalar_to_vector (loadf64 addr:$src2)))))],
408 SSEPackedDouble>, TB, OpSize;
411 let isAsmParserOnly = 1, AddedComplexity = 20 in {
412 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
413 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
414 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
417 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
418 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
419 "\t{$src2, $dst|$dst, $src2}">;
420 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
421 "\t{$src2, $dst|$dst, $src2}">;
424 let isAsmParserOnly = 1 in {
425 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
426 "movlps\t{$src, $dst|$dst, $src}",
427 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
428 (iPTR 0))), addr:$dst)]>, VEX;
429 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
430 "movlpd\t{$src, $dst|$dst, $src}",
431 [(store (f64 (vector_extract (v2f64 VR128:$src),
432 (iPTR 0))), addr:$dst)]>, VEX;
434 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
435 "movlps\t{$src, $dst|$dst, $src}",
436 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
437 (iPTR 0))), addr:$dst)]>;
438 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movlpd\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract (v2f64 VR128:$src),
441 (iPTR 0))), addr:$dst)]>;
443 // v2f64 extract element 1 is always custom lowered to unpack high to low
444 // and extract element 0 so the non-store version isn't too horrible.
445 let isAsmParserOnly = 1 in {
446 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
447 "movhps\t{$src, $dst|$dst, $src}",
448 [(store (f64 (vector_extract
449 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
450 (undef)), (iPTR 0))), addr:$dst)]>,
452 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
453 "movhpd\t{$src, $dst|$dst, $src}",
454 [(store (f64 (vector_extract
455 (v2f64 (unpckh VR128:$src, (undef))),
456 (iPTR 0))), addr:$dst)]>,
459 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
460 "movhps\t{$src, $dst|$dst, $src}",
461 [(store (f64 (vector_extract
462 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
463 (undef)), (iPTR 0))), addr:$dst)]>;
464 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
465 "movhpd\t{$src, $dst|$dst, $src}",
466 [(store (f64 (vector_extract
467 (v2f64 (unpckh VR128:$src, (undef))),
468 (iPTR 0))), addr:$dst)]>;
470 let isAsmParserOnly = 1, AddedComplexity = 20 in {
471 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
472 (ins VR128:$src1, VR128:$src2),
473 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
475 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
477 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
478 (ins VR128:$src1, VR128:$src2),
479 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
481 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
484 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
485 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
486 (ins VR128:$src1, VR128:$src2),
487 "movlhps\t{$src2, $dst|$dst, $src2}",
489 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
490 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
491 (ins VR128:$src1, VR128:$src2),
492 "movhlps\t{$src2, $dst|$dst, $src2}",
494 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
497 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
498 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
499 let AddedComplexity = 20 in {
500 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
501 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
502 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
503 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
506 //===----------------------------------------------------------------------===//
507 // SSE 1 & 2 - Conversion Instructions
508 //===----------------------------------------------------------------------===//
510 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
511 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
513 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
514 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
515 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
516 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
519 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
520 X86MemOperand x86memop, string asm> {
521 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
523 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
527 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
528 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
529 string asm, Domain d> {
530 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
531 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
532 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
533 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
536 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
537 X86MemOperand x86memop, string asm> {
538 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
539 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
540 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
541 (ins DstRC:$src1, x86memop:$src),
542 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
545 let isAsmParserOnly = 1 in {
546 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
547 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
548 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
549 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
551 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
552 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
553 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
554 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
557 // The assembler can recognize rr 64-bit instructions by seeing a rxx
558 // register, but the same isn't true when only using memory operands,
559 // provide other assembly "l" and "q" forms to address this explicitly
560 // where appropriate to do so.
561 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
563 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
565 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
567 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
569 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
573 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
574 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
575 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
576 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
577 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
578 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
579 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
580 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
581 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
582 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
583 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
584 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
585 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
586 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
587 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
588 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
590 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
591 // and/or XMM operand(s).
592 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
593 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
594 string asm, Domain d> {
595 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
596 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
597 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
598 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
601 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
602 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
604 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
605 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
606 [(set DstRC:$dst, (Int SrcRC:$src))]>;
607 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
608 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
609 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
612 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
613 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
614 PatFrag ld_frag, string asm, Domain d> {
615 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
616 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
617 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
618 (ins DstRC:$src1, x86memop:$src2), asm,
619 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
622 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
623 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
624 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
625 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
627 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
628 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
629 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
630 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
631 (ins DstRC:$src1, x86memop:$src2),
633 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
634 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
635 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
638 let isAsmParserOnly = 1 in {
639 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
640 f32mem, load, "cvtss2si">, XS, VEX;
641 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
642 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
644 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
645 f128mem, load, "cvtsd2si">, XD, VEX;
646 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
647 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
650 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
651 // Get rid of this hack or rename the intrinsics, there are several
652 // intructions that only match with the intrinsic form, why create duplicates
653 // to let them be recognized by the assembler?
654 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
655 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
656 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
657 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
659 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
660 f32mem, load, "cvtss2si">, XS;
661 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
662 f32mem, load, "cvtss2si{q}">, XS, REX_W;
663 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
664 f128mem, load, "cvtsd2si">, XD;
665 defm Int_CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
666 f128mem, load, "cvtsd2si">, XD, REX_W;
668 defm CVTSD2SI64 : sse12_cvt_s_np<0x2D, VR128, GR64, f64mem, "cvtsd2si{q}">, XD,
671 let isAsmParserOnly = 1 in {
672 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
673 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
674 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
675 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
677 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
678 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
679 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
680 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
684 let Constraints = "$src1 = $dst" in {
685 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
686 int_x86_sse_cvtsi2ss, i32mem, loadi32,
688 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
689 int_x86_sse_cvtsi642ss, i64mem, loadi64,
690 "cvtsi2ss{q}">, XS, REX_W;
691 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
692 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
694 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
695 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
696 "cvtsi2sd">, XD, REX_W;
699 // Instructions below don't have an AVX form.
700 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
701 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
702 SSEPackedSingle>, TB;
703 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
704 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
705 SSEPackedDouble>, TB, OpSize;
706 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
707 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
708 SSEPackedSingle>, TB;
709 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
710 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
711 SSEPackedDouble>, TB, OpSize;
712 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
713 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
714 SSEPackedDouble>, TB, OpSize;
715 let Constraints = "$src1 = $dst" in {
716 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
717 int_x86_sse_cvtpi2ps,
718 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
719 SSEPackedSingle>, TB;
724 // Aliases for intrinsics
725 let isAsmParserOnly = 1 in {
726 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
727 f32mem, load, "cvttss2si">, XS, VEX;
728 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
729 int_x86_sse_cvttss2si64, f32mem, load,
730 "cvttss2si">, XS, VEX, VEX_W;
731 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
732 f128mem, load, "cvttss2si">, XD, VEX;
733 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
734 int_x86_sse2_cvttsd2si64, f128mem, load,
735 "cvttss2si">, XD, VEX, VEX_W;
737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
738 f32mem, load, "cvttss2si">, XS;
739 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
740 int_x86_sse_cvttss2si64, f32mem, load,
741 "cvttss2si{q}">, XS, REX_W;
742 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
743 f128mem, load, "cvttss2si">, XD;
744 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
745 int_x86_sse2_cvttsd2si64, f128mem, load,
746 "cvttss2si{q}">, XD, REX_W;
748 let isAsmParserOnly = 1, Pattern = []<dag> in {
749 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
750 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
751 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
752 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
754 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
755 "cvtdq2ps\t{$src, $dst|$dst, $src}",
756 SSEPackedSingle>, TB, VEX;
757 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, f256mem, load,
758 "cvtdq2ps\t{$src, $dst|$dst, $src}",
759 SSEPackedSingle>, TB, VEX;
761 let Pattern = []<dag> in {
762 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
763 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
764 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
765 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
766 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
767 "cvtdq2ps\t{$src, $dst|$dst, $src}",
768 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
773 // Convert scalar double to scalar single
774 let isAsmParserOnly = 1 in {
775 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
776 (ins FR64:$src1, FR64:$src2),
777 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
779 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
780 (ins FR64:$src1, f64mem:$src2),
781 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
782 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
784 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
785 "cvtsd2ss\t{$src, $dst|$dst, $src}",
786 [(set FR32:$dst, (fround FR64:$src))]>;
787 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
788 "cvtsd2ss\t{$src, $dst|$dst, $src}",
789 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
790 Requires<[HasSSE2, OptForSize]>;
792 let isAsmParserOnly = 1 in
793 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
794 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
796 let Constraints = "$src1 = $dst" in
797 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
798 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
800 // Convert scalar single to scalar double
801 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
802 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
803 (ins FR32:$src1, FR32:$src2),
804 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
805 []>, XS, Requires<[HasAVX]>, VEX_4V;
806 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
807 (ins FR32:$src1, f32mem:$src2),
808 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
809 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
811 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
812 "cvtss2sd\t{$src, $dst|$dst, $src}",
813 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
815 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
816 "cvtss2sd\t{$src, $dst|$dst, $src}",
817 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
818 Requires<[HasSSE2, OptForSize]>;
820 let isAsmParserOnly = 1 in {
821 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
822 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
823 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
824 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
825 VR128:$src2))]>, XS, VEX_4V,
827 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
828 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
829 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
830 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
831 (load addr:$src2)))]>, XS, VEX_4V,
834 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
835 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
836 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
837 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
838 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
841 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
842 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
843 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
844 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
845 (load addr:$src2)))]>, XS,
849 def : Pat<(extloadf32 addr:$src),
850 (CVTSS2SDrr (MOVSSrm addr:$src))>,
851 Requires<[HasSSE2, OptForSpeed]>;
853 // Convert doubleword to packed single/double fp
854 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
855 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
856 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
857 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
858 TB, VEX, Requires<[HasAVX]>;
859 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
860 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
861 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
862 (bitconvert (memopv2i64 addr:$src))))]>,
863 TB, VEX, Requires<[HasAVX]>;
865 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
866 "cvtdq2ps\t{$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
868 TB, Requires<[HasSSE2]>;
869 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
870 "cvtdq2ps\t{$src, $dst|$dst, $src}",
871 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
872 (bitconvert (memopv2i64 addr:$src))))]>,
873 TB, Requires<[HasSSE2]>;
875 // FIXME: why the non-intrinsic version is described as SSE3?
876 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
877 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
878 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
880 XS, VEX, Requires<[HasAVX]>;
881 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
882 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
884 (bitconvert (memopv2i64 addr:$src))))]>,
885 XS, VEX, Requires<[HasAVX]>;
887 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
888 "cvtdq2pd\t{$src, $dst|$dst, $src}",
889 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
890 XS, Requires<[HasSSE2]>;
891 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
892 "cvtdq2pd\t{$src, $dst|$dst, $src}",
893 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
894 (bitconvert (memopv2i64 addr:$src))))]>,
895 XS, Requires<[HasSSE2]>;
897 // Convert packed single/double fp to doubleword
898 let isAsmParserOnly = 1 in {
899 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
900 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
901 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
903 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
904 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
905 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
906 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
908 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
909 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
910 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
913 let isAsmParserOnly = 1 in {
914 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
915 "cvtps2dq\t{$src, $dst|$dst, $src}",
916 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
918 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
920 "cvtps2dq\t{$src, $dst|$dst, $src}",
921 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
922 (memop addr:$src)))]>, VEX;
924 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
925 "cvtps2dq\t{$src, $dst|$dst, $src}",
926 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
927 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
928 "cvtps2dq\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
930 (memop addr:$src)))]>;
932 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
933 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
934 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
936 XD, VEX, Requires<[HasAVX]>;
937 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
938 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
939 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
940 (memop addr:$src)))]>,
941 XD, VEX, Requires<[HasAVX]>;
943 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
944 "cvtpd2dq\t{$src, $dst|$dst, $src}",
945 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
946 XD, Requires<[HasSSE2]>;
947 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
948 "cvtpd2dq\t{$src, $dst|$dst, $src}",
949 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
950 (memop addr:$src)))]>,
951 XD, Requires<[HasSSE2]>;
954 // Convert with truncation packed single/double fp to doubleword
955 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
956 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
960 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
961 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
963 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
965 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
966 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
967 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
968 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
971 let isAsmParserOnly = 1 in {
972 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "vcvttps2dq\t{$src, $dst|$dst, $src}",
975 (int_x86_sse2_cvttps2dq VR128:$src))]>,
976 XS, VEX, Requires<[HasAVX]>;
977 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
978 "vcvttps2dq\t{$src, $dst|$dst, $src}",
979 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
980 (memop addr:$src)))]>,
981 XS, VEX, Requires<[HasAVX]>;
983 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
984 "cvttps2dq\t{$src, $dst|$dst, $src}",
986 (int_x86_sse2_cvttps2dq VR128:$src))]>,
987 XS, Requires<[HasSSE2]>;
988 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
989 "cvttps2dq\t{$src, $dst|$dst, $src}",
990 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
991 (memop addr:$src)))]>,
992 XS, Requires<[HasSSE2]>;
994 let isAsmParserOnly = 1 in {
995 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
997 "cvttpd2dq\t{$src, $dst|$dst, $src}",
998 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
1000 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
1002 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1003 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1004 (memop addr:$src)))]>, VEX;
1006 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1007 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1008 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1009 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1010 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1011 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1012 (memop addr:$src)))]>;
1014 let isAsmParserOnly = 1 in {
1015 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1016 // register, but the same isn't true when using memory operands instead.
1017 // Provide other assembly rr and rm forms to address this explicitly.
1018 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1019 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1020 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1021 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
1024 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1025 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1026 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1027 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
1030 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1031 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
1032 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1033 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1036 // Convert packed single to packed double
1037 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1038 // SSE2 instructions without OpSize prefix
1039 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1040 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1041 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1042 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1043 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
1044 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1045 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
1046 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
1048 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1049 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1050 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1051 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1053 let isAsmParserOnly = 1 in {
1054 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1055 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1056 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1057 VEX, Requires<[HasAVX]>;
1058 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1059 "vcvtps2pd\t{$src, $dst|$dst, $src}",
1060 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1061 (load addr:$src)))]>,
1062 VEX, Requires<[HasAVX]>;
1064 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1065 "cvtps2pd\t{$src, $dst|$dst, $src}",
1066 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1067 TB, Requires<[HasSSE2]>;
1068 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1069 "cvtps2pd\t{$src, $dst|$dst, $src}",
1070 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1071 (load addr:$src)))]>,
1072 TB, Requires<[HasSSE2]>;
1074 // Convert packed double to packed single
1075 let isAsmParserOnly = 1 in {
1076 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1077 // register, but the same isn't true when using memory operands instead.
1078 // Provide other assembly rr and rm forms to address this explicitly.
1079 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1080 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1081 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1082 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
1085 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1086 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1087 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1088 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
1091 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
1092 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
1093 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
1094 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
1096 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1097 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1098 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1099 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1102 let isAsmParserOnly = 1 in {
1103 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1104 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1105 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1106 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
1108 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1109 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1110 (memop addr:$src)))]>;
1112 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1113 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1114 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1115 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1116 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1117 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1118 (memop addr:$src)))]>;
1120 //===----------------------------------------------------------------------===//
1121 // SSE 1 & 2 - Compare Instructions
1122 //===----------------------------------------------------------------------===//
1124 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1125 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1126 string asm, string asm_alt> {
1127 def rr : SIi8<0xC2, MRMSrcReg,
1128 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1131 def rm : SIi8<0xC2, MRMSrcMem,
1132 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1134 // Accept explicit immediate argument form instead of comparison code.
1135 let isAsmParserOnly = 1 in {
1136 def rr_alt : SIi8<0xC2, MRMSrcReg,
1137 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1140 def rm_alt : SIi8<0xC2, MRMSrcMem,
1141 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1146 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1147 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1148 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1149 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1151 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1152 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1153 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1157 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1158 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1159 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1160 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1161 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1162 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1163 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1166 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1167 Intrinsic Int, string asm> {
1168 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1169 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1170 [(set VR128:$dst, (Int VR128:$src1,
1171 VR128:$src, imm:$cc))]>;
1172 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1173 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1174 [(set VR128:$dst, (Int VR128:$src1,
1175 (load addr:$src), imm:$cc))]>;
1178 // Aliases to match intrinsics which expect XMM operand(s).
1179 let isAsmParserOnly = 1 in {
1180 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1181 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1183 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1184 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1187 let Constraints = "$src1 = $dst" in {
1188 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1189 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1190 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1191 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1195 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1196 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1197 ValueType vt, X86MemOperand x86memop,
1198 PatFrag ld_frag, string OpcodeStr, Domain d> {
1199 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1200 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1201 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1202 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1203 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1204 [(set EFLAGS, (OpNode (vt RC:$src1),
1205 (ld_frag addr:$src2)))], d>;
1208 let Defs = [EFLAGS] in {
1209 let isAsmParserOnly = 1 in {
1210 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1211 "ucomiss", SSEPackedSingle>, VEX;
1212 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1213 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1214 let Pattern = []<dag> in {
1215 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1216 "comiss", SSEPackedSingle>, VEX;
1217 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1218 "comisd", SSEPackedDouble>, OpSize, VEX;
1221 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1222 load, "ucomiss", SSEPackedSingle>, VEX;
1223 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1224 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1226 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1227 load, "comiss", SSEPackedSingle>, VEX;
1228 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1229 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1231 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1232 "ucomiss", SSEPackedSingle>, TB;
1233 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1234 "ucomisd", SSEPackedDouble>, TB, OpSize;
1236 let Pattern = []<dag> in {
1237 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1238 "comiss", SSEPackedSingle>, TB;
1239 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1240 "comisd", SSEPackedDouble>, TB, OpSize;
1243 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1244 load, "ucomiss", SSEPackedSingle>, TB;
1245 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1246 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1248 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1249 "comiss", SSEPackedSingle>, TB;
1250 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1251 "comisd", SSEPackedDouble>, TB, OpSize;
1252 } // Defs = [EFLAGS]
1254 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1255 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1256 Intrinsic Int, string asm, string asm_alt,
1258 def rri : PIi8<0xC2, MRMSrcReg,
1259 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1260 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1261 def rmi : PIi8<0xC2, MRMSrcMem,
1262 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1263 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1264 // Accept explicit immediate argument form instead of comparison code.
1265 let isAsmParserOnly = 1 in {
1266 def rri_alt : PIi8<0xC2, MRMSrcReg,
1267 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1269 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1270 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1275 let isAsmParserOnly = 1 in {
1276 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1277 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1278 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1279 SSEPackedSingle>, VEX_4V;
1280 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1281 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1282 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1283 SSEPackedDouble>, OpSize, VEX_4V;
1284 let Pattern = []<dag> in {
1285 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_sse_cmp_ps,
1286 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1287 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1288 SSEPackedSingle>, VEX_4V;
1289 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_sse2_cmp_pd,
1290 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1291 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1292 SSEPackedDouble>, OpSize, VEX_4V;
1295 let Constraints = "$src1 = $dst" in {
1296 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1297 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1298 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1299 SSEPackedSingle>, TB;
1300 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1301 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1302 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1303 SSEPackedDouble>, TB, OpSize;
1306 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1307 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1308 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1309 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1310 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1311 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1312 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1313 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1315 //===----------------------------------------------------------------------===//
1316 // SSE 1 & 2 - Shuffle Instructions
1317 //===----------------------------------------------------------------------===//
1319 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1320 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1321 ValueType vt, string asm, PatFrag mem_frag,
1322 Domain d, bit IsConvertibleToThreeAddress = 0> {
1323 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1324 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1325 [(set RC:$dst, (vt (shufp:$src3
1326 RC:$src1, (mem_frag addr:$src2))))], d>;
1327 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1328 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1329 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1331 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1334 let isAsmParserOnly = 1 in {
1335 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1336 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1337 memopv4f32, SSEPackedSingle>, VEX_4V;
1338 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1339 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1340 memopv8f32, SSEPackedSingle>, VEX_4V;
1341 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1342 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1343 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1344 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1345 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1346 memopv4f64, SSEPackedDouble>, OpSize, VEX_4V;
1349 let Constraints = "$src1 = $dst" in {
1350 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1351 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1352 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1354 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1355 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1356 memopv2f64, SSEPackedDouble>, TB, OpSize;
1359 //===----------------------------------------------------------------------===//
1360 // SSE 1 & 2 - Unpack Instructions
1361 //===----------------------------------------------------------------------===//
1363 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1364 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1365 PatFrag mem_frag, RegisterClass RC,
1366 X86MemOperand x86memop, string asm,
1368 def rr : PI<opc, MRMSrcReg,
1369 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1371 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1372 def rm : PI<opc, MRMSrcMem,
1373 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1375 (vt (OpNode RC:$src1,
1376 (mem_frag addr:$src2))))], d>;
1379 let AddedComplexity = 10 in {
1380 let isAsmParserOnly = 1 in {
1381 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1382 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1383 SSEPackedSingle>, VEX_4V;
1384 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1385 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1386 SSEPackedDouble>, OpSize, VEX_4V;
1387 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1388 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1389 SSEPackedSingle>, VEX_4V;
1390 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1391 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1392 SSEPackedDouble>, OpSize, VEX_4V;
1394 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1395 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1396 SSEPackedSingle>, VEX_4V;
1397 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1398 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1399 SSEPackedDouble>, OpSize, VEX_4V;
1400 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1401 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 SSEPackedSingle>, VEX_4V;
1403 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1404 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1405 SSEPackedDouble>, OpSize, VEX_4V;
1408 let Constraints = "$src1 = $dst" in {
1409 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1410 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1411 SSEPackedSingle>, TB;
1412 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1413 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1414 SSEPackedDouble>, TB, OpSize;
1415 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1416 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1417 SSEPackedSingle>, TB;
1418 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1419 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1420 SSEPackedDouble>, TB, OpSize;
1421 } // Constraints = "$src1 = $dst"
1422 } // AddedComplexity
1424 //===----------------------------------------------------------------------===//
1425 // SSE 1 & 2 - Extract Floating-Point Sign mask
1426 //===----------------------------------------------------------------------===//
1428 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1429 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1431 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1432 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1433 [(set GR32:$dst, (Int RC:$src))], d>;
1437 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1438 SSEPackedSingle>, TB;
1439 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1440 SSEPackedDouble>, TB, OpSize;
1442 let isAsmParserOnly = 1 in {
1443 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1444 "movmskps", SSEPackedSingle>, VEX;
1445 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1446 "movmskpd", SSEPackedDouble>, OpSize,
1449 // FIXME: merge with multiclass above when the intrinsics come.
1450 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1451 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1452 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1453 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1456 def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1457 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1458 def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1459 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1462 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1463 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1464 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1465 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1469 //===----------------------------------------------------------------------===//
1470 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1471 //===----------------------------------------------------------------------===//
1473 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1474 // names that start with 'Fs'.
1476 // Alias instructions that map fld0 to pxor for sse.
1477 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1478 canFoldAsLoad = 1 in {
1479 // FIXME: Set encoding to pseudo!
1480 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1481 [(set FR32:$dst, fp32imm0)]>,
1482 Requires<[HasSSE1]>, TB, OpSize;
1483 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1484 [(set FR64:$dst, fpimm0)]>,
1485 Requires<[HasSSE2]>, TB, OpSize;
1488 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1489 // bits are disregarded.
1490 let neverHasSideEffects = 1 in {
1491 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1492 "movaps\t{$src, $dst|$dst, $src}", []>;
1493 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1494 "movapd\t{$src, $dst|$dst, $src}", []>;
1497 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1498 // bits are disregarded.
1499 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1500 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1501 "movaps\t{$src, $dst|$dst, $src}",
1502 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1503 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1504 "movapd\t{$src, $dst|$dst, $src}",
1505 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1508 //===----------------------------------------------------------------------===//
1509 // SSE 1 & 2 - Logical Instructions
1510 //===----------------------------------------------------------------------===//
1512 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1514 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1516 let isAsmParserOnly = 1 in {
1517 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1518 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1520 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1521 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1524 let Constraints = "$src1 = $dst" in {
1525 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1526 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1528 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1529 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1533 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1534 let mayLoad = 0 in {
1535 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1536 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1537 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1540 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1541 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1543 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1545 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1546 SDNode OpNode, int HasPat = 0,
1547 list<list<dag>> Pattern = []> {
1548 let isAsmParserOnly = 1, Pattern = []<dag> in {
1549 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1550 !strconcat(OpcodeStr, "ps"), f128mem,
1551 !if(HasPat, Pattern[0], // rr
1552 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1554 !if(HasPat, Pattern[2], // rm
1555 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1556 (memopv2i64 addr:$src2)))]), 0>,
1559 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1560 !strconcat(OpcodeStr, "pd"), f128mem,
1561 !if(HasPat, Pattern[1], // rr
1562 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1565 !if(HasPat, Pattern[3], // rm
1566 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1567 (memopv2i64 addr:$src2)))]), 0>,
1570 let Constraints = "$src1 = $dst" in {
1571 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1572 !strconcat(OpcodeStr, "ps"), f128mem,
1573 !if(HasPat, Pattern[0], // rr
1574 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1576 !if(HasPat, Pattern[2], // rm
1577 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1578 (memopv2i64 addr:$src2)))])>, TB;
1580 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1581 !strconcat(OpcodeStr, "pd"), f128mem,
1582 !if(HasPat, Pattern[1], // rr
1583 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1586 !if(HasPat, Pattern[3], // rm
1587 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1588 (memopv2i64 addr:$src2)))])>,
1593 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1595 let isAsmParserOnly = 1 in {
1596 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1597 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1598 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1600 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1601 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1605 // AVX 256-bit packed logical ops forms
1606 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1607 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1608 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1609 let isCommutable = 0 in
1610 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1612 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1613 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1614 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1615 let isCommutable = 0 in
1616 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1618 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1619 (bc_v2i64 (v4i32 immAllOnesV))),
1622 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1623 (bc_v2i64 (v2f64 VR128:$src2))))],
1625 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1626 (bc_v2i64 (v4i32 immAllOnesV))),
1627 (memopv2i64 addr:$src2))))],
1629 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1630 (memopv2i64 addr:$src2)))]]>;
1632 //===----------------------------------------------------------------------===//
1633 // SSE 1 & 2 - Arithmetic Instructions
1634 //===----------------------------------------------------------------------===//
1636 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1639 /// In addition, we also have a special variant of the scalar form here to
1640 /// represent the associated intrinsic operation. This form is unlike the
1641 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1642 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1644 /// These three forms can each be reg+reg or reg+mem.
1647 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1649 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1651 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1652 OpNode, FR32, f32mem, Is2Addr>, XS;
1653 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1654 OpNode, FR64, f64mem, Is2Addr>, XD;
1657 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1659 let mayLoad = 0 in {
1660 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1661 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1662 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1663 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1667 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1669 let mayLoad = 0 in {
1670 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1671 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1672 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1673 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1677 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1679 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1680 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1681 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1682 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1685 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1687 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1688 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1689 SSEPackedSingle, Is2Addr>, TB;
1691 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1692 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1693 SSEPackedDouble, Is2Addr>, TB, OpSize;
1696 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1697 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1698 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1699 SSEPackedSingle, 0>, TB;
1701 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1702 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1703 SSEPackedDouble, 0>, TB, OpSize;
1706 // Binary Arithmetic instructions
1707 let isAsmParserOnly = 1 in {
1708 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1709 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1710 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1711 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1712 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1713 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1714 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1715 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1717 let isCommutable = 0 in {
1718 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1719 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1720 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1721 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1722 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1723 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1724 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1725 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1726 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1727 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1728 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1729 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1730 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1731 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1732 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1733 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1734 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1735 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1736 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1737 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1741 let Constraints = "$src1 = $dst" in {
1742 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1743 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1744 basic_sse12_fp_binop_s_int<0x58, "add">;
1745 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1746 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1747 basic_sse12_fp_binop_s_int<0x59, "mul">;
1749 let isCommutable = 0 in {
1750 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1751 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1752 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1753 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1754 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1755 basic_sse12_fp_binop_s_int<0x5E, "div">;
1756 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1757 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1758 basic_sse12_fp_binop_s_int<0x5F, "max">,
1759 basic_sse12_fp_binop_p_int<0x5F, "max">;
1760 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1761 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1762 basic_sse12_fp_binop_s_int<0x5D, "min">,
1763 basic_sse12_fp_binop_p_int<0x5D, "min">;
1768 /// In addition, we also have a special variant of the scalar form here to
1769 /// represent the associated intrinsic operation. This form is unlike the
1770 /// plain scalar form, in that it takes an entire vector (instead of a
1771 /// scalar) and leaves the top elements undefined.
1773 /// And, we have a special variant form for a full-vector intrinsic form.
1775 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1776 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1777 SDNode OpNode, Intrinsic F32Int> {
1778 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1779 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1780 [(set FR32:$dst, (OpNode FR32:$src))]>;
1781 // For scalar unary operations, fold a load into the operation
1782 // only in OptForSize mode. It eliminates an instruction, but it also
1783 // eliminates a whole-register clobber (the load), so it introduces a
1784 // partial register update condition.
1785 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1786 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1787 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1788 Requires<[HasSSE1, OptForSize]>;
1789 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1790 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1791 [(set VR128:$dst, (F32Int VR128:$src))]>;
1792 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1793 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1794 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1797 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1798 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1799 SDNode OpNode, Intrinsic F32Int> {
1800 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1801 !strconcat(OpcodeStr,
1802 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1803 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1804 !strconcat(OpcodeStr,
1805 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1806 []>, XS, Requires<[HasAVX, OptForSize]>;
1807 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1808 !strconcat(OpcodeStr,
1809 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1810 [(set VR128:$dst, (F32Int VR128:$src))]>;
1811 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1812 !strconcat(OpcodeStr,
1813 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1814 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1817 /// sse1_fp_unop_p - SSE1 unops in packed form.
1818 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1819 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1820 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1821 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1822 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1823 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1824 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1827 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1828 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1829 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1830 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1831 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1832 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1833 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1834 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1837 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1838 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1839 Intrinsic V4F32Int> {
1840 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1841 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1842 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1843 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1844 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1845 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1848 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1849 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1850 Intrinsic V4F32Int> {
1851 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1852 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1853 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1854 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1855 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1856 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1859 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1860 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1861 SDNode OpNode, Intrinsic F64Int> {
1862 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1863 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1864 [(set FR64:$dst, (OpNode FR64:$src))]>;
1865 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1866 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1867 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1868 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1869 Requires<[HasSSE2, OptForSize]>;
1870 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1871 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1872 [(set VR128:$dst, (F64Int VR128:$src))]>;
1873 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1874 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1875 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1878 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1879 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1880 SDNode OpNode, Intrinsic F64Int> {
1881 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1882 !strconcat(OpcodeStr,
1883 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1884 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1885 (ins FR64:$src1, f64mem:$src2),
1886 !strconcat(OpcodeStr,
1887 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1888 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1889 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1890 [(set VR128:$dst, (F64Int VR128:$src))]>;
1891 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1892 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1893 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1896 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1897 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1899 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1900 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1901 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1902 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1903 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1904 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1907 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1908 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1909 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1910 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1911 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1912 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1913 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1914 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1917 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1918 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1919 Intrinsic V2F64Int> {
1920 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1921 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1922 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1923 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1924 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1925 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1928 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1929 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1930 Intrinsic V2F64Int> {
1931 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1932 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1933 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1934 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1935 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1936 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1939 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1941 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1942 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1945 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1946 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1947 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1948 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1949 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1950 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1951 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1952 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1955 // Reciprocal approximations. Note that these typically require refinement
1956 // in order to obtain suitable precision.
1957 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1958 int_x86_sse_rsqrt_ss>, VEX_4V;
1959 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1960 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1961 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1962 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1964 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1966 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1967 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1968 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1969 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1973 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1974 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1975 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1976 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1977 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1978 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1980 // Reciprocal approximations. Note that these typically require refinement
1981 // in order to obtain suitable precision.
1982 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1983 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1984 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1985 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1986 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1987 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1989 // There is no f64 version of the reciprocal approximation instructions.
1991 //===----------------------------------------------------------------------===//
1992 // SSE 1 & 2 - Non-temporal stores
1993 //===----------------------------------------------------------------------===//
1995 let isAsmParserOnly = 1 in {
1996 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
1997 (ins i128mem:$dst, VR128:$src),
1998 "movntps\t{$src, $dst|$dst, $src}",
1999 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
2000 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
2001 (ins i128mem:$dst, VR128:$src),
2002 "movntpd\t{$src, $dst|$dst, $src}",
2003 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
2005 let ExeDomain = SSEPackedInt in
2006 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
2007 (ins f128mem:$dst, VR128:$src),
2008 "movntdq\t{$src, $dst|$dst, $src}",
2009 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
2011 let AddedComplexity = 400 in { // Prefer non-temporal versions
2012 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
2013 (ins f128mem:$dst, VR128:$src),
2014 "movntps\t{$src, $dst|$dst, $src}",
2015 [(alignednontemporalstore (v4f32 VR128:$src),
2017 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
2018 (ins f128mem:$dst, VR128:$src),
2019 "movntpd\t{$src, $dst|$dst, $src}",
2020 [(alignednontemporalstore (v2f64 VR128:$src),
2022 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
2023 (ins f128mem:$dst, VR128:$src),
2024 "movntdq\t{$src, $dst|$dst, $src}",
2025 [(alignednontemporalstore (v2f64 VR128:$src),
2027 let ExeDomain = SSEPackedInt in
2028 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
2029 (ins f128mem:$dst, VR128:$src),
2030 "movntdq\t{$src, $dst|$dst, $src}",
2031 [(alignednontemporalstore (v4f32 VR128:$src),
2034 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
2035 (ins f256mem:$dst, VR256:$src),
2036 "movntps\t{$src, $dst|$dst, $src}",
2037 [(alignednontemporalstore (v8f32 VR256:$src),
2039 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
2040 (ins f256mem:$dst, VR256:$src),
2041 "movntpd\t{$src, $dst|$dst, $src}",
2042 [(alignednontemporalstore (v4f64 VR256:$src),
2044 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
2045 (ins f256mem:$dst, VR256:$src),
2046 "movntdq\t{$src, $dst|$dst, $src}",
2047 [(alignednontemporalstore (v4f64 VR256:$src),
2049 let ExeDomain = SSEPackedInt in
2050 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
2051 (ins f256mem:$dst, VR256:$src),
2052 "movntdq\t{$src, $dst|$dst, $src}",
2053 [(alignednontemporalstore (v8f32 VR256:$src),
2058 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2059 "movntps\t{$src, $dst|$dst, $src}",
2060 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2061 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2062 "movntpd\t{$src, $dst|$dst, $src}",
2063 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2065 let ExeDomain = SSEPackedInt in
2066 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2067 "movntdq\t{$src, $dst|$dst, $src}",
2068 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2070 let AddedComplexity = 400 in { // Prefer non-temporal versions
2071 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2072 "movntps\t{$src, $dst|$dst, $src}",
2073 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2074 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2075 "movntpd\t{$src, $dst|$dst, $src}",
2076 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2078 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2079 "movntdq\t{$src, $dst|$dst, $src}",
2080 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
2082 let ExeDomain = SSEPackedInt in
2083 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2084 "movntdq\t{$src, $dst|$dst, $src}",
2085 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2087 // There is no AVX form for instructions below this point
2088 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2089 "movnti\t{$src, $dst|$dst, $src}",
2090 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
2091 TB, Requires<[HasSSE2]>;
2093 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
2094 "movnti\t{$src, $dst|$dst, $src}",
2095 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2096 TB, Requires<[HasSSE2]>;
2099 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2100 "movnti\t{$src, $dst|$dst, $src}",
2101 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2102 TB, Requires<[HasSSE2]>;
2104 //===----------------------------------------------------------------------===//
2105 // SSE 1 & 2 - Misc Instructions (No AVX form)
2106 //===----------------------------------------------------------------------===//
2108 // Prefetch intrinsic.
2109 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2110 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2111 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2112 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2113 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2114 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2115 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2116 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2118 // Load, store, and memory fence
2119 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2120 TB, Requires<[HasSSE1]>;
2121 def : Pat<(X86SFence), (SFENCE)>;
2123 // Alias instructions that map zero vector to pxor / xorp* for sse.
2124 // We set canFoldAsLoad because this can be converted to a constant-pool
2125 // load of an all-zeros value if folding it would be beneficial.
2126 // FIXME: Change encoding to pseudo!
2127 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2128 isCodeGenOnly = 1 in {
2129 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2130 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2131 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2132 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2133 let ExeDomain = SSEPackedInt in
2134 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2135 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2138 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2139 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2140 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2142 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2143 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2145 //===----------------------------------------------------------------------===//
2146 // SSE 1 & 2 - Load/Store XCSR register
2147 //===----------------------------------------------------------------------===//
2149 let isAsmParserOnly = 1 in {
2150 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2151 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2152 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2153 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2156 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2157 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2158 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2159 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2161 //===---------------------------------------------------------------------===//
2162 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2163 //===---------------------------------------------------------------------===//
2165 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2167 let isAsmParserOnly = 1 in {
2168 let neverHasSideEffects = 1 in {
2169 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2170 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2171 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2172 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2174 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2175 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2176 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2177 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2179 let canFoldAsLoad = 1, mayLoad = 1 in {
2180 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2181 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2182 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2183 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2184 let Predicates = [HasAVX] in {
2185 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2186 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2187 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2188 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2192 let mayStore = 1 in {
2193 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2194 (ins i128mem:$dst, VR128:$src),
2195 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2196 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2197 (ins i256mem:$dst, VR256:$src),
2198 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2199 let Predicates = [HasAVX] in {
2200 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2201 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2202 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2203 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2208 let neverHasSideEffects = 1 in
2209 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2210 "movdqa\t{$src, $dst|$dst, $src}", []>;
2212 let canFoldAsLoad = 1, mayLoad = 1 in {
2213 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2214 "movdqa\t{$src, $dst|$dst, $src}",
2215 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2216 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2217 "movdqu\t{$src, $dst|$dst, $src}",
2218 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2219 XS, Requires<[HasSSE2]>;
2222 let mayStore = 1 in {
2223 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2224 "movdqa\t{$src, $dst|$dst, $src}",
2225 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2226 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2227 "movdqu\t{$src, $dst|$dst, $src}",
2228 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2229 XS, Requires<[HasSSE2]>;
2232 // Intrinsic forms of MOVDQU load and store
2233 let isAsmParserOnly = 1 in {
2234 let canFoldAsLoad = 1 in
2235 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2236 "vmovdqu\t{$src, $dst|$dst, $src}",
2237 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2238 XS, VEX, Requires<[HasAVX]>;
2239 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2240 "vmovdqu\t{$src, $dst|$dst, $src}",
2241 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2242 XS, VEX, Requires<[HasAVX]>;
2245 let canFoldAsLoad = 1 in
2246 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2247 "movdqu\t{$src, $dst|$dst, $src}",
2248 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2249 XS, Requires<[HasSSE2]>;
2250 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2251 "movdqu\t{$src, $dst|$dst, $src}",
2252 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2253 XS, Requires<[HasSSE2]>;
2255 } // ExeDomain = SSEPackedInt
2257 //===---------------------------------------------------------------------===//
2258 // SSE2 - Packed Integer Arithmetic Instructions
2259 //===---------------------------------------------------------------------===//
2261 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2263 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2264 bit IsCommutable = 0, bit Is2Addr = 1> {
2265 let isCommutable = IsCommutable in
2266 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2267 (ins VR128:$src1, VR128:$src2),
2269 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2270 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2271 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2272 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2273 (ins VR128:$src1, i128mem:$src2),
2275 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2276 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2277 [(set VR128:$dst, (IntId VR128:$src1,
2278 (bitconvert (memopv2i64 addr:$src2))))]>;
2281 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2282 string OpcodeStr, Intrinsic IntId,
2283 Intrinsic IntId2, bit Is2Addr = 1> {
2284 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2285 (ins VR128:$src1, VR128:$src2),
2287 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2288 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2289 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2290 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2291 (ins VR128:$src1, i128mem:$src2),
2293 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2294 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2295 [(set VR128:$dst, (IntId VR128:$src1,
2296 (bitconvert (memopv2i64 addr:$src2))))]>;
2297 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2298 (ins VR128:$src1, i32i8imm:$src2),
2300 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2301 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2302 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2305 /// PDI_binop_rm - Simple SSE2 binary operator.
2306 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2307 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2308 let isCommutable = IsCommutable in
2309 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2310 (ins VR128:$src1, VR128:$src2),
2312 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2313 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2314 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2315 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2316 (ins VR128:$src1, i128mem:$src2),
2318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2320 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2321 (bitconvert (memopv2i64 addr:$src2)))))]>;
2324 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2326 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2327 /// to collapse (bitconvert VT to VT) into its operand.
2329 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2330 bit IsCommutable = 0, bit Is2Addr = 1> {
2331 let isCommutable = IsCommutable in
2332 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2333 (ins VR128:$src1, VR128:$src2),
2335 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2336 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2337 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2338 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2339 (ins VR128:$src1, i128mem:$src2),
2341 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2342 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2343 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2346 } // ExeDomain = SSEPackedInt
2348 // 128-bit Integer Arithmetic
2350 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2351 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2352 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2353 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2354 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2355 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2356 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2357 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2358 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2359 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2362 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2364 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2366 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2368 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2370 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2372 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2374 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2376 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2378 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2380 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2382 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2384 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2386 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2388 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2390 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2392 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2394 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2396 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2398 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2402 let Constraints = "$src1 = $dst" in {
2403 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2404 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2405 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2406 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2407 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2408 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2409 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2410 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2411 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2414 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2415 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2416 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2417 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2418 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2419 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2420 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2421 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2422 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2423 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2424 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2425 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2426 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2427 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2428 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2429 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2430 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2431 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2432 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2434 } // Constraints = "$src1 = $dst"
2436 //===---------------------------------------------------------------------===//
2437 // SSE2 - Packed Integer Logical Instructions
2438 //===---------------------------------------------------------------------===//
2440 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2441 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2442 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2444 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2445 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2447 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2448 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2451 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2452 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2454 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2455 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2457 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2458 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2461 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2462 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2464 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2465 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2468 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2469 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2470 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2472 let ExeDomain = SSEPackedInt in {
2473 let neverHasSideEffects = 1 in {
2474 // 128-bit logical shifts.
2475 def VPSLLDQri : PDIi8<0x73, MRM7r,
2476 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2477 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2479 def VPSRLDQri : PDIi8<0x73, MRM3r,
2480 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2481 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2483 // PSRADQri doesn't exist in SSE[1-3].
2485 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2486 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2487 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2488 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2489 VR128:$src2)))]>, VEX_4V;
2491 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2492 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2493 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2494 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2495 (memopv2i64 addr:$src2))))]>,
2500 let Constraints = "$src1 = $dst" in {
2501 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2502 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2503 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2504 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2505 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2506 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2508 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2509 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2510 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2511 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2512 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2513 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2515 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2516 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2517 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2518 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2520 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2521 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2522 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2524 let ExeDomain = SSEPackedInt in {
2525 let neverHasSideEffects = 1 in {
2526 // 128-bit logical shifts.
2527 def PSLLDQri : PDIi8<0x73, MRM7r,
2528 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2529 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2530 def PSRLDQri : PDIi8<0x73, MRM3r,
2531 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2532 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2533 // PSRADQri doesn't exist in SSE[1-3].
2535 def PANDNrr : PDI<0xDF, MRMSrcReg,
2536 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2537 "pandn\t{$src2, $dst|$dst, $src2}",
2538 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2541 def PANDNrm : PDI<0xDF, MRMSrcMem,
2542 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2543 "pandn\t{$src2, $dst|$dst, $src2}",
2544 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2545 (memopv2i64 addr:$src2))))]>;
2547 } // Constraints = "$src1 = $dst"
2549 let Predicates = [HasAVX] in {
2550 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2551 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2552 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2553 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2554 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2555 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2556 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2557 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2558 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2559 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2561 // Shift up / down and insert zero's.
2562 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2563 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2564 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2565 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2568 let Predicates = [HasSSE2] in {
2569 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2570 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2571 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2572 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2573 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2574 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2575 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2576 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2577 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2578 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2580 // Shift up / down and insert zero's.
2581 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2582 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2583 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2584 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2587 //===---------------------------------------------------------------------===//
2588 // SSE2 - Packed Integer Comparison Instructions
2589 //===---------------------------------------------------------------------===//
2591 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2592 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2594 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2596 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2598 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2600 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2602 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2606 let Constraints = "$src1 = $dst" in {
2607 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2608 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2609 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2610 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2611 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2612 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2613 } // Constraints = "$src1 = $dst"
2615 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2616 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2617 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2618 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2619 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2620 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2621 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2622 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2623 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2624 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2625 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2626 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2628 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2629 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2630 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2631 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2632 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2633 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2634 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2635 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2636 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2637 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2638 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2639 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2641 //===---------------------------------------------------------------------===//
2642 // SSE2 - Packed Integer Pack Instructions
2643 //===---------------------------------------------------------------------===//
2645 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2646 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2648 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2650 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2654 let Constraints = "$src1 = $dst" in {
2655 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2656 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2657 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2658 } // Constraints = "$src1 = $dst"
2660 //===---------------------------------------------------------------------===//
2661 // SSE2 - Packed Integer Shuffle Instructions
2662 //===---------------------------------------------------------------------===//
2664 let ExeDomain = SSEPackedInt in {
2665 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2667 def ri : Ii8<0x70, MRMSrcReg,
2668 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2669 !strconcat(OpcodeStr,
2670 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2671 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2673 def mi : Ii8<0x70, MRMSrcMem,
2674 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2675 !strconcat(OpcodeStr,
2676 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2677 [(set VR128:$dst, (vt (pshuf_frag:$src2
2678 (bc_frag (memopv2i64 addr:$src1)),
2681 } // ExeDomain = SSEPackedInt
2683 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2684 let AddedComplexity = 5 in
2685 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2688 // SSE2 with ImmT == Imm8 and XS prefix.
2689 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2692 // SSE2 with ImmT == Imm8 and XD prefix.
2693 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2697 let Predicates = [HasSSE2] in {
2698 let AddedComplexity = 5 in
2699 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2701 // SSE2 with ImmT == Imm8 and XS prefix.
2702 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2704 // SSE2 with ImmT == Imm8 and XD prefix.
2705 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2708 //===---------------------------------------------------------------------===//
2709 // SSE2 - Packed Integer Unpack Instructions
2710 //===---------------------------------------------------------------------===//
2712 let ExeDomain = SSEPackedInt in {
2713 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2714 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2715 def rr : PDI<opc, MRMSrcReg,
2716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2718 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2719 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2720 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2721 def rm : PDI<opc, MRMSrcMem,
2722 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2724 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2725 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2726 [(set VR128:$dst, (unp_frag VR128:$src1,
2727 (bc_frag (memopv2i64
2731 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2732 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2734 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2736 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2739 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2740 /// knew to collapse (bitconvert VT to VT) into its operand.
2741 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2742 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2743 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2745 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2746 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2747 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2748 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2750 (v2i64 (unpckl VR128:$src1,
2751 (memopv2i64 addr:$src2))))]>, VEX_4V;
2753 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2755 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2757 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2760 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2761 /// knew to collapse (bitconvert VT to VT) into its operand.
2762 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2763 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2764 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2766 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2767 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2768 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2769 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2771 (v2i64 (unpckh VR128:$src1,
2772 (memopv2i64 addr:$src2))))]>, VEX_4V;
2775 let Constraints = "$src1 = $dst" in {
2776 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2777 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2778 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2780 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2781 /// knew to collapse (bitconvert VT to VT) into its operand.
2782 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2783 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2784 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2786 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2787 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2788 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2789 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2791 (v2i64 (unpckl VR128:$src1,
2792 (memopv2i64 addr:$src2))))]>;
2794 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2795 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2796 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2798 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2799 /// knew to collapse (bitconvert VT to VT) into its operand.
2800 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2801 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2802 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2804 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2805 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2806 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2807 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2809 (v2i64 (unpckh VR128:$src1,
2810 (memopv2i64 addr:$src2))))]>;
2813 } // ExeDomain = SSEPackedInt
2815 //===---------------------------------------------------------------------===//
2816 // SSE2 - Packed Integer Extract and Insert
2817 //===---------------------------------------------------------------------===//
2819 let ExeDomain = SSEPackedInt in {
2820 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2821 def rri : Ii8<0xC4, MRMSrcReg,
2822 (outs VR128:$dst), (ins VR128:$src1,
2823 GR32:$src2, i32i8imm:$src3),
2825 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2826 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2828 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2829 def rmi : Ii8<0xC4, MRMSrcMem,
2830 (outs VR128:$dst), (ins VR128:$src1,
2831 i16mem:$src2, i32i8imm:$src3),
2833 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2834 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2836 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2841 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2842 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2843 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2844 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2845 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2846 imm:$src2))]>, OpSize, VEX;
2847 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2848 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2849 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2850 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2854 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2855 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2856 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2857 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2858 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2859 []>, OpSize, VEX_4V;
2862 let Constraints = "$src1 = $dst" in
2863 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2865 } // ExeDomain = SSEPackedInt
2867 //===---------------------------------------------------------------------===//
2868 // SSE2 - Packed Mask Creation
2869 //===---------------------------------------------------------------------===//
2871 let ExeDomain = SSEPackedInt in {
2873 let isAsmParserOnly = 1 in {
2874 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2875 "pmovmskb\t{$src, $dst|$dst, $src}",
2876 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2877 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2878 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2880 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2881 "pmovmskb\t{$src, $dst|$dst, $src}",
2882 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2884 } // ExeDomain = SSEPackedInt
2886 //===---------------------------------------------------------------------===//
2887 // SSE2 - Conditional Store
2888 //===---------------------------------------------------------------------===//
2890 let ExeDomain = SSEPackedInt in {
2892 let isAsmParserOnly = 1 in {
2894 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2895 (ins VR128:$src, VR128:$mask),
2896 "maskmovdqu\t{$mask, $src|$src, $mask}",
2897 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2899 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2900 (ins VR128:$src, VR128:$mask),
2901 "maskmovdqu\t{$mask, $src|$src, $mask}",
2902 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2906 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2907 "maskmovdqu\t{$mask, $src|$src, $mask}",
2908 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2910 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2911 "maskmovdqu\t{$mask, $src|$src, $mask}",
2912 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2914 } // ExeDomain = SSEPackedInt
2916 //===---------------------------------------------------------------------===//
2917 // SSE2 - Move Doubleword
2918 //===---------------------------------------------------------------------===//
2920 // Move Int Doubleword to Packed Double Int
2921 let isAsmParserOnly = 1 in {
2922 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2923 "movd\t{$src, $dst|$dst, $src}",
2925 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2926 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2927 "movd\t{$src, $dst|$dst, $src}",
2929 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2932 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2933 "movd\t{$src, $dst|$dst, $src}",
2935 (v4i32 (scalar_to_vector GR32:$src)))]>;
2936 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2937 "movd\t{$src, $dst|$dst, $src}",
2939 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2942 // Move Int Doubleword to Single Scalar
2943 let isAsmParserOnly = 1 in {
2944 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2945 "movd\t{$src, $dst|$dst, $src}",
2946 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2948 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2949 "movd\t{$src, $dst|$dst, $src}",
2950 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2953 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2954 "movd\t{$src, $dst|$dst, $src}",
2955 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2957 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2958 "movd\t{$src, $dst|$dst, $src}",
2959 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2961 // Move Packed Doubleword Int to Packed Double Int
2962 let isAsmParserOnly = 1 in {
2963 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2964 "movd\t{$src, $dst|$dst, $src}",
2965 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2967 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2968 (ins i32mem:$dst, VR128:$src),
2969 "movd\t{$src, $dst|$dst, $src}",
2970 [(store (i32 (vector_extract (v4i32 VR128:$src),
2971 (iPTR 0))), addr:$dst)]>, VEX;
2973 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2974 "movd\t{$src, $dst|$dst, $src}",
2975 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2977 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2978 "movd\t{$src, $dst|$dst, $src}",
2979 [(store (i32 (vector_extract (v4i32 VR128:$src),
2980 (iPTR 0))), addr:$dst)]>;
2982 // Move Scalar Single to Double Int
2983 let isAsmParserOnly = 1 in {
2984 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2985 "movd\t{$src, $dst|$dst, $src}",
2986 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2987 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2988 "movd\t{$src, $dst|$dst, $src}",
2989 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2991 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2992 "movd\t{$src, $dst|$dst, $src}",
2993 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2994 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2995 "movd\t{$src, $dst|$dst, $src}",
2996 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2998 // movd / movq to XMM register zero-extends
2999 let AddedComplexity = 15, isAsmParserOnly = 1 in {
3000 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3001 "movd\t{$src, $dst|$dst, $src}",
3002 [(set VR128:$dst, (v4i32 (X86vzmovl
3003 (v4i32 (scalar_to_vector GR32:$src)))))]>,
3005 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3006 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3007 [(set VR128:$dst, (v2i64 (X86vzmovl
3008 (v2i64 (scalar_to_vector GR64:$src)))))]>,
3011 let AddedComplexity = 15 in {
3012 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
3013 "movd\t{$src, $dst|$dst, $src}",
3014 [(set VR128:$dst, (v4i32 (X86vzmovl
3015 (v4i32 (scalar_to_vector GR32:$src)))))]>;
3016 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3017 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
3018 [(set VR128:$dst, (v2i64 (X86vzmovl
3019 (v2i64 (scalar_to_vector GR64:$src)))))]>;
3022 let AddedComplexity = 20 in {
3023 let isAsmParserOnly = 1 in
3024 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3025 "movd\t{$src, $dst|$dst, $src}",
3027 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3028 (loadi32 addr:$src))))))]>,
3030 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3031 "movd\t{$src, $dst|$dst, $src}",
3033 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
3034 (loadi32 addr:$src))))))]>;
3036 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
3037 (MOVZDI2PDIrm addr:$src)>;
3038 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
3039 (MOVZDI2PDIrm addr:$src)>;
3040 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
3041 (MOVZDI2PDIrm addr:$src)>;
3044 //===---------------------------------------------------------------------===//
3045 // SSE2 - Move Quadword
3046 //===---------------------------------------------------------------------===//
3048 // Move Quadword Int to Packed Quadword Int
3049 let isAsmParserOnly = 1 in
3050 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3051 "vmovq\t{$src, $dst|$dst, $src}",
3053 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3054 VEX, Requires<[HasAVX]>;
3055 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3056 "movq\t{$src, $dst|$dst, $src}",
3058 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
3059 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
3061 // Move Packed Quadword Int to Quadword Int
3062 let isAsmParserOnly = 1 in
3063 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3064 "movq\t{$src, $dst|$dst, $src}",
3065 [(store (i64 (vector_extract (v2i64 VR128:$src),
3066 (iPTR 0))), addr:$dst)]>, VEX;
3067 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3068 "movq\t{$src, $dst|$dst, $src}",
3069 [(store (i64 (vector_extract (v2i64 VR128:$src),
3070 (iPTR 0))), addr:$dst)]>;
3072 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
3073 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
3075 // Store / copy lower 64-bits of a XMM register.
3076 let isAsmParserOnly = 1 in
3077 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3078 "movq\t{$src, $dst|$dst, $src}",
3079 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
3080 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
3081 "movq\t{$src, $dst|$dst, $src}",
3082 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
3084 let AddedComplexity = 20, isAsmParserOnly = 1 in
3085 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3086 "vmovq\t{$src, $dst|$dst, $src}",
3088 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3089 (loadi64 addr:$src))))))]>,
3090 XS, VEX, Requires<[HasAVX]>;
3092 let AddedComplexity = 20 in {
3093 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3094 "movq\t{$src, $dst|$dst, $src}",
3096 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3097 (loadi64 addr:$src))))))]>,
3098 XS, Requires<[HasSSE2]>;
3100 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3101 (MOVZQI2PQIrm addr:$src)>;
3102 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3103 (MOVZQI2PQIrm addr:$src)>;
3104 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3107 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3108 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3109 let isAsmParserOnly = 1, AddedComplexity = 15 in
3110 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3111 "vmovq\t{$src, $dst|$dst, $src}",
3112 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3113 XS, VEX, Requires<[HasAVX]>;
3114 let AddedComplexity = 15 in
3115 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3116 "movq\t{$src, $dst|$dst, $src}",
3117 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3118 XS, Requires<[HasSSE2]>;
3120 let AddedComplexity = 20, isAsmParserOnly = 1 in
3121 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3122 "vmovq\t{$src, $dst|$dst, $src}",
3123 [(set VR128:$dst, (v2i64 (X86vzmovl
3124 (loadv2i64 addr:$src))))]>,
3125 XS, VEX, Requires<[HasAVX]>;
3126 let AddedComplexity = 20 in {
3127 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3128 "movq\t{$src, $dst|$dst, $src}",
3129 [(set VR128:$dst, (v2i64 (X86vzmovl
3130 (loadv2i64 addr:$src))))]>,
3131 XS, Requires<[HasSSE2]>;
3133 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3134 (MOVZPQILo2PQIrm addr:$src)>;
3137 // Instructions to match in the assembler
3138 let isAsmParserOnly = 1 in {
3139 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3140 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3141 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3142 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3143 // Recognize "movd" with GR64 destination, but encode as a "movq"
3144 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3145 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3148 // Instructions for the disassembler
3149 // xr = XMM register
3152 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3153 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3154 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3155 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3156 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3158 //===---------------------------------------------------------------------===//
3159 // SSE2 - Misc Instructions
3160 //===---------------------------------------------------------------------===//
3163 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3164 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3165 TB, Requires<[HasSSE2]>;
3167 // Load, store, and memory fence
3168 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3169 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3170 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3171 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3172 def : Pat<(X86LFence), (LFENCE)>;
3173 def : Pat<(X86MFence), (MFENCE)>;
3176 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3177 // was introduced with SSE2, it's backward compatible.
3178 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3180 // Alias instructions that map zero vector to pxor / xorp* for sse.
3181 // We set canFoldAsLoad because this can be converted to a constant-pool
3182 // load of an all-ones value if folding it would be beneficial.
3183 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3184 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3185 // FIXME: Change encoding to pseudo.
3186 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3187 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3189 //===---------------------------------------------------------------------===//
3190 // SSE3 - Conversion Instructions
3191 //===---------------------------------------------------------------------===//
3193 // Convert Packed Double FP to Packed DW Integers
3194 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3195 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3196 // register, but the same isn't true when using memory operands instead.
3197 // Provide other assembly rr and rm forms to address this explicitly.
3198 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3199 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3200 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3201 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3204 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3205 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3206 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3207 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3210 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3211 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3212 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3213 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3216 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3217 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3218 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3219 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3221 // Convert Packed DW Integers to Packed Double FP
3222 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3223 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3224 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3225 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3226 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3227 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3228 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3229 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3230 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3233 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3234 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3235 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3236 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3238 //===---------------------------------------------------------------------===//
3239 // SSE3 - Move Instructions
3240 //===---------------------------------------------------------------------===//
3242 // Replicate Single FP
3243 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3244 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3245 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3246 [(set VR128:$dst, (v4f32 (rep_frag
3247 VR128:$src, (undef))))]>;
3248 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3249 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3250 [(set VR128:$dst, (rep_frag
3251 (memopv4f32 addr:$src), (undef)))]>;
3254 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3256 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3257 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3258 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3259 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3262 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3263 // FIXME: Merge above classes when we have patterns for the ymm version
3264 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3265 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3266 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3267 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3269 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3270 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3272 // Replicate Double FP
3273 multiclass sse3_replicate_dfp<string OpcodeStr> {
3274 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3275 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3276 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3277 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3278 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3280 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3284 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3285 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3286 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3288 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3289 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3293 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3294 // FIXME: Merge above classes when we have patterns for the ymm version
3295 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3296 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3298 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3300 // Move Unaligned Integer
3301 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3302 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3303 "vlddqu\t{$src, $dst|$dst, $src}",
3304 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3305 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3306 "vlddqu\t{$src, $dst|$dst, $src}", []>, VEX;
3308 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3309 "lddqu\t{$src, $dst|$dst, $src}",
3310 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3312 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3314 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3316 // Several Move patterns
3317 let AddedComplexity = 5 in {
3318 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3319 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3320 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3321 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3322 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3323 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3324 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3325 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3328 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3329 let AddedComplexity = 15 in
3330 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3331 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3332 let AddedComplexity = 20 in
3333 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3334 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3336 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3337 let AddedComplexity = 15 in
3338 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3339 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3340 let AddedComplexity = 20 in
3341 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3342 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3344 //===---------------------------------------------------------------------===//
3345 // SSE3 - Arithmetic
3346 //===---------------------------------------------------------------------===//
3348 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3349 X86MemOperand x86memop, bit Is2Addr = 1> {
3350 def rr : I<0xD0, MRMSrcReg,
3351 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3353 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3354 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3355 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3356 def rm : I<0xD0, MRMSrcMem,
3357 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3359 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3360 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3361 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3364 let isAsmParserOnly = 1, Predicates = [HasAVX],
3365 ExeDomain = SSEPackedDouble in {
3366 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3367 f128mem, 0>, XD, VEX_4V;
3368 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3369 f128mem, 0>, OpSize, VEX_4V;
3370 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3371 f256mem, 0>, XD, VEX_4V;
3372 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3373 f256mem, 0>, OpSize, VEX_4V;
3375 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3376 ExeDomain = SSEPackedDouble in {
3377 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3379 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3380 f128mem>, TB, OpSize;
3383 //===---------------------------------------------------------------------===//
3384 // SSE3 Instructions
3385 //===---------------------------------------------------------------------===//
3388 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3389 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3390 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3392 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3393 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3394 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3396 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3398 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3399 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3400 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3402 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3403 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3404 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3406 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3407 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3408 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3410 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3412 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3413 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3414 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3417 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3418 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3419 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3420 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3421 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3422 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3423 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3424 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3425 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3426 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3427 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3428 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3429 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3430 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3431 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3432 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3433 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3436 let Constraints = "$src1 = $dst" in {
3437 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3438 int_x86_sse3_hadd_ps>;
3439 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3440 int_x86_sse3_hadd_pd>;
3441 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3442 int_x86_sse3_hsub_ps>;
3443 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3444 int_x86_sse3_hsub_pd>;
3447 //===---------------------------------------------------------------------===//
3448 // SSSE3 - Packed Absolute Instructions
3449 //===---------------------------------------------------------------------===//
3451 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3452 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3453 PatFrag mem_frag64, PatFrag mem_frag128,
3454 Intrinsic IntId64, Intrinsic IntId128> {
3455 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3456 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3457 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3459 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3460 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3462 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3464 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3466 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3467 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3470 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3472 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3475 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3478 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3479 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3480 int_x86_ssse3_pabs_b,
3481 int_x86_ssse3_pabs_b_128>, VEX;
3482 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3483 int_x86_ssse3_pabs_w,
3484 int_x86_ssse3_pabs_w_128>, VEX;
3485 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3486 int_x86_ssse3_pabs_d,
3487 int_x86_ssse3_pabs_d_128>, VEX;
3490 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3491 int_x86_ssse3_pabs_b,
3492 int_x86_ssse3_pabs_b_128>;
3493 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3494 int_x86_ssse3_pabs_w,
3495 int_x86_ssse3_pabs_w_128>;
3496 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3497 int_x86_ssse3_pabs_d,
3498 int_x86_ssse3_pabs_d_128>;
3500 //===---------------------------------------------------------------------===//
3501 // SSSE3 - Packed Binary Operator Instructions
3502 //===---------------------------------------------------------------------===//
3504 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3505 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3506 PatFrag mem_frag64, PatFrag mem_frag128,
3507 Intrinsic IntId64, Intrinsic IntId128,
3509 let isCommutable = 1 in
3510 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3511 (ins VR64:$src1, VR64:$src2),
3513 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3514 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3515 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3516 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3517 (ins VR64:$src1, i64mem:$src2),
3519 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3520 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3522 (IntId64 VR64:$src1,
3523 (bitconvert (memopv8i8 addr:$src2))))]>;
3525 let isCommutable = 1 in
3526 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3527 (ins VR128:$src1, VR128:$src2),
3529 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3530 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3531 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3533 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3534 (ins VR128:$src1, i128mem:$src2),
3536 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3537 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3539 (IntId128 VR128:$src1,
3540 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3543 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3544 let isCommutable = 0 in {
3545 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3546 int_x86_ssse3_phadd_w,
3547 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3548 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3549 int_x86_ssse3_phadd_d,
3550 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3551 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3552 int_x86_ssse3_phadd_sw,
3553 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3554 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3555 int_x86_ssse3_phsub_w,
3556 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3557 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3558 int_x86_ssse3_phsub_d,
3559 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3560 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3561 int_x86_ssse3_phsub_sw,
3562 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3563 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3564 int_x86_ssse3_pmadd_ub_sw,
3565 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3566 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3567 int_x86_ssse3_pshuf_b,
3568 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3569 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3570 int_x86_ssse3_psign_b,
3571 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3572 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3573 int_x86_ssse3_psign_w,
3574 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3575 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3576 int_x86_ssse3_psign_d,
3577 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3579 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3580 int_x86_ssse3_pmul_hr_sw,
3581 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3584 // None of these have i8 immediate fields.
3585 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3586 let isCommutable = 0 in {
3587 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3588 int_x86_ssse3_phadd_w,
3589 int_x86_ssse3_phadd_w_128>;
3590 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3591 int_x86_ssse3_phadd_d,
3592 int_x86_ssse3_phadd_d_128>;
3593 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3594 int_x86_ssse3_phadd_sw,
3595 int_x86_ssse3_phadd_sw_128>;
3596 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3597 int_x86_ssse3_phsub_w,
3598 int_x86_ssse3_phsub_w_128>;
3599 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3600 int_x86_ssse3_phsub_d,
3601 int_x86_ssse3_phsub_d_128>;
3602 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3603 int_x86_ssse3_phsub_sw,
3604 int_x86_ssse3_phsub_sw_128>;
3605 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3606 int_x86_ssse3_pmadd_ub_sw,
3607 int_x86_ssse3_pmadd_ub_sw_128>;
3608 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3609 int_x86_ssse3_pshuf_b,
3610 int_x86_ssse3_pshuf_b_128>;
3611 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3612 int_x86_ssse3_psign_b,
3613 int_x86_ssse3_psign_b_128>;
3614 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3615 int_x86_ssse3_psign_w,
3616 int_x86_ssse3_psign_w_128>;
3617 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3618 int_x86_ssse3_psign_d,
3619 int_x86_ssse3_psign_d_128>;
3621 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3622 int_x86_ssse3_pmul_hr_sw,
3623 int_x86_ssse3_pmul_hr_sw_128>;
3626 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3627 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3628 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3629 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3631 //===---------------------------------------------------------------------===//
3632 // SSSE3 - Packed Align Instruction Patterns
3633 //===---------------------------------------------------------------------===//
3635 multiclass sse3_palign<string asm, bit Is2Addr = 1> {
3636 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3637 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3639 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3641 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3643 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3644 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3646 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3648 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3651 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3652 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3654 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3656 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3658 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3659 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3661 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3663 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3667 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3668 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3669 let Constraints = "$src1 = $dst" in
3670 defm PALIGN : sse3_palign<"palignr">;
3672 let AddedComplexity = 5 in {
3674 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3675 (PALIGNR64rr VR64:$src2, VR64:$src1,
3676 (SHUFFLE_get_palign_imm VR64:$src3))>,
3677 Requires<[HasSSSE3]>;
3678 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3679 (PALIGNR64rr VR64:$src2, VR64:$src1,
3680 (SHUFFLE_get_palign_imm VR64:$src3))>,
3681 Requires<[HasSSSE3]>;
3682 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3683 (PALIGNR64rr VR64:$src2, VR64:$src1,
3684 (SHUFFLE_get_palign_imm VR64:$src3))>,
3685 Requires<[HasSSSE3]>;
3686 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3687 (PALIGNR64rr VR64:$src2, VR64:$src1,
3688 (SHUFFLE_get_palign_imm VR64:$src3))>,
3689 Requires<[HasSSSE3]>;
3691 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3692 (PALIGNR128rr VR128:$src2, VR128:$src1,
3693 (SHUFFLE_get_palign_imm VR128:$src3))>,
3694 Requires<[HasSSSE3]>;
3695 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3696 (PALIGNR128rr VR128:$src2, VR128:$src1,
3697 (SHUFFLE_get_palign_imm VR128:$src3))>,
3698 Requires<[HasSSSE3]>;
3699 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3700 (PALIGNR128rr VR128:$src2, VR128:$src1,
3701 (SHUFFLE_get_palign_imm VR128:$src3))>,
3702 Requires<[HasSSSE3]>;
3703 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3704 (PALIGNR128rr VR128:$src2, VR128:$src1,
3705 (SHUFFLE_get_palign_imm VR128:$src3))>,
3706 Requires<[HasSSSE3]>;
3709 //===---------------------------------------------------------------------===//
3710 // SSSE3 Misc Instructions
3711 //===---------------------------------------------------------------------===//
3713 // Thread synchronization
3714 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3715 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3716 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3717 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3719 //===---------------------------------------------------------------------===//
3720 // Non-Instruction Patterns
3721 //===---------------------------------------------------------------------===//
3723 // extload f32 -> f64. This matches load+fextend because we have a hack in
3724 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3726 // Since these loads aren't folded into the fextend, we have to match it
3728 let Predicates = [HasSSE2] in
3729 def : Pat<(fextend (loadf32 addr:$src)),
3730 (CVTSS2SDrm addr:$src)>;
3733 let Predicates = [HasSSE2] in {
3734 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3735 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3736 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3737 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3738 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3739 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3740 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3741 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3742 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3743 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3744 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3745 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3746 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3747 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3748 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3749 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3750 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3751 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3752 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3753 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3754 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3755 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3756 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3757 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3758 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3759 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3760 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3761 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3762 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3763 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3766 // Move scalar to XMM zero-extended
3767 // movd to XMM register zero-extends
3768 let AddedComplexity = 15 in {
3769 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3770 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3771 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3772 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3773 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3774 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3775 (MOVSSrr (v4f32 (V_SET0PS)),
3776 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3777 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3778 (MOVSSrr (v4i32 (V_SET0PI)),
3779 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3782 // Splat v2f64 / v2i64
3783 let AddedComplexity = 10 in {
3784 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3785 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3786 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3787 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3788 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3789 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3790 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3791 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3794 // Special unary SHUFPSrri case.
3795 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3796 (SHUFPSrri VR128:$src1, VR128:$src1,
3797 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3798 let AddedComplexity = 5 in
3799 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3800 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3801 Requires<[HasSSE2]>;
3802 // Special unary SHUFPDrri case.
3803 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3804 (SHUFPDrri VR128:$src1, VR128:$src1,
3805 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3806 Requires<[HasSSE2]>;
3807 // Special unary SHUFPDrri case.
3808 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3809 (SHUFPDrri VR128:$src1, VR128:$src1,
3810 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3811 Requires<[HasSSE2]>;
3812 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3813 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3814 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3815 Requires<[HasSSE2]>;
3817 // Special binary v4i32 shuffle cases with SHUFPS.
3818 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3819 (SHUFPSrri VR128:$src1, VR128:$src2,
3820 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3821 Requires<[HasSSE2]>;
3822 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3823 (SHUFPSrmi VR128:$src1, addr:$src2,
3824 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3825 Requires<[HasSSE2]>;
3826 // Special binary v2i64 shuffle cases using SHUFPDrri.
3827 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3828 (SHUFPDrri VR128:$src1, VR128:$src2,
3829 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3830 Requires<[HasSSE2]>;
3832 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3833 let AddedComplexity = 15 in {
3834 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3835 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3836 Requires<[OptForSpeed, HasSSE2]>;
3837 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3838 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3839 Requires<[OptForSpeed, HasSSE2]>;
3841 let AddedComplexity = 10 in {
3842 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3843 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3844 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3845 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3846 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3847 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3848 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3849 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3852 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3853 let AddedComplexity = 15 in {
3854 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3855 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3856 Requires<[OptForSpeed, HasSSE2]>;
3857 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3858 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3859 Requires<[OptForSpeed, HasSSE2]>;
3861 let AddedComplexity = 10 in {
3862 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3863 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3864 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3865 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3866 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3867 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3868 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3869 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3872 let AddedComplexity = 20 in {
3873 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3874 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3875 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3877 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3878 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3879 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3881 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3882 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3883 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3884 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3885 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3888 let AddedComplexity = 20 in {
3889 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3890 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3891 (MOVLPSrm VR128:$src1, addr:$src2)>;
3892 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3893 (MOVLPDrm VR128:$src1, addr:$src2)>;
3894 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3895 (MOVLPSrm VR128:$src1, addr:$src2)>;
3896 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3897 (MOVLPDrm VR128:$src1, addr:$src2)>;
3900 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3901 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3902 (MOVLPSmr addr:$src1, VR128:$src2)>;
3903 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3904 (MOVLPDmr addr:$src1, VR128:$src2)>;
3905 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3907 (MOVLPSmr addr:$src1, VR128:$src2)>;
3908 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3909 (MOVLPDmr addr:$src1, VR128:$src2)>;
3911 let AddedComplexity = 15 in {
3912 // Setting the lowest element in the vector.
3913 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3914 (MOVSSrr (v4i32 VR128:$src1),
3915 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3916 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3917 (MOVSDrr (v2i64 VR128:$src1),
3918 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3920 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3921 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3922 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3923 Requires<[HasSSE2]>;
3924 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3925 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3926 Requires<[HasSSE2]>;
3929 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3930 // fall back to this for SSE1)
3931 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3932 (SHUFPSrri VR128:$src2, VR128:$src1,
3933 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3935 // Set lowest element and zero upper elements.
3936 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3937 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3939 // Some special case pandn patterns.
3940 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3942 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3943 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3945 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3946 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3948 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3950 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3951 (memop addr:$src2))),
3952 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3953 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3954 (memop addr:$src2))),
3955 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3956 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3957 (memop addr:$src2))),
3958 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3960 // vector -> vector casts
3961 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3962 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3963 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3964 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3965 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3966 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3967 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3968 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3970 // Use movaps / movups for SSE integer load / store (one byte shorter).
3971 def : Pat<(alignedloadv4i32 addr:$src),
3972 (MOVAPSrm addr:$src)>;
3973 def : Pat<(loadv4i32 addr:$src),
3974 (MOVUPSrm addr:$src)>;
3975 def : Pat<(alignedloadv2i64 addr:$src),
3976 (MOVAPSrm addr:$src)>;
3977 def : Pat<(loadv2i64 addr:$src),
3978 (MOVUPSrm addr:$src)>;
3980 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3981 (MOVAPSmr addr:$dst, VR128:$src)>;
3982 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3983 (MOVAPSmr addr:$dst, VR128:$src)>;
3984 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3985 (MOVAPSmr addr:$dst, VR128:$src)>;
3986 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3987 (MOVAPSmr addr:$dst, VR128:$src)>;
3988 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3989 (MOVUPSmr addr:$dst, VR128:$src)>;
3990 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3991 (MOVUPSmr addr:$dst, VR128:$src)>;
3992 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3993 (MOVUPSmr addr:$dst, VR128:$src)>;
3994 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3995 (MOVUPSmr addr:$dst, VR128:$src)>;
3997 //===----------------------------------------------------------------------===//
3998 // SSE4.1 - Packed Move with Sign/Zero Extend
3999 //===----------------------------------------------------------------------===//
4001 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4002 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4003 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4004 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4006 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4007 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4009 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
4013 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4014 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
4016 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
4018 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
4020 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
4022 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
4024 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
4028 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
4029 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
4030 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
4031 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
4032 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
4033 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
4035 // Common patterns involving scalar load.
4036 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
4037 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4038 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
4039 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
4041 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
4042 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4043 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
4044 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
4046 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
4047 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4048 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
4049 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
4051 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
4052 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4053 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
4054 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
4056 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
4057 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4058 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
4059 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
4061 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
4062 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4063 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
4064 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
4067 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4068 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4069 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4070 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4072 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4073 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4075 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
4079 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4080 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
4082 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
4084 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
4086 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
4090 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
4091 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
4092 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
4093 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
4095 // Common patterns involving scalar load
4096 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
4097 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
4098 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
4099 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
4101 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
4102 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
4103 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
4104 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
4107 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4108 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4109 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4110 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
4112 // Expecting a i16 load any extended to i32 value.
4113 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
4114 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4115 [(set VR128:$dst, (IntId (bitconvert
4116 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
4120 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4121 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
4123 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
4126 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
4127 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
4129 // Common patterns involving scalar load
4130 def : Pat<(int_x86_sse41_pmovsxbq
4131 (bitconvert (v4i32 (X86vzmovl
4132 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4133 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4135 def : Pat<(int_x86_sse41_pmovzxbq
4136 (bitconvert (v4i32 (X86vzmovl
4137 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4138 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4140 //===----------------------------------------------------------------------===//
4141 // SSE4.1 - Extract Instructions
4142 //===----------------------------------------------------------------------===//
4144 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4145 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4146 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4147 (ins VR128:$src1, i32i8imm:$src2),
4148 !strconcat(OpcodeStr,
4149 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4150 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4152 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4153 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4154 !strconcat(OpcodeStr,
4155 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4158 // There's an AssertZext in the way of writing the store pattern
4159 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4162 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4163 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4164 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4165 (ins VR128:$src1, i32i8imm:$src2),
4166 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4169 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4172 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4173 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4174 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4175 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4176 !strconcat(OpcodeStr,
4177 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4180 // There's an AssertZext in the way of writing the store pattern
4181 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4184 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4185 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4187 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4190 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4191 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4192 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4193 (ins VR128:$src1, i32i8imm:$src2),
4194 !strconcat(OpcodeStr,
4195 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4197 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4198 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4199 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4200 !strconcat(OpcodeStr,
4201 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4202 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4203 addr:$dst)]>, OpSize;
4206 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4207 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4209 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4211 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4212 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4213 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4214 (ins VR128:$src1, i32i8imm:$src2),
4215 !strconcat(OpcodeStr,
4216 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4218 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4219 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4220 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4221 !strconcat(OpcodeStr,
4222 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4223 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4224 addr:$dst)]>, OpSize, REX_W;
4227 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4228 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4230 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4232 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4234 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4235 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4236 (ins VR128:$src1, i32i8imm:$src2),
4237 !strconcat(OpcodeStr,
4238 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4240 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4242 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4243 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4244 !strconcat(OpcodeStr,
4245 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4246 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4247 addr:$dst)]>, OpSize;
4250 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4251 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4252 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4253 (ins VR128:$src1, i32i8imm:$src2),
4254 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4257 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4259 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4260 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4263 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4264 Requires<[HasSSE41]>;
4266 //===----------------------------------------------------------------------===//
4267 // SSE4.1 - Insert Instructions
4268 //===----------------------------------------------------------------------===//
4270 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4271 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4272 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4274 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4276 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4278 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4279 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4280 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4282 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4284 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4286 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4287 imm:$src3))]>, OpSize;
4290 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4291 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4292 let Constraints = "$src1 = $dst" in
4293 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4295 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4296 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4297 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4299 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4301 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4303 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4305 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4306 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4308 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4310 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4312 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4313 imm:$src3)))]>, OpSize;
4316 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4317 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4318 let Constraints = "$src1 = $dst" in
4319 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4321 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4322 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4323 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4325 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4327 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4329 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4331 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4332 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4334 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4336 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4338 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4339 imm:$src3)))]>, OpSize;
4342 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4343 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4344 let Constraints = "$src1 = $dst" in
4345 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4347 // insertps has a few different modes, there's the first two here below which
4348 // are optimized inserts that won't zero arbitrary elements in the destination
4349 // vector. The next one matches the intrinsic and could zero arbitrary elements
4350 // in the target vector.
4351 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4352 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4353 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4355 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4357 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4359 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4361 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4362 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4364 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4366 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4368 (X86insrtps VR128:$src1,
4369 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4370 imm:$src3))]>, OpSize;
4373 let Constraints = "$src1 = $dst" in
4374 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4375 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4376 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4378 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4379 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4381 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4382 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4383 Requires<[HasSSE41]>;
4385 //===----------------------------------------------------------------------===//
4386 // SSE4.1 - Round Instructions
4387 //===----------------------------------------------------------------------===//
4389 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4390 X86MemOperand x86memop, RegisterClass RC,
4391 PatFrag mem_frag32, PatFrag mem_frag64,
4392 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4393 // Intrinsic operation, reg.
4394 // Vector intrinsic operation, reg
4395 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
4396 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4397 !strconcat(OpcodeStr,
4398 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4399 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4402 // Vector intrinsic operation, mem
4403 def PSm_Int : Ii8<opcps, MRMSrcMem,
4404 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4405 !strconcat(OpcodeStr,
4406 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4408 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4410 Requires<[HasSSE41]>;
4412 // Vector intrinsic operation, reg
4413 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
4414 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4415 !strconcat(OpcodeStr,
4416 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4417 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4420 // Vector intrinsic operation, mem
4421 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
4422 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4423 !strconcat(OpcodeStr,
4424 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4426 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4430 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4431 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4432 // Intrinsic operation, reg.
4433 // Vector intrinsic operation, reg
4434 def PSr : SS4AIi8<opcps, MRMSrcReg,
4435 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4436 !strconcat(OpcodeStr,
4437 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4440 // Vector intrinsic operation, mem
4441 def PSm : Ii8<opcps, MRMSrcMem,
4442 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4443 !strconcat(OpcodeStr,
4444 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4445 []>, TA, OpSize, Requires<[HasSSE41]>;
4447 // Vector intrinsic operation, reg
4448 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4449 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4450 !strconcat(OpcodeStr,
4451 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4454 // Vector intrinsic operation, mem
4455 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4456 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4457 !strconcat(OpcodeStr,
4458 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4462 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4465 Intrinsic F64Int, bit Is2Addr = 1> {
4466 // Intrinsic operation, reg.
4467 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
4468 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4470 !strconcat(OpcodeStr,
4471 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4472 !strconcat(OpcodeStr,
4473 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4474 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4477 // Intrinsic operation, mem.
4478 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
4479 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4481 !strconcat(OpcodeStr,
4482 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4483 !strconcat(OpcodeStr,
4484 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4486 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4489 // Intrinsic operation, reg.
4490 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
4491 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4493 !strconcat(OpcodeStr,
4494 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4495 !strconcat(OpcodeStr,
4496 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4497 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4500 // Intrinsic operation, mem.
4501 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
4502 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4504 !strconcat(OpcodeStr,
4505 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4506 !strconcat(OpcodeStr,
4507 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4509 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4513 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4515 // Intrinsic operation, reg.
4516 def SSr : SS4AIi8<opcss, MRMSrcReg,
4517 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4518 !strconcat(OpcodeStr,
4519 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4522 // Intrinsic operation, mem.
4523 def SSm : SS4AIi8<opcss, MRMSrcMem,
4524 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4525 !strconcat(OpcodeStr,
4526 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4529 // Intrinsic operation, reg.
4530 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4531 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4532 !strconcat(OpcodeStr,
4533 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4536 // Intrinsic operation, mem.
4537 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4538 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4539 !strconcat(OpcodeStr,
4540 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4544 // FP round - roundss, roundps, roundsd, roundpd
4545 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4547 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4548 memopv4f32, memopv2f64,
4549 int_x86_sse41_round_ps,
4550 int_x86_sse41_round_pd>, VEX;
4551 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4552 memopv8f32, memopv4f64,
4553 int_x86_avx_round_ps_256,
4554 int_x86_avx_round_pd_256>, VEX;
4555 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4556 int_x86_sse41_round_ss,
4557 int_x86_sse41_round_sd, 0>, VEX_4V;
4559 // Instructions for the assembler
4560 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4562 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4564 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4567 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4568 memopv4f32, memopv2f64,
4569 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4570 let Constraints = "$src1 = $dst" in
4571 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4572 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4574 //===----------------------------------------------------------------------===//
4575 // SSE4.1 - Packed Bit Test
4576 //===----------------------------------------------------------------------===//
4578 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4579 // the intel intrinsic that corresponds to this.
4580 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4581 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4582 "vptest\t{$src2, $src1|$src1, $src2}",
4583 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4585 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4586 "vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
4588 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4589 "vptest\t{$src2, $src1|$src1, $src2}",
4590 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4592 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4593 "vptest\t{$src2, $src1|$src1, $src2}", []>, OpSize, VEX;
4596 let Defs = [EFLAGS] in {
4597 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4598 "ptest \t{$src2, $src1|$src1, $src2}",
4599 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4601 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4602 "ptest \t{$src2, $src1|$src1, $src2}",
4603 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4607 // The bit test instructions below are AVX only
4608 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4609 X86MemOperand x86memop> {
4610 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4613 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4618 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4619 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem>;
4620 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem>;
4621 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem>;
4622 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem>;
4625 //===----------------------------------------------------------------------===//
4626 // SSE4.1 - Misc Instructions
4627 //===----------------------------------------------------------------------===//
4629 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4630 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4631 Intrinsic IntId128> {
4632 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4634 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4635 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4636 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4638 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4641 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4644 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4645 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4646 int_x86_sse41_phminposuw>, VEX;
4647 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4648 int_x86_sse41_phminposuw>;
4650 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4651 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4652 Intrinsic IntId128, bit Is2Addr = 1> {
4653 let isCommutable = 1 in
4654 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4655 (ins VR128:$src1, VR128:$src2),
4657 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4658 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4659 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4660 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4661 (ins VR128:$src1, i128mem:$src2),
4663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4666 (IntId128 VR128:$src1,
4667 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4670 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4671 let isCommutable = 0 in
4672 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4674 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4676 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4678 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4680 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4682 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4684 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4686 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4688 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4690 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4692 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4696 let Constraints = "$src1 = $dst" in {
4697 let isCommutable = 0 in
4698 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4699 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4700 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4701 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4702 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4703 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4704 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4705 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4706 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4707 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4708 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4711 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4712 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4713 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4714 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4716 /// SS48I_binop_rm - Simple SSE41 binary operator.
4717 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4718 ValueType OpVT, bit Is2Addr = 1> {
4719 let isCommutable = 1 in
4720 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4721 (ins VR128:$src1, VR128:$src2),
4723 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4724 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4725 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4727 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4728 (ins VR128:$src1, i128mem:$src2),
4730 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4731 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4732 [(set VR128:$dst, (OpNode VR128:$src1,
4733 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4737 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4738 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4739 let Constraints = "$src1 = $dst" in
4740 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4742 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4743 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4744 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4745 X86MemOperand x86memop, bit Is2Addr = 1> {
4746 let isCommutable = 1 in
4747 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4748 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4750 !strconcat(OpcodeStr,
4751 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4752 !strconcat(OpcodeStr,
4753 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4754 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4756 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4757 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4759 !strconcat(OpcodeStr,
4760 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4761 !strconcat(OpcodeStr,
4762 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4765 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4769 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4770 let isCommutable = 0 in {
4771 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4772 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4773 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4774 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4775 let Pattern = []<dag> in {
4776 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4777 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4778 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4779 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4781 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4782 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4783 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4784 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4786 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4787 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4788 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4789 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4790 let Pattern = []<dag> in
4791 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4792 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4795 let Constraints = "$src1 = $dst" in {
4796 let isCommutable = 0 in {
4797 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4798 VR128, memopv16i8, i128mem>;
4799 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4800 VR128, memopv16i8, i128mem>;
4801 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4802 VR128, memopv16i8, i128mem>;
4803 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4804 VR128, memopv16i8, i128mem>;
4806 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4807 VR128, memopv16i8, i128mem>;
4808 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4809 VR128, memopv16i8, i128mem>;
4812 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4813 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4814 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4815 RegisterClass RC, X86MemOperand x86memop,
4816 PatFrag mem_frag, Intrinsic IntId> {
4817 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4818 (ins RC:$src1, RC:$src2, RC:$src3),
4819 !strconcat(OpcodeStr,
4820 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4821 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4822 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4824 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4825 (ins RC:$src1, x86memop:$src2, RC:$src3),
4826 !strconcat(OpcodeStr,
4827 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4829 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4831 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4835 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4836 memopv16i8, int_x86_sse41_blendvpd>;
4837 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4838 memopv16i8, int_x86_sse41_blendvps>;
4839 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4840 memopv16i8, int_x86_sse41_pblendvb>;
4842 let Pattern = []<dag> in { // FIXME: implement 256 intrinsics here.
4843 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4844 memopv32i8, int_x86_sse41_blendvpd>;
4845 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4846 memopv32i8, int_x86_sse41_blendvps>;
4849 /// SS41I_ternary_int - SSE 4.1 ternary operator
4850 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4851 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4852 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4853 (ins VR128:$src1, VR128:$src2),
4854 !strconcat(OpcodeStr,
4855 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4856 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4859 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4860 (ins VR128:$src1, i128mem:$src2),
4861 !strconcat(OpcodeStr,
4862 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4865 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4869 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4870 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4871 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4873 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4874 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4875 "vmovntdqa\t{$src, $dst|$dst, $src}",
4876 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4878 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4879 "movntdqa\t{$src, $dst|$dst, $src}",
4880 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4883 //===----------------------------------------------------------------------===//
4884 // SSE4.2 - Compare Instructions
4885 //===----------------------------------------------------------------------===//
4887 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4888 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4889 Intrinsic IntId128, bit Is2Addr = 1> {
4890 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4891 (ins VR128:$src1, VR128:$src2),
4893 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4894 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4895 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4897 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4898 (ins VR128:$src1, i128mem:$src2),
4900 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4901 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4903 (IntId128 VR128:$src1,
4904 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4907 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4908 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4910 let Constraints = "$src1 = $dst" in
4911 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4913 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4914 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4915 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4916 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4918 //===----------------------------------------------------------------------===//
4919 // SSE4.2 - String/text Processing Instructions
4920 //===----------------------------------------------------------------------===//
4922 // Packed Compare Implicit Length Strings, Return Mask
4923 multiclass pseudo_pcmpistrm<string asm> {
4924 def REG : Ii8<0, Pseudo, (outs VR128:$dst),
4925 (ins VR128:$src1, VR128:$src2, i8imm:$src3), !strconcat(asm, "rr PSEUDO"),
4926 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4928 def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
4929 (ins VR128:$src1, i128mem:$src2, i8imm:$src3), !strconcat(asm, "rm PSEUDO"),
4930 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4931 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4934 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4935 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4936 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4939 let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
4940 Predicates = [HasAVX] in {
4941 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4942 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4943 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4944 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4945 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4946 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4949 let Defs = [XMM0, EFLAGS] in {
4950 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4951 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4952 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4953 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4954 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4955 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4958 // Packed Compare Explicit Length Strings, Return Mask
4959 multiclass pseudo_pcmpestrm<string asm> {
4960 def REG : Ii8<0, Pseudo, (outs VR128:$dst),
4961 (ins VR128:$src1, VR128:$src3, i8imm:$src5), !strconcat(asm, "rr PSEUDO"),
4962 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4963 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4964 def MEM : Ii8<0, Pseudo, (outs VR128:$dst),
4965 (ins VR128:$src1, i128mem:$src3, i8imm:$src5), !strconcat(asm, "rm PSEUDO"),
4966 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4967 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4970 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4971 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4972 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4975 let isAsmParserOnly = 1, Predicates = [HasAVX],
4976 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4977 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4978 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4979 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4980 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4981 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4982 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4985 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4986 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4987 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4988 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4989 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4990 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4991 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4994 // Packed Compare Implicit Length Strings, Return Index
4995 let Defs = [ECX, EFLAGS] in {
4996 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4997 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4998 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4999 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5000 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
5001 (implicit EFLAGS)]>, OpSize;
5002 def rm : SS42AI<0x63, MRMSrcMem, (outs),
5003 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5004 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
5005 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
5006 (implicit EFLAGS)]>, OpSize;
5010 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5011 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
5013 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
5015 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
5017 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
5019 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
5021 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
5025 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
5026 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
5027 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
5028 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
5029 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
5030 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
5032 // Packed Compare Explicit Length Strings, Return Index
5033 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
5034 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
5035 def rr : SS42AI<0x61, MRMSrcReg, (outs),
5036 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
5037 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5038 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
5039 (implicit EFLAGS)]>, OpSize;
5040 def rm : SS42AI<0x61, MRMSrcMem, (outs),
5041 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
5042 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
5044 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
5045 (implicit EFLAGS)]>, OpSize;
5049 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
5050 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
5052 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
5054 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
5056 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
5058 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
5060 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
5064 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
5065 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
5066 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
5067 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
5068 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
5069 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
5071 //===----------------------------------------------------------------------===//
5072 // SSE4.2 - CRC Instructions
5073 //===----------------------------------------------------------------------===//
5075 // No CRC instructions have AVX equivalents
5077 // crc intrinsic instruction
5078 // This set of instructions are only rm, the only difference is the size
5080 let Constraints = "$src1 = $dst" in {
5081 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
5082 (ins GR32:$src1, i8mem:$src2),
5083 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5085 (int_x86_sse42_crc32_8 GR32:$src1,
5086 (load addr:$src2)))]>;
5087 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
5088 (ins GR32:$src1, GR8:$src2),
5089 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5091 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
5092 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5093 (ins GR32:$src1, i16mem:$src2),
5094 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5096 (int_x86_sse42_crc32_16 GR32:$src1,
5097 (load addr:$src2)))]>,
5099 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5100 (ins GR32:$src1, GR16:$src2),
5101 "crc32{w} \t{$src2, $src1|$src1, $src2}",
5103 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
5105 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5106 (ins GR32:$src1, i32mem:$src2),
5107 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5109 (int_x86_sse42_crc32_32 GR32:$src1,
5110 (load addr:$src2)))]>;
5111 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5112 (ins GR32:$src1, GR32:$src2),
5113 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5115 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
5116 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5117 (ins GR64:$src1, i8mem:$src2),
5118 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5120 (int_x86_sse42_crc64_8 GR64:$src1,
5121 (load addr:$src2)))]>,
5123 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5124 (ins GR64:$src1, GR8:$src2),
5125 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5127 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
5129 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5130 (ins GR64:$src1, i64mem:$src2),
5131 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5133 (int_x86_sse42_crc64_64 GR64:$src1,
5134 (load addr:$src2)))]>,
5136 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5137 (ins GR64:$src1, GR64:$src2),
5138 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5140 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
5144 //===----------------------------------------------------------------------===//
5145 // AES-NI Instructions
5146 //===----------------------------------------------------------------------===//
5148 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5149 Intrinsic IntId128, bit Is2Addr = 1> {
5150 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5151 (ins VR128:$src1, VR128:$src2),
5153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5155 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5157 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5158 (ins VR128:$src1, i128mem:$src2),
5160 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5161 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5163 (IntId128 VR128:$src1,
5164 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5167 // Perform One Round of an AES Encryption/Decryption Flow
5168 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5169 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5170 int_x86_aesni_aesenc, 0>, VEX_4V;
5171 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5172 int_x86_aesni_aesenclast, 0>, VEX_4V;
5173 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5174 int_x86_aesni_aesdec, 0>, VEX_4V;
5175 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5176 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5179 let Constraints = "$src1 = $dst" in {
5180 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5181 int_x86_aesni_aesenc>;
5182 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5183 int_x86_aesni_aesenclast>;
5184 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5185 int_x86_aesni_aesdec>;
5186 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5187 int_x86_aesni_aesdeclast>;
5190 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5191 (AESENCrr VR128:$src1, VR128:$src2)>;
5192 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5193 (AESENCrm VR128:$src1, addr:$src2)>;
5194 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5195 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5196 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5197 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5198 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5199 (AESDECrr VR128:$src1, VR128:$src2)>;
5200 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5201 (AESDECrm VR128:$src1, addr:$src2)>;
5202 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5203 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5204 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5205 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5207 // Perform the AES InvMixColumn Transformation
5208 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5209 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5211 "vaesimc\t{$src1, $dst|$dst, $src1}",
5213 (int_x86_aesni_aesimc VR128:$src1))]>,
5215 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5216 (ins i128mem:$src1),
5217 "vaesimc\t{$src1, $dst|$dst, $src1}",
5219 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5222 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5224 "aesimc\t{$src1, $dst|$dst, $src1}",
5226 (int_x86_aesni_aesimc VR128:$src1))]>,
5228 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5229 (ins i128mem:$src1),
5230 "aesimc\t{$src1, $dst|$dst, $src1}",
5232 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5235 // AES Round Key Generation Assist
5236 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
5237 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5238 (ins VR128:$src1, i8imm:$src2),
5239 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5241 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5243 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5244 (ins i128mem:$src1, i8imm:$src2),
5245 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5247 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5251 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5252 (ins VR128:$src1, i8imm:$src2),
5253 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5255 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5257 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5258 (ins i128mem:$src1, i8imm:$src2),
5259 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5261 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5265 //===----------------------------------------------------------------------===//
5266 // CLMUL Instructions
5267 //===----------------------------------------------------------------------===//
5269 // Only the AVX version of CLMUL instructions are described here.
5271 // Carry-less Multiplication instructions
5272 let isAsmParserOnly = 1 in {
5273 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5274 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5275 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5278 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5279 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5280 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5284 multiclass avx_vpclmul<string asm> {
5285 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5286 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5289 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5290 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5293 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5294 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5295 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5296 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5298 } // isAsmParserOnly
5300 //===----------------------------------------------------------------------===//
5302 //===----------------------------------------------------------------------===//
5304 let isAsmParserOnly = 1 in {
5306 // Load from memory and broadcast to all elements of the destination operand
5307 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5308 X86MemOperand x86memop> :
5309 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5310 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>, VEX;
5312 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem>;
5313 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem>;
5314 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem>;
5315 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem>;
5317 // Insert packed floating-point values
5318 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5319 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5320 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5322 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5323 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5324 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5327 // Extract packed floating-point values
5328 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5329 (ins VR256:$src1, i8imm:$src2),
5330 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5332 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5333 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5334 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5337 // Conditional SIMD Packed Loads and Stores
5338 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr> {
5339 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5340 (ins VR128:$src1, f128mem:$src2),
5341 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5343 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5344 (ins VR256:$src1, f256mem:$src2),
5345 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5347 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5348 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5349 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5351 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5352 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5353 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5357 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps">;
5358 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd">;
5360 // Permute Floating-Point Values
5361 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5362 RegisterClass RC, X86MemOperand x86memop_f,
5363 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5364 Intrinsic IntVar, Intrinsic IntImm> {
5365 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5366 (ins RC:$src1, RC:$src2),
5367 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5368 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5369 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5370 (ins RC:$src1, x86memop_i:$src2),
5371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5372 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5374 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5375 (ins RC:$src1, i8imm:$src2),
5376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5377 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5378 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5379 (ins x86memop_f:$src1, i8imm:$src2),
5380 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5381 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5384 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5385 memopv4f32, memopv4i32,
5386 int_x86_avx_vpermilvar_ps,
5387 int_x86_avx_vpermil_ps>;
5388 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5389 memopv8f32, memopv8i32,
5390 int_x86_avx_vpermilvar_ps_256,
5391 int_x86_avx_vpermil_ps_256>;
5392 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5393 memopv2f64, memopv2i64,
5394 int_x86_avx_vpermilvar_pd,
5395 int_x86_avx_vpermil_pd>;
5396 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5397 memopv4f64, memopv4i64,
5398 int_x86_avx_vpermilvar_pd_256,
5399 int_x86_avx_vpermil_pd_256>;
5401 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5402 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5403 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5405 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5406 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5407 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5410 // Zero All YMM registers
5411 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L,
5414 // Zero Upper bits of YMM registers
5415 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX,
5418 } // isAsmParserOnly
5420 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5421 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5422 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5423 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5424 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5425 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5427 def : Pat<(int_x86_avx_vperm2f128_ps_256
5428 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5429 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5430 def : Pat<(int_x86_avx_vperm2f128_pd_256
5431 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5432 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5433 def : Pat<(int_x86_avx_vperm2f128_si_256
5434 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5435 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;