1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
246 let isCommutable = 1 in {
247 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
249 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
250 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
251 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>,
252 Sched<[itins.Sched]>;
254 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
257 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
258 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>,
259 Sched<[itins.Sched.Folded, ReadAfterLd]>;
262 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
263 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
264 string asm, string SSEVer, string FPSizeStr,
265 Operand memopr, ComplexPattern mem_cpat,
268 let isCodeGenOnly = 1 in {
269 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
271 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
272 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
273 [(set RC:$dst, (!cast<Intrinsic>(
274 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
275 RC:$src1, RC:$src2))], itins.rr>,
276 Sched<[itins.Sched]>;
277 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
279 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
280 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
281 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
282 SSEVer, "_", OpcodeStr, FPSizeStr))
283 RC:$src1, mem_cpat:$src2))], itins.rm>,
284 Sched<[itins.Sched.Folded, ReadAfterLd]>;
288 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
289 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
290 RegisterClass RC, ValueType vt,
291 X86MemOperand x86memop, PatFrag mem_frag,
292 Domain d, OpndItins itins, bit Is2Addr = 1> {
293 let isCommutable = 1 in
294 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
296 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
297 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
298 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
299 Sched<[itins.Sched]>;
301 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
303 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
304 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
305 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
307 Sched<[itins.Sched.Folded, ReadAfterLd]>;
310 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
311 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
312 string OpcodeStr, X86MemOperand x86memop,
313 list<dag> pat_rr, list<dag> pat_rm,
315 let isCommutable = 1, hasSideEffects = 0 in
316 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
318 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
319 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
320 pat_rr, NoItinerary, d>,
321 Sched<[WriteVecLogic]>;
322 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
324 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
325 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
326 pat_rm, NoItinerary, d>,
327 Sched<[WriteVecLogicLd, ReadAfterLd]>;
330 //===----------------------------------------------------------------------===//
331 // Non-instruction patterns
332 //===----------------------------------------------------------------------===//
334 // A vector extract of the first f32/f64 position is a subregister copy
335 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
337 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
338 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
340 // A 128-bit subvector extract from the first 256-bit vector position
341 // is a subregister copy that needs no instruction.
342 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
343 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
344 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
345 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
347 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
348 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
349 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
350 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
352 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
353 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
354 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
355 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
357 // A 128-bit subvector insert to the first 256-bit vector position
358 // is a subregister copy that needs no instruction.
359 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
360 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
370 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
371 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
374 // Implicitly promote a 32-bit scalar to a vector.
375 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
378 (COPY_TO_REGCLASS FR32:$src, VR128)>;
379 // Implicitly promote a 64-bit scalar to a vector.
380 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
382 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
383 (COPY_TO_REGCLASS FR64:$src, VR128)>;
385 // Bitcasts between 128-bit vector types. Return the original type since
386 // no instruction is needed for the conversion
387 let Predicates = [HasSSE2] in {
388 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
392 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
397 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
402 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
407 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
412 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
416 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
417 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
420 // Bitcasts between 256-bit vector types. Return the original type since
421 // no instruction is needed for the conversion
422 let Predicates = [HasAVX] in {
423 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
427 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
432 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
437 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
442 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
447 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
451 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
452 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
455 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
456 // This is expanded by ExpandPostRAPseudos.
457 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
458 isPseudo = 1, SchedRW = [WriteZero] in {
459 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
460 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
461 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
462 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
465 //===----------------------------------------------------------------------===//
466 // AVX & SSE - Zero/One Vectors
467 //===----------------------------------------------------------------------===//
469 // Alias instruction that maps zero vector to pxor / xorp* for sse.
470 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
471 // swizzled by ExecutionDepsFix to pxor.
472 // We set canFoldAsLoad because this can be converted to a constant-pool
473 // load of an all-zeros value if folding it would be beneficial.
474 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
475 isPseudo = 1, SchedRW = [WriteZero] in {
476 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
477 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
480 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
482 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
483 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
484 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
487 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
488 // and doesn't need it because on sandy bridge the register is set to zero
489 // at the rename stage without using any execution unit, so SET0PSY
490 // and SET0PDY can be used for vector int instructions without penalty
491 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
492 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
493 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
494 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
497 let Predicates = [HasAVX] in
498 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
500 let Predicates = [HasAVX2] in {
501 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
503 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
504 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
507 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
508 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
509 let Predicates = [HasAVX1Only] in {
510 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
511 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
512 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
514 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
515 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
516 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
518 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
519 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
520 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
522 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
523 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
524 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
527 // We set canFoldAsLoad because this can be converted to a constant-pool
528 // load of an all-ones value if folding it would be beneficial.
529 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
530 isPseudo = 1, SchedRW = [WriteZero] in {
531 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
532 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
533 let Predicates = [HasAVX2] in
534 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
535 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
539 //===----------------------------------------------------------------------===//
540 // SSE 1 & 2 - Move FP Scalar Instructions
542 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
543 // register copies because it's a partial register update; Register-to-register
544 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
545 // that the insert be implementable in terms of a copy, and just mentioned, we
546 // don't use movss/movsd for copies.
547 //===----------------------------------------------------------------------===//
549 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
550 X86MemOperand x86memop, string base_opc,
552 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
553 (ins VR128:$src1, RC:$src2),
554 !strconcat(base_opc, asm_opr),
555 [(set VR128:$dst, (vt (OpNode VR128:$src1,
556 (scalar_to_vector RC:$src2))))],
557 IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
559 // For the disassembler
560 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
561 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
562 (ins VR128:$src1, RC:$src2),
563 !strconcat(base_opc, asm_opr),
564 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
567 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
568 X86MemOperand x86memop, string OpcodeStr> {
570 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
571 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
574 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
575 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
576 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
577 VEX, VEX_LIG, Sched<[WriteStore]>;
579 let Constraints = "$src1 = $dst" in {
580 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
581 "\t{$src2, $dst|$dst, $src2}">;
584 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
586 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
590 // Loading from memory automatically zeroing upper bits.
591 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
592 PatFrag mem_pat, string OpcodeStr> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss">, XS;
604 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd">, XD;
606 let canFoldAsLoad = 1, isReMaterializable = 1 in {
607 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
609 let AddedComplexity = 20 in
610 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
614 let Predicates = [UseAVX] in {
615 let AddedComplexity = 15 in {
616 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
617 // MOVS{S,D} to the lower bits.
618 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
619 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
620 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
621 (VMOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
622 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
623 (VMOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
624 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
625 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
627 // Move low f32 and clear high bits.
628 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
629 (SUBREG_TO_REG (i32 0),
630 (VMOVSSrr (v4f32 (V_SET0)),
631 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm)), sub_xmm)>;
632 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
633 (SUBREG_TO_REG (i32 0),
634 (VMOVSSrr (v4i32 (V_SET0)),
635 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm)), sub_xmm)>;
638 let AddedComplexity = 20 in {
639 // MOVSSrm zeros the high parts of the register; represent this
640 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
641 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
642 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
643 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
644 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
645 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
646 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
648 // MOVSDrm zeros the high parts of the register; represent this
649 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
650 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
651 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
652 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
653 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
654 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
655 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
656 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
657 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
658 def : Pat<(v2f64 (X86vzload addr:$src)),
659 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
661 // Represent the same patterns above but in the form they appear for
663 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
664 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
665 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
666 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
667 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
668 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
669 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
670 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
671 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
673 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
674 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
675 (SUBREG_TO_REG (i32 0),
676 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
678 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
679 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
680 (SUBREG_TO_REG (i64 0),
681 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
683 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
684 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
685 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_xmm)>;
687 // Move low f64 and clear high bits.
688 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
689 (SUBREG_TO_REG (i32 0),
690 (VMOVSDrr (v2f64 (V_SET0)),
691 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm)), sub_xmm)>;
693 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
694 (SUBREG_TO_REG (i32 0),
695 (VMOVSDrr (v2i64 (V_SET0)),
696 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm)), sub_xmm)>;
698 // Extract and store.
699 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
701 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
702 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
704 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
706 // Shuffle with VMOVSS
707 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
708 (VMOVSSrr (v4i32 VR128:$src1),
709 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
710 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
711 (VMOVSSrr (v4f32 VR128:$src1),
712 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
715 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
716 (SUBREG_TO_REG (i32 0),
717 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
718 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
720 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
721 (SUBREG_TO_REG (i32 0),
722 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
723 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
726 // Shuffle with VMOVSD
727 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
728 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
729 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
730 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
731 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
732 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
733 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
734 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
737 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
738 (SUBREG_TO_REG (i32 0),
739 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
740 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
742 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
743 (SUBREG_TO_REG (i32 0),
744 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
745 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
749 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
750 // is during lowering, where it's not possible to recognize the fold cause
751 // it has two uses through a bitcast. One use disappears at isel time and the
752 // fold opportunity reappears.
753 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
754 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
755 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
756 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
757 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
758 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
759 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
760 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
763 let Predicates = [UseSSE1] in {
764 let AddedComplexity = 15 in {
765 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
766 // MOVSS to the lower bits.
767 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
768 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
769 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
770 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
771 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
772 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
775 let AddedComplexity = 20 in {
776 // MOVSSrm already zeros the high parts of the register.
777 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
778 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
779 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
780 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
781 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
782 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
785 // Extract and store.
786 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
788 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
790 // Shuffle with MOVSS
791 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
792 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
793 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
794 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
797 let Predicates = [UseSSE2] in {
798 let AddedComplexity = 15 in {
799 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
800 // MOVSD to the lower bits.
801 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
802 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
805 let AddedComplexity = 20 in {
806 // MOVSDrm already zeros the high parts of the register.
807 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
808 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
809 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
810 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
811 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
812 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
813 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
814 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
815 def : Pat<(v2f64 (X86vzload addr:$src)),
816 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
819 // Extract and store.
820 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
822 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
824 // Shuffle with MOVSD
825 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
826 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
827 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
828 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
829 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
830 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
831 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
832 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
834 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
835 // is during lowering, where it's not possible to recognize the fold cause
836 // it has two uses through a bitcast. One use disappears at isel time and the
837 // fold opportunity reappears.
838 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
839 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
840 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
841 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
842 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
843 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
844 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
845 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
848 //===----------------------------------------------------------------------===//
849 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
850 //===----------------------------------------------------------------------===//
852 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
853 X86MemOperand x86memop, PatFrag ld_frag,
854 string asm, Domain d,
856 bit IsReMaterializable = 1> {
857 let neverHasSideEffects = 1 in
858 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
859 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
860 Sched<[WriteFShuffle]>;
861 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
862 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
863 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
864 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
868 let Predicates = [HasAVX, NoVLX] in {
869 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
870 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
872 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
873 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
875 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
876 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
878 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
879 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
882 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
883 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
885 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
886 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
888 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
889 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
891 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
892 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
896 let Predicates = [UseSSE1] in {
897 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
898 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
900 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
901 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
904 let Predicates = [UseSSE2] in {
905 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
906 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
908 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
909 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
913 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
914 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
915 "movaps\t{$src, $dst|$dst, $src}",
916 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
917 IIC_SSE_MOVA_P_MR>, VEX;
918 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
919 "movapd\t{$src, $dst|$dst, $src}",
920 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
921 IIC_SSE_MOVA_P_MR>, VEX;
922 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
923 "movups\t{$src, $dst|$dst, $src}",
924 [(store (v4f32 VR128:$src), addr:$dst)],
925 IIC_SSE_MOVU_P_MR>, VEX;
926 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
927 "movupd\t{$src, $dst|$dst, $src}",
928 [(store (v2f64 VR128:$src), addr:$dst)],
929 IIC_SSE_MOVU_P_MR>, VEX;
930 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
931 "movaps\t{$src, $dst|$dst, $src}",
932 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
933 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
934 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
935 "movapd\t{$src, $dst|$dst, $src}",
936 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
937 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
938 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
939 "movups\t{$src, $dst|$dst, $src}",
940 [(store (v8f32 VR256:$src), addr:$dst)],
941 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
942 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
943 "movupd\t{$src, $dst|$dst, $src}",
944 [(store (v4f64 VR256:$src), addr:$dst)],
945 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
949 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
950 SchedRW = [WriteFShuffle] in {
951 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
953 "movaps\t{$src, $dst|$dst, $src}", [],
954 IIC_SSE_MOVA_P_RR>, VEX;
955 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
957 "movapd\t{$src, $dst|$dst, $src}", [],
958 IIC_SSE_MOVA_P_RR>, VEX;
959 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
961 "movups\t{$src, $dst|$dst, $src}", [],
962 IIC_SSE_MOVU_P_RR>, VEX;
963 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
965 "movupd\t{$src, $dst|$dst, $src}", [],
966 IIC_SSE_MOVU_P_RR>, VEX;
967 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
969 "movaps\t{$src, $dst|$dst, $src}", [],
970 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
971 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
973 "movapd\t{$src, $dst|$dst, $src}", [],
974 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
975 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
977 "movups\t{$src, $dst|$dst, $src}", [],
978 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
979 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
981 "movupd\t{$src, $dst|$dst, $src}", [],
982 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
985 let Predicates = [HasAVX] in {
986 def : Pat<(v8i32 (X86vzmovl
987 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
988 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
989 def : Pat<(v4i64 (X86vzmovl
990 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
991 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
992 def : Pat<(v8f32 (X86vzmovl
993 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
994 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
995 def : Pat<(v4f64 (X86vzmovl
996 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
997 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
1001 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
1002 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1003 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
1004 (VMOVUPDYmr addr:$dst, VR256:$src)>;
1006 let SchedRW = [WriteStore] in {
1007 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1008 "movaps\t{$src, $dst|$dst, $src}",
1009 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
1011 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1012 "movapd\t{$src, $dst|$dst, $src}",
1013 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
1015 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1016 "movups\t{$src, $dst|$dst, $src}",
1017 [(store (v4f32 VR128:$src), addr:$dst)],
1019 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1020 "movupd\t{$src, $dst|$dst, $src}",
1021 [(store (v2f64 VR128:$src), addr:$dst)],
1026 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
1027 SchedRW = [WriteFShuffle] in {
1028 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1029 "movaps\t{$src, $dst|$dst, $src}", [],
1031 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1032 "movapd\t{$src, $dst|$dst, $src}", [],
1034 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1035 "movups\t{$src, $dst|$dst, $src}", [],
1037 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
1038 "movupd\t{$src, $dst|$dst, $src}", [],
1042 let Predicates = [HasAVX] in {
1043 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1044 (VMOVUPSmr addr:$dst, VR128:$src)>;
1045 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1046 (VMOVUPDmr addr:$dst, VR128:$src)>;
1049 let Predicates = [UseSSE1] in
1050 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1051 (MOVUPSmr addr:$dst, VR128:$src)>;
1052 let Predicates = [UseSSE2] in
1053 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1054 (MOVUPDmr addr:$dst, VR128:$src)>;
1056 // Use vmovaps/vmovups for AVX integer load/store.
1057 let Predicates = [HasAVX, NoVLX] in {
1058 // 128-bit load/store
1059 def : Pat<(alignedloadv2i64 addr:$src),
1060 (VMOVAPSrm addr:$src)>;
1061 def : Pat<(loadv2i64 addr:$src),
1062 (VMOVUPSrm addr:$src)>;
1064 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1065 (VMOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1067 (VMOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1069 (VMOVAPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1071 (VMOVAPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1073 (VMOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1075 (VMOVUPSmr addr:$dst, VR128:$src)>;
1076 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1077 (VMOVUPSmr addr:$dst, VR128:$src)>;
1078 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1079 (VMOVUPSmr addr:$dst, VR128:$src)>;
1081 // 256-bit load/store
1082 def : Pat<(alignedloadv4i64 addr:$src),
1083 (VMOVAPSYrm addr:$src)>;
1084 def : Pat<(loadv4i64 addr:$src),
1085 (VMOVUPSYrm addr:$src)>;
1086 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1087 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1088 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1089 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1090 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1091 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1092 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1093 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1094 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1095 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1096 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1097 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1098 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1099 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1100 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1101 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1103 // Special patterns for storing subvector extracts of lower 128-bits
1104 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1105 def : Pat<(alignedstore (v2f64 (extract_subvector
1106 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1107 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1108 def : Pat<(alignedstore (v4f32 (extract_subvector
1109 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1110 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1111 def : Pat<(alignedstore (v2i64 (extract_subvector
1112 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1113 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1114 def : Pat<(alignedstore (v4i32 (extract_subvector
1115 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1116 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1117 def : Pat<(alignedstore (v8i16 (extract_subvector
1118 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1119 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1120 def : Pat<(alignedstore (v16i8 (extract_subvector
1121 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1122 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1124 def : Pat<(store (v2f64 (extract_subvector
1125 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1126 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1127 def : Pat<(store (v4f32 (extract_subvector
1128 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1129 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1130 def : Pat<(store (v2i64 (extract_subvector
1131 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1132 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1133 def : Pat<(store (v4i32 (extract_subvector
1134 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1135 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1136 def : Pat<(store (v8i16 (extract_subvector
1137 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1138 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1139 def : Pat<(store (v16i8 (extract_subvector
1140 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1141 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1144 // Use movaps / movups for SSE integer load / store (one byte shorter).
1145 // The instructions selected below are then converted to MOVDQA/MOVDQU
1146 // during the SSE domain pass.
1147 let Predicates = [UseSSE1] in {
1148 def : Pat<(alignedloadv2i64 addr:$src),
1149 (MOVAPSrm addr:$src)>;
1150 def : Pat<(loadv2i64 addr:$src),
1151 (MOVUPSrm addr:$src)>;
1153 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1154 (MOVAPSmr addr:$dst, VR128:$src)>;
1155 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1156 (MOVAPSmr addr:$dst, VR128:$src)>;
1157 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1158 (MOVAPSmr addr:$dst, VR128:$src)>;
1159 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1160 (MOVAPSmr addr:$dst, VR128:$src)>;
1161 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1162 (MOVUPSmr addr:$dst, VR128:$src)>;
1163 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1164 (MOVUPSmr addr:$dst, VR128:$src)>;
1165 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1166 (MOVUPSmr addr:$dst, VR128:$src)>;
1167 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1168 (MOVUPSmr addr:$dst, VR128:$src)>;
1171 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1172 // bits are disregarded. FIXME: Set encoding to pseudo!
1173 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1174 let isCodeGenOnly = 1 in {
1175 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1176 "movaps\t{$src, $dst|$dst, $src}",
1177 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1178 IIC_SSE_MOVA_P_RM>, VEX;
1179 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1180 "movapd\t{$src, $dst|$dst, $src}",
1181 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1182 IIC_SSE_MOVA_P_RM>, VEX;
1183 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1184 "movaps\t{$src, $dst|$dst, $src}",
1185 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1187 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1188 "movapd\t{$src, $dst|$dst, $src}",
1189 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1194 //===----------------------------------------------------------------------===//
1195 // SSE 1 & 2 - Move Low packed FP Instructions
1196 //===----------------------------------------------------------------------===//
1198 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1199 string base_opc, string asm_opr,
1200 InstrItinClass itin> {
1201 def PSrm : PI<opc, MRMSrcMem,
1202 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1203 !strconcat(base_opc, "s", asm_opr),
1205 (psnode VR128:$src1,
1206 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1207 itin, SSEPackedSingle>, PS,
1208 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1210 def PDrm : PI<opc, MRMSrcMem,
1211 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1212 !strconcat(base_opc, "d", asm_opr),
1213 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1214 (scalar_to_vector (loadf64 addr:$src2)))))],
1215 itin, SSEPackedDouble>, PD,
1216 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1220 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1221 string base_opc, InstrItinClass itin> {
1222 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1223 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1226 let Constraints = "$src1 = $dst" in
1227 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1228 "\t{$src2, $dst|$dst, $src2}",
1232 let AddedComplexity = 20 in {
1233 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1237 let SchedRW = [WriteStore] in {
1238 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1239 "movlps\t{$src, $dst|$dst, $src}",
1240 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1241 (iPTR 0))), addr:$dst)],
1242 IIC_SSE_MOV_LH>, VEX;
1243 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1244 "movlpd\t{$src, $dst|$dst, $src}",
1245 [(store (f64 (vector_extract (v2f64 VR128:$src),
1246 (iPTR 0))), addr:$dst)],
1247 IIC_SSE_MOV_LH>, VEX;
1248 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1249 "movlps\t{$src, $dst|$dst, $src}",
1250 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1251 (iPTR 0))), addr:$dst)],
1253 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1254 "movlpd\t{$src, $dst|$dst, $src}",
1255 [(store (f64 (vector_extract (v2f64 VR128:$src),
1256 (iPTR 0))), addr:$dst)],
1260 let Predicates = [HasAVX] in {
1261 // Shuffle with VMOVLPS
1262 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1263 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1264 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1265 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1267 // Shuffle with VMOVLPD
1268 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1269 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1270 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1271 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1274 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1276 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1277 def : Pat<(store (v4i32 (X86Movlps
1278 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1279 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1288 let Predicates = [UseSSE1] in {
1289 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1290 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1291 (iPTR 0))), addr:$src1),
1292 (MOVLPSmr addr:$src1, VR128:$src2)>;
1294 // Shuffle with MOVLPS
1295 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1296 (MOVLPSrm VR128:$src1, addr:$src2)>;
1297 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1298 (MOVLPSrm VR128:$src1, addr:$src2)>;
1299 def : Pat<(X86Movlps VR128:$src1,
1300 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1301 (MOVLPSrm VR128:$src1, addr:$src2)>;
1304 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1306 (MOVLPSmr addr:$src1, VR128:$src2)>;
1307 def : Pat<(store (v4i32 (X86Movlps
1308 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1310 (MOVLPSmr addr:$src1, VR128:$src2)>;
1313 let Predicates = [UseSSE2] in {
1314 // Shuffle with MOVLPD
1315 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1316 (MOVLPDrm VR128:$src1, addr:$src2)>;
1317 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1318 (MOVLPDrm VR128:$src1, addr:$src2)>;
1321 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1323 (MOVLPDmr addr:$src1, VR128:$src2)>;
1324 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1326 (MOVLPDmr addr:$src1, VR128:$src2)>;
1329 //===----------------------------------------------------------------------===//
1330 // SSE 1 & 2 - Move Hi packed FP Instructions
1331 //===----------------------------------------------------------------------===//
1333 let AddedComplexity = 20 in {
1334 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1338 let SchedRW = [WriteStore] in {
1339 // v2f64 extract element 1 is always custom lowered to unpack high to low
1340 // and extract element 0 so the non-store version isn't too horrible.
1341 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1342 "movhps\t{$src, $dst|$dst, $src}",
1343 [(store (f64 (vector_extract
1344 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1345 (bc_v2f64 (v4f32 VR128:$src))),
1346 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1347 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1348 "movhpd\t{$src, $dst|$dst, $src}",
1349 [(store (f64 (vector_extract
1350 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1351 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1352 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1353 "movhps\t{$src, $dst|$dst, $src}",
1354 [(store (f64 (vector_extract
1355 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1356 (bc_v2f64 (v4f32 VR128:$src))),
1357 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1358 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1359 "movhpd\t{$src, $dst|$dst, $src}",
1360 [(store (f64 (vector_extract
1361 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1362 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1365 let Predicates = [HasAVX] in {
1367 def : Pat<(X86Movlhps VR128:$src1,
1368 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1369 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1370 def : Pat<(X86Movlhps VR128:$src1,
1371 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1372 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1374 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1375 // is during lowering, where it's not possible to recognize the load fold
1376 // cause it has two uses through a bitcast. One use disappears at isel time
1377 // and the fold opportunity reappears.
1378 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1379 (scalar_to_vector (loadf64 addr:$src2)))),
1380 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1381 // Also handle an i64 load because that may get selected as a faster way to
1383 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1384 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1385 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1388 let Predicates = [UseSSE1] in {
1390 def : Pat<(X86Movlhps VR128:$src1,
1391 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1392 (MOVHPSrm VR128:$src1, addr:$src2)>;
1393 def : Pat<(X86Movlhps VR128:$src1,
1394 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1395 (MOVHPSrm VR128:$src1, addr:$src2)>;
1398 let Predicates = [UseSSE2] in {
1399 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1400 // is during lowering, where it's not possible to recognize the load fold
1401 // cause it has two uses through a bitcast. One use disappears at isel time
1402 // and the fold opportunity reappears.
1403 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1404 (scalar_to_vector (loadf64 addr:$src2)))),
1405 (MOVHPDrm VR128:$src1, addr:$src2)>;
1406 // Also handle an i64 load because that may get selected as a faster way to
1408 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1409 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1410 (MOVHPDrm VR128:$src1, addr:$src2)>;
1413 //===----------------------------------------------------------------------===//
1414 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1415 //===----------------------------------------------------------------------===//
1417 let AddedComplexity = 20, Predicates = [UseAVX] in {
1418 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1419 (ins VR128:$src1, VR128:$src2),
1420 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1422 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1424 VEX_4V, Sched<[WriteFShuffle]>;
1425 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1426 (ins VR128:$src1, VR128:$src2),
1427 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1429 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1431 VEX_4V, Sched<[WriteFShuffle]>;
1433 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1434 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1435 (ins VR128:$src1, VR128:$src2),
1436 "movlhps\t{$src2, $dst|$dst, $src2}",
1438 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1439 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1440 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1441 (ins VR128:$src1, VR128:$src2),
1442 "movhlps\t{$src2, $dst|$dst, $src2}",
1444 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1445 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1448 let Predicates = [UseAVX] in {
1450 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1451 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1452 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1453 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1456 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1457 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1460 let Predicates = [UseSSE1] in {
1462 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1463 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1464 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1465 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1468 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1469 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1472 //===----------------------------------------------------------------------===//
1473 // SSE 1 & 2 - Conversion Instructions
1474 //===----------------------------------------------------------------------===//
1476 def SSE_CVT_PD : OpndItins<
1477 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1480 let Sched = WriteCvtI2F in
1481 def SSE_CVT_PS : OpndItins<
1482 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1485 let Sched = WriteCvtI2F in
1486 def SSE_CVT_Scalar : OpndItins<
1487 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1490 let Sched = WriteCvtF2I in
1491 def SSE_CVT_SS2SI_32 : OpndItins<
1492 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1495 let Sched = WriteCvtF2I in
1496 def SSE_CVT_SS2SI_64 : OpndItins<
1497 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1500 let Sched = WriteCvtF2I in
1501 def SSE_CVT_SD2SI : OpndItins<
1502 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1505 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1506 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1507 string asm, OpndItins itins> {
1508 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1509 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1510 itins.rr>, Sched<[itins.Sched]>;
1511 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1512 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1513 itins.rm>, Sched<[itins.Sched.Folded]>;
1516 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1517 X86MemOperand x86memop, string asm, Domain d,
1519 let neverHasSideEffects = 1 in {
1520 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1521 [], itins.rr, d>, Sched<[itins.Sched]>;
1523 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1524 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1528 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1529 X86MemOperand x86memop, string asm> {
1530 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1531 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1532 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1533 Sched<[WriteCvtI2F]>;
1535 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1536 (ins DstRC:$src1, x86memop:$src),
1537 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1538 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1539 } // neverHasSideEffects = 1
1542 let Predicates = [UseAVX] in {
1543 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1544 "cvttss2si\t{$src, $dst|$dst, $src}",
1547 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1548 "cvttss2si\t{$src, $dst|$dst, $src}",
1550 XS, VEX, VEX_W, VEX_LIG;
1551 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1552 "cvttsd2si\t{$src, $dst|$dst, $src}",
1555 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1556 "cvttsd2si\t{$src, $dst|$dst, $src}",
1558 XD, VEX, VEX_W, VEX_LIG;
1560 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1561 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1562 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1563 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1564 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1565 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1566 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1567 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1568 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1569 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1570 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1571 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1572 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1573 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1574 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1575 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1577 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1578 // register, but the same isn't true when only using memory operands,
1579 // provide other assembly "l" and "q" forms to address this explicitly
1580 // where appropriate to do so.
1581 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1582 XS, VEX_4V, VEX_LIG;
1583 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1584 XS, VEX_4V, VEX_W, VEX_LIG;
1585 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1586 XD, VEX_4V, VEX_LIG;
1587 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1588 XD, VEX_4V, VEX_W, VEX_LIG;
1590 let Predicates = [UseAVX] in {
1591 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1592 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1593 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1594 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1596 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1597 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1598 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1599 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1600 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1601 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1602 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1603 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1605 def : Pat<(f32 (sint_to_fp GR32:$src)),
1606 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1607 def : Pat<(f32 (sint_to_fp GR64:$src)),
1608 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1609 def : Pat<(f64 (sint_to_fp GR32:$src)),
1610 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1611 def : Pat<(f64 (sint_to_fp GR64:$src)),
1612 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1615 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1616 "cvttss2si\t{$src, $dst|$dst, $src}",
1617 SSE_CVT_SS2SI_32>, XS;
1618 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1619 "cvttss2si\t{$src, $dst|$dst, $src}",
1620 SSE_CVT_SS2SI_64>, XS, REX_W;
1621 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1622 "cvttsd2si\t{$src, $dst|$dst, $src}",
1624 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1625 "cvttsd2si\t{$src, $dst|$dst, $src}",
1626 SSE_CVT_SD2SI>, XD, REX_W;
1627 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1628 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1629 SSE_CVT_Scalar>, XS;
1630 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1631 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1632 SSE_CVT_Scalar>, XS, REX_W;
1633 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1634 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1635 SSE_CVT_Scalar>, XD;
1636 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1637 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1638 SSE_CVT_Scalar>, XD, REX_W;
1640 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1641 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1642 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1643 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1644 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1645 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1646 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1647 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1648 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1649 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1650 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1651 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1652 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1653 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1654 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1655 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1657 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1658 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1659 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1660 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1662 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1663 // and/or XMM operand(s).
1665 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1666 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1667 string asm, OpndItins itins> {
1668 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1669 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1670 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1671 Sched<[itins.Sched]>;
1672 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1673 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1674 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1675 Sched<[itins.Sched.Folded]>;
1678 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1679 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1680 PatFrag ld_frag, string asm, OpndItins itins,
1682 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1684 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1685 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1686 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1687 itins.rr>, Sched<[itins.Sched]>;
1688 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1689 (ins DstRC:$src1, x86memop:$src2),
1691 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1692 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1693 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1694 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1697 let Predicates = [UseAVX] in {
1698 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1699 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1700 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1701 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1702 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1703 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1705 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1706 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1707 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1708 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1711 let isCodeGenOnly = 1 in {
1712 let Predicates = [UseAVX] in {
1713 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1714 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1715 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1716 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1717 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1718 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1720 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1721 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1722 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1723 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1724 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1725 SSE_CVT_Scalar, 0>, XD,
1728 let Constraints = "$src1 = $dst" in {
1729 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1730 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1731 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1732 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1733 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1734 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1735 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1736 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1737 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1738 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1739 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1740 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1742 } // isCodeGenOnly = 1
1746 // Aliases for intrinsics
1747 let isCodeGenOnly = 1 in {
1748 let Predicates = [UseAVX] in {
1749 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1750 ssmem, sse_load_f32, "cvttss2si",
1751 SSE_CVT_SS2SI_32>, XS, VEX;
1752 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1753 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1754 "cvttss2si", SSE_CVT_SS2SI_64>,
1756 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1757 sdmem, sse_load_f64, "cvttsd2si",
1758 SSE_CVT_SD2SI>, XD, VEX;
1759 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1760 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1761 "cvttsd2si", SSE_CVT_SD2SI>,
1764 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1765 ssmem, sse_load_f32, "cvttss2si",
1766 SSE_CVT_SS2SI_32>, XS;
1767 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1768 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1769 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1770 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1771 sdmem, sse_load_f64, "cvttsd2si",
1773 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1774 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1775 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1776 } // isCodeGenOnly = 1
1778 let Predicates = [UseAVX] in {
1779 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1780 ssmem, sse_load_f32, "cvtss2si",
1781 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1782 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1783 ssmem, sse_load_f32, "cvtss2si",
1784 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1786 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1787 ssmem, sse_load_f32, "cvtss2si",
1788 SSE_CVT_SS2SI_32>, XS;
1789 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1790 ssmem, sse_load_f32, "cvtss2si",
1791 SSE_CVT_SS2SI_64>, XS, REX_W;
1793 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1794 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1795 SSEPackedSingle, SSE_CVT_PS>,
1796 PS, VEX, Requires<[HasAVX]>;
1797 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1798 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1799 SSEPackedSingle, SSE_CVT_PS>,
1800 PS, VEX, VEX_L, Requires<[HasAVX]>;
1802 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1803 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1804 SSEPackedSingle, SSE_CVT_PS>,
1805 PS, Requires<[UseSSE2]>;
1807 let Predicates = [UseAVX] in {
1808 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1809 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1810 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1811 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1812 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1813 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1814 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1815 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1816 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1817 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1818 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1819 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1820 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1821 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1822 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1823 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1826 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1827 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1828 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1829 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1830 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1831 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1832 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1833 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1834 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1835 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1836 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1837 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1838 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1839 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1840 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1841 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1845 // Convert scalar double to scalar single
1846 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1847 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1848 (ins FR64:$src1, FR64:$src2),
1849 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1850 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1851 Sched<[WriteCvtF2F]>;
1853 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1854 (ins FR64:$src1, f64mem:$src2),
1855 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1856 [], IIC_SSE_CVT_Scalar_RM>,
1857 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1858 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1861 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1864 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1865 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1866 [(set FR32:$dst, (fround FR64:$src))],
1867 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1868 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1869 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1870 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1871 IIC_SSE_CVT_Scalar_RM>,
1873 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1875 let isCodeGenOnly = 1 in {
1876 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1877 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1878 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1880 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1881 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1882 Sched<[WriteCvtF2F]>;
1883 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1884 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1885 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1886 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1887 VR128:$src1, sse_load_f64:$src2))],
1888 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1889 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1891 let Constraints = "$src1 = $dst" in {
1892 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1893 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1894 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1896 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1897 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1898 Sched<[WriteCvtF2F]>;
1899 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1900 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1901 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1902 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1903 VR128:$src1, sse_load_f64:$src2))],
1904 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1905 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1907 } // isCodeGenOnly = 1
1909 // Convert scalar single to scalar double
1910 // SSE2 instructions with XS prefix
1911 let neverHasSideEffects = 1, Predicates = [UseAVX] in {
1912 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1913 (ins FR32:$src1, FR32:$src2),
1914 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1915 [], IIC_SSE_CVT_Scalar_RR>,
1916 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1917 Sched<[WriteCvtF2F]>;
1919 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1920 (ins FR32:$src1, f32mem:$src2),
1921 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1922 [], IIC_SSE_CVT_Scalar_RM>,
1923 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1924 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1927 def : Pat<(f64 (fextend FR32:$src)),
1928 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1929 def : Pat<(fextend (loadf32 addr:$src)),
1930 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1932 def : Pat<(extloadf32 addr:$src),
1933 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1934 Requires<[UseAVX, OptForSize]>;
1935 def : Pat<(extloadf32 addr:$src),
1936 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1937 Requires<[UseAVX, OptForSpeed]>;
1939 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1940 "cvtss2sd\t{$src, $dst|$dst, $src}",
1941 [(set FR64:$dst, (fextend FR32:$src))],
1942 IIC_SSE_CVT_Scalar_RR>, XS,
1943 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1944 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1945 "cvtss2sd\t{$src, $dst|$dst, $src}",
1946 [(set FR64:$dst, (extloadf32 addr:$src))],
1947 IIC_SSE_CVT_Scalar_RM>, XS,
1948 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1950 // extload f32 -> f64. This matches load+fextend because we have a hack in
1951 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1953 // Since these loads aren't folded into the fextend, we have to match it
1955 def : Pat<(fextend (loadf32 addr:$src)),
1956 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1957 def : Pat<(extloadf32 addr:$src),
1958 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1960 let isCodeGenOnly = 1 in {
1961 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1962 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1963 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1965 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1966 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1967 Sched<[WriteCvtF2F]>;
1968 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1969 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1970 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1972 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1973 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1974 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1975 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1976 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1977 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1978 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1980 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1981 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1982 Sched<[WriteCvtF2F]>;
1983 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1984 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1985 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1987 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1988 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1989 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1991 } // isCodeGenOnly = 1
1993 // Convert packed single/double fp to doubleword
1994 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1995 "cvtps2dq\t{$src, $dst|$dst, $src}",
1996 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1997 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1998 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1999 "cvtps2dq\t{$src, $dst|$dst, $src}",
2001 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
2002 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2003 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2004 "cvtps2dq\t{$src, $dst|$dst, $src}",
2006 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
2007 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2008 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2009 "cvtps2dq\t{$src, $dst|$dst, $src}",
2011 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
2012 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2013 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2014 "cvtps2dq\t{$src, $dst|$dst, $src}",
2015 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
2016 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2017 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2018 "cvtps2dq\t{$src, $dst|$dst, $src}",
2020 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
2021 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2024 // Convert Packed Double FP to Packed DW Integers
2025 let Predicates = [HasAVX] in {
2026 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2027 // register, but the same isn't true when using memory operands instead.
2028 // Provide other assembly rr and rm forms to address this explicitly.
2029 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2030 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2031 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2032 VEX, Sched<[WriteCvtF2I]>;
2035 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2036 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2037 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2038 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2040 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2041 Sched<[WriteCvtF2ILd]>;
2044 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2045 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2047 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2048 Sched<[WriteCvtF2I]>;
2049 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2050 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2052 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2053 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2054 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2055 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2058 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2059 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2061 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2062 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2063 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2064 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2065 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2066 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2068 // Convert with truncation packed single/double fp to doubleword
2069 // SSE2 packed instructions with XS prefix
2070 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2071 "cvttps2dq\t{$src, $dst|$dst, $src}",
2073 (int_x86_sse2_cvttps2dq VR128:$src))],
2074 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2075 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2076 "cvttps2dq\t{$src, $dst|$dst, $src}",
2077 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2078 (loadv4f32 addr:$src)))],
2079 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2080 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2081 "cvttps2dq\t{$src, $dst|$dst, $src}",
2083 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2084 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2085 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2086 "cvttps2dq\t{$src, $dst|$dst, $src}",
2087 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2088 (loadv8f32 addr:$src)))],
2089 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2090 Sched<[WriteCvtF2ILd]>;
2092 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2093 "cvttps2dq\t{$src, $dst|$dst, $src}",
2094 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2095 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2096 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2097 "cvttps2dq\t{$src, $dst|$dst, $src}",
2099 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2100 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2102 let Predicates = [HasAVX] in {
2103 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2104 (VCVTDQ2PSrr VR128:$src)>;
2105 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2106 (VCVTDQ2PSrm addr:$src)>;
2108 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2109 (VCVTDQ2PSrr VR128:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2111 (VCVTDQ2PSrm addr:$src)>;
2113 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2114 (VCVTTPS2DQrr VR128:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2116 (VCVTTPS2DQrm addr:$src)>;
2118 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2119 (VCVTDQ2PSYrr VR256:$src)>;
2120 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2121 (VCVTDQ2PSYrm addr:$src)>;
2123 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2124 (VCVTTPS2DQYrr VR256:$src)>;
2125 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2126 (VCVTTPS2DQYrm addr:$src)>;
2129 let Predicates = [UseSSE2] in {
2130 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2131 (CVTDQ2PSrr VR128:$src)>;
2132 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2133 (CVTDQ2PSrm addr:$src)>;
2135 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2136 (CVTDQ2PSrr VR128:$src)>;
2137 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2138 (CVTDQ2PSrm addr:$src)>;
2140 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2141 (CVTTPS2DQrr VR128:$src)>;
2142 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2143 (CVTTPS2DQrm addr:$src)>;
2146 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2147 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2149 (int_x86_sse2_cvttpd2dq VR128:$src))],
2150 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2152 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2153 // register, but the same isn't true when using memory operands instead.
2154 // Provide other assembly rr and rm forms to address this explicitly.
2157 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2158 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2159 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2160 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2161 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2162 (loadv2f64 addr:$src)))],
2163 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2166 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2167 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2169 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2170 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2171 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2172 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2174 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2175 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2176 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2177 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2179 let Predicates = [HasAVX] in {
2180 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2181 (VCVTTPD2DQYrr VR256:$src)>;
2182 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2183 (VCVTTPD2DQYrm addr:$src)>;
2184 } // Predicates = [HasAVX]
2186 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2187 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2188 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2189 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2190 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2191 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2192 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2193 (memopv2f64 addr:$src)))],
2195 Sched<[WriteCvtF2ILd]>;
2197 // Convert packed single to packed double
2198 let Predicates = [HasAVX] in {
2199 // SSE2 instructions without OpSize prefix
2200 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2201 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2202 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2203 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2204 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2205 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2206 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2207 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2208 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2209 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2211 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2212 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2213 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2214 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2216 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2217 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2220 let Predicates = [UseSSE2] in {
2221 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2222 "cvtps2pd\t{$src, $dst|$dst, $src}",
2223 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2224 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2225 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2226 "cvtps2pd\t{$src, $dst|$dst, $src}",
2227 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2228 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2231 // Convert Packed DW Integers to Packed Double FP
2232 let Predicates = [HasAVX] in {
2233 let neverHasSideEffects = 1, mayLoad = 1 in
2234 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2235 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2236 []>, VEX, Sched<[WriteCvtI2FLd]>;
2237 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2238 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2240 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2241 Sched<[WriteCvtI2F]>;
2242 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2243 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2245 (int_x86_avx_cvtdq2_pd_256
2246 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2247 Sched<[WriteCvtI2FLd]>;
2248 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2249 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2251 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2252 Sched<[WriteCvtI2F]>;
2255 let neverHasSideEffects = 1, mayLoad = 1 in
2256 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2257 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2258 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2259 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2260 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2261 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2262 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2264 // AVX 256-bit register conversion intrinsics
2265 let Predicates = [HasAVX] in {
2266 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2267 (VCVTDQ2PDYrr VR128:$src)>;
2268 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2269 (VCVTDQ2PDYrm addr:$src)>;
2270 } // Predicates = [HasAVX]
2272 // Convert packed double to packed single
2273 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2274 // register, but the same isn't true when using memory operands instead.
2275 // Provide other assembly rr and rm forms to address this explicitly.
2276 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2277 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2278 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2279 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2282 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2283 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2284 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2285 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2287 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2288 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2291 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2292 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2294 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2295 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2296 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2297 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2299 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2300 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2301 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2302 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2304 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2305 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2306 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2307 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2308 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2309 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2311 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2312 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2315 // AVX 256-bit register conversion intrinsics
2316 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2317 // whenever possible to avoid declaring two versions of each one.
2318 let Predicates = [HasAVX] in {
2319 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2320 (VCVTDQ2PSYrr VR256:$src)>;
2321 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2322 (VCVTDQ2PSYrm addr:$src)>;
2324 // Match fround and fextend for 128/256-bit conversions
2325 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2326 (VCVTPD2PSrr VR128:$src)>;
2327 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2328 (VCVTPD2PSXrm addr:$src)>;
2329 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2330 (VCVTPD2PSYrr VR256:$src)>;
2331 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2332 (VCVTPD2PSYrm addr:$src)>;
2334 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2335 (VCVTPS2PDrr VR128:$src)>;
2336 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2337 (VCVTPS2PDYrr VR128:$src)>;
2338 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2339 (VCVTPS2PDYrm addr:$src)>;
2342 let Predicates = [UseSSE2] in {
2343 // Match fround and fextend for 128 conversions
2344 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2345 (CVTPD2PSrr VR128:$src)>;
2346 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2347 (CVTPD2PSrm addr:$src)>;
2349 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2350 (CVTPS2PDrr VR128:$src)>;
2353 //===----------------------------------------------------------------------===//
2354 // SSE 1 & 2 - Compare Instructions
2355 //===----------------------------------------------------------------------===//
2357 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2358 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2359 Operand CC, SDNode OpNode, ValueType VT,
2360 PatFrag ld_frag, string asm, string asm_alt,
2362 def rr : SIi8<0xC2, MRMSrcReg,
2363 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2364 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2365 itins.rr>, Sched<[itins.Sched]>;
2366 def rm : SIi8<0xC2, MRMSrcMem,
2367 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2368 [(set RC:$dst, (OpNode (VT RC:$src1),
2369 (ld_frag addr:$src2), imm:$cc))],
2371 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2373 // Accept explicit immediate argument form instead of comparison code.
2374 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2375 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2376 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2377 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2379 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2380 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2381 IIC_SSE_ALU_F32S_RM>,
2382 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2386 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2387 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2388 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2390 XS, VEX_4V, VEX_LIG;
2391 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2392 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2393 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2394 SSE_ALU_F32S>, // same latency as 32 bit compare
2395 XD, VEX_4V, VEX_LIG;
2397 let Constraints = "$src1 = $dst" in {
2398 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2399 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2400 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2402 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2403 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2404 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2409 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2410 Intrinsic Int, string asm, OpndItins itins> {
2411 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2412 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2413 [(set VR128:$dst, (Int VR128:$src1,
2414 VR128:$src, imm:$cc))],
2416 Sched<[itins.Sched]>;
2417 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2418 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2419 [(set VR128:$dst, (Int VR128:$src1,
2420 (load addr:$src), imm:$cc))],
2422 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2425 let isCodeGenOnly = 1 in {
2426 // Aliases to match intrinsics which expect XMM operand(s).
2427 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2428 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2431 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2432 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2433 SSE_ALU_F32S>, // same latency as f32
2435 let Constraints = "$src1 = $dst" in {
2436 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2437 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2439 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2440 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2447 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2448 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2449 ValueType vt, X86MemOperand x86memop,
2450 PatFrag ld_frag, string OpcodeStr> {
2451 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2452 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2453 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2456 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2457 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2458 [(set EFLAGS, (OpNode (vt RC:$src1),
2459 (ld_frag addr:$src2)))],
2461 Sched<[WriteFAddLd, ReadAfterLd]>;
2464 let Defs = [EFLAGS] in {
2465 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2466 "ucomiss">, PS, VEX, VEX_LIG;
2467 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2468 "ucomisd">, PD, VEX, VEX_LIG;
2469 let Pattern = []<dag> in {
2470 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2471 "comiss">, PS, VEX, VEX_LIG;
2472 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2473 "comisd">, PD, VEX, VEX_LIG;
2476 let isCodeGenOnly = 1 in {
2477 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2478 load, "ucomiss">, PS, VEX;
2479 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2480 load, "ucomisd">, PD, VEX;
2482 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2483 load, "comiss">, PS, VEX;
2484 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2485 load, "comisd">, PD, VEX;
2487 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2489 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2492 let Pattern = []<dag> in {
2493 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2495 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2499 let isCodeGenOnly = 1 in {
2500 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2501 load, "ucomiss">, PS;
2502 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2503 load, "ucomisd">, PD;
2505 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2507 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2510 } // Defs = [EFLAGS]
2512 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2513 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2514 Operand CC, Intrinsic Int, string asm,
2515 string asm_alt, Domain d,
2516 OpndItins itins = SSE_ALU_F32P> {
2517 def rri : PIi8<0xC2, MRMSrcReg,
2518 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2519 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2522 def rmi : PIi8<0xC2, MRMSrcMem,
2523 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2524 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2526 Sched<[WriteFAddLd, ReadAfterLd]>;
2528 // Accept explicit immediate argument form instead of comparison code.
2529 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2530 def rri_alt : PIi8<0xC2, MRMSrcReg,
2531 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2532 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2533 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2534 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2535 asm_alt, [], itins.rm, d>,
2536 Sched<[WriteFAddLd, ReadAfterLd]>;
2540 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2541 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2542 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2543 SSEPackedSingle>, PS, VEX_4V;
2544 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2545 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2546 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2547 SSEPackedDouble>, PD, VEX_4V;
2548 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2549 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2550 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2551 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2552 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2553 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2554 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2555 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2556 let Constraints = "$src1 = $dst" in {
2557 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2558 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2559 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2560 SSEPackedSingle, SSE_ALU_F32P>, PS;
2561 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2562 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2563 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2564 SSEPackedDouble, SSE_ALU_F64P>, PD;
2567 let Predicates = [HasAVX] in {
2568 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2569 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2570 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2571 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2572 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2573 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2574 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2575 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2577 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2578 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2579 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2580 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2581 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2582 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2583 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2584 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2587 let Predicates = [UseSSE1] in {
2588 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2589 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2590 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2591 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2594 let Predicates = [UseSSE2] in {
2595 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2596 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2597 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2598 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2601 //===----------------------------------------------------------------------===//
2602 // SSE 1 & 2 - Shuffle Instructions
2603 //===----------------------------------------------------------------------===//
2605 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2606 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2607 ValueType vt, string asm, PatFrag mem_frag,
2608 Domain d, bit IsConvertibleToThreeAddress = 0> {
2609 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2610 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2611 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2612 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2613 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2614 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2615 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2616 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2617 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2618 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2619 Sched<[WriteFShuffle]>;
2622 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2623 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2624 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2625 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2626 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2627 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2628 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2629 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2630 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2631 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2632 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2633 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2635 let Constraints = "$src1 = $dst" in {
2636 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2637 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2638 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>, PS;
2639 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2640 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2641 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>, PD;
2644 let Predicates = [HasAVX] in {
2645 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2646 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2647 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2648 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2649 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2651 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2652 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2653 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2654 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2655 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2658 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2659 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2660 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2661 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2662 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2664 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2665 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2666 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2667 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2668 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2671 let Predicates = [UseSSE1] in {
2672 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2673 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2674 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2675 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2676 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2679 let Predicates = [UseSSE2] in {
2680 // Generic SHUFPD patterns
2681 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2682 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2683 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2684 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2685 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2688 //===----------------------------------------------------------------------===//
2689 // SSE 1 & 2 - Unpack FP Instructions
2690 //===----------------------------------------------------------------------===//
2692 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2693 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2694 PatFrag mem_frag, RegisterClass RC,
2695 X86MemOperand x86memop, string asm,
2697 def rr : PI<opc, MRMSrcReg,
2698 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2700 (vt (OpNode RC:$src1, RC:$src2)))],
2701 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2702 def rm : PI<opc, MRMSrcMem,
2703 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2705 (vt (OpNode RC:$src1,
2706 (mem_frag addr:$src2))))],
2708 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2711 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2712 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2713 SSEPackedSingle>, PS, VEX_4V;
2714 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2715 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2716 SSEPackedDouble>, PD, VEX_4V;
2717 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2718 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2719 SSEPackedSingle>, PS, VEX_4V;
2720 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2721 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2722 SSEPackedDouble>, PD, VEX_4V;
2724 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2725 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2726 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2727 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2728 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2729 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2730 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2731 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2732 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2733 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2734 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2735 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2737 let Constraints = "$src1 = $dst" in {
2738 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2739 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2740 SSEPackedSingle>, PS;
2741 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2742 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2743 SSEPackedDouble>, PD;
2744 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2745 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2746 SSEPackedSingle>, PS;
2747 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2748 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2749 SSEPackedDouble>, PD;
2750 } // Constraints = "$src1 = $dst"
2752 let Predicates = [HasAVX1Only] in {
2753 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2754 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2755 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2756 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2757 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2758 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2759 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2760 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2762 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2763 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2764 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2765 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2766 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2767 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2768 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2769 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2772 let Predicates = [HasAVX] in {
2773 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2774 // problem is during lowering, where it's not possible to recognize the load
2775 // fold cause it has two uses through a bitcast. One use disappears at isel
2776 // time and the fold opportunity reappears.
2777 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2778 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2781 let Predicates = [UseSSE2] in {
2782 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2783 // problem is during lowering, where it's not possible to recognize the load
2784 // fold cause it has two uses through a bitcast. One use disappears at isel
2785 // time and the fold opportunity reappears.
2786 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2787 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2790 //===----------------------------------------------------------------------===//
2791 // SSE 1 & 2 - Extract Floating-Point Sign mask
2792 //===----------------------------------------------------------------------===//
2794 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2795 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2797 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2798 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2799 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2800 Sched<[WriteVecLogic]>;
2803 let Predicates = [HasAVX] in {
2804 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2805 "movmskps", SSEPackedSingle>, PS, VEX;
2806 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2807 "movmskpd", SSEPackedDouble>, PD, VEX;
2808 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2809 "movmskps", SSEPackedSingle>, PS,
2811 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2812 "movmskpd", SSEPackedDouble>, PD,
2815 def : Pat<(i32 (X86fgetsign FR32:$src)),
2816 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2817 def : Pat<(i64 (X86fgetsign FR32:$src)),
2818 (SUBREG_TO_REG (i64 0),
2819 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2820 def : Pat<(i32 (X86fgetsign FR64:$src)),
2821 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2822 def : Pat<(i64 (X86fgetsign FR64:$src)),
2823 (SUBREG_TO_REG (i64 0),
2824 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2827 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2828 SSEPackedSingle>, PS;
2829 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2830 SSEPackedDouble>, PD;
2832 def : Pat<(i32 (X86fgetsign FR32:$src)),
2833 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2834 Requires<[UseSSE1]>;
2835 def : Pat<(i64 (X86fgetsign FR32:$src)),
2836 (SUBREG_TO_REG (i64 0),
2837 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2838 Requires<[UseSSE1]>;
2839 def : Pat<(i32 (X86fgetsign FR64:$src)),
2840 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2841 Requires<[UseSSE2]>;
2842 def : Pat<(i64 (X86fgetsign FR64:$src)),
2843 (SUBREG_TO_REG (i64 0),
2844 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2845 Requires<[UseSSE2]>;
2847 //===---------------------------------------------------------------------===//
2848 // SSE2 - Packed Integer Logical Instructions
2849 //===---------------------------------------------------------------------===//
2851 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2853 /// PDI_binop_rm - Simple SSE2 binary operator.
2854 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2855 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2856 X86MemOperand x86memop, OpndItins itins,
2857 bit IsCommutable, bit Is2Addr> {
2858 let isCommutable = IsCommutable in
2859 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2860 (ins RC:$src1, RC:$src2),
2862 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2863 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2864 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2865 Sched<[itins.Sched]>;
2866 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2867 (ins RC:$src1, x86memop:$src2),
2869 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2870 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2871 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2872 (bitconvert (memop_frag addr:$src2)))))],
2874 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2876 } // ExeDomain = SSEPackedInt
2878 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2879 ValueType OpVT128, ValueType OpVT256,
2880 OpndItins itins, bit IsCommutable = 0> {
2881 let Predicates = [HasAVX] in
2882 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2883 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2885 let Constraints = "$src1 = $dst" in
2886 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2887 memopv2i64, i128mem, itins, IsCommutable, 1>;
2889 let Predicates = [HasAVX2] in
2890 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2891 OpVT256, VR256, loadv4i64, i256mem, itins,
2892 IsCommutable, 0>, VEX_4V, VEX_L;
2895 // These are ordered here for pattern ordering requirements with the fp versions
2897 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2898 SSE_VEC_BIT_ITINS_P, 1>;
2899 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2900 SSE_VEC_BIT_ITINS_P, 1>;
2901 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2902 SSE_VEC_BIT_ITINS_P, 1>;
2903 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2904 SSE_VEC_BIT_ITINS_P, 0>;
2906 //===----------------------------------------------------------------------===//
2907 // SSE 1 & 2 - Logical Instructions
2908 //===----------------------------------------------------------------------===//
2910 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2912 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2913 SDNode OpNode, OpndItins itins> {
2914 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2915 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2918 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2919 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2922 let Constraints = "$src1 = $dst" in {
2923 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2924 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2927 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2928 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2933 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2934 let isCodeGenOnly = 1 in {
2935 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2937 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2939 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2942 let isCommutable = 0 in
2943 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", X86fandn,
2947 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2949 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2951 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2952 !strconcat(OpcodeStr, "ps"), f256mem,
2953 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2954 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2955 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2957 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2958 !strconcat(OpcodeStr, "pd"), f256mem,
2959 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2960 (bc_v4i64 (v4f64 VR256:$src2))))],
2961 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2962 (loadv4i64 addr:$src2)))], 0>,
2965 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2966 // are all promoted to v2i64, and the patterns are covered by the int
2967 // version. This is needed in SSE only, because v2i64 isn't supported on
2968 // SSE1, but only on SSE2.
2969 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2970 !strconcat(OpcodeStr, "ps"), f128mem, [],
2971 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2972 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2974 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2975 !strconcat(OpcodeStr, "pd"), f128mem,
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2977 (bc_v2i64 (v2f64 VR128:$src2))))],
2978 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2979 (loadv2i64 addr:$src2)))], 0>,
2982 let Constraints = "$src1 = $dst" in {
2983 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2984 !strconcat(OpcodeStr, "ps"), f128mem,
2985 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2986 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2987 (memopv2i64 addr:$src2)))]>, PS;
2989 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2990 !strconcat(OpcodeStr, "pd"), f128mem,
2991 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2992 (bc_v2i64 (v2f64 VR128:$src2))))],
2993 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2994 (memopv2i64 addr:$src2)))]>, PD;
2998 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2999 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
3000 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
3001 let isCommutable = 0 in
3002 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
3004 // AVX1 requires type coercions in order to fold loads directly into logical
3006 let Predicates = [HasAVX1Only] in {
3007 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
3008 (VANDPSYrm VR256:$src1, addr:$src2)>;
3009 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3010 (VORPSYrm VR256:$src1, addr:$src2)>;
3011 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3012 (VXORPSYrm VR256:$src1, addr:$src2)>;
3013 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3014 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3017 //===----------------------------------------------------------------------===//
3018 // SSE 1 & 2 - Arithmetic Instructions
3019 //===----------------------------------------------------------------------===//
3021 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3024 /// In addition, we also have a special variant of the scalar form here to
3025 /// represent the associated intrinsic operation. This form is unlike the
3026 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3027 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3029 /// These three forms can each be reg+reg or reg+mem.
3032 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3034 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3035 SDNode OpNode, SizeItins itins> {
3036 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3037 VR128, v4f32, f128mem, loadv4f32,
3038 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3039 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3040 VR128, v2f64, f128mem, loadv2f64,
3041 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3043 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3044 OpNode, VR256, v8f32, f256mem, loadv8f32,
3045 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3046 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3047 OpNode, VR256, v4f64, f256mem, loadv4f64,
3048 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3050 let Constraints = "$src1 = $dst" in {
3051 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3052 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3054 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3055 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3060 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3062 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3063 OpNode, FR32, f32mem, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3064 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3065 OpNode, FR64, f64mem, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3067 let Constraints = "$src1 = $dst" in {
3068 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3069 OpNode, FR32, f32mem, itins.s>, XS;
3070 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3071 OpNode, FR64, f64mem, itins.d>, XD;
3075 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3077 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3078 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3079 itins.s, 0>, XS, VEX_4V, VEX_LIG;
3080 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3081 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3082 itins.d, 0>, XD, VEX_4V, VEX_LIG;
3084 let Constraints = "$src1 = $dst" in {
3085 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3086 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3088 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3089 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3094 // Binary Arithmetic instructions
3095 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3096 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3097 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3098 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3101 let isCommutable = 0 in {
3102 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3103 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3104 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3105 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3106 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3107 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3108 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3109 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3110 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3111 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3112 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3113 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3116 let isCodeGenOnly = 1 in {
3117 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3118 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3119 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3120 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3123 // Patterns used to select SSE scalar fp arithmetic instructions from
3124 // a scalar fp operation followed by a blend.
3126 // These patterns know, for example, how to select an ADDSS from a
3127 // float add plus vector insert.
3129 // The effect is that the backend no longer emits unnecessary vector
3130 // insert instructions immediately after SSE scalar fp instructions
3131 // like addss or mulss.
3133 // For example, given the following code:
3134 // __m128 foo(__m128 A, __m128 B) {
3139 // previously we generated:
3140 // addss %xmm0, %xmm1
3141 // movss %xmm1, %xmm0
3144 // addss %xmm1, %xmm0
3146 let Predicates = [UseSSE1] in {
3147 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fadd
3148 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3150 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3151 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fsub
3152 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3154 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3155 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fmul
3156 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3158 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3159 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector (fdiv
3160 (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3162 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3165 let Predicates = [UseSSE2] in {
3166 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3168 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3169 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3171 (ADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3172 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3173 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3175 (SUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3176 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3177 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3179 (MULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3180 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3181 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3183 (DIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3186 let Predicates = [UseSSE41] in {
3187 // If the subtarget has SSE4.1 but not AVX, the vector insert
3188 // instruction is lowered into a X86insertps rather than a X86Movss.
3189 // When selecting SSE scalar single-precision fp arithmetic instructions,
3190 // make sure that we correctly match the X86insertps.
3192 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3193 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3194 FR32:$src))), (iPTR 0))),
3195 (ADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3196 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3197 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3198 FR32:$src))), (iPTR 0))),
3199 (SUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3200 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3201 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3202 FR32:$src))), (iPTR 0))),
3203 (MULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3204 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3205 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3206 FR32:$src))), (iPTR 0))),
3207 (DIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3210 let Predicates = [HasAVX] in {
3211 // The following patterns select AVX Scalar single/double precision fp
3212 // arithmetic instructions.
3214 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fadd
3215 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3217 (VADDSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3218 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fsub
3219 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3221 (VSUBSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3222 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fmul
3223 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3225 (VMULSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3226 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector (fdiv
3227 (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3229 (VDIVSDrr_Int v2f64:$dst, (COPY_TO_REGCLASS FR64:$src, VR128))>;
3230 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3231 (fadd (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3232 FR32:$src))), (iPTR 0))),
3233 (VADDSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3234 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3235 (fsub (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3236 FR32:$src))), (iPTR 0))),
3237 (VSUBSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3238 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3239 (fmul (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3240 FR32:$src))), (iPTR 0))),
3241 (VMULSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3242 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3243 (fdiv (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3244 FR32:$src))), (iPTR 0))),
3245 (VDIVSSrr_Int v4f32:$dst, (COPY_TO_REGCLASS FR32:$src, VR128))>;
3248 // Patterns used to select SSE scalar fp arithmetic instructions from
3249 // a vector packed single/double fp operation followed by a vector insert.
3251 // The effect is that the backend converts the packed fp instruction
3252 // followed by a vector insert into a single SSE scalar fp instruction.
3254 // For example, given the following code:
3255 // __m128 foo(__m128 A, __m128 B) {
3256 // __m128 C = A + B;
3257 // return (__m128) {c[0], a[1], a[2], a[3]};
3260 // previously we generated:
3261 // addps %xmm0, %xmm1
3262 // movss %xmm1, %xmm0
3265 // addss %xmm1, %xmm0
3267 let Predicates = [UseSSE1] in {
3268 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3269 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3270 (ADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3271 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3272 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3273 (SUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3274 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3275 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3276 (MULSSrr_Int v4f32:$dst, v4f32:$src)>;
3277 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3278 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3279 (DIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3282 let Predicates = [UseSSE2] in {
3283 // SSE2 patterns to select scalar double-precision fp arithmetic instructions
3284 // from a packed double-precision fp instruction plus movsd.
3286 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3287 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3288 (ADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3289 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3290 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3291 (SUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3292 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3293 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3294 (MULSDrr_Int v2f64:$dst, v2f64:$src)>;
3295 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3296 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3297 (DIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3300 let Predicates = [HasAVX] in {
3301 // The following patterns select AVX Scalar single/double precision fp
3302 // arithmetic instructions from a packed single precision fp instruction
3303 // plus movss/movsd.
3305 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3306 (fadd (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3307 (VADDSSrr_Int v4f32:$dst, v4f32:$src)>;
3308 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3309 (fsub (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3310 (VSUBSSrr_Int v4f32:$dst, v4f32:$src)>;
3311 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3312 (fmul (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3313 (VMULSSrr_Int v4f32:$dst, v4f32:$src)>;
3314 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3315 (fdiv (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3316 (VDIVSSrr_Int v4f32:$dst, v4f32:$src)>;
3317 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3318 (fadd (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3319 (VADDSDrr_Int v2f64:$dst, v2f64:$src)>;
3320 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3321 (fsub (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3322 (VSUBSDrr_Int v2f64:$dst, v2f64:$src)>;
3323 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3324 (fmul (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3325 (VMULSDrr_Int v2f64:$dst, v2f64:$src)>;
3326 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3327 (fdiv (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3328 (VDIVSDrr_Int v2f64:$dst, v2f64:$src)>;
3332 /// In addition, we also have a special variant of the scalar form here to
3333 /// represent the associated intrinsic operation. This form is unlike the
3334 /// plain scalar form, in that it takes an entire vector (instead of a
3335 /// scalar) and leaves the top elements undefined.
3337 /// And, we have a special variant form for a full-vector intrinsic form.
3339 let Sched = WriteFSqrt in {
3340 def SSE_SQRTPS : OpndItins<
3341 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3344 def SSE_SQRTSS : OpndItins<
3345 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3348 def SSE_SQRTPD : OpndItins<
3349 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3352 def SSE_SQRTSD : OpndItins<
3353 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3357 let Sched = WriteFRsqrt in {
3358 def SSE_RSQRTPS : OpndItins<
3359 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3362 def SSE_RSQRTSS : OpndItins<
3363 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3367 let Sched = WriteFRcp in {
3368 def SSE_RCPP : OpndItins<
3369 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3372 def SSE_RCPS : OpndItins<
3373 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3377 /// sse1_fp_unop_s - SSE1 unops in scalar form.
3378 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
3379 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
3380 let Predicates = [HasAVX], hasSideEffects = 0 in {
3381 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3382 (ins FR32:$src1, FR32:$src2),
3383 !strconcat("v", OpcodeStr,
3384 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3385 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3386 let mayLoad = 1 in {
3387 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3388 (ins FR32:$src1,f32mem:$src2),
3389 !strconcat("v", OpcodeStr,
3390 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3391 []>, VEX_4V, VEX_LIG,
3392 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3393 let isCodeGenOnly = 1 in
3394 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3395 (ins VR128:$src1, ssmem:$src2),
3396 !strconcat("v", OpcodeStr,
3397 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3398 []>, VEX_4V, VEX_LIG,
3399 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3403 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3404 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3405 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3406 // For scalar unary operations, fold a load into the operation
3407 // only in OptForSize mode. It eliminates an instruction, but it also
3408 // eliminates a whole-register clobber (the load), so it introduces a
3409 // partial register update condition.
3410 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3411 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3412 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3413 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3414 let isCodeGenOnly = 1 in {
3415 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3416 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3417 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>,
3418 Sched<[itins.Sched]>;
3419 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3420 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3421 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>,
3422 Sched<[itins.Sched.Folded]>;
3426 /// sse1_fp_unop_s_rw - SSE1 unops where vector form has a read-write operand.
3427 multiclass sse1_fp_unop_rw<bits<8> opc, string OpcodeStr, SDNode OpNode,
3429 let Predicates = [HasAVX], hasSideEffects = 0 in {
3430 def V#NAME#SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst),
3431 (ins FR32:$src1, FR32:$src2),
3432 !strconcat("v", OpcodeStr,
3433 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3434 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3435 let mayLoad = 1 in {
3436 def V#NAME#SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
3437 (ins FR32:$src1,f32mem:$src2),
3438 !strconcat("v", OpcodeStr,
3439 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3440 []>, VEX_4V, VEX_LIG,
3441 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3442 let isCodeGenOnly = 1 in
3443 def V#NAME#SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3444 (ins VR128:$src1, ssmem:$src2),
3445 !strconcat("v", OpcodeStr,
3446 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3447 []>, VEX_4V, VEX_LIG,
3448 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3452 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
3453 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3454 [(set FR32:$dst, (OpNode FR32:$src))]>, Sched<[itins.Sched]>;
3455 // For scalar unary operations, fold a load into the operation
3456 // only in OptForSize mode. It eliminates an instruction, but it also
3457 // eliminates a whole-register clobber (the load), so it introduces a
3458 // partial register update condition.
3459 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3460 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3461 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3462 Requires<[UseSSE1, OptForSize]>, Sched<[itins.Sched.Folded]>;
3463 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3464 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
3465 (ins VR128:$src1, VR128:$src2),
3466 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3467 [], itins.rr>, Sched<[itins.Sched]>;
3468 let mayLoad = 1, hasSideEffects = 0 in
3469 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3470 (ins VR128:$src1, ssmem:$src2),
3471 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
3472 [], itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3476 /// sse1_fp_unop_p - SSE1 unops in packed form.
3477 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3479 let Predicates = [HasAVX] in {
3480 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3481 !strconcat("v", OpcodeStr,
3482 "ps\t{$src, $dst|$dst, $src}"),
3483 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3484 itins.rr>, VEX, Sched<[itins.Sched]>;
3485 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3486 !strconcat("v", OpcodeStr,
3487 "ps\t{$src, $dst|$dst, $src}"),
3488 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3489 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3490 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3491 !strconcat("v", OpcodeStr,
3492 "ps\t{$src, $dst|$dst, $src}"),
3493 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3494 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3495 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3496 !strconcat("v", OpcodeStr,
3497 "ps\t{$src, $dst|$dst, $src}"),
3498 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3499 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3502 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3503 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3504 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3505 Sched<[itins.Sched]>;
3506 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3507 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3508 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3509 Sched<[itins.Sched.Folded]>;
3512 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3513 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3514 Intrinsic V4F32Int, Intrinsic V8F32Int,
3516 let isCodeGenOnly = 1 in {
3517 let Predicates = [HasAVX] in {
3518 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3519 !strconcat("v", OpcodeStr,
3520 "ps\t{$src, $dst|$dst, $src}"),
3521 [(set VR128:$dst, (V4F32Int VR128:$src))],
3522 itins.rr>, VEX, Sched<[itins.Sched]>;
3523 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3524 !strconcat("v", OpcodeStr,
3525 "ps\t{$src, $dst|$dst, $src}"),
3526 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3527 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3528 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3529 !strconcat("v", OpcodeStr,
3530 "ps\t{$src, $dst|$dst, $src}"),
3531 [(set VR256:$dst, (V8F32Int VR256:$src))],
3532 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3533 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3535 !strconcat("v", OpcodeStr,
3536 "ps\t{$src, $dst|$dst, $src}"),
3537 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3538 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3541 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3542 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3543 [(set VR128:$dst, (V4F32Int VR128:$src))],
3544 itins.rr>, Sched<[itins.Sched]>;
3545 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3546 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3547 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3548 itins.rm>, Sched<[itins.Sched.Folded]>;
3549 } // isCodeGenOnly = 1
3552 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3553 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3554 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3555 let Predicates = [HasAVX], hasSideEffects = 0 in {
3556 def V#NAME#SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst),
3557 (ins FR64:$src1, FR64:$src2),
3558 !strconcat("v", OpcodeStr,
3559 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3560 []>, VEX_4V, VEX_LIG, Sched<[itins.Sched]>;
3561 let mayLoad = 1 in {
3562 def V#NAME#SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
3563 (ins FR64:$src1,f64mem:$src2),
3564 !strconcat("v", OpcodeStr,
3565 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3566 []>, VEX_4V, VEX_LIG,
3567 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3568 let isCodeGenOnly = 1 in
3569 def V#NAME#SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3570 (ins VR128:$src1, sdmem:$src2),
3571 !strconcat("v", OpcodeStr,
3572 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3573 []>, VEX_4V, VEX_LIG,
3574 Sched<[itins.Sched.Folded, ReadAfterLd]>;
3578 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3579 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3580 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>,
3581 Sched<[itins.Sched]>;
3582 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3583 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3584 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3585 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3586 Requires<[UseSSE2, OptForSize]>, Sched<[itins.Sched.Folded]>;
3587 let isCodeGenOnly = 1 in {
3588 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3589 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3590 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>,
3591 Sched<[itins.Sched]>;
3592 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3593 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3594 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>,
3595 Sched<[itins.Sched.Folded]>;
3599 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3600 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3601 SDNode OpNode, OpndItins itins> {
3602 let Predicates = [HasAVX] in {
3603 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3604 !strconcat("v", OpcodeStr,
3605 "pd\t{$src, $dst|$dst, $src}"),
3606 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3607 itins.rr>, VEX, Sched<[itins.Sched]>;
3608 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3609 !strconcat("v", OpcodeStr,
3610 "pd\t{$src, $dst|$dst, $src}"),
3611 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3612 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3613 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3614 !strconcat("v", OpcodeStr,
3615 "pd\t{$src, $dst|$dst, $src}"),
3616 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3617 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3618 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3619 !strconcat("v", OpcodeStr,
3620 "pd\t{$src, $dst|$dst, $src}"),
3621 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3622 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3625 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3626 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3627 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3628 Sched<[itins.Sched]>;
3629 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3630 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3631 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3632 Sched<[itins.Sched.Folded]>;
3636 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3638 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3639 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3641 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3643 // Reciprocal approximations. Note that these typically require refinement
3644 // in order to obtain suitable precision.
3645 defm RSQRT : sse1_fp_unop_rw<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3646 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3647 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3648 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3649 defm RCP : sse1_fp_unop_rw<0x53, "rcp", X86frcp, SSE_RCPS>,
3650 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3651 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3652 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3654 let Predicates = [UseAVX] in {
3655 def : Pat<(f32 (fsqrt FR32:$src)),
3656 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3657 def : Pat<(f32 (fsqrt (load addr:$src))),
3658 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3659 Requires<[HasAVX, OptForSize]>;
3660 def : Pat<(f64 (fsqrt FR64:$src)),
3661 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3662 def : Pat<(f64 (fsqrt (load addr:$src))),
3663 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3664 Requires<[HasAVX, OptForSize]>;
3666 def : Pat<(f32 (X86frsqrt FR32:$src)),
3667 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3668 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3669 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3670 Requires<[HasAVX, OptForSize]>;
3672 def : Pat<(f32 (X86frcp FR32:$src)),
3673 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3674 def : Pat<(f32 (X86frcp (load addr:$src))),
3675 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3676 Requires<[HasAVX, OptForSize]>;
3678 let Predicates = [UseAVX] in {
3679 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3680 (COPY_TO_REGCLASS (VSQRTSSr (f32 (IMPLICIT_DEF)),
3681 (COPY_TO_REGCLASS VR128:$src, FR32)),
3683 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3684 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3686 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3687 (COPY_TO_REGCLASS (VSQRTSDr (f64 (IMPLICIT_DEF)),
3688 (COPY_TO_REGCLASS VR128:$src, FR64)),
3690 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3691 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3694 let Predicates = [HasAVX] in {
3695 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3696 (COPY_TO_REGCLASS (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3697 (COPY_TO_REGCLASS VR128:$src, FR32)),
3699 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3700 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3702 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3703 (COPY_TO_REGCLASS (VRCPSSr (f32 (IMPLICIT_DEF)),
3704 (COPY_TO_REGCLASS VR128:$src, FR32)),
3706 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3707 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3710 // Reciprocal approximations. Note that these typically require refinement
3711 // in order to obtain suitable precision.
3712 let Predicates = [UseSSE1] in {
3713 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3714 (RSQRTSSr_Int VR128:$src, VR128:$src)>;
3715 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3716 (RCPSSr_Int VR128:$src, VR128:$src)>;
3719 // There is no f64 version of the reciprocal approximation instructions.
3721 //===----------------------------------------------------------------------===//
3722 // SSE 1 & 2 - Non-temporal stores
3723 //===----------------------------------------------------------------------===//
3725 let AddedComplexity = 400 in { // Prefer non-temporal versions
3726 let SchedRW = [WriteStore] in {
3727 let Predicates = [HasAVX, NoVLX] in {
3728 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3729 (ins f128mem:$dst, VR128:$src),
3730 "movntps\t{$src, $dst|$dst, $src}",
3731 [(alignednontemporalstore (v4f32 VR128:$src),
3733 IIC_SSE_MOVNT>, VEX;
3734 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3735 (ins f128mem:$dst, VR128:$src),
3736 "movntpd\t{$src, $dst|$dst, $src}",
3737 [(alignednontemporalstore (v2f64 VR128:$src),
3739 IIC_SSE_MOVNT>, VEX;
3741 let ExeDomain = SSEPackedInt in
3742 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3743 (ins f128mem:$dst, VR128:$src),
3744 "movntdq\t{$src, $dst|$dst, $src}",
3745 [(alignednontemporalstore (v2i64 VR128:$src),
3747 IIC_SSE_MOVNT>, VEX;
3749 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3750 (ins f256mem:$dst, VR256:$src),
3751 "movntps\t{$src, $dst|$dst, $src}",
3752 [(alignednontemporalstore (v8f32 VR256:$src),
3754 IIC_SSE_MOVNT>, VEX, VEX_L;
3755 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3756 (ins f256mem:$dst, VR256:$src),
3757 "movntpd\t{$src, $dst|$dst, $src}",
3758 [(alignednontemporalstore (v4f64 VR256:$src),
3760 IIC_SSE_MOVNT>, VEX, VEX_L;
3761 let ExeDomain = SSEPackedInt in
3762 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3763 (ins f256mem:$dst, VR256:$src),
3764 "movntdq\t{$src, $dst|$dst, $src}",
3765 [(alignednontemporalstore (v4i64 VR256:$src),
3767 IIC_SSE_MOVNT>, VEX, VEX_L;
3770 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3771 "movntps\t{$src, $dst|$dst, $src}",
3772 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3774 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3775 "movntpd\t{$src, $dst|$dst, $src}",
3776 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3779 let ExeDomain = SSEPackedInt in
3780 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3781 "movntdq\t{$src, $dst|$dst, $src}",
3782 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3785 // There is no AVX form for instructions below this point
3786 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3787 "movnti{l}\t{$src, $dst|$dst, $src}",
3788 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3790 PS, Requires<[HasSSE2]>;
3791 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3792 "movnti{q}\t{$src, $dst|$dst, $src}",
3793 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3795 PS, Requires<[HasSSE2]>;
3796 } // SchedRW = [WriteStore]
3798 } // AddedComplexity
3800 //===----------------------------------------------------------------------===//
3801 // SSE 1 & 2 - Prefetch and memory fence
3802 //===----------------------------------------------------------------------===//
3804 // Prefetch intrinsic.
3805 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3806 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3807 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3808 IIC_SSE_PREFETCH>, TB;
3809 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3810 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3811 IIC_SSE_PREFETCH>, TB;
3812 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3813 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3814 IIC_SSE_PREFETCH>, TB;
3815 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3816 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3817 IIC_SSE_PREFETCH>, TB;
3820 // FIXME: How should flush instruction be modeled?
3821 let SchedRW = [WriteLoad] in {
3823 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3824 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3825 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3828 let SchedRW = [WriteNop] in {
3829 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3830 // was introduced with SSE2, it's backward compatible.
3831 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3832 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3833 OBXS, Requires<[HasSSE2]>;
3836 let SchedRW = [WriteFence] in {
3837 // Load, store, and memory fence
3838 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3839 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3840 TB, Requires<[HasSSE1]>;
3841 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3842 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3843 TB, Requires<[HasSSE2]>;
3844 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3845 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3846 TB, Requires<[HasSSE2]>;
3849 def : Pat<(X86SFence), (SFENCE)>;
3850 def : Pat<(X86LFence), (LFENCE)>;
3851 def : Pat<(X86MFence), (MFENCE)>;
3853 //===----------------------------------------------------------------------===//
3854 // SSE 1 & 2 - Load/Store XCSR register
3855 //===----------------------------------------------------------------------===//
3857 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3858 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3859 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3860 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3861 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3862 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3864 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3865 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3866 IIC_SSE_LDMXCSR>, Sched<[WriteLoad]>;
3867 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3868 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3869 IIC_SSE_STMXCSR>, Sched<[WriteStore]>;
3871 //===---------------------------------------------------------------------===//
3872 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3873 //===---------------------------------------------------------------------===//
3875 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3877 let neverHasSideEffects = 1, SchedRW = [WriteMove] in {
3878 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3879 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3881 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3882 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3884 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3885 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3887 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3888 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3893 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3894 SchedRW = [WriteMove] in {
3895 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3896 "movdqa\t{$src, $dst|$dst, $src}", [],
3899 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3900 "movdqa\t{$src, $dst|$dst, $src}", [],
3901 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3902 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3903 "movdqu\t{$src, $dst|$dst, $src}", [],
3906 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3907 "movdqu\t{$src, $dst|$dst, $src}", [],
3908 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3911 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3912 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3913 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3914 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3916 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3917 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3919 let Predicates = [HasAVX] in {
3920 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3921 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3923 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3924 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3929 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3930 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3931 (ins i128mem:$dst, VR128:$src),
3932 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3934 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3935 (ins i256mem:$dst, VR256:$src),
3936 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3938 let Predicates = [HasAVX] in {
3939 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3940 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3942 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3943 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3948 let SchedRW = [WriteMove] in {
3949 let neverHasSideEffects = 1 in
3950 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3951 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3953 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3954 "movdqu\t{$src, $dst|$dst, $src}",
3955 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3958 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3959 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3960 "movdqa\t{$src, $dst|$dst, $src}", [],
3963 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3964 "movdqu\t{$src, $dst|$dst, $src}",
3965 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3969 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3970 neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
3971 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3972 "movdqa\t{$src, $dst|$dst, $src}",
3973 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3975 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3976 "movdqu\t{$src, $dst|$dst, $src}",
3977 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3979 XS, Requires<[UseSSE2]>;
3982 let mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
3983 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3984 "movdqa\t{$src, $dst|$dst, $src}",
3985 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3987 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3988 "movdqu\t{$src, $dst|$dst, $src}",
3989 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3991 XS, Requires<[UseSSE2]>;
3994 } // ExeDomain = SSEPackedInt
3996 let Predicates = [HasAVX] in {
3997 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3998 (VMOVDQUmr addr:$dst, VR128:$src)>;
3999 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
4000 (VMOVDQUYmr addr:$dst, VR256:$src)>;
4002 let Predicates = [UseSSE2] in
4003 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
4004 (MOVDQUmr addr:$dst, VR128:$src)>;
4006 //===---------------------------------------------------------------------===//
4007 // SSE2 - Packed Integer Arithmetic Instructions
4008 //===---------------------------------------------------------------------===//
4010 let Sched = WriteVecIMul in
4011 def SSE_PMADD : OpndItins<
4012 IIC_SSE_PMADD, IIC_SSE_PMADD
4015 let ExeDomain = SSEPackedInt in { // SSE integer instructions
4017 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
4018 RegisterClass RC, PatFrag memop_frag,
4019 X86MemOperand x86memop,
4021 bit IsCommutable = 0,
4023 let isCommutable = IsCommutable in
4024 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4025 (ins RC:$src1, RC:$src2),
4027 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4028 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4029 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
4030 Sched<[itins.Sched]>;
4031 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4032 (ins RC:$src1, x86memop:$src2),
4034 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4035 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4036 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
4037 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
4040 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
4041 Intrinsic IntId256, OpndItins itins,
4042 bit IsCommutable = 0> {
4043 let Predicates = [HasAVX] in
4044 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
4045 VR128, loadv2i64, i128mem, itins,
4046 IsCommutable, 0>, VEX_4V;
4048 let Constraints = "$src1 = $dst" in
4049 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
4050 i128mem, itins, IsCommutable, 1>;
4052 let Predicates = [HasAVX2] in
4053 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
4054 VR256, loadv4i64, i256mem, itins,
4055 IsCommutable, 0>, VEX_4V, VEX_L;
4058 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
4059 string OpcodeStr, SDNode OpNode,
4060 SDNode OpNode2, RegisterClass RC,
4061 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
4062 ShiftOpndItins itins,
4064 // src2 is always 128-bit
4065 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4066 (ins RC:$src1, VR128:$src2),
4068 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4069 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4070 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
4071 itins.rr>, Sched<[WriteVecShift]>;
4072 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4073 (ins RC:$src1, i128mem:$src2),
4075 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4076 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4077 [(set RC:$dst, (DstVT (OpNode RC:$src1,
4078 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>,
4079 Sched<[WriteVecShiftLd, ReadAfterLd]>;
4080 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
4081 (ins RC:$src1, i8imm:$src2),
4083 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4084 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4085 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
4086 Sched<[WriteVecShift]>;
4089 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
4090 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
4091 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
4092 PatFrag memop_frag, X86MemOperand x86memop,
4094 bit IsCommutable = 0, bit Is2Addr = 1> {
4095 let isCommutable = IsCommutable in
4096 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
4097 (ins RC:$src1, RC:$src2),
4099 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4100 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4101 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
4102 Sched<[itins.Sched]>;
4103 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
4104 (ins RC:$src1, x86memop:$src2),
4106 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4107 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4108 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4109 (bitconvert (memop_frag addr:$src2)))))]>,
4110 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4112 } // ExeDomain = SSEPackedInt
4114 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4115 SSE_INTALU_ITINS_P, 1>;
4116 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4117 SSE_INTALU_ITINS_P, 1>;
4118 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4119 SSE_INTALU_ITINS_P, 1>;
4120 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4121 SSE_INTALUQ_ITINS_P, 1>;
4122 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4123 SSE_INTMUL_ITINS_P, 1>;
4124 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4125 SSE_INTMUL_ITINS_P, 1>;
4126 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4127 SSE_INTMUL_ITINS_P, 1>;
4128 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4129 SSE_INTALU_ITINS_P, 0>;
4130 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4131 SSE_INTALU_ITINS_P, 0>;
4132 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4133 SSE_INTALU_ITINS_P, 0>;
4134 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4135 SSE_INTALUQ_ITINS_P, 0>;
4136 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4137 SSE_INTALU_ITINS_P, 0>;
4138 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4139 SSE_INTALU_ITINS_P, 0>;
4140 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4141 SSE_INTALU_ITINS_P, 1>;
4142 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4143 SSE_INTALU_ITINS_P, 1>;
4144 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4145 SSE_INTALU_ITINS_P, 1>;
4146 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4147 SSE_INTALU_ITINS_P, 1>;
4150 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4151 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4152 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4153 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4154 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4155 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4156 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4157 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4158 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4159 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4160 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4161 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4162 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4163 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4164 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4165 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4166 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4167 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4168 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4169 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4171 let Predicates = [HasAVX] in
4172 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4173 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4175 let Predicates = [HasAVX2] in
4176 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4177 VR256, loadv4i64, i256mem,
4178 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4179 let Constraints = "$src1 = $dst" in
4180 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4181 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4183 //===---------------------------------------------------------------------===//
4184 // SSE2 - Packed Integer Logical Instructions
4185 //===---------------------------------------------------------------------===//
4187 let Predicates = [HasAVX] in {
4188 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4189 VR128, v8i16, v8i16, bc_v8i16,
4190 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4191 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4192 VR128, v4i32, v4i32, bc_v4i32,
4193 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4194 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4195 VR128, v2i64, v2i64, bc_v2i64,
4196 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4198 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4199 VR128, v8i16, v8i16, bc_v8i16,
4200 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4201 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4202 VR128, v4i32, v4i32, bc_v4i32,
4203 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4204 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4205 VR128, v2i64, v2i64, bc_v2i64,
4206 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4208 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4209 VR128, v8i16, v8i16, bc_v8i16,
4210 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4211 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4212 VR128, v4i32, v4i32, bc_v4i32,
4213 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4215 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4216 // 128-bit logical shifts.
4217 def VPSLLDQri : PDIi8<0x73, MRM7r,
4218 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4219 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4221 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
4223 def VPSRLDQri : PDIi8<0x73, MRM3r,
4224 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4225 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4227 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
4229 // PSRADQri doesn't exist in SSE[1-3].
4231 } // Predicates = [HasAVX]
4233 let Predicates = [HasAVX2] in {
4234 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4235 VR256, v16i16, v8i16, bc_v8i16,
4236 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4237 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4238 VR256, v8i32, v4i32, bc_v4i32,
4239 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4240 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4241 VR256, v4i64, v2i64, bc_v2i64,
4242 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4244 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4245 VR256, v16i16, v8i16, bc_v8i16,
4246 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4247 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4248 VR256, v8i32, v4i32, bc_v4i32,
4249 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4250 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4251 VR256, v4i64, v2i64, bc_v2i64,
4252 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4254 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4255 VR256, v16i16, v8i16, bc_v8i16,
4256 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4257 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4258 VR256, v8i32, v4i32, bc_v4i32,
4259 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4261 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4262 // 256-bit logical shifts.
4263 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4264 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4265 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4267 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
4269 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4270 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
4271 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4273 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
4275 // PSRADQYri doesn't exist in SSE[1-3].
4277 } // Predicates = [HasAVX2]
4279 let Constraints = "$src1 = $dst" in {
4280 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4281 VR128, v8i16, v8i16, bc_v8i16,
4282 SSE_INTSHIFT_ITINS_P>;
4283 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4284 VR128, v4i32, v4i32, bc_v4i32,
4285 SSE_INTSHIFT_ITINS_P>;
4286 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4287 VR128, v2i64, v2i64, bc_v2i64,
4288 SSE_INTSHIFT_ITINS_P>;
4290 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4291 VR128, v8i16, v8i16, bc_v8i16,
4292 SSE_INTSHIFT_ITINS_P>;
4293 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4294 VR128, v4i32, v4i32, bc_v4i32,
4295 SSE_INTSHIFT_ITINS_P>;
4296 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4297 VR128, v2i64, v2i64, bc_v2i64,
4298 SSE_INTSHIFT_ITINS_P>;
4300 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4301 VR128, v8i16, v8i16, bc_v8i16,
4302 SSE_INTSHIFT_ITINS_P>;
4303 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4304 VR128, v4i32, v4i32, bc_v4i32,
4305 SSE_INTSHIFT_ITINS_P>;
4307 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4308 // 128-bit logical shifts.
4309 def PSLLDQri : PDIi8<0x73, MRM7r,
4310 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4311 "pslldq\t{$src2, $dst|$dst, $src2}",
4313 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))],
4314 IIC_SSE_INTSHDQ_P_RI>;
4315 def PSRLDQri : PDIi8<0x73, MRM3r,
4316 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4317 "psrldq\t{$src2, $dst|$dst, $src2}",
4319 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))],
4320 IIC_SSE_INTSHDQ_P_RI>;
4321 // PSRADQri doesn't exist in SSE[1-3].
4323 } // Constraints = "$src1 = $dst"
4325 let Predicates = [HasAVX] in {
4326 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4327 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4328 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4329 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4330 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4331 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4333 // Shift up / down and insert zero's.
4334 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4335 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4336 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4337 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4340 let Predicates = [HasAVX2] in {
4341 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4342 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4343 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4344 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4347 let Predicates = [UseSSE2] in {
4348 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4349 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4350 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4351 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4352 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4353 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4355 // Shift up / down and insert zero's.
4356 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4357 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4358 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4359 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4362 //===---------------------------------------------------------------------===//
4363 // SSE2 - Packed Integer Comparison Instructions
4364 //===---------------------------------------------------------------------===//
4366 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4367 SSE_INTALU_ITINS_P, 1>;
4368 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4369 SSE_INTALU_ITINS_P, 1>;
4370 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4371 SSE_INTALU_ITINS_P, 1>;
4372 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4373 SSE_INTALU_ITINS_P, 0>;
4374 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4375 SSE_INTALU_ITINS_P, 0>;
4376 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4377 SSE_INTALU_ITINS_P, 0>;
4379 //===---------------------------------------------------------------------===//
4380 // SSE2 - Packed Integer Shuffle Instructions
4381 //===---------------------------------------------------------------------===//
4383 let ExeDomain = SSEPackedInt in {
4384 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4386 let Predicates = [HasAVX] in {
4387 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4388 (ins VR128:$src1, i8imm:$src2),
4389 !strconcat("v", OpcodeStr,
4390 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4392 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4393 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4394 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4395 (ins i128mem:$src1, i8imm:$src2),
4396 !strconcat("v", OpcodeStr,
4397 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4399 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4400 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4401 Sched<[WriteShuffleLd]>;
4404 let Predicates = [HasAVX2] in {
4405 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4406 (ins VR256:$src1, i8imm:$src2),
4407 !strconcat("v", OpcodeStr,
4408 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4410 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4411 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4412 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4413 (ins i256mem:$src1, i8imm:$src2),
4414 !strconcat("v", OpcodeStr,
4415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4417 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4418 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4419 Sched<[WriteShuffleLd]>;
4422 let Predicates = [UseSSE2] in {
4423 def ri : Ii8<0x70, MRMSrcReg,
4424 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4425 !strconcat(OpcodeStr,
4426 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4428 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4429 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4430 def mi : Ii8<0x70, MRMSrcMem,
4431 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4432 !strconcat(OpcodeStr,
4433 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4435 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4436 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4437 Sched<[WriteShuffleLd, ReadAfterLd]>;
4440 } // ExeDomain = SSEPackedInt
4442 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4443 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4444 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4446 let Predicates = [HasAVX] in {
4447 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4448 (VPSHUFDmi addr:$src1, imm:$imm)>;
4449 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4450 (VPSHUFDri VR128:$src1, imm:$imm)>;
4453 let Predicates = [UseSSE2] in {
4454 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4455 (PSHUFDmi addr:$src1, imm:$imm)>;
4456 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4457 (PSHUFDri VR128:$src1, imm:$imm)>;
4460 //===---------------------------------------------------------------------===//
4461 // Packed Integer Pack Instructions (SSE & AVX)
4462 //===---------------------------------------------------------------------===//
4464 let ExeDomain = SSEPackedInt in {
4465 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4466 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4468 def rr : PDI<opc, MRMSrcReg,
4469 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4471 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4472 !strconcat(OpcodeStr,
4473 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4475 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4476 Sched<[WriteShuffle]>;
4477 def rm : PDI<opc, MRMSrcMem,
4478 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4480 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4481 !strconcat(OpcodeStr,
4482 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4484 (OutVT (OpNode VR128:$src1,
4485 (bc_frag (memopv2i64 addr:$src2)))))]>,
4486 Sched<[WriteShuffleLd, ReadAfterLd]>;
4489 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4490 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4491 def Yrr : PDI<opc, MRMSrcReg,
4492 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4493 !strconcat(OpcodeStr,
4494 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4496 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4497 Sched<[WriteShuffle]>;
4498 def Yrm : PDI<opc, MRMSrcMem,
4499 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4500 !strconcat(OpcodeStr,
4501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4503 (OutVT (OpNode VR256:$src1,
4504 (bc_frag (memopv4i64 addr:$src2)))))]>,
4505 Sched<[WriteShuffleLd, ReadAfterLd]>;
4508 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4509 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4511 def rr : SS48I<opc, MRMSrcReg,
4512 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4514 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4515 !strconcat(OpcodeStr,
4516 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4518 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4519 Sched<[WriteShuffle]>;
4520 def rm : SS48I<opc, MRMSrcMem,
4521 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4523 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4524 !strconcat(OpcodeStr,
4525 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4527 (OutVT (OpNode VR128:$src1,
4528 (bc_frag (memopv2i64 addr:$src2)))))]>,
4529 Sched<[WriteShuffleLd, ReadAfterLd]>;
4532 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4533 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4534 def Yrr : SS48I<opc, MRMSrcReg,
4535 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4536 !strconcat(OpcodeStr,
4537 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4539 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4540 Sched<[WriteShuffle]>;
4541 def Yrm : SS48I<opc, MRMSrcMem,
4542 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4543 !strconcat(OpcodeStr,
4544 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4546 (OutVT (OpNode VR256:$src1,
4547 (bc_frag (memopv4i64 addr:$src2)))))]>,
4548 Sched<[WriteShuffleLd, ReadAfterLd]>;
4551 let Predicates = [HasAVX] in {
4552 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4553 bc_v8i16, 0>, VEX_4V;
4554 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4555 bc_v4i32, 0>, VEX_4V;
4557 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4558 bc_v8i16, 0>, VEX_4V;
4559 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4560 bc_v4i32, 0>, VEX_4V;
4563 let Predicates = [HasAVX2] in {
4564 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4565 bc_v16i16>, VEX_4V, VEX_L;
4566 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4567 bc_v8i32>, VEX_4V, VEX_L;
4569 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4570 bc_v16i16>, VEX_4V, VEX_L;
4571 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4572 bc_v8i32>, VEX_4V, VEX_L;
4575 let Constraints = "$src1 = $dst" in {
4576 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4578 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4581 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4584 let Predicates = [HasSSE41] in
4585 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4588 } // ExeDomain = SSEPackedInt
4590 //===---------------------------------------------------------------------===//
4591 // SSE2 - Packed Integer Unpack Instructions
4592 //===---------------------------------------------------------------------===//
4594 let ExeDomain = SSEPackedInt in {
4595 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4596 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4597 def rr : PDI<opc, MRMSrcReg,
4598 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4600 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4601 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4602 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4603 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4604 def rm : PDI<opc, MRMSrcMem,
4605 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4607 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4608 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4609 [(set VR128:$dst, (OpNode VR128:$src1,
4610 (bc_frag (memopv2i64
4613 Sched<[WriteShuffleLd, ReadAfterLd]>;
4616 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4617 SDNode OpNode, PatFrag bc_frag> {
4618 def Yrr : PDI<opc, MRMSrcReg,
4619 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4620 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4621 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4622 Sched<[WriteShuffle]>;
4623 def Yrm : PDI<opc, MRMSrcMem,
4624 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4625 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4626 [(set VR256:$dst, (OpNode VR256:$src1,
4627 (bc_frag (memopv4i64 addr:$src2))))]>,
4628 Sched<[WriteShuffleLd, ReadAfterLd]>;
4631 let Predicates = [HasAVX] in {
4632 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4633 bc_v16i8, 0>, VEX_4V;
4634 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4635 bc_v8i16, 0>, VEX_4V;
4636 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4637 bc_v4i32, 0>, VEX_4V;
4638 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4639 bc_v2i64, 0>, VEX_4V;
4641 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4642 bc_v16i8, 0>, VEX_4V;
4643 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4644 bc_v8i16, 0>, VEX_4V;
4645 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4646 bc_v4i32, 0>, VEX_4V;
4647 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4648 bc_v2i64, 0>, VEX_4V;
4651 let Predicates = [HasAVX2] in {
4652 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4653 bc_v32i8>, VEX_4V, VEX_L;
4654 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4655 bc_v16i16>, VEX_4V, VEX_L;
4656 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4657 bc_v8i32>, VEX_4V, VEX_L;
4658 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4659 bc_v4i64>, VEX_4V, VEX_L;
4661 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4662 bc_v32i8>, VEX_4V, VEX_L;
4663 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4664 bc_v16i16>, VEX_4V, VEX_L;
4665 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4666 bc_v8i32>, VEX_4V, VEX_L;
4667 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4668 bc_v4i64>, VEX_4V, VEX_L;
4671 let Constraints = "$src1 = $dst" in {
4672 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4674 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4676 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4678 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4681 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4683 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4685 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4687 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4690 } // ExeDomain = SSEPackedInt
4692 //===---------------------------------------------------------------------===//
4693 // SSE2 - Packed Integer Extract and Insert
4694 //===---------------------------------------------------------------------===//
4696 let ExeDomain = SSEPackedInt in {
4697 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4698 def rri : Ii8<0xC4, MRMSrcReg,
4699 (outs VR128:$dst), (ins VR128:$src1,
4700 GR32orGR64:$src2, i32i8imm:$src3),
4702 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4703 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4705 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4706 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4707 def rmi : Ii8<0xC4, MRMSrcMem,
4708 (outs VR128:$dst), (ins VR128:$src1,
4709 i16mem:$src2, i32i8imm:$src3),
4711 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4712 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4714 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4715 imm:$src3))], IIC_SSE_PINSRW>,
4716 Sched<[WriteShuffleLd, ReadAfterLd]>;
4720 let Predicates = [HasAVX] in
4721 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4722 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4723 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4724 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4725 imm:$src2))]>, PD, VEX,
4726 Sched<[WriteShuffle]>;
4727 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4728 (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),
4729 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4730 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4731 imm:$src2))], IIC_SSE_PEXTRW>,
4732 Sched<[WriteShuffleLd, ReadAfterLd]>;
4735 let Predicates = [HasAVX] in
4736 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4738 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4739 defm PINSRW : sse2_pinsrw, PD;
4741 } // ExeDomain = SSEPackedInt
4743 //===---------------------------------------------------------------------===//
4744 // SSE2 - Packed Mask Creation
4745 //===---------------------------------------------------------------------===//
4747 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4749 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4751 "pmovmskb\t{$src, $dst|$dst, $src}",
4752 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4753 IIC_SSE_MOVMSK>, VEX;
4755 let Predicates = [HasAVX2] in {
4756 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4758 "pmovmskb\t{$src, $dst|$dst, $src}",
4759 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4763 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4764 "pmovmskb\t{$src, $dst|$dst, $src}",
4765 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4768 } // ExeDomain = SSEPackedInt
4770 //===---------------------------------------------------------------------===//
4771 // SSE2 - Conditional Store
4772 //===---------------------------------------------------------------------===//
4774 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4776 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4777 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4778 (ins VR128:$src, VR128:$mask),
4779 "maskmovdqu\t{$mask, $src|$src, $mask}",
4780 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4781 IIC_SSE_MASKMOV>, VEX;
4782 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4783 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4784 (ins VR128:$src, VR128:$mask),
4785 "maskmovdqu\t{$mask, $src|$src, $mask}",
4786 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4787 IIC_SSE_MASKMOV>, VEX;
4789 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4790 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4791 "maskmovdqu\t{$mask, $src|$src, $mask}",
4792 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4794 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4795 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4796 "maskmovdqu\t{$mask, $src|$src, $mask}",
4797 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4800 } // ExeDomain = SSEPackedInt
4802 //===---------------------------------------------------------------------===//
4803 // SSE2 - Move Doubleword
4804 //===---------------------------------------------------------------------===//
4806 //===---------------------------------------------------------------------===//
4807 // Move Int Doubleword to Packed Double Int
4809 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4810 "movd\t{$src, $dst|$dst, $src}",
4812 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4813 VEX, Sched<[WriteMove]>;
4814 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4815 "movd\t{$src, $dst|$dst, $src}",
4817 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4819 VEX, Sched<[WriteLoad]>;
4820 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4821 "movq\t{$src, $dst|$dst, $src}",
4823 (v2i64 (scalar_to_vector GR64:$src)))],
4824 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4825 let isCodeGenOnly = 1 in
4826 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4827 "movq\t{$src, $dst|$dst, $src}",
4828 [(set FR64:$dst, (bitconvert GR64:$src))],
4829 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4831 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4832 "movd\t{$src, $dst|$dst, $src}",
4834 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4836 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4837 "movd\t{$src, $dst|$dst, $src}",
4839 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4840 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4841 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4842 "mov{d|q}\t{$src, $dst|$dst, $src}",
4844 (v2i64 (scalar_to_vector GR64:$src)))],
4845 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4846 let isCodeGenOnly = 1 in
4847 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4848 "mov{d|q}\t{$src, $dst|$dst, $src}",
4849 [(set FR64:$dst, (bitconvert GR64:$src))],
4850 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4852 //===---------------------------------------------------------------------===//
4853 // Move Int Doubleword to Single Scalar
4855 let isCodeGenOnly = 1 in {
4856 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4857 "movd\t{$src, $dst|$dst, $src}",
4858 [(set FR32:$dst, (bitconvert GR32:$src))],
4859 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4861 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4862 "movd\t{$src, $dst|$dst, $src}",
4863 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4865 VEX, Sched<[WriteLoad]>;
4866 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4867 "movd\t{$src, $dst|$dst, $src}",
4868 [(set FR32:$dst, (bitconvert GR32:$src))],
4869 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4871 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4872 "movd\t{$src, $dst|$dst, $src}",
4873 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4874 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4877 //===---------------------------------------------------------------------===//
4878 // Move Packed Doubleword Int to Packed Double Int
4880 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4881 "movd\t{$src, $dst|$dst, $src}",
4882 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4883 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4885 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4886 (ins i32mem:$dst, VR128:$src),
4887 "movd\t{$src, $dst|$dst, $src}",
4888 [(store (i32 (vector_extract (v4i32 VR128:$src),
4889 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4890 VEX, Sched<[WriteStore]>;
4891 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4892 "movd\t{$src, $dst|$dst, $src}",
4893 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4894 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4896 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4897 "movd\t{$src, $dst|$dst, $src}",
4898 [(store (i32 (vector_extract (v4i32 VR128:$src),
4899 (iPTR 0))), addr:$dst)],
4900 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4902 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4903 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4905 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4906 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4908 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4909 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4911 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4912 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4914 //===---------------------------------------------------------------------===//
4915 // Move Packed Doubleword Int first element to Doubleword Int
4917 let SchedRW = [WriteMove] in {
4918 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4919 "movq\t{$src, $dst|$dst, $src}",
4920 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4925 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4926 "mov{d|q}\t{$src, $dst|$dst, $src}",
4927 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4932 //===---------------------------------------------------------------------===//
4933 // Bitcast FR64 <-> GR64
4935 let isCodeGenOnly = 1 in {
4936 let Predicates = [UseAVX] in
4937 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4938 "movq\t{$src, $dst|$dst, $src}",
4939 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4940 VEX, Sched<[WriteLoad]>;
4941 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4942 "movq\t{$src, $dst|$dst, $src}",
4943 [(set GR64:$dst, (bitconvert FR64:$src))],
4944 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4945 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4946 "movq\t{$src, $dst|$dst, $src}",
4947 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4948 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4950 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4951 "movq\t{$src, $dst|$dst, $src}",
4952 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4953 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4954 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4955 "mov{d|q}\t{$src, $dst|$dst, $src}",
4956 [(set GR64:$dst, (bitconvert FR64:$src))],
4957 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4958 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4959 "movq\t{$src, $dst|$dst, $src}",
4960 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4961 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4964 //===---------------------------------------------------------------------===//
4965 // Move Scalar Single to Double Int
4967 let isCodeGenOnly = 1 in {
4968 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4969 "movd\t{$src, $dst|$dst, $src}",
4970 [(set GR32:$dst, (bitconvert FR32:$src))],
4971 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4972 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4973 "movd\t{$src, $dst|$dst, $src}",
4974 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4975 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4976 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4977 "movd\t{$src, $dst|$dst, $src}",
4978 [(set GR32:$dst, (bitconvert FR32:$src))],
4979 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4980 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4981 "movd\t{$src, $dst|$dst, $src}",
4982 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4983 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4986 //===---------------------------------------------------------------------===//
4987 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4989 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4990 let AddedComplexity = 15 in {
4991 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4992 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4993 [(set VR128:$dst, (v2i64 (X86vzmovl
4994 (v2i64 (scalar_to_vector GR64:$src)))))],
4997 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4998 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4999 [(set VR128:$dst, (v2i64 (X86vzmovl
5000 (v2i64 (scalar_to_vector GR64:$src)))))],
5003 } // isCodeGenOnly, SchedRW
5005 let Predicates = [UseAVX] in {
5006 let AddedComplexity = 15 in
5007 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5008 (VMOVDI2PDIrr GR32:$src)>;
5010 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
5011 let AddedComplexity = 20 in {
5012 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5013 (VMOVDI2PDIrm addr:$src)>;
5014 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5015 (VMOVDI2PDIrm addr:$src)>;
5016 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5017 (VMOVDI2PDIrm addr:$src)>;
5019 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
5020 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
5021 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
5022 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
5023 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5024 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
5025 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
5028 let Predicates = [UseSSE2] in {
5029 let AddedComplexity = 15 in
5030 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
5031 (MOVDI2PDIrr GR32:$src)>;
5033 let AddedComplexity = 20 in {
5034 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
5035 (MOVDI2PDIrm addr:$src)>;
5036 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
5037 (MOVDI2PDIrm addr:$src)>;
5038 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
5039 (MOVDI2PDIrm addr:$src)>;
5043 // These are the correct encodings of the instructions so that we know how to
5044 // read correct assembly, even though we continue to emit the wrong ones for
5045 // compatibility with Darwin's buggy assembler.
5046 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5047 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5048 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
5049 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5050 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
5051 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5052 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
5053 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
5054 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
5056 //===---------------------------------------------------------------------===//
5057 // SSE2 - Move Quadword
5058 //===---------------------------------------------------------------------===//
5060 //===---------------------------------------------------------------------===//
5061 // Move Quadword Int to Packed Quadword Int
5064 let SchedRW = [WriteLoad] in {
5065 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5066 "vmovq\t{$src, $dst|$dst, $src}",
5068 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
5069 VEX, Requires<[UseAVX]>;
5070 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5071 "movq\t{$src, $dst|$dst, $src}",
5073 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
5075 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
5078 //===---------------------------------------------------------------------===//
5079 // Move Packed Quadword Int to Quadword Int
5081 let SchedRW = [WriteStore] in {
5082 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5083 "movq\t{$src, $dst|$dst, $src}",
5084 [(store (i64 (vector_extract (v2i64 VR128:$src),
5085 (iPTR 0))), addr:$dst)],
5086 IIC_SSE_MOVDQ>, VEX;
5087 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
5088 "movq\t{$src, $dst|$dst, $src}",
5089 [(store (i64 (vector_extract (v2i64 VR128:$src),
5090 (iPTR 0))), addr:$dst)],
5094 // For disassembler only
5095 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
5096 SchedRW = [WriteVecLogic] in {
5097 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5098 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
5099 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
5100 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
5103 //===---------------------------------------------------------------------===//
5104 // Store / copy lower 64-bits of a XMM register.
5106 let Predicates = [UseAVX] in
5107 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5108 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
5109 let Predicates = [UseSSE2] in
5110 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
5111 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5113 let isCodeGenOnly = 1, AddedComplexity = 20 in {
5114 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5115 "vmovq\t{$src, $dst|$dst, $src}",
5117 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5118 (loadi64 addr:$src))))))],
5120 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5122 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5123 "movq\t{$src, $dst|$dst, $src}",
5125 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5126 (loadi64 addr:$src))))))],
5128 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5131 let Predicates = [UseAVX], AddedComplexity = 20 in {
5132 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5133 (VMOVZQI2PQIrm addr:$src)>;
5134 def : Pat<(v2i64 (X86vzload addr:$src)),
5135 (VMOVZQI2PQIrm addr:$src)>;
5138 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5139 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5140 (MOVZQI2PQIrm addr:$src)>;
5141 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5144 let Predicates = [HasAVX] in {
5145 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5146 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5147 def : Pat<(v4i64 (X86vzload addr:$src)),
5148 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5151 //===---------------------------------------------------------------------===//
5152 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5153 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5155 let SchedRW = [WriteVecLogic] in {
5156 let AddedComplexity = 15 in
5157 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5158 "vmovq\t{$src, $dst|$dst, $src}",
5159 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5161 XS, VEX, Requires<[UseAVX]>;
5162 let AddedComplexity = 15 in
5163 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5164 "movq\t{$src, $dst|$dst, $src}",
5165 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5167 XS, Requires<[UseSSE2]>;
5170 let isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5171 let AddedComplexity = 20 in
5172 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5173 "vmovq\t{$src, $dst|$dst, $src}",
5174 [(set VR128:$dst, (v2i64 (X86vzmovl
5175 (loadv2i64 addr:$src))))],
5177 XS, VEX, Requires<[UseAVX]>;
5178 let AddedComplexity = 20 in {
5179 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5180 "movq\t{$src, $dst|$dst, $src}",
5181 [(set VR128:$dst, (v2i64 (X86vzmovl
5182 (loadv2i64 addr:$src))))],
5184 XS, Requires<[UseSSE2]>;
5186 } // isCodeGenOnly, SchedRW
5188 let AddedComplexity = 20 in {
5189 let Predicates = [UseAVX] in {
5190 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5191 (VMOVZPQILo2PQIrr VR128:$src)>;
5193 let Predicates = [UseSSE2] in {
5194 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5195 (MOVZPQILo2PQIrr VR128:$src)>;
5199 //===---------------------------------------------------------------------===//
5200 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5201 //===---------------------------------------------------------------------===//
5202 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5203 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5204 X86MemOperand x86memop> {
5205 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5206 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5207 [(set RC:$dst, (vt (OpNode RC:$src)))],
5208 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5209 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5210 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5211 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5212 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5215 let Predicates = [HasAVX] in {
5216 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5217 v4f32, VR128, loadv4f32, f128mem>, VEX;
5218 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5219 v4f32, VR128, loadv4f32, f128mem>, VEX;
5220 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5221 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5222 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5223 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5225 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5226 memopv4f32, f128mem>;
5227 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5228 memopv4f32, f128mem>;
5230 let Predicates = [HasAVX] in {
5231 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5232 (VMOVSHDUPrr VR128:$src)>;
5233 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5234 (VMOVSHDUPrm addr:$src)>;
5235 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5236 (VMOVSLDUPrr VR128:$src)>;
5237 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5238 (VMOVSLDUPrm addr:$src)>;
5239 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5240 (VMOVSHDUPYrr VR256:$src)>;
5241 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5242 (VMOVSHDUPYrm addr:$src)>;
5243 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5244 (VMOVSLDUPYrr VR256:$src)>;
5245 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5246 (VMOVSLDUPYrm addr:$src)>;
5249 let Predicates = [UseSSE3] in {
5250 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5251 (MOVSHDUPrr VR128:$src)>;
5252 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5253 (MOVSHDUPrm addr:$src)>;
5254 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5255 (MOVSLDUPrr VR128:$src)>;
5256 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5257 (MOVSLDUPrm addr:$src)>;
5260 //===---------------------------------------------------------------------===//
5261 // SSE3 - Replicate Double FP - MOVDDUP
5262 //===---------------------------------------------------------------------===//
5264 multiclass sse3_replicate_dfp<string OpcodeStr> {
5265 let neverHasSideEffects = 1 in
5266 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5267 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5268 [], IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5269 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5270 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5273 (scalar_to_vector (loadf64 addr:$src)))))],
5274 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5277 // FIXME: Merge with above classe when there're patterns for the ymm version
5278 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5279 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5280 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5281 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5282 Sched<[WriteFShuffle]>;
5283 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5284 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5287 (scalar_to_vector (loadf64 addr:$src)))))]>,
5291 let Predicates = [HasAVX] in {
5292 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5293 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5296 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5298 let Predicates = [HasAVX] in {
5299 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5300 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5301 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5302 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5303 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5304 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5305 def : Pat<(X86Movddup (bc_v2f64
5306 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5307 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5310 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5311 (VMOVDDUPYrm addr:$src)>;
5312 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5313 (VMOVDDUPYrm addr:$src)>;
5314 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5315 (VMOVDDUPYrm addr:$src)>;
5316 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5317 (VMOVDDUPYrr VR256:$src)>;
5320 let Predicates = [UseAVX, OptForSize] in {
5321 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5322 (VMOVDDUPrm addr:$src)>;
5323 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5324 (VMOVDDUPrm addr:$src)>;
5327 let Predicates = [UseSSE3] in {
5328 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5329 (MOVDDUPrm addr:$src)>;
5330 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5331 (MOVDDUPrm addr:$src)>;
5332 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5333 (MOVDDUPrm addr:$src)>;
5334 def : Pat<(X86Movddup (bc_v2f64
5335 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5336 (MOVDDUPrm addr:$src)>;
5339 //===---------------------------------------------------------------------===//
5340 // SSE3 - Move Unaligned Integer
5341 //===---------------------------------------------------------------------===//
5343 let SchedRW = [WriteLoad] in {
5344 let Predicates = [HasAVX] in {
5345 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5346 "vlddqu\t{$src, $dst|$dst, $src}",
5347 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5348 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5349 "vlddqu\t{$src, $dst|$dst, $src}",
5350 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5353 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5354 "lddqu\t{$src, $dst|$dst, $src}",
5355 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5359 //===---------------------------------------------------------------------===//
5360 // SSE3 - Arithmetic
5361 //===---------------------------------------------------------------------===//
5363 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5364 X86MemOperand x86memop, OpndItins itins,
5366 def rr : I<0xD0, MRMSrcReg,
5367 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5370 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5371 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5372 Sched<[itins.Sched]>;
5373 def rm : I<0xD0, MRMSrcMem,
5374 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5377 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5378 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>,
5379 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5382 let Predicates = [HasAVX] in {
5383 let ExeDomain = SSEPackedSingle in {
5384 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5385 f128mem, SSE_ALU_F32P, 0>, XD, VEX_4V;
5386 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5387 f256mem, SSE_ALU_F32P, 0>, XD, VEX_4V, VEX_L;
5389 let ExeDomain = SSEPackedDouble in {
5390 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5391 f128mem, SSE_ALU_F64P, 0>, PD, VEX_4V;
5392 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5393 f256mem, SSE_ALU_F64P, 0>, PD, VEX_4V, VEX_L;
5396 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5397 let ExeDomain = SSEPackedSingle in
5398 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5399 f128mem, SSE_ALU_F32P>, XD;
5400 let ExeDomain = SSEPackedDouble in
5401 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5402 f128mem, SSE_ALU_F64P>, PD;
5405 // Patterns used to select 'addsub' instructions.
5406 let Predicates = [HasAVX] in {
5407 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5408 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5409 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5410 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5411 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5412 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5413 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5414 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5416 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5417 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5418 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 (memop addr:$rhs)))),
5419 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5420 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5421 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5422 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 (memop addr:$rhs)))),
5423 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5426 let Predicates = [UseSSE3] in {
5427 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5428 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5429 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 (memop addr:$rhs)))),
5430 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5431 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5432 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5433 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 (memop addr:$rhs)))),
5434 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5437 //===---------------------------------------------------------------------===//
5438 // SSE3 Instructions
5439 //===---------------------------------------------------------------------===//
5442 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5443 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5444 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5446 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5447 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5448 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5451 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5453 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5454 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5455 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5456 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5458 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5459 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5460 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5462 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5463 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5464 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5467 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5469 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5470 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5471 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5472 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5475 let Predicates = [HasAVX] in {
5476 let ExeDomain = SSEPackedSingle in {
5477 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5478 X86fhadd, 0>, VEX_4V;
5479 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5480 X86fhsub, 0>, VEX_4V;
5481 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5482 X86fhadd, 0>, VEX_4V, VEX_L;
5483 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5484 X86fhsub, 0>, VEX_4V, VEX_L;
5486 let ExeDomain = SSEPackedDouble in {
5487 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5488 X86fhadd, 0>, VEX_4V;
5489 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5490 X86fhsub, 0>, VEX_4V;
5491 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5492 X86fhadd, 0>, VEX_4V, VEX_L;
5493 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5494 X86fhsub, 0>, VEX_4V, VEX_L;
5498 let Constraints = "$src1 = $dst" in {
5499 let ExeDomain = SSEPackedSingle in {
5500 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5501 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5503 let ExeDomain = SSEPackedDouble in {
5504 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5505 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5509 //===---------------------------------------------------------------------===//
5510 // SSSE3 - Packed Absolute Instructions
5511 //===---------------------------------------------------------------------===//
5514 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5515 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5516 Intrinsic IntId128> {
5517 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5519 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5520 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5521 Sched<[WriteVecALU]>;
5523 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5525 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5528 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5529 Sched<[WriteVecALULd]>;
5532 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5533 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5534 Intrinsic IntId256> {
5535 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5537 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5538 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5539 Sched<[WriteVecALU]>;
5541 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5543 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5546 (bitconvert (memopv4i64 addr:$src))))]>,
5547 Sched<[WriteVecALULd]>;
5550 // Helper fragments to match sext vXi1 to vXiY.
5551 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5553 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5554 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5555 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5557 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5558 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5560 let Predicates = [HasAVX] in {
5561 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5562 int_x86_ssse3_pabs_b_128>, VEX;
5563 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5564 int_x86_ssse3_pabs_w_128>, VEX;
5565 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5566 int_x86_ssse3_pabs_d_128>, VEX;
5569 (bc_v2i64 (v16i1sextv16i8)),
5570 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5571 (VPABSBrr128 VR128:$src)>;
5573 (bc_v2i64 (v8i1sextv8i16)),
5574 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5575 (VPABSWrr128 VR128:$src)>;
5577 (bc_v2i64 (v4i1sextv4i32)),
5578 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5579 (VPABSDrr128 VR128:$src)>;
5582 let Predicates = [HasAVX2] in {
5583 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5584 int_x86_avx2_pabs_b>, VEX, VEX_L;
5585 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5586 int_x86_avx2_pabs_w>, VEX, VEX_L;
5587 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5588 int_x86_avx2_pabs_d>, VEX, VEX_L;
5591 (bc_v4i64 (v32i1sextv32i8)),
5592 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5593 (VPABSBrr256 VR256:$src)>;
5595 (bc_v4i64 (v16i1sextv16i16)),
5596 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5597 (VPABSWrr256 VR256:$src)>;
5599 (bc_v4i64 (v8i1sextv8i32)),
5600 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5601 (VPABSDrr256 VR256:$src)>;
5604 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5605 int_x86_ssse3_pabs_b_128>;
5606 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5607 int_x86_ssse3_pabs_w_128>;
5608 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5609 int_x86_ssse3_pabs_d_128>;
5611 let Predicates = [HasSSSE3] in {
5613 (bc_v2i64 (v16i1sextv16i8)),
5614 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5615 (PABSBrr128 VR128:$src)>;
5617 (bc_v2i64 (v8i1sextv8i16)),
5618 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5619 (PABSWrr128 VR128:$src)>;
5621 (bc_v2i64 (v4i1sextv4i32)),
5622 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5623 (PABSDrr128 VR128:$src)>;
5626 //===---------------------------------------------------------------------===//
5627 // SSSE3 - Packed Binary Operator Instructions
5628 //===---------------------------------------------------------------------===//
5630 let Sched = WriteVecALU in {
5631 def SSE_PHADDSUBD : OpndItins<
5632 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5634 def SSE_PHADDSUBSW : OpndItins<
5635 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5637 def SSE_PHADDSUBW : OpndItins<
5638 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5641 let Sched = WriteShuffle in
5642 def SSE_PSHUFB : OpndItins<
5643 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5645 let Sched = WriteVecALU in
5646 def SSE_PSIGN : OpndItins<
5647 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5649 let Sched = WriteVecIMul in
5650 def SSE_PMULHRSW : OpndItins<
5651 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5654 /// SS3I_binop_rm - Simple SSSE3 bin op
5655 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5656 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5657 X86MemOperand x86memop, OpndItins itins,
5659 let isCommutable = 1 in
5660 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5661 (ins RC:$src1, RC:$src2),
5663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5664 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5665 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5666 Sched<[itins.Sched]>;
5667 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5668 (ins RC:$src1, x86memop:$src2),
5670 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5671 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5673 (OpVT (OpNode RC:$src1,
5674 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5675 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5678 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5679 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5680 Intrinsic IntId128, OpndItins itins,
5682 let isCommutable = 1 in
5683 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5684 (ins VR128:$src1, VR128:$src2),
5686 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5687 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5688 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5689 Sched<[itins.Sched]>;
5690 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5691 (ins VR128:$src1, i128mem:$src2),
5693 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5694 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5696 (IntId128 VR128:$src1,
5697 (bitconvert (memopv2i64 addr:$src2))))]>,
5698 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5701 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5703 X86FoldableSchedWrite Sched> {
5704 let isCommutable = 1 in
5705 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5706 (ins VR256:$src1, VR256:$src2),
5707 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5708 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5710 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5711 (ins VR256:$src1, i256mem:$src2),
5712 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5714 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5715 Sched<[Sched.Folded, ReadAfterLd]>;
5718 let ImmT = NoImm, Predicates = [HasAVX] in {
5719 let isCommutable = 0 in {
5720 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5722 SSE_PHADDSUBW, 0>, VEX_4V;
5723 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5725 SSE_PHADDSUBD, 0>, VEX_4V;
5726 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5728 SSE_PHADDSUBW, 0>, VEX_4V;
5729 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5731 SSE_PHADDSUBD, 0>, VEX_4V;
5732 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5734 SSE_PSIGN, 0>, VEX_4V;
5735 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5737 SSE_PSIGN, 0>, VEX_4V;
5738 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5740 SSE_PSIGN, 0>, VEX_4V;
5741 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5743 SSE_PSHUFB, 0>, VEX_4V;
5744 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5745 int_x86_ssse3_phadd_sw_128,
5746 SSE_PHADDSUBSW, 0>, VEX_4V;
5747 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5748 int_x86_ssse3_phsub_sw_128,
5749 SSE_PHADDSUBSW, 0>, VEX_4V;
5750 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5751 int_x86_ssse3_pmadd_ub_sw_128,
5752 SSE_PMADD, 0>, VEX_4V;
5754 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5755 int_x86_ssse3_pmul_hr_sw_128,
5756 SSE_PMULHRSW, 0>, VEX_4V;
5759 let ImmT = NoImm, Predicates = [HasAVX2] in {
5760 let isCommutable = 0 in {
5761 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5763 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5764 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5766 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5767 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5769 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5770 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5772 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5773 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5775 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5776 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5778 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5779 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5781 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5782 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5784 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5785 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5786 int_x86_avx2_phadd_sw,
5787 WriteVecALU>, VEX_4V, VEX_L;
5788 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5789 int_x86_avx2_phsub_sw,
5790 WriteVecALU>, VEX_4V, VEX_L;
5791 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5792 int_x86_avx2_pmadd_ub_sw,
5793 WriteVecIMul>, VEX_4V, VEX_L;
5795 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5796 int_x86_avx2_pmul_hr_sw,
5797 WriteVecIMul>, VEX_4V, VEX_L;
5800 // None of these have i8 immediate fields.
5801 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5802 let isCommutable = 0 in {
5803 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5804 memopv2i64, i128mem, SSE_PHADDSUBW>;
5805 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5806 memopv2i64, i128mem, SSE_PHADDSUBD>;
5807 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5808 memopv2i64, i128mem, SSE_PHADDSUBW>;
5809 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5810 memopv2i64, i128mem, SSE_PHADDSUBD>;
5811 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5812 memopv2i64, i128mem, SSE_PSIGN>;
5813 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5814 memopv2i64, i128mem, SSE_PSIGN>;
5815 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5816 memopv2i64, i128mem, SSE_PSIGN>;
5817 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5818 memopv2i64, i128mem, SSE_PSHUFB>;
5819 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5820 int_x86_ssse3_phadd_sw_128,
5822 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5823 int_x86_ssse3_phsub_sw_128,
5825 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5826 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5828 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5829 int_x86_ssse3_pmul_hr_sw_128,
5833 //===---------------------------------------------------------------------===//
5834 // SSSE3 - Packed Align Instruction Patterns
5835 //===---------------------------------------------------------------------===//
5837 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5838 let neverHasSideEffects = 1 in {
5839 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5840 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5842 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5844 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5845 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5847 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5848 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5850 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5852 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5853 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5857 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5858 let neverHasSideEffects = 1 in {
5859 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5860 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5862 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5863 []>, Sched<[WriteShuffle]>;
5865 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5866 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5868 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5869 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5873 let Predicates = [HasAVX] in
5874 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5875 let Predicates = [HasAVX2] in
5876 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5877 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5878 defm PALIGN : ssse3_palignr<"palignr">;
5880 let Predicates = [HasAVX2] in {
5881 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5882 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5883 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5884 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5885 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5886 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5887 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5888 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5891 let Predicates = [HasAVX] in {
5892 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5893 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5894 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5895 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5896 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5897 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5898 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5899 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5902 let Predicates = [UseSSSE3] in {
5903 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5904 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5905 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5906 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5907 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5908 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5909 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5910 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5913 //===---------------------------------------------------------------------===//
5914 // SSSE3 - Thread synchronization
5915 //===---------------------------------------------------------------------===//
5917 let SchedRW = [WriteSystem] in {
5918 let usesCustomInserter = 1 in {
5919 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5920 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5921 Requires<[HasSSE3]>;
5924 let Uses = [EAX, ECX, EDX] in
5925 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5926 TB, Requires<[HasSSE3]>;
5927 let Uses = [ECX, EAX] in
5928 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5929 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5930 TB, Requires<[HasSSE3]>;
5933 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5934 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5936 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5937 Requires<[Not64BitMode]>;
5938 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5939 Requires<[In64BitMode]>;
5941 //===----------------------------------------------------------------------===//
5942 // SSE4.1 - Packed Move with Sign/Zero Extend
5943 //===----------------------------------------------------------------------===//
5945 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId,
5946 OpndItins itins = DEFAULT_ITINS> {
5947 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5948 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5949 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
5950 Sched<[itins.Sched]>;
5952 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5953 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5955 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))],
5956 itins.rm>, Sched<[itins.Sched.Folded]>;
5959 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5960 Intrinsic IntId, X86FoldableSchedWrite Sched> {
5961 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5962 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5963 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
5965 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5966 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5967 [(set VR256:$dst, (IntId (load addr:$src)))]>,
5968 Sched<[Sched.Folded]>;
5971 let Predicates = [HasAVX] in {
5972 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw",
5973 int_x86_sse41_pmovsxbw,
5974 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5975 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd",
5976 int_x86_sse41_pmovsxwd,
5977 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5978 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq",
5979 int_x86_sse41_pmovsxdq,
5980 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5981 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw",
5982 int_x86_sse41_pmovzxbw,
5983 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5984 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd",
5985 int_x86_sse41_pmovzxwd,
5986 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5987 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq",
5988 int_x86_sse41_pmovzxdq,
5989 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
5992 let Predicates = [HasAVX2] in {
5993 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5994 int_x86_avx2_pmovsxbw,
5995 WriteShuffle>, VEX, VEX_L;
5996 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5997 int_x86_avx2_pmovsxwd,
5998 WriteShuffle>, VEX, VEX_L;
5999 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
6000 int_x86_avx2_pmovsxdq,
6001 WriteShuffle>, VEX, VEX_L;
6002 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
6003 int_x86_avx2_pmovzxbw,
6004 WriteShuffle>, VEX, VEX_L;
6005 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
6006 int_x86_avx2_pmovzxwd,
6007 WriteShuffle>, VEX, VEX_L;
6008 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
6009 int_x86_avx2_pmovzxdq,
6010 WriteShuffle>, VEX, VEX_L;
6013 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw,
6014 SSE_INTALU_ITINS_SHUFF_P>;
6015 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd,
6016 SSE_INTALU_ITINS_SHUFF_P>;
6017 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq,
6018 SSE_INTALU_ITINS_SHUFF_P>;
6019 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw,
6020 SSE_INTALU_ITINS_SHUFF_P>;
6021 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd,
6022 SSE_INTALU_ITINS_SHUFF_P>;
6023 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq,
6024 SSE_INTALU_ITINS_SHUFF_P>;
6026 let Predicates = [HasAVX] in {
6027 // Common patterns involving scalar load.
6028 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6029 (VPMOVSXBWrm addr:$src)>;
6030 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6031 (VPMOVSXBWrm addr:$src)>;
6032 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6033 (VPMOVSXBWrm addr:$src)>;
6035 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6036 (VPMOVSXWDrm addr:$src)>;
6037 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6038 (VPMOVSXWDrm addr:$src)>;
6039 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6040 (VPMOVSXWDrm addr:$src)>;
6042 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6043 (VPMOVSXDQrm addr:$src)>;
6044 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6045 (VPMOVSXDQrm addr:$src)>;
6046 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6047 (VPMOVSXDQrm addr:$src)>;
6049 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6050 (VPMOVZXBWrm addr:$src)>;
6051 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6052 (VPMOVZXBWrm addr:$src)>;
6053 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6054 (VPMOVZXBWrm addr:$src)>;
6056 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6057 (VPMOVZXWDrm addr:$src)>;
6058 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6059 (VPMOVZXWDrm addr:$src)>;
6060 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6061 (VPMOVZXWDrm addr:$src)>;
6063 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6064 (VPMOVZXDQrm addr:$src)>;
6065 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6066 (VPMOVZXDQrm addr:$src)>;
6067 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6068 (VPMOVZXDQrm addr:$src)>;
6071 let Predicates = [UseSSE41] in {
6072 // Common patterns involving scalar load.
6073 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
6074 (PMOVSXBWrm addr:$src)>;
6075 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
6076 (PMOVSXBWrm addr:$src)>;
6077 def : Pat<(int_x86_sse41_pmovsxbw (bc_v16i8 (loadv2i64 addr:$src))),
6078 (PMOVSXBWrm addr:$src)>;
6080 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
6081 (PMOVSXWDrm addr:$src)>;
6082 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
6083 (PMOVSXWDrm addr:$src)>;
6084 def : Pat<(int_x86_sse41_pmovsxwd (bc_v8i16 (loadv2i64 addr:$src))),
6085 (PMOVSXWDrm addr:$src)>;
6087 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
6088 (PMOVSXDQrm addr:$src)>;
6089 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
6090 (PMOVSXDQrm addr:$src)>;
6091 def : Pat<(int_x86_sse41_pmovsxdq (bc_v4i32 (loadv2i64 addr:$src))),
6092 (PMOVSXDQrm addr:$src)>;
6094 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
6095 (PMOVZXBWrm addr:$src)>;
6096 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
6097 (PMOVZXBWrm addr:$src)>;
6098 def : Pat<(int_x86_sse41_pmovzxbw (bc_v16i8 (loadv2i64 addr:$src))),
6099 (PMOVZXBWrm addr:$src)>;
6101 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
6102 (PMOVZXWDrm addr:$src)>;
6103 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
6104 (PMOVZXWDrm addr:$src)>;
6105 def : Pat<(int_x86_sse41_pmovzxwd (bc_v8i16 (loadv2i64 addr:$src))),
6106 (PMOVZXWDrm addr:$src)>;
6108 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
6109 (PMOVZXDQrm addr:$src)>;
6110 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
6111 (PMOVZXDQrm addr:$src)>;
6112 def : Pat<(int_x86_sse41_pmovzxdq (bc_v4i32 (loadv2i64 addr:$src))),
6113 (PMOVZXDQrm addr:$src)>;
6116 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6117 OpndItins itins = DEFAULT_ITINS> {
6118 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6119 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6120 [(set VR128:$dst, (IntId VR128:$src))], itins.rr>,
6121 Sched<[itins.Sched]>;
6123 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
6124 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6126 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))],
6127 itins.rm>, Sched<[itins.Sched.Folded]>;
6130 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
6131 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6132 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6133 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6134 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6136 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
6137 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6139 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
6140 Sched<[Sched.Folded]>;
6143 let Predicates = [HasAVX] in {
6144 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd,
6145 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6146 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq,
6147 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6148 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd,
6149 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6150 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq,
6151 DEFAULT_ITINS_SHUFFLESCHED>, VEX;
6154 let Predicates = [HasAVX2] in {
6155 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
6156 int_x86_avx2_pmovsxbd, WriteShuffle>,
6158 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
6159 int_x86_avx2_pmovsxwq, WriteShuffle>,
6161 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
6162 int_x86_avx2_pmovzxbd, WriteShuffle>,
6164 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
6165 int_x86_avx2_pmovzxwq, WriteShuffle>,
6169 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd,
6170 SSE_INTALU_ITINS_SHUFF_P>;
6171 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq,
6172 SSE_INTALU_ITINS_SHUFF_P>;
6173 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd,
6174 SSE_INTALU_ITINS_SHUFF_P>;
6175 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq,
6176 SSE_INTALU_ITINS_SHUFF_P>;
6178 let Predicates = [HasAVX] in {
6179 // Common patterns involving scalar load
6180 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6181 (VPMOVSXBDrm addr:$src)>;
6182 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6183 (VPMOVSXWQrm addr:$src)>;
6185 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6186 (VPMOVZXBDrm addr:$src)>;
6187 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6188 (VPMOVZXWQrm addr:$src)>;
6191 let Predicates = [UseSSE41] in {
6192 // Common patterns involving scalar load
6193 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
6194 (PMOVSXBDrm addr:$src)>;
6195 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
6196 (PMOVSXWQrm addr:$src)>;
6198 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
6199 (PMOVZXBDrm addr:$src)>;
6200 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
6201 (PMOVZXWQrm addr:$src)>;
6204 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId,
6205 X86FoldableSchedWrite Sched> {
6206 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6207 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6208 [(set VR128:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6210 // Expecting a i16 load any extended to i32 value.
6211 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
6212 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6213 [(set VR128:$dst, (IntId (bitconvert
6214 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
6215 Sched<[Sched.Folded]>;
6218 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
6219 Intrinsic IntId, X86FoldableSchedWrite Sched> {
6220 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6221 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6222 [(set VR256:$dst, (IntId VR128:$src))]>, Sched<[Sched]>;
6224 // Expecting a i16 load any extended to i32 value.
6225 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
6226 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6227 [(set VR256:$dst, (IntId (bitconvert
6228 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
6229 Sched<[Sched.Folded]>;
6232 let Predicates = [HasAVX] in {
6233 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq,
6235 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq,
6238 let Predicates = [HasAVX2] in {
6239 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq", int_x86_avx2_pmovsxbq,
6240 WriteShuffle>, VEX, VEX_L;
6241 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq", int_x86_avx2_pmovzxbq,
6242 WriteShuffle>, VEX, VEX_L;
6244 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq,
6246 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq,
6249 let Predicates = [HasAVX2] in {
6250 def : Pat<(v16i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWYrr VR128:$src)>;
6251 def : Pat<(v8i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDYrr VR128:$src)>;
6252 def : Pat<(v4i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQYrr VR128:$src)>;
6254 def : Pat<(v8i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
6255 def : Pat<(v4i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQYrr VR128:$src)>;
6257 def : Pat<(v4i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
6259 def : Pat<(v16i16 (X86vsext (v32i8 VR256:$src))),
6260 (VPMOVSXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6261 def : Pat<(v8i32 (X86vsext (v32i8 VR256:$src))),
6262 (VPMOVSXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6263 def : Pat<(v4i64 (X86vsext (v32i8 VR256:$src))),
6264 (VPMOVSXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6266 def : Pat<(v8i32 (X86vsext (v16i16 VR256:$src))),
6267 (VPMOVSXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6268 def : Pat<(v4i64 (X86vsext (v16i16 VR256:$src))),
6269 (VPMOVSXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6271 def : Pat<(v4i64 (X86vsext (v8i32 VR256:$src))),
6272 (VPMOVSXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6274 def : Pat<(v8i32 (X86vsext (v8i16 (bitconvert (v2i64 (load addr:$src)))))),
6275 (VPMOVSXWDYrm addr:$src)>;
6276 def : Pat<(v4i64 (X86vsext (v4i32 (bitconvert (v2i64 (load addr:$src)))))),
6277 (VPMOVSXDQYrm addr:$src)>;
6279 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2i64
6280 (scalar_to_vector (loadi64 addr:$src))))))),
6281 (VPMOVSXBDYrm addr:$src)>;
6282 def : Pat<(v8i32 (X86vsext (v16i8 (bitconvert (v2f64
6283 (scalar_to_vector (loadf64 addr:$src))))))),
6284 (VPMOVSXBDYrm addr:$src)>;
6286 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2i64
6287 (scalar_to_vector (loadi64 addr:$src))))))),
6288 (VPMOVSXWQYrm addr:$src)>;
6289 def : Pat<(v4i64 (X86vsext (v8i16 (bitconvert (v2f64
6290 (scalar_to_vector (loadf64 addr:$src))))))),
6291 (VPMOVSXWQYrm addr:$src)>;
6293 def : Pat<(v4i64 (X86vsext (v16i8 (bitconvert (v4i32
6294 (scalar_to_vector (loadi32 addr:$src))))))),
6295 (VPMOVSXBQYrm addr:$src)>;
6298 let Predicates = [HasAVX] in {
6299 // Common patterns involving scalar load
6300 def : Pat<(int_x86_sse41_pmovsxbq
6301 (bitconvert (v4i32 (X86vzmovl
6302 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6303 (VPMOVSXBQrm addr:$src)>;
6305 def : Pat<(int_x86_sse41_pmovzxbq
6306 (bitconvert (v4i32 (X86vzmovl
6307 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6308 (VPMOVZXBQrm addr:$src)>;
6311 let Predicates = [UseSSE41] in {
6312 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (PMOVSXBWrr VR128:$src)>;
6313 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (PMOVSXBDrr VR128:$src)>;
6314 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (PMOVSXBQrr VR128:$src)>;
6316 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
6317 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (PMOVSXWQrr VR128:$src)>;
6319 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
6321 // Common patterns involving scalar load
6322 def : Pat<(int_x86_sse41_pmovsxbq
6323 (bitconvert (v4i32 (X86vzmovl
6324 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6325 (PMOVSXBQrm addr:$src)>;
6327 def : Pat<(int_x86_sse41_pmovzxbq
6328 (bitconvert (v4i32 (X86vzmovl
6329 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6330 (PMOVZXBQrm addr:$src)>;
6332 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6333 (scalar_to_vector (loadi64 addr:$src))))))),
6334 (PMOVSXWDrm addr:$src)>;
6335 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6336 (scalar_to_vector (loadf64 addr:$src))))))),
6337 (PMOVSXWDrm addr:$src)>;
6338 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6339 (scalar_to_vector (loadi32 addr:$src))))))),
6340 (PMOVSXBDrm addr:$src)>;
6341 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6342 (scalar_to_vector (loadi32 addr:$src))))))),
6343 (PMOVSXWQrm addr:$src)>;
6344 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6345 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6346 (PMOVSXBQrm addr:$src)>;
6347 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6348 (scalar_to_vector (loadi64 addr:$src))))))),
6349 (PMOVSXDQrm addr:$src)>;
6350 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6351 (scalar_to_vector (loadf64 addr:$src))))))),
6352 (PMOVSXDQrm addr:$src)>;
6353 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6354 (scalar_to_vector (loadi64 addr:$src))))))),
6355 (PMOVSXBWrm addr:$src)>;
6356 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6357 (scalar_to_vector (loadf64 addr:$src))))))),
6358 (PMOVSXBWrm addr:$src)>;
6361 let Predicates = [HasAVX2] in {
6362 def : Pat<(v16i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWYrr VR128:$src)>;
6363 def : Pat<(v8i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDYrr VR128:$src)>;
6364 def : Pat<(v4i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQYrr VR128:$src)>;
6366 def : Pat<(v8i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDYrr VR128:$src)>;
6367 def : Pat<(v4i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQYrr VR128:$src)>;
6369 def : Pat<(v4i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQYrr VR128:$src)>;
6371 def : Pat<(v16i16 (X86vzext (v32i8 VR256:$src))),
6372 (VPMOVZXBWYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6373 def : Pat<(v8i32 (X86vzext (v32i8 VR256:$src))),
6374 (VPMOVZXBDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6375 def : Pat<(v4i64 (X86vzext (v32i8 VR256:$src))),
6376 (VPMOVZXBQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6378 def : Pat<(v8i32 (X86vzext (v16i16 VR256:$src))),
6379 (VPMOVZXWDYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6380 def : Pat<(v4i64 (X86vzext (v16i16 VR256:$src))),
6381 (VPMOVZXWQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6383 def : Pat<(v4i64 (X86vzext (v8i32 VR256:$src))),
6384 (VPMOVZXDQYrr (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
6387 let Predicates = [HasAVX] in {
6388 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBWrr VR128:$src)>;
6389 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBDrr VR128:$src)>;
6390 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (VPMOVZXBQrr VR128:$src)>;
6392 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWDrr VR128:$src)>;
6393 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (VPMOVZXWQrr VR128:$src)>;
6395 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (VPMOVZXDQrr VR128:$src)>;
6397 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6398 (VPMOVZXBWrm addr:$src)>;
6399 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6400 (VPMOVZXBWrm addr:$src)>;
6401 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6402 (VPMOVZXBDrm addr:$src)>;
6403 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6404 (VPMOVZXBQrm addr:$src)>;
6406 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6407 (VPMOVZXWDrm addr:$src)>;
6408 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6409 (VPMOVZXWDrm addr:$src)>;
6410 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6411 (VPMOVZXWQrm addr:$src)>;
6413 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6414 (VPMOVZXDQrm addr:$src)>;
6415 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6416 (VPMOVZXDQrm addr:$src)>;
6417 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6418 (VPMOVZXDQrm addr:$src)>;
6420 def : Pat<(v8i16 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBWrr VR128:$src)>;
6421 def : Pat<(v4i32 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBDrr VR128:$src)>;
6422 def : Pat<(v2i64 (X86vsext (v16i8 VR128:$src))), (VPMOVSXBQrr VR128:$src)>;
6424 def : Pat<(v4i32 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
6425 def : Pat<(v2i64 (X86vsext (v8i16 VR128:$src))), (VPMOVSXWQrr VR128:$src)>;
6427 def : Pat<(v2i64 (X86vsext (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
6429 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2i64
6430 (scalar_to_vector (loadi64 addr:$src))))))),
6431 (VPMOVSXWDrm addr:$src)>;
6432 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2i64
6433 (scalar_to_vector (loadi64 addr:$src))))))),
6434 (VPMOVSXDQrm addr:$src)>;
6435 def : Pat<(v4i32 (X86vsext (v8i16 (bitconvert (v2f64
6436 (scalar_to_vector (loadf64 addr:$src))))))),
6437 (VPMOVSXWDrm addr:$src)>;
6438 def : Pat<(v2i64 (X86vsext (v4i32 (bitconvert (v2f64
6439 (scalar_to_vector (loadf64 addr:$src))))))),
6440 (VPMOVSXDQrm addr:$src)>;
6441 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2i64
6442 (scalar_to_vector (loadi64 addr:$src))))))),
6443 (VPMOVSXBWrm addr:$src)>;
6444 def : Pat<(v8i16 (X86vsext (v16i8 (bitconvert (v2f64
6445 (scalar_to_vector (loadf64 addr:$src))))))),
6446 (VPMOVSXBWrm addr:$src)>;
6448 def : Pat<(v4i32 (X86vsext (v16i8 (bitconvert (v4i32
6449 (scalar_to_vector (loadi32 addr:$src))))))),
6450 (VPMOVSXBDrm addr:$src)>;
6451 def : Pat<(v2i64 (X86vsext (v8i16 (bitconvert (v4i32
6452 (scalar_to_vector (loadi32 addr:$src))))))),
6453 (VPMOVSXWQrm addr:$src)>;
6454 def : Pat<(v2i64 (X86vsext (v16i8 (bitconvert (v4i32
6455 (scalar_to_vector (extloadi32i16 addr:$src))))))),
6456 (VPMOVSXBQrm addr:$src)>;
6459 let Predicates = [UseSSE41] in {
6460 def : Pat<(v8i16 (X86vzext (v16i8 VR128:$src))), (PMOVZXBWrr VR128:$src)>;
6461 def : Pat<(v4i32 (X86vzext (v16i8 VR128:$src))), (PMOVZXBDrr VR128:$src)>;
6462 def : Pat<(v2i64 (X86vzext (v16i8 VR128:$src))), (PMOVZXBQrr VR128:$src)>;
6464 def : Pat<(v4i32 (X86vzext (v8i16 VR128:$src))), (PMOVZXWDrr VR128:$src)>;
6465 def : Pat<(v2i64 (X86vzext (v8i16 VR128:$src))), (PMOVZXWQrr VR128:$src)>;
6467 def : Pat<(v2i64 (X86vzext (v4i32 VR128:$src))), (PMOVZXDQrr VR128:$src)>;
6469 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6470 (PMOVZXBWrm addr:$src)>;
6471 def : Pat<(v8i16 (X86vzext (v16i8 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6472 (PMOVZXBWrm addr:$src)>;
6473 def : Pat<(v4i32 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6474 (PMOVZXBDrm addr:$src)>;
6475 def : Pat<(v2i64 (X86vzext (v16i8 (bitconvert (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))),
6476 (PMOVZXBQrm addr:$src)>;
6478 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6479 (PMOVZXWDrm addr:$src)>;
6480 def : Pat<(v4i32 (X86vzext (v8i16 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6481 (PMOVZXWDrm addr:$src)>;
6482 def : Pat<(v2i64 (X86vzext (v8i16 (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
6483 (PMOVZXWQrm addr:$src)>;
6485 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))),
6486 (PMOVZXDQrm addr:$src)>;
6487 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2f64 (scalar_to_vector (loadf64 addr:$src))))))),
6488 (PMOVZXDQrm addr:$src)>;
6489 def : Pat<(v2i64 (X86vzext (v4i32 (bitconvert (v2i64 (X86vzload addr:$src)))))),
6490 (PMOVZXDQrm addr:$src)>;
6493 //===----------------------------------------------------------------------===//
6494 // SSE4.1 - Extract Instructions
6495 //===----------------------------------------------------------------------===//
6497 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6498 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6499 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6500 (ins VR128:$src1, i32i8imm:$src2),
6501 !strconcat(OpcodeStr,
6502 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6503 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6505 Sched<[WriteShuffle]>;
6506 let neverHasSideEffects = 1, mayStore = 1,
6507 SchedRW = [WriteShuffleLd, WriteRMW] in
6508 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6509 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
6510 !strconcat(OpcodeStr,
6511 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6512 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6513 imm:$src2)))), addr:$dst)]>;
6516 let Predicates = [HasAVX] in
6517 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6519 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6522 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6523 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6524 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6525 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6526 (ins VR128:$src1, i32i8imm:$src2),
6527 !strconcat(OpcodeStr,
6528 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6529 []>, Sched<[WriteShuffle]>;
6531 let neverHasSideEffects = 1, mayStore = 1,
6532 SchedRW = [WriteShuffleLd, WriteRMW] in
6533 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6534 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
6535 !strconcat(OpcodeStr,
6536 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6537 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6538 imm:$src2)))), addr:$dst)]>;
6541 let Predicates = [HasAVX] in
6542 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6544 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6547 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6548 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6549 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6550 (ins VR128:$src1, i32i8imm:$src2),
6551 !strconcat(OpcodeStr,
6552 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6554 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6555 Sched<[WriteShuffle]>;
6556 let SchedRW = [WriteShuffleLd, WriteRMW] in
6557 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6558 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
6559 !strconcat(OpcodeStr,
6560 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6561 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6565 let Predicates = [HasAVX] in
6566 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6568 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6570 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6571 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6572 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6573 (ins VR128:$src1, i32i8imm:$src2),
6574 !strconcat(OpcodeStr,
6575 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6577 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6578 Sched<[WriteShuffle]>, REX_W;
6579 let SchedRW = [WriteShuffleLd, WriteRMW] in
6580 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6581 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
6582 !strconcat(OpcodeStr,
6583 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6584 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6585 addr:$dst)]>, REX_W;
6588 let Predicates = [HasAVX] in
6589 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6591 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6593 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6595 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6596 OpndItins itins = DEFAULT_ITINS> {
6597 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6598 (ins VR128:$src1, i32i8imm:$src2),
6599 !strconcat(OpcodeStr,
6600 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6601 [(set GR32orGR64:$dst,
6602 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6603 itins.rr>, Sched<[WriteFBlend]>;
6604 let SchedRW = [WriteFBlendLd, WriteRMW] in
6605 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6606 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6607 !strconcat(OpcodeStr,
6608 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6609 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6610 addr:$dst)], itins.rm>;
6613 let ExeDomain = SSEPackedSingle in {
6614 let Predicates = [UseAVX] in
6615 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6616 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6619 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6620 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6623 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6625 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6628 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6629 Requires<[UseSSE41]>;
6631 //===----------------------------------------------------------------------===//
6632 // SSE4.1 - Insert Instructions
6633 //===----------------------------------------------------------------------===//
6635 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6636 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6637 (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),
6639 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6641 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6643 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6644 Sched<[WriteShuffle]>;
6645 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6646 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6648 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6650 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6652 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6653 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6656 let Predicates = [HasAVX] in
6657 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6658 let Constraints = "$src1 = $dst" in
6659 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6661 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6662 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6663 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6665 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6667 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6669 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6670 Sched<[WriteShuffle]>;
6671 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6672 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6674 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6676 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6678 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6679 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6682 let Predicates = [HasAVX] in
6683 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6684 let Constraints = "$src1 = $dst" in
6685 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6687 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6688 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6689 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6691 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6693 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6695 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6696 Sched<[WriteShuffle]>;
6697 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6698 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6700 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6702 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6704 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6705 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6708 let Predicates = [HasAVX] in
6709 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6710 let Constraints = "$src1 = $dst" in
6711 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6713 // insertps has a few different modes, there's the first two here below which
6714 // are optimized inserts that won't zero arbitrary elements in the destination
6715 // vector. The next one matches the intrinsic and could zero arbitrary elements
6716 // in the target vector.
6717 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6718 OpndItins itins = DEFAULT_ITINS> {
6719 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6720 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6722 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6724 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6726 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6727 Sched<[WriteFShuffle]>;
6728 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6729 (ins VR128:$src1, f32mem:$src2, i8imm:$src3),
6731 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6733 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6735 (X86insertps VR128:$src1,
6736 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6737 imm:$src3))], itins.rm>,
6738 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6741 let ExeDomain = SSEPackedSingle in {
6742 let Predicates = [UseAVX] in
6743 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6744 let Constraints = "$src1 = $dst" in
6745 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6748 let Predicates = [UseSSE41] in {
6749 // If we're inserting an element from a load or a null pshuf of a load,
6750 // fold the load into the insertps instruction.
6751 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6752 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6754 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6755 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6756 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6757 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6760 let Predicates = [UseAVX] in {
6761 // If we're inserting an element from a vbroadcast of a load, fold the
6762 // load into the X86insertps instruction.
6763 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6764 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6765 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6766 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6767 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6768 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6771 //===----------------------------------------------------------------------===//
6772 // SSE4.1 - Round Instructions
6773 //===----------------------------------------------------------------------===//
6775 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6776 X86MemOperand x86memop, RegisterClass RC,
6777 PatFrag mem_frag32, PatFrag mem_frag64,
6778 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6779 let ExeDomain = SSEPackedSingle in {
6780 // Intrinsic operation, reg.
6781 // Vector intrinsic operation, reg
6782 def PSr : SS4AIi8<opcps, MRMSrcReg,
6783 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6784 !strconcat(OpcodeStr,
6785 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6786 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6787 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6789 // Vector intrinsic operation, mem
6790 def PSm : SS4AIi8<opcps, MRMSrcMem,
6791 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6792 !strconcat(OpcodeStr,
6793 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6795 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6796 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6797 } // ExeDomain = SSEPackedSingle
6799 let ExeDomain = SSEPackedDouble in {
6800 // Vector intrinsic operation, reg
6801 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6802 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6803 !strconcat(OpcodeStr,
6804 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6805 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6806 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6808 // Vector intrinsic operation, mem
6809 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6810 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6811 !strconcat(OpcodeStr,
6812 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6814 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6815 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6816 } // ExeDomain = SSEPackedDouble
6819 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6822 Intrinsic F64Int, bit Is2Addr = 1> {
6823 let ExeDomain = GenericDomain in {
6825 let hasSideEffects = 0 in
6826 def SSr : SS4AIi8<opcss, MRMSrcReg,
6827 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6829 !strconcat(OpcodeStr,
6830 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6831 !strconcat(OpcodeStr,
6832 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6833 []>, Sched<[WriteFAdd]>;
6835 // Intrinsic operation, reg.
6836 let isCodeGenOnly = 1 in
6837 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6838 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6840 !strconcat(OpcodeStr,
6841 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6842 !strconcat(OpcodeStr,
6843 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6844 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6847 // Intrinsic operation, mem.
6848 def SSm : SS4AIi8<opcss, MRMSrcMem,
6849 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6851 !strconcat(OpcodeStr,
6852 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6853 !strconcat(OpcodeStr,
6854 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6856 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6857 Sched<[WriteFAddLd, ReadAfterLd]>;
6860 let hasSideEffects = 0 in
6861 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6862 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6864 !strconcat(OpcodeStr,
6865 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6866 !strconcat(OpcodeStr,
6867 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6868 []>, Sched<[WriteFAdd]>;
6870 // Intrinsic operation, reg.
6871 let isCodeGenOnly = 1 in
6872 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6873 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6875 !strconcat(OpcodeStr,
6876 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6877 !strconcat(OpcodeStr,
6878 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6879 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6882 // Intrinsic operation, mem.
6883 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6884 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6886 !strconcat(OpcodeStr,
6887 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6888 !strconcat(OpcodeStr,
6889 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6891 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6892 Sched<[WriteFAddLd, ReadAfterLd]>;
6893 } // ExeDomain = GenericDomain
6896 // FP round - roundss, roundps, roundsd, roundpd
6897 let Predicates = [HasAVX] in {
6899 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6900 loadv4f32, loadv2f64,
6901 int_x86_sse41_round_ps,
6902 int_x86_sse41_round_pd>, VEX;
6903 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6904 loadv8f32, loadv4f64,
6905 int_x86_avx_round_ps_256,
6906 int_x86_avx_round_pd_256>, VEX, VEX_L;
6907 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6908 int_x86_sse41_round_ss,
6909 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6911 def : Pat<(ffloor FR32:$src),
6912 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6913 def : Pat<(f64 (ffloor FR64:$src)),
6914 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6915 def : Pat<(f32 (fnearbyint FR32:$src)),
6916 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6917 def : Pat<(f64 (fnearbyint FR64:$src)),
6918 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6919 def : Pat<(f32 (fceil FR32:$src)),
6920 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6921 def : Pat<(f64 (fceil FR64:$src)),
6922 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6923 def : Pat<(f32 (frint FR32:$src)),
6924 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6925 def : Pat<(f64 (frint FR64:$src)),
6926 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6927 def : Pat<(f32 (ftrunc FR32:$src)),
6928 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6929 def : Pat<(f64 (ftrunc FR64:$src)),
6930 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6932 def : Pat<(v4f32 (ffloor VR128:$src)),
6933 (VROUNDPSr VR128:$src, (i32 0x1))>;
6934 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6935 (VROUNDPSr VR128:$src, (i32 0xC))>;
6936 def : Pat<(v4f32 (fceil VR128:$src)),
6937 (VROUNDPSr VR128:$src, (i32 0x2))>;
6938 def : Pat<(v4f32 (frint VR128:$src)),
6939 (VROUNDPSr VR128:$src, (i32 0x4))>;
6940 def : Pat<(v4f32 (ftrunc VR128:$src)),
6941 (VROUNDPSr VR128:$src, (i32 0x3))>;
6943 def : Pat<(v2f64 (ffloor VR128:$src)),
6944 (VROUNDPDr VR128:$src, (i32 0x1))>;
6945 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6946 (VROUNDPDr VR128:$src, (i32 0xC))>;
6947 def : Pat<(v2f64 (fceil VR128:$src)),
6948 (VROUNDPDr VR128:$src, (i32 0x2))>;
6949 def : Pat<(v2f64 (frint VR128:$src)),
6950 (VROUNDPDr VR128:$src, (i32 0x4))>;
6951 def : Pat<(v2f64 (ftrunc VR128:$src)),
6952 (VROUNDPDr VR128:$src, (i32 0x3))>;
6954 def : Pat<(v8f32 (ffloor VR256:$src)),
6955 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6956 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6957 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6958 def : Pat<(v8f32 (fceil VR256:$src)),
6959 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6960 def : Pat<(v8f32 (frint VR256:$src)),
6961 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6962 def : Pat<(v8f32 (ftrunc VR256:$src)),
6963 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6965 def : Pat<(v4f64 (ffloor VR256:$src)),
6966 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6967 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6968 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6969 def : Pat<(v4f64 (fceil VR256:$src)),
6970 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6971 def : Pat<(v4f64 (frint VR256:$src)),
6972 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6973 def : Pat<(v4f64 (ftrunc VR256:$src)),
6974 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6977 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6978 memopv4f32, memopv2f64,
6979 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6980 let Constraints = "$src1 = $dst" in
6981 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6982 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6984 let Predicates = [UseSSE41] in {
6985 def : Pat<(ffloor FR32:$src),
6986 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6987 def : Pat<(f64 (ffloor FR64:$src)),
6988 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6989 def : Pat<(f32 (fnearbyint FR32:$src)),
6990 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6991 def : Pat<(f64 (fnearbyint FR64:$src)),
6992 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6993 def : Pat<(f32 (fceil FR32:$src)),
6994 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6995 def : Pat<(f64 (fceil FR64:$src)),
6996 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6997 def : Pat<(f32 (frint FR32:$src)),
6998 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6999 def : Pat<(f64 (frint FR64:$src)),
7000 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
7001 def : Pat<(f32 (ftrunc FR32:$src)),
7002 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
7003 def : Pat<(f64 (ftrunc FR64:$src)),
7004 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
7006 def : Pat<(v4f32 (ffloor VR128:$src)),
7007 (ROUNDPSr VR128:$src, (i32 0x1))>;
7008 def : Pat<(v4f32 (fnearbyint VR128:$src)),
7009 (ROUNDPSr VR128:$src, (i32 0xC))>;
7010 def : Pat<(v4f32 (fceil VR128:$src)),
7011 (ROUNDPSr VR128:$src, (i32 0x2))>;
7012 def : Pat<(v4f32 (frint VR128:$src)),
7013 (ROUNDPSr VR128:$src, (i32 0x4))>;
7014 def : Pat<(v4f32 (ftrunc VR128:$src)),
7015 (ROUNDPSr VR128:$src, (i32 0x3))>;
7017 def : Pat<(v2f64 (ffloor VR128:$src)),
7018 (ROUNDPDr VR128:$src, (i32 0x1))>;
7019 def : Pat<(v2f64 (fnearbyint VR128:$src)),
7020 (ROUNDPDr VR128:$src, (i32 0xC))>;
7021 def : Pat<(v2f64 (fceil VR128:$src)),
7022 (ROUNDPDr VR128:$src, (i32 0x2))>;
7023 def : Pat<(v2f64 (frint VR128:$src)),
7024 (ROUNDPDr VR128:$src, (i32 0x4))>;
7025 def : Pat<(v2f64 (ftrunc VR128:$src)),
7026 (ROUNDPDr VR128:$src, (i32 0x3))>;
7029 //===----------------------------------------------------------------------===//
7030 // SSE4.1 - Packed Bit Test
7031 //===----------------------------------------------------------------------===//
7033 // ptest instruction we'll lower to this in X86ISelLowering primarily from
7034 // the intel intrinsic that corresponds to this.
7035 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7036 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7037 "vptest\t{$src2, $src1|$src1, $src2}",
7038 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7039 Sched<[WriteVecLogic]>, VEX;
7040 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7041 "vptest\t{$src2, $src1|$src1, $src2}",
7042 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
7043 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7045 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
7046 "vptest\t{$src2, $src1|$src1, $src2}",
7047 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
7048 Sched<[WriteVecLogic]>, VEX, VEX_L;
7049 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
7050 "vptest\t{$src2, $src1|$src1, $src2}",
7051 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
7052 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
7055 let Defs = [EFLAGS] in {
7056 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
7057 "ptest\t{$src2, $src1|$src1, $src2}",
7058 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
7059 Sched<[WriteVecLogic]>;
7060 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
7061 "ptest\t{$src2, $src1|$src1, $src2}",
7062 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
7063 Sched<[WriteVecLogicLd, ReadAfterLd]>;
7066 // The bit test instructions below are AVX only
7067 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
7068 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
7069 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
7070 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7071 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
7072 Sched<[WriteVecLogic]>, VEX;
7073 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
7074 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
7075 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
7076 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
7079 let Defs = [EFLAGS], Predicates = [HasAVX] in {
7080 let ExeDomain = SSEPackedSingle in {
7081 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
7082 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
7085 let ExeDomain = SSEPackedDouble in {
7086 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
7087 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
7092 //===----------------------------------------------------------------------===//
7093 // SSE4.1 - Misc Instructions
7094 //===----------------------------------------------------------------------===//
7096 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
7097 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
7098 "popcnt{w}\t{$src, $dst|$dst, $src}",
7099 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
7100 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7102 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
7103 "popcnt{w}\t{$src, $dst|$dst, $src}",
7104 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
7105 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7106 Sched<[WriteFAddLd]>, OpSize16, XS;
7108 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
7109 "popcnt{l}\t{$src, $dst|$dst, $src}",
7110 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
7111 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
7114 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
7115 "popcnt{l}\t{$src, $dst|$dst, $src}",
7116 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
7117 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7118 Sched<[WriteFAddLd]>, OpSize32, XS;
7120 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
7121 "popcnt{q}\t{$src, $dst|$dst, $src}",
7122 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
7123 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
7124 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
7125 "popcnt{q}\t{$src, $dst|$dst, $src}",
7126 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
7127 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
7128 Sched<[WriteFAddLd]>, XS;
7133 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
7134 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
7136 X86FoldableSchedWrite Sched> {
7137 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7139 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7140 [(set VR128:$dst, (IntId128 VR128:$src))]>,
7142 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7144 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7146 (IntId128 (bitconvert (memopv2i64 addr:$src))))]>,
7147 Sched<[Sched.Folded]>;
7150 // PHMIN has the same profile as PSAD, thus we use the same scheduling
7151 // model, although the naming is misleading.
7152 let Predicates = [HasAVX] in
7153 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
7154 int_x86_sse41_phminposuw,
7156 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
7157 int_x86_sse41_phminposuw,
7160 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
7161 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
7162 Intrinsic IntId128, bit Is2Addr = 1,
7163 OpndItins itins = DEFAULT_ITINS> {
7164 let isCommutable = 1 in
7165 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7166 (ins VR128:$src1, VR128:$src2),
7168 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7169 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7170 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))],
7171 itins.rr>, Sched<[itins.Sched]>;
7172 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7173 (ins VR128:$src1, i128mem:$src2),
7175 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7176 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7178 (IntId128 VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))],
7179 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7182 /// SS41I_binop_rm_int_y - Simple SSE 4.1 binary operator
7183 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
7185 X86FoldableSchedWrite Sched> {
7186 let isCommutable = 1 in
7187 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
7188 (ins VR256:$src1, VR256:$src2),
7189 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7190 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
7192 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
7193 (ins VR256:$src1, i256mem:$src2),
7194 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7196 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
7197 Sched<[Sched.Folded, ReadAfterLd]>;
7201 /// SS48I_binop_rm - Simple SSE41 binary operator.
7202 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7203 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7204 X86MemOperand x86memop, bit Is2Addr = 1,
7205 OpndItins itins = SSE_INTALU_ITINS_P> {
7206 let isCommutable = 1 in
7207 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7208 (ins RC:$src1, RC:$src2),
7210 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7211 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7212 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
7213 Sched<[itins.Sched]>;
7214 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7215 (ins RC:$src1, x86memop:$src2),
7217 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7218 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7220 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
7221 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7224 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
7226 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
7227 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
7228 PatFrag memop_frag, X86MemOperand x86memop,
7230 bit IsCommutable = 0, bit Is2Addr = 1> {
7231 let isCommutable = IsCommutable in
7232 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
7233 (ins RC:$src1, RC:$src2),
7235 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7236 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7237 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
7238 Sched<[itins.Sched]>;
7239 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
7240 (ins RC:$src1, x86memop:$src2),
7242 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7243 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7244 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
7245 (bitconvert (memop_frag addr:$src2)))))]>,
7246 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7249 let Predicates = [HasAVX] in {
7250 let isCommutable = 0 in
7251 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
7252 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7254 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
7255 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7257 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
7258 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7260 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
7261 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7263 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
7264 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7266 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
7267 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7269 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
7270 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7272 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
7273 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7275 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
7276 VR128, loadv2i64, i128mem,
7277 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
7280 let Predicates = [HasAVX2] in {
7281 let isCommutable = 0 in
7282 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
7283 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7285 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
7286 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7288 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
7289 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7291 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
7292 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7294 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
7295 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7297 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
7298 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7300 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
7301 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7303 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
7304 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7306 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
7307 VR256, loadv4i64, i256mem,
7308 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
7311 let Constraints = "$src1 = $dst" in {
7312 let isCommutable = 0 in
7313 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
7314 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7315 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
7316 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7317 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
7318 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7319 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
7320 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7321 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
7322 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7323 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
7324 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7325 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
7326 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7327 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
7328 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
7329 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
7330 VR128, memopv2i64, i128mem,
7331 SSE_INTMUL_ITINS_P, 1>;
7334 let Predicates = [HasAVX] in {
7335 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
7336 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
7338 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
7339 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
7342 let Predicates = [HasAVX2] in {
7343 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
7344 memopv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
7346 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
7347 memopv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
7351 let Constraints = "$src1 = $dst" in {
7352 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
7353 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
7354 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
7355 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
7358 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
7359 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
7360 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7361 X86MemOperand x86memop, bit Is2Addr = 1,
7362 OpndItins itins = DEFAULT_ITINS> {
7363 let isCommutable = 1 in
7364 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
7365 (ins RC:$src1, RC:$src2, i8imm:$src3),
7367 !strconcat(OpcodeStr,
7368 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7369 !strconcat(OpcodeStr,
7370 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7371 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
7372 Sched<[itins.Sched]>;
7373 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
7374 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
7376 !strconcat(OpcodeStr,
7377 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
7378 !strconcat(OpcodeStr,
7379 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
7382 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
7383 Sched<[itins.Sched.Folded, ReadAfterLd]>;
7386 let Predicates = [HasAVX] in {
7387 let isCommutable = 0 in {
7388 let ExeDomain = SSEPackedSingle in {
7389 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
7390 VR128, loadv4f32, f128mem, 0,
7391 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7392 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
7393 int_x86_avx_blend_ps_256, VR256, loadv8f32,
7394 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7397 let ExeDomain = SSEPackedDouble in {
7398 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
7399 VR128, loadv2f64, f128mem, 0,
7400 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7401 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
7402 int_x86_avx_blend_pd_256,VR256, loadv4f64,
7403 f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,
7406 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
7407 VR128, loadv2i64, i128mem, 0,
7408 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7409 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
7410 VR128, loadv2i64, i128mem, 0,
7411 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
7413 let ExeDomain = SSEPackedSingle in
7414 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7415 VR128, loadv4f32, f128mem, 0,
7416 SSE_DPPS_ITINS>, VEX_4V;
7417 let ExeDomain = SSEPackedDouble in
7418 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7419 VR128, loadv2f64, f128mem, 0,
7420 SSE_DPPS_ITINS>, VEX_4V;
7421 let ExeDomain = SSEPackedSingle in
7422 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7423 VR256, loadv8f32, i256mem, 0,
7424 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7427 let Predicates = [HasAVX2] in {
7428 let isCommutable = 0 in {
7429 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
7430 VR256, loadv4i64, i256mem, 0,
7431 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7432 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7433 VR256, loadv4i64, i256mem, 0,
7434 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7438 let Constraints = "$src1 = $dst" in {
7439 let isCommutable = 0 in {
7440 let ExeDomain = SSEPackedSingle in
7441 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
7442 VR128, memopv4f32, f128mem,
7443 1, SSE_INTALU_ITINS_FBLEND_P>;
7444 let ExeDomain = SSEPackedDouble in
7445 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
7446 VR128, memopv2f64, f128mem,
7447 1, SSE_INTALU_ITINS_FBLEND_P>;
7448 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
7449 VR128, memopv2i64, i128mem,
7450 1, SSE_INTALU_ITINS_BLEND_P>;
7451 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7452 VR128, memopv2i64, i128mem,
7453 1, SSE_MPSADBW_ITINS>;
7455 let ExeDomain = SSEPackedSingle in
7456 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7457 VR128, memopv4f32, f128mem, 1,
7459 let ExeDomain = SSEPackedDouble in
7460 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7461 VR128, memopv2f64, f128mem, 1,
7465 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7466 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7467 RegisterClass RC, X86MemOperand x86memop,
7468 PatFrag mem_frag, Intrinsic IntId,
7469 X86FoldableSchedWrite Sched> {
7470 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7471 (ins RC:$src1, RC:$src2, RC:$src3),
7472 !strconcat(OpcodeStr,
7473 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7474 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7475 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7478 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7479 (ins RC:$src1, x86memop:$src2, RC:$src3),
7480 !strconcat(OpcodeStr,
7481 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7483 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7485 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7486 Sched<[Sched.Folded, ReadAfterLd]>;
7489 let Predicates = [HasAVX] in {
7490 let ExeDomain = SSEPackedDouble in {
7491 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7492 loadv2f64, int_x86_sse41_blendvpd,
7494 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7495 loadv4f64, int_x86_avx_blendv_pd_256,
7496 WriteFVarBlend>, VEX_L;
7497 } // ExeDomain = SSEPackedDouble
7498 let ExeDomain = SSEPackedSingle in {
7499 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7500 loadv4f32, int_x86_sse41_blendvps,
7502 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7503 loadv8f32, int_x86_avx_blendv_ps_256,
7504 WriteFVarBlend>, VEX_L;
7505 } // ExeDomain = SSEPackedSingle
7506 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7507 loadv2i64, int_x86_sse41_pblendvb,
7511 let Predicates = [HasAVX2] in {
7512 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7513 loadv4i64, int_x86_avx2_pblendvb,
7514 WriteVarBlend>, VEX_L;
7517 let Predicates = [HasAVX] in {
7518 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7519 (v16i8 VR128:$src2))),
7520 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7521 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7522 (v4i32 VR128:$src2))),
7523 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7524 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7525 (v4f32 VR128:$src2))),
7526 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7527 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7528 (v2i64 VR128:$src2))),
7529 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7530 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7531 (v2f64 VR128:$src2))),
7532 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7533 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7534 (v8i32 VR256:$src2))),
7535 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7536 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7537 (v8f32 VR256:$src2))),
7538 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7539 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7540 (v4i64 VR256:$src2))),
7541 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7542 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7543 (v4f64 VR256:$src2))),
7544 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7546 def : Pat<(v8f32 (X86Blendi (v8f32 VR256:$src1), (v8f32 VR256:$src2),
7548 (VBLENDPSYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7549 def : Pat<(v4f64 (X86Blendi (v4f64 VR256:$src1), (v4f64 VR256:$src2),
7551 (VBLENDPDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7553 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7555 (VPBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7556 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7558 (VBLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7559 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7561 (VBLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7564 let Predicates = [HasAVX2] in {
7565 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7566 (v32i8 VR256:$src2))),
7567 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7568 def : Pat<(v16i16 (X86Blendi (v16i16 VR256:$src1), (v16i16 VR256:$src2),
7570 (VPBLENDWYrri VR256:$src1, VR256:$src2, imm:$mask)>;
7573 /// SS41I_ternary_int - SSE 4.1 ternary operator
7574 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7575 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7576 X86MemOperand x86memop, Intrinsic IntId,
7577 OpndItins itins = DEFAULT_ITINS> {
7578 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7579 (ins VR128:$src1, VR128:$src2),
7580 !strconcat(OpcodeStr,
7581 "\t{$src2, $dst|$dst, $src2}"),
7582 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7583 itins.rr>, Sched<[itins.Sched]>;
7585 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7586 (ins VR128:$src1, x86memop:$src2),
7587 !strconcat(OpcodeStr,
7588 "\t{$src2, $dst|$dst, $src2}"),
7591 (bitconvert (mem_frag addr:$src2)), XMM0))],
7592 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7596 let ExeDomain = SSEPackedDouble in
7597 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7598 int_x86_sse41_blendvpd,
7599 DEFAULT_ITINS_FBLENDSCHED>;
7600 let ExeDomain = SSEPackedSingle in
7601 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7602 int_x86_sse41_blendvps,
7603 DEFAULT_ITINS_FBLENDSCHED>;
7604 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7605 int_x86_sse41_pblendvb,
7606 DEFAULT_ITINS_VARBLENDSCHED>;
7608 // Aliases with the implicit xmm0 argument
7609 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7610 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7611 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7612 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7613 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7614 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7615 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7616 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7617 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7618 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7619 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7620 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7622 let Predicates = [UseSSE41] in {
7623 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7624 (v16i8 VR128:$src2))),
7625 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7626 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7627 (v4i32 VR128:$src2))),
7628 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7629 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7630 (v4f32 VR128:$src2))),
7631 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7632 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7633 (v2i64 VR128:$src2))),
7634 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7635 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7636 (v2f64 VR128:$src2))),
7637 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7639 def : Pat<(v8i16 (X86Blendi (v8i16 VR128:$src1), (v8i16 VR128:$src2),
7641 (PBLENDWrri VR128:$src1, VR128:$src2, imm:$mask)>;
7642 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$src1), (v4f32 VR128:$src2),
7644 (BLENDPSrri VR128:$src1, VR128:$src2, imm:$mask)>;
7645 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$src1), (v2f64 VR128:$src2),
7647 (BLENDPDrri VR128:$src1, VR128:$src2, imm:$mask)>;
7651 let SchedRW = [WriteLoad] in {
7652 let Predicates = [HasAVX] in
7653 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7654 "vmovntdqa\t{$src, $dst|$dst, $src}",
7655 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7657 let Predicates = [HasAVX2] in
7658 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7659 "vmovntdqa\t{$src, $dst|$dst, $src}",
7660 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7662 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7663 "movntdqa\t{$src, $dst|$dst, $src}",
7664 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7667 //===----------------------------------------------------------------------===//
7668 // SSE4.2 - Compare Instructions
7669 //===----------------------------------------------------------------------===//
7671 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7672 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7673 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7674 X86MemOperand x86memop, bit Is2Addr = 1> {
7675 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7676 (ins RC:$src1, RC:$src2),
7678 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7679 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7680 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7681 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7682 (ins RC:$src1, x86memop:$src2),
7684 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7685 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7687 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7690 let Predicates = [HasAVX] in
7691 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7692 loadv2i64, i128mem, 0>, VEX_4V;
7694 let Predicates = [HasAVX2] in
7695 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7696 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7698 let Constraints = "$src1 = $dst" in
7699 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7700 memopv2i64, i128mem>;
7702 //===----------------------------------------------------------------------===//
7703 // SSE4.2 - String/text Processing Instructions
7704 //===----------------------------------------------------------------------===//
7706 // Packed Compare Implicit Length Strings, Return Mask
7707 multiclass pseudo_pcmpistrm<string asm> {
7708 def REG : PseudoI<(outs VR128:$dst),
7709 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7710 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7712 def MEM : PseudoI<(outs VR128:$dst),
7713 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7714 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7715 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7718 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7719 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
7720 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[UseSSE42]>;
7723 multiclass pcmpistrm_SS42AI<string asm> {
7724 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7725 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7726 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7727 []>, Sched<[WritePCmpIStrM]>;
7729 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7730 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7731 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7732 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7735 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
7736 let Predicates = [HasAVX] in
7737 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7738 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7741 // Packed Compare Explicit Length Strings, Return Mask
7742 multiclass pseudo_pcmpestrm<string asm> {
7743 def REG : PseudoI<(outs VR128:$dst),
7744 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7745 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7746 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7747 def MEM : PseudoI<(outs VR128:$dst),
7748 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7749 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7750 (bc_v16i8 (memopv2i64 addr:$src3)), EDX, imm:$src5))]>;
7753 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7754 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
7755 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[UseSSE42]>;
7758 multiclass SS42AI_pcmpestrm<string asm> {
7759 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7760 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7761 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7762 []>, Sched<[WritePCmpEStrM]>;
7764 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7765 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7766 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7767 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7770 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7771 let Predicates = [HasAVX] in
7772 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7773 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7776 // Packed Compare Implicit Length Strings, Return Index
7777 multiclass pseudo_pcmpistri<string asm> {
7778 def REG : PseudoI<(outs GR32:$dst),
7779 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7780 [(set GR32:$dst, EFLAGS,
7781 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7782 def MEM : PseudoI<(outs GR32:$dst),
7783 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7784 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7785 (bc_v16i8 (memopv2i64 addr:$src2)), imm:$src3))]>;
7788 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7789 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI">, Requires<[HasAVX]>;
7790 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI">, Requires<[UseSSE42]>;
7793 multiclass SS42AI_pcmpistri<string asm> {
7794 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7795 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7796 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7797 []>, Sched<[WritePCmpIStrI]>;
7799 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7800 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7801 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7802 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7805 let Defs = [ECX, EFLAGS], neverHasSideEffects = 1 in {
7806 let Predicates = [HasAVX] in
7807 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7808 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7811 // Packed Compare Explicit Length Strings, Return Index
7812 multiclass pseudo_pcmpestri<string asm> {
7813 def REG : PseudoI<(outs GR32:$dst),
7814 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7815 [(set GR32:$dst, EFLAGS,
7816 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7817 def MEM : PseudoI<(outs GR32:$dst),
7818 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7819 [(set GR32:$dst, EFLAGS,
7820 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (memopv2i64 addr:$src3)), EDX,
7824 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7825 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI">, Requires<[HasAVX]>;
7826 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI">, Requires<[UseSSE42]>;
7829 multiclass SS42AI_pcmpestri<string asm> {
7830 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7831 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7832 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7833 []>, Sched<[WritePCmpEStrI]>;
7835 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7836 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7837 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7838 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7841 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
7842 let Predicates = [HasAVX] in
7843 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7844 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7847 //===----------------------------------------------------------------------===//
7848 // SSE4.2 - CRC Instructions
7849 //===----------------------------------------------------------------------===//
7851 // No CRC instructions have AVX equivalents
7853 // crc intrinsic instruction
7854 // This set of instructions are only rm, the only difference is the size
7856 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7857 RegisterClass RCIn, SDPatternOperator Int> :
7858 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7859 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7860 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7863 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7864 X86MemOperand x86memop, SDPatternOperator Int> :
7865 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7866 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7867 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7868 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7870 let Constraints = "$src1 = $dst" in {
7871 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7872 int_x86_sse42_crc32_32_8>;
7873 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7874 int_x86_sse42_crc32_32_8>;
7875 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7876 int_x86_sse42_crc32_32_16>, OpSize16;
7877 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7878 int_x86_sse42_crc32_32_16>, OpSize16;
7879 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7880 int_x86_sse42_crc32_32_32>, OpSize32;
7881 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7882 int_x86_sse42_crc32_32_32>, OpSize32;
7883 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7884 int_x86_sse42_crc32_64_64>, REX_W;
7885 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7886 int_x86_sse42_crc32_64_64>, REX_W;
7887 let hasSideEffects = 0 in {
7889 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7891 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7896 //===----------------------------------------------------------------------===//
7897 // SHA-NI Instructions
7898 //===----------------------------------------------------------------------===//
7900 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7902 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7903 (ins VR128:$src1, VR128:$src2),
7904 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7906 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7907 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7909 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7910 (ins VR128:$src1, i128mem:$src2),
7911 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7913 (set VR128:$dst, (IntId VR128:$src1,
7914 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7915 (set VR128:$dst, (IntId VR128:$src1,
7916 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7919 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7920 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7921 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7922 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7924 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7925 (i8 imm:$src3)))]>, TA;
7926 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7927 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7928 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7930 (int_x86_sha1rnds4 VR128:$src1,
7931 (bc_v4i32 (memopv2i64 addr:$src2)),
7932 (i8 imm:$src3)))]>, TA;
7934 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7935 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7936 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7939 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7941 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7942 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7945 // Aliases with explicit %xmm0
7946 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7947 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7948 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7949 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7951 //===----------------------------------------------------------------------===//
7952 // AES-NI Instructions
7953 //===----------------------------------------------------------------------===//
7955 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7956 Intrinsic IntId128, bit Is2Addr = 1> {
7957 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7958 (ins VR128:$src1, VR128:$src2),
7960 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7961 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7962 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7963 Sched<[WriteAESDecEnc]>;
7964 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7965 (ins VR128:$src1, i128mem:$src2),
7967 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7968 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7970 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>,
7971 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7974 // Perform One Round of an AES Encryption/Decryption Flow
7975 let Predicates = [HasAVX, HasAES] in {
7976 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7977 int_x86_aesni_aesenc, 0>, VEX_4V;
7978 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7979 int_x86_aesni_aesenclast, 0>, VEX_4V;
7980 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7981 int_x86_aesni_aesdec, 0>, VEX_4V;
7982 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7983 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7986 let Constraints = "$src1 = $dst" in {
7987 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7988 int_x86_aesni_aesenc>;
7989 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7990 int_x86_aesni_aesenclast>;
7991 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7992 int_x86_aesni_aesdec>;
7993 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7994 int_x86_aesni_aesdeclast>;
7997 // Perform the AES InvMixColumn Transformation
7998 let Predicates = [HasAVX, HasAES] in {
7999 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
8001 "vaesimc\t{$src1, $dst|$dst, $src1}",
8003 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
8005 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
8006 (ins i128mem:$src1),
8007 "vaesimc\t{$src1, $dst|$dst, $src1}",
8008 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
8009 Sched<[WriteAESIMCLd]>, VEX;
8011 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
8013 "aesimc\t{$src1, $dst|$dst, $src1}",
8015 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
8016 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
8017 (ins i128mem:$src1),
8018 "aesimc\t{$src1, $dst|$dst, $src1}",
8019 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
8020 Sched<[WriteAESIMCLd]>;
8022 // AES Round Key Generation Assist
8023 let Predicates = [HasAVX, HasAES] in {
8024 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8025 (ins VR128:$src1, i8imm:$src2),
8026 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8028 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8029 Sched<[WriteAESKeyGen]>, VEX;
8030 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8031 (ins i128mem:$src1, i8imm:$src2),
8032 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8034 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
8035 Sched<[WriteAESKeyGenLd]>, VEX;
8037 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
8038 (ins VR128:$src1, i8imm:$src2),
8039 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8041 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
8042 Sched<[WriteAESKeyGen]>;
8043 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
8044 (ins i128mem:$src1, i8imm:$src2),
8045 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8047 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
8048 Sched<[WriteAESKeyGenLd]>;
8050 //===----------------------------------------------------------------------===//
8051 // PCLMUL Instructions
8052 //===----------------------------------------------------------------------===//
8054 // AVX carry-less Multiplication instructions
8055 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8056 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8057 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8059 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
8060 Sched<[WriteCLMul]>;
8062 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8063 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8064 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8065 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8066 (loadv2i64 addr:$src2), imm:$src3))]>,
8067 Sched<[WriteCLMulLd, ReadAfterLd]>;
8069 // Carry-less Multiplication instructions
8070 let Constraints = "$src1 = $dst" in {
8071 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
8072 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
8073 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8075 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
8076 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
8078 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
8079 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
8080 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
8081 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
8082 (memopv2i64 addr:$src2), imm:$src3))],
8083 IIC_SSE_PCLMULQDQ_RM>,
8084 Sched<[WriteCLMulLd, ReadAfterLd]>;
8085 } // Constraints = "$src1 = $dst"
8088 multiclass pclmul_alias<string asm, int immop> {
8089 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8090 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
8092 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
8093 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
8095 def : InstAlias<!strconcat("vpclmul", asm,
8096 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8097 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
8100 def : InstAlias<!strconcat("vpclmul", asm,
8101 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
8102 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
8105 defm : pclmul_alias<"hqhq", 0x11>;
8106 defm : pclmul_alias<"hqlq", 0x01>;
8107 defm : pclmul_alias<"lqhq", 0x10>;
8108 defm : pclmul_alias<"lqlq", 0x00>;
8110 //===----------------------------------------------------------------------===//
8111 // SSE4A Instructions
8112 //===----------------------------------------------------------------------===//
8114 let Predicates = [HasSSE4A] in {
8116 let Constraints = "$src = $dst" in {
8117 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
8118 (ins VR128:$src, i8imm:$len, i8imm:$idx),
8119 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
8120 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
8122 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8123 (ins VR128:$src, VR128:$mask),
8124 "extrq\t{$mask, $src|$src, $mask}",
8125 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
8126 VR128:$mask))]>, PD;
8128 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
8129 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
8130 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
8131 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
8132 VR128:$src2, imm:$len, imm:$idx))]>, XD;
8133 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
8134 (ins VR128:$src, VR128:$mask),
8135 "insertq\t{$mask, $src|$src, $mask}",
8136 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
8137 VR128:$mask))]>, XD;
8140 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
8141 "movntss\t{$src, $dst|$dst, $src}",
8142 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
8144 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
8145 "movntsd\t{$src, $dst|$dst, $src}",
8146 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
8149 //===----------------------------------------------------------------------===//
8151 //===----------------------------------------------------------------------===//
8153 //===----------------------------------------------------------------------===//
8154 // VBROADCAST - Load from memory and broadcast to all elements of the
8155 // destination operand
8157 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
8158 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
8159 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8160 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8161 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
8163 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
8164 X86MemOperand x86memop, ValueType VT,
8165 PatFrag ld_frag, SchedWrite Sched> :
8166 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8167 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8168 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
8169 Sched<[Sched]>, VEX {
8173 // AVX2 adds register forms
8174 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
8175 Intrinsic Int, SchedWrite Sched> :
8176 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8177 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8178 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
8180 let ExeDomain = SSEPackedSingle in {
8181 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
8182 f32mem, v4f32, loadf32, WriteLoad>;
8183 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
8184 f32mem, v8f32, loadf32,
8185 WriteFShuffleLd>, VEX_L;
8187 let ExeDomain = SSEPackedDouble in
8188 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
8189 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
8190 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
8191 int_x86_avx_vbroadcastf128_pd_256,
8192 WriteFShuffleLd>, VEX_L;
8194 let ExeDomain = SSEPackedSingle in {
8195 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
8196 int_x86_avx2_vbroadcast_ss_ps,
8198 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
8199 int_x86_avx2_vbroadcast_ss_ps_256,
8200 WriteFShuffle256>, VEX_L;
8202 let ExeDomain = SSEPackedDouble in
8203 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
8204 int_x86_avx2_vbroadcast_sd_pd_256,
8205 WriteFShuffle256>, VEX_L;
8207 let Predicates = [HasAVX2] in
8208 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
8209 int_x86_avx2_vbroadcasti128, WriteLoad>,
8212 let Predicates = [HasAVX] in
8213 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
8214 (VBROADCASTF128 addr:$src)>;
8217 //===----------------------------------------------------------------------===//
8218 // VINSERTF128 - Insert packed floating-point values
8220 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8221 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
8222 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8223 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8224 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
8226 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
8227 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
8228 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8229 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
8232 let Predicates = [HasAVX] in {
8233 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
8235 (VINSERTF128rr VR256:$src1, VR128:$src2,
8236 (INSERT_get_vinsert128_imm VR256:$ins))>;
8237 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
8239 (VINSERTF128rr VR256:$src1, VR128:$src2,
8240 (INSERT_get_vinsert128_imm VR256:$ins))>;
8242 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
8244 (VINSERTF128rm VR256:$src1, addr:$src2,
8245 (INSERT_get_vinsert128_imm VR256:$ins))>;
8246 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
8248 (VINSERTF128rm VR256:$src1, addr:$src2,
8249 (INSERT_get_vinsert128_imm VR256:$ins))>;
8252 let Predicates = [HasAVX1Only] in {
8253 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8255 (VINSERTF128rr VR256:$src1, VR128:$src2,
8256 (INSERT_get_vinsert128_imm VR256:$ins))>;
8257 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8259 (VINSERTF128rr VR256:$src1, VR128:$src2,
8260 (INSERT_get_vinsert128_imm VR256:$ins))>;
8261 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8263 (VINSERTF128rr VR256:$src1, VR128:$src2,
8264 (INSERT_get_vinsert128_imm VR256:$ins))>;
8265 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8267 (VINSERTF128rr VR256:$src1, VR128:$src2,
8268 (INSERT_get_vinsert128_imm VR256:$ins))>;
8270 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8272 (VINSERTF128rm VR256:$src1, addr:$src2,
8273 (INSERT_get_vinsert128_imm VR256:$ins))>;
8274 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8275 (bc_v4i32 (loadv2i64 addr:$src2)),
8277 (VINSERTF128rm VR256:$src1, addr:$src2,
8278 (INSERT_get_vinsert128_imm VR256:$ins))>;
8279 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8280 (bc_v16i8 (loadv2i64 addr:$src2)),
8282 (VINSERTF128rm VR256:$src1, addr:$src2,
8283 (INSERT_get_vinsert128_imm VR256:$ins))>;
8284 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8285 (bc_v8i16 (loadv2i64 addr:$src2)),
8287 (VINSERTF128rm VR256:$src1, addr:$src2,
8288 (INSERT_get_vinsert128_imm VR256:$ins))>;
8291 //===----------------------------------------------------------------------===//
8292 // VEXTRACTF128 - Extract packed floating-point values
8294 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
8295 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
8296 (ins VR256:$src1, i8imm:$src2),
8297 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8298 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
8300 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
8301 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
8302 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8303 []>, Sched<[WriteStore]>, VEX, VEX_L;
8307 let Predicates = [HasAVX] in {
8308 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8309 (v4f32 (VEXTRACTF128rr
8310 (v8f32 VR256:$src1),
8311 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8312 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8313 (v2f64 (VEXTRACTF128rr
8314 (v4f64 VR256:$src1),
8315 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8317 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
8318 (iPTR imm))), addr:$dst),
8319 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8320 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8321 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
8322 (iPTR imm))), addr:$dst),
8323 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8324 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8327 let Predicates = [HasAVX1Only] in {
8328 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8329 (v2i64 (VEXTRACTF128rr
8330 (v4i64 VR256:$src1),
8331 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8332 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8333 (v4i32 (VEXTRACTF128rr
8334 (v8i32 VR256:$src1),
8335 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8336 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8337 (v8i16 (VEXTRACTF128rr
8338 (v16i16 VR256:$src1),
8339 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8340 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8341 (v16i8 (VEXTRACTF128rr
8342 (v32i8 VR256:$src1),
8343 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8345 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8346 (iPTR imm))), addr:$dst),
8347 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8348 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8349 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8350 (iPTR imm))), addr:$dst),
8351 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8352 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8353 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8354 (iPTR imm))), addr:$dst),
8355 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8356 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8357 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8358 (iPTR imm))), addr:$dst),
8359 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8360 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8363 //===----------------------------------------------------------------------===//
8364 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8366 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8367 Intrinsic IntLd, Intrinsic IntLd256,
8368 Intrinsic IntSt, Intrinsic IntSt256> {
8369 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8370 (ins VR128:$src1, f128mem:$src2),
8371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8372 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8374 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8375 (ins VR256:$src1, f256mem:$src2),
8376 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8377 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8379 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8380 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8381 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8382 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8383 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8384 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8385 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8386 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8389 let ExeDomain = SSEPackedSingle in
8390 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8391 int_x86_avx_maskload_ps,
8392 int_x86_avx_maskload_ps_256,
8393 int_x86_avx_maskstore_ps,
8394 int_x86_avx_maskstore_ps_256>;
8395 let ExeDomain = SSEPackedDouble in
8396 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8397 int_x86_avx_maskload_pd,
8398 int_x86_avx_maskload_pd_256,
8399 int_x86_avx_maskstore_pd,
8400 int_x86_avx_maskstore_pd_256>;
8402 //===----------------------------------------------------------------------===//
8403 // VPERMIL - Permute Single and Double Floating-Point Values
8405 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8406 RegisterClass RC, X86MemOperand x86memop_f,
8407 X86MemOperand x86memop_i, PatFrag i_frag,
8408 Intrinsic IntVar, ValueType vt> {
8409 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8410 (ins RC:$src1, RC:$src2),
8411 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8412 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8413 Sched<[WriteFShuffle]>;
8414 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8415 (ins RC:$src1, x86memop_i:$src2),
8416 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8417 [(set RC:$dst, (IntVar RC:$src1,
8418 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8419 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8421 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8422 (ins RC:$src1, i8imm:$src2),
8423 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8424 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8425 Sched<[WriteFShuffle]>;
8426 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8427 (ins x86memop_f:$src1, i8imm:$src2),
8428 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8430 (vt (X86VPermilpi (memop addr:$src1), (i8 imm:$src2))))]>, VEX,
8431 Sched<[WriteFShuffleLd]>;
8434 let ExeDomain = SSEPackedSingle in {
8435 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8436 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8437 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8438 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8440 let ExeDomain = SSEPackedDouble in {
8441 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8442 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8443 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8444 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8447 let Predicates = [HasAVX] in {
8448 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8449 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8450 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8451 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8452 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8453 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8454 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8455 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8457 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8458 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8459 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8460 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8461 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8463 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8464 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8465 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8467 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8468 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8469 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8470 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8471 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8472 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8473 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8474 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8476 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8477 (VPERMILPDri VR128:$src1, imm:$imm)>;
8478 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8479 (VPERMILPDmi addr:$src1, imm:$imm)>;
8482 //===----------------------------------------------------------------------===//
8483 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8485 let ExeDomain = SSEPackedSingle in {
8486 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8487 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8488 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8489 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8490 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8491 Sched<[WriteFShuffle]>;
8492 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8493 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8494 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8495 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8496 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8497 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8500 let Predicates = [HasAVX] in {
8501 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8502 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8503 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8504 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8505 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8508 let Predicates = [HasAVX1Only] in {
8509 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8510 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8511 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8512 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8513 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8514 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8515 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8516 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8518 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8519 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8520 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8521 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8522 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8523 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8524 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8525 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8526 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8527 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8528 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8529 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8532 //===----------------------------------------------------------------------===//
8533 // VZERO - Zero YMM registers
8535 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8536 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8537 // Zero All YMM registers
8538 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8539 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8541 // Zero Upper bits of YMM registers
8542 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8543 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8546 //===----------------------------------------------------------------------===//
8547 // Half precision conversion instructions
8548 //===----------------------------------------------------------------------===//
8549 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8550 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8551 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8552 [(set RC:$dst, (Int VR128:$src))]>,
8553 T8PD, VEX, Sched<[WriteCvtF2F]>;
8554 let neverHasSideEffects = 1, mayLoad = 1 in
8555 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8556 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8557 Sched<[WriteCvtF2FLd]>;
8560 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8561 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8562 (ins RC:$src1, i32i8imm:$src2),
8563 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8564 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8565 TAPD, VEX, Sched<[WriteCvtF2F]>;
8566 let neverHasSideEffects = 1, mayStore = 1,
8567 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8568 def mr : Ii8<0x1D, MRMDestMem, (outs),
8569 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
8570 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8574 let Predicates = [HasF16C] in {
8575 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8576 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8577 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8578 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8580 // Pattern match vcvtph2ps of a scalar i64 load.
8581 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8582 (VCVTPH2PSrm addr:$src)>;
8583 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8584 (VCVTPH2PSrm addr:$src)>;
8587 // Patterns for matching conversions from float to half-float and vice versa.
8588 let Predicates = [HasF16C] in {
8589 def : Pat<(fp_to_f16 FR32:$src),
8590 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8591 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8593 def : Pat<(f16_to_fp GR16:$src),
8594 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8595 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8597 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8598 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8599 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8602 //===----------------------------------------------------------------------===//
8603 // AVX2 Instructions
8604 //===----------------------------------------------------------------------===//
8606 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
8607 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
8608 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
8609 X86MemOperand x86memop> {
8610 let isCommutable = 1 in
8611 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8612 (ins RC:$src1, RC:$src2, i8imm:$src3),
8613 !strconcat(OpcodeStr,
8614 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8615 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
8616 Sched<[WriteBlend]>, VEX_4V;
8617 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8618 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
8619 !strconcat(OpcodeStr,
8620 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8623 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
8624 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8627 let isCommutable = 0 in {
8628 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
8629 VR128, loadv2i64, i128mem>;
8630 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
8631 VR256, loadv4i64, i256mem>, VEX_L;
8634 def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),
8636 (VPBLENDDrri VR128:$src1, VR128:$src2, imm:$mask)>;
8637 def : Pat<(v8i32 (X86Blendi (v8i32 VR256:$src1), (v8i32 VR256:$src2),
8639 (VPBLENDDYrri VR256:$src1, VR256:$src2, imm:$mask)>;
8641 //===----------------------------------------------------------------------===//
8642 // VPBROADCAST - Load from memory and broadcast to all elements of the
8643 // destination operand
8645 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8646 X86MemOperand x86memop, PatFrag ld_frag,
8647 Intrinsic Int128, Intrinsic Int256> {
8648 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8649 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8650 [(set VR128:$dst, (Int128 VR128:$src))]>,
8651 Sched<[WriteShuffle]>, VEX;
8652 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8653 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8655 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8656 Sched<[WriteLoad]>, VEX;
8657 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8658 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8659 [(set VR256:$dst, (Int256 VR128:$src))]>,
8660 Sched<[WriteShuffle256]>, VEX, VEX_L;
8661 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8662 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8664 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8665 Sched<[WriteLoad]>, VEX, VEX_L;
8668 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8669 int_x86_avx2_pbroadcastb_128,
8670 int_x86_avx2_pbroadcastb_256>;
8671 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8672 int_x86_avx2_pbroadcastw_128,
8673 int_x86_avx2_pbroadcastw_256>;
8674 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8675 int_x86_avx2_pbroadcastd_128,
8676 int_x86_avx2_pbroadcastd_256>;
8677 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8678 int_x86_avx2_pbroadcastq_128,
8679 int_x86_avx2_pbroadcastq_256>;
8681 let Predicates = [HasAVX2] in {
8682 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8683 (VPBROADCASTBrm addr:$src)>;
8684 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8685 (VPBROADCASTBYrm addr:$src)>;
8686 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8687 (VPBROADCASTWrm addr:$src)>;
8688 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8689 (VPBROADCASTWYrm addr:$src)>;
8690 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8691 (VPBROADCASTDrm addr:$src)>;
8692 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8693 (VPBROADCASTDYrm addr:$src)>;
8694 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8695 (VPBROADCASTQrm addr:$src)>;
8696 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8697 (VPBROADCASTQYrm addr:$src)>;
8699 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8700 (VPBROADCASTBrr VR128:$src)>;
8701 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8702 (VPBROADCASTBYrr VR128:$src)>;
8703 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8704 (VPBROADCASTWrr VR128:$src)>;
8705 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8706 (VPBROADCASTWYrr VR128:$src)>;
8707 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8708 (VPBROADCASTDrr VR128:$src)>;
8709 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8710 (VPBROADCASTDYrr VR128:$src)>;
8711 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8712 (VPBROADCASTQrr VR128:$src)>;
8713 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8714 (VPBROADCASTQYrr VR128:$src)>;
8715 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8716 (VBROADCASTSSrr VR128:$src)>;
8717 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8718 (VBROADCASTSSYrr VR128:$src)>;
8719 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8720 (VPBROADCASTQrr VR128:$src)>;
8721 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8722 (VBROADCASTSDYrr VR128:$src)>;
8724 // Provide aliases for broadcast from the same regitser class that
8725 // automatically does the extract.
8726 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8727 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8729 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8730 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8732 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8733 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8735 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8736 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8738 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8739 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8741 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8742 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8745 // Provide fallback in case the load node that is used in the patterns above
8746 // is used by additional users, which prevents the pattern selection.
8747 let AddedComplexity = 20 in {
8748 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8749 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8750 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8751 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8752 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8753 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8755 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8756 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8757 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8758 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8759 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8760 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8762 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8763 (VPBROADCASTBrr (COPY_TO_REGCLASS
8764 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8766 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8767 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8768 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8771 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8772 (VPBROADCASTWrr (COPY_TO_REGCLASS
8773 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8775 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8776 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8777 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8780 // The patterns for VPBROADCASTD are not needed because they would match
8781 // the exact same thing as VBROADCASTSS patterns.
8783 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8784 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8785 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8789 // AVX1 broadcast patterns
8790 let Predicates = [HasAVX1Only] in {
8791 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8792 (VBROADCASTSSYrm addr:$src)>;
8793 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8794 (VBROADCASTSDYrm addr:$src)>;
8795 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8796 (VBROADCASTSSrm addr:$src)>;
8799 let Predicates = [HasAVX] in {
8800 // Provide fallback in case the load node that is used in the patterns above
8801 // is used by additional users, which prevents the pattern selection.
8802 let AddedComplexity = 20 in {
8803 // 128bit broadcasts:
8804 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8805 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8806 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8807 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8808 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8809 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8810 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8811 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8812 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8813 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8815 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8816 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8817 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8818 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8819 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8820 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8821 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8822 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8823 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8824 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8827 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8828 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8831 //===----------------------------------------------------------------------===//
8832 // VPERM - Permute instructions
8835 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8836 ValueType OpVT, X86FoldableSchedWrite Sched> {
8837 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8838 (ins VR256:$src1, VR256:$src2),
8839 !strconcat(OpcodeStr,
8840 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8842 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8843 Sched<[Sched]>, VEX_4V, VEX_L;
8844 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8845 (ins VR256:$src1, i256mem:$src2),
8846 !strconcat(OpcodeStr,
8847 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8849 (OpVT (X86VPermv VR256:$src1,
8850 (bitconvert (mem_frag addr:$src2)))))]>,
8851 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8854 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8855 let ExeDomain = SSEPackedSingle in
8856 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8858 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8859 ValueType OpVT, X86FoldableSchedWrite Sched> {
8860 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8861 (ins VR256:$src1, i8imm:$src2),
8862 !strconcat(OpcodeStr,
8863 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8865 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8866 Sched<[Sched]>, VEX, VEX_L;
8867 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8868 (ins i256mem:$src1, i8imm:$src2),
8869 !strconcat(OpcodeStr,
8870 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8872 (OpVT (X86VPermi (mem_frag addr:$src1),
8873 (i8 imm:$src2))))]>,
8874 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8877 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8878 WriteShuffle256>, VEX_W;
8879 let ExeDomain = SSEPackedDouble in
8880 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8881 WriteFShuffle256>, VEX_W;
8883 //===----------------------------------------------------------------------===//
8884 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8886 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8887 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
8888 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8889 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8890 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8892 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8893 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
8894 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8895 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8897 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8899 let Predicates = [HasAVX2] in {
8900 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8901 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8902 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8903 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8904 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8905 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8907 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8909 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8910 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8911 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8912 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8913 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8915 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8919 //===----------------------------------------------------------------------===//
8920 // VINSERTI128 - Insert packed integer values
8922 let neverHasSideEffects = 1 in {
8923 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8924 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
8925 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8926 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8928 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8929 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
8930 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8931 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8934 let Predicates = [HasAVX2] in {
8935 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8937 (VINSERTI128rr VR256:$src1, VR128:$src2,
8938 (INSERT_get_vinsert128_imm VR256:$ins))>;
8939 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8941 (VINSERTI128rr VR256:$src1, VR128:$src2,
8942 (INSERT_get_vinsert128_imm VR256:$ins))>;
8943 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8945 (VINSERTI128rr VR256:$src1, VR128:$src2,
8946 (INSERT_get_vinsert128_imm VR256:$ins))>;
8947 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8949 (VINSERTI128rr VR256:$src1, VR128:$src2,
8950 (INSERT_get_vinsert128_imm VR256:$ins))>;
8952 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8954 (VINSERTI128rm VR256:$src1, addr:$src2,
8955 (INSERT_get_vinsert128_imm VR256:$ins))>;
8956 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8957 (bc_v4i32 (loadv2i64 addr:$src2)),
8959 (VINSERTI128rm VR256:$src1, addr:$src2,
8960 (INSERT_get_vinsert128_imm VR256:$ins))>;
8961 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8962 (bc_v16i8 (loadv2i64 addr:$src2)),
8964 (VINSERTI128rm VR256:$src1, addr:$src2,
8965 (INSERT_get_vinsert128_imm VR256:$ins))>;
8966 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8967 (bc_v8i16 (loadv2i64 addr:$src2)),
8969 (VINSERTI128rm VR256:$src1, addr:$src2,
8970 (INSERT_get_vinsert128_imm VR256:$ins))>;
8973 //===----------------------------------------------------------------------===//
8974 // VEXTRACTI128 - Extract packed integer values
8976 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8977 (ins VR256:$src1, i8imm:$src2),
8978 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8980 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
8981 Sched<[WriteShuffle256]>, VEX, VEX_L;
8982 let neverHasSideEffects = 1, mayStore = 1 in
8983 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8984 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
8985 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8986 Sched<[WriteStore]>, VEX, VEX_L;
8988 let Predicates = [HasAVX2] in {
8989 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8990 (v2i64 (VEXTRACTI128rr
8991 (v4i64 VR256:$src1),
8992 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8993 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8994 (v4i32 (VEXTRACTI128rr
8995 (v8i32 VR256:$src1),
8996 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8997 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8998 (v8i16 (VEXTRACTI128rr
8999 (v16i16 VR256:$src1),
9000 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
9001 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
9002 (v16i8 (VEXTRACTI128rr
9003 (v32i8 VR256:$src1),
9004 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
9006 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
9007 (iPTR imm))), addr:$dst),
9008 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9009 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9010 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
9011 (iPTR imm))), addr:$dst),
9012 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9013 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9014 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
9015 (iPTR imm))), addr:$dst),
9016 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9017 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9018 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
9019 (iPTR imm))), addr:$dst),
9020 (VEXTRACTI128mr addr:$dst, VR256:$src1,
9021 (EXTRACT_get_vextract128_imm VR128:$ext))>;
9024 //===----------------------------------------------------------------------===//
9025 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
9027 multiclass avx2_pmovmask<string OpcodeStr,
9028 Intrinsic IntLd128, Intrinsic IntLd256,
9029 Intrinsic IntSt128, Intrinsic IntSt256> {
9030 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
9031 (ins VR128:$src1, i128mem:$src2),
9032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9033 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
9034 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
9035 (ins VR256:$src1, i256mem:$src2),
9036 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9037 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
9039 def mr : AVX28I<0x8e, MRMDestMem, (outs),
9040 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
9041 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9042 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
9043 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
9044 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
9045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9046 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
9049 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
9050 int_x86_avx2_maskload_d,
9051 int_x86_avx2_maskload_d_256,
9052 int_x86_avx2_maskstore_d,
9053 int_x86_avx2_maskstore_d_256>;
9054 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
9055 int_x86_avx2_maskload_q,
9056 int_x86_avx2_maskload_q_256,
9057 int_x86_avx2_maskstore_q,
9058 int_x86_avx2_maskstore_q_256>, VEX_W;
9061 //===----------------------------------------------------------------------===//
9062 // Variable Bit Shifts
9064 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
9065 ValueType vt128, ValueType vt256> {
9066 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
9067 (ins VR128:$src1, VR128:$src2),
9068 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9070 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
9071 VEX_4V, Sched<[WriteVarVecShift]>;
9072 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
9073 (ins VR128:$src1, i128mem:$src2),
9074 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9076 (vt128 (OpNode VR128:$src1,
9077 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
9078 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9079 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
9080 (ins VR256:$src1, VR256:$src2),
9081 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9083 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
9084 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
9085 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
9086 (ins VR256:$src1, i256mem:$src2),
9087 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
9089 (vt256 (OpNode VR256:$src1,
9090 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
9091 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
9094 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
9095 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
9096 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
9097 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
9098 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
9100 //===----------------------------------------------------------------------===//
9101 // VGATHER - GATHER Operations
9102 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
9103 X86MemOperand memop128, X86MemOperand memop256> {
9104 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
9105 (ins VR128:$src1, memop128:$src2, VR128:$mask),
9106 !strconcat(OpcodeStr,
9107 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9109 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
9110 (ins RC256:$src1, memop256:$src2, RC256:$mask),
9111 !strconcat(OpcodeStr,
9112 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
9113 []>, VEX_4VOp3, VEX_L;
9116 let mayLoad = 1, Constraints
9117 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
9119 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
9120 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
9121 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
9122 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
9124 let ExeDomain = SSEPackedDouble in {
9125 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
9126 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
9129 let ExeDomain = SSEPackedSingle in {
9130 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
9131 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;