1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (st node:$val, node:$ptr), [{
102 StoreSDNode *ST = cast<StoreSDNode>(N);
103 return !ST->isTruncatingStore() &&
104 ST->getAddressingMode() == ISD::UNINDEXED &&
105 ST->getAlignment() >= 16;
108 // Like 'load', but always requires vector alignment.
109 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
110 LoadSDNode *LD = cast<LoadSDNode>(N);
111 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
112 LD->getAddressingMode() == ISD::UNINDEXED &&
113 LD->getAlignment() >= 16;
116 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
117 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
118 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
119 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
120 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
121 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
123 // Like 'load', but uses special alignment checks suitable for use in
124 // memory operands in most SSE instructions, which are required to
125 // be naturally aligned on some targets but not on others.
126 // FIXME: Actually implement support for targets that don't require the
127 // alignment. This probably wants a subtarget predicate.
128 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
129 LoadSDNode *LD = cast<LoadSDNode>(N);
130 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
131 LD->getAddressingMode() == ISD::UNINDEXED &&
132 LD->getAlignment() >= 16;
135 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
136 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
137 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
138 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
139 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
140 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
141 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
143 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
145 // FIXME: 8 byte alignment for mmx reads is not required
146 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
147 LoadSDNode *LD = cast<LoadSDNode>(N);
148 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
149 LD->getAddressingMode() == ISD::UNINDEXED &&
150 LD->getAlignment() >= 8;
153 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
154 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
155 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
156 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
158 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
159 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
160 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
161 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
162 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
163 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
165 def vzmovl_v2i64 : PatFrag<(ops node:$src),
166 (bitconvert (v2i64 (X86vzmovl
167 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
168 def vzmovl_v4i32 : PatFrag<(ops node:$src),
169 (bitconvert (v4i32 (X86vzmovl
170 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
172 def vzload_v2i64 : PatFrag<(ops node:$src),
173 (bitconvert (v2i64 (X86vzload node:$src)))>;
176 def fp32imm0 : PatLeaf<(f32 fpimm), [{
177 return N->isExactlyValue(+0.0);
180 def PSxLDQ_imm : SDNodeXForm<imm, [{
181 // Transformation function: imm >> 3
182 return getI32Imm(N->getZExtValue() >> 3);
185 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
187 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
188 return getI8Imm(X86::getShuffleSHUFImmediate(N));
191 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
193 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
194 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
197 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
199 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
200 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
203 def SSE_splat_mask : PatLeaf<(build_vector), [{
204 return X86::isSplatMask(N);
205 }], SHUFFLE_get_shuf_imm>;
207 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
208 return X86::isSplatLoMask(N);
211 def MOVDDUP_shuffle_mask : PatLeaf<(build_vector), [{
212 return X86::isMOVDDUPMask(N);
215 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
216 return X86::isMOVHLPSMask(N);
219 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
220 return X86::isMOVHLPS_v_undef_Mask(N);
223 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
224 return X86::isMOVHPMask(N);
227 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
228 return X86::isMOVLPMask(N);
231 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
232 return X86::isMOVLMask(N);
235 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
236 return X86::isMOVSHDUPMask(N);
239 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
240 return X86::isMOVSLDUPMask(N);
243 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
244 return X86::isUNPCKLMask(N);
247 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
248 return X86::isUNPCKHMask(N);
251 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
252 return X86::isUNPCKL_v_undef_Mask(N);
255 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
256 return X86::isUNPCKH_v_undef_Mask(N);
259 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
260 return X86::isPSHUFDMask(N);
261 }], SHUFFLE_get_shuf_imm>;
263 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
264 return X86::isPSHUFHWMask(N);
265 }], SHUFFLE_get_pshufhw_imm>;
267 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
268 return X86::isPSHUFLWMask(N);
269 }], SHUFFLE_get_pshuflw_imm>;
271 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
272 return X86::isPSHUFDMask(N);
273 }], SHUFFLE_get_shuf_imm>;
275 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
276 return X86::isSHUFPMask(N);
277 }], SHUFFLE_get_shuf_imm>;
279 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
280 return X86::isSHUFPMask(N);
281 }], SHUFFLE_get_shuf_imm>;
284 //===----------------------------------------------------------------------===//
285 // SSE scalar FP Instructions
286 //===----------------------------------------------------------------------===//
288 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
289 // scheduler into a branch sequence.
290 // These are expanded by the scheduler.
291 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
292 def CMOV_FR32 : I<0, Pseudo,
293 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
294 "#CMOV_FR32 PSEUDO!",
295 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
297 def CMOV_FR64 : I<0, Pseudo,
298 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
299 "#CMOV_FR64 PSEUDO!",
300 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
302 def CMOV_V4F32 : I<0, Pseudo,
303 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
304 "#CMOV_V4F32 PSEUDO!",
306 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
308 def CMOV_V2F64 : I<0, Pseudo,
309 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
310 "#CMOV_V2F64 PSEUDO!",
312 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
314 def CMOV_V2I64 : I<0, Pseudo,
315 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
316 "#CMOV_V2I64 PSEUDO!",
318 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
322 //===----------------------------------------------------------------------===//
324 //===----------------------------------------------------------------------===//
327 let neverHasSideEffects = 1 in
328 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
329 "movss\t{$src, $dst|$dst, $src}", []>;
330 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
331 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
332 "movss\t{$src, $dst|$dst, $src}",
333 [(set FR32:$dst, (loadf32 addr:$src))]>;
334 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
335 "movss\t{$src, $dst|$dst, $src}",
336 [(store FR32:$src, addr:$dst)]>;
338 // Conversion instructions
339 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
340 "cvttss2si\t{$src, $dst|$dst, $src}",
341 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
342 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
343 "cvttss2si\t{$src, $dst|$dst, $src}",
344 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
345 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
346 "cvtsi2ss\t{$src, $dst|$dst, $src}",
347 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
348 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
349 "cvtsi2ss\t{$src, $dst|$dst, $src}",
350 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
352 // Match intrinsics which expect XMM operand(s).
353 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
354 "cvtss2si\t{$src, $dst|$dst, $src}",
355 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
356 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
357 "cvtss2si\t{$src, $dst|$dst, $src}",
358 [(set GR32:$dst, (int_x86_sse_cvtss2si
359 (load addr:$src)))]>;
361 // Match intrinisics which expect MM and XMM operand(s).
362 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
363 "cvtps2pi\t{$src, $dst|$dst, $src}",
364 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
365 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
366 "cvtps2pi\t{$src, $dst|$dst, $src}",
367 [(set VR64:$dst, (int_x86_sse_cvtps2pi
368 (load addr:$src)))]>;
369 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
370 "cvttps2pi\t{$src, $dst|$dst, $src}",
371 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
372 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
373 "cvttps2pi\t{$src, $dst|$dst, $src}",
374 [(set VR64:$dst, (int_x86_sse_cvttps2pi
375 (load addr:$src)))]>;
376 let Constraints = "$src1 = $dst" in {
377 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
378 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
379 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
380 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
382 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
383 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
384 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
385 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
386 (load addr:$src2)))]>;
389 // Aliases for intrinsics
390 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
391 "cvttss2si\t{$src, $dst|$dst, $src}",
393 (int_x86_sse_cvttss2si VR128:$src))]>;
394 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
395 "cvttss2si\t{$src, $dst|$dst, $src}",
397 (int_x86_sse_cvttss2si(load addr:$src)))]>;
399 let Constraints = "$src1 = $dst" in {
400 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
401 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
402 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
403 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
405 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
406 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
407 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
408 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
409 (loadi32 addr:$src2)))]>;
412 // Comparison instructions
413 let Constraints = "$src1 = $dst" in {
414 let neverHasSideEffects = 1 in
415 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
416 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
417 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
418 let neverHasSideEffects = 1, mayLoad = 1 in
419 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
420 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
421 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
424 let Defs = [EFLAGS] in {
425 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
426 "ucomiss\t{$src2, $src1|$src1, $src2}",
427 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
428 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
429 "ucomiss\t{$src2, $src1|$src1, $src2}",
430 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
434 // Aliases to match intrinsics which expect XMM operand(s).
435 let Constraints = "$src1 = $dst" in {
436 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
437 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
438 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
439 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
440 VR128:$src, imm:$cc))]>;
441 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
442 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
443 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
444 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
445 (load addr:$src), imm:$cc))]>;
448 let Defs = [EFLAGS] in {
449 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
450 (ins VR128:$src1, VR128:$src2),
451 "ucomiss\t{$src2, $src1|$src1, $src2}",
452 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
454 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
455 (ins VR128:$src1, f128mem:$src2),
456 "ucomiss\t{$src2, $src1|$src1, $src2}",
457 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
460 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
461 (ins VR128:$src1, VR128:$src2),
462 "comiss\t{$src2, $src1|$src1, $src2}",
463 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
465 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
466 (ins VR128:$src1, f128mem:$src2),
467 "comiss\t{$src2, $src1|$src1, $src2}",
468 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
472 // Aliases of packed SSE1 instructions for scalar use. These all have names that
475 // Alias instructions that map fld0 to pxor for sse.
476 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
477 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
478 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
479 Requires<[HasSSE1]>, TB, OpSize;
481 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
483 let neverHasSideEffects = 1 in
484 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
485 "movaps\t{$src, $dst|$dst, $src}", []>;
487 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
489 let isSimpleLoad = 1 in
490 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
491 "movaps\t{$src, $dst|$dst, $src}",
492 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
494 // Alias bitwise logical operations using SSE logical ops on packed FP values.
495 let Constraints = "$src1 = $dst" in {
496 let isCommutable = 1 in {
497 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
498 "andps\t{$src2, $dst|$dst, $src2}",
499 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
500 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
501 "orps\t{$src2, $dst|$dst, $src2}",
502 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
503 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
504 "xorps\t{$src2, $dst|$dst, $src2}",
505 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
508 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
509 "andps\t{$src2, $dst|$dst, $src2}",
510 [(set FR32:$dst, (X86fand FR32:$src1,
511 (memopfsf32 addr:$src2)))]>;
512 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
513 "orps\t{$src2, $dst|$dst, $src2}",
514 [(set FR32:$dst, (X86for FR32:$src1,
515 (memopfsf32 addr:$src2)))]>;
516 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
517 "xorps\t{$src2, $dst|$dst, $src2}",
518 [(set FR32:$dst, (X86fxor FR32:$src1,
519 (memopfsf32 addr:$src2)))]>;
520 let neverHasSideEffects = 1 in {
521 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
522 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
523 "andnps\t{$src2, $dst|$dst, $src2}", []>;
526 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
527 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
528 "andnps\t{$src2, $dst|$dst, $src2}", []>;
532 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
534 /// In addition, we also have a special variant of the scalar form here to
535 /// represent the associated intrinsic operation. This form is unlike the
536 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
537 /// and leaves the top elements undefined.
539 /// These three forms can each be reg+reg or reg+mem, so there are a total of
540 /// six "instructions".
542 let Constraints = "$src1 = $dst" in {
543 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
544 SDNode OpNode, Intrinsic F32Int,
545 bit Commutable = 0> {
546 // Scalar operation, reg+reg.
547 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
548 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
549 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
550 let isCommutable = Commutable;
553 // Scalar operation, reg+mem.
554 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
555 (ins FR32:$src1, f32mem:$src2),
556 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
557 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
559 // Vector operation, reg+reg.
560 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
561 (ins VR128:$src1, VR128:$src2),
562 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
563 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
564 let isCommutable = Commutable;
567 // Vector operation, reg+mem.
568 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
569 (ins VR128:$src1, f128mem:$src2),
570 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
571 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
573 // Intrinsic operation, reg+reg.
574 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
575 (ins VR128:$src1, VR128:$src2),
576 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
577 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
578 let isCommutable = Commutable;
581 // Intrinsic operation, reg+mem.
582 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
583 (ins VR128:$src1, ssmem:$src2),
584 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
585 [(set VR128:$dst, (F32Int VR128:$src1,
586 sse_load_f32:$src2))]>;
590 // Arithmetic instructions
591 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
592 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
593 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
594 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
596 /// sse1_fp_binop_rm - Other SSE1 binops
598 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
599 /// instructions for a full-vector intrinsic form. Operations that map
600 /// onto C operators don't use this form since they just use the plain
601 /// vector form instead of having a separate vector intrinsic form.
603 /// This provides a total of eight "instructions".
605 let Constraints = "$src1 = $dst" in {
606 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
610 bit Commutable = 0> {
612 // Scalar operation, reg+reg.
613 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
614 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
615 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
616 let isCommutable = Commutable;
619 // Scalar operation, reg+mem.
620 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
621 (ins FR32:$src1, f32mem:$src2),
622 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
623 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
625 // Vector operation, reg+reg.
626 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
627 (ins VR128:$src1, VR128:$src2),
628 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
629 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
630 let isCommutable = Commutable;
633 // Vector operation, reg+mem.
634 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
635 (ins VR128:$src1, f128mem:$src2),
636 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
637 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
639 // Intrinsic operation, reg+reg.
640 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
641 (ins VR128:$src1, VR128:$src2),
642 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
643 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
644 let isCommutable = Commutable;
647 // Intrinsic operation, reg+mem.
648 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
649 (ins VR128:$src1, ssmem:$src2),
650 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
651 [(set VR128:$dst, (F32Int VR128:$src1,
652 sse_load_f32:$src2))]>;
654 // Vector intrinsic operation, reg+reg.
655 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
656 (ins VR128:$src1, VR128:$src2),
657 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
658 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
659 let isCommutable = Commutable;
662 // Vector intrinsic operation, reg+mem.
663 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
664 (ins VR128:$src1, f128mem:$src2),
665 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
666 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
670 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
671 int_x86_sse_max_ss, int_x86_sse_max_ps>;
672 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
673 int_x86_sse_min_ss, int_x86_sse_min_ps>;
675 //===----------------------------------------------------------------------===//
676 // SSE packed FP Instructions
679 let neverHasSideEffects = 1 in
680 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
681 "movaps\t{$src, $dst|$dst, $src}", []>;
682 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
683 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
684 "movaps\t{$src, $dst|$dst, $src}",
685 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
687 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
688 "movaps\t{$src, $dst|$dst, $src}",
689 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
691 let neverHasSideEffects = 1 in
692 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
693 "movups\t{$src, $dst|$dst, $src}", []>;
694 let isSimpleLoad = 1 in
695 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
696 "movups\t{$src, $dst|$dst, $src}",
697 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
698 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
699 "movups\t{$src, $dst|$dst, $src}",
700 [(store (v4f32 VR128:$src), addr:$dst)]>;
702 // Intrinsic forms of MOVUPS load and store
703 let isSimpleLoad = 1 in
704 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
705 "movups\t{$src, $dst|$dst, $src}",
706 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
707 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
708 "movups\t{$src, $dst|$dst, $src}",
709 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
711 let Constraints = "$src1 = $dst" in {
712 let AddedComplexity = 20 in {
713 def MOVLPSrm : PSI<0x12, MRMSrcMem,
714 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
715 "movlps\t{$src2, $dst|$dst, $src2}",
717 (v4f32 (vector_shuffle VR128:$src1,
718 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
719 MOVLP_shuffle_mask)))]>;
720 def MOVHPSrm : PSI<0x16, MRMSrcMem,
721 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
722 "movhps\t{$src2, $dst|$dst, $src2}",
724 (v4f32 (vector_shuffle VR128:$src1,
725 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
726 MOVHP_shuffle_mask)))]>;
728 } // Constraints = "$src1 = $dst"
731 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
732 "movlps\t{$src, $dst|$dst, $src}",
733 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
734 (iPTR 0))), addr:$dst)]>;
736 // v2f64 extract element 1 is always custom lowered to unpack high to low
737 // and extract element 0 so the non-store version isn't too horrible.
738 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
739 "movhps\t{$src, $dst|$dst, $src}",
740 [(store (f64 (vector_extract
741 (v2f64 (vector_shuffle
742 (bc_v2f64 (v4f32 VR128:$src)), (undef),
743 UNPCKH_shuffle_mask)), (iPTR 0))),
746 let Constraints = "$src1 = $dst" in {
747 let AddedComplexity = 15 in {
748 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
749 "movlhps\t{$src2, $dst|$dst, $src2}",
751 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
752 MOVHP_shuffle_mask)))]>;
754 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
755 "movhlps\t{$src2, $dst|$dst, $src2}",
757 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
758 MOVHLPS_shuffle_mask)))]>;
760 } // Constraints = "$src1 = $dst"
762 let AddedComplexity = 15 in
763 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef), MOVDDUP_shuffle_mask)),
764 (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
771 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
773 /// In addition, we also have a special variant of the scalar form here to
774 /// represent the associated intrinsic operation. This form is unlike the
775 /// plain scalar form, in that it takes an entire vector (instead of a
776 /// scalar) and leaves the top elements undefined.
778 /// And, we have a special variant form for a full-vector intrinsic form.
780 /// These four forms can each have a reg or a mem operand, so there are a
781 /// total of eight "instructions".
783 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
787 bit Commutable = 0> {
788 // Scalar operation, reg.
789 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
790 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
791 [(set FR32:$dst, (OpNode FR32:$src))]> {
792 let isCommutable = Commutable;
795 // Scalar operation, mem.
796 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
797 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
798 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
800 // Vector operation, reg.
801 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
802 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
803 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
804 let isCommutable = Commutable;
807 // Vector operation, mem.
808 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
809 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
810 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
812 // Intrinsic operation, reg.
813 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
814 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
815 [(set VR128:$dst, (F32Int VR128:$src))]> {
816 let isCommutable = Commutable;
819 // Intrinsic operation, mem.
820 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
821 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
822 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
824 // Vector intrinsic operation, reg
825 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
826 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
827 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
828 let isCommutable = Commutable;
831 // Vector intrinsic operation, mem
832 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
833 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
834 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
838 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
839 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
841 // Reciprocal approximations. Note that these typically require refinement
842 // in order to obtain suitable precision.
843 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
844 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
845 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
846 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
849 let Constraints = "$src1 = $dst" in {
850 let isCommutable = 1 in {
851 def ANDPSrr : PSI<0x54, MRMSrcReg,
852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
853 "andps\t{$src2, $dst|$dst, $src2}",
854 [(set VR128:$dst, (v2i64
855 (and VR128:$src1, VR128:$src2)))]>;
856 def ORPSrr : PSI<0x56, MRMSrcReg,
857 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
858 "orps\t{$src2, $dst|$dst, $src2}",
859 [(set VR128:$dst, (v2i64
860 (or VR128:$src1, VR128:$src2)))]>;
861 def XORPSrr : PSI<0x57, MRMSrcReg,
862 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
863 "xorps\t{$src2, $dst|$dst, $src2}",
864 [(set VR128:$dst, (v2i64
865 (xor VR128:$src1, VR128:$src2)))]>;
868 def ANDPSrm : PSI<0x54, MRMSrcMem,
869 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
870 "andps\t{$src2, $dst|$dst, $src2}",
871 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
872 (memopv2i64 addr:$src2)))]>;
873 def ORPSrm : PSI<0x56, MRMSrcMem,
874 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
875 "orps\t{$src2, $dst|$dst, $src2}",
876 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
877 (memopv2i64 addr:$src2)))]>;
878 def XORPSrm : PSI<0x57, MRMSrcMem,
879 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
880 "xorps\t{$src2, $dst|$dst, $src2}",
881 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
882 (memopv2i64 addr:$src2)))]>;
883 def ANDNPSrr : PSI<0x55, MRMSrcReg,
884 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
885 "andnps\t{$src2, $dst|$dst, $src2}",
887 (v2i64 (and (xor VR128:$src1,
888 (bc_v2i64 (v4i32 immAllOnesV))),
890 def ANDNPSrm : PSI<0x55, MRMSrcMem,
891 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
892 "andnps\t{$src2, $dst|$dst, $src2}",
894 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
895 (bc_v2i64 (v4i32 immAllOnesV))),
896 (memopv2i64 addr:$src2))))]>;
899 let Constraints = "$src1 = $dst" in {
900 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
901 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
902 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
903 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
904 VR128:$src, imm:$cc))]>;
905 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
906 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
907 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
908 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
909 (memop addr:$src), imm:$cc))]>;
911 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
912 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
913 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
914 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
916 // Shuffle and unpack instructions
917 let Constraints = "$src1 = $dst" in {
918 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
919 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
920 (outs VR128:$dst), (ins VR128:$src1,
921 VR128:$src2, i32i8imm:$src3),
922 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
924 (v4f32 (vector_shuffle
925 VR128:$src1, VR128:$src2,
926 SHUFP_shuffle_mask:$src3)))]>;
927 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
928 (outs VR128:$dst), (ins VR128:$src1,
929 f128mem:$src2, i32i8imm:$src3),
930 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
932 (v4f32 (vector_shuffle
933 VR128:$src1, (memopv4f32 addr:$src2),
934 SHUFP_shuffle_mask:$src3)))]>;
936 let AddedComplexity = 10 in {
937 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
938 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
939 "unpckhps\t{$src2, $dst|$dst, $src2}",
941 (v4f32 (vector_shuffle
942 VR128:$src1, VR128:$src2,
943 UNPCKH_shuffle_mask)))]>;
944 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
945 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
946 "unpckhps\t{$src2, $dst|$dst, $src2}",
948 (v4f32 (vector_shuffle
949 VR128:$src1, (memopv4f32 addr:$src2),
950 UNPCKH_shuffle_mask)))]>;
952 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
953 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
954 "unpcklps\t{$src2, $dst|$dst, $src2}",
956 (v4f32 (vector_shuffle
957 VR128:$src1, VR128:$src2,
958 UNPCKL_shuffle_mask)))]>;
959 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
960 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
961 "unpcklps\t{$src2, $dst|$dst, $src2}",
963 (v4f32 (vector_shuffle
964 VR128:$src1, (memopv4f32 addr:$src2),
965 UNPCKL_shuffle_mask)))]>;
967 } // Constraints = "$src1 = $dst"
970 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
971 "movmskps\t{$src, $dst|$dst, $src}",
972 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
973 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
974 "movmskpd\t{$src, $dst|$dst, $src}",
975 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
977 // Prefetch intrinsic.
978 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
979 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
980 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
981 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
982 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
983 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
984 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
985 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
987 // Non-temporal stores
988 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
989 "movntps\t{$src, $dst|$dst, $src}",
990 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
992 // Load, store, and memory fence
993 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
996 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
997 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
998 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
999 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1001 // Alias instructions that map zero vector to pxor / xorp* for sse.
1002 let isReMaterializable = 1 in
1003 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
1004 "xorps\t$dst, $dst",
1005 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1007 let Predicates = [HasSSE1] in {
1008 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
1009 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
1010 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
1011 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
1012 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
1015 // FR32 to 128-bit vector conversion.
1016 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1017 "movss\t{$src, $dst|$dst, $src}",
1019 (v4f32 (scalar_to_vector FR32:$src)))]>;
1020 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1021 "movss\t{$src, $dst|$dst, $src}",
1023 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1025 // FIXME: may not be able to eliminate this movss with coalescing the src and
1026 // dest register classes are different. We really want to write this pattern
1028 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1029 // (f32 FR32:$src)>;
1030 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1031 "movss\t{$src, $dst|$dst, $src}",
1032 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1034 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1035 "movss\t{$src, $dst|$dst, $src}",
1036 [(store (f32 (vector_extract (v4f32 VR128:$src),
1037 (iPTR 0))), addr:$dst)]>;
1040 // Move to lower bits of a VR128, leaving upper bits alone.
1041 // Three operand (but two address) aliases.
1042 let Constraints = "$src1 = $dst" in {
1043 let neverHasSideEffects = 1 in
1044 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1045 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1046 "movss\t{$src2, $dst|$dst, $src2}", []>;
1048 let AddedComplexity = 15 in
1049 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1050 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1051 "movss\t{$src2, $dst|$dst, $src2}",
1053 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1054 MOVL_shuffle_mask)))]>;
1057 // Move to lower bits of a VR128 and zeroing upper bits.
1058 // Loading from memory automatically zeroing upper bits.
1059 let AddedComplexity = 20 in
1060 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1061 "movss\t{$src, $dst|$dst, $src}",
1062 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1063 (loadf32 addr:$src))))))]>;
1065 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1066 (MOVZSS2PSrm addr:$src)>;
1068 //===----------------------------------------------------------------------===//
1069 // SSE2 Instructions
1070 //===----------------------------------------------------------------------===//
1072 // Move Instructions
1073 let neverHasSideEffects = 1 in
1074 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1075 "movsd\t{$src, $dst|$dst, $src}", []>;
1076 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1077 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1078 "movsd\t{$src, $dst|$dst, $src}",
1079 [(set FR64:$dst, (loadf64 addr:$src))]>;
1080 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1081 "movsd\t{$src, $dst|$dst, $src}",
1082 [(store FR64:$src, addr:$dst)]>;
1084 // Conversion instructions
1085 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1086 "cvttsd2si\t{$src, $dst|$dst, $src}",
1087 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1088 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1089 "cvttsd2si\t{$src, $dst|$dst, $src}",
1090 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1091 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1092 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1093 [(set FR32:$dst, (fround FR64:$src))]>;
1094 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1095 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1096 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1097 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1098 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1099 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1100 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1101 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1102 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1104 // SSE2 instructions with XS prefix
1105 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1106 "cvtss2sd\t{$src, $dst|$dst, $src}",
1107 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1108 Requires<[HasSSE2]>;
1109 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1110 "cvtss2sd\t{$src, $dst|$dst, $src}",
1111 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1112 Requires<[HasSSE2]>;
1114 // Match intrinsics which expect XMM operand(s).
1115 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1116 "cvtsd2si\t{$src, $dst|$dst, $src}",
1117 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1118 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1119 "cvtsd2si\t{$src, $dst|$dst, $src}",
1120 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1121 (load addr:$src)))]>;
1123 // Match intrinisics which expect MM and XMM operand(s).
1124 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1125 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1126 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1127 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1128 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1129 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1130 (memop addr:$src)))]>;
1131 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1132 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1133 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1134 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1135 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1136 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1137 (memop addr:$src)))]>;
1138 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1139 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1140 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1141 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1142 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1143 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1144 (load addr:$src)))]>;
1146 // Aliases for intrinsics
1147 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1148 "cvttsd2si\t{$src, $dst|$dst, $src}",
1150 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1151 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1152 "cvttsd2si\t{$src, $dst|$dst, $src}",
1153 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1154 (load addr:$src)))]>;
1156 // Comparison instructions
1157 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1158 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1159 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1160 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1162 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1163 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1164 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1167 let Defs = [EFLAGS] in {
1168 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1169 "ucomisd\t{$src2, $src1|$src1, $src2}",
1170 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1171 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1172 "ucomisd\t{$src2, $src1|$src1, $src2}",
1173 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1174 (implicit EFLAGS)]>;
1177 // Aliases to match intrinsics which expect XMM operand(s).
1178 let Constraints = "$src1 = $dst" in {
1179 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1180 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1181 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1182 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1183 VR128:$src, imm:$cc))]>;
1184 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1185 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1186 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1187 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1188 (load addr:$src), imm:$cc))]>;
1191 let Defs = [EFLAGS] in {
1192 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1193 "ucomisd\t{$src2, $src1|$src1, $src2}",
1194 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1195 (implicit EFLAGS)]>;
1196 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1197 "ucomisd\t{$src2, $src1|$src1, $src2}",
1198 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1199 (implicit EFLAGS)]>;
1201 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1202 "comisd\t{$src2, $src1|$src1, $src2}",
1203 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1204 (implicit EFLAGS)]>;
1205 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1206 "comisd\t{$src2, $src1|$src1, $src2}",
1207 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1208 (implicit EFLAGS)]>;
1211 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1214 // Alias instructions that map fld0 to pxor for sse.
1215 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1216 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1217 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1218 Requires<[HasSSE2]>, TB, OpSize;
1220 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1222 let neverHasSideEffects = 1 in
1223 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1224 "movapd\t{$src, $dst|$dst, $src}", []>;
1226 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1228 let isSimpleLoad = 1 in
1229 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1230 "movapd\t{$src, $dst|$dst, $src}",
1231 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1233 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1234 let Constraints = "$src1 = $dst" in {
1235 let isCommutable = 1 in {
1236 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1237 (ins FR64:$src1, FR64:$src2),
1238 "andpd\t{$src2, $dst|$dst, $src2}",
1239 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1240 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1241 (ins FR64:$src1, FR64:$src2),
1242 "orpd\t{$src2, $dst|$dst, $src2}",
1243 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1244 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1245 (ins FR64:$src1, FR64:$src2),
1246 "xorpd\t{$src2, $dst|$dst, $src2}",
1247 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1250 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1251 (ins FR64:$src1, f128mem:$src2),
1252 "andpd\t{$src2, $dst|$dst, $src2}",
1253 [(set FR64:$dst, (X86fand FR64:$src1,
1254 (memopfsf64 addr:$src2)))]>;
1255 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1256 (ins FR64:$src1, f128mem:$src2),
1257 "orpd\t{$src2, $dst|$dst, $src2}",
1258 [(set FR64:$dst, (X86for FR64:$src1,
1259 (memopfsf64 addr:$src2)))]>;
1260 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1261 (ins FR64:$src1, f128mem:$src2),
1262 "xorpd\t{$src2, $dst|$dst, $src2}",
1263 [(set FR64:$dst, (X86fxor FR64:$src1,
1264 (memopfsf64 addr:$src2)))]>;
1266 let neverHasSideEffects = 1 in {
1267 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1268 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1269 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1271 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1272 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1273 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1277 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1279 /// In addition, we also have a special variant of the scalar form here to
1280 /// represent the associated intrinsic operation. This form is unlike the
1281 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1282 /// and leaves the top elements undefined.
1284 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1285 /// six "instructions".
1287 let Constraints = "$src1 = $dst" in {
1288 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1289 SDNode OpNode, Intrinsic F64Int,
1290 bit Commutable = 0> {
1291 // Scalar operation, reg+reg.
1292 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1293 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1294 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1295 let isCommutable = Commutable;
1298 // Scalar operation, reg+mem.
1299 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1300 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1301 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1303 // Vector operation, reg+reg.
1304 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1305 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1306 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1307 let isCommutable = Commutable;
1310 // Vector operation, reg+mem.
1311 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1312 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1313 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1315 // Intrinsic operation, reg+reg.
1316 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1317 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1318 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1319 let isCommutable = Commutable;
1322 // Intrinsic operation, reg+mem.
1323 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1324 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1325 [(set VR128:$dst, (F64Int VR128:$src1,
1326 sse_load_f64:$src2))]>;
1330 // Arithmetic instructions
1331 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1332 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1333 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1334 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1336 /// sse2_fp_binop_rm - Other SSE2 binops
1338 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1339 /// instructions for a full-vector intrinsic form. Operations that map
1340 /// onto C operators don't use this form since they just use the plain
1341 /// vector form instead of having a separate vector intrinsic form.
1343 /// This provides a total of eight "instructions".
1345 let Constraints = "$src1 = $dst" in {
1346 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1350 bit Commutable = 0> {
1352 // Scalar operation, reg+reg.
1353 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1354 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1355 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1356 let isCommutable = Commutable;
1359 // Scalar operation, reg+mem.
1360 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1361 (ins FR64:$src1, f64mem:$src2),
1362 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1363 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1365 // Vector operation, reg+reg.
1366 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1367 (ins VR128:$src1, VR128:$src2),
1368 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1369 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1370 let isCommutable = Commutable;
1373 // Vector operation, reg+mem.
1374 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1375 (ins VR128:$src1, f128mem:$src2),
1376 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1377 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1379 // Intrinsic operation, reg+reg.
1380 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1381 (ins VR128:$src1, VR128:$src2),
1382 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1383 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1384 let isCommutable = Commutable;
1387 // Intrinsic operation, reg+mem.
1388 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1389 (ins VR128:$src1, sdmem:$src2),
1390 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1391 [(set VR128:$dst, (F64Int VR128:$src1,
1392 sse_load_f64:$src2))]>;
1394 // Vector intrinsic operation, reg+reg.
1395 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1396 (ins VR128:$src1, VR128:$src2),
1397 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1398 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1399 let isCommutable = Commutable;
1402 // Vector intrinsic operation, reg+mem.
1403 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1404 (ins VR128:$src1, f128mem:$src2),
1405 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1406 [(set VR128:$dst, (V2F64Int VR128:$src1,
1407 (memopv2f64 addr:$src2)))]>;
1411 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1412 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1413 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1414 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1416 //===----------------------------------------------------------------------===//
1417 // SSE packed FP Instructions
1419 // Move Instructions
1420 let neverHasSideEffects = 1 in
1421 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1422 "movapd\t{$src, $dst|$dst, $src}", []>;
1423 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1424 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1425 "movapd\t{$src, $dst|$dst, $src}",
1426 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1428 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1429 "movapd\t{$src, $dst|$dst, $src}",
1430 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1432 let neverHasSideEffects = 1 in
1433 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1434 "movupd\t{$src, $dst|$dst, $src}", []>;
1435 let isSimpleLoad = 1 in
1436 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1437 "movupd\t{$src, $dst|$dst, $src}",
1438 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1439 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1440 "movupd\t{$src, $dst|$dst, $src}",
1441 [(store (v2f64 VR128:$src), addr:$dst)]>;
1443 // Intrinsic forms of MOVUPD load and store
1444 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1445 "movupd\t{$src, $dst|$dst, $src}",
1446 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1447 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1448 "movupd\t{$src, $dst|$dst, $src}",
1449 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1451 let Constraints = "$src1 = $dst" in {
1452 let AddedComplexity = 20 in {
1453 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1454 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1455 "movlpd\t{$src2, $dst|$dst, $src2}",
1457 (v2f64 (vector_shuffle VR128:$src1,
1458 (scalar_to_vector (loadf64 addr:$src2)),
1459 MOVLP_shuffle_mask)))]>;
1460 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1461 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1462 "movhpd\t{$src2, $dst|$dst, $src2}",
1464 (v2f64 (vector_shuffle VR128:$src1,
1465 (scalar_to_vector (loadf64 addr:$src2)),
1466 MOVHP_shuffle_mask)))]>;
1467 } // AddedComplexity
1468 } // Constraints = "$src1 = $dst"
1470 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1471 "movlpd\t{$src, $dst|$dst, $src}",
1472 [(store (f64 (vector_extract (v2f64 VR128:$src),
1473 (iPTR 0))), addr:$dst)]>;
1475 // v2f64 extract element 1 is always custom lowered to unpack high to low
1476 // and extract element 0 so the non-store version isn't too horrible.
1477 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1478 "movhpd\t{$src, $dst|$dst, $src}",
1479 [(store (f64 (vector_extract
1480 (v2f64 (vector_shuffle VR128:$src, (undef),
1481 UNPCKH_shuffle_mask)), (iPTR 0))),
1484 // SSE2 instructions without OpSize prefix
1485 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1486 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1487 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1488 TB, Requires<[HasSSE2]>;
1489 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1490 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1491 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1492 (bitconvert (memopv2i64 addr:$src))))]>,
1493 TB, Requires<[HasSSE2]>;
1495 // SSE2 instructions with XS prefix
1496 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1497 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1498 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1499 XS, Requires<[HasSSE2]>;
1500 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1501 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1502 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1503 (bitconvert (memopv2i64 addr:$src))))]>,
1504 XS, Requires<[HasSSE2]>;
1506 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1507 "cvtps2dq\t{$src, $dst|$dst, $src}",
1508 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1509 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1510 "cvtps2dq\t{$src, $dst|$dst, $src}",
1511 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1512 (memop addr:$src)))]>;
1513 // SSE2 packed instructions with XS prefix
1514 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1515 "cvttps2dq\t{$src, $dst|$dst, $src}",
1516 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1517 XS, Requires<[HasSSE2]>;
1518 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1519 "cvttps2dq\t{$src, $dst|$dst, $src}",
1520 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1521 (memop addr:$src)))]>,
1522 XS, Requires<[HasSSE2]>;
1524 // SSE2 packed instructions with XD prefix
1525 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1526 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1527 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1528 XD, Requires<[HasSSE2]>;
1529 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1530 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1531 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1532 (memop addr:$src)))]>,
1533 XD, Requires<[HasSSE2]>;
1535 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1536 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1537 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1538 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1539 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1540 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1541 (memop addr:$src)))]>;
1543 // SSE2 instructions without OpSize prefix
1544 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1545 "cvtps2pd\t{$src, $dst|$dst, $src}",
1546 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1547 TB, Requires<[HasSSE2]>;
1548 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1549 "cvtps2pd\t{$src, $dst|$dst, $src}",
1550 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1551 (load addr:$src)))]>,
1552 TB, Requires<[HasSSE2]>;
1554 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1555 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1556 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1557 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1558 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1559 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1560 (memop addr:$src)))]>;
1562 // Match intrinsics which expect XMM operand(s).
1563 // Aliases for intrinsics
1564 let Constraints = "$src1 = $dst" in {
1565 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1566 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1567 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1568 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1570 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1571 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1572 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1573 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1574 (loadi32 addr:$src2)))]>;
1575 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1576 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1577 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1578 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1580 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1581 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1582 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1583 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1584 (load addr:$src2)))]>;
1585 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1586 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1587 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1588 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1589 VR128:$src2))]>, XS,
1590 Requires<[HasSSE2]>;
1591 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1592 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1593 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1594 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1595 (load addr:$src2)))]>, XS,
1596 Requires<[HasSSE2]>;
1601 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1603 /// In addition, we also have a special variant of the scalar form here to
1604 /// represent the associated intrinsic operation. This form is unlike the
1605 /// plain scalar form, in that it takes an entire vector (instead of a
1606 /// scalar) and leaves the top elements undefined.
1608 /// And, we have a special variant form for a full-vector intrinsic form.
1610 /// These four forms can each have a reg or a mem operand, so there are a
1611 /// total of eight "instructions".
1613 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1617 bit Commutable = 0> {
1618 // Scalar operation, reg.
1619 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1620 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1621 [(set FR64:$dst, (OpNode FR64:$src))]> {
1622 let isCommutable = Commutable;
1625 // Scalar operation, mem.
1626 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1627 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1628 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1630 // Vector operation, reg.
1631 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1632 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1633 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1634 let isCommutable = Commutable;
1637 // Vector operation, mem.
1638 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1639 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1640 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1642 // Intrinsic operation, reg.
1643 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1644 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1645 [(set VR128:$dst, (F64Int VR128:$src))]> {
1646 let isCommutable = Commutable;
1649 // Intrinsic operation, mem.
1650 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1651 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1652 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1654 // Vector intrinsic operation, reg
1655 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1656 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1657 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1658 let isCommutable = Commutable;
1661 // Vector intrinsic operation, mem
1662 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1663 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1664 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1668 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1669 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1671 // There is no f64 version of the reciprocal approximation instructions.
1674 let Constraints = "$src1 = $dst" in {
1675 let isCommutable = 1 in {
1676 def ANDPDrr : PDI<0x54, MRMSrcReg,
1677 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1678 "andpd\t{$src2, $dst|$dst, $src2}",
1680 (and (bc_v2i64 (v2f64 VR128:$src1)),
1681 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1682 def ORPDrr : PDI<0x56, MRMSrcReg,
1683 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1684 "orpd\t{$src2, $dst|$dst, $src2}",
1686 (or (bc_v2i64 (v2f64 VR128:$src1)),
1687 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1688 def XORPDrr : PDI<0x57, MRMSrcReg,
1689 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1690 "xorpd\t{$src2, $dst|$dst, $src2}",
1692 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1693 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1696 def ANDPDrm : PDI<0x54, MRMSrcMem,
1697 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1698 "andpd\t{$src2, $dst|$dst, $src2}",
1700 (and (bc_v2i64 (v2f64 VR128:$src1)),
1701 (memopv2i64 addr:$src2)))]>;
1702 def ORPDrm : PDI<0x56, MRMSrcMem,
1703 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1704 "orpd\t{$src2, $dst|$dst, $src2}",
1706 (or (bc_v2i64 (v2f64 VR128:$src1)),
1707 (memopv2i64 addr:$src2)))]>;
1708 def XORPDrm : PDI<0x57, MRMSrcMem,
1709 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1710 "xorpd\t{$src2, $dst|$dst, $src2}",
1712 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1713 (memopv2i64 addr:$src2)))]>;
1714 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1715 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1716 "andnpd\t{$src2, $dst|$dst, $src2}",
1718 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1719 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1720 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1721 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1722 "andnpd\t{$src2, $dst|$dst, $src2}",
1724 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1725 (memopv2i64 addr:$src2)))]>;
1728 let Constraints = "$src1 = $dst" in {
1729 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1730 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1731 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1732 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1733 VR128:$src, imm:$cc))]>;
1734 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1735 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1736 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1737 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1738 (memop addr:$src), imm:$cc))]>;
1740 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1741 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1742 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1743 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1745 // Shuffle and unpack instructions
1746 let Constraints = "$src1 = $dst" in {
1747 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1749 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1750 [(set VR128:$dst, (v2f64 (vector_shuffle
1751 VR128:$src1, VR128:$src2,
1752 SHUFP_shuffle_mask:$src3)))]>;
1753 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1754 (outs VR128:$dst), (ins VR128:$src1,
1755 f128mem:$src2, i8imm:$src3),
1756 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1758 (v2f64 (vector_shuffle
1759 VR128:$src1, (memopv2f64 addr:$src2),
1760 SHUFP_shuffle_mask:$src3)))]>;
1762 let AddedComplexity = 10 in {
1763 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1764 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1765 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1767 (v2f64 (vector_shuffle
1768 VR128:$src1, VR128:$src2,
1769 UNPCKH_shuffle_mask)))]>;
1770 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1771 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1772 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1774 (v2f64 (vector_shuffle
1775 VR128:$src1, (memopv2f64 addr:$src2),
1776 UNPCKH_shuffle_mask)))]>;
1778 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1779 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1780 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1782 (v2f64 (vector_shuffle
1783 VR128:$src1, VR128:$src2,
1784 UNPCKL_shuffle_mask)))]>;
1785 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1786 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1787 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1789 (v2f64 (vector_shuffle
1790 VR128:$src1, (memopv2f64 addr:$src2),
1791 UNPCKL_shuffle_mask)))]>;
1792 } // AddedComplexity
1793 } // Constraints = "$src1 = $dst"
1796 //===----------------------------------------------------------------------===//
1797 // SSE integer instructions
1799 // Move Instructions
1800 let neverHasSideEffects = 1 in
1801 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1802 "movdqa\t{$src, $dst|$dst, $src}", []>;
1803 let isSimpleLoad = 1, mayLoad = 1 in
1804 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1805 "movdqa\t{$src, $dst|$dst, $src}",
1806 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1808 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1809 "movdqa\t{$src, $dst|$dst, $src}",
1810 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1811 let isSimpleLoad = 1, mayLoad = 1 in
1812 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1813 "movdqu\t{$src, $dst|$dst, $src}",
1814 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1815 XS, Requires<[HasSSE2]>;
1817 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1818 "movdqu\t{$src, $dst|$dst, $src}",
1819 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1820 XS, Requires<[HasSSE2]>;
1822 // Intrinsic forms of MOVDQU load and store
1823 let isSimpleLoad = 1 in
1824 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1825 "movdqu\t{$src, $dst|$dst, $src}",
1826 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1827 XS, Requires<[HasSSE2]>;
1828 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1829 "movdqu\t{$src, $dst|$dst, $src}",
1830 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1831 XS, Requires<[HasSSE2]>;
1833 let Constraints = "$src1 = $dst" in {
1835 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1836 bit Commutable = 0> {
1837 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1838 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1839 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1840 let isCommutable = Commutable;
1842 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1844 [(set VR128:$dst, (IntId VR128:$src1,
1845 (bitconvert (memopv2i64 addr:$src2))))]>;
1848 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1850 Intrinsic IntId, Intrinsic IntId2> {
1851 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1853 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1854 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1856 [(set VR128:$dst, (IntId VR128:$src1,
1857 (bitconvert (memopv2i64 addr:$src2))))]>;
1858 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1859 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1860 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1863 /// PDI_binop_rm - Simple SSE2 binary operator.
1864 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1865 ValueType OpVT, bit Commutable = 0> {
1866 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1868 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1869 let isCommutable = Commutable;
1871 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1872 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1873 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1874 (bitconvert (memopv2i64 addr:$src2)))))]>;
1877 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1879 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1880 /// to collapse (bitconvert VT to VT) into its operand.
1882 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1883 bit Commutable = 0> {
1884 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1885 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1886 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1887 let isCommutable = Commutable;
1889 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1890 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1891 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1894 } // Constraints = "$src1 = $dst"
1896 // 128-bit Integer Arithmetic
1898 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1899 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1900 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1901 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1903 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1904 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1905 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1906 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1908 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1909 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1910 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1911 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1913 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1914 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1915 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1916 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1918 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1920 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1921 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1922 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1924 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1926 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1927 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1930 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1931 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1932 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1933 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1934 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1937 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1938 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1939 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1940 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1941 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1942 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1944 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1945 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1946 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1947 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1948 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1949 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1951 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1952 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1953 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1954 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1956 // 128-bit logical shifts.
1957 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1958 def PSLLDQri : PDIi8<0x73, MRM7r,
1959 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1960 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1961 def PSRLDQri : PDIi8<0x73, MRM3r,
1962 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1963 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1964 // PSRADQri doesn't exist in SSE[1-3].
1967 let Predicates = [HasSSE2] in {
1968 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1969 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1970 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1971 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1972 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1973 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1975 // Shift up / down and insert zero's.
1976 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1977 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1978 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1979 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1983 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1984 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1985 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1987 let Constraints = "$src1 = $dst" in {
1988 def PANDNrr : PDI<0xDF, MRMSrcReg,
1989 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1990 "pandn\t{$src2, $dst|$dst, $src2}",
1991 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1994 def PANDNrm : PDI<0xDF, MRMSrcMem,
1995 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1996 "pandn\t{$src2, $dst|$dst, $src2}",
1997 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1998 (memopv2i64 addr:$src2))))]>;
2001 // SSE2 Integer comparison
2002 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2003 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2004 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2005 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2006 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2007 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2009 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2010 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2011 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2012 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2013 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2014 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2015 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2016 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2017 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2018 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2019 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2020 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2022 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2023 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2024 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2025 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2026 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2027 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2028 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2029 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2030 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2031 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2032 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2033 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2036 // Pack instructions
2037 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2038 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2039 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2041 // Shuffle and unpack instructions
2042 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2043 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2044 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2045 [(set VR128:$dst, (v4i32 (vector_shuffle
2046 VR128:$src1, (undef),
2047 PSHUFD_shuffle_mask:$src2)))]>;
2048 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2049 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2050 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2051 [(set VR128:$dst, (v4i32 (vector_shuffle
2052 (bc_v4i32(memopv2i64 addr:$src1)),
2054 PSHUFD_shuffle_mask:$src2)))]>;
2056 // SSE2 with ImmT == Imm8 and XS prefix.
2057 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2058 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2059 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2060 [(set VR128:$dst, (v8i16 (vector_shuffle
2061 VR128:$src1, (undef),
2062 PSHUFHW_shuffle_mask:$src2)))]>,
2063 XS, Requires<[HasSSE2]>;
2064 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2065 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2066 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2067 [(set VR128:$dst, (v8i16 (vector_shuffle
2068 (bc_v8i16 (memopv2i64 addr:$src1)),
2070 PSHUFHW_shuffle_mask:$src2)))]>,
2071 XS, Requires<[HasSSE2]>;
2073 // SSE2 with ImmT == Imm8 and XD prefix.
2074 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2075 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2076 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2077 [(set VR128:$dst, (v8i16 (vector_shuffle
2078 VR128:$src1, (undef),
2079 PSHUFLW_shuffle_mask:$src2)))]>,
2080 XD, Requires<[HasSSE2]>;
2081 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2082 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2083 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2084 [(set VR128:$dst, (v8i16 (vector_shuffle
2085 (bc_v8i16 (memopv2i64 addr:$src1)),
2087 PSHUFLW_shuffle_mask:$src2)))]>,
2088 XD, Requires<[HasSSE2]>;
2091 let Constraints = "$src1 = $dst" in {
2092 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2093 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2094 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2096 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2097 UNPCKL_shuffle_mask)))]>;
2098 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2099 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2100 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2102 (v16i8 (vector_shuffle VR128:$src1,
2103 (bc_v16i8 (memopv2i64 addr:$src2)),
2104 UNPCKL_shuffle_mask)))]>;
2105 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2106 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2107 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2109 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2110 UNPCKL_shuffle_mask)))]>;
2111 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2112 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2113 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2115 (v8i16 (vector_shuffle VR128:$src1,
2116 (bc_v8i16 (memopv2i64 addr:$src2)),
2117 UNPCKL_shuffle_mask)))]>;
2118 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2119 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2120 "punpckldq\t{$src2, $dst|$dst, $src2}",
2122 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2123 UNPCKL_shuffle_mask)))]>;
2124 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2125 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2126 "punpckldq\t{$src2, $dst|$dst, $src2}",
2128 (v4i32 (vector_shuffle VR128:$src1,
2129 (bc_v4i32 (memopv2i64 addr:$src2)),
2130 UNPCKL_shuffle_mask)))]>;
2131 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2132 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2133 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2135 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2136 UNPCKL_shuffle_mask)))]>;
2137 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2138 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2139 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2141 (v2i64 (vector_shuffle VR128:$src1,
2142 (memopv2i64 addr:$src2),
2143 UNPCKL_shuffle_mask)))]>;
2145 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2146 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2147 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2149 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2150 UNPCKH_shuffle_mask)))]>;
2151 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2152 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2153 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2155 (v16i8 (vector_shuffle VR128:$src1,
2156 (bc_v16i8 (memopv2i64 addr:$src2)),
2157 UNPCKH_shuffle_mask)))]>;
2158 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2159 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2160 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2162 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2163 UNPCKH_shuffle_mask)))]>;
2164 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2165 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2166 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2168 (v8i16 (vector_shuffle VR128:$src1,
2169 (bc_v8i16 (memopv2i64 addr:$src2)),
2170 UNPCKH_shuffle_mask)))]>;
2171 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2172 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2173 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2175 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2176 UNPCKH_shuffle_mask)))]>;
2177 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2178 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2179 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2181 (v4i32 (vector_shuffle VR128:$src1,
2182 (bc_v4i32 (memopv2i64 addr:$src2)),
2183 UNPCKH_shuffle_mask)))]>;
2184 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2185 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2186 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2188 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2189 UNPCKH_shuffle_mask)))]>;
2190 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2191 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2192 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2194 (v2i64 (vector_shuffle VR128:$src1,
2195 (memopv2i64 addr:$src2),
2196 UNPCKH_shuffle_mask)))]>;
2200 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2201 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2202 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2203 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2205 let Constraints = "$src1 = $dst" in {
2206 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2207 (outs VR128:$dst), (ins VR128:$src1,
2208 GR32:$src2, i32i8imm:$src3),
2209 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2211 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2212 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2213 (outs VR128:$dst), (ins VR128:$src1,
2214 i16mem:$src2, i32i8imm:$src3),
2215 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2217 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2222 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2223 "pmovmskb\t{$src, $dst|$dst, $src}",
2224 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2226 // Conditional store
2228 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2229 "maskmovdqu\t{$mask, $src|$src, $mask}",
2230 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2232 // Non-temporal stores
2233 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2234 "movntpd\t{$src, $dst|$dst, $src}",
2235 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2236 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2237 "movntdq\t{$src, $dst|$dst, $src}",
2238 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2239 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2240 "movnti\t{$src, $dst|$dst, $src}",
2241 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2242 TB, Requires<[HasSSE2]>;
2245 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2246 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2247 TB, Requires<[HasSSE2]>;
2249 // Load, store, and memory fence
2250 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2251 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2252 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2253 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2255 //TODO: custom lower this so as to never even generate the noop
2256 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2258 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2259 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2260 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2263 // Alias instructions that map zero vector to pxor / xorp* for sse.
2264 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2265 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2266 "pcmpeqd\t$dst, $dst",
2267 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2269 // FR64 to 128-bit vector conversion.
2270 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2271 "movsd\t{$src, $dst|$dst, $src}",
2273 (v2f64 (scalar_to_vector FR64:$src)))]>;
2274 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2275 "movsd\t{$src, $dst|$dst, $src}",
2277 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2279 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2280 "movd\t{$src, $dst|$dst, $src}",
2282 (v4i32 (scalar_to_vector GR32:$src)))]>;
2283 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2284 "movd\t{$src, $dst|$dst, $src}",
2286 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2288 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2289 "movd\t{$src, $dst|$dst, $src}",
2290 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2292 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2293 "movd\t{$src, $dst|$dst, $src}",
2294 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2296 // SSE2 instructions with XS prefix
2297 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2298 "movq\t{$src, $dst|$dst, $src}",
2300 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2301 Requires<[HasSSE2]>;
2302 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2303 "movq\t{$src, $dst|$dst, $src}",
2304 [(store (i64 (vector_extract (v2i64 VR128:$src),
2305 (iPTR 0))), addr:$dst)]>;
2307 // FIXME: may not be able to eliminate this movss with coalescing the src and
2308 // dest register classes are different. We really want to write this pattern
2310 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2311 // (f32 FR32:$src)>;
2312 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2313 "movsd\t{$src, $dst|$dst, $src}",
2314 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2316 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2317 "movsd\t{$src, $dst|$dst, $src}",
2318 [(store (f64 (vector_extract (v2f64 VR128:$src),
2319 (iPTR 0))), addr:$dst)]>;
2320 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2321 "movd\t{$src, $dst|$dst, $src}",
2322 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2324 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2325 "movd\t{$src, $dst|$dst, $src}",
2326 [(store (i32 (vector_extract (v4i32 VR128:$src),
2327 (iPTR 0))), addr:$dst)]>;
2329 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2330 "movd\t{$src, $dst|$dst, $src}",
2331 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2332 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2333 "movd\t{$src, $dst|$dst, $src}",
2334 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2337 // Move to lower bits of a VR128, leaving upper bits alone.
2338 // Three operand (but two address) aliases.
2339 let Constraints = "$src1 = $dst" in {
2340 let neverHasSideEffects = 1 in
2341 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2342 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2343 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2345 let AddedComplexity = 15 in
2346 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2347 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2348 "movsd\t{$src2, $dst|$dst, $src2}",
2350 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2351 MOVL_shuffle_mask)))]>;
2354 // Store / copy lower 64-bits of a XMM register.
2355 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2356 "movq\t{$src, $dst|$dst, $src}",
2357 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2359 // Move to lower bits of a VR128 and zeroing upper bits.
2360 // Loading from memory automatically zeroing upper bits.
2361 let AddedComplexity = 20 in {
2362 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2363 "movsd\t{$src, $dst|$dst, $src}",
2365 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2366 (loadf64 addr:$src))))))]>;
2368 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2369 (MOVZSD2PDrm addr:$src)>;
2370 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2371 (MOVZSD2PDrm addr:$src)>;
2372 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2375 // movd / movq to XMM register zero-extends
2376 let AddedComplexity = 15 in {
2377 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2378 "movd\t{$src, $dst|$dst, $src}",
2379 [(set VR128:$dst, (v4i32 (X86vzmovl
2380 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2381 // This is X86-64 only.
2382 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2383 "mov{d|q}\t{$src, $dst|$dst, $src}",
2384 [(set VR128:$dst, (v2i64 (X86vzmovl
2385 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2388 let AddedComplexity = 20 in {
2389 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2390 "movd\t{$src, $dst|$dst, $src}",
2392 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2393 (loadi32 addr:$src))))))]>;
2395 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2396 (MOVZDI2PDIrm addr:$src)>;
2397 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2398 (MOVZDI2PDIrm addr:$src)>;
2399 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2400 (MOVZDI2PDIrm addr:$src)>;
2402 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2403 "movq\t{$src, $dst|$dst, $src}",
2405 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2406 (loadi64 addr:$src))))))]>, XS,
2407 Requires<[HasSSE2]>;
2409 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2410 (MOVZQI2PQIrm addr:$src)>;
2411 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2412 (MOVZQI2PQIrm addr:$src)>;
2413 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2416 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2417 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2418 let AddedComplexity = 15 in
2419 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2420 "movq\t{$src, $dst|$dst, $src}",
2421 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2422 XS, Requires<[HasSSE2]>;
2424 let AddedComplexity = 20 in {
2425 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2426 "movq\t{$src, $dst|$dst, $src}",
2427 [(set VR128:$dst, (v2i64 (X86vzmovl
2428 (loadv2i64 addr:$src))))]>,
2429 XS, Requires<[HasSSE2]>;
2431 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2432 (MOVZPQILo2PQIrm addr:$src)>;
2435 //===----------------------------------------------------------------------===//
2436 // SSE3 Instructions
2437 //===----------------------------------------------------------------------===//
2439 // Move Instructions
2440 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2441 "movshdup\t{$src, $dst|$dst, $src}",
2442 [(set VR128:$dst, (v4f32 (vector_shuffle
2443 VR128:$src, (undef),
2444 MOVSHDUP_shuffle_mask)))]>;
2445 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2446 "movshdup\t{$src, $dst|$dst, $src}",
2447 [(set VR128:$dst, (v4f32 (vector_shuffle
2448 (memopv4f32 addr:$src), (undef),
2449 MOVSHDUP_shuffle_mask)))]>;
2451 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2452 "movsldup\t{$src, $dst|$dst, $src}",
2453 [(set VR128:$dst, (v4f32 (vector_shuffle
2454 VR128:$src, (undef),
2455 MOVSLDUP_shuffle_mask)))]>;
2456 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2457 "movsldup\t{$src, $dst|$dst, $src}",
2458 [(set VR128:$dst, (v4f32 (vector_shuffle
2459 (memopv4f32 addr:$src), (undef),
2460 MOVSLDUP_shuffle_mask)))]>;
2462 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2463 "movddup\t{$src, $dst|$dst, $src}",
2465 (v2f64 (vector_shuffle VR128:$src, (undef),
2466 MOVDDUP_shuffle_mask)))]>;
2467 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2468 "movddup\t{$src, $dst|$dst, $src}",
2470 (v2f64 (vector_shuffle
2471 (scalar_to_vector (loadf64 addr:$src)),
2472 (undef), MOVDDUP_shuffle_mask)))]>;
2474 def : Pat<(vector_shuffle
2475 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2476 (undef), MOVDDUP_shuffle_mask),
2477 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2478 def : Pat<(vector_shuffle
2479 (memopv2f64 addr:$src), (undef), MOVDDUP_shuffle_mask),
2480 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2484 let Constraints = "$src1 = $dst" in {
2485 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2486 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2487 "addsubps\t{$src2, $dst|$dst, $src2}",
2488 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2490 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2491 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2492 "addsubps\t{$src2, $dst|$dst, $src2}",
2493 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2494 (memop addr:$src2)))]>;
2495 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2496 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2497 "addsubpd\t{$src2, $dst|$dst, $src2}",
2498 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2500 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2501 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2502 "addsubpd\t{$src2, $dst|$dst, $src2}",
2503 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2504 (memop addr:$src2)))]>;
2507 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2508 "lddqu\t{$src, $dst|$dst, $src}",
2509 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2512 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2513 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2514 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2515 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2516 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2517 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2519 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2520 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2521 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2522 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2523 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2524 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2525 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2526 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2527 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2529 let Constraints = "$src1 = $dst" in {
2530 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2531 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2532 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2533 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2534 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2535 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2536 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2537 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2540 // Thread synchronization
2541 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2542 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2543 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2544 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2546 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2547 let AddedComplexity = 15 in
2548 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2549 MOVSHDUP_shuffle_mask)),
2550 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2551 let AddedComplexity = 20 in
2552 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2553 MOVSHDUP_shuffle_mask)),
2554 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2556 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2557 let AddedComplexity = 15 in
2558 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2559 MOVSLDUP_shuffle_mask)),
2560 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2561 let AddedComplexity = 20 in
2562 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2563 MOVSLDUP_shuffle_mask)),
2564 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2566 //===----------------------------------------------------------------------===//
2567 // SSSE3 Instructions
2568 //===----------------------------------------------------------------------===//
2570 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2571 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2572 Intrinsic IntId64, Intrinsic IntId128> {
2573 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2575 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2577 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2580 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2582 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2585 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2588 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2590 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2593 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2596 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2597 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2598 Intrinsic IntId64, Intrinsic IntId128> {
2599 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2601 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2602 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2604 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2606 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2609 (bitconvert (memopv4i16 addr:$src))))]>;
2611 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2613 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2614 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2617 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2622 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2625 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2626 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2627 Intrinsic IntId64, Intrinsic IntId128> {
2628 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2630 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2631 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2633 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2635 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2638 (bitconvert (memopv2i32 addr:$src))))]>;
2640 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2642 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2643 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2646 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2648 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2651 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2654 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2655 int_x86_ssse3_pabs_b,
2656 int_x86_ssse3_pabs_b_128>;
2657 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2658 int_x86_ssse3_pabs_w,
2659 int_x86_ssse3_pabs_w_128>;
2660 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2661 int_x86_ssse3_pabs_d,
2662 int_x86_ssse3_pabs_d_128>;
2664 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2665 let Constraints = "$src1 = $dst" in {
2666 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2667 Intrinsic IntId64, Intrinsic IntId128,
2668 bit Commutable = 0> {
2669 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2670 (ins VR64:$src1, VR64:$src2),
2671 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2672 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2673 let isCommutable = Commutable;
2675 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2676 (ins VR64:$src1, i64mem:$src2),
2677 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2679 (IntId64 VR64:$src1,
2680 (bitconvert (memopv8i8 addr:$src2))))]>;
2682 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2683 (ins VR128:$src1, VR128:$src2),
2684 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2685 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2687 let isCommutable = Commutable;
2689 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2690 (ins VR128:$src1, i128mem:$src2),
2691 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2693 (IntId128 VR128:$src1,
2694 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2698 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2699 let Constraints = "$src1 = $dst" in {
2700 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2701 Intrinsic IntId64, Intrinsic IntId128,
2702 bit Commutable = 0> {
2703 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2704 (ins VR64:$src1, VR64:$src2),
2705 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2706 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2707 let isCommutable = Commutable;
2709 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2710 (ins VR64:$src1, i64mem:$src2),
2711 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2713 (IntId64 VR64:$src1,
2714 (bitconvert (memopv4i16 addr:$src2))))]>;
2716 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2717 (ins VR128:$src1, VR128:$src2),
2718 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2719 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2721 let isCommutable = Commutable;
2723 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2724 (ins VR128:$src1, i128mem:$src2),
2725 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2727 (IntId128 VR128:$src1,
2728 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2732 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2733 let Constraints = "$src1 = $dst" in {
2734 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2735 Intrinsic IntId64, Intrinsic IntId128,
2736 bit Commutable = 0> {
2737 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2738 (ins VR64:$src1, VR64:$src2),
2739 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2740 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2741 let isCommutable = Commutable;
2743 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2744 (ins VR64:$src1, i64mem:$src2),
2745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2747 (IntId64 VR64:$src1,
2748 (bitconvert (memopv2i32 addr:$src2))))]>;
2750 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2751 (ins VR128:$src1, VR128:$src2),
2752 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2753 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2755 let isCommutable = Commutable;
2757 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2758 (ins VR128:$src1, i128mem:$src2),
2759 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2761 (IntId128 VR128:$src1,
2762 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2766 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2767 int_x86_ssse3_phadd_w,
2768 int_x86_ssse3_phadd_w_128>;
2769 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2770 int_x86_ssse3_phadd_d,
2771 int_x86_ssse3_phadd_d_128>;
2772 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2773 int_x86_ssse3_phadd_sw,
2774 int_x86_ssse3_phadd_sw_128>;
2775 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2776 int_x86_ssse3_phsub_w,
2777 int_x86_ssse3_phsub_w_128>;
2778 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2779 int_x86_ssse3_phsub_d,
2780 int_x86_ssse3_phsub_d_128>;
2781 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2782 int_x86_ssse3_phsub_sw,
2783 int_x86_ssse3_phsub_sw_128>;
2784 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2785 int_x86_ssse3_pmadd_ub_sw,
2786 int_x86_ssse3_pmadd_ub_sw_128>;
2787 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2788 int_x86_ssse3_pmul_hr_sw,
2789 int_x86_ssse3_pmul_hr_sw_128, 1>;
2790 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2791 int_x86_ssse3_pshuf_b,
2792 int_x86_ssse3_pshuf_b_128>;
2793 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2794 int_x86_ssse3_psign_b,
2795 int_x86_ssse3_psign_b_128>;
2796 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2797 int_x86_ssse3_psign_w,
2798 int_x86_ssse3_psign_w_128>;
2799 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2800 int_x86_ssse3_psign_d,
2801 int_x86_ssse3_psign_d_128>;
2803 let Constraints = "$src1 = $dst" in {
2804 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2805 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2806 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2808 (int_x86_ssse3_palign_r
2809 VR64:$src1, VR64:$src2,
2811 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2812 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2813 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2815 (int_x86_ssse3_palign_r
2817 (bitconvert (memopv2i32 addr:$src2)),
2820 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2821 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2822 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2824 (int_x86_ssse3_palign_r_128
2825 VR128:$src1, VR128:$src2,
2826 imm:$src3))]>, OpSize;
2827 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2828 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2829 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2831 (int_x86_ssse3_palign_r_128
2833 (bitconvert (memopv4i32 addr:$src2)),
2834 imm:$src3))]>, OpSize;
2837 //===----------------------------------------------------------------------===//
2838 // Non-Instruction Patterns
2839 //===----------------------------------------------------------------------===//
2841 // extload f32 -> f64. This matches load+fextend because we have a hack in
2842 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2843 // Since these loads aren't folded into the fextend, we have to match it
2845 let Predicates = [HasSSE2] in
2846 def : Pat<(fextend (loadf32 addr:$src)),
2847 (CVTSS2SDrm addr:$src)>;
2850 let Predicates = [HasSSE2] in {
2851 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2852 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2853 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2854 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2855 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2856 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2857 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2858 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2859 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2860 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2861 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2862 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2863 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2864 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2865 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2866 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2867 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2868 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2869 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2870 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2871 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2872 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2873 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2874 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2875 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2876 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2877 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2878 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2879 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2880 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2883 // Move scalar to XMM zero-extended
2884 // movd to XMM register zero-extends
2885 let AddedComplexity = 15 in {
2886 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2887 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2888 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2889 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2890 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2891 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2892 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2893 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2894 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2897 // Splat v2f64 / v2i64
2898 let AddedComplexity = 10 in {
2899 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2900 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2901 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2902 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2903 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2904 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2905 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2906 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2909 // Special unary SHUFPSrri case.
2910 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2911 SHUFP_unary_shuffle_mask:$sm)),
2912 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2913 Requires<[HasSSE1]>;
2914 // Special unary SHUFPDrri case.
2915 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2916 SHUFP_unary_shuffle_mask:$sm)),
2917 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2918 Requires<[HasSSE2]>;
2919 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2920 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2921 SHUFP_unary_shuffle_mask:$sm),
2922 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2923 Requires<[HasSSE2]>;
2924 // Special binary v4i32 shuffle cases with SHUFPS.
2925 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2926 PSHUFD_binary_shuffle_mask:$sm)),
2927 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2928 Requires<[HasSSE2]>;
2929 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2930 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2931 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2932 Requires<[HasSSE2]>;
2933 // Special binary v2i64 shuffle cases using SHUFPDrri.
2934 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2935 SHUFP_shuffle_mask:$sm)),
2936 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2937 Requires<[HasSSE2]>;
2938 // Special unary SHUFPDrri case.
2939 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2940 SHUFP_unary_shuffle_mask:$sm)),
2941 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2942 Requires<[HasSSE2]>;
2944 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2945 let AddedComplexity = 10 in {
2946 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2947 UNPCKL_v_undef_shuffle_mask)),
2948 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2949 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2950 UNPCKL_v_undef_shuffle_mask)),
2951 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2952 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2953 UNPCKL_v_undef_shuffle_mask)),
2954 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2955 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2956 UNPCKL_v_undef_shuffle_mask)),
2957 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2960 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2961 let AddedComplexity = 10 in {
2962 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2963 UNPCKH_v_undef_shuffle_mask)),
2964 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2965 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2966 UNPCKH_v_undef_shuffle_mask)),
2967 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2968 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2969 UNPCKH_v_undef_shuffle_mask)),
2970 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2971 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2972 UNPCKH_v_undef_shuffle_mask)),
2973 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2976 let AddedComplexity = 15 in {
2977 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2978 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2979 MOVHP_shuffle_mask)),
2980 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2982 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2983 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2984 MOVHLPS_shuffle_mask)),
2985 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2987 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2988 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2989 MOVHLPS_v_undef_shuffle_mask)),
2990 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2991 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2992 MOVHLPS_v_undef_shuffle_mask)),
2993 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2996 let AddedComplexity = 20 in {
2997 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2998 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2999 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3000 MOVLP_shuffle_mask)),
3001 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3002 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3003 MOVLP_shuffle_mask)),
3004 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3005 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
3006 MOVHP_shuffle_mask)),
3007 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3008 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3009 MOVHP_shuffle_mask)),
3010 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3012 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3013 (bc_v4i32 (memopv2i64 addr:$src2)),
3014 MOVLP_shuffle_mask)),
3015 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3016 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3017 MOVLP_shuffle_mask)),
3018 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3019 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
3020 (bc_v4i32 (memopv2i64 addr:$src2)),
3021 MOVHP_shuffle_mask)),
3022 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
3023 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3024 MOVHP_shuffle_mask)),
3025 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3028 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3029 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3030 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3031 MOVLP_shuffle_mask)), addr:$src1),
3032 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3033 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3034 MOVLP_shuffle_mask)), addr:$src1),
3035 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3036 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3037 MOVHP_shuffle_mask)), addr:$src1),
3038 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3039 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3040 MOVHP_shuffle_mask)), addr:$src1),
3041 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3043 def : Pat<(store (v4i32 (vector_shuffle
3044 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3045 MOVLP_shuffle_mask)), addr:$src1),
3046 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3047 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3048 MOVLP_shuffle_mask)), addr:$src1),
3049 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3050 def : Pat<(store (v4i32 (vector_shuffle
3051 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3052 MOVHP_shuffle_mask)), addr:$src1),
3053 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3054 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3055 MOVHP_shuffle_mask)), addr:$src1),
3056 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3059 let AddedComplexity = 15 in {
3060 // Setting the lowest element in the vector.
3061 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3062 MOVL_shuffle_mask)),
3063 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3064 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3065 MOVL_shuffle_mask)),
3066 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3068 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3069 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3070 MOVLP_shuffle_mask)),
3071 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3072 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3073 MOVLP_shuffle_mask)),
3074 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3077 // Set lowest element and zero upper elements.
3078 let AddedComplexity = 15 in
3079 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3080 MOVL_shuffle_mask)),
3081 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3082 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3083 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3085 // Some special case pandn patterns.
3086 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3088 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3089 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3091 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3092 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3094 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3096 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3097 (memop addr:$src2))),
3098 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3099 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3100 (memop addr:$src2))),
3101 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3102 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3103 (memop addr:$src2))),
3104 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3106 // vector -> vector casts
3107 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3108 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3109 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3110 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3111 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3112 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3113 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3114 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3116 // Use movaps / movups for SSE integer load / store (one byte shorter).
3117 def : Pat<(alignedloadv4i32 addr:$src),
3118 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3119 def : Pat<(loadv4i32 addr:$src),
3120 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3121 def : Pat<(alignedloadv2i64 addr:$src),
3122 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3123 def : Pat<(loadv2i64 addr:$src),
3124 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3126 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3127 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3128 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3129 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3130 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3131 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3132 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3133 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3134 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3135 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3136 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3137 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3138 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3139 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3140 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3141 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3143 //===----------------------------------------------------------------------===//
3144 // SSE4.1 Instructions
3145 //===----------------------------------------------------------------------===//
3147 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3148 bits<8> opcsd, bits<8> opcpd,
3153 Intrinsic V2F64Int> {
3154 // Intrinsic operation, reg.
3155 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3156 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3157 !strconcat(OpcodeStr,
3158 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3159 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3162 // Intrinsic operation, mem.
3163 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3164 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3165 !strconcat(OpcodeStr,
3166 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3167 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3170 // Vector intrinsic operation, reg
3171 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3172 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3173 !strconcat(OpcodeStr,
3174 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3175 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3178 // Vector intrinsic operation, mem
3179 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3180 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3181 !strconcat(OpcodeStr,
3182 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3184 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3187 // Intrinsic operation, reg.
3188 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3189 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3190 !strconcat(OpcodeStr,
3191 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3192 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3195 // Intrinsic operation, mem.
3196 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3197 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3198 !strconcat(OpcodeStr,
3199 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3200 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3203 // Vector intrinsic operation, reg
3204 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3205 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3206 !strconcat(OpcodeStr,
3207 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3208 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3211 // Vector intrinsic operation, mem
3212 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3213 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3214 !strconcat(OpcodeStr,
3215 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3217 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3221 // FP round - roundss, roundps, roundsd, roundpd
3222 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3223 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3224 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3226 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3227 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3228 Intrinsic IntId128> {
3229 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3231 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3232 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3233 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3235 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3238 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3241 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3242 int_x86_sse41_phminposuw>;
3244 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3245 let Constraints = "$src1 = $dst" in {
3246 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3247 Intrinsic IntId128, bit Commutable = 0> {
3248 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3249 (ins VR128:$src1, VR128:$src2),
3250 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3251 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3253 let isCommutable = Commutable;
3255 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3256 (ins VR128:$src1, i128mem:$src2),
3257 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3259 (IntId128 VR128:$src1,
3260 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3264 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3265 int_x86_sse41_pcmpeqq, 1>;
3266 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3267 int_x86_sse41_packusdw, 0>;
3268 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3269 int_x86_sse41_pminsb, 1>;
3270 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3271 int_x86_sse41_pminsd, 1>;
3272 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3273 int_x86_sse41_pminud, 1>;
3274 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3275 int_x86_sse41_pminuw, 1>;
3276 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3277 int_x86_sse41_pmaxsb, 1>;
3278 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3279 int_x86_sse41_pmaxsd, 1>;
3280 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3281 int_x86_sse41_pmaxud, 1>;
3282 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3283 int_x86_sse41_pmaxuw, 1>;
3285 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3286 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3287 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3288 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3291 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3292 let Constraints = "$src1 = $dst" in {
3293 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3294 SDNode OpNode, Intrinsic IntId128,
3295 bit Commutable = 0> {
3296 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3297 (ins VR128:$src1, VR128:$src2),
3298 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3299 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3300 VR128:$src2))]>, OpSize {
3301 let isCommutable = Commutable;
3303 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3304 (ins VR128:$src1, VR128:$src2),
3305 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3306 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3308 let isCommutable = Commutable;
3310 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3311 (ins VR128:$src1, i128mem:$src2),
3312 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3314 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3315 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3316 (ins VR128:$src1, i128mem:$src2),
3317 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3319 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3323 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3324 int_x86_sse41_pmulld, 1>;
3325 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3326 int_x86_sse41_pmuldq, 1>;
3329 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3330 let Constraints = "$src1 = $dst" in {
3331 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3332 Intrinsic IntId128, bit Commutable = 0> {
3333 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3334 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3335 !strconcat(OpcodeStr,
3336 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3338 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3340 let isCommutable = Commutable;
3342 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3343 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3344 !strconcat(OpcodeStr,
3345 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3347 (IntId128 VR128:$src1,
3348 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3353 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3354 int_x86_sse41_blendps, 0>;
3355 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3356 int_x86_sse41_blendpd, 0>;
3357 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3358 int_x86_sse41_pblendw, 0>;
3359 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3360 int_x86_sse41_dpps, 1>;
3361 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3362 int_x86_sse41_dppd, 1>;
3363 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3364 int_x86_sse41_mpsadbw, 1>;
3367 /// SS41I_ternary_int - SSE 4.1 ternary operator
3368 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3369 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3370 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3371 (ins VR128:$src1, VR128:$src2),
3372 !strconcat(OpcodeStr,
3373 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3374 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3377 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3378 (ins VR128:$src1, i128mem:$src2),
3379 !strconcat(OpcodeStr,
3380 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3383 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3387 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3388 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3389 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3392 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3393 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3394 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3395 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3397 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3398 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3400 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3404 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3405 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3406 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3407 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3408 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3409 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3411 // Common patterns involving scalar load.
3412 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3413 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3414 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3415 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3417 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3418 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3419 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3420 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3422 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3423 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3424 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3425 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3427 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3428 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3429 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3430 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3432 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3433 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3434 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3435 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3437 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3438 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3439 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3440 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3443 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3444 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3445 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3446 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3448 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3449 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3451 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3455 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3456 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3457 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3458 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3460 // Common patterns involving scalar load
3461 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3462 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3463 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3464 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3466 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3467 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3468 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3469 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3472 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3473 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3474 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3475 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3477 // Expecting a i16 load any extended to i32 value.
3478 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3479 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3480 [(set VR128:$dst, (IntId (bitconvert
3481 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3485 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3486 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3488 // Common patterns involving scalar load
3489 def : Pat<(int_x86_sse41_pmovsxbq
3490 (bitconvert (v4i32 (X86vzmovl
3491 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3492 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3494 def : Pat<(int_x86_sse41_pmovzxbq
3495 (bitconvert (v4i32 (X86vzmovl
3496 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3497 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3500 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3501 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3502 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3503 (ins VR128:$src1, i32i8imm:$src2),
3504 !strconcat(OpcodeStr,
3505 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3506 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3508 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3509 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3510 !strconcat(OpcodeStr,
3511 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3514 // There's an AssertZext in the way of writing the store pattern
3515 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3518 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3521 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3522 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3523 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3524 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3525 !strconcat(OpcodeStr,
3526 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3529 // There's an AssertZext in the way of writing the store pattern
3530 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3533 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3536 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3537 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3538 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3539 (ins VR128:$src1, i32i8imm:$src2),
3540 !strconcat(OpcodeStr,
3541 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3543 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3544 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3545 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3546 !strconcat(OpcodeStr,
3547 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3548 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3549 addr:$dst)]>, OpSize;
3552 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3555 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3557 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3558 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3559 (ins VR128:$src1, i32i8imm:$src2),
3560 !strconcat(OpcodeStr,
3561 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3563 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3565 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3566 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3567 !strconcat(OpcodeStr,
3568 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3569 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3570 addr:$dst)]>, OpSize;
3573 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3575 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3576 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3579 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3580 Requires<[HasSSE41]>;
3582 let Constraints = "$src1 = $dst" in {
3583 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3584 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3585 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3586 !strconcat(OpcodeStr,
3587 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3589 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3590 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3591 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3592 !strconcat(OpcodeStr,
3593 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3595 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3596 imm:$src3))]>, OpSize;
3600 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3602 let Constraints = "$src1 = $dst" in {
3603 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3604 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3605 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3606 !strconcat(OpcodeStr,
3607 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3609 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3611 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3612 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3613 !strconcat(OpcodeStr,
3614 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3616 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3617 imm:$src3)))]>, OpSize;
3621 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3623 let Constraints = "$src1 = $dst" in {
3624 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3625 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3626 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3627 !strconcat(OpcodeStr,
3628 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3630 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3631 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3632 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3633 !strconcat(OpcodeStr,
3634 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3636 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3637 imm:$src3))]>, OpSize;
3641 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3643 let Defs = [EFLAGS] in {
3644 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3645 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3646 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3647 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3650 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3651 "movntdqa\t{$src, $dst|$dst, $src}",
3652 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3654 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3655 let Constraints = "$src1 = $dst" in {
3656 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3657 Intrinsic IntId128, bit Commutable = 0> {
3658 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3659 (ins VR128:$src1, VR128:$src2),
3660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3661 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3663 let isCommutable = Commutable;
3665 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3666 (ins VR128:$src1, i128mem:$src2),
3667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3669 (IntId128 VR128:$src1,
3670 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3674 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3676 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3677 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3678 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3679 (PCMPGTQrm VR128:$src1, addr:$src2)>;