1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
21 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
27 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
28 InstrItinClass arg_ri> {
29 InstrItinClass rr = arg_rr;
30 InstrItinClass rm = arg_rm;
31 InstrItinClass ri = arg_ri;
36 def SSE_ALU_F32S : OpndItins<
37 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
40 def SSE_ALU_F64S : OpndItins<
41 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
44 def SSE_ALU_ITINS_S : SizeItins<
45 SSE_ALU_F32S, SSE_ALU_F64S
48 def SSE_MUL_F32S : OpndItins<
49 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
52 def SSE_MUL_F64S : OpndItins<
53 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
56 def SSE_MUL_ITINS_S : SizeItins<
57 SSE_MUL_F32S, SSE_MUL_F64S
60 def SSE_DIV_F32S : OpndItins<
61 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
64 def SSE_DIV_F64S : OpndItins<
65 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
68 def SSE_DIV_ITINS_S : SizeItins<
69 SSE_DIV_F32S, SSE_DIV_F64S
73 def SSE_ALU_F32P : OpndItins<
74 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
77 def SSE_ALU_F64P : OpndItins<
78 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
81 def SSE_ALU_ITINS_P : SizeItins<
82 SSE_ALU_F32P, SSE_ALU_F64P
85 def SSE_MUL_F32P : OpndItins<
86 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
89 def SSE_MUL_F64P : OpndItins<
90 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
93 def SSE_MUL_ITINS_P : SizeItins<
94 SSE_MUL_F32P, SSE_MUL_F64P
97 def SSE_DIV_F32P : OpndItins<
98 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
101 def SSE_DIV_F64P : OpndItins<
102 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
105 def SSE_DIV_ITINS_P : SizeItins<
106 SSE_DIV_F32P, SSE_DIV_F64P
109 def SSE_BIT_ITINS_P : OpndItins<
110 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
113 def SSE_INTALU_ITINS_P : OpndItins<
114 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
117 def SSE_INTALUQ_ITINS_P : OpndItins<
118 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
121 def SSE_INTMUL_ITINS_P : OpndItins<
122 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
125 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
126 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
129 def SSE_MOVA_ITINS : OpndItins<
130 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
133 def SSE_MOVU_ITINS : OpndItins<
134 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
137 //===----------------------------------------------------------------------===//
138 // SSE 1 & 2 Instructions Classes
139 //===----------------------------------------------------------------------===//
141 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
142 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
143 RegisterClass RC, X86MemOperand x86memop,
146 let isCommutable = 1 in {
147 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
149 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
151 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr>;
153 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
155 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
156 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
157 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm>;
160 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
161 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
162 string asm, string SSEVer, string FPSizeStr,
163 Operand memopr, ComplexPattern mem_cpat,
166 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
168 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
169 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
170 [(set RC:$dst, (!cast<Intrinsic>(
171 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
172 RC:$src1, RC:$src2))], itins.rr>;
173 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
175 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
176 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
177 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
178 SSEVer, "_", OpcodeStr, FPSizeStr))
179 RC:$src1, mem_cpat:$src2))], itins.rm>;
182 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
183 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
184 RegisterClass RC, ValueType vt,
185 X86MemOperand x86memop, PatFrag mem_frag,
186 Domain d, OpndItins itins, bit Is2Addr = 1> {
187 let isCommutable = 1 in
188 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
191 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
192 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>;
194 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
196 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
197 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
198 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
202 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
203 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
204 string OpcodeStr, X86MemOperand x86memop,
205 list<dag> pat_rr, list<dag> pat_rm,
207 bit rr_hasSideEffects = 0> {
208 let isCommutable = 1, neverHasSideEffects = rr_hasSideEffects in
209 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
211 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
212 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
213 pat_rr, IIC_DEFAULT, d>;
214 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
216 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
217 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
218 pat_rm, IIC_DEFAULT, d>;
221 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
222 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
223 string asm, string SSEVer, string FPSizeStr,
224 X86MemOperand x86memop, PatFrag mem_frag,
225 Domain d, OpndItins itins, bit Is2Addr = 1> {
226 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
228 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
229 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
230 [(set RC:$dst, (!cast<Intrinsic>(
231 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
232 RC:$src1, RC:$src2))], IIC_DEFAULT, d>;
233 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
235 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
236 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
237 [(set RC:$dst, (!cast<Intrinsic>(
238 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
239 RC:$src1, (mem_frag addr:$src2)))], IIC_DEFAULT, d>;
242 //===----------------------------------------------------------------------===//
243 // Non-instruction patterns
244 //===----------------------------------------------------------------------===//
246 // A vector extract of the first f32/f64 position is a subregister copy
247 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
248 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
249 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
250 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
252 // A 128-bit subvector extract from the first 256-bit vector position
253 // is a subregister copy that needs no instruction.
254 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
255 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
256 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
257 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
259 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
260 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
261 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
262 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
264 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (i32 0))),
265 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
266 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (i32 0))),
267 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
269 // A 128-bit subvector insert to the first 256-bit vector position
270 // is a subregister copy that needs no instruction.
271 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
272 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
273 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
274 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
275 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
276 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
277 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
278 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
279 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
280 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
281 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
282 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
284 // Implicitly promote a 32-bit scalar to a vector.
285 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
286 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
287 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
288 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
289 // Implicitly promote a 64-bit scalar to a vector.
290 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
291 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
292 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
293 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
295 // Bitcasts between 128-bit vector types. Return the original type since
296 // no instruction is needed for the conversion
297 let Predicates = [HasSSE2] in {
298 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
299 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
300 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
301 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
302 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
303 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
304 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
305 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
306 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
307 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
308 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
309 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
310 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
311 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
312 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
314 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
315 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
316 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
317 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
318 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
319 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
320 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
321 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
322 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
323 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
324 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
325 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
326 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
327 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
330 // Bitcasts between 256-bit vector types. Return the original type since
331 // no instruction is needed for the conversion
332 let Predicates = [HasAVX] in {
333 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
334 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
335 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
336 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
337 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
338 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
339 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
340 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
341 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
342 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
343 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
344 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
345 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
346 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
347 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
348 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
349 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
350 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
351 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
352 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
353 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
354 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
355 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
356 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
357 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
358 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
359 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
360 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
361 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
362 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
365 // Alias instructions that map fld0 to pxor for sse.
366 // This is expanded by ExpandPostRAPseudos.
367 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
369 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
370 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
371 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
372 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
375 //===----------------------------------------------------------------------===//
376 // AVX & SSE - Zero/One Vectors
377 //===----------------------------------------------------------------------===//
379 // Alias instruction that maps zero vector to pxor / xorp* for sse.
380 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
381 // swizzled by ExecutionDepsFix to pxor.
382 // We set canFoldAsLoad because this can be converted to a constant-pool
383 // load of an all-zeros value if folding it would be beneficial.
384 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
385 isPseudo = 1, neverHasSideEffects = 1 in {
386 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "", []>;
389 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
390 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
391 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
392 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
393 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
394 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
397 // The same as done above but for AVX. The 256-bit ISA does not support PI,
398 // and doesn't need it because on sandy bridge the register is set to zero
399 // at the rename stage without using any execution unit, so SET0PSY
400 // and SET0PDY can be used for vector int instructions without penalty
401 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
402 // JIT implementatioan, it does not expand the instructions below like
403 // X86MCInstLower does.
404 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
405 isCodeGenOnly = 1 in {
406 let Predicates = [HasAVX] in {
407 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
408 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
409 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
410 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
412 let Predicates = [HasAVX2], neverHasSideEffects = 1 in
413 def AVX2_SET0 : PDI<0xef, MRMInitReg, (outs VR256:$dst), (ins), "",
417 let Predicates = [HasAVX2], AddedComplexity = 5 in {
418 def : Pat<(v4i64 immAllZerosV), (AVX2_SET0)>;
419 def : Pat<(v8i32 immAllZerosV), (AVX2_SET0)>;
420 def : Pat<(v16i16 immAllZerosV), (AVX2_SET0)>;
421 def : Pat<(v32i8 immAllZerosV), (AVX2_SET0)>;
424 // AVX has no support for 256-bit integer instructions, but since the 128-bit
425 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
426 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
427 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
428 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
430 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
431 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
432 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
434 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
435 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
436 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
438 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
439 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
440 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
442 // We set canFoldAsLoad because this can be converted to a constant-pool
443 // load of an all-ones value if folding it would be beneficial.
444 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
445 // JIT implementation, it does not expand the instructions below like
446 // X86MCInstLower does.
447 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
448 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in {
449 let Predicates = [HasAVX] in
450 def AVX_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
451 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
452 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
453 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
454 let Predicates = [HasAVX2] in
455 def AVX2_SETALLONES : PDI<0x76, MRMInitReg, (outs VR256:$dst), (ins), "",
456 [(set VR256:$dst, (v8i32 immAllOnesV))]>, VEX_4V;
460 //===----------------------------------------------------------------------===//
461 // SSE 1 & 2 - Move FP Scalar Instructions
463 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
464 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
465 // is used instead. Register-to-register movss/movsd is not modeled as an
466 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
467 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
468 //===----------------------------------------------------------------------===//
470 class sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt, string asm> :
471 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
472 [(set VR128:$dst, (vt (OpNode VR128:$src1,
473 (scalar_to_vector RC:$src2))))],
476 // Loading from memory automatically zeroing upper bits.
477 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
478 PatFrag mem_pat, string OpcodeStr> :
479 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
481 [(set RC:$dst, (mem_pat addr:$src))],
485 def VMOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
486 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
488 def VMOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
489 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
492 // For the disassembler
493 let isCodeGenOnly = 1 in {
494 def VMOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
495 (ins VR128:$src1, FR32:$src2),
496 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
499 def VMOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
500 (ins VR128:$src1, FR64:$src2),
501 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
506 let canFoldAsLoad = 1, isReMaterializable = 1 in {
507 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
509 let AddedComplexity = 20 in
510 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
514 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
515 "movss\t{$src, $dst|$dst, $src}",
516 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
518 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
519 "movsd\t{$src, $dst|$dst, $src}",
520 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
524 let Constraints = "$src1 = $dst" in {
525 def MOVSSrr : sse12_move_rr<FR32, X86Movss, v4f32,
526 "movss\t{$src2, $dst|$dst, $src2}">, XS;
527 def MOVSDrr : sse12_move_rr<FR64, X86Movsd, v2f64,
528 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
530 // For the disassembler
531 let isCodeGenOnly = 1 in {
532 def MOVSSrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
533 (ins VR128:$src1, FR32:$src2),
534 "movss\t{$src2, $dst|$dst, $src2}", [],
535 IIC_SSE_MOV_S_RR>, XS;
536 def MOVSDrr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
537 (ins VR128:$src1, FR64:$src2),
538 "movsd\t{$src2, $dst|$dst, $src2}", [],
539 IIC_SSE_MOV_S_RR>, XD;
543 let canFoldAsLoad = 1, isReMaterializable = 1 in {
544 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
546 let AddedComplexity = 20 in
547 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
550 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
551 "movss\t{$src, $dst|$dst, $src}",
552 [(store FR32:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
553 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
554 "movsd\t{$src, $dst|$dst, $src}",
555 [(store FR64:$src, addr:$dst)], IIC_SSE_MOV_S_MR>;
558 let Predicates = [HasAVX] in {
559 let AddedComplexity = 15 in {
560 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
561 // MOVS{S,D} to the lower bits.
562 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
563 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
564 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
565 (VMOVSSrr (v4f32 (V_SET0)),
566 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
567 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
568 (VMOVSSrr (v4i32 (V_SET0)),
569 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
570 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
571 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
573 // Move low f32 and clear high bits.
574 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
575 (SUBREG_TO_REG (i32 0),
576 (VMOVSSrr (v4f32 (V_SET0)),
577 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_ss)), sub_xmm)>;
578 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
579 (SUBREG_TO_REG (i32 0),
580 (VMOVSSrr (v4i32 (V_SET0)),
581 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_ss)), sub_xmm)>;
584 let AddedComplexity = 20 in {
585 // MOVSSrm zeros the high parts of the register; represent this
586 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
587 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
588 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
589 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
590 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
591 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
592 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
594 // MOVSDrm zeros the high parts of the register; represent this
595 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
596 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
597 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
598 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
599 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
600 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
601 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
602 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
603 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
604 def : Pat<(v2f64 (X86vzload addr:$src)),
605 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
607 // Represent the same patterns above but in the form they appear for
609 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
610 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (i32 0)))),
611 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
612 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
613 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (i32 0)))),
614 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_ss)>;
615 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
616 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (i32 0)))),
617 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_sd)>;
619 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
620 (v4f32 (scalar_to_vector FR32:$src)), (i32 0)))),
621 (SUBREG_TO_REG (i32 0),
622 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
624 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
625 (v2f64 (scalar_to_vector FR64:$src)), (i32 0)))),
626 (SUBREG_TO_REG (i64 0),
627 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
629 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
630 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
631 (SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
633 // Move low f64 and clear high bits.
634 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
635 (SUBREG_TO_REG (i32 0),
636 (VMOVSDrr (v2f64 (V_SET0)),
637 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_sd)), sub_xmm)>;
639 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
640 (SUBREG_TO_REG (i32 0),
641 (VMOVSDrr (v2i64 (V_SET0)),
642 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_sd)), sub_xmm)>;
644 // Extract and store.
645 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
648 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
649 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
652 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
654 // Shuffle with VMOVSS
655 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
656 (VMOVSSrr (v4i32 VR128:$src1),
657 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
658 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
659 (VMOVSSrr (v4f32 VR128:$src1),
660 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
663 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
664 (SUBREG_TO_REG (i32 0),
665 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_ss),
666 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_ss)), sub_xmm)>;
667 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
668 (SUBREG_TO_REG (i32 0),
669 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_ss),
670 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_ss)), sub_xmm)>;
672 // Shuffle with VMOVSD
673 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
674 (VMOVSDrr (v2i64 VR128:$src1),
675 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
676 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
677 (VMOVSDrr (v2f64 VR128:$src1),
678 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
679 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
680 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
682 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
683 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
687 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
688 (SUBREG_TO_REG (i32 0),
689 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_sd),
690 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_sd)), sub_xmm)>;
691 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_sd),
694 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_sd)), sub_xmm)>;
697 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
698 // is during lowering, where it's not possible to recognize the fold cause
699 // it has two uses through a bitcast. One use disappears at isel time and the
700 // fold opportunity reappears.
701 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
702 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),
704 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
705 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),
707 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
708 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),
710 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),
715 let Predicates = [HasSSE1] in {
716 let AddedComplexity = 15 in {
717 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
718 // MOVSS to the lower bits.
719 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
720 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
721 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
722 (MOVSSrr (v4f32 (V_SET0)),
723 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)),
726 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
729 let AddedComplexity = 20 in {
730 // MOVSSrm zeros the high parts of the register; represent this
731 // with SUBREG_TO_REG.
732 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
733 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
734 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
735 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
736 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
737 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
740 // Extract and store.
741 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
744 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
746 // Shuffle with MOVSS
747 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
748 (MOVSSrr (v4i32 VR128:$src1),
749 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
750 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
751 (MOVSSrr (v4f32 VR128:$src1),
752 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
755 let Predicates = [HasSSE2] in {
756 let AddedComplexity = 15 in {
757 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
758 // MOVSD to the lower bits.
759 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
760 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
763 let AddedComplexity = 20 in {
764 // MOVSDrm zeros the high parts of the register; represent this
765 // with SUBREG_TO_REG.
766 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
767 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
768 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
769 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
770 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
771 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
772 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
773 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
774 def : Pat<(v2f64 (X86vzload addr:$src)),
775 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
778 // Extract and store.
779 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
782 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
784 // Shuffle with MOVSD
785 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
786 (MOVSDrr (v2i64 VR128:$src1),
787 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
788 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
789 (MOVSDrr (v2f64 VR128:$src1),
790 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
791 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
793 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
796 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
797 // is during lowering, where it's not possible to recognize the fold cause
798 // it has two uses through a bitcast. One use disappears at isel time and the
799 // fold opportunity reappears.
800 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
801 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2f64 VR128:$src2),sub_sd))>;
802 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
803 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v2i64 VR128:$src2),sub_sd))>;
804 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
805 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2),sub_sd))>;
806 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
807 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2),sub_sd))>;
810 //===----------------------------------------------------------------------===//
811 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
812 //===----------------------------------------------------------------------===//
814 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
815 X86MemOperand x86memop, PatFrag ld_frag,
816 string asm, Domain d,
818 bit IsReMaterializable = 1> {
819 let neverHasSideEffects = 1 in
820 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
821 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>;
822 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
823 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
824 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
825 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>;
828 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
829 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
831 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
832 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
834 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
835 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
837 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
838 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
841 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
842 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
844 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
845 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
847 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
848 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
850 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
851 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
853 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
854 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
856 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
857 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
859 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
860 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
862 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
863 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
867 "movaps\t{$src, $dst|$dst, $src}",
868 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
869 IIC_SSE_MOVA_P_MR>, VEX;
870 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
871 "movapd\t{$src, $dst|$dst, $src}",
872 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
873 IIC_SSE_MOVA_P_MR>, VEX;
874 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
875 "movups\t{$src, $dst|$dst, $src}",
876 [(store (v4f32 VR128:$src), addr:$dst)],
877 IIC_SSE_MOVU_P_MR>, VEX;
878 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
879 "movupd\t{$src, $dst|$dst, $src}",
880 [(store (v2f64 VR128:$src), addr:$dst)],
881 IIC_SSE_MOVU_P_MR>, VEX;
882 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
883 "movaps\t{$src, $dst|$dst, $src}",
884 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
885 IIC_SSE_MOVA_P_MR>, VEX;
886 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
887 "movapd\t{$src, $dst|$dst, $src}",
888 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
889 IIC_SSE_MOVA_P_MR>, VEX;
890 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
891 "movups\t{$src, $dst|$dst, $src}",
892 [(store (v8f32 VR256:$src), addr:$dst)],
893 IIC_SSE_MOVU_P_MR>, VEX;
894 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
895 "movupd\t{$src, $dst|$dst, $src}",
896 [(store (v4f64 VR256:$src), addr:$dst)],
897 IIC_SSE_MOVU_P_MR>, VEX;
900 let isCodeGenOnly = 1 in {
901 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
903 "movaps\t{$src, $dst|$dst, $src}", [],
904 IIC_SSE_MOVA_P_RR>, VEX;
905 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
907 "movapd\t{$src, $dst|$dst, $src}", [],
908 IIC_SSE_MOVA_P_RR>, VEX;
909 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
911 "movups\t{$src, $dst|$dst, $src}", [],
912 IIC_SSE_MOVU_P_RR>, VEX;
913 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
915 "movupd\t{$src, $dst|$dst, $src}", [],
916 IIC_SSE_MOVU_P_RR>, VEX;
917 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
919 "movaps\t{$src, $dst|$dst, $src}", [],
920 IIC_SSE_MOVA_P_RR>, VEX;
921 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
923 "movapd\t{$src, $dst|$dst, $src}", [],
924 IIC_SSE_MOVA_P_RR>, VEX;
925 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
927 "movups\t{$src, $dst|$dst, $src}", [],
928 IIC_SSE_MOVU_P_RR>, VEX;
929 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
931 "movupd\t{$src, $dst|$dst, $src}", [],
932 IIC_SSE_MOVU_P_RR>, VEX;
935 let Predicates = [HasAVX] in {
936 def : Pat<(v8i32 (X86vzmovl
937 (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
938 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
939 def : Pat<(v4i64 (X86vzmovl
940 (insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v8f32 (X86vzmovl
943 (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v4f64 (X86vzmovl
946 (insert_subvector undef, (v2f64 VR128:$src), (i32 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
951 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
952 (VMOVUPSYmr addr:$dst, VR256:$src)>;
953 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
954 (VMOVUPDYmr addr:$dst, VR256:$src)>;
956 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
957 "movaps\t{$src, $dst|$dst, $src}",
958 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
960 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movapd\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
964 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movups\t{$src, $dst|$dst, $src}",
966 [(store (v4f32 VR128:$src), addr:$dst)],
968 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movupd\t{$src, $dst|$dst, $src}",
970 [(store (v2f64 VR128:$src), addr:$dst)],
974 let isCodeGenOnly = 1 in {
975 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
976 "movaps\t{$src, $dst|$dst, $src}", [],
978 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
979 "movapd\t{$src, $dst|$dst, $src}", [],
981 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movups\t{$src, $dst|$dst, $src}", [],
984 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movupd\t{$src, $dst|$dst, $src}", [],
989 let Predicates = [HasAVX] in {
990 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
991 (VMOVUPSmr addr:$dst, VR128:$src)>;
992 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
993 (VMOVUPDmr addr:$dst, VR128:$src)>;
996 let Predicates = [HasSSE1] in
997 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
998 (MOVUPSmr addr:$dst, VR128:$src)>;
999 let Predicates = [HasSSE2] in
1000 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1001 (MOVUPDmr addr:$dst, VR128:$src)>;
1003 // Use vmovaps/vmovups for AVX integer load/store.
1004 let Predicates = [HasAVX] in {
1005 // 128-bit load/store
1006 def : Pat<(alignedloadv2i64 addr:$src),
1007 (VMOVAPSrm addr:$src)>;
1008 def : Pat<(loadv2i64 addr:$src),
1009 (VMOVUPSrm addr:$src)>;
1011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1012 (VMOVAPSmr addr:$dst, VR128:$src)>;
1013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1014 (VMOVAPSmr addr:$dst, VR128:$src)>;
1015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1016 (VMOVAPSmr addr:$dst, VR128:$src)>;
1017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1020 (VMOVUPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1022 (VMOVUPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1024 (VMOVUPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1028 // 256-bit load/store
1029 def : Pat<(alignedloadv4i64 addr:$src),
1030 (VMOVAPSYrm addr:$src)>;
1031 def : Pat<(loadv4i64 addr:$src),
1032 (VMOVUPSYrm addr:$src)>;
1033 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1034 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1035 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1036 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1037 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1038 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1039 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1042 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1044 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1046 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 // Use movaps / movups for SSE integer load / store (one byte shorter).
1052 // The instructions selected below are then converted to MOVDQA/MOVDQU
1053 // during the SSE domain pass.
1054 let Predicates = [HasSSE1] in {
1055 def : Pat<(alignedloadv2i64 addr:$src),
1056 (MOVAPSrm addr:$src)>;
1057 def : Pat<(loadv2i64 addr:$src),
1058 (MOVUPSrm addr:$src)>;
1060 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1061 (MOVAPSmr addr:$dst, VR128:$src)>;
1062 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1063 (MOVAPSmr addr:$dst, VR128:$src)>;
1064 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1065 (MOVAPSmr addr:$dst, VR128:$src)>;
1066 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1067 (MOVAPSmr addr:$dst, VR128:$src)>;
1068 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1069 (MOVUPSmr addr:$dst, VR128:$src)>;
1070 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1071 (MOVUPSmr addr:$dst, VR128:$src)>;
1072 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1073 (MOVUPSmr addr:$dst, VR128:$src)>;
1074 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1075 (MOVUPSmr addr:$dst, VR128:$src)>;
1078 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1079 // bits are disregarded. FIXME: Set encoding to pseudo!
1080 let neverHasSideEffects = 1 in {
1081 def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1082 "movaps\t{$src, $dst|$dst, $src}", [],
1083 IIC_SSE_MOVA_P_RR>, VEX;
1084 def FsVMOVAPDrr : VPDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1085 "movapd\t{$src, $dst|$dst, $src}", [],
1086 IIC_SSE_MOVA_P_RR>, VEX;
1087 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1088 "movaps\t{$src, $dst|$dst, $src}", [],
1090 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1091 "movapd\t{$src, $dst|$dst, $src}", [],
1095 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1096 // bits are disregarded. FIXME: Set encoding to pseudo!
1097 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1098 let isCodeGenOnly = 1 in {
1099 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1100 "movaps\t{$src, $dst|$dst, $src}",
1101 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1102 IIC_SSE_MOVA_P_RM>, VEX;
1103 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1104 "movapd\t{$src, $dst|$dst, $src}",
1105 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1106 IIC_SSE_MOVA_P_RM>, VEX;
1108 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1109 "movaps\t{$src, $dst|$dst, $src}",
1110 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1112 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1113 "movapd\t{$src, $dst|$dst, $src}",
1114 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1118 //===----------------------------------------------------------------------===//
1119 // SSE 1 & 2 - Move Low packed FP Instructions
1120 //===----------------------------------------------------------------------===//
1122 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
1123 SDNode psnode, SDNode pdnode, string base_opc,
1124 string asm_opr, InstrItinClass itin> {
1125 def PSrm : PI<opc, MRMSrcMem,
1126 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1127 !strconcat(base_opc, "s", asm_opr),
1130 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1131 itin, SSEPackedSingle>, TB;
1133 def PDrm : PI<opc, MRMSrcMem,
1134 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
1135 !strconcat(base_opc, "d", asm_opr),
1136 [(set RC:$dst, (v2f64 (pdnode RC:$src1,
1137 (scalar_to_vector (loadf64 addr:$src2)))))],
1138 itin, SSEPackedDouble>, TB, OpSize;
1141 let AddedComplexity = 20 in {
1142 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1144 IIC_SSE_MOV_LH>, VEX_4V;
1146 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1147 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, X86Movlps, X86Movlpd, "movlp",
1148 "\t{$src2, $dst|$dst, $src2}",
1152 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1153 "movlps\t{$src, $dst|$dst, $src}",
1154 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1155 (iPTR 0))), addr:$dst)],
1156 IIC_SSE_MOV_LH>, VEX;
1157 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1158 "movlpd\t{$src, $dst|$dst, $src}",
1159 [(store (f64 (vector_extract (v2f64 VR128:$src),
1160 (iPTR 0))), addr:$dst)],
1161 IIC_SSE_MOV_LH>, VEX;
1162 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1163 "movlps\t{$src, $dst|$dst, $src}",
1164 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1165 (iPTR 0))), addr:$dst)],
1167 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1168 "movlpd\t{$src, $dst|$dst, $src}",
1169 [(store (f64 (vector_extract (v2f64 VR128:$src),
1170 (iPTR 0))), addr:$dst)],
1173 let Predicates = [HasAVX] in {
1174 // Shuffle with VMOVLPS
1175 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1176 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1177 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1178 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1180 // Shuffle with VMOVLPD
1181 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1182 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1183 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1184 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1187 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1189 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1190 def : Pat<(store (v4i32 (X86Movlps
1191 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1192 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1193 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1195 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1196 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1198 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1201 let Predicates = [HasSSE1] in {
1202 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1203 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1204 (iPTR 0))), addr:$src1),
1205 (MOVLPSmr addr:$src1, VR128:$src2)>;
1207 // Shuffle with MOVLPS
1208 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1209 (MOVLPSrm VR128:$src1, addr:$src2)>;
1210 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1211 (MOVLPSrm VR128:$src1, addr:$src2)>;
1212 def : Pat<(X86Movlps VR128:$src1,
1213 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1214 (MOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1219 (MOVLPSmr addr:$src1, VR128:$src2)>;
1220 def : Pat<(store (v4i32 (X86Movlps
1221 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1223 (MOVLPSmr addr:$src1, VR128:$src2)>;
1226 let Predicates = [HasSSE2] in {
1227 // Shuffle with MOVLPD
1228 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1229 (MOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1231 (MOVLPDrm VR128:$src1, addr:$src2)>;
1234 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1236 (MOVLPDmr addr:$src1, VR128:$src2)>;
1237 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1239 (MOVLPDmr addr:$src1, VR128:$src2)>;
1242 //===----------------------------------------------------------------------===//
1243 // SSE 1 & 2 - Move Hi packed FP Instructions
1244 //===----------------------------------------------------------------------===//
1246 let AddedComplexity = 20 in {
1247 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1248 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1249 IIC_SSE_MOV_LH>, VEX_4V;
1251 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1252 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, X86Movlhps, X86Movlhpd, "movhp",
1253 "\t{$src2, $dst|$dst, $src2}",
1257 // v2f64 extract element 1 is always custom lowered to unpack high to low
1258 // and extract element 0 so the non-store version isn't too horrible.
1259 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1260 "movhps\t{$src, $dst|$dst, $src}",
1261 [(store (f64 (vector_extract
1262 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1263 (bc_v2f64 (v4f32 VR128:$src))),
1264 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1265 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1266 "movhpd\t{$src, $dst|$dst, $src}",
1267 [(store (f64 (vector_extract
1268 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1269 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1270 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1271 "movhps\t{$src, $dst|$dst, $src}",
1272 [(store (f64 (vector_extract
1273 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1274 (bc_v2f64 (v4f32 VR128:$src))),
1275 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1276 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1277 "movhpd\t{$src, $dst|$dst, $src}",
1278 [(store (f64 (vector_extract
1279 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1280 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1282 let Predicates = [HasAVX] in {
1284 def : Pat<(X86Movlhps VR128:$src1,
1285 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1286 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1287 def : Pat<(X86Movlhps VR128:$src1,
1288 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1289 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1291 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1292 // is during lowering, where it's not possible to recognize the load fold
1293 // cause it has two uses through a bitcast. One use disappears at isel time
1294 // and the fold opportunity reappears.
1295 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1296 (scalar_to_vector (loadf64 addr:$src2)))),
1297 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1300 let Predicates = [HasSSE1] in {
1302 def : Pat<(X86Movlhps VR128:$src1,
1303 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1304 (MOVHPSrm VR128:$src1, addr:$src2)>;
1305 def : Pat<(X86Movlhps VR128:$src1,
1306 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1307 (MOVHPSrm VR128:$src1, addr:$src2)>;
1310 let Predicates = [HasSSE2] in {
1311 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1312 // is during lowering, where it's not possible to recognize the load fold
1313 // cause it has two uses through a bitcast. One use disappears at isel time
1314 // and the fold opportunity reappears.
1315 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1316 (scalar_to_vector (loadf64 addr:$src2)))),
1317 (MOVHPDrm VR128:$src1, addr:$src2)>;
1320 //===----------------------------------------------------------------------===//
1321 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1322 //===----------------------------------------------------------------------===//
1324 let AddedComplexity = 20 in {
1325 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1326 (ins VR128:$src1, VR128:$src2),
1327 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1329 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1332 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1333 (ins VR128:$src1, VR128:$src2),
1334 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1336 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1340 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1341 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1342 (ins VR128:$src1, VR128:$src2),
1343 "movlhps\t{$src2, $dst|$dst, $src2}",
1345 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1347 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1348 (ins VR128:$src1, VR128:$src2),
1349 "movhlps\t{$src2, $dst|$dst, $src2}",
1351 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1355 let Predicates = [HasAVX] in {
1357 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1358 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1359 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1360 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1363 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1364 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1367 let Predicates = [HasSSE1] in {
1369 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1370 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1371 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1372 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1375 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1376 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1379 //===----------------------------------------------------------------------===//
1380 // SSE 1 & 2 - Conversion Instructions
1381 //===----------------------------------------------------------------------===//
1383 def SSE_CVT_PD : OpndItins<
1384 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1387 def SSE_CVT_PS : OpndItins<
1388 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1391 def SSE_CVT_Scalar : OpndItins<
1392 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1395 def SSE_CVT_SS2SI_32 : OpndItins<
1396 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1399 def SSE_CVT_SS2SI_64 : OpndItins<
1400 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1403 def SSE_CVT_SD2SI : OpndItins<
1404 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1407 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1408 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1409 string asm, OpndItins itins> {
1410 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1411 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1413 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1414 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1418 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1419 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1420 string asm, Domain d, OpndItins itins> {
1421 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1422 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1424 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1425 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1429 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1430 X86MemOperand x86memop, string asm> {
1431 let neverHasSideEffects = 1 in {
1432 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1433 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1435 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1436 (ins DstRC:$src1, x86memop:$src),
1437 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
1438 } // neverHasSideEffects = 1
1441 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1442 "cvttss2si\t{$src, $dst|$dst, $src}",
1445 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1446 "cvttss2si\t{$src, $dst|$dst, $src}",
1448 XS, VEX, VEX_W, VEX_LIG;
1449 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1450 "cvttsd2si\t{$src, $dst|$dst, $src}",
1453 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1454 "cvttsd2si\t{$src, $dst|$dst, $src}",
1456 XD, VEX, VEX_W, VEX_LIG;
1458 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1459 // register, but the same isn't true when only using memory operands,
1460 // provide other assembly "l" and "q" forms to address this explicitly
1461 // where appropriate to do so.
1462 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">,
1463 XS, VEX_4V, VEX_LIG;
1464 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1465 XS, VEX_4V, VEX_W, VEX_LIG;
1466 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">,
1467 XD, VEX_4V, VEX_LIG;
1468 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1469 XD, VEX_4V, VEX_LIG;
1470 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1471 XD, VEX_4V, VEX_W, VEX_LIG;
1473 let Predicates = [HasAVX], AddedComplexity = 1 in {
1474 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1475 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1476 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1477 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1478 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1479 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1480 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1481 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1483 def : Pat<(f32 (sint_to_fp GR32:$src)),
1484 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1485 def : Pat<(f32 (sint_to_fp GR64:$src)),
1486 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1487 def : Pat<(f64 (sint_to_fp GR32:$src)),
1488 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1489 def : Pat<(f64 (sint_to_fp GR64:$src)),
1490 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1493 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1494 "cvttss2si\t{$src, $dst|$dst, $src}",
1495 SSE_CVT_SS2SI_32>, XS;
1496 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1497 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1498 SSE_CVT_SS2SI_64>, XS, REX_W;
1499 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1500 "cvttsd2si\t{$src, $dst|$dst, $src}",
1502 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1503 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1504 SSE_CVT_SD2SI>, XD, REX_W;
1505 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1506 "cvtsi2ss\t{$src, $dst|$dst, $src}",
1507 SSE_CVT_Scalar>, XS;
1508 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1509 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1510 SSE_CVT_Scalar>, XS, REX_W;
1511 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1512 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1513 SSE_CVT_Scalar>, XD;
1514 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1515 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1516 SSE_CVT_Scalar>, XD, REX_W;
1518 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1519 // and/or XMM operand(s).
1521 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1522 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
1523 string asm, OpndItins itins> {
1524 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1525 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1526 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>;
1527 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
1528 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1529 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], itins.rm>;
1532 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1533 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1534 PatFrag ld_frag, string asm, OpndItins itins,
1536 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1538 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1539 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1540 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1542 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1543 (ins DstRC:$src1, x86memop:$src2),
1545 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1546 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1547 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1551 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1552 f128mem, load, "cvtsd2si", SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1553 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1554 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si",
1555 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1557 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1558 f128mem, load, "cvtsd2si{l}", SSE_CVT_SD2SI>, XD;
1559 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1560 f128mem, load, "cvtsd2si{q}", SSE_CVT_SD2SI>, XD, REX_W;
1563 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1564 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss",
1565 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1566 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1567 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss",
1568 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1570 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1571 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd",
1572 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1573 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1574 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd",
1575 SSE_CVT_Scalar, 0>, XD,
1578 let Constraints = "$src1 = $dst" in {
1579 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1580 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1581 "cvtsi2ss", SSE_CVT_Scalar>, XS;
1582 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1583 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1584 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1585 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1586 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1587 "cvtsi2sd", SSE_CVT_Scalar>, XD;
1588 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1589 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1590 "cvtsi2sd", SSE_CVT_Scalar>, XD, REX_W;
1595 // Aliases for intrinsics
1596 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1597 f32mem, load, "cvttss2si",
1598 SSE_CVT_SS2SI_32>, XS, VEX;
1599 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1600 int_x86_sse_cvttss2si64, f32mem, load,
1601 "cvttss2si", SSE_CVT_SS2SI_64>,
1603 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1604 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1606 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1607 int_x86_sse2_cvttsd2si64, f128mem, load,
1608 "cvttsd2si", SSE_CVT_SD2SI>,
1610 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1611 f32mem, load, "cvttss2si",
1612 SSE_CVT_SS2SI_32>, XS;
1613 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1614 int_x86_sse_cvttss2si64, f32mem, load,
1615 "cvttss2si{q}", SSE_CVT_SS2SI_64>,
1617 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1618 f128mem, load, "cvttsd2si", SSE_CVT_SD2SI>,
1620 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1621 int_x86_sse2_cvttsd2si64, f128mem, load,
1622 "cvttsd2si{q}", SSE_CVT_SD2SI>,
1625 let Pattern = []<dag> in {
1626 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
1627 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1628 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1629 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
1630 "cvtss2si\t{$src, $dst|$dst, $src}",
1631 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1632 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
1633 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1634 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1635 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
1636 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1637 SSEPackedSingle, SSE_CVT_PS>, TB, VEX;
1640 let Pattern = []<dag> in {
1641 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
1642 "cvtss2si{l}\t{$src, $dst|$dst, $src}",
1643 SSE_CVT_SS2SI_32>, XS;
1644 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
1645 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1646 SSE_CVT_SS2SI_64>, XS, REX_W;
1647 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
1648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1649 SSEPackedSingle, SSE_CVT_PS>,
1650 TB; /* PD SSE3 form is avaiable */
1653 let Predicates = [HasAVX] in {
1654 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1655 (VCVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1656 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1657 (VCVTSS2SIrm addr:$src)>;
1658 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1659 (VCVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1660 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1661 (VCVTSS2SI64rm addr:$src)>;
1664 let Predicates = [HasSSE1] in {
1665 def : Pat<(int_x86_sse_cvtss2si VR128:$src),
1666 (CVTSS2SIrr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1667 def : Pat<(int_x86_sse_cvtss2si (load addr:$src)),
1668 (CVTSS2SIrm addr:$src)>;
1669 def : Pat<(int_x86_sse_cvtss2si64 VR128:$src),
1670 (CVTSS2SI64rr (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1671 def : Pat<(int_x86_sse_cvtss2si64 (load addr:$src)),
1672 (CVTSS2SI64rm addr:$src)>;
1677 // Convert scalar double to scalar single
1678 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1679 (ins FR64:$src1, FR64:$src2),
1680 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1681 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG;
1683 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1684 (ins FR64:$src1, f64mem:$src2),
1685 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1686 [], IIC_SSE_CVT_Scalar_RM>,
1687 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG;
1689 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1692 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1693 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1694 [(set FR32:$dst, (fround FR64:$src))],
1695 IIC_SSE_CVT_Scalar_RR>;
1696 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1697 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1698 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1699 IIC_SSE_CVT_Scalar_RM>,
1701 Requires<[HasSSE2, OptForSize]>;
1703 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1704 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1707 let Constraints = "$src1 = $dst" in
1708 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
1709 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss",
1710 SSE_CVT_Scalar>, XS;
1712 // Convert scalar single to scalar double
1713 // SSE2 instructions with XS prefix
1714 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1715 (ins FR32:$src1, FR32:$src2),
1716 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1717 [], IIC_SSE_CVT_Scalar_RR>,
1718 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG;
1720 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1721 (ins FR32:$src1, f32mem:$src2),
1722 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1723 [], IIC_SSE_CVT_Scalar_RM>,
1724 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>;
1726 let Predicates = [HasAVX] in {
1727 def : Pat<(f64 (fextend FR32:$src)),
1728 (VCVTSS2SDrr FR32:$src, FR32:$src)>;
1729 def : Pat<(fextend (loadf32 addr:$src)),
1730 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1731 def : Pat<(extloadf32 addr:$src),
1732 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1735 def : Pat<(extloadf32 addr:$src),
1736 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (MOVSSrm addr:$src))>,
1737 Requires<[HasAVX, OptForSpeed]>;
1739 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1740 "cvtss2sd\t{$src, $dst|$dst, $src}",
1741 [(set FR64:$dst, (fextend FR32:$src))],
1742 IIC_SSE_CVT_Scalar_RR>, XS,
1743 Requires<[HasSSE2]>;
1744 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1745 "cvtss2sd\t{$src, $dst|$dst, $src}",
1746 [(set FR64:$dst, (extloadf32 addr:$src))],
1747 IIC_SSE_CVT_Scalar_RM>, XS,
1748 Requires<[HasSSE2, OptForSize]>;
1750 // extload f32 -> f64. This matches load+fextend because we have a hack in
1751 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1753 // Since these loads aren't folded into the fextend, we have to match it
1755 def : Pat<(fextend (loadf32 addr:$src)),
1756 (CVTSS2SDrm addr:$src)>, Requires<[HasSSE2]>;
1757 def : Pat<(extloadf32 addr:$src),
1758 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>;
1760 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1761 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1762 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1763 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1765 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V,
1767 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1768 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1769 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1770 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1771 (load addr:$src2)))],
1772 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V,
1774 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1775 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1776 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1777 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1778 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1780 IIC_SSE_CVT_Scalar_RR>, XS,
1781 Requires<[HasSSE2]>;
1782 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1783 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1784 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1786 (load addr:$src2)))],
1787 IIC_SSE_CVT_Scalar_RM>, XS,
1788 Requires<[HasSSE2]>;
1791 // Convert doubleword to packed single/double fp
1792 // SSE2 instructions without OpSize prefix
1793 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1794 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1795 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1797 TB, VEX, Requires<[HasAVX]>;
1798 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1799 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1800 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1801 (bitconvert (memopv2i64 addr:$src))))],
1803 TB, VEX, Requires<[HasAVX]>;
1804 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1805 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))],
1808 TB, Requires<[HasSSE2]>;
1809 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1810 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1811 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1812 (bitconvert (memopv2i64 addr:$src))))],
1814 TB, Requires<[HasSSE2]>;
1816 // FIXME: why the non-intrinsic version is described as SSE3?
1817 // SSE2 instructions with XS prefix
1818 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1819 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1820 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
1822 XS, VEX, Requires<[HasAVX]>;
1823 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1824 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
1825 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1826 (bitconvert (memopv2i64 addr:$src))))],
1828 XS, VEX, Requires<[HasAVX]>;
1829 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1830 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1831 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
1833 XS, Requires<[HasSSE2]>;
1834 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1835 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1836 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1837 (bitconvert (memopv2i64 addr:$src))))],
1839 XS, Requires<[HasSSE2]>;
1842 // Convert packed single/double fp to doubleword
1843 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1844 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1845 IIC_SSE_CVT_PS_RR>, VEX;
1846 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1847 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1848 IIC_SSE_CVT_PS_RM>, VEX;
1849 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1850 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1851 IIC_SSE_CVT_PS_RR>, VEX;
1852 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1853 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1854 IIC_SSE_CVT_PS_RM>, VEX;
1855 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1856 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1858 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1859 "cvtps2dq\t{$src, $dst|$dst, $src}", [],
1862 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1863 "cvtps2dq\t{$src, $dst|$dst, $src}",
1864 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1867 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
1869 "cvtps2dq\t{$src, $dst|$dst, $src}",
1870 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1871 (memop addr:$src)))],
1872 IIC_SSE_CVT_PS_RM>, VEX;
1873 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1874 "cvtps2dq\t{$src, $dst|$dst, $src}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1877 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1878 "cvtps2dq\t{$src, $dst|$dst, $src}",
1879 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1880 (memop addr:$src)))],
1883 // SSE2 packed instructions with XD prefix
1884 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1885 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1886 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1888 XD, VEX, Requires<[HasAVX]>;
1889 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1890 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
1891 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1892 (memop addr:$src)))],
1894 XD, VEX, Requires<[HasAVX]>;
1895 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1896 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1897 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
1899 XD, Requires<[HasSSE2]>;
1900 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1901 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1902 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1903 (memop addr:$src)))],
1905 XD, Requires<[HasSSE2]>;
1908 // Convert with truncation packed single/double fp to doubleword
1909 // SSE2 packed instructions with XS prefix
1910 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1911 "cvttps2dq\t{$src, $dst|$dst, $src}",
1913 (int_x86_sse2_cvttps2dq VR128:$src))],
1914 IIC_SSE_CVT_PS_RR>, VEX;
1915 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1916 "cvttps2dq\t{$src, $dst|$dst, $src}",
1917 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1918 (memop addr:$src)))],
1919 IIC_SSE_CVT_PS_RM>, VEX;
1920 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1921 "cvttps2dq\t{$src, $dst|$dst, $src}",
1923 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
1924 IIC_SSE_CVT_PS_RR>, VEX;
1925 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1926 "cvttps2dq\t{$src, $dst|$dst, $src}",
1927 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
1928 (memopv8f32 addr:$src)))],
1929 IIC_SSE_CVT_PS_RM>, VEX;
1931 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1932 "cvttps2dq\t{$src, $dst|$dst, $src}",
1934 (int_x86_sse2_cvttps2dq VR128:$src))],
1936 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1937 "cvttps2dq\t{$src, $dst|$dst, $src}",
1939 (int_x86_sse2_cvttps2dq (memop addr:$src)))],
1942 let Predicates = [HasAVX] in {
1943 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1944 (Int_VCVTDQ2PSrr VR128:$src)>;
1945 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1946 (Int_VCVTDQ2PSrm addr:$src)>;
1948 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1949 (VCVTTPS2DQrr VR128:$src)>;
1950 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1951 (VCVTTPS2DQrm addr:$src)>;
1953 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
1954 (VCVTDQ2PSYrr VR256:$src)>;
1955 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (memopv4i64 addr:$src)))),
1956 (VCVTDQ2PSYrm addr:$src)>;
1958 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
1959 (VCVTTPS2DQYrr VR256:$src)>;
1960 def : Pat<(v8i32 (fp_to_sint (memopv8f32 addr:$src))),
1961 (VCVTTPS2DQYrm addr:$src)>;
1964 let Predicates = [HasSSE2] in {
1965 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
1966 (Int_CVTDQ2PSrr VR128:$src)>;
1967 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
1968 (Int_CVTDQ2PSrm addr:$src)>;
1970 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
1971 (CVTTPS2DQrr VR128:$src)>;
1972 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
1973 (CVTTPS2DQrm addr:$src)>;
1976 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1977 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_sse2_cvttpd2dq VR128:$src))],
1980 IIC_SSE_CVT_PD_RR>, VEX;
1981 let isCodeGenOnly = 1 in
1982 def VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1983 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1984 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1985 (memop addr:$src)))],
1986 IIC_SSE_CVT_PD_RM>, VEX;
1987 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1988 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1989 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
1991 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1992 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1993 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1994 (memop addr:$src)))],
1997 // The assembler can recognize rr 256-bit instructions by seeing a ymm
1998 // register, but the same isn't true when using memory operands instead.
1999 // Provide other assembly rr and rm forms to address this explicitly.
2000 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2001 "cvttpd2dq\t{$src, $dst|$dst, $src}", [],
2002 IIC_SSE_CVT_PD_RR>, VEX;
2005 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2006 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2007 IIC_SSE_CVT_PD_RR>, VEX;
2008 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2009 "cvttpd2dqx\t{$src, $dst|$dst, $src}", [],
2010 IIC_SSE_CVT_PD_RM>, VEX;
2013 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2014 "cvttpd2dqy\t{$src, $dst|$dst, $src}", [],
2015 IIC_SSE_CVT_PD_RR>, VEX;
2016 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2017 "cvttpd2dqy\t{$src, $dst|$dst, $src}", [],
2018 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2020 // Convert packed single to packed double
2021 let Predicates = [HasAVX] in {
2022 // SSE2 instructions without OpSize prefix
2023 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2024 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2025 IIC_SSE_CVT_PD_RR>, TB, VEX;
2026 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2027 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2028 IIC_SSE_CVT_PD_RM>, TB, VEX;
2029 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2030 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2031 IIC_SSE_CVT_PD_RR>, TB, VEX;
2032 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2033 "vcvtps2pd\t{$src, $dst|$dst, $src}", [],
2034 IIC_SSE_CVT_PD_RM>, TB, VEX;
2036 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2038 IIC_SSE_CVT_PD_RR>, TB;
2039 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2040 "cvtps2pd\t{$src, $dst|$dst, $src}", [],
2041 IIC_SSE_CVT_PD_RM>, TB;
2043 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2045 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2047 TB, VEX, Requires<[HasAVX]>;
2048 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2049 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2051 (load addr:$src)))],
2053 TB, VEX, Requires<[HasAVX]>;
2054 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2055 "cvtps2pd\t{$src, $dst|$dst, $src}",
2056 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2058 TB, Requires<[HasSSE2]>;
2059 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2060 "cvtps2pd\t{$src, $dst|$dst, $src}",
2061 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
2062 (load addr:$src)))],
2064 TB, Requires<[HasSSE2]>;
2066 // Convert packed double to packed single
2067 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2068 // register, but the same isn't true when using memory operands instead.
2069 // Provide other assembly rr and rm forms to address this explicitly.
2070 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2071 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2072 IIC_SSE_CVT_PD_RR>, VEX;
2073 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2074 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2075 IIC_SSE_CVT_PD_RR>, VEX;
2078 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2079 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2080 IIC_SSE_CVT_PD_RR>, VEX;
2081 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2082 "cvtpd2psx\t{$src, $dst|$dst, $src}", [],
2083 IIC_SSE_CVT_PD_RM>, VEX;
2086 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2087 "cvtpd2psy\t{$src, $dst|$dst, $src}", [],
2088 IIC_SSE_CVT_PD_RR>, VEX;
2089 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2090 "cvtpd2psy\t{$src, $dst|$dst, $src}", [],
2091 IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
2092 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2093 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2095 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2096 "cvtpd2ps\t{$src, $dst|$dst, $src}", [],
2100 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2101 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2102 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2104 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
2106 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2107 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2108 (memop addr:$src)))],
2110 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2111 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2112 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2114 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2115 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2116 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
2117 (memop addr:$src)))],
2120 // AVX 256-bit register conversion intrinsics
2121 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2122 // whenever possible to avoid declaring two versions of each one.
2123 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2124 (VCVTDQ2PSYrr VR256:$src)>;
2125 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (memopv4i64 addr:$src))),
2126 (VCVTDQ2PSYrm addr:$src)>;
2128 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
2129 (VCVTPD2PSYrr VR256:$src)>;
2130 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
2131 (VCVTPD2PSYrm addr:$src)>;
2133 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
2134 (VCVTPS2DQYrr VR256:$src)>;
2135 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
2136 (VCVTPS2DQYrm addr:$src)>;
2138 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
2139 (VCVTPS2PDYrr VR128:$src)>;
2140 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
2141 (VCVTPS2PDYrm addr:$src)>;
2143 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
2144 (VCVTTPD2DQYrr VR256:$src)>;
2145 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
2146 (VCVTTPD2DQYrm addr:$src)>;
2148 // Match fround and fextend for 128/256-bit conversions
2149 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2150 (VCVTPD2PSYrr VR256:$src)>;
2151 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2152 (VCVTPD2PSYrm addr:$src)>;
2154 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2155 (VCVTPS2PDYrr VR128:$src)>;
2156 def : Pat<(v4f64 (fextend (loadv4f32 addr:$src))),
2157 (VCVTPS2PDYrm addr:$src)>;
2159 //===----------------------------------------------------------------------===//
2160 // SSE 1 & 2 - Compare Instructions
2161 //===----------------------------------------------------------------------===//
2163 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2164 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2165 Operand CC, SDNode OpNode, ValueType VT,
2166 PatFrag ld_frag, string asm, string asm_alt,
2168 def rr : SIi8<0xC2, MRMSrcReg,
2169 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2170 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
2172 def rm : SIi8<0xC2, MRMSrcMem,
2173 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2174 [(set RC:$dst, (OpNode (VT RC:$src1),
2175 (ld_frag addr:$src2), imm:$cc))],
2178 // Accept explicit immediate argument form instead of comparison code.
2179 let neverHasSideEffects = 1 in {
2180 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2181 (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
2182 IIC_SSE_ALU_F32S_RR>;
2184 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2185 (ins RC:$src1, x86memop:$src2, i8imm:$cc), asm_alt, [],
2186 IIC_SSE_ALU_F32S_RM>;
2190 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmpss, f32, loadf32,
2191 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2192 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2194 XS, VEX_4V, VEX_LIG;
2195 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmpsd, f64, loadf64,
2196 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2197 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2198 SSE_ALU_F32S>, // same latency as 32 bit compare
2199 XD, VEX_4V, VEX_LIG;
2201 let Constraints = "$src1 = $dst" in {
2202 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmpss, f32, loadf32,
2203 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2204 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
2206 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmpsd, f64, loadf64,
2207 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2208 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2209 SSE_ALU_F32S>, // same latency as 32 bit compare
2213 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2214 Intrinsic Int, string asm, OpndItins itins> {
2215 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2216 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2217 [(set VR128:$dst, (Int VR128:$src1,
2218 VR128:$src, imm:$cc))],
2220 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2221 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2222 [(set VR128:$dst, (Int VR128:$src1,
2223 (load addr:$src), imm:$cc))],
2227 // Aliases to match intrinsics which expect XMM operand(s).
2228 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2229 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2232 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2233 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2234 SSE_ALU_F32S>, // same latency as f32
2236 let Constraints = "$src1 = $dst" in {
2237 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2238 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2240 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2241 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2242 SSE_ALU_F32S>, // same latency as f32
2247 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2248 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2249 ValueType vt, X86MemOperand x86memop,
2250 PatFrag ld_frag, string OpcodeStr, Domain d> {
2251 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2252 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2253 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2254 IIC_SSE_COMIS_RR, d>;
2255 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2256 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2257 [(set EFLAGS, (OpNode (vt RC:$src1),
2258 (ld_frag addr:$src2)))],
2259 IIC_SSE_COMIS_RM, d>;
2262 let Defs = [EFLAGS] in {
2263 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2264 "ucomiss", SSEPackedSingle>, TB, VEX, VEX_LIG;
2265 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2266 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
2268 let Pattern = []<dag> in {
2269 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2270 "comiss", SSEPackedSingle>, TB, VEX,
2272 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2273 "comisd", SSEPackedDouble>, TB, OpSize, VEX,
2277 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2278 load, "ucomiss", SSEPackedSingle>, TB, VEX;
2279 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2280 load, "ucomisd", SSEPackedDouble>, TB, OpSize, VEX;
2282 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2283 load, "comiss", SSEPackedSingle>, TB, VEX;
2284 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2285 load, "comisd", SSEPackedDouble>, TB, OpSize, VEX;
2286 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2287 "ucomiss", SSEPackedSingle>, TB;
2288 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2289 "ucomisd", SSEPackedDouble>, TB, OpSize;
2291 let Pattern = []<dag> in {
2292 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2293 "comiss", SSEPackedSingle>, TB;
2294 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2295 "comisd", SSEPackedDouble>, TB, OpSize;
2298 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2299 load, "ucomiss", SSEPackedSingle>, TB;
2300 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2301 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
2303 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2304 "comiss", SSEPackedSingle>, TB;
2305 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2306 "comisd", SSEPackedDouble>, TB, OpSize;
2307 } // Defs = [EFLAGS]
2309 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2310 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2311 Operand CC, Intrinsic Int, string asm,
2312 string asm_alt, Domain d> {
2313 def rri : PIi8<0xC2, MRMSrcReg,
2314 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2315 [(set RC:$dst, (Int RC:$src1, RC:$src2, imm:$cc))],
2316 IIC_SSE_CMPP_RR, d>;
2317 def rmi : PIi8<0xC2, MRMSrcMem,
2318 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2319 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2), imm:$cc))],
2320 IIC_SSE_CMPP_RM, d>;
2322 // Accept explicit immediate argument form instead of comparison code.
2323 let neverHasSideEffects = 1 in {
2324 def rri_alt : PIi8<0xC2, MRMSrcReg,
2325 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
2326 asm_alt, [], IIC_SSE_CMPP_RR, d>;
2327 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2328 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
2329 asm_alt, [], IIC_SSE_CMPP_RM, d>;
2333 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2334 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2335 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2336 SSEPackedSingle>, TB, VEX_4V;
2337 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2338 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2339 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2340 SSEPackedDouble>, TB, OpSize, VEX_4V;
2341 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2342 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2343 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2344 SSEPackedSingle>, TB, VEX_4V;
2345 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2346 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2347 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2348 SSEPackedDouble>, TB, OpSize, VEX_4V;
2349 let Constraints = "$src1 = $dst" in {
2350 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2351 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2352 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2353 SSEPackedSingle>, TB;
2354 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2355 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2356 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2357 SSEPackedDouble>, TB, OpSize;
2360 let Predicates = [HasAVX] in {
2361 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2362 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2363 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2364 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2365 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2366 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2367 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2368 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2370 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2371 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2372 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (memop addr:$src2), imm:$cc)),
2373 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2374 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2375 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2376 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (memop addr:$src2), imm:$cc)),
2377 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2380 let Predicates = [HasSSE1] in {
2381 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2382 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2383 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
2384 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2387 let Predicates = [HasSSE2] in {
2388 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2389 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2390 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
2391 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2394 //===----------------------------------------------------------------------===//
2395 // SSE 1 & 2 - Shuffle Instructions
2396 //===----------------------------------------------------------------------===//
2398 /// sse12_shuffle - sse 1 & 2 shuffle instructions
2399 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2400 ValueType vt, string asm, PatFrag mem_frag,
2401 Domain d, bit IsConvertibleToThreeAddress = 0> {
2402 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2403 (ins RC:$src1, x86memop:$src2, i8imm:$src3), asm,
2404 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2405 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2406 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
2407 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2408 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
2409 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2410 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>;
2413 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2414 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2415 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
2416 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2417 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2418 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
2419 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2420 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2421 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2422 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2423 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
2424 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
2426 let Constraints = "$src1 = $dst" in {
2427 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2428 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2429 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
2431 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2432 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2433 memopv2f64, SSEPackedDouble, 1 /* cvt to pshufd */>,
2437 let Predicates = [HasAVX] in {
2438 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2439 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2440 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2441 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2442 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2444 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2445 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2446 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2447 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2448 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2451 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2452 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2453 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2454 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
2455 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2457 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2458 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2459 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2460 (memopv4i64 addr:$src2), (i8 imm:$imm))),
2461 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2464 let Predicates = [HasSSE1] in {
2465 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2466 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2467 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2468 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2469 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2472 let Predicates = [HasSSE2] in {
2473 // Generic SHUFPD patterns
2474 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2475 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2476 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2477 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2478 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2481 //===----------------------------------------------------------------------===//
2482 // SSE 1 & 2 - Unpack Instructions
2483 //===----------------------------------------------------------------------===//
2485 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
2486 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2487 PatFrag mem_frag, RegisterClass RC,
2488 X86MemOperand x86memop, string asm,
2490 def rr : PI<opc, MRMSrcReg,
2491 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2493 (vt (OpNode RC:$src1, RC:$src2)))],
2495 def rm : PI<opc, MRMSrcMem,
2496 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2498 (vt (OpNode RC:$src1,
2499 (mem_frag addr:$src2))))],
2503 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2504 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2505 SSEPackedSingle>, TB, VEX_4V;
2506 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2507 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2508 SSEPackedDouble>, TB, OpSize, VEX_4V;
2509 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2510 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2511 SSEPackedSingle>, TB, VEX_4V;
2512 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2513 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2514 SSEPackedDouble>, TB, OpSize, VEX_4V;
2516 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
2517 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2518 SSEPackedSingle>, TB, VEX_4V;
2519 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
2520 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 SSEPackedDouble>, TB, OpSize, VEX_4V;
2522 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
2523 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 SSEPackedSingle>, TB, VEX_4V;
2525 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
2526 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2527 SSEPackedDouble>, TB, OpSize, VEX_4V;
2529 let Constraints = "$src1 = $dst" in {
2530 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2531 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2532 SSEPackedSingle>, TB;
2533 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2534 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2535 SSEPackedDouble>, TB, OpSize;
2536 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2537 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2538 SSEPackedSingle>, TB;
2539 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2540 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2541 SSEPackedDouble>, TB, OpSize;
2542 } // Constraints = "$src1 = $dst"
2544 let Predicates = [HasAVX], AddedComplexity = 1 in {
2545 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2546 // problem is during lowering, where it's not possible to recognize the load
2547 // fold cause it has two uses through a bitcast. One use disappears at isel
2548 // time and the fold opportunity reappears.
2549 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2550 (VUNPCKLPDrr VR128:$src, VR128:$src)>;
2553 let Predicates = [HasSSE2] in {
2554 // FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
2555 // problem is during lowering, where it's not possible to recognize the load
2556 // fold cause it has two uses through a bitcast. One use disappears at isel
2557 // time and the fold opportunity reappears.
2558 def : Pat<(v2f64 (X86Movddup VR128:$src)),
2559 (UNPCKLPDrr VR128:$src, VR128:$src)>;
2562 //===----------------------------------------------------------------------===//
2563 // SSE 1 & 2 - Extract Floating-Point Sign mask
2564 //===----------------------------------------------------------------------===//
2566 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2567 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2569 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
2570 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2571 [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>;
2572 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
2573 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],
2574 IIC_SSE_MOVMSK, d>, REX_W;
2577 let Predicates = [HasAVX] in {
2578 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2579 "movmskps", SSEPackedSingle>, TB, VEX;
2580 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2581 "movmskpd", SSEPackedDouble>, TB,
2583 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2584 "movmskps", SSEPackedSingle>, TB, VEX;
2585 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2586 "movmskpd", SSEPackedDouble>, TB,
2589 def : Pat<(i32 (X86fgetsign FR32:$src)),
2590 (VMOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2592 def : Pat<(i64 (X86fgetsign FR32:$src)),
2593 (VMOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2595 def : Pat<(i32 (X86fgetsign FR64:$src)),
2596 (VMOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2598 def : Pat<(i64 (X86fgetsign FR64:$src)),
2599 (VMOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2603 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2604 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2605 SSEPackedSingle>, TB, VEX;
2606 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2607 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2608 SSEPackedDouble>, TB,
2610 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2611 "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2612 SSEPackedSingle>, TB, VEX;
2613 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
2614 "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
2615 SSEPackedDouble>, TB,
2619 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2620 SSEPackedSingle>, TB;
2621 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2622 SSEPackedDouble>, TB, OpSize;
2624 def : Pat<(i32 (X86fgetsign FR32:$src)),
2625 (MOVMSKPSrr32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2626 sub_ss))>, Requires<[HasSSE1]>;
2627 def : Pat<(i64 (X86fgetsign FR32:$src)),
2628 (MOVMSKPSrr64 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src,
2629 sub_ss))>, Requires<[HasSSE1]>;
2630 def : Pat<(i32 (X86fgetsign FR64:$src)),
2631 (MOVMSKPDrr32 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2632 sub_sd))>, Requires<[HasSSE2]>;
2633 def : Pat<(i64 (X86fgetsign FR64:$src)),
2634 (MOVMSKPDrr64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src,
2635 sub_sd))>, Requires<[HasSSE2]>;
2637 //===---------------------------------------------------------------------===//
2638 // SSE2 - Packed Integer Logical Instructions
2639 //===---------------------------------------------------------------------===//
2641 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2643 /// PDI_binop_rm - Simple SSE2 binary operator.
2644 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2645 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2646 X86MemOperand x86memop,
2648 bit IsCommutable = 0,
2650 let isCommutable = IsCommutable in
2651 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2652 (ins RC:$src1, RC:$src2),
2654 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2655 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2656 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>;
2657 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2658 (ins RC:$src1, x86memop:$src2),
2660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2661 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2662 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2663 (bitconvert (memop_frag addr:$src2)))))],
2666 } // ExeDomain = SSEPackedInt
2668 // These are ordered here for pattern ordering requirements with the fp versions
2670 let Predicates = [HasAVX] in {
2671 defm VPAND : PDI_binop_rm<0xDB, "vpand", and, v2i64, VR128, memopv2i64,
2672 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2673 defm VPOR : PDI_binop_rm<0xEB, "vpor" , or, v2i64, VR128, memopv2i64,
2674 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2675 defm VPXOR : PDI_binop_rm<0xEF, "vpxor", xor, v2i64, VR128, memopv2i64,
2676 i128mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2677 defm VPANDN : PDI_binop_rm<0xDF, "vpandn", X86andnp, v2i64, VR128, memopv2i64,
2678 i128mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2681 let Constraints = "$src1 = $dst" in {
2682 defm PAND : PDI_binop_rm<0xDB, "pand", and, v2i64, VR128, memopv2i64,
2683 i128mem, SSE_BIT_ITINS_P, 1>;
2684 defm POR : PDI_binop_rm<0xEB, "por" , or, v2i64, VR128, memopv2i64,
2685 i128mem, SSE_BIT_ITINS_P, 1>;
2686 defm PXOR : PDI_binop_rm<0xEF, "pxor", xor, v2i64, VR128, memopv2i64,
2687 i128mem, SSE_BIT_ITINS_P, 1>;
2688 defm PANDN : PDI_binop_rm<0xDF, "pandn", X86andnp, v2i64, VR128, memopv2i64,
2689 i128mem, SSE_BIT_ITINS_P, 0>;
2690 } // Constraints = "$src1 = $dst"
2692 let Predicates = [HasAVX2] in {
2693 defm VPANDY : PDI_binop_rm<0xDB, "vpand", and, v4i64, VR256, memopv4i64,
2694 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2695 defm VPORY : PDI_binop_rm<0xEB, "vpor", or, v4i64, VR256, memopv4i64,
2696 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2697 defm VPXORY : PDI_binop_rm<0xEF, "vpxor", xor, v4i64, VR256, memopv4i64,
2698 i256mem, SSE_BIT_ITINS_P, 1, 0>, VEX_4V;
2699 defm VPANDNY : PDI_binop_rm<0xDF, "vpandn", X86andnp, v4i64, VR256, memopv4i64,
2700 i256mem, SSE_BIT_ITINS_P, 0, 0>, VEX_4V;
2703 //===----------------------------------------------------------------------===//
2704 // SSE 1 & 2 - Logical Instructions
2705 //===----------------------------------------------------------------------===//
2707 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
2709 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
2710 SDNode OpNode, OpndItins itins> {
2711 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2712 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, itins, 0>,
2715 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2716 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, itins, 0>,
2719 let Constraints = "$src1 = $dst" in {
2720 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2721 f32, f128mem, memopfsf32, SSEPackedSingle, itins>,
2724 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2725 f64, f128mem, memopfsf64, SSEPackedDouble, itins>,
2730 // Alias bitwise logical operations using SSE logical ops on packed FP values.
2731 let mayLoad = 0 in {
2732 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand,
2734 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for,
2736 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor,
2740 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
2741 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef,
2744 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2746 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2748 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2749 // are all promoted to v2i64, and the patterns are covered by the int
2750 // version. This is needed in SSE only, because v2i64 isn't supported on
2751 // SSE1, but only on SSE2.
2752 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2753 !strconcat(OpcodeStr, "ps"), f128mem, [],
2754 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2755 (memopv2i64 addr:$src2)))], 0, 1>, TB, VEX_4V;
2757 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2758 !strconcat(OpcodeStr, "pd"), f128mem,
2759 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2760 (bc_v2i64 (v2f64 VR128:$src2))))],
2761 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2762 (memopv2i64 addr:$src2)))], 0>,
2764 let Constraints = "$src1 = $dst" in {
2765 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2766 !strconcat(OpcodeStr, "ps"), f128mem,
2767 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2768 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2769 (memopv2i64 addr:$src2)))]>, TB;
2771 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2772 !strconcat(OpcodeStr, "pd"), f128mem,
2773 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2774 (bc_v2i64 (v2f64 VR128:$src2))))],
2775 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2776 (memopv2i64 addr:$src2)))]>, TB, OpSize;
2780 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
2782 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr,
2784 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2785 !strconcat(OpcodeStr, "ps"), f256mem,
2786 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2787 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2788 (memopv4i64 addr:$src2)))], 0>, TB, VEX_4V;
2790 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2791 !strconcat(OpcodeStr, "pd"), f256mem,
2792 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2793 (bc_v4i64 (v4f64 VR256:$src2))))],
2794 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2795 (memopv4i64 addr:$src2)))], 0>,
2799 // AVX 256-bit packed logical ops forms
2800 defm VAND : sse12_fp_packed_logical_y<0x54, "and", and>;
2801 defm VOR : sse12_fp_packed_logical_y<0x56, "or", or>;
2802 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor", xor>;
2803 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn", X86andnp>;
2805 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2806 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2807 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2808 let isCommutable = 0 in
2809 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2811 //===----------------------------------------------------------------------===//
2812 // SSE 1 & 2 - Arithmetic Instructions
2813 //===----------------------------------------------------------------------===//
2815 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
2818 /// In addition, we also have a special variant of the scalar form here to
2819 /// represent the associated intrinsic operation. This form is unlike the
2820 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
2821 /// and leaves the top elements unmodified (therefore these cannot be commuted).
2823 /// These three forms can each be reg+reg or reg+mem.
2826 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
2828 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2831 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
2832 OpNode, FR32, f32mem,
2833 itins.s, Is2Addr>, XS;
2834 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
2835 OpNode, FR64, f64mem,
2836 itins.d, Is2Addr>, XD;
2839 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
2842 let mayLoad = 0 in {
2843 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2844 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins.s, Is2Addr>,
2846 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2847 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins.d, Is2Addr>,
2852 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
2855 let mayLoad = 0 in {
2856 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
2857 v8f32, f256mem, memopv8f32, SSEPackedSingle, itins.s, 0>,
2859 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
2860 v4f64, f256mem, memopv4f64, SSEPackedDouble, itins.d, 0>,
2865 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
2868 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2869 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
2870 itins.s, Is2Addr>, XS;
2871 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
2872 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
2873 itins.d, Is2Addr>, XD;
2876 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
2879 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2880 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
2881 SSEPackedSingle, itins.s, Is2Addr>,
2884 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
2885 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
2886 SSEPackedDouble, itins.d, Is2Addr>,
2890 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr,
2892 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2893 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
2894 SSEPackedSingle, itins.s, 0>, TB;
2896 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
2897 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
2898 SSEPackedDouble, itins.d, 0>, TB, OpSize;
2901 // Binary Arithmetic instructions
2902 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S, 0>,
2903 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S, 0>,
2905 defm VADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P, 0>,
2906 basic_sse12_fp_binop_p_y<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2908 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S, 0>,
2909 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S, 0>,
2911 defm VMUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P, 0>,
2912 basic_sse12_fp_binop_p_y<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2915 let isCommutable = 0 in {
2916 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S, 0>,
2917 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S, 0>,
2919 defm VSUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P, 0>,
2920 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub, SSE_ALU_ITINS_P>, VEX_4V;
2921 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S, 0>,
2922 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S, 0>,
2924 defm VDIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_ALU_ITINS_P, 0>,
2925 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2927 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S, 0>,
2928 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S, 0>,
2930 defm VMAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P, 0>,
2931 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P, 0>,
2932 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2933 basic_sse12_fp_binop_p_y_int<0x5F, "max", SSE_ALU_ITINS_P>,
2935 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S, 0>,
2936 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S, 0>,
2938 defm VMIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P, 0>,
2939 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P, 0>,
2940 basic_sse12_fp_binop_p_y_int<0x5D, "min", SSE_ALU_ITINS_P>,
2941 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2945 let Constraints = "$src1 = $dst" in {
2946 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
2947 basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
2948 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
2949 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
2950 basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
2951 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
2953 let isCommutable = 0 in {
2954 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
2955 basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
2956 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
2957 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
2958 basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
2959 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
2960 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
2961 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
2962 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>,
2963 basic_sse12_fp_binop_p_int<0x5F, "max", SSE_ALU_ITINS_P>;
2964 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
2965 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
2966 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>,
2967 basic_sse12_fp_binop_p_int<0x5D, "min", SSE_ALU_ITINS_P>;
2972 /// In addition, we also have a special variant of the scalar form here to
2973 /// represent the associated intrinsic operation. This form is unlike the
2974 /// plain scalar form, in that it takes an entire vector (instead of a
2975 /// scalar) and leaves the top elements undefined.
2977 /// And, we have a special variant form for a full-vector intrinsic form.
2979 def SSE_SQRTP : OpndItins<
2980 IIC_SSE_SQRTP_RR, IIC_SSE_SQRTP_RM
2983 def SSE_SQRTS : OpndItins<
2984 IIC_SSE_SQRTS_RR, IIC_SSE_SQRTS_RM
2987 def SSE_RCPP : OpndItins<
2988 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
2991 def SSE_RCPS : OpndItins<
2992 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
2995 /// sse1_fp_unop_s - SSE1 unops in scalar form.
2996 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
2997 SDNode OpNode, Intrinsic F32Int, OpndItins itins> {
2998 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
2999 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3000 [(set FR32:$dst, (OpNode FR32:$src))]>;
3001 // For scalar unary operations, fold a load into the operation
3002 // only in OptForSize mode. It eliminates an instruction, but it also
3003 // eliminates a whole-register clobber (the load), so it introduces a
3004 // partial register update condition.
3005 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
3006 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3007 [(set FR32:$dst, (OpNode (load addr:$src)))], itins.rm>, XS,
3008 Requires<[HasSSE1, OptForSize]>;
3009 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3010 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3011 [(set VR128:$dst, (F32Int VR128:$src))], itins.rr>;
3012 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
3013 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
3014 [(set VR128:$dst, (F32Int sse_load_f32:$src))], itins.rm>;
3017 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
3018 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3019 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
3020 !strconcat(OpcodeStr,
3021 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3023 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1,f32mem:$src2),
3024 !strconcat(OpcodeStr,
3025 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3026 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
3027 (ins VR128:$src1, ssmem:$src2),
3028 !strconcat(OpcodeStr,
3029 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3032 /// sse1_fp_unop_p - SSE1 unops in packed form.
3033 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3035 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3036 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3037 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>;
3038 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3039 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3040 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>;
3043 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
3044 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3046 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3047 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3048 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3050 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3051 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3052 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))],
3056 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3057 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3058 Intrinsic V4F32Int, OpndItins itins> {
3059 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3060 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3061 [(set VR128:$dst, (V4F32Int VR128:$src))],
3063 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3064 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3065 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3069 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
3070 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3071 Intrinsic V4F32Int, OpndItins itins> {
3072 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3073 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3074 [(set VR256:$dst, (V4F32Int VR256:$src))],
3076 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3077 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3078 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))],
3082 /// sse2_fp_unop_s - SSE2 unops in scalar form.
3083 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
3084 SDNode OpNode, Intrinsic F64Int, OpndItins itins> {
3085 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
3086 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3087 [(set FR64:$dst, (OpNode FR64:$src))], itins.rr>;
3088 // See the comments in sse1_fp_unop_s for why this is OptForSize.
3089 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
3090 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3091 [(set FR64:$dst, (OpNode (load addr:$src)))], itins.rm>, XD,
3092 Requires<[HasSSE2, OptForSize]>;
3093 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3094 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3095 [(set VR128:$dst, (F64Int VR128:$src))], itins.rr>;
3096 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
3097 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
3098 [(set VR128:$dst, (F64Int sse_load_f64:$src))], itins.rm>;
3101 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
3102 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr> {
3103 let neverHasSideEffects = 1 in {
3104 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
3105 !strconcat(OpcodeStr,
3106 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3108 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1,f64mem:$src2),
3109 !strconcat(OpcodeStr,
3110 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3112 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
3113 (ins VR128:$src1, sdmem:$src2),
3114 !strconcat(OpcodeStr,
3115 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
3118 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3119 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3120 SDNode OpNode, OpndItins itins> {
3121 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3122 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3123 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>;
3124 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3125 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3126 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>;
3129 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
3130 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode,
3132 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3133 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3134 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3136 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3137 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3138 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))],
3142 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
3143 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3144 Intrinsic V2F64Int, OpndItins itins> {
3145 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3146 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3147 [(set VR128:$dst, (V2F64Int VR128:$src))],
3149 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3150 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3151 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))],
3155 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
3156 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
3157 Intrinsic V2F64Int, OpndItins itins> {
3158 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3159 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3160 [(set VR256:$dst, (V2F64Int VR256:$src))],
3162 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3163 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3164 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))],
3168 let Predicates = [HasAVX] in {
3170 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt">,
3171 sse2_fp_unop_s_avx<0x51, "vsqrt">, VEX_4V, VEX_LIG;
3173 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3174 sse2_fp_unop_p<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3175 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3176 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt, SSE_SQRTP>,
3177 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps,
3179 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd,
3181 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256,
3183 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256,
3187 // Reciprocal approximations. Note that these typically require refinement
3188 // in order to obtain suitable precision.
3189 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt">, VEX_4V, VEX_LIG;
3190 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3191 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt, SSE_SQRTP>,
3192 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256,
3194 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps,
3197 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp">, VEX_4V, VEX_LIG;
3198 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp, SSE_RCPP>,
3199 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp, SSE_RCPP>,
3200 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256,
3202 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps,
3206 let AddedComplexity = 1 in {
3207 def : Pat<(f32 (fsqrt FR32:$src)),
3208 (VSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3209 def : Pat<(f32 (fsqrt (load addr:$src))),
3210 (VSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3211 Requires<[HasAVX, OptForSize]>;
3212 def : Pat<(f64 (fsqrt FR64:$src)),
3213 (VSQRTSDr (f64 (IMPLICIT_DEF)), FR64:$src)>, Requires<[HasAVX]>;
3214 def : Pat<(f64 (fsqrt (load addr:$src))),
3215 (VSQRTSDm (f64 (IMPLICIT_DEF)), addr:$src)>,
3216 Requires<[HasAVX, OptForSize]>;
3218 def : Pat<(f32 (X86frsqrt FR32:$src)),
3219 (VRSQRTSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3220 def : Pat<(f32 (X86frsqrt (load addr:$src))),
3221 (VRSQRTSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3222 Requires<[HasAVX, OptForSize]>;
3224 def : Pat<(f32 (X86frcp FR32:$src)),
3225 (VRCPSSr (f32 (IMPLICIT_DEF)), FR32:$src)>, Requires<[HasAVX]>;
3226 def : Pat<(f32 (X86frcp (load addr:$src))),
3227 (VRCPSSm (f32 (IMPLICIT_DEF)), addr:$src)>,
3228 Requires<[HasAVX, OptForSize]>;
3231 let Predicates = [HasAVX], AddedComplexity = 1 in {
3232 def : Pat<(int_x86_sse_sqrt_ss VR128:$src),
3233 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3234 (VSQRTSSr (f32 (IMPLICIT_DEF)),
3235 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3237 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
3238 (VSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3240 def : Pat<(int_x86_sse2_sqrt_sd VR128:$src),
3241 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)),
3242 (VSQRTSDr (f64 (IMPLICIT_DEF)),
3243 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd)),
3245 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
3246 (VSQRTSDm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
3248 def : Pat<(int_x86_sse_rsqrt_ss VR128:$src),
3249 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3250 (VRSQRTSSr (f32 (IMPLICIT_DEF)),
3251 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3253 def : Pat<(int_x86_sse_rsqrt_ss sse_load_f32:$src),
3254 (VRSQRTSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3256 def : Pat<(int_x86_sse_rcp_ss VR128:$src),
3257 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)),
3258 (VRCPSSr (f32 (IMPLICIT_DEF)),
3259 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)),
3261 def : Pat<(int_x86_sse_rcp_ss sse_load_f32:$src),
3262 (VRCPSSm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
3266 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss,
3268 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3269 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps, SSE_SQRTS>,
3270 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd,
3272 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTS>,
3273 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd, SSE_SQRTS>;
3275 // Reciprocal approximations. Note that these typically require refinement
3276 // in order to obtain suitable precision.
3277 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss,
3279 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_SQRTS>,
3280 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3282 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss,
3284 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPS>,
3285 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps, SSE_RCPS>;
3287 // There is no f64 version of the reciprocal approximation instructions.
3289 //===----------------------------------------------------------------------===//
3290 // SSE 1 & 2 - Non-temporal stores
3291 //===----------------------------------------------------------------------===//
3293 let AddedComplexity = 400 in { // Prefer non-temporal versions
3294 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3295 (ins f128mem:$dst, VR128:$src),
3296 "movntps\t{$src, $dst|$dst, $src}",
3297 [(alignednontemporalstore (v4f32 VR128:$src),
3299 IIC_SSE_MOVNT>, VEX;
3300 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3301 (ins f128mem:$dst, VR128:$src),
3302 "movntpd\t{$src, $dst|$dst, $src}",
3303 [(alignednontemporalstore (v2f64 VR128:$src),
3305 IIC_SSE_MOVNT>, VEX;
3307 let ExeDomain = SSEPackedInt in
3308 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3309 (ins f128mem:$dst, VR128:$src),
3310 "movntdq\t{$src, $dst|$dst, $src}",
3311 [(alignednontemporalstore (v2i64 VR128:$src),
3313 IIC_SSE_MOVNT>, VEX;
3315 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3316 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
3318 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3319 (ins f256mem:$dst, VR256:$src),
3320 "movntps\t{$src, $dst|$dst, $src}",
3321 [(alignednontemporalstore (v8f32 VR256:$src),
3323 IIC_SSE_MOVNT>, VEX;
3324 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3325 (ins f256mem:$dst, VR256:$src),
3326 "movntpd\t{$src, $dst|$dst, $src}",
3327 [(alignednontemporalstore (v4f64 VR256:$src),
3329 IIC_SSE_MOVNT>, VEX;
3330 let ExeDomain = SSEPackedInt in
3331 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3332 (ins f256mem:$dst, VR256:$src),
3333 "movntdq\t{$src, $dst|$dst, $src}",
3334 [(alignednontemporalstore (v4i64 VR256:$src),
3336 IIC_SSE_MOVNT>, VEX;
3339 let AddedComplexity = 400 in { // Prefer non-temporal versions
3340 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3341 "movntps\t{$src, $dst|$dst, $src}",
3342 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3344 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3345 "movntpd\t{$src, $dst|$dst, $src}",
3346 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3349 let ExeDomain = SSEPackedInt in
3350 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3351 "movntdq\t{$src, $dst|$dst, $src}",
3352 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3355 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
3356 (MOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3358 // There is no AVX form for instructions below this point
3359 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3360 "movnti{l}\t{$src, $dst|$dst, $src}",
3361 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3363 TB, Requires<[HasSSE2]>;
3364 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3365 "movnti{q}\t{$src, $dst|$dst, $src}",
3366 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3368 TB, Requires<[HasSSE2]>;
3371 //===----------------------------------------------------------------------===//
3372 // SSE 1 & 2 - Prefetch and memory fence
3373 //===----------------------------------------------------------------------===//
3375 // Prefetch intrinsic.
3376 let Predicates = [HasSSE1] in {
3377 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3378 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3379 IIC_SSE_PREFETCH>, TB;
3380 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3381 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3382 IIC_SSE_PREFETCH>, TB;
3383 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3384 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3385 IIC_SSE_PREFETCH>, TB;
3386 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3387 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3388 IIC_SSE_PREFETCH>, TB;
3392 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3393 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3394 IIC_SSE_PREFETCH>, TB, Requires<[HasSSE2]>;
3396 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3397 // was introduced with SSE2, it's backward compatible.
3398 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", [], IIC_SSE_PAUSE>, REP;
3400 // Load, store, and memory fence
3401 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3402 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3403 TB, Requires<[HasSSE1]>;
3404 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3405 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3406 TB, Requires<[HasSSE2]>;
3407 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3408 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3409 TB, Requires<[HasSSE2]>;
3411 def : Pat<(X86SFence), (SFENCE)>;
3412 def : Pat<(X86LFence), (LFENCE)>;
3413 def : Pat<(X86MFence), (MFENCE)>;
3415 //===----------------------------------------------------------------------===//
3416 // SSE 1 & 2 - Load/Store XCSR register
3417 //===----------------------------------------------------------------------===//
3419 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3420 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3421 IIC_SSE_LDMXCSR>, VEX;
3422 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3423 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3424 IIC_SSE_STMXCSR>, VEX;
3426 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3427 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3429 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3430 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3433 //===---------------------------------------------------------------------===//
3434 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3435 //===---------------------------------------------------------------------===//
3437 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3439 let neverHasSideEffects = 1 in {
3440 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3441 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3443 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3444 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3447 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3448 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3450 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3451 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3455 let isCodeGenOnly = 1 in {
3456 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3457 "movdqa\t{$src, $dst|$dst, $src}", [],
3460 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3461 "movdqa\t{$src, $dst|$dst, $src}", [],
3464 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3465 "movdqu\t{$src, $dst|$dst, $src}", [],
3468 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3469 "movdqu\t{$src, $dst|$dst, $src}", [],
3474 let canFoldAsLoad = 1, mayLoad = 1 in {
3475 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3476 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3478 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3479 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3481 let Predicates = [HasAVX] in {
3482 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3483 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3485 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3486 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3491 let mayStore = 1 in {
3492 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3493 (ins i128mem:$dst, VR128:$src),
3494 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3496 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3497 (ins i256mem:$dst, VR256:$src),
3498 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3500 let Predicates = [HasAVX] in {
3501 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3502 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3504 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3505 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3510 let neverHasSideEffects = 1 in
3511 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3512 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3514 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3515 "movdqu\t{$src, $dst|$dst, $src}",
3516 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3519 let isCodeGenOnly = 1 in {
3520 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3521 "movdqa\t{$src, $dst|$dst, $src}", [],
3524 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3525 "movdqu\t{$src, $dst|$dst, $src}",
3526 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[HasSSE2]>;
3529 let canFoldAsLoad = 1, mayLoad = 1 in {
3530 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3531 "movdqa\t{$src, $dst|$dst, $src}",
3532 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3534 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3535 "movdqu\t{$src, $dst|$dst, $src}",
3536 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3538 XS, Requires<[HasSSE2]>;
3541 let mayStore = 1 in {
3542 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3543 "movdqa\t{$src, $dst|$dst, $src}",
3544 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3546 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3547 "movdqu\t{$src, $dst|$dst, $src}",
3548 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3550 XS, Requires<[HasSSE2]>;
3553 // Intrinsic forms of MOVDQU load and store
3554 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3555 "vmovdqu\t{$src, $dst|$dst, $src}",
3556 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3558 XS, VEX, Requires<[HasAVX]>;
3560 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3561 "movdqu\t{$src, $dst|$dst, $src}",
3562 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)],
3564 XS, Requires<[HasSSE2]>;
3566 } // ExeDomain = SSEPackedInt
3568 let Predicates = [HasAVX] in {
3569 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3570 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3573 //===---------------------------------------------------------------------===//
3574 // SSE2 - Packed Integer Arithmetic Instructions
3575 //===---------------------------------------------------------------------===//
3577 def SSE_PMADD : OpndItins<
3578 IIC_SSE_PMADD, IIC_SSE_PMADD
3581 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3583 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3584 RegisterClass RC, PatFrag memop_frag,
3585 X86MemOperand x86memop,
3587 bit IsCommutable = 0,
3589 let isCommutable = IsCommutable in
3590 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3591 (ins RC:$src1, RC:$src2),
3593 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3594 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3595 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>;
3596 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3597 (ins RC:$src1, x86memop:$src2),
3599 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3600 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3601 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3605 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3606 string OpcodeStr, SDNode OpNode,
3607 SDNode OpNode2, RegisterClass RC,
3608 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3609 ShiftOpndItins itins,
3611 // src2 is always 128-bit
3612 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3613 (ins RC:$src1, VR128:$src2),
3615 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3617 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3619 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3620 (ins RC:$src1, i128mem:$src2),
3622 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3623 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3624 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3625 (bc_frag (memopv2i64 addr:$src2)))))], itins.rm>;
3626 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3627 (ins RC:$src1, i32i8imm:$src2),
3629 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3630 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3631 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i32 imm:$src2))))], itins.ri>;
3634 /// PDI_binop_rm - Simple SSE2 binary operator with different src and dst types
3635 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3636 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3637 PatFrag memop_frag, X86MemOperand x86memop,
3639 bit IsCommutable = 0, bit Is2Addr = 1> {
3640 let isCommutable = IsCommutable in
3641 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3642 (ins RC:$src1, RC:$src2),
3644 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3645 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3646 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>;
3647 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3648 (ins RC:$src1, x86memop:$src2),
3650 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3651 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3652 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
3653 (bitconvert (memop_frag addr:$src2)))))]>;
3655 } // ExeDomain = SSEPackedInt
3657 // 128-bit Integer Arithmetic
3659 let Predicates = [HasAVX] in {
3660 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, VR128, memopv2i64,
3661 i128mem, SSE_INTALU_ITINS_P, 1, 0 /*3addr*/>,
3663 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, VR128, memopv2i64,
3664 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3665 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, VR128, memopv2i64,
3666 i128mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3667 defm VPADDQ : PDI_binop_rm<0xD4, "vpaddq", add, v2i64, VR128, memopv2i64,
3668 i128mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3669 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, VR128, memopv2i64,
3670 i128mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3671 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, VR128, memopv2i64,
3672 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3673 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, VR128, memopv2i64,
3674 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3675 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, VR128, memopv2i64,
3676 i128mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3677 defm VPSUBQ : PDI_binop_rm<0xFB, "vpsubq", sub, v2i64, VR128, memopv2i64,
3678 i128mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3679 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
3680 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
3684 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b,
3685 VR128, memopv2i64, i128mem,
3686 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3687 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w,
3688 VR128, memopv2i64, i128mem,
3689 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3690 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b,
3691 VR128, memopv2i64, i128mem,
3692 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3693 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w,
3694 VR128, memopv2i64, i128mem,
3695 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3696 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b,
3697 VR128, memopv2i64, i128mem,
3698 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3699 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w,
3700 VR128, memopv2i64, i128mem,
3701 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3702 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b,
3703 VR128, memopv2i64, i128mem,
3704 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3705 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w,
3706 VR128, memopv2i64, i128mem,
3707 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3708 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w,
3709 VR128, memopv2i64, i128mem,
3710 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3711 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w,
3712 VR128, memopv2i64, i128mem,
3713 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3714 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd,
3715 VR128, memopv2i64, i128mem,
3716 SSE_PMADD, 1, 0>, VEX_4V;
3717 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b,
3718 VR128, memopv2i64, i128mem,
3719 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3720 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w,
3721 VR128, memopv2i64, i128mem,
3722 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3723 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b,
3724 VR128, memopv2i64, i128mem,
3725 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3726 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w,
3727 VR128, memopv2i64, i128mem,
3728 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3729 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b,
3730 VR128, memopv2i64, i128mem,
3731 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3732 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w,
3733 VR128, memopv2i64, i128mem,
3734 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3735 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw,
3736 VR128, memopv2i64, i128mem,
3737 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3740 let Predicates = [HasAVX2] in {
3741 defm VPADDBY : PDI_binop_rm<0xFC, "vpaddb", add, v32i8, VR256, memopv4i64,
3742 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3743 defm VPADDWY : PDI_binop_rm<0xFD, "vpaddw", add, v16i16, VR256, memopv4i64,
3744 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3745 defm VPADDDY : PDI_binop_rm<0xFE, "vpaddd", add, v8i32, VR256, memopv4i64,
3746 i256mem, SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3747 defm VPADDQY : PDI_binop_rm<0xD4, "vpaddq", add, v4i64, VR256, memopv4i64,
3748 i256mem, SSE_INTALUQ_ITINS_P, 1, 0>, VEX_4V;
3749 defm VPMULLWY : PDI_binop_rm<0xD5, "vpmullw", mul, v16i16, VR256, memopv4i64,
3750 i256mem, SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3751 defm VPSUBBY : PDI_binop_rm<0xF8, "vpsubb", sub, v32i8, VR256, memopv4i64,
3752 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3753 defm VPSUBWY : PDI_binop_rm<0xF9, "vpsubw", sub, v16i16,VR256, memopv4i64,
3754 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3755 defm VPSUBDY : PDI_binop_rm<0xFA, "vpsubd", sub, v8i32, VR256, memopv4i64,
3756 i256mem, SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3757 defm VPSUBQY : PDI_binop_rm<0xFB, "vpsubq", sub, v4i64, VR256, memopv4i64,
3758 i256mem, SSE_INTALUQ_ITINS_P, 0, 0>, VEX_4V;
3759 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
3760 VR256, memopv4i64, i256mem,
3761 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3764 defm VPSUBSBY : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_avx2_psubs_b,
3765 VR256, memopv4i64, i256mem,
3766 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3767 defm VPSUBSWY : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_avx2_psubs_w,
3768 VR256, memopv4i64, i256mem,
3769 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3770 defm VPSUBUSBY : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_avx2_psubus_b,
3771 VR256, memopv4i64, i256mem,
3772 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3773 defm VPSUBUSWY : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_avx2_psubus_w,
3774 VR256, memopv4i64, i256mem,
3775 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
3776 defm VPADDSBY : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_avx2_padds_b,
3777 VR256, memopv4i64, i256mem,
3778 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3779 defm VPADDSWY : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_avx2_padds_w,
3780 VR256, memopv4i64, i256mem,
3781 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3782 defm VPADDUSBY : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_avx2_paddus_b,
3783 VR256, memopv4i64, i256mem,
3784 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3785 defm VPADDUSWY : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_avx2_paddus_w,
3786 VR256, memopv4i64, i256mem,
3787 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3788 defm VPMULHUWY : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_avx2_pmulhu_w,
3789 VR256, memopv4i64, i256mem,
3790 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3791 defm VPMULHWY : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_avx2_pmulh_w,
3792 VR256, memopv4i64, i256mem,
3793 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
3794 defm VPMADDWDY : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_avx2_pmadd_wd,
3795 VR256, memopv4i64, i256mem,
3796 SSE_PMADD, 1, 0>, VEX_4V;
3797 defm VPAVGBY : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_avx2_pavg_b,
3798 VR256, memopv4i64, i256mem,
3799 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3800 defm VPAVGWY : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_avx2_pavg_w,
3801 VR256, memopv4i64, i256mem,
3802 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3803 defm VPMINUBY : PDI_binop_rm_int<0xDA, "vpminub", int_x86_avx2_pminu_b,
3804 VR256, memopv4i64, i256mem,
3805 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3806 defm VPMINSWY : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_avx2_pmins_w,
3807 VR256, memopv4i64, i256mem,
3808 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3809 defm VPMAXUBY : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_avx2_pmaxu_b,
3810 VR256, memopv4i64, i256mem,
3811 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3812 defm VPMAXSWY : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_avx2_pmaxs_w,
3813 VR256, memopv4i64, i256mem,
3814 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3815 defm VPSADBWY : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_avx2_psad_bw,
3816 VR256, memopv4i64, i256mem,
3817 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
3820 let Constraints = "$src1 = $dst" in {
3821 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, VR128, memopv2i64,
3822 i128mem, SSE_INTALU_ITINS_P, 1>;
3823 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, VR128, memopv2i64,
3824 i128mem, SSE_INTALU_ITINS_P, 1>;
3825 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, VR128, memopv2i64,
3826 i128mem, SSE_INTALU_ITINS_P, 1>;
3827 defm PADDQ : PDI_binop_rm<0xD4, "paddq", add, v2i64, VR128, memopv2i64,
3828 i128mem, SSE_INTALUQ_ITINS_P, 1>;
3829 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, VR128, memopv2i64,
3830 i128mem, SSE_INTMUL_ITINS_P, 1>;
3831 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8, VR128, memopv2i64,
3832 i128mem, SSE_INTALU_ITINS_P>;
3833 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16, VR128, memopv2i64,
3834 i128mem, SSE_INTALU_ITINS_P>;
3835 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32, VR128, memopv2i64,
3836 i128mem, SSE_INTALU_ITINS_P>;
3837 defm PSUBQ : PDI_binop_rm<0xFB, "psubq", sub, v2i64, VR128, memopv2i64,
3838 i128mem, SSE_INTALUQ_ITINS_P>;
3839 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
3840 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
3843 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b,
3844 VR128, memopv2i64, i128mem,
3845 SSE_INTALU_ITINS_P>;
3846 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
3847 VR128, memopv2i64, i128mem,
3848 SSE_INTALU_ITINS_P>;
3849 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b,
3850 VR128, memopv2i64, i128mem,
3851 SSE_INTALU_ITINS_P>;
3852 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w,
3853 VR128, memopv2i64, i128mem,
3854 SSE_INTALU_ITINS_P>;
3855 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
3856 VR128, memopv2i64, i128mem,
3857 SSE_INTALU_ITINS_P, 1>;
3858 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w,
3859 VR128, memopv2i64, i128mem,
3860 SSE_INTALU_ITINS_P, 1>;
3861 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
3862 VR128, memopv2i64, i128mem,
3863 SSE_INTALU_ITINS_P, 1>;
3864 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
3865 VR128, memopv2i64, i128mem,
3866 SSE_INTALU_ITINS_P, 1>;
3867 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w,
3868 VR128, memopv2i64, i128mem,
3869 SSE_INTMUL_ITINS_P, 1>;
3870 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w,
3871 VR128, memopv2i64, i128mem,
3872 SSE_INTMUL_ITINS_P, 1>;
3873 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
3874 VR128, memopv2i64, i128mem,
3876 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
3877 VR128, memopv2i64, i128mem,
3878 SSE_INTALU_ITINS_P, 1>;
3879 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
3880 VR128, memopv2i64, i128mem,
3881 SSE_INTALU_ITINS_P, 1>;
3882 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b,
3883 VR128, memopv2i64, i128mem,
3884 SSE_INTALU_ITINS_P, 1>;
3885 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w,
3886 VR128, memopv2i64, i128mem,
3887 SSE_INTALU_ITINS_P, 1>;
3888 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b,
3889 VR128, memopv2i64, i128mem,
3890 SSE_INTALU_ITINS_P, 1>;
3891 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w,
3892 VR128, memopv2i64, i128mem,
3893 SSE_INTALU_ITINS_P, 1>;
3894 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
3895 VR128, memopv2i64, i128mem,
3896 SSE_INTALU_ITINS_P, 1>;
3898 } // Constraints = "$src1 = $dst"
3900 //===---------------------------------------------------------------------===//
3901 // SSE2 - Packed Integer Logical Instructions
3902 //===---------------------------------------------------------------------===//
3904 let Predicates = [HasAVX] in {
3905 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3906 VR128, v8i16, v8i16, bc_v8i16,
3907 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3908 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3909 VR128, v4i32, v4i32, bc_v4i32,
3910 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3911 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3912 VR128, v2i64, v2i64, bc_v2i64,
3913 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3915 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3916 VR128, v8i16, v8i16, bc_v8i16,
3917 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3918 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3919 VR128, v4i32, v4i32, bc_v4i32,
3920 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3921 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3922 VR128, v2i64, v2i64, bc_v2i64,
3923 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3925 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3926 VR128, v8i16, v8i16, bc_v8i16,
3927 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3928 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3929 VR128, v4i32, v4i32, bc_v4i32,
3930 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3932 let ExeDomain = SSEPackedInt in {
3933 // 128-bit logical shifts.
3934 def VPSLLDQri : PDIi8<0x73, MRM7r,
3935 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3936 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3938 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>,
3940 def VPSRLDQri : PDIi8<0x73, MRM3r,
3941 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3942 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3944 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>,
3946 // PSRADQri doesn't exist in SSE[1-3].
3948 } // Predicates = [HasAVX]
3950 let Predicates = [HasAVX2] in {
3951 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
3952 VR256, v16i16, v8i16, bc_v8i16,
3953 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3954 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
3955 VR256, v8i32, v4i32, bc_v4i32,
3956 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3957 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
3958 VR256, v4i64, v2i64, bc_v2i64,
3959 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3961 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
3962 VR256, v16i16, v8i16, bc_v8i16,
3963 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3964 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
3965 VR256, v8i32, v4i32, bc_v4i32,
3966 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3967 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
3968 VR256, v4i64, v2i64, bc_v2i64,
3969 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3971 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
3972 VR256, v16i16, v8i16, bc_v8i16,
3973 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3974 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
3975 VR256, v8i32, v4i32, bc_v4i32,
3976 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
3978 let ExeDomain = SSEPackedInt in {
3979 // 256-bit logical shifts.
3980 def VPSLLDQYri : PDIi8<0x73, MRM7r,
3981 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3982 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3984 (int_x86_avx2_psll_dq_bs VR256:$src1, imm:$src2))]>,
3986 def VPSRLDQYri : PDIi8<0x73, MRM3r,
3987 (outs VR256:$dst), (ins VR256:$src1, i32i8imm:$src2),
3988 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3990 (int_x86_avx2_psrl_dq_bs VR256:$src1, imm:$src2))]>,
3992 // PSRADQYri doesn't exist in SSE[1-3].
3994 } // Predicates = [HasAVX2]
3996 let Constraints = "$src1 = $dst" in {
3997 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
3998 VR128, v8i16, v8i16, bc_v8i16,
3999 SSE_INTSHIFT_ITINS_P>;
4000 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4001 VR128, v4i32, v4i32, bc_v4i32,
4002 SSE_INTSHIFT_ITINS_P>;
4003 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4004 VR128, v2i64, v2i64, bc_v2i64,
4005 SSE_INTSHIFT_ITINS_P>;
4007 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4008 VR128, v8i16, v8i16, bc_v8i16,
4009 SSE_INTSHIFT_ITINS_P>;
4010 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4011 VR128, v4i32, v4i32, bc_v4i32,
4012 SSE_INTSHIFT_ITINS_P>;
4013 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4014 VR128, v2i64, v2i64, bc_v2i64,
4015 SSE_INTSHIFT_ITINS_P>;
4017 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4018 VR128, v8i16, v8i16, bc_v8i16,
4019 SSE_INTSHIFT_ITINS_P>;
4020 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4021 VR128, v4i32, v4i32, bc_v4i32,
4022 SSE_INTSHIFT_ITINS_P>;
4024 let ExeDomain = SSEPackedInt in {
4025 // 128-bit logical shifts.
4026 def PSLLDQri : PDIi8<0x73, MRM7r,
4027 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4028 "pslldq\t{$src2, $dst|$dst, $src2}",
4030 (int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2))]>;
4031 def PSRLDQri : PDIi8<0x73, MRM3r,
4032 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4033 "psrldq\t{$src2, $dst|$dst, $src2}",
4035 (int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2))]>;
4036 // PSRADQri doesn't exist in SSE[1-3].
4038 } // Constraints = "$src1 = $dst"
4040 let Predicates = [HasAVX] in {
4041 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4042 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4043 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4044 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4045 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4046 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4048 // Shift up / down and insert zero's.
4049 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4050 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4051 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4052 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4055 let Predicates = [HasAVX2] in {
4056 def : Pat<(int_x86_avx2_psll_dq VR256:$src1, imm:$src2),
4057 (VPSLLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4058 def : Pat<(int_x86_avx2_psrl_dq VR256:$src1, imm:$src2),
4059 (VPSRLDQYri VR256:$src1, (BYTE_imm imm:$src2))>;
4062 let Predicates = [HasSSE2] in {
4063 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
4064 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4065 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
4066 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4067 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4068 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4070 // Shift up / down and insert zero's.
4071 def : Pat<(v2i64 (X86vshldq VR128:$src, (i8 imm:$amt))),
4072 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4073 def : Pat<(v2i64 (X86vshrdq VR128:$src, (i8 imm:$amt))),
4074 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt))>;
4077 //===---------------------------------------------------------------------===//
4078 // SSE2 - Packed Integer Comparison Instructions
4079 //===---------------------------------------------------------------------===//
4081 let Predicates = [HasAVX] in {
4082 defm VPCMPEQB : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v16i8,
4083 VR128, memopv2i64, i128mem,
4084 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4085 defm VPCMPEQW : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v8i16,
4086 VR128, memopv2i64, i128mem,
4087 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4088 defm VPCMPEQD : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v4i32,
4089 VR128, memopv2i64, i128mem,
4090 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4091 defm VPCMPGTB : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v16i8,
4092 VR128, memopv2i64, i128mem,
4093 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4094 defm VPCMPGTW : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v8i16,
4095 VR128, memopv2i64, i128mem,
4096 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4097 defm VPCMPGTD : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v4i32,
4098 VR128, memopv2i64, i128mem,
4099 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4102 let Predicates = [HasAVX2] in {
4103 defm VPCMPEQBY : PDI_binop_rm<0x74, "vpcmpeqb", X86pcmpeq, v32i8,
4104 VR256, memopv4i64, i256mem,
4105 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4106 defm VPCMPEQWY : PDI_binop_rm<0x75, "vpcmpeqw", X86pcmpeq, v16i16,
4107 VR256, memopv4i64, i256mem,
4108 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4109 defm VPCMPEQDY : PDI_binop_rm<0x76, "vpcmpeqd", X86pcmpeq, v8i32,
4110 VR256, memopv4i64, i256mem,
4111 SSE_INTALU_ITINS_P, 1, 0>, VEX_4V;
4112 defm VPCMPGTBY : PDI_binop_rm<0x64, "vpcmpgtb", X86pcmpgt, v32i8,
4113 VR256, memopv4i64, i256mem,
4114 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4115 defm VPCMPGTWY : PDI_binop_rm<0x65, "vpcmpgtw", X86pcmpgt, v16i16,
4116 VR256, memopv4i64, i256mem,
4117 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4118 defm VPCMPGTDY : PDI_binop_rm<0x66, "vpcmpgtd", X86pcmpgt, v8i32,
4119 VR256, memopv4i64, i256mem,
4120 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4123 let Constraints = "$src1 = $dst" in {
4124 defm PCMPEQB : PDI_binop_rm<0x74, "pcmpeqb", X86pcmpeq, v16i8,
4125 VR128, memopv2i64, i128mem,
4126 SSE_INTALU_ITINS_P, 1>;
4127 defm PCMPEQW : PDI_binop_rm<0x75, "pcmpeqw", X86pcmpeq, v8i16,
4128 VR128, memopv2i64, i128mem,
4129 SSE_INTALU_ITINS_P, 1>;
4130 defm PCMPEQD : PDI_binop_rm<0x76, "pcmpeqd", X86pcmpeq, v4i32,
4131 VR128, memopv2i64, i128mem,
4132 SSE_INTALU_ITINS_P, 1>;
4133 defm PCMPGTB : PDI_binop_rm<0x64, "pcmpgtb", X86pcmpgt, v16i8,
4134 VR128, memopv2i64, i128mem,
4135 SSE_INTALU_ITINS_P>;
4136 defm PCMPGTW : PDI_binop_rm<0x65, "pcmpgtw", X86pcmpgt, v8i16,
4137 VR128, memopv2i64, i128mem,
4138 SSE_INTALU_ITINS_P>;
4139 defm PCMPGTD : PDI_binop_rm<0x66, "pcmpgtd", X86pcmpgt, v4i32,
4140 VR128, memopv2i64, i128mem,
4141 SSE_INTALU_ITINS_P>;
4142 } // Constraints = "$src1 = $dst"
4144 //===---------------------------------------------------------------------===//
4145 // SSE2 - Packed Integer Pack Instructions
4146 //===---------------------------------------------------------------------===//
4148 let Predicates = [HasAVX] in {
4149 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
4150 VR128, memopv2i64, i128mem,
4151 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4152 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
4153 VR128, memopv2i64, i128mem,
4154 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4155 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
4156 VR128, memopv2i64, i128mem,
4157 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4160 let Predicates = [HasAVX2] in {
4161 defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
4162 VR256, memopv4i64, i256mem,
4163 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4164 defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
4165 VR256, memopv4i64, i256mem,
4166 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4167 defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
4168 VR256, memopv4i64, i256mem,
4169 SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
4172 let Constraints = "$src1 = $dst" in {
4173 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
4174 VR128, memopv2i64, i128mem,
4175 SSE_INTALU_ITINS_P>;
4176 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
4177 VR128, memopv2i64, i128mem,
4178 SSE_INTALU_ITINS_P>;
4179 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
4180 VR128, memopv2i64, i128mem,
4181 SSE_INTALU_ITINS_P>;
4182 } // Constraints = "$src1 = $dst"
4184 //===---------------------------------------------------------------------===//
4185 // SSE2 - Packed Integer Shuffle Instructions
4186 //===---------------------------------------------------------------------===//
4188 let ExeDomain = SSEPackedInt in {
4189 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, SDNode OpNode> {
4190 def ri : Ii8<0x70, MRMSrcReg,
4191 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
4192 !strconcat(OpcodeStr,
4193 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4194 [(set VR128:$dst, (vt (OpNode VR128:$src1, (i8 imm:$src2))))],
4196 def mi : Ii8<0x70, MRMSrcMem,
4197 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
4198 !strconcat(OpcodeStr,
4199 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4201 (vt (OpNode (bitconvert (memopv2i64 addr:$src1)),
4206 multiclass sse2_pshuffle_y<string OpcodeStr, ValueType vt, SDNode OpNode> {
4207 def Yri : Ii8<0x70, MRMSrcReg,
4208 (outs VR256:$dst), (ins VR256:$src1, i8imm:$src2),
4209 !strconcat(OpcodeStr,
4210 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4211 [(set VR256:$dst, (vt (OpNode VR256:$src1, (i8 imm:$src2))))]>;
4212 def Ymi : Ii8<0x70, MRMSrcMem,
4213 (outs VR256:$dst), (ins i256mem:$src1, i8imm:$src2),
4214 !strconcat(OpcodeStr,
4215 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4217 (vt (OpNode (bitconvert (memopv4i64 addr:$src1)),
4218 (i8 imm:$src2))))]>;
4220 } // ExeDomain = SSEPackedInt
4222 let Predicates = [HasAVX] in {
4223 let AddedComplexity = 5 in
4224 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, X86PShufd>, TB, OpSize, VEX;
4226 // SSE2 with ImmT == Imm8 and XS prefix.
4227 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, X86PShufhw>, XS, VEX;
4229 // SSE2 with ImmT == Imm8 and XD prefix.
4230 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, X86PShuflw>, XD, VEX;
4232 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4233 (VPSHUFDmi addr:$src1, imm:$imm)>;
4234 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4235 (VPSHUFDri VR128:$src1, imm:$imm)>;
4238 let Predicates = [HasAVX2] in {
4239 defm VPSHUFD : sse2_pshuffle_y<"vpshufd", v8i32, X86PShufd>, TB, OpSize, VEX;
4240 defm VPSHUFHW : sse2_pshuffle_y<"vpshufhw", v16i16, X86PShufhw>, XS, VEX;
4241 defm VPSHUFLW : sse2_pshuffle_y<"vpshuflw", v16i16, X86PShuflw>, XD, VEX;
4244 let Predicates = [HasSSE2] in {
4245 let AddedComplexity = 5 in
4246 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, X86PShufd>, TB, OpSize;
4248 // SSE2 with ImmT == Imm8 and XS prefix.
4249 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, X86PShufhw>, XS;
4251 // SSE2 with ImmT == Imm8 and XD prefix.
4252 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, X86PShuflw>, XD;
4254 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4255 (PSHUFDmi addr:$src1, imm:$imm)>;
4256 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4257 (PSHUFDri VR128:$src1, imm:$imm)>;
4260 //===---------------------------------------------------------------------===//
4261 // SSE2 - Packed Integer Unpack Instructions
4262 //===---------------------------------------------------------------------===//
4264 let ExeDomain = SSEPackedInt in {
4265 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4266 SDNode OpNode, PatFrag bc_frag, bit Is2Addr = 1> {
4267 def rr : PDI<opc, MRMSrcReg,
4268 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4270 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4271 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4272 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4274 def rm : PDI<opc, MRMSrcMem,
4275 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4277 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4278 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4279 [(set VR128:$dst, (OpNode VR128:$src1,
4280 (bc_frag (memopv2i64
4285 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4286 SDNode OpNode, PatFrag bc_frag> {
4287 def Yrr : PDI<opc, MRMSrcReg,
4288 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4289 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4290 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>;
4291 def Yrm : PDI<opc, MRMSrcMem,
4292 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4293 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4294 [(set VR256:$dst, (OpNode VR256:$src1,
4295 (bc_frag (memopv4i64 addr:$src2))))]>;
4298 let Predicates = [HasAVX] in {
4299 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4300 bc_v16i8, 0>, VEX_4V;
4301 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4302 bc_v8i16, 0>, VEX_4V;
4303 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4304 bc_v4i32, 0>, VEX_4V;
4305 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4306 bc_v2i64, 0>, VEX_4V;
4308 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4309 bc_v16i8, 0>, VEX_4V;
4310 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4311 bc_v8i16, 0>, VEX_4V;
4312 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4313 bc_v4i32, 0>, VEX_4V;
4314 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4315 bc_v2i64, 0>, VEX_4V;
4318 let Predicates = [HasAVX2] in {
4319 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4321 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4323 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4325 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4328 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4330 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4332 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4334 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4338 let Constraints = "$src1 = $dst" in {
4339 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4341 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4343 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4345 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4348 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4350 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4352 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4354 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4357 } // ExeDomain = SSEPackedInt
4359 // Patterns for using AVX1 instructions with integer vectors
4360 // Here to give AVX2 priority
4361 let Predicates = [HasAVX] in {
4362 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4363 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
4364 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
4365 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
4366 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)))),
4367 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
4368 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
4369 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
4371 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (memopv4i64 addr:$src2))),
4372 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
4373 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
4374 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
4375 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (memopv4i64 addr:$src2))),
4376 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
4377 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
4378 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
4381 //===---------------------------------------------------------------------===//
4382 // SSE2 - Packed Integer Extract and Insert
4383 //===---------------------------------------------------------------------===//
4385 let ExeDomain = SSEPackedInt in {
4386 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4387 def rri : Ii8<0xC4, MRMSrcReg,
4388 (outs VR128:$dst), (ins VR128:$src1,
4389 GR32:$src2, i32i8imm:$src3),
4391 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4392 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4394 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>;
4395 def rmi : Ii8<0xC4, MRMSrcMem,
4396 (outs VR128:$dst), (ins VR128:$src1,
4397 i16mem:$src2, i32i8imm:$src3),
4399 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4400 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4402 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4403 imm:$src3))], IIC_SSE_PINSRW>;
4407 let Predicates = [HasAVX] in
4408 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4409 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4410 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4411 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4412 imm:$src2))]>, TB, OpSize, VEX;
4413 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4414 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
4415 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4416 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
4417 imm:$src2))], IIC_SSE_PEXTRW>;
4420 let Predicates = [HasAVX] in {
4421 defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;
4422 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
4423 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4424 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
4425 []>, TB, OpSize, VEX_4V;
4428 let Constraints = "$src1 = $dst" in
4429 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
4431 } // ExeDomain = SSEPackedInt
4433 //===---------------------------------------------------------------------===//
4434 // SSE2 - Packed Mask Creation
4435 //===---------------------------------------------------------------------===//
4437 let ExeDomain = SSEPackedInt in {
4439 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4440 "pmovmskb\t{$src, $dst|$dst, $src}",
4441 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4442 IIC_SSE_MOVMSK>, VEX;
4443 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
4444 "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;
4446 let Predicates = [HasAVX2] in {
4447 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
4448 "pmovmskb\t{$src, $dst|$dst, $src}",
4449 [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX;
4450 def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
4451 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
4454 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
4455 "pmovmskb\t{$src, $dst|$dst, $src}",
4456 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4459 } // ExeDomain = SSEPackedInt
4461 //===---------------------------------------------------------------------===//
4462 // SSE2 - Conditional Store
4463 //===---------------------------------------------------------------------===//
4465 let ExeDomain = SSEPackedInt in {
4468 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4469 (ins VR128:$src, VR128:$mask),
4470 "maskmovdqu\t{$mask, $src|$src, $mask}",
4471 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4472 IIC_SSE_MASKMOV>, VEX;
4474 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4475 (ins VR128:$src, VR128:$mask),
4476 "maskmovdqu\t{$mask, $src|$src, $mask}",
4477 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4478 IIC_SSE_MASKMOV>, VEX;
4481 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4482 "maskmovdqu\t{$mask, $src|$src, $mask}",
4483 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4486 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4487 "maskmovdqu\t{$mask, $src|$src, $mask}",
4488 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4491 } // ExeDomain = SSEPackedInt
4493 //===---------------------------------------------------------------------===//
4494 // SSE2 - Move Doubleword
4495 //===---------------------------------------------------------------------===//
4497 //===---------------------------------------------------------------------===//
4498 // Move Int Doubleword to Packed Double Int
4500 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4501 "movd\t{$src, $dst|$dst, $src}",
4503 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4505 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4506 "movd\t{$src, $dst|$dst, $src}",
4508 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4511 def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4512 "mov{d|q}\t{$src, $dst|$dst, $src}",
4514 (v2i64 (scalar_to_vector GR64:$src)))],
4515 IIC_SSE_MOVDQ>, VEX;
4516 def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4517 "mov{d|q}\t{$src, $dst|$dst, $src}",
4518 [(set FR64:$dst, (bitconvert GR64:$src))],
4519 IIC_SSE_MOVDQ>, VEX;
4521 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4522 "movd\t{$src, $dst|$dst, $src}",
4524 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>;
4525 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4526 "movd\t{$src, $dst|$dst, $src}",
4528 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4530 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4531 "mov{d|q}\t{$src, $dst|$dst, $src}",
4533 (v2i64 (scalar_to_vector GR64:$src)))],
4535 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4536 "mov{d|q}\t{$src, $dst|$dst, $src}",
4537 [(set FR64:$dst, (bitconvert GR64:$src))],
4540 //===---------------------------------------------------------------------===//
4541 // Move Int Doubleword to Single Scalar
4543 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4544 "movd\t{$src, $dst|$dst, $src}",
4545 [(set FR32:$dst, (bitconvert GR32:$src))],
4546 IIC_SSE_MOVDQ>, VEX;
4548 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4549 "movd\t{$src, $dst|$dst, $src}",
4550 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4553 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4554 "movd\t{$src, $dst|$dst, $src}",
4555 [(set FR32:$dst, (bitconvert GR32:$src))],
4558 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4559 "movd\t{$src, $dst|$dst, $src}",
4560 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4563 //===---------------------------------------------------------------------===//
4564 // Move Packed Doubleword Int to Packed Double Int
4566 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4567 "movd\t{$src, $dst|$dst, $src}",
4568 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4569 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX;
4570 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
4571 (ins i32mem:$dst, VR128:$src),
4572 "movd\t{$src, $dst|$dst, $src}",
4573 [(store (i32 (vector_extract (v4i32 VR128:$src),
4574 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4576 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4577 "movd\t{$src, $dst|$dst, $src}",
4578 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4579 (iPTR 0)))], IIC_SSE_MOVD_ToGP>;
4580 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4581 "movd\t{$src, $dst|$dst, $src}",
4582 [(store (i32 (vector_extract (v4i32 VR128:$src),
4583 (iPTR 0))), addr:$dst)],
4586 //===---------------------------------------------------------------------===//
4587 // Move Packed Doubleword Int first element to Doubleword Int
4589 def VMOVPQIto64rr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4590 "mov{d|q}\t{$src, $dst|$dst, $src}",
4591 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4594 TB, OpSize, VEX, VEX_W, Requires<[HasAVX, In64BitMode]>;
4596 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4597 "mov{d|q}\t{$src, $dst|$dst, $src}",
4598 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4602 //===---------------------------------------------------------------------===//
4603 // Bitcast FR64 <-> GR64
4605 let Predicates = [HasAVX] in
4606 def VMOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4607 "vmovq\t{$src, $dst|$dst, $src}",
4608 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4610 def VMOVSDto64rr : VRPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4611 "mov{d|q}\t{$src, $dst|$dst, $src}",
4612 [(set GR64:$dst, (bitconvert FR64:$src))],
4613 IIC_SSE_MOVDQ>, VEX;
4614 def VMOVSDto64mr : VRPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4615 "movq\t{$src, $dst|$dst, $src}",
4616 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4617 IIC_SSE_MOVDQ>, VEX;
4619 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4620 "movq\t{$src, $dst|$dst, $src}",
4621 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4623 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4624 "mov{d|q}\t{$src, $dst|$dst, $src}",
4625 [(set GR64:$dst, (bitconvert FR64:$src))],
4627 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4628 "movq\t{$src, $dst|$dst, $src}",
4629 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4632 //===---------------------------------------------------------------------===//
4633 // Move Scalar Single to Double Int
4635 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4636 "movd\t{$src, $dst|$dst, $src}",
4637 [(set GR32:$dst, (bitconvert FR32:$src))],
4638 IIC_SSE_MOVD_ToGP>, VEX;
4639 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4640 "movd\t{$src, $dst|$dst, $src}",
4641 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4642 IIC_SSE_MOVDQ>, VEX;
4643 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4644 "movd\t{$src, $dst|$dst, $src}",
4645 [(set GR32:$dst, (bitconvert FR32:$src))],
4647 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4648 "movd\t{$src, $dst|$dst, $src}",
4649 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4652 //===---------------------------------------------------------------------===//
4653 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4655 let AddedComplexity = 15 in {
4656 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4657 "movd\t{$src, $dst|$dst, $src}",
4658 [(set VR128:$dst, (v4i32 (X86vzmovl
4659 (v4i32 (scalar_to_vector GR32:$src)))))],
4660 IIC_SSE_MOVDQ>, VEX;
4661 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4662 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4663 [(set VR128:$dst, (v2i64 (X86vzmovl
4664 (v2i64 (scalar_to_vector GR64:$src)))))],
4668 let AddedComplexity = 15 in {
4669 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4670 "movd\t{$src, $dst|$dst, $src}",
4671 [(set VR128:$dst, (v4i32 (X86vzmovl
4672 (v4i32 (scalar_to_vector GR32:$src)))))],
4674 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4675 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4676 [(set VR128:$dst, (v2i64 (X86vzmovl
4677 (v2i64 (scalar_to_vector GR64:$src)))))],
4681 let AddedComplexity = 20 in {
4682 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4683 "movd\t{$src, $dst|$dst, $src}",
4685 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4686 (loadi32 addr:$src))))))],
4687 IIC_SSE_MOVDQ>, VEX;
4688 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4689 "movd\t{$src, $dst|$dst, $src}",
4691 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
4692 (loadi32 addr:$src))))))],
4696 let Predicates = [HasAVX] in {
4697 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
4698 let AddedComplexity = 20 in {
4699 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4700 (VMOVZDI2PDIrm addr:$src)>;
4701 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4702 (VMOVZDI2PDIrm addr:$src)>;
4704 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4705 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4706 (v4i32 (scalar_to_vector GR32:$src)),(i32 0)))),
4707 (SUBREG_TO_REG (i32 0), (VMOVZDI2PDIrr GR32:$src), sub_xmm)>;
4708 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4709 (v2i64 (scalar_to_vector GR64:$src)),(i32 0)))),
4710 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4713 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4714 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4715 (MOVZDI2PDIrm addr:$src)>;
4716 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4717 (MOVZDI2PDIrm addr:$src)>;
4720 // These are the correct encodings of the instructions so that we know how to
4721 // read correct assembly, even though we continue to emit the wrong ones for
4722 // compatibility with Darwin's buggy assembler.
4723 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4724 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4725 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4726 (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
4727 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4728 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4729 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4730 (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
4731 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4732 (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4733 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4734 (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
4736 //===---------------------------------------------------------------------===//
4737 // SSE2 - Move Quadword
4738 //===---------------------------------------------------------------------===//
4740 //===---------------------------------------------------------------------===//
4741 // Move Quadword Int to Packed Quadword Int
4743 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4744 "vmovq\t{$src, $dst|$dst, $src}",
4746 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4747 VEX, Requires<[HasAVX]>;
4748 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4749 "movq\t{$src, $dst|$dst, $src}",
4751 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4753 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
4755 //===---------------------------------------------------------------------===//
4756 // Move Packed Quadword Int to Quadword Int
4758 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4759 "movq\t{$src, $dst|$dst, $src}",
4760 [(store (i64 (vector_extract (v2i64 VR128:$src),
4761 (iPTR 0))), addr:$dst)],
4762 IIC_SSE_MOVDQ>, VEX;
4763 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4764 "movq\t{$src, $dst|$dst, $src}",
4765 [(store (i64 (vector_extract (v2i64 VR128:$src),
4766 (iPTR 0))), addr:$dst)],
4769 //===---------------------------------------------------------------------===//
4770 // Store / copy lower 64-bits of a XMM register.
4772 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4773 "movq\t{$src, $dst|$dst, $src}",
4774 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
4775 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4776 "movq\t{$src, $dst|$dst, $src}",
4777 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)],
4780 let AddedComplexity = 20 in
4781 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4782 "vmovq\t{$src, $dst|$dst, $src}",
4784 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4785 (loadi64 addr:$src))))))],
4787 XS, VEX, Requires<[HasAVX]>;
4789 let AddedComplexity = 20 in
4790 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4791 "movq\t{$src, $dst|$dst, $src}",
4793 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
4794 (loadi64 addr:$src))))))],
4796 XS, Requires<[HasSSE2]>;
4798 let Predicates = [HasAVX], AddedComplexity = 20 in {
4799 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4800 (VMOVZQI2PQIrm addr:$src)>;
4801 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4802 (VMOVZQI2PQIrm addr:$src)>;
4803 def : Pat<(v2i64 (X86vzload addr:$src)),
4804 (VMOVZQI2PQIrm addr:$src)>;
4807 let Predicates = [HasSSE2], AddedComplexity = 20 in {
4808 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4809 (MOVZQI2PQIrm addr:$src)>;
4810 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
4811 (MOVZQI2PQIrm addr:$src)>;
4812 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
4815 let Predicates = [HasAVX] in {
4816 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
4817 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
4818 def : Pat<(v4i64 (X86vzload addr:$src)),
4819 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
4822 //===---------------------------------------------------------------------===//
4823 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
4824 // IA32 document. movq xmm1, xmm2 does clear the high bits.
4826 let AddedComplexity = 15 in
4827 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4828 "vmovq\t{$src, $dst|$dst, $src}",
4829 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4831 XS, VEX, Requires<[HasAVX]>;
4832 let AddedComplexity = 15 in
4833 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
4837 XS, Requires<[HasSSE2]>;
4839 let AddedComplexity = 20 in
4840 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4841 "vmovq\t{$src, $dst|$dst, $src}",
4842 [(set VR128:$dst, (v2i64 (X86vzmovl
4843 (loadv2i64 addr:$src))))],
4845 XS, VEX, Requires<[HasAVX]>;
4846 let AddedComplexity = 20 in {
4847 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4848 "movq\t{$src, $dst|$dst, $src}",
4849 [(set VR128:$dst, (v2i64 (X86vzmovl
4850 (loadv2i64 addr:$src))))],
4852 XS, Requires<[HasSSE2]>;
4855 let AddedComplexity = 20 in {
4856 let Predicates = [HasAVX] in {
4857 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4858 (VMOVZPQILo2PQIrm addr:$src)>;
4859 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4860 (VMOVZPQILo2PQIrr VR128:$src)>;
4862 let Predicates = [HasSSE2] in {
4863 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
4864 (MOVZPQILo2PQIrm addr:$src)>;
4865 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
4866 (MOVZPQILo2PQIrr VR128:$src)>;
4870 // Instructions to match in the assembler
4871 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4872 "movq\t{$src, $dst|$dst, $src}", [],
4873 IIC_SSE_MOVDQ>, VEX, VEX_W;
4874 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4875 "movq\t{$src, $dst|$dst, $src}", [],
4876 IIC_SSE_MOVDQ>, VEX, VEX_W;
4877 // Recognize "movd" with GR64 destination, but encode as a "movq"
4878 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4879 "movd\t{$src, $dst|$dst, $src}", [],
4880 IIC_SSE_MOVDQ>, VEX, VEX_W;
4882 // Instructions for the disassembler
4883 // xr = XMM register
4886 let Predicates = [HasAVX] in
4887 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4888 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
4889 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4890 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, XS;
4892 //===---------------------------------------------------------------------===//
4893 // SSE3 - Conversion Instructions
4894 //===---------------------------------------------------------------------===//
4896 // Convert Packed Double FP to Packed DW Integers
4897 let Predicates = [HasAVX] in {
4898 // The assembler can recognize rr 256-bit instructions by seeing a ymm
4899 // register, but the same isn't true when using memory operands instead.
4900 // Provide other assembly rr and rm forms to address this explicitly.
4901 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4902 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4903 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4904 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
4907 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4908 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4909 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4910 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
4913 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
4914 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
4915 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
4916 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
4919 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4920 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4922 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4923 "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
4926 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
4927 (VCVTTPD2DQYrr VR256:$src)>;
4928 def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
4929 (VCVTTPD2DQYrm addr:$src)>;
4931 // Convert Packed DW Integers to Packed Double FP
4932 let Predicates = [HasAVX] in {
4933 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4934 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4935 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4936 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4937 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
4938 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4939 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
4940 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
4943 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
4944 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4946 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
4947 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
4950 // AVX 256-bit register conversion intrinsics
4951 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
4952 (VCVTDQ2PDYrr VR128:$src)>;
4953 def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
4954 (VCVTDQ2PDYrm addr:$src)>;
4956 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
4957 (VCVTPD2DQYrr VR256:$src)>;
4958 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
4959 (VCVTPD2DQYrm addr:$src)>;
4961 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
4962 (VCVTDQ2PDYrr VR128:$src)>;
4963 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
4964 (VCVTDQ2PDYrm addr:$src)>;
4966 //===---------------------------------------------------------------------===//
4967 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
4968 //===---------------------------------------------------------------------===//
4969 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
4970 ValueType vt, RegisterClass RC, PatFrag mem_frag,
4971 X86MemOperand x86memop> {
4972 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4973 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4974 [(set RC:$dst, (vt (OpNode RC:$src)))],
4976 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
4977 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4978 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
4982 let Predicates = [HasAVX] in {
4983 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4984 v4f32, VR128, memopv4f32, f128mem>, VEX;
4985 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4986 v4f32, VR128, memopv4f32, f128mem>, VEX;
4987 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
4988 v8f32, VR256, memopv8f32, f256mem>, VEX;
4989 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
4990 v8f32, VR256, memopv8f32, f256mem>, VEX;
4992 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
4993 memopv4f32, f128mem>;
4994 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
4995 memopv4f32, f128mem>;
4997 let Predicates = [HasAVX] in {
4998 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
4999 (VMOVSHDUPrr VR128:$src)>;
5000 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5001 (VMOVSHDUPrm addr:$src)>;
5002 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5003 (VMOVSLDUPrr VR128:$src)>;
5004 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5005 (VMOVSLDUPrm addr:$src)>;
5006 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5007 (VMOVSHDUPYrr VR256:$src)>;
5008 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (memopv4i64 addr:$src)))),
5009 (VMOVSHDUPYrm addr:$src)>;
5010 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5011 (VMOVSLDUPYrr VR256:$src)>;
5012 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (memopv4i64 addr:$src)))),
5013 (VMOVSLDUPYrm addr:$src)>;
5016 let Predicates = [HasSSE3] in {
5017 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5018 (MOVSHDUPrr VR128:$src)>;
5019 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5020 (MOVSHDUPrm addr:$src)>;
5021 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5022 (MOVSLDUPrr VR128:$src)>;
5023 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5024 (MOVSLDUPrm addr:$src)>;
5027 //===---------------------------------------------------------------------===//
5028 // SSE3 - Replicate Double FP - MOVDDUP
5029 //===---------------------------------------------------------------------===//
5031 multiclass sse3_replicate_dfp<string OpcodeStr> {
5032 let neverHasSideEffects = 1 in
5033 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5034 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5035 [], IIC_SSE_MOV_LH>;
5036 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5037 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5040 (scalar_to_vector (loadf64 addr:$src)))))],
5044 // FIXME: Merge with above classe when there're patterns for the ymm version
5045 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5046 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5047 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5048 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>;
5049 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5050 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5053 (scalar_to_vector (loadf64 addr:$src)))))]>;
5056 let Predicates = [HasAVX] in {
5057 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5058 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
5061 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5063 let Predicates = [HasAVX] in {
5064 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5065 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5066 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5067 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5068 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5069 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5070 def : Pat<(X86Movddup (bc_v2f64
5071 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5072 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5075 def : Pat<(X86Movddup (memopv4f64 addr:$src)),
5076 (VMOVDDUPYrm addr:$src)>;
5077 def : Pat<(X86Movddup (memopv4i64 addr:$src)),
5078 (VMOVDDUPYrm addr:$src)>;
5079 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5080 (VMOVDDUPYrm addr:$src)>;
5081 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5082 (VMOVDDUPYrr VR256:$src)>;
5085 let Predicates = [HasSSE3] in {
5086 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5087 (MOVDDUPrm addr:$src)>;
5088 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5089 (MOVDDUPrm addr:$src)>;
5090 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5091 (MOVDDUPrm addr:$src)>;
5092 def : Pat<(X86Movddup (bc_v2f64
5093 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5094 (MOVDDUPrm addr:$src)>;
5097 //===---------------------------------------------------------------------===//
5098 // SSE3 - Move Unaligned Integer
5099 //===---------------------------------------------------------------------===//
5101 let Predicates = [HasAVX] in {
5102 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5103 "vlddqu\t{$src, $dst|$dst, $src}",
5104 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5105 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5106 "vlddqu\t{$src, $dst|$dst, $src}",
5107 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
5109 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5110 "lddqu\t{$src, $dst|$dst, $src}",
5111 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5114 //===---------------------------------------------------------------------===//
5115 // SSE3 - Arithmetic
5116 //===---------------------------------------------------------------------===//
5118 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5119 X86MemOperand x86memop, OpndItins itins,
5121 def rr : I<0xD0, MRMSrcReg,
5122 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5124 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5125 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5126 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>;
5127 def rm : I<0xD0, MRMSrcMem,
5128 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5130 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5131 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5132 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))], itins.rr>;
5135 let Predicates = [HasAVX] in {
5136 let ExeDomain = SSEPackedSingle in {
5137 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5138 f128mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5139 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5140 f256mem, SSE_ALU_F32P, 0>, TB, XD, VEX_4V;
5142 let ExeDomain = SSEPackedDouble in {
5143 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5144 f128mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5145 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5146 f256mem, SSE_ALU_F64P, 0>, TB, OpSize, VEX_4V;
5149 let Constraints = "$src1 = $dst", Predicates = [HasSSE3] in {
5150 let ExeDomain = SSEPackedSingle in
5151 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5152 f128mem, SSE_ALU_F32P>, TB, XD;
5153 let ExeDomain = SSEPackedDouble in
5154 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5155 f128mem, SSE_ALU_F64P>, TB, OpSize;
5158 //===---------------------------------------------------------------------===//
5159 // SSE3 Instructions
5160 //===---------------------------------------------------------------------===//
5163 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5164 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5165 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5167 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5168 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5169 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5171 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5173 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5174 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5175 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5176 IIC_SSE_HADDSUB_RM>;
5178 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5179 X86MemOperand x86memop, SDNode OpNode, bit Is2Addr = 1> {
5180 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5182 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5184 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>;
5186 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5188 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5189 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5190 [(set RC:$dst, (vt (OpNode RC:$src1, (memop addr:$src2))))],
5191 IIC_SSE_HADDSUB_RM>;
5194 let Predicates = [HasAVX] in {
5195 let ExeDomain = SSEPackedSingle in {
5196 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5197 X86fhadd, 0>, VEX_4V;
5198 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5199 X86fhsub, 0>, VEX_4V;
5200 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5201 X86fhadd, 0>, VEX_4V;
5202 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5203 X86fhsub, 0>, VEX_4V;
5205 let ExeDomain = SSEPackedDouble in {
5206 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5207 X86fhadd, 0>, VEX_4V;
5208 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5209 X86fhsub, 0>, VEX_4V;
5210 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5211 X86fhadd, 0>, VEX_4V;
5212 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5213 X86fhsub, 0>, VEX_4V;
5217 let Constraints = "$src1 = $dst" in {
5218 let ExeDomain = SSEPackedSingle in {
5219 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd>;
5220 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub>;
5222 let ExeDomain = SSEPackedDouble in {
5223 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd>;
5224 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub>;
5228 //===---------------------------------------------------------------------===//
5229 // SSSE3 - Packed Absolute Instructions
5230 //===---------------------------------------------------------------------===//
5233 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5234 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
5235 Intrinsic IntId128> {
5236 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5238 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5239 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5242 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5244 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5247 (bitconvert (memopv2i64 addr:$src))))], IIC_SSE_PABS_RM>,
5251 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5252 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5253 Intrinsic IntId256> {
5254 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5256 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5257 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5260 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5262 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5265 (bitconvert (memopv4i64 addr:$src))))]>, OpSize;
5268 let Predicates = [HasAVX] in {
5269 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb",
5270 int_x86_ssse3_pabs_b_128>, VEX;
5271 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw",
5272 int_x86_ssse3_pabs_w_128>, VEX;
5273 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd",
5274 int_x86_ssse3_pabs_d_128>, VEX;
5277 let Predicates = [HasAVX2] in {
5278 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5279 int_x86_avx2_pabs_b>, VEX;
5280 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5281 int_x86_avx2_pabs_w>, VEX;
5282 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5283 int_x86_avx2_pabs_d>, VEX;
5286 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb",
5287 int_x86_ssse3_pabs_b_128>;
5288 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw",
5289 int_x86_ssse3_pabs_w_128>;
5290 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd",
5291 int_x86_ssse3_pabs_d_128>;
5293 //===---------------------------------------------------------------------===//
5294 // SSSE3 - Packed Binary Operator Instructions
5295 //===---------------------------------------------------------------------===//
5297 def SSE_PHADDSUBD : OpndItins<
5298 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5300 def SSE_PHADDSUBSW : OpndItins<
5301 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5303 def SSE_PHADDSUBW : OpndItins<
5304 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5306 def SSE_PSHUFB : OpndItins<
5307 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5309 def SSE_PSIGN : OpndItins<
5310 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5312 def SSE_PMULHRSW : OpndItins<
5313 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5316 /// SS3I_binop_rm - Simple SSSE3 bin op
5317 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5318 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5319 X86MemOperand x86memop, OpndItins itins,
5321 let isCommutable = 1 in
5322 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5323 (ins RC:$src1, RC:$src2),
5325 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5327 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5329 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5330 (ins RC:$src1, x86memop:$src2),
5332 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5333 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5335 (OpVT (OpNode RC:$src1,
5336 (bitconvert (memop_frag addr:$src2)))))], itins.rm>, OpSize;
5339 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5340 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5341 Intrinsic IntId128, OpndItins itins,
5343 let isCommutable = 1 in
5344 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5345 (ins VR128:$src1, VR128:$src2),
5347 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5348 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5349 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5351 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5352 (ins VR128:$src1, i128mem:$src2),
5354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5357 (IntId128 VR128:$src1,
5358 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
5361 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5362 Intrinsic IntId256> {
5363 let isCommutable = 1 in
5364 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5365 (ins VR256:$src1, VR256:$src2),
5366 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5367 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5369 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5370 (ins VR256:$src1, i256mem:$src2),
5371 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5373 (IntId256 VR256:$src1,
5374 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
5377 let ImmT = NoImm, Predicates = [HasAVX] in {
5378 let isCommutable = 0 in {
5379 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5380 memopv2i64, i128mem,
5381 SSE_PHADDSUBW, 0>, VEX_4V;
5382 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5383 memopv2i64, i128mem,
5384 SSE_PHADDSUBD, 0>, VEX_4V;
5385 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5386 memopv2i64, i128mem,
5387 SSE_PHADDSUBW, 0>, VEX_4V;
5388 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5389 memopv2i64, i128mem,
5390 SSE_PHADDSUBD, 0>, VEX_4V;
5391 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5392 memopv2i64, i128mem,
5393 SSE_PSIGN, 0>, VEX_4V;
5394 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5395 memopv2i64, i128mem,
5396 SSE_PSIGN, 0>, VEX_4V;
5397 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5398 memopv2i64, i128mem,
5399 SSE_PSIGN, 0>, VEX_4V;
5400 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5401 memopv2i64, i128mem,
5402 SSE_PSHUFB, 0>, VEX_4V;
5403 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5404 int_x86_ssse3_phadd_sw_128,
5405 SSE_PHADDSUBSW, 0>, VEX_4V;
5406 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5407 int_x86_ssse3_phsub_sw_128,
5408 SSE_PHADDSUBSW, 0>, VEX_4V;
5409 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5410 int_x86_ssse3_pmadd_ub_sw_128,
5411 SSE_PMADD, 0>, VEX_4V;
5413 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5414 int_x86_ssse3_pmul_hr_sw_128,
5415 SSE_PMULHRSW, 0>, VEX_4V;
5418 let ImmT = NoImm, Predicates = [HasAVX2] in {
5419 let isCommutable = 0 in {
5420 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5421 memopv4i64, i256mem,
5422 SSE_PHADDSUBW, 0>, VEX_4V;
5423 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5424 memopv4i64, i256mem,
5425 SSE_PHADDSUBW, 0>, VEX_4V;
5426 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5427 memopv4i64, i256mem,
5428 SSE_PHADDSUBW, 0>, VEX_4V;
5429 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5430 memopv4i64, i256mem,
5431 SSE_PHADDSUBW, 0>, VEX_4V;
5432 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5433 memopv4i64, i256mem,
5434 SSE_PHADDSUBW, 0>, VEX_4V;
5435 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5436 memopv4i64, i256mem,
5437 SSE_PHADDSUBW, 0>, VEX_4V;
5438 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5439 memopv4i64, i256mem,
5440 SSE_PHADDSUBW, 0>, VEX_4V;
5441 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5442 memopv4i64, i256mem,
5443 SSE_PHADDSUBW, 0>, VEX_4V;
5444 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5445 int_x86_avx2_phadd_sw>, VEX_4V;
5446 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5447 int_x86_avx2_phsub_sw>, VEX_4V;
5448 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5449 int_x86_avx2_pmadd_ub_sw>, VEX_4V;
5451 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5452 int_x86_avx2_pmul_hr_sw>, VEX_4V;
5455 // None of these have i8 immediate fields.
5456 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5457 let isCommutable = 0 in {
5458 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5459 memopv2i64, i128mem, SSE_PHADDSUBW>;
5460 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5461 memopv2i64, i128mem, SSE_PHADDSUBD>;
5462 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5463 memopv2i64, i128mem, SSE_PHADDSUBW>;
5464 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5465 memopv2i64, i128mem, SSE_PHADDSUBD>;
5466 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5467 memopv2i64, i128mem, SSE_PSIGN>;
5468 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5469 memopv2i64, i128mem, SSE_PSIGN>;
5470 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5471 memopv2i64, i128mem, SSE_PSIGN>;
5472 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5473 memopv2i64, i128mem, SSE_PSHUFB>;
5474 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5475 int_x86_ssse3_phadd_sw_128,
5477 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5478 int_x86_ssse3_phsub_sw_128,
5480 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5481 int_x86_ssse3_pmadd_ub_sw_128, SSE_PMADD>;
5483 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5484 int_x86_ssse3_pmul_hr_sw_128,
5488 //===---------------------------------------------------------------------===//
5489 // SSSE3 - Packed Align Instruction Patterns
5490 //===---------------------------------------------------------------------===//
5492 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
5493 let neverHasSideEffects = 1 in {
5494 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5495 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5497 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5499 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5500 [], IIC_SSE_PALIGNR>, OpSize;
5502 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5503 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5505 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5507 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5508 [], IIC_SSE_PALIGNR>, OpSize;
5512 multiclass ssse3_palign_y<string asm, bit Is2Addr = 1> {
5513 let neverHasSideEffects = 1 in {
5514 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5515 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5517 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5520 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5521 (ins VR256:$src1, i256mem:$src2, i8imm:$src3),
5523 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5528 let Predicates = [HasAVX] in
5529 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
5530 let Predicates = [HasAVX2] in
5531 defm VPALIGN : ssse3_palign_y<"vpalignr", 0>, VEX_4V;
5532 let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
5533 defm PALIGN : ssse3_palign<"palignr">;
5535 let Predicates = [HasAVX2] in {
5536 def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5537 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5538 def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5539 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5540 def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5541 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5542 def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5543 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5546 let Predicates = [HasAVX] in {
5547 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5548 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5549 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5550 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5551 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5552 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5553 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5554 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5557 let Predicates = [HasSSSE3] in {
5558 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5559 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5560 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5561 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5562 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5563 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5564 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5565 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5568 //===---------------------------------------------------------------------===//
5569 // SSSE3 - Thread synchronization
5570 //===---------------------------------------------------------------------===//
5572 let usesCustomInserter = 1 in {
5573 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5574 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5575 Requires<[HasSSE3]>;
5576 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
5577 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>,
5578 Requires<[HasSSE3]>;
5581 let Uses = [EAX, ECX, EDX] in
5582 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5583 TB, Requires<[HasSSE3]>;
5584 let Uses = [ECX, EAX] in
5585 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", [], IIC_SSE_MWAIT>,
5586 TB, Requires<[HasSSE3]>;
5588 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
5589 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
5591 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
5592 Requires<[In32BitMode]>;
5593 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
5594 Requires<[In64BitMode]>;
5596 //===----------------------------------------------------------------------===//
5597 // SSE4.1 - Packed Move with Sign/Zero Extend
5598 //===----------------------------------------------------------------------===//
5600 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5601 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5602 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5603 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5605 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5606 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5608 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5612 multiclass SS41I_binop_rm_int16_y<bits<8> opc, string OpcodeStr,
5614 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5615 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5616 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5618 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
5619 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5620 [(set VR256:$dst, (IntId (load addr:$src)))]>, OpSize;
5623 let Predicates = [HasAVX] in {
5624 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
5626 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
5628 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
5630 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
5632 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
5634 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
5638 let Predicates = [HasAVX2] in {
5639 defm VPMOVSXBW : SS41I_binop_rm_int16_y<0x20, "vpmovsxbw",
5640 int_x86_avx2_pmovsxbw>, VEX;
5641 defm VPMOVSXWD : SS41I_binop_rm_int16_y<0x23, "vpmovsxwd",
5642 int_x86_avx2_pmovsxwd>, VEX;
5643 defm VPMOVSXDQ : SS41I_binop_rm_int16_y<0x25, "vpmovsxdq",
5644 int_x86_avx2_pmovsxdq>, VEX;
5645 defm VPMOVZXBW : SS41I_binop_rm_int16_y<0x30, "vpmovzxbw",
5646 int_x86_avx2_pmovzxbw>, VEX;
5647 defm VPMOVZXWD : SS41I_binop_rm_int16_y<0x33, "vpmovzxwd",
5648 int_x86_avx2_pmovzxwd>, VEX;
5649 defm VPMOVZXDQ : SS41I_binop_rm_int16_y<0x35, "vpmovzxdq",
5650 int_x86_avx2_pmovzxdq>, VEX;
5653 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
5654 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
5655 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
5656 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
5657 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
5658 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
5660 let Predicates = [HasAVX] in {
5661 // Common patterns involving scalar load.
5662 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5663 (VPMOVSXBWrm addr:$src)>;
5664 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5665 (VPMOVSXBWrm addr:$src)>;
5667 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5668 (VPMOVSXWDrm addr:$src)>;
5669 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5670 (VPMOVSXWDrm addr:$src)>;
5672 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5673 (VPMOVSXDQrm addr:$src)>;
5674 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5675 (VPMOVSXDQrm addr:$src)>;
5677 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5678 (VPMOVZXBWrm addr:$src)>;
5679 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5680 (VPMOVZXBWrm addr:$src)>;
5682 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5683 (VPMOVZXWDrm addr:$src)>;
5684 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5685 (VPMOVZXWDrm addr:$src)>;
5687 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5688 (VPMOVZXDQrm addr:$src)>;
5689 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5690 (VPMOVZXDQrm addr:$src)>;
5693 let Predicates = [HasSSE41] in {
5694 // Common patterns involving scalar load.
5695 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
5696 (PMOVSXBWrm addr:$src)>;
5697 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
5698 (PMOVSXBWrm addr:$src)>;
5700 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
5701 (PMOVSXWDrm addr:$src)>;
5702 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
5703 (PMOVSXWDrm addr:$src)>;
5705 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
5706 (PMOVSXDQrm addr:$src)>;
5707 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
5708 (PMOVSXDQrm addr:$src)>;
5710 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
5711 (PMOVZXBWrm addr:$src)>;
5712 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
5713 (PMOVZXBWrm addr:$src)>;
5715 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
5716 (PMOVZXWDrm addr:$src)>;
5717 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
5718 (PMOVZXWDrm addr:$src)>;
5720 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
5721 (PMOVZXDQrm addr:$src)>;
5722 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
5723 (PMOVZXDQrm addr:$src)>;
5726 let Predicates = [HasAVX2] in {
5727 let AddedComplexity = 15 in {
5728 def : Pat<(v4i64 (X86vzmovly (v4i32 VR128:$src))),
5729 (VPMOVZXDQYrr VR128:$src)>;
5730 def : Pat<(v8i32 (X86vzmovly (v8i16 VR128:$src))),
5731 (VPMOVZXWDYrr VR128:$src)>;
5734 def : Pat<(v4i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQYrr VR128:$src)>;
5735 def : Pat<(v8i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDYrr VR128:$src)>;
5738 let Predicates = [HasAVX] in {
5739 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (VPMOVSXDQrr VR128:$src)>;
5740 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (VPMOVSXWDrr VR128:$src)>;
5743 let Predicates = [HasSSE41] in {
5744 def : Pat<(v2i64 (X86vsmovl (v4i32 VR128:$src))), (PMOVSXDQrr VR128:$src)>;
5745 def : Pat<(v4i32 (X86vsmovl (v8i16 VR128:$src))), (PMOVSXWDrr VR128:$src)>;
5749 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5750 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5752 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5754 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
5755 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5757 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5761 multiclass SS41I_binop_rm_int8_y<bits<8> opc, string OpcodeStr,
5763 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5765 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5767 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i32mem:$src),
5768 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5770 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
5774 let Predicates = [HasAVX] in {
5775 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
5777 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
5779 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
5781 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
5785 let Predicates = [HasAVX2] in {
5786 defm VPMOVSXBD : SS41I_binop_rm_int8_y<0x21, "vpmovsxbd",
5787 int_x86_avx2_pmovsxbd>, VEX;
5788 defm VPMOVSXWQ : SS41I_binop_rm_int8_y<0x24, "vpmovsxwq",
5789 int_x86_avx2_pmovsxwq>, VEX;
5790 defm VPMOVZXBD : SS41I_binop_rm_int8_y<0x31, "vpmovzxbd",
5791 int_x86_avx2_pmovzxbd>, VEX;
5792 defm VPMOVZXWQ : SS41I_binop_rm_int8_y<0x34, "vpmovzxwq",
5793 int_x86_avx2_pmovzxwq>, VEX;
5796 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
5797 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
5798 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
5799 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
5801 let Predicates = [HasAVX] in {
5802 // Common patterns involving scalar load
5803 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5804 (VPMOVSXBDrm addr:$src)>;
5805 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5806 (VPMOVSXWQrm addr:$src)>;
5808 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5809 (VPMOVZXBDrm addr:$src)>;
5810 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5811 (VPMOVZXWQrm addr:$src)>;
5814 let Predicates = [HasSSE41] in {
5815 // Common patterns involving scalar load
5816 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
5817 (PMOVSXBDrm addr:$src)>;
5818 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
5819 (PMOVSXWQrm addr:$src)>;
5821 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
5822 (PMOVZXBDrm addr:$src)>;
5823 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
5824 (PMOVZXWQrm addr:$src)>;
5827 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
5828 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5829 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5830 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
5832 // Expecting a i16 load any extended to i32 value.
5833 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
5834 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5835 [(set VR128:$dst, (IntId (bitconvert
5836 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
5840 multiclass SS41I_binop_rm_int4_y<bits<8> opc, string OpcodeStr,
5842 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
5843 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5844 [(set VR256:$dst, (IntId VR128:$src))]>, OpSize;
5846 // Expecting a i16 load any extended to i32 value.
5847 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst), (ins i16mem:$src),
5848 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5849 [(set VR256:$dst, (IntId (bitconvert
5850 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
5854 let Predicates = [HasAVX] in {
5855 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
5857 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
5860 let Predicates = [HasAVX2] in {
5861 defm VPMOVSXBQ : SS41I_binop_rm_int4_y<0x22, "vpmovsxbq",
5862 int_x86_avx2_pmovsxbq>, VEX;
5863 defm VPMOVZXBQ : SS41I_binop_rm_int4_y<0x32, "vpmovzxbq",
5864 int_x86_avx2_pmovzxbq>, VEX;
5866 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
5867 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
5869 let Predicates = [HasAVX] in {
5870 // Common patterns involving scalar load
5871 def : Pat<(int_x86_sse41_pmovsxbq
5872 (bitconvert (v4i32 (X86vzmovl
5873 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5874 (VPMOVSXBQrm addr:$src)>;
5876 def : Pat<(int_x86_sse41_pmovzxbq
5877 (bitconvert (v4i32 (X86vzmovl
5878 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5879 (VPMOVZXBQrm addr:$src)>;
5882 let Predicates = [HasSSE41] in {
5883 // Common patterns involving scalar load
5884 def : Pat<(int_x86_sse41_pmovsxbq
5885 (bitconvert (v4i32 (X86vzmovl
5886 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5887 (PMOVSXBQrm addr:$src)>;
5889 def : Pat<(int_x86_sse41_pmovzxbq
5890 (bitconvert (v4i32 (X86vzmovl
5891 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
5892 (PMOVZXBQrm addr:$src)>;
5895 //===----------------------------------------------------------------------===//
5896 // SSE4.1 - Extract Instructions
5897 //===----------------------------------------------------------------------===//
5899 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
5900 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
5901 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5902 (ins VR128:$src1, i32i8imm:$src2),
5903 !strconcat(OpcodeStr,
5904 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5905 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
5907 let neverHasSideEffects = 1, mayStore = 1 in
5908 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5909 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
5910 !strconcat(OpcodeStr,
5911 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5914 // There's an AssertZext in the way of writing the store pattern
5915 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5918 let Predicates = [HasAVX] in {
5919 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
5920 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
5921 (ins VR128:$src1, i32i8imm:$src2),
5922 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
5925 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
5928 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
5929 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
5930 let neverHasSideEffects = 1, mayStore = 1 in
5931 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5932 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
5933 !strconcat(OpcodeStr,
5934 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5937 // There's an AssertZext in the way of writing the store pattern
5938 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
5941 let Predicates = [HasAVX] in
5942 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
5944 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
5947 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5948 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
5949 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5950 (ins VR128:$src1, i32i8imm:$src2),
5951 !strconcat(OpcodeStr,
5952 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5954 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
5955 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5956 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
5957 !strconcat(OpcodeStr,
5958 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5959 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
5960 addr:$dst)]>, OpSize;
5963 let Predicates = [HasAVX] in
5964 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
5966 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
5968 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
5969 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
5970 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
5971 (ins VR128:$src1, i32i8imm:$src2),
5972 !strconcat(OpcodeStr,
5973 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5975 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
5976 def mr : SS4AIi8<opc, MRMDestMem, (outs),
5977 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
5978 !strconcat(OpcodeStr,
5979 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5980 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
5981 addr:$dst)]>, OpSize, REX_W;
5984 let Predicates = [HasAVX] in
5985 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
5987 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
5989 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
5991 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
5992 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
5993 (ins VR128:$src1, i32i8imm:$src2),
5994 !strconcat(OpcodeStr,
5995 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5997 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
5999 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6000 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
6001 !strconcat(OpcodeStr,
6002 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6003 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6004 addr:$dst)]>, OpSize;
6007 let ExeDomain = SSEPackedSingle in {
6008 let Predicates = [HasAVX] in {
6009 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6010 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
6011 (ins VR128:$src1, i32i8imm:$src2),
6012 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
6015 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
6018 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6019 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6022 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6024 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6027 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6028 Requires<[HasSSE41]>;
6030 //===----------------------------------------------------------------------===//
6031 // SSE4.1 - Insert Instructions
6032 //===----------------------------------------------------------------------===//
6034 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6035 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6036 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6038 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6040 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6042 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
6043 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6044 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
6046 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6048 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6050 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6051 imm:$src3))]>, OpSize;
6054 let Predicates = [HasAVX] in
6055 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6056 let Constraints = "$src1 = $dst" in
6057 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6059 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6060 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6061 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
6063 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6065 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6067 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6069 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6070 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
6072 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6074 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6076 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6077 imm:$src3)))]>, OpSize;
6080 let Predicates = [HasAVX] in
6081 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6082 let Constraints = "$src1 = $dst" in
6083 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6085 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6086 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6087 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
6089 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6091 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6093 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6095 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6096 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
6098 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6100 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6102 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6103 imm:$src3)))]>, OpSize;
6106 let Predicates = [HasAVX] in
6107 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6108 let Constraints = "$src1 = $dst" in
6109 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6111 // insertps has a few different modes, there's the first two here below which
6112 // are optimized inserts that won't zero arbitrary elements in the destination
6113 // vector. The next one matches the intrinsic and could zero arbitrary elements
6114 // in the target vector.
6115 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
6116 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6117 (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),
6119 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6121 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6123 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
6125 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6126 (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),
6128 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6130 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6132 (X86insrtps VR128:$src1,
6133 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6134 imm:$src3))]>, OpSize;
6137 let ExeDomain = SSEPackedSingle in {
6138 let Predicates = [HasAVX] in
6139 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6140 let Constraints = "$src1 = $dst" in
6141 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
6144 //===----------------------------------------------------------------------===//
6145 // SSE4.1 - Round Instructions
6146 //===----------------------------------------------------------------------===//
6148 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6149 X86MemOperand x86memop, RegisterClass RC,
6150 PatFrag mem_frag32, PatFrag mem_frag64,
6151 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6152 let ExeDomain = SSEPackedSingle in {
6153 // Intrinsic operation, reg.
6154 // Vector intrinsic operation, reg
6155 def PSr : SS4AIi8<opcps, MRMSrcReg,
6156 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6157 !strconcat(OpcodeStr,
6158 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6159 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
6162 // Vector intrinsic operation, mem
6163 def PSm : SS4AIi8<opcps, MRMSrcMem,
6164 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6165 !strconcat(OpcodeStr,
6166 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6168 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
6170 } // ExeDomain = SSEPackedSingle
6172 let ExeDomain = SSEPackedDouble in {
6173 // Vector intrinsic operation, reg
6174 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6175 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
6176 !strconcat(OpcodeStr,
6177 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6178 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
6181 // Vector intrinsic operation, mem
6182 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6183 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
6184 !strconcat(OpcodeStr,
6185 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6187 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
6189 } // ExeDomain = SSEPackedDouble
6192 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6195 Intrinsic F64Int, bit Is2Addr = 1> {
6196 let ExeDomain = GenericDomain in {
6198 def SSr : SS4AIi8<opcss, MRMSrcReg,
6199 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32i8imm:$src3),
6201 !strconcat(OpcodeStr,
6202 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6203 !strconcat(OpcodeStr,
6204 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6207 // Intrinsic operation, reg.
6208 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6209 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6211 !strconcat(OpcodeStr,
6212 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6213 !strconcat(OpcodeStr,
6214 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6215 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6218 // Intrinsic operation, mem.
6219 def SSm : SS4AIi8<opcss, MRMSrcMem,
6220 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
6222 !strconcat(OpcodeStr,
6223 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6224 !strconcat(OpcodeStr,
6225 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6227 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6231 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6232 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32i8imm:$src3),
6234 !strconcat(OpcodeStr,
6235 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6236 !strconcat(OpcodeStr,
6237 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6240 // Intrinsic operation, reg.
6241 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6242 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
6244 !strconcat(OpcodeStr,
6245 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6246 !strconcat(OpcodeStr,
6247 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6248 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6251 // Intrinsic operation, mem.
6252 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6253 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
6255 !strconcat(OpcodeStr,
6256 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6257 !strconcat(OpcodeStr,
6258 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6260 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6262 } // ExeDomain = GenericDomain
6265 // FP round - roundss, roundps, roundsd, roundpd
6266 let Predicates = [HasAVX] in {
6268 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6269 memopv4f32, memopv2f64,
6270 int_x86_sse41_round_ps,
6271 int_x86_sse41_round_pd>, VEX;
6272 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6273 memopv8f32, memopv4f64,
6274 int_x86_avx_round_ps_256,
6275 int_x86_avx_round_pd_256>, VEX;
6276 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6277 int_x86_sse41_round_ss,
6278 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6280 def : Pat<(ffloor FR32:$src),
6281 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6282 def : Pat<(f64 (ffloor FR64:$src)),
6283 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6284 def : Pat<(f32 (fnearbyint FR32:$src)),
6285 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6286 def : Pat<(f64 (fnearbyint FR64:$src)),
6287 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6288 def : Pat<(f32 (fceil FR32:$src)),
6289 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6290 def : Pat<(f64 (fceil FR64:$src)),
6291 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6292 def : Pat<(f32 (frint FR32:$src)),
6293 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6294 def : Pat<(f64 (frint FR64:$src)),
6295 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6296 def : Pat<(f32 (ftrunc FR32:$src)),
6297 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6298 def : Pat<(f64 (ftrunc FR64:$src)),
6299 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6302 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6303 memopv4f32, memopv2f64,
6304 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6305 let Constraints = "$src1 = $dst" in
6306 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6307 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6309 def : Pat<(ffloor FR32:$src),
6310 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6311 def : Pat<(f64 (ffloor FR64:$src)),
6312 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6313 def : Pat<(f32 (fnearbyint FR32:$src)),
6314 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6315 def : Pat<(f64 (fnearbyint FR64:$src)),
6316 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6317 def : Pat<(f32 (fceil FR32:$src)),
6318 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6319 def : Pat<(f64 (fceil FR64:$src)),
6320 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6321 def : Pat<(f32 (frint FR32:$src)),
6322 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6323 def : Pat<(f64 (frint FR64:$src)),
6324 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6325 def : Pat<(f32 (ftrunc FR32:$src)),
6326 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6327 def : Pat<(f64 (ftrunc FR64:$src)),
6328 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6330 //===----------------------------------------------------------------------===//
6331 // SSE4.1 - Packed Bit Test
6332 //===----------------------------------------------------------------------===//
6334 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6335 // the intel intrinsic that corresponds to this.
6336 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6337 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6338 "vptest\t{$src2, $src1|$src1, $src2}",
6339 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6341 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6342 "vptest\t{$src2, $src1|$src1, $src2}",
6343 [(set EFLAGS,(X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6346 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6347 "vptest\t{$src2, $src1|$src1, $src2}",
6348 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6350 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6351 "vptest\t{$src2, $src1|$src1, $src2}",
6352 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
6356 let Defs = [EFLAGS] in {
6357 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6358 "ptest\t{$src2, $src1|$src1, $src2}",
6359 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6361 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6362 "ptest\t{$src2, $src1|$src1, $src2}",
6363 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6367 // The bit test instructions below are AVX only
6368 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6369 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6370 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6371 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6372 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
6373 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6374 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6375 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6379 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6380 let ExeDomain = SSEPackedSingle in {
6381 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
6382 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
6384 let ExeDomain = SSEPackedDouble in {
6385 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
6386 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
6390 //===----------------------------------------------------------------------===//
6391 // SSE4.1 - Misc Instructions
6392 //===----------------------------------------------------------------------===//
6394 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6395 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6396 "popcnt{w}\t{$src, $dst|$dst, $src}",
6397 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>,
6399 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6400 "popcnt{w}\t{$src, $dst|$dst, $src}",
6401 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6402 (implicit EFLAGS)]>, OpSize, XS;
6404 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6405 "popcnt{l}\t{$src, $dst|$dst, $src}",
6406 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>,
6408 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6409 "popcnt{l}\t{$src, $dst|$dst, $src}",
6410 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6411 (implicit EFLAGS)]>, XS;
6413 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6414 "popcnt{q}\t{$src, $dst|$dst, $src}",
6415 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>,
6417 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6418 "popcnt{q}\t{$src, $dst|$dst, $src}",
6419 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6420 (implicit EFLAGS)]>, XS;
6425 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6426 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6427 Intrinsic IntId128> {
6428 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6430 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6431 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
6432 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6434 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6437 (bitconvert (memopv2i64 addr:$src))))]>, OpSize;
6440 let Predicates = [HasAVX] in
6441 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6442 int_x86_sse41_phminposuw>, VEX;
6443 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6444 int_x86_sse41_phminposuw>;
6446 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6447 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
6448 Intrinsic IntId128, bit Is2Addr = 1> {
6449 let isCommutable = 1 in
6450 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6451 (ins VR128:$src1, VR128:$src2),
6453 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6454 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6455 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
6456 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6457 (ins VR128:$src1, i128mem:$src2),
6459 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6460 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6462 (IntId128 VR128:$src1,
6463 (bitconvert (memopv2i64 addr:$src2))))]>, OpSize;
6466 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
6467 multiclass SS41I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
6468 Intrinsic IntId256> {
6469 let isCommutable = 1 in
6470 def Yrr : SS48I<opc, MRMSrcReg, (outs VR256:$dst),
6471 (ins VR256:$src1, VR256:$src2),
6472 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6473 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>, OpSize;
6474 def Yrm : SS48I<opc, MRMSrcMem, (outs VR256:$dst),
6475 (ins VR256:$src1, i256mem:$src2),
6476 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6478 (IntId256 VR256:$src1,
6479 (bitconvert (memopv4i64 addr:$src2))))]>, OpSize;
6482 let Predicates = [HasAVX] in {
6483 let isCommutable = 0 in
6484 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
6486 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
6488 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
6490 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
6492 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
6494 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
6496 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
6498 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
6500 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
6502 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
6506 let Predicates = [HasAVX2] in {
6507 let isCommutable = 0 in
6508 defm VPACKUSDW : SS41I_binop_rm_int_y<0x2B, "vpackusdw",
6509 int_x86_avx2_packusdw>, VEX_4V;
6510 defm VPMINSB : SS41I_binop_rm_int_y<0x38, "vpminsb",
6511 int_x86_avx2_pmins_b>, VEX_4V;
6512 defm VPMINSD : SS41I_binop_rm_int_y<0x39, "vpminsd",
6513 int_x86_avx2_pmins_d>, VEX_4V;
6514 defm VPMINUD : SS41I_binop_rm_int_y<0x3B, "vpminud",
6515 int_x86_avx2_pminu_d>, VEX_4V;
6516 defm VPMINUW : SS41I_binop_rm_int_y<0x3A, "vpminuw",
6517 int_x86_avx2_pminu_w>, VEX_4V;
6518 defm VPMAXSB : SS41I_binop_rm_int_y<0x3C, "vpmaxsb",
6519 int_x86_avx2_pmaxs_b>, VEX_4V;
6520 defm VPMAXSD : SS41I_binop_rm_int_y<0x3D, "vpmaxsd",
6521 int_x86_avx2_pmaxs_d>, VEX_4V;
6522 defm VPMAXUD : SS41I_binop_rm_int_y<0x3F, "vpmaxud",
6523 int_x86_avx2_pmaxu_d>, VEX_4V;
6524 defm VPMAXUW : SS41I_binop_rm_int_y<0x3E, "vpmaxuw",
6525 int_x86_avx2_pmaxu_w>, VEX_4V;
6526 defm VPMULDQ : SS41I_binop_rm_int_y<0x28, "vpmuldq",
6527 int_x86_avx2_pmul_dq>, VEX_4V;
6530 let Constraints = "$src1 = $dst" in {
6531 let isCommutable = 0 in
6532 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
6533 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
6534 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
6535 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
6536 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
6537 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
6538 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
6539 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
6540 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
6541 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
6544 /// SS48I_binop_rm - Simple SSE41 binary operator.
6545 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6546 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6547 X86MemOperand x86memop, bit Is2Addr = 1> {
6548 let isCommutable = 1 in
6549 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6550 (ins RC:$src1, RC:$src2),
6552 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6553 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6554 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>, OpSize;
6555 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6556 (ins RC:$src1, x86memop:$src2),
6558 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6559 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6561 (OpVT (OpNode RC:$src1,
6562 (bitconvert (memop_frag addr:$src2)))))]>, OpSize;
6565 let Predicates = [HasAVX] in {
6566 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6567 memopv2i64, i128mem, 0>, VEX_4V;
6568 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6569 memopv2i64, i128mem, 0>, VEX_4V;
6571 let Predicates = [HasAVX2] in {
6572 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6573 memopv4i64, i256mem, 0>, VEX_4V;
6574 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6575 memopv4i64, i256mem, 0>, VEX_4V;
6578 let Constraints = "$src1 = $dst" in {
6579 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6580 memopv2i64, i128mem>;
6581 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6582 memopv2i64, i128mem>;
6585 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6586 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6587 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6588 X86MemOperand x86memop, bit Is2Addr = 1> {
6589 let isCommutable = 1 in
6590 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6591 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
6593 !strconcat(OpcodeStr,
6594 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6595 !strconcat(OpcodeStr,
6596 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6597 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
6599 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6600 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
6602 !strconcat(OpcodeStr,
6603 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6604 !strconcat(OpcodeStr,
6605 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6608 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
6612 let Predicates = [HasAVX] in {
6613 let isCommutable = 0 in {
6614 let ExeDomain = SSEPackedSingle in {
6615 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
6616 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6617 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
6618 int_x86_avx_blend_ps_256, VR256, memopv8f32, i256mem, 0>, VEX_4V;
6620 let ExeDomain = SSEPackedDouble in {
6621 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
6622 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6623 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
6624 int_x86_avx_blend_pd_256, VR256, memopv4f64, i256mem, 0>, VEX_4V;
6626 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
6627 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6628 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6629 VR128, memopv2i64, i128mem, 0>, VEX_4V;
6631 let ExeDomain = SSEPackedSingle in
6632 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
6633 VR128, memopv4f32, i128mem, 0>, VEX_4V;
6634 let ExeDomain = SSEPackedDouble in
6635 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
6636 VR128, memopv2f64, i128mem, 0>, VEX_4V;
6637 let ExeDomain = SSEPackedSingle in
6638 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
6639 VR256, memopv8f32, i256mem, 0>, VEX_4V;
6642 let Predicates = [HasAVX2] in {
6643 let isCommutable = 0 in {
6644 defm VPBLENDWY : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_avx2_pblendw,
6645 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6646 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
6647 VR256, memopv4i64, i256mem, 0>, VEX_4V;
6651 let Constraints = "$src1 = $dst" in {
6652 let isCommutable = 0 in {
6653 let ExeDomain = SSEPackedSingle in
6654 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
6655 VR128, memopv4f32, i128mem>;
6656 let ExeDomain = SSEPackedDouble in
6657 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
6658 VR128, memopv2f64, i128mem>;
6659 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
6660 VR128, memopv2i64, i128mem>;
6661 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
6662 VR128, memopv2i64, i128mem>;
6664 let ExeDomain = SSEPackedSingle in
6665 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
6666 VR128, memopv4f32, i128mem>;
6667 let ExeDomain = SSEPackedDouble in
6668 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
6669 VR128, memopv2f64, i128mem>;
6672 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
6673 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
6674 RegisterClass RC, X86MemOperand x86memop,
6675 PatFrag mem_frag, Intrinsic IntId> {
6676 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
6677 (ins RC:$src1, RC:$src2, RC:$src3),
6678 !strconcat(OpcodeStr,
6679 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6680 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
6681 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6683 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
6684 (ins RC:$src1, x86memop:$src2, RC:$src3),
6685 !strconcat(OpcodeStr,
6686 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
6688 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
6690 IIC_DEFAULT, SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
6693 let Predicates = [HasAVX] in {
6694 let ExeDomain = SSEPackedDouble in {
6695 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
6696 memopv2f64, int_x86_sse41_blendvpd>;
6697 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
6698 memopv4f64, int_x86_avx_blendv_pd_256>;
6699 } // ExeDomain = SSEPackedDouble
6700 let ExeDomain = SSEPackedSingle in {
6701 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
6702 memopv4f32, int_x86_sse41_blendvps>;
6703 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
6704 memopv8f32, int_x86_avx_blendv_ps_256>;
6705 } // ExeDomain = SSEPackedSingle
6706 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
6707 memopv2i64, int_x86_sse41_pblendvb>;
6710 let Predicates = [HasAVX2] in {
6711 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
6712 memopv4i64, int_x86_avx2_pblendvb>;
6715 let Predicates = [HasAVX] in {
6716 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
6717 (v16i8 VR128:$src2))),
6718 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6719 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
6720 (v4i32 VR128:$src2))),
6721 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6722 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
6723 (v4f32 VR128:$src2))),
6724 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6725 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
6726 (v2i64 VR128:$src2))),
6727 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6728 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
6729 (v2f64 VR128:$src2))),
6730 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
6731 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
6732 (v8i32 VR256:$src2))),
6733 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6734 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
6735 (v8f32 VR256:$src2))),
6736 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6737 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
6738 (v4i64 VR256:$src2))),
6739 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6740 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
6741 (v4f64 VR256:$src2))),
6742 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6744 def : Pat<(v8f32 (X86Blendps (v8f32 VR256:$src1), (v8f32 VR256:$src2),
6746 (VBLENDPSYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6747 def : Pat<(v4f64 (X86Blendpd (v4f64 VR256:$src1), (v4f64 VR256:$src2),
6749 (VBLENDPDYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6751 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6753 (VPBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6754 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6756 (VBLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6757 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6759 (VBLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6762 let Predicates = [HasAVX2] in {
6763 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
6764 (v32i8 VR256:$src2))),
6765 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
6766 def : Pat<(v16i16 (X86Blendpw (v16i16 VR256:$src1), (v16i16 VR256:$src2),
6768 (VPBLENDWYrri VR256:$src2, VR256:$src1, imm:$mask)>;
6771 /// SS41I_ternary_int - SSE 4.1 ternary operator
6772 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
6773 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
6775 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6776 (ins VR128:$src1, VR128:$src2),
6777 !strconcat(OpcodeStr,
6778 "\t{$src2, $dst|$dst, $src2}"),
6779 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
6782 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6783 (ins VR128:$src1, i128mem:$src2),
6784 !strconcat(OpcodeStr,
6785 "\t{$src2, $dst|$dst, $src2}"),
6788 (bitconvert (mem_frag addr:$src2)), XMM0))]>, OpSize;
6792 let ExeDomain = SSEPackedDouble in
6793 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64,
6794 int_x86_sse41_blendvpd>;
6795 let ExeDomain = SSEPackedSingle in
6796 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32,
6797 int_x86_sse41_blendvps>;
6798 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64,
6799 int_x86_sse41_pblendvb>;
6801 let Predicates = [HasSSE41] in {
6802 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
6803 (v16i8 VR128:$src2))),
6804 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
6805 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
6806 (v4i32 VR128:$src2))),
6807 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6808 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
6809 (v4f32 VR128:$src2))),
6810 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
6811 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
6812 (v2i64 VR128:$src2))),
6813 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6814 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
6815 (v2f64 VR128:$src2))),
6816 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
6818 def : Pat<(v8i16 (X86Blendpw (v8i16 VR128:$src1), (v8i16 VR128:$src2),
6820 (PBLENDWrri VR128:$src2, VR128:$src1, imm:$mask)>;
6821 def : Pat<(v4f32 (X86Blendps (v4f32 VR128:$src1), (v4f32 VR128:$src2),
6823 (BLENDPSrri VR128:$src2, VR128:$src1, imm:$mask)>;
6824 def : Pat<(v2f64 (X86Blendpd (v2f64 VR128:$src1), (v2f64 VR128:$src2),
6826 (BLENDPDrri VR128:$src2, VR128:$src1, imm:$mask)>;
6830 let Predicates = [HasAVX] in
6831 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6832 "vmovntdqa\t{$src, $dst|$dst, $src}",
6833 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6835 let Predicates = [HasAVX2] in
6836 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
6837 "vmovntdqa\t{$src, $dst|$dst, $src}",
6838 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
6840 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
6841 "movntdqa\t{$src, $dst|$dst, $src}",
6842 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
6845 //===----------------------------------------------------------------------===//
6846 // SSE4.2 - Compare Instructions
6847 //===----------------------------------------------------------------------===//
6849 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
6850 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6851 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6852 X86MemOperand x86memop, bit Is2Addr = 1> {
6853 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
6854 (ins RC:$src1, RC:$src2),
6856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6857 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6858 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6860 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
6861 (ins RC:$src1, x86memop:$src2),
6863 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6864 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6866 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>, OpSize;
6869 let Predicates = [HasAVX] in
6870 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
6871 memopv2i64, i128mem, 0>, VEX_4V;
6873 let Predicates = [HasAVX2] in
6874 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
6875 memopv4i64, i256mem, 0>, VEX_4V;
6877 let Constraints = "$src1 = $dst" in
6878 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
6879 memopv2i64, i128mem>;
6881 //===----------------------------------------------------------------------===//
6882 // SSE4.2 - String/text Processing Instructions
6883 //===----------------------------------------------------------------------===//
6885 // Packed Compare Implicit Length Strings, Return Mask
6886 multiclass pseudo_pcmpistrm<string asm> {
6887 def REG : PseudoI<(outs VR128:$dst),
6888 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6889 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
6891 def MEM : PseudoI<(outs VR128:$dst),
6892 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6893 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
6894 VR128:$src1, (load addr:$src2), imm:$src3))]>;
6897 let Defs = [EFLAGS], usesCustomInserter = 1 in {
6898 let AddedComplexity = 1 in
6899 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
6900 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
6903 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1, Predicates = [HasAVX] in {
6904 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6905 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6906 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6908 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6909 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6910 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
6913 let Defs = [XMM0, EFLAGS], neverHasSideEffects = 1 in {
6914 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
6915 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6916 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6918 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
6919 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6920 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
6923 // Packed Compare Explicit Length Strings, Return Mask
6924 multiclass pseudo_pcmpestrm<string asm> {
6925 def REG : PseudoI<(outs VR128:$dst),
6926 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6927 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6928 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
6929 def MEM : PseudoI<(outs VR128:$dst),
6930 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6931 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
6932 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
6935 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
6936 let AddedComplexity = 1 in
6937 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
6938 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
6941 let Predicates = [HasAVX],
6942 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6943 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6944 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6945 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6947 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6948 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6949 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
6952 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], neverHasSideEffects = 1 in {
6953 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
6954 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
6955 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6957 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
6958 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
6959 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
6962 // Packed Compare Implicit Length Strings, Return Index
6963 let Defs = [ECX, EFLAGS] in {
6964 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
6965 def rr : SS42AI<0x63, MRMSrcReg, (outs),
6966 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
6967 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6968 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
6969 (implicit EFLAGS)]>, OpSize;
6970 def rm : SS42AI<0x63, MRMSrcMem, (outs),
6971 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
6972 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
6973 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
6974 (implicit EFLAGS)]>, OpSize;
6978 let Predicates = [HasAVX] in {
6979 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
6981 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
6983 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
6985 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
6987 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
6989 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
6993 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
6994 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
6995 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
6996 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
6997 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
6998 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
7000 // Packed Compare Explicit Length Strings, Return Index
7001 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
7002 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
7003 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7004 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
7005 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7006 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
7007 (implicit EFLAGS)]>, OpSize;
7008 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7009 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
7010 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7012 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
7013 (implicit EFLAGS)]>, OpSize;
7017 let Predicates = [HasAVX] in {
7018 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
7020 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
7022 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
7024 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
7026 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
7028 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
7032 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
7033 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
7034 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
7035 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
7036 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
7037 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
7039 //===----------------------------------------------------------------------===//
7040 // SSE4.2 - CRC Instructions
7041 //===----------------------------------------------------------------------===//
7043 // No CRC instructions have AVX equivalents
7045 // crc intrinsic instruction
7046 // This set of instructions are only rm, the only difference is the size
7048 let Constraints = "$src1 = $dst" in {
7049 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
7050 (ins GR32:$src1, i8mem:$src2),
7051 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7053 (int_x86_sse42_crc32_32_8 GR32:$src1,
7054 (load addr:$src2)))]>;
7055 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
7056 (ins GR32:$src1, GR8:$src2),
7057 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7059 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
7060 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7061 (ins GR32:$src1, i16mem:$src2),
7062 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7064 (int_x86_sse42_crc32_32_16 GR32:$src1,
7065 (load addr:$src2)))]>,
7067 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7068 (ins GR32:$src1, GR16:$src2),
7069 "crc32{w} \t{$src2, $src1|$src1, $src2}",
7071 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
7073 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
7074 (ins GR32:$src1, i32mem:$src2),
7075 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7077 (int_x86_sse42_crc32_32_32 GR32:$src1,
7078 (load addr:$src2)))]>;
7079 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
7080 (ins GR32:$src1, GR32:$src2),
7081 "crc32{l} \t{$src2, $src1|$src1, $src2}",
7083 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
7084 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
7085 (ins GR64:$src1, i8mem:$src2),
7086 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7088 (int_x86_sse42_crc32_64_8 GR64:$src1,
7089 (load addr:$src2)))]>,
7091 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
7092 (ins GR64:$src1, GR8:$src2),
7093 "crc32{b} \t{$src2, $src1|$src1, $src2}",
7095 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
7097 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
7098 (ins GR64:$src1, i64mem:$src2),
7099 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7101 (int_x86_sse42_crc32_64_64 GR64:$src1,
7102 (load addr:$src2)))]>,
7104 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
7105 (ins GR64:$src1, GR64:$src2),
7106 "crc32{q} \t{$src2, $src1|$src1, $src2}",
7108 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
7112 //===----------------------------------------------------------------------===//
7113 // AES-NI Instructions
7114 //===----------------------------------------------------------------------===//
7116 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
7117 Intrinsic IntId128, bit Is2Addr = 1> {
7118 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7119 (ins VR128:$src1, VR128:$src2),
7121 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7122 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7123 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7125 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7126 (ins VR128:$src1, i128mem:$src2),
7128 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7129 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7131 (IntId128 VR128:$src1, (memopv2i64 addr:$src2)))]>, OpSize;
7134 // Perform One Round of an AES Encryption/Decryption Flow
7135 let Predicates = [HasAVX, HasAES] in {
7136 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7137 int_x86_aesni_aesenc, 0>, VEX_4V;
7138 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7139 int_x86_aesni_aesenclast, 0>, VEX_4V;
7140 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7141 int_x86_aesni_aesdec, 0>, VEX_4V;
7142 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7143 int_x86_aesni_aesdeclast, 0>, VEX_4V;
7146 let Constraints = "$src1 = $dst" in {
7147 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7148 int_x86_aesni_aesenc>;
7149 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7150 int_x86_aesni_aesenclast>;
7151 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7152 int_x86_aesni_aesdec>;
7153 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7154 int_x86_aesni_aesdeclast>;
7157 // Perform the AES InvMixColumn Transformation
7158 let Predicates = [HasAVX, HasAES] in {
7159 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7161 "vaesimc\t{$src1, $dst|$dst, $src1}",
7163 (int_x86_aesni_aesimc VR128:$src1))]>,
7165 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7166 (ins i128mem:$src1),
7167 "vaesimc\t{$src1, $dst|$dst, $src1}",
7168 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7171 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7173 "aesimc\t{$src1, $dst|$dst, $src1}",
7175 (int_x86_aesni_aesimc VR128:$src1))]>,
7177 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7178 (ins i128mem:$src1),
7179 "aesimc\t{$src1, $dst|$dst, $src1}",
7180 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7183 // AES Round Key Generation Assist
7184 let Predicates = [HasAVX, HasAES] in {
7185 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7186 (ins VR128:$src1, i8imm:$src2),
7187 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7189 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7191 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7192 (ins i128mem:$src1, i8imm:$src2),
7193 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7195 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7198 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7199 (ins VR128:$src1, i8imm:$src2),
7200 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7202 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7204 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7205 (ins i128mem:$src1, i8imm:$src2),
7206 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7208 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7211 //===----------------------------------------------------------------------===//
7212 // PCLMUL Instructions
7213 //===----------------------------------------------------------------------===//
7215 // AVX carry-less Multiplication instructions
7216 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7217 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7218 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7220 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7222 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7223 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7224 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7225 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7226 (memopv2i64 addr:$src2), imm:$src3))]>;
7228 // Carry-less Multiplication instructions
7229 let Constraints = "$src1 = $dst" in {
7230 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7231 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
7232 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7234 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>;
7236 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7237 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
7238 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7239 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7240 (memopv2i64 addr:$src2), imm:$src3))]>;
7241 } // Constraints = "$src1 = $dst"
7244 multiclass pclmul_alias<string asm, int immop> {
7245 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7246 (PCLMULQDQrr VR128:$dst, VR128:$src, immop)>;
7248 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7249 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop)>;
7251 def : InstAlias<!strconcat("vpclmul", asm,
7252 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7253 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop)>;
7255 def : InstAlias<!strconcat("vpclmul", asm,
7256 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7257 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop)>;
7259 defm : pclmul_alias<"hqhq", 0x11>;
7260 defm : pclmul_alias<"hqlq", 0x01>;
7261 defm : pclmul_alias<"lqhq", 0x10>;
7262 defm : pclmul_alias<"lqlq", 0x00>;
7264 //===----------------------------------------------------------------------===//
7265 // SSE4A Instructions
7266 //===----------------------------------------------------------------------===//
7268 let Predicates = [HasSSE4A] in {
7270 let Constraints = "$src = $dst" in {
7271 def EXTRQI : Ii8<0x78, MRM0r, (outs VR128:$dst),
7272 (ins VR128:$src, i8imm:$len, i8imm:$idx),
7273 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7274 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7275 imm:$idx))]>, TB, OpSize;
7276 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7277 (ins VR128:$src, VR128:$mask),
7278 "extrq\t{$mask, $src|$src, $mask}",
7279 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7280 VR128:$mask))]>, TB, OpSize;
7282 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7283 (ins VR128:$src, VR128:$src2, i8imm:$len, i8imm:$idx),
7284 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7285 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7286 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7287 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7288 (ins VR128:$src, VR128:$mask),
7289 "insertq\t{$mask, $src|$src, $mask}",
7290 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7291 VR128:$mask))]>, XD;
7294 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7295 "movntss\t{$src, $dst|$dst, $src}",
7296 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7298 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7299 "movntsd\t{$src, $dst|$dst, $src}",
7300 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7303 //===----------------------------------------------------------------------===//
7305 //===----------------------------------------------------------------------===//
7307 //===----------------------------------------------------------------------===//
7308 // VBROADCAST - Load from memory and broadcast to all elements of the
7309 // destination operand
7311 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7312 X86MemOperand x86memop, Intrinsic Int> :
7313 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7314 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7315 [(set RC:$dst, (Int addr:$src))]>, VEX;
7317 // AVX2 adds register forms
7318 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7320 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7321 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7322 [(set RC:$dst, (Int VR128:$src))]>, VEX;
7324 let ExeDomain = SSEPackedSingle in {
7325 def VBROADCASTSSrm : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
7326 int_x86_avx_vbroadcast_ss>;
7327 def VBROADCASTSSYrm : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
7328 int_x86_avx_vbroadcast_ss_256>;
7330 let ExeDomain = SSEPackedDouble in
7331 def VBROADCASTSDrm : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
7332 int_x86_avx_vbroadcast_sd_256>;
7333 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7334 int_x86_avx_vbroadcastf128_pd_256>;
7336 let ExeDomain = SSEPackedSingle in {
7337 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7338 int_x86_avx2_vbroadcast_ss_ps>;
7339 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7340 int_x86_avx2_vbroadcast_ss_ps_256>;
7342 let ExeDomain = SSEPackedDouble in
7343 def VBROADCASTSDrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7344 int_x86_avx2_vbroadcast_sd_pd_256>;
7346 let Predicates = [HasAVX2] in
7347 def VBROADCASTI128 : avx_broadcast<0x5A, "vbroadcasti128", VR256, i128mem,
7348 int_x86_avx2_vbroadcasti128>;
7350 let Predicates = [HasAVX] in
7351 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7352 (VBROADCASTF128 addr:$src)>;
7355 //===----------------------------------------------------------------------===//
7356 // VINSERTF128 - Insert packed floating-point values
7358 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7359 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7360 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7361 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7364 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7365 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
7366 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7370 let Predicates = [HasAVX] in {
7371 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7373 (VINSERTF128rr VR256:$src1, VR128:$src2,
7374 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7375 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7377 (VINSERTF128rr VR256:$src1, VR128:$src2,
7378 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7379 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7381 (VINSERTF128rr VR256:$src1, VR128:$src2,
7382 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7383 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7385 (VINSERTF128rr VR256:$src1, VR128:$src2,
7386 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7387 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7389 (VINSERTF128rr VR256:$src1, VR128:$src2,
7390 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7391 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7393 (VINSERTF128rr VR256:$src1, VR128:$src2,
7394 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7396 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7398 (VINSERTF128rm VR256:$src1, addr:$src2,
7399 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7400 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7402 (VINSERTF128rm VR256:$src1, addr:$src2,
7403 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7404 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7406 (VINSERTF128rm VR256:$src1, addr:$src2,
7407 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7410 //===----------------------------------------------------------------------===//
7411 // VEXTRACTF128 - Extract packed floating-point values
7413 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
7414 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7415 (ins VR256:$src1, i8imm:$src2),
7416 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7419 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7420 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
7421 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7425 // Extract and store.
7426 let Predicates = [HasAVX] in {
7427 def : Pat<(alignedstore (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2), addr:$dst),
7428 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7429 def : Pat<(alignedstore (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2), addr:$dst),
7430 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7431 def : Pat<(alignedstore (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2), addr:$dst),
7432 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7434 def : Pat<(int_x86_sse_storeu_ps addr:$dst, (int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2)),
7435 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7436 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, (int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2)),
7437 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7438 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, (bc_v16i8 (int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2))),
7439 (VEXTRACTF128mr addr:$dst, VR256:$src1, imm:$src2)>;
7443 let Predicates = [HasAVX] in {
7444 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
7445 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7446 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
7447 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7448 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
7449 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
7451 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7452 (v4f32 (VEXTRACTF128rr
7453 (v8f32 VR256:$src1),
7454 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7455 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7456 (v2f64 (VEXTRACTF128rr
7457 (v4f64 VR256:$src1),
7458 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7459 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7460 (v2i64 (VEXTRACTF128rr
7461 (v4i64 VR256:$src1),
7462 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7463 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7464 (v4i32 (VEXTRACTF128rr
7465 (v8i32 VR256:$src1),
7466 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7467 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7468 (v8i16 (VEXTRACTF128rr
7469 (v16i16 VR256:$src1),
7470 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7471 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7472 (v16i8 (VEXTRACTF128rr
7473 (v32i8 VR256:$src1),
7474 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7477 //===----------------------------------------------------------------------===//
7478 // VMASKMOV - Conditional SIMD Packed Loads and Stores
7480 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
7481 Intrinsic IntLd, Intrinsic IntLd256,
7482 Intrinsic IntSt, Intrinsic IntSt256> {
7483 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
7484 (ins VR128:$src1, f128mem:$src2),
7485 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7486 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
7488 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
7489 (ins VR256:$src1, f256mem:$src2),
7490 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7491 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
7493 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
7494 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
7495 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7496 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
7497 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
7498 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
7499 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7500 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
7503 let ExeDomain = SSEPackedSingle in
7504 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
7505 int_x86_avx_maskload_ps,
7506 int_x86_avx_maskload_ps_256,
7507 int_x86_avx_maskstore_ps,
7508 int_x86_avx_maskstore_ps_256>;
7509 let ExeDomain = SSEPackedDouble in
7510 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
7511 int_x86_avx_maskload_pd,
7512 int_x86_avx_maskload_pd_256,
7513 int_x86_avx_maskstore_pd,
7514 int_x86_avx_maskstore_pd_256>;
7516 //===----------------------------------------------------------------------===//
7517 // VPERMIL - Permute Single and Double Floating-Point Values
7519 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
7520 RegisterClass RC, X86MemOperand x86memop_f,
7521 X86MemOperand x86memop_i, PatFrag i_frag,
7522 Intrinsic IntVar, ValueType vt> {
7523 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
7524 (ins RC:$src1, RC:$src2),
7525 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7526 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
7527 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
7528 (ins RC:$src1, x86memop_i:$src2),
7529 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7530 [(set RC:$dst, (IntVar RC:$src1,
7531 (bitconvert (i_frag addr:$src2))))]>, VEX_4V;
7533 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
7534 (ins RC:$src1, i8imm:$src2),
7535 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7536 [(set RC:$dst, (vt (X86VPermilp RC:$src1, (i8 imm:$src2))))]>, VEX;
7537 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
7538 (ins x86memop_f:$src1, i8imm:$src2),
7539 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7541 (vt (X86VPermilp (memop addr:$src1), (i8 imm:$src2))))]>, VEX;
7544 let ExeDomain = SSEPackedSingle in {
7545 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
7546 memopv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
7547 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
7548 memopv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>;
7550 let ExeDomain = SSEPackedDouble in {
7551 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
7552 memopv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
7553 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
7554 memopv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>;
7557 let Predicates = [HasAVX] in {
7558 def : Pat<(v8i32 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7559 (VPERMILPSYri VR256:$src1, imm:$imm)>;
7560 def : Pat<(v4i64 (X86VPermilp VR256:$src1, (i8 imm:$imm))),
7561 (VPERMILPDYri VR256:$src1, imm:$imm)>;
7562 def : Pat<(v8i32 (X86VPermilp (bc_v8i32 (memopv4i64 addr:$src1)),
7564 (VPERMILPSYmi addr:$src1, imm:$imm)>;
7565 def : Pat<(v4i64 (X86VPermilp (memopv4i64 addr:$src1), (i8 imm:$imm))),
7566 (VPERMILPDYmi addr:$src1, imm:$imm)>;
7568 def : Pat<(v2i64 (X86VPermilp VR128:$src1, (i8 imm:$imm))),
7569 (VPERMILPDri VR128:$src1, imm:$imm)>;
7570 def : Pat<(v2i64 (X86VPermilp (memopv2i64 addr:$src1), (i8 imm:$imm))),
7571 (VPERMILPDmi addr:$src1, imm:$imm)>;
7574 //===----------------------------------------------------------------------===//
7575 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
7577 let ExeDomain = SSEPackedSingle in {
7578 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
7579 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7580 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7581 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7582 (i8 imm:$src3))))]>, VEX_4V;
7583 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
7584 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7585 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7586 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv8f32 addr:$src2),
7587 (i8 imm:$src3)))]>, VEX_4V;
7590 let Predicates = [HasAVX] in {
7591 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7592 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7593 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7594 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7595 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7596 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7597 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7598 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7599 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7600 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7602 def : Pat<(v8f32 (X86VPerm2x128 VR256:$src1,
7603 (memopv8f32 addr:$src2), (i8 imm:$imm))),
7604 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7605 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
7606 (bc_v8i32 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7607 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7608 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
7609 (memopv4i64 addr:$src2), (i8 imm:$imm))),
7610 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7611 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
7612 (memopv4f64 addr:$src2), (i8 imm:$imm))),
7613 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7614 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
7615 (bc_v32i8 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7616 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7617 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7618 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7619 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
7622 //===----------------------------------------------------------------------===//
7623 // VZERO - Zero YMM registers
7625 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
7626 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
7627 // Zero All YMM registers
7628 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
7629 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
7631 // Zero Upper bits of YMM registers
7632 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
7633 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
7636 //===----------------------------------------------------------------------===//
7637 // Half precision conversion instructions
7638 //===----------------------------------------------------------------------===//
7639 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7640 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7641 "vcvtph2ps\t{$src, $dst|$dst, $src}",
7642 [(set RC:$dst, (Int VR128:$src))]>,
7644 let neverHasSideEffects = 1, mayLoad = 1 in
7645 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7646 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
7649 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
7650 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
7651 (ins RC:$src1, i32i8imm:$src2),
7652 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7653 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
7655 let neverHasSideEffects = 1, mayStore = 1 in
7656 def mr : Ii8<0x1D, MRMDestMem, (outs),
7657 (ins x86memop:$dst, RC:$src1, i32i8imm:$src2),
7658 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
7662 let Predicates = [HasAVX, HasF16C] in {
7663 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
7664 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>;
7665 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
7666 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>;
7669 //===----------------------------------------------------------------------===//
7670 // AVX2 Instructions
7671 //===----------------------------------------------------------------------===//
7673 /// AVX2_binop_rmi_int - AVX2 binary operator with 8-bit immediate
7674 multiclass AVX2_binop_rmi_int<bits<8> opc, string OpcodeStr,
7675 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
7676 X86MemOperand x86memop> {
7677 let isCommutable = 1 in
7678 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
7679 (ins RC:$src1, RC:$src2, u32u8imm:$src3),
7680 !strconcat(OpcodeStr,
7681 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7682 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
7684 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
7685 (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),
7686 !strconcat(OpcodeStr,
7687 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7690 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
7694 let isCommutable = 0 in {
7695 defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,
7696 VR128, memopv2i64, i128mem>;
7697 defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,
7698 VR256, memopv4i64, i256mem>;
7701 //===----------------------------------------------------------------------===//
7702 // VPBROADCAST - Load from memory and broadcast to all elements of the
7703 // destination operand
7705 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
7706 X86MemOperand x86memop, PatFrag ld_frag,
7707 Intrinsic Int128, Intrinsic Int256> {
7708 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
7709 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7710 [(set VR128:$dst, (Int128 VR128:$src))]>, VEX;
7711 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
7712 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7714 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7715 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
7716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7717 [(set VR256:$dst, (Int256 VR128:$src))]>, VEX;
7718 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
7719 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7721 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>, VEX;
7724 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
7725 int_x86_avx2_pbroadcastb_128,
7726 int_x86_avx2_pbroadcastb_256>;
7727 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
7728 int_x86_avx2_pbroadcastw_128,
7729 int_x86_avx2_pbroadcastw_256>;
7730 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
7731 int_x86_avx2_pbroadcastd_128,
7732 int_x86_avx2_pbroadcastd_256>;
7733 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
7734 int_x86_avx2_pbroadcastq_128,
7735 int_x86_avx2_pbroadcastq_256>;
7737 let Predicates = [HasAVX2] in {
7738 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
7739 (VPBROADCASTBrm addr:$src)>;
7740 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
7741 (VPBROADCASTBYrm addr:$src)>;
7742 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
7743 (VPBROADCASTWrm addr:$src)>;
7744 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
7745 (VPBROADCASTWYrm addr:$src)>;
7746 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7747 (VPBROADCASTDrm addr:$src)>;
7748 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7749 (VPBROADCASTDYrm addr:$src)>;
7750 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
7751 (VPBROADCASTQrm addr:$src)>;
7752 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7753 (VPBROADCASTQYrm addr:$src)>;
7755 // Provide fallback in case the load node that is used in the patterns above
7756 // is used by additional users, which prevents the pattern selection.
7757 let AddedComplexity = 20 in {
7758 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7760 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7761 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7763 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss))>;
7764 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7766 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd))>;
7768 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7770 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7771 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7773 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss))>;
7774 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7776 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd))>;
7780 // AVX1 broadcast patterns
7781 let Predicates = [HasAVX] in {
7782 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
7783 (VBROADCASTSSYrm addr:$src)>;
7784 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
7785 (VBROADCASTSDrm addr:$src)>;
7786 def : Pat<(v8f32 (X86VBroadcast (loadf32 addr:$src))),
7787 (VBROADCASTSSYrm addr:$src)>;
7788 def : Pat<(v4f64 (X86VBroadcast (loadf64 addr:$src))),
7789 (VBROADCASTSDrm addr:$src)>;
7790 def : Pat<(v4f32 (X86VBroadcast (loadf32 addr:$src))),
7791 (VBROADCASTSSrm addr:$src)>;
7792 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
7793 (VBROADCASTSSrm addr:$src)>;
7795 // Provide fallback in case the load node that is used in the patterns above
7796 // is used by additional users, which prevents the pattern selection.
7797 let AddedComplexity = 20 in {
7798 // 128bit broadcasts:
7799 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
7801 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0)>;
7802 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
7803 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
7805 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss), 0),
7808 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss),
7810 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
7811 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
7813 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd), 0),
7816 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd),
7819 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
7821 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0)>;
7822 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
7823 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
7825 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss), 0),
7828 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), GR32:$src, sub_ss),
7830 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
7831 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
7833 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd), 0),
7836 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), GR64:$src, sub_sd),
7841 //===----------------------------------------------------------------------===//
7842 // VPERM - Permute instructions
7845 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7847 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
7848 (ins VR256:$src1, VR256:$src2),
7849 !strconcat(OpcodeStr,
7850 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7852 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>, VEX_4V;
7853 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
7854 (ins VR256:$src1, i256mem:$src2),
7855 !strconcat(OpcodeStr,
7856 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7858 (OpVT (X86VPermv VR256:$src1,
7859 (bitconvert (mem_frag addr:$src2)))))]>,
7863 defm VPERMD : avx2_perm<0x36, "vpermd", memopv4i64, v8i32>;
7864 let ExeDomain = SSEPackedSingle in
7865 defm VPERMPS : avx2_perm<0x16, "vpermps", memopv8f32, v8f32>;
7867 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7869 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
7870 (ins VR256:$src1, i8imm:$src2),
7871 !strconcat(OpcodeStr,
7872 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7874 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>, VEX;
7875 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
7876 (ins i256mem:$src1, i8imm:$src2),
7877 !strconcat(OpcodeStr,
7878 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
7880 (OpVT (X86VPermi (mem_frag addr:$src1),
7881 (i8 imm:$src2))))]>, VEX;
7884 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", memopv4i64, v4i64>, VEX_W;
7885 let ExeDomain = SSEPackedDouble in
7886 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", memopv4f64, v4f64>, VEX_W;
7888 //===----------------------------------------------------------------------===//
7889 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
7891 let AddedComplexity = 1 in {
7892 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
7893 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
7894 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7895 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
7896 (i8 imm:$src3))))]>, VEX_4V;
7897 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
7898 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
7899 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7900 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (memopv4i64 addr:$src2),
7901 (i8 imm:$src3)))]>, VEX_4V;
7904 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7905 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7906 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7907 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7908 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7909 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
7910 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
7912 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (memopv4i64 addr:$src2)),
7914 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7915 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
7916 (bc_v16i16 (memopv4i64 addr:$src2)), (i8 imm:$imm))),
7917 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7918 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (memopv4i64 addr:$src2)),
7920 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
7924 //===----------------------------------------------------------------------===//
7925 // VINSERTI128 - Insert packed integer values
7927 let neverHasSideEffects = 1 in {
7928 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
7929 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
7930 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7933 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
7934 (ins VR256:$src1, i128mem:$src2, i8imm:$src3),
7935 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7939 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7940 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7942 (VINSERTI128rr VR256:$src1, VR128:$src2,
7943 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7944 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7946 (VINSERTI128rr VR256:$src1, VR128:$src2,
7947 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7948 def : Pat<(vinsertf128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7950 (VINSERTI128rr VR256:$src1, VR128:$src2,
7951 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7952 def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7954 (VINSERTI128rr VR256:$src1, VR128:$src2,
7955 (INSERT_get_vinsertf128_imm VR256:$ins))>;
7958 //===----------------------------------------------------------------------===//
7959 // VEXTRACTI128 - Extract packed integer values
7961 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
7962 (ins VR256:$src1, i8imm:$src2),
7963 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7965 (int_x86_avx2_vextracti128 VR256:$src1, imm:$src2))]>,
7967 let neverHasSideEffects = 1, mayStore = 1 in
7968 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
7969 (ins i128mem:$dst, VR256:$src1, i8imm:$src2),
7970 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, VEX;
7972 let Predicates = [HasAVX2], AddedComplexity = 1 in {
7973 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7974 (v2i64 (VEXTRACTI128rr
7975 (v4i64 VR256:$src1),
7976 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7977 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7978 (v4i32 (VEXTRACTI128rr
7979 (v8i32 VR256:$src1),
7980 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7981 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7982 (v8i16 (VEXTRACTI128rr
7983 (v16i16 VR256:$src1),
7984 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7985 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
7986 (v16i8 (VEXTRACTI128rr
7987 (v32i8 VR256:$src1),
7988 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
7991 //===----------------------------------------------------------------------===//
7992 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
7994 multiclass avx2_pmovmask<string OpcodeStr,
7995 Intrinsic IntLd128, Intrinsic IntLd256,
7996 Intrinsic IntSt128, Intrinsic IntSt256> {
7997 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
7998 (ins VR128:$src1, i128mem:$src2),
7999 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8000 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8001 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8002 (ins VR256:$src1, i256mem:$src2),
8003 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8004 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>, VEX_4V;
8005 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8006 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8007 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8008 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8009 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8010 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8011 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8012 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
8015 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8016 int_x86_avx2_maskload_d,
8017 int_x86_avx2_maskload_d_256,
8018 int_x86_avx2_maskstore_d,
8019 int_x86_avx2_maskstore_d_256>;
8020 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8021 int_x86_avx2_maskload_q,
8022 int_x86_avx2_maskload_q_256,
8023 int_x86_avx2_maskstore_q,
8024 int_x86_avx2_maskstore_q_256>, VEX_W;
8027 //===----------------------------------------------------------------------===//
8028 // Variable Bit Shifts
8030 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8031 ValueType vt128, ValueType vt256> {
8032 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8033 (ins VR128:$src1, VR128:$src2),
8034 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8036 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8038 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8039 (ins VR128:$src1, i128mem:$src2),
8040 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8042 (vt128 (OpNode VR128:$src1,
8043 (vt128 (bitconvert (memopv2i64 addr:$src2))))))]>,
8045 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8046 (ins VR256:$src1, VR256:$src2),
8047 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8049 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8051 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8052 (ins VR256:$src1, i256mem:$src2),
8053 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8055 (vt256 (OpNode VR256:$src1,
8056 (vt256 (bitconvert (memopv4i64 addr:$src2))))))]>,
8060 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8061 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8062 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8063 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8064 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;