1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
92 return X86::isSplatMask(N);
95 def MOVLHPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVLHPSMask(N);
99 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHLPSMask(N);
103 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVHPMask(N);
107 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVLPMask(N);
111 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVSMask(N);
115 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVSHDUPMask(N);
119 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isMOVSLDUPMask(N);
123 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isUNPCKLMask(N);
127 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isUNPCKHMask(N);
131 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isUNPCKL_v_undef_Mask(N);
135 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFDMask(N);
137 }], SHUFFLE_get_shuf_imm>;
139 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isPSHUFHWMask(N);
141 }], SHUFFLE_get_pshufhw_imm>;
143 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isPSHUFLWMask(N);
145 }], SHUFFLE_get_pshuflw_imm>;
147 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isPSHUFDMask(N);
149 }], SHUFFLE_get_shuf_imm>;
151 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isSHUFPMask(N);
153 }], SHUFFLE_get_shuf_imm>;
155 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
156 return X86::isSHUFPMask(N);
157 }], SHUFFLE_get_shuf_imm>;
159 //===----------------------------------------------------------------------===//
160 // SSE scalar FP Instructions
161 //===----------------------------------------------------------------------===//
163 // Instruction templates
164 // SSI - SSE1 instructions with XS prefix.
165 // SDI - SSE2 instructions with XD prefix.
166 // PSI - SSE1 instructions with TB prefix.
167 // PDI - SSE2 instructions with TB and OpSize prefixes.
168 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
169 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
170 // S3I - SSE3 instructions with TB and OpSize prefixes.
171 // S3SI - SSE3 instructions with XS prefix.
172 // S3DI - SSE3 instructions with XD prefix.
173 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
174 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
175 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
176 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
177 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
178 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
179 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
180 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
181 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
182 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
183 let Pattern = pattern;
185 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
186 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
187 let Pattern = pattern;
189 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
190 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
191 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
192 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
193 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
194 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
196 //===----------------------------------------------------------------------===//
197 // Helpers for defining instructions that directly correspond to intrinsics.
198 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
199 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
200 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
201 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
202 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
203 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
204 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
205 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
206 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
207 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
208 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
209 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
211 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
212 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
213 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
214 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
215 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
216 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
217 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
218 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
219 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
220 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
221 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
222 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
224 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
225 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
226 [(set VR128:$dst, (IntId VR128:$src))]>;
227 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
228 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
229 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
230 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
231 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
232 [(set VR128:$dst, (IntId VR128:$src))]>;
233 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
234 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
235 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
237 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
238 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
239 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
240 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
241 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
242 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
243 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
244 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
245 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
246 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
247 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
248 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
250 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
251 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
252 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
253 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
254 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
255 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
256 (loadv4f32 addr:$src2))))]>;
257 class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
258 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
259 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
260 class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
261 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
262 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
263 (loadv2f64 addr:$src2))))]>;
265 // Some 'special' instructions
266 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
267 "#IMPLICIT_DEF $dst",
268 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
269 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
270 "#IMPLICIT_DEF $dst",
271 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
273 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
274 // scheduler into a branch sequence.
275 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
276 def CMOV_FR32 : I<0, Pseudo,
277 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
278 "#CMOV_FR32 PSEUDO!",
279 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
280 def CMOV_FR64 : I<0, Pseudo,
281 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
282 "#CMOV_FR64 PSEUDO!",
283 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
284 def CMOV_V4F32 : I<0, Pseudo,
285 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
286 "#CMOV_V4F32 PSEUDO!",
288 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
289 def CMOV_V2F64 : I<0, Pseudo,
290 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
291 "#CMOV_V2F64 PSEUDO!",
293 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
294 def CMOV_V2I64 : I<0, Pseudo,
295 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
296 "#CMOV_V2I64 PSEUDO!",
298 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
302 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
303 "movss {$src, $dst|$dst, $src}", []>;
304 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
305 "movss {$src, $dst|$dst, $src}",
306 [(set FR32:$dst, (loadf32 addr:$src))]>;
307 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
308 "movsd {$src, $dst|$dst, $src}", []>;
309 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
310 "movsd {$src, $dst|$dst, $src}",
311 [(set FR64:$dst, (loadf64 addr:$src))]>;
313 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
314 "movss {$src, $dst|$dst, $src}",
315 [(store FR32:$src, addr:$dst)]>;
316 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
317 "movsd {$src, $dst|$dst, $src}",
318 [(store FR64:$src, addr:$dst)]>;
320 // Arithmetic instructions
321 let isTwoAddress = 1 in {
322 let isCommutable = 1 in {
323 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
324 "addss {$src2, $dst|$dst, $src2}",
325 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
326 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
327 "addsd {$src2, $dst|$dst, $src2}",
328 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
329 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
330 "mulss {$src2, $dst|$dst, $src2}",
331 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
332 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
333 "mulsd {$src2, $dst|$dst, $src2}",
334 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
337 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
338 "addss {$src2, $dst|$dst, $src2}",
339 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
340 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
341 "addsd {$src2, $dst|$dst, $src2}",
342 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
343 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
344 "mulss {$src2, $dst|$dst, $src2}",
345 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
346 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
347 "mulsd {$src2, $dst|$dst, $src2}",
348 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
350 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
351 "divss {$src2, $dst|$dst, $src2}",
352 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
353 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
354 "divss {$src2, $dst|$dst, $src2}",
355 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
356 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
357 "divsd {$src2, $dst|$dst, $src2}",
358 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
359 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
360 "divsd {$src2, $dst|$dst, $src2}",
361 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
363 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
364 "subss {$src2, $dst|$dst, $src2}",
365 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
366 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
367 "subss {$src2, $dst|$dst, $src2}",
368 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
369 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
370 "subsd {$src2, $dst|$dst, $src2}",
371 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
372 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
373 "subsd {$src2, $dst|$dst, $src2}",
374 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
377 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
378 "sqrtss {$src, $dst|$dst, $src}",
379 [(set FR32:$dst, (fsqrt FR32:$src))]>;
380 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
381 "sqrtss {$src, $dst|$dst, $src}",
382 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
383 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
384 "sqrtsd {$src, $dst|$dst, $src}",
385 [(set FR64:$dst, (fsqrt FR64:$src))]>;
386 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
387 "sqrtsd {$src, $dst|$dst, $src}",
388 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
390 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
391 "rsqrtss {$src, $dst|$dst, $src}", []>;
392 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
393 "rsqrtss {$src, $dst|$dst, $src}", []>;
394 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
395 "rcpss {$src, $dst|$dst, $src}", []>;
396 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
397 "rcpss {$src, $dst|$dst, $src}", []>;
399 let isTwoAddress = 1 in {
400 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
401 "maxss {$src2, $dst|$dst, $src2}", []>;
402 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
403 "maxss {$src2, $dst|$dst, $src2}", []>;
404 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
405 "maxsd {$src2, $dst|$dst, $src2}", []>;
406 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
407 "maxsd {$src2, $dst|$dst, $src2}", []>;
408 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
409 "minss {$src2, $dst|$dst, $src2}", []>;
410 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
411 "minss {$src2, $dst|$dst, $src2}", []>;
412 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
413 "minsd {$src2, $dst|$dst, $src2}", []>;
414 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
415 "minsd {$src2, $dst|$dst, $src2}", []>;
418 // Aliases to match intrinsics which expect XMM operand(s).
419 let isTwoAddress = 1 in {
420 let isCommutable = 1 in {
421 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
423 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
424 int_x86_sse2_add_sd>;
425 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
427 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
428 int_x86_sse2_mul_sd>;
431 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
433 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
434 int_x86_sse2_add_sd>;
435 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
437 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
438 int_x86_sse2_mul_sd>;
440 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
442 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
444 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
445 int_x86_sse2_div_sd>;
446 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
447 int_x86_sse2_div_sd>;
449 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
451 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
453 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
454 int_x86_sse2_sub_sd>;
455 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
456 int_x86_sse2_sub_sd>;
459 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
460 int_x86_sse_sqrt_ss>;
461 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
462 int_x86_sse_sqrt_ss>;
463 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
464 int_x86_sse2_sqrt_sd>;
465 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
466 int_x86_sse2_sqrt_sd>;
468 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
469 int_x86_sse_rsqrt_ss>;
470 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
471 int_x86_sse_rsqrt_ss>;
472 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
474 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
477 let isTwoAddress = 1 in {
478 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
480 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
482 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
483 int_x86_sse2_max_sd>;
484 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
485 int_x86_sse2_max_sd>;
486 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
488 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
490 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
491 int_x86_sse2_min_sd>;
492 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
493 int_x86_sse2_min_sd>;
496 // Conversion instructions
497 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
498 "cvttss2si {$src, $dst|$dst, $src}",
499 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
500 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
501 "cvttss2si {$src, $dst|$dst, $src}",
502 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
503 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
504 "cvttsd2si {$src, $dst|$dst, $src}",
505 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
506 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
507 "cvttsd2si {$src, $dst|$dst, $src}",
508 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
509 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
510 "cvtsd2ss {$src, $dst|$dst, $src}",
511 [(set FR32:$dst, (fround FR64:$src))]>;
512 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
513 "cvtsd2ss {$src, $dst|$dst, $src}",
514 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
515 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
516 "cvtsi2ss {$src, $dst|$dst, $src}",
517 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
518 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
519 "cvtsi2ss {$src, $dst|$dst, $src}",
520 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
521 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
522 "cvtsi2sd {$src, $dst|$dst, $src}",
523 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
524 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
525 "cvtsi2sd {$src, $dst|$dst, $src}",
526 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
528 // SSE2 instructions with XS prefix
529 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
530 "cvtss2sd {$src, $dst|$dst, $src}",
531 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
533 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
534 "cvtss2sd {$src, $dst|$dst, $src}",
535 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
538 // Match intrinsics which expect XMM operand(s).
539 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
540 "cvtss2si {$src, $dst|$dst, $src}",
541 [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
542 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
543 "cvtss2si {$src, $dst|$dst, $src}",
544 [(set R32:$dst, (int_x86_sse_cvtss2si
545 (loadv4f32 addr:$src)))]>;
546 def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
547 "cvtsd2si {$src, $dst|$dst, $src}",
548 [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
549 def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
550 "cvtsd2si {$src, $dst|$dst, $src}",
551 [(set R32:$dst, (int_x86_sse2_cvtsd2si
552 (loadv2f64 addr:$src)))]>;
554 // Aliases for intrinsics
555 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
556 "cvttss2si {$src, $dst|$dst, $src}",
557 [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
558 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
559 "cvttss2si {$src, $dst|$dst, $src}",
560 [(set R32:$dst, (int_x86_sse_cvttss2si
561 (loadv4f32 addr:$src)))]>;
562 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
563 "cvttsd2si {$src, $dst|$dst, $src}",
564 [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
565 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
566 "cvttsd2si {$src, $dst|$dst, $src}",
567 [(set R32:$dst, (int_x86_sse2_cvttsd2si
568 (loadv2f64 addr:$src)))]>;
570 let isTwoAddress = 1 in {
571 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
572 (ops VR128:$dst, VR128:$src1, R32:$src2),
573 "cvtsi2ss {$src2, $dst|$dst, $src2}",
574 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
576 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
577 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
578 "cvtsi2ss {$src2, $dst|$dst, $src2}",
579 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
580 (loadi32 addr:$src2)))]>;
583 // Comparison instructions
584 let isTwoAddress = 1 in {
585 def CMPSSrr : SSI<0xC2, MRMSrcReg,
586 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
587 "cmp${cc}ss {$src, $dst|$dst, $src}",
589 def CMPSSrm : SSI<0xC2, MRMSrcMem,
590 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
591 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
592 def CMPSDrr : SDI<0xC2, MRMSrcReg,
593 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
594 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
595 def CMPSDrm : SDI<0xC2, MRMSrcMem,
596 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
597 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
600 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
601 "ucomiss {$src2, $src1|$src1, $src2}",
602 [(X86cmp FR32:$src1, FR32:$src2)]>;
603 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
604 "ucomiss {$src2, $src1|$src1, $src2}",
605 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
606 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
607 "ucomisd {$src2, $src1|$src1, $src2}",
608 [(X86cmp FR64:$src1, FR64:$src2)]>;
609 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
610 "ucomisd {$src2, $src1|$src1, $src2}",
611 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
613 // Aliases to match intrinsics which expect XMM operand(s).
614 let isTwoAddress = 1 in {
615 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
616 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
617 "cmp${cc}ss {$src, $dst|$dst, $src}",
618 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
619 VR128:$src, imm:$cc))]>;
620 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
621 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
622 "cmp${cc}ss {$src, $dst|$dst, $src}",
623 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
624 (load addr:$src), imm:$cc))]>;
625 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
626 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
627 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
628 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
629 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
630 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
633 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
634 "ucomiss {$src2, $src1|$src1, $src2}",
635 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
636 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
637 "ucomiss {$src2, $src1|$src1, $src2}",
638 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
639 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
640 "ucomisd {$src2, $src1|$src1, $src2}",
641 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
642 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
643 "ucomisd {$src2, $src1|$src1, $src2}",
644 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
646 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
647 "comiss {$src2, $src1|$src1, $src2}",
648 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
649 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
650 "comiss {$src2, $src1|$src1, $src2}",
651 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
652 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
653 "comisd {$src2, $src1|$src1, $src2}",
654 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
655 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
656 "comisd {$src2, $src1|$src1, $src2}",
657 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
659 // Aliases of packed instructions for scalar use. These all have names that
662 // Alias instructions that map fld0 to pxor for sse.
663 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
664 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
665 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
666 Requires<[HasSSE1]>, TB, OpSize;
667 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
668 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
669 Requires<[HasSSE2]>, TB, OpSize;
671 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
672 // Upper bits are disregarded.
673 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
674 "movaps {$src, $dst|$dst, $src}", []>;
675 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
676 "movapd {$src, $dst|$dst, $src}", []>;
678 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
679 // Upper bits are disregarded.
680 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
681 "movaps {$src, $dst|$dst, $src}",
682 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
683 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
684 "movapd {$src, $dst|$dst, $src}",
685 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
687 // Alias bitwise logical operations using SSE logical ops on packed FP values.
688 let isTwoAddress = 1 in {
689 let isCommutable = 1 in {
690 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
691 "andps {$src2, $dst|$dst, $src2}",
692 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
693 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
694 "andpd {$src2, $dst|$dst, $src2}",
695 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
696 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
697 "orps {$src2, $dst|$dst, $src2}", []>;
698 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
699 "orpd {$src2, $dst|$dst, $src2}", []>;
700 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
701 "xorps {$src2, $dst|$dst, $src2}",
702 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
703 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
704 "xorpd {$src2, $dst|$dst, $src2}",
705 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
707 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
708 "andps {$src2, $dst|$dst, $src2}",
709 [(set FR32:$dst, (X86fand FR32:$src1,
710 (X86loadpf32 addr:$src2)))]>;
711 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
712 "andpd {$src2, $dst|$dst, $src2}",
713 [(set FR64:$dst, (X86fand FR64:$src1,
714 (X86loadpf64 addr:$src2)))]>;
715 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
716 "orps {$src2, $dst|$dst, $src2}", []>;
717 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
718 "orpd {$src2, $dst|$dst, $src2}", []>;
719 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
720 "xorps {$src2, $dst|$dst, $src2}",
721 [(set FR32:$dst, (X86fxor FR32:$src1,
722 (X86loadpf32 addr:$src2)))]>;
723 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
724 "xorpd {$src2, $dst|$dst, $src2}",
725 [(set FR64:$dst, (X86fxor FR64:$src1,
726 (X86loadpf64 addr:$src2)))]>;
728 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
729 "andnps {$src2, $dst|$dst, $src2}", []>;
730 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
731 "andnps {$src2, $dst|$dst, $src2}", []>;
732 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
733 "andnpd {$src2, $dst|$dst, $src2}", []>;
734 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
735 "andnpd {$src2, $dst|$dst, $src2}", []>;
738 //===----------------------------------------------------------------------===//
739 // SSE packed FP Instructions
740 //===----------------------------------------------------------------------===//
742 // Some 'special' instructions
743 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
744 "#IMPLICIT_DEF $dst",
745 [(set VR128:$dst, (v4f32 (undef)))]>,
749 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
750 "movaps {$src, $dst|$dst, $src}", []>;
751 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
752 "movaps {$src, $dst|$dst, $src}",
753 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
754 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
755 "movapd {$src, $dst|$dst, $src}", []>;
756 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
757 "movapd {$src, $dst|$dst, $src}",
758 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
760 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
761 "movaps {$src, $dst|$dst, $src}",
762 [(store (v4f32 VR128:$src), addr:$dst)]>;
763 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
764 "movapd {$src, $dst|$dst, $src}",
765 [(store (v2f64 VR128:$src), addr:$dst)]>;
767 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
768 "movups {$src, $dst|$dst, $src}", []>;
769 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
770 "movups {$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
772 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
773 "movups {$src, $dst|$dst, $src}",
774 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
775 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
776 "movupd {$src, $dst|$dst, $src}", []>;
777 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
778 "movupd {$src, $dst|$dst, $src}",
779 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
780 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
781 "movupd {$src, $dst|$dst, $src}",
782 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
784 let isTwoAddress = 1 in {
785 let AddedCost = 10 in {
786 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
787 "movlps {$src2, $dst|$dst, $src2}",
789 (v4f32 (vector_shuffle VR128:$src1,
790 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
791 MOVLP_shuffle_mask)))]>, Cost<20>;
792 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
793 "movlpd {$src2, $dst|$dst, $src2}",
795 (v2f64 (vector_shuffle VR128:$src1,
796 (scalar_to_vector (loadf64 addr:$src2)),
797 MOVLP_shuffle_mask)))]>;
798 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
799 "movhps {$src2, $dst|$dst, $src2}",
801 (v4f32 (vector_shuffle VR128:$src1,
802 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
803 MOVHP_shuffle_mask)))]>, Cost<20>;
804 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
805 "movhpd {$src2, $dst|$dst, $src2}",
807 (v2f64 (vector_shuffle VR128:$src1,
808 (scalar_to_vector (loadf64 addr:$src2)),
809 MOVHP_shuffle_mask)))]>;
813 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
814 "movlps {$src, $dst|$dst, $src}",
815 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
816 (i32 0))), addr:$dst)]>;
817 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
818 "movlpd {$src, $dst|$dst, $src}",
819 [(store (f64 (vector_extract (v2f64 VR128:$src),
820 (i32 0))), addr:$dst)]>;
822 // v2f64 extract element 1 is always custom lowered to unpack high to low
823 // and extract element 0 so the non-store version isn't too horrible.
824 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
825 "movhps {$src, $dst|$dst, $src}",
826 [(store (f64 (vector_extract
827 (v2f64 (vector_shuffle
828 (bc_v2f64 (v4f32 VR128:$src)), (undef),
829 UNPCKH_shuffle_mask)), (i32 0))),
831 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
832 "movhpd {$src, $dst|$dst, $src}",
833 [(store (f64 (vector_extract
834 (v2f64 (vector_shuffle VR128:$src, (undef),
835 UNPCKH_shuffle_mask)), (i32 0))),
838 let isTwoAddress = 1 in {
839 let AddedCost = 10 in {
840 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
841 "movlhps {$src2, $dst|$dst, $src2}",
843 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
844 MOVLHPS_shuffle_mask)))]>;
846 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
847 "movhlps {$src2, $dst|$dst, $src2}",
849 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
850 MOVHLPS_shuffle_mask)))]>;
854 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
855 "movshdup {$src, $dst|$dst, $src}",
856 [(set VR128:$dst, (v4f32 (vector_shuffle
858 MOVSHDUP_shuffle_mask)))]>;
859 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
860 "movshdup {$src, $dst|$dst, $src}",
861 [(set VR128:$dst, (v4f32 (vector_shuffle
862 (loadv4f32 addr:$src), (undef),
863 MOVSHDUP_shuffle_mask)))]>;
865 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
866 "movsldup {$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (v4f32 (vector_shuffle
869 MOVSLDUP_shuffle_mask)))]>;
870 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
871 "movsldup {$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (v4f32 (vector_shuffle
873 (loadv4f32 addr:$src), (undef),
874 MOVSLDUP_shuffle_mask)))]>;
876 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
877 "movddup {$src, $dst|$dst, $src}",
878 [(set VR128:$dst, (v2f64 (vector_shuffle
880 SSE_splat_v2_mask)))]>;
881 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
882 "movddup {$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (v2f64 (vector_shuffle
884 (scalar_to_vector (loadf64 addr:$src)),
886 SSE_splat_v2_mask)))]>;
888 // SSE2 instructions without OpSize prefix
889 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
890 "cvtdq2ps {$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
892 TB, Requires<[HasSSE2]>;
893 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
894 "cvtdq2ps {$src, $dst|$dst, $src}",
895 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
896 (bc_v4i32 (loadv2i64 addr:$src))))]>,
897 TB, Requires<[HasSSE2]>;
899 // SSE2 instructions with XS prefix
900 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
901 "cvtdq2pd {$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
903 XS, Requires<[HasSSE2]>;
904 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
905 "cvtdq2pd {$src, $dst|$dst, $src}",
906 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
907 (bc_v4i32 (loadv2i64 addr:$src))))]>,
908 XS, Requires<[HasSSE2]>;
910 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
911 "cvtps2dq {$src, $dst|$dst, $src}",
912 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
913 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
914 "cvtps2dq {$src, $dst|$dst, $src}",
915 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
916 (loadv4f32 addr:$src)))]>;
917 // SSE2 packed instructions with XS prefix
918 def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
919 "cvttps2dq {$src, $dst|$dst, $src}",
920 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
921 XS, Requires<[HasSSE2]>;
922 def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
923 "cvttps2dq {$src, $dst|$dst, $src}",
924 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
925 (loadv4f32 addr:$src)))]>,
926 XS, Requires<[HasSSE2]>;
928 // SSE2 packed instructions with XD prefix
929 def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
930 "cvtpd2dq {$src, $dst|$dst, $src}",
931 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
932 XD, Requires<[HasSSE2]>;
933 def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
934 "cvtpd2dq {$src, $dst|$dst, $src}",
935 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
936 (loadv2f64 addr:$src)))]>,
937 XD, Requires<[HasSSE2]>;
938 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
939 "cvttpd2dq {$src, $dst|$dst, $src}",
940 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
941 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
942 "cvttpd2dq {$src, $dst|$dst, $src}",
943 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
944 (loadv2f64 addr:$src)))]>;
946 // SSE2 instructions without OpSize prefix
947 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
948 "cvtps2pd {$src, $dst|$dst, $src}",
949 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
950 TB, Requires<[HasSSE2]>;
951 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
952 "cvtps2pd {$src, $dst|$dst, $src}",
953 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
954 (loadv4f32 addr:$src)))]>,
955 TB, Requires<[HasSSE2]>;
957 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
958 "cvtpd2ps {$src, $dst|$dst, $src}",
959 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
960 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
961 "cvtpd2ps {$src, $dst|$dst, $src}",
962 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
963 (loadv2f64 addr:$src)))]>;
965 // Match intrinsics which expect XMM operand(s).
966 // Aliases for intrinsics
967 let isTwoAddress = 1 in {
968 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
969 (ops VR128:$dst, VR128:$src1, R32:$src2),
970 "cvtsi2sd {$src2, $dst|$dst, $src2}",
971 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
973 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
974 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
975 "cvtsi2sd {$src2, $dst|$dst, $src2}",
976 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
977 (loadi32 addr:$src2)))]>;
978 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
979 (ops VR128:$dst, VR128:$src1, VR128:$src2),
980 "cvtsd2ss {$src2, $dst|$dst, $src2}",
981 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
983 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
984 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
985 "cvtsd2ss {$src2, $dst|$dst, $src2}",
986 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
987 (loadv2f64 addr:$src2)))]>;
988 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
989 (ops VR128:$dst, VR128:$src1, VR128:$src2),
990 "cvtss2sd {$src2, $dst|$dst, $src2}",
991 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
994 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
995 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
996 "cvtss2sd {$src2, $dst|$dst, $src2}",
997 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
998 (loadv4f32 addr:$src2)))]>, XS,
1003 let isTwoAddress = 1 in {
1004 let isCommutable = 1 in {
1005 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1006 "addps {$src2, $dst|$dst, $src2}",
1007 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
1008 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1009 "addpd {$src2, $dst|$dst, $src2}",
1010 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
1011 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1012 "mulps {$src2, $dst|$dst, $src2}",
1013 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
1014 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1015 "mulpd {$src2, $dst|$dst, $src2}",
1016 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
1019 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1020 "addps {$src2, $dst|$dst, $src2}",
1021 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
1022 (load addr:$src2))))]>;
1023 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1024 "addpd {$src2, $dst|$dst, $src2}",
1025 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
1026 (load addr:$src2))))]>;
1027 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1028 "mulps {$src2, $dst|$dst, $src2}",
1029 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
1030 (load addr:$src2))))]>;
1031 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1032 "mulpd {$src2, $dst|$dst, $src2}",
1033 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
1034 (load addr:$src2))))]>;
1036 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1037 "divps {$src2, $dst|$dst, $src2}",
1038 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
1039 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1040 "divps {$src2, $dst|$dst, $src2}",
1041 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
1042 (load addr:$src2))))]>;
1043 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1044 "divpd {$src2, $dst|$dst, $src2}",
1045 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
1046 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1047 "divpd {$src2, $dst|$dst, $src2}",
1048 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
1049 (load addr:$src2))))]>;
1051 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1052 "subps {$src2, $dst|$dst, $src2}",
1053 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
1054 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1055 "subps {$src2, $dst|$dst, $src2}",
1056 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
1057 (load addr:$src2))))]>;
1058 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1059 "subpd {$src2, $dst|$dst, $src2}",
1060 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1061 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1062 "subpd {$src2, $dst|$dst, $src2}",
1063 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1064 (load addr:$src2))))]>;
1066 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
1067 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1068 "addsubps {$src2, $dst|$dst, $src2}",
1069 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1071 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1072 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1073 "addsubps {$src2, $dst|$dst, $src2}",
1074 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1075 (loadv4f32 addr:$src2)))]>;
1076 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1077 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1078 "addsubpd {$src2, $dst|$dst, $src2}",
1079 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1081 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1082 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1083 "addsubpd {$src2, $dst|$dst, $src2}",
1084 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1085 (loadv2f64 addr:$src2)))]>;
1088 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1089 int_x86_sse_sqrt_ps>;
1090 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1091 int_x86_sse_sqrt_ps>;
1092 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1093 int_x86_sse2_sqrt_pd>;
1094 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1095 int_x86_sse2_sqrt_pd>;
1097 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1098 int_x86_sse_rsqrt_ps>;
1099 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1100 int_x86_sse_rsqrt_ps>;
1101 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1102 int_x86_sse_rcp_ps>;
1103 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1104 int_x86_sse_rcp_ps>;
1106 let isTwoAddress = 1 in {
1107 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1108 int_x86_sse_max_ps>;
1109 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1110 int_x86_sse_max_ps>;
1111 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1112 int_x86_sse2_max_pd>;
1113 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1114 int_x86_sse2_max_pd>;
1115 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1116 int_x86_sse_min_ps>;
1117 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1118 int_x86_sse_min_ps>;
1119 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1120 int_x86_sse2_min_pd>;
1121 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1122 int_x86_sse2_min_pd>;
1126 let isTwoAddress = 1 in {
1127 let isCommutable = 1 in {
1128 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1129 "andps {$src2, $dst|$dst, $src2}",
1130 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1131 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1132 "andpd {$src2, $dst|$dst, $src2}",
1134 (and (bc_v2i64 (v2f64 VR128:$src1)),
1135 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1136 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1137 "orps {$src2, $dst|$dst, $src2}",
1138 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1139 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1140 "orpd {$src2, $dst|$dst, $src2}",
1142 (or (bc_v2i64 (v2f64 VR128:$src1)),
1143 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1144 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1145 "xorps {$src2, $dst|$dst, $src2}",
1146 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1147 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1148 "xorpd {$src2, $dst|$dst, $src2}",
1150 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1151 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1153 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1154 "andps {$src2, $dst|$dst, $src2}",
1155 [(set VR128:$dst, (and VR128:$src1,
1156 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1157 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1158 "andpd {$src2, $dst|$dst, $src2}",
1160 (and (bc_v2i64 (v2f64 VR128:$src1)),
1161 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1162 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1163 "orps {$src2, $dst|$dst, $src2}",
1164 [(set VR128:$dst, (or VR128:$src1,
1165 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1166 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1167 "orpd {$src2, $dst|$dst, $src2}",
1169 (or (bc_v2i64 (v2f64 VR128:$src1)),
1170 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1171 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1172 "xorps {$src2, $dst|$dst, $src2}",
1173 [(set VR128:$dst, (xor VR128:$src1,
1174 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1175 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1176 "xorpd {$src2, $dst|$dst, $src2}",
1178 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1179 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1180 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1181 "andnps {$src2, $dst|$dst, $src2}",
1182 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1183 (bc_v2i64 (v4i32 immAllOnesV))),
1185 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1186 "andnps {$src2, $dst|$dst, $src2}",
1187 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1188 (bc_v2i64 (v4i32 immAllOnesV))),
1189 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1190 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1191 "andnpd {$src2, $dst|$dst, $src2}",
1193 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1194 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1195 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1196 "andnpd {$src2, $dst|$dst, $src2}",
1198 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1199 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1202 let isTwoAddress = 1 in {
1203 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1204 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1205 "cmp${cc}ps {$src, $dst|$dst, $src}",
1206 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1207 VR128:$src, imm:$cc))]>;
1208 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1209 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1210 "cmp${cc}ps {$src, $dst|$dst, $src}",
1211 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1212 (load addr:$src), imm:$cc))]>;
1213 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1214 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1215 "cmp${cc}pd {$src, $dst|$dst, $src}",
1216 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1217 VR128:$src, imm:$cc))]>;
1218 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1219 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1220 "cmp${cc}pd {$src, $dst|$dst, $src}",
1221 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1222 (load addr:$src), imm:$cc))]>;
1225 // Shuffle and unpack instructions
1226 let isTwoAddress = 1 in {
1227 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1228 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1229 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1230 [(set VR128:$dst, (v4f32 (vector_shuffle
1231 VR128:$src1, VR128:$src2,
1232 SHUFP_shuffle_mask:$src3)))]>;
1233 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1234 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1235 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1236 [(set VR128:$dst, (v4f32 (vector_shuffle
1237 VR128:$src1, (load addr:$src2),
1238 SHUFP_shuffle_mask:$src3)))]>;
1239 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1240 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1241 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1242 [(set VR128:$dst, (v2f64 (vector_shuffle
1243 VR128:$src1, VR128:$src2,
1244 SHUFP_shuffle_mask:$src3)))]>;
1245 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1246 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1247 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1248 [(set VR128:$dst, (v2f64 (vector_shuffle
1249 VR128:$src1, (load addr:$src2),
1250 SHUFP_shuffle_mask:$src3)))]>;
1252 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1253 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1254 "unpckhps {$src2, $dst|$dst, $src2}",
1255 [(set VR128:$dst, (v4f32 (vector_shuffle
1256 VR128:$src1, VR128:$src2,
1257 UNPCKH_shuffle_mask)))]>;
1258 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1259 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1260 "unpckhps {$src2, $dst|$dst, $src2}",
1261 [(set VR128:$dst, (v4f32 (vector_shuffle
1262 VR128:$src1, (load addr:$src2),
1263 UNPCKH_shuffle_mask)))]>;
1264 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1265 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1266 "unpckhpd {$src2, $dst|$dst, $src2}",
1267 [(set VR128:$dst, (v2f64 (vector_shuffle
1268 VR128:$src1, VR128:$src2,
1269 UNPCKH_shuffle_mask)))]>;
1270 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1271 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1272 "unpckhpd {$src2, $dst|$dst, $src2}",
1273 [(set VR128:$dst, (v2f64 (vector_shuffle
1274 VR128:$src1, (load addr:$src2),
1275 UNPCKH_shuffle_mask)))]>;
1277 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1278 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1279 "unpcklps {$src2, $dst|$dst, $src2}",
1280 [(set VR128:$dst, (v4f32 (vector_shuffle
1281 VR128:$src1, VR128:$src2,
1282 UNPCKL_shuffle_mask)))]>;
1283 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1284 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1285 "unpcklps {$src2, $dst|$dst, $src2}",
1286 [(set VR128:$dst, (v4f32 (vector_shuffle
1287 VR128:$src1, (load addr:$src2),
1288 UNPCKL_shuffle_mask)))]>;
1289 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1290 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1291 "unpcklpd {$src2, $dst|$dst, $src2}",
1292 [(set VR128:$dst, (v2f64 (vector_shuffle
1293 VR128:$src1, VR128:$src2,
1294 UNPCKL_shuffle_mask)))]>;
1295 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1296 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1297 "unpcklpd {$src2, $dst|$dst, $src2}",
1298 [(set VR128:$dst, (v2f64 (vector_shuffle
1299 VR128:$src1, (load addr:$src2),
1300 UNPCKL_shuffle_mask)))]>;
1304 let isTwoAddress = 1 in {
1305 def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1306 int_x86_sse3_hadd_ps>;
1307 def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1308 int_x86_sse3_hadd_ps>;
1309 def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1310 int_x86_sse3_hadd_pd>;
1311 def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1312 int_x86_sse3_hadd_pd>;
1313 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1314 int_x86_sse3_hsub_ps>;
1315 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1316 int_x86_sse3_hsub_ps>;
1317 def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1318 int_x86_sse3_hsub_pd>;
1319 def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1320 int_x86_sse3_hsub_pd>;
1323 //===----------------------------------------------------------------------===//
1324 // SSE integer instructions
1325 //===----------------------------------------------------------------------===//
1327 // Move Instructions
1328 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1329 "movdqa {$src, $dst|$dst, $src}", []>;
1330 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1331 "movdqa {$src, $dst|$dst, $src}",
1332 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1333 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1334 "movdqa {$src, $dst|$dst, $src}",
1335 [(store (v2i64 VR128:$src), addr:$dst)]>;
1336 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1337 "movdqu {$src, $dst|$dst, $src}",
1338 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1339 XS, Requires<[HasSSE2]>;
1340 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1341 "movdqu {$src, $dst|$dst, $src}",
1342 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1343 XS, Requires<[HasSSE2]>;
1344 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1345 "lddqu {$src, $dst|$dst, $src}",
1346 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1348 // 128-bit Integer Arithmetic
1349 let isTwoAddress = 1 in {
1350 let isCommutable = 1 in {
1351 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1352 "paddb {$src2, $dst|$dst, $src2}",
1353 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1354 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1355 "paddw {$src2, $dst|$dst, $src2}",
1356 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1357 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1358 "paddd {$src2, $dst|$dst, $src2}",
1359 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1361 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1362 "paddq {$src2, $dst|$dst, $src2}",
1363 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1365 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1366 "paddb {$src2, $dst|$dst, $src2}",
1367 [(set VR128:$dst, (add VR128:$src1,
1368 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1369 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1370 "paddw {$src2, $dst|$dst, $src2}",
1371 [(set VR128:$dst, (add VR128:$src1,
1372 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1373 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1374 "paddd {$src2, $dst|$dst, $src2}",
1375 [(set VR128:$dst, (add VR128:$src1,
1376 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1377 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1378 "paddd {$src2, $dst|$dst, $src2}",
1379 [(set VR128:$dst, (add VR128:$src1,
1380 (loadv2i64 addr:$src2)))]>;
1382 let isCommutable = 1 in {
1383 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1384 "paddsb {$src2, $dst|$dst, $src2}",
1385 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1387 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1388 "paddsw {$src2, $dst|$dst, $src2}",
1389 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1391 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1392 "paddusb {$src2, $dst|$dst, $src2}",
1393 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1395 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1396 "paddusw {$src2, $dst|$dst, $src2}",
1397 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1400 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1401 "paddsb {$src2, $dst|$dst, $src2}",
1402 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1403 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1404 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1405 "paddsw {$src2, $dst|$dst, $src2}",
1406 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1407 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1408 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1409 "paddusb {$src2, $dst|$dst, $src2}",
1410 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1411 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1412 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1413 "paddusw {$src2, $dst|$dst, $src2}",
1414 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1415 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1418 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1419 "psubb {$src2, $dst|$dst, $src2}",
1420 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1421 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1422 "psubw {$src2, $dst|$dst, $src2}",
1423 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1424 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1425 "psubd {$src2, $dst|$dst, $src2}",
1426 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1427 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1428 "psubq {$src2, $dst|$dst, $src2}",
1429 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1431 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1432 "psubb {$src2, $dst|$dst, $src2}",
1433 [(set VR128:$dst, (sub VR128:$src1,
1434 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1435 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1436 "psubw {$src2, $dst|$dst, $src2}",
1437 [(set VR128:$dst, (sub VR128:$src1,
1438 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1439 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1440 "psubd {$src2, $dst|$dst, $src2}",
1441 [(set VR128:$dst, (sub VR128:$src1,
1442 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1443 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1444 "psubd {$src2, $dst|$dst, $src2}",
1445 [(set VR128:$dst, (sub VR128:$src1,
1446 (loadv2i64 addr:$src2)))]>;
1448 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1449 "psubsb {$src2, $dst|$dst, $src2}",
1450 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1452 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1453 "psubsw {$src2, $dst|$dst, $src2}",
1454 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1456 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1457 "psubusb {$src2, $dst|$dst, $src2}",
1458 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1460 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1461 "psubusw {$src2, $dst|$dst, $src2}",
1462 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1465 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1466 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1467 "psubsb {$src2, $dst|$dst, $src2}",
1468 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1469 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1470 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1471 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1472 "psubsw {$src2, $dst|$dst, $src2}",
1473 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1474 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1475 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1476 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1477 "psubusb {$src2, $dst|$dst, $src2}",
1478 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1479 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1480 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1481 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1482 "psubusw {$src2, $dst|$dst, $src2}",
1483 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1484 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1486 let isCommutable = 1 in {
1487 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1488 "pmulhuw {$src2, $dst|$dst, $src2}",
1489 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1491 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1492 "pmulhw {$src2, $dst|$dst, $src2}",
1493 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1495 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1496 "pmullw {$src2, $dst|$dst, $src2}",
1497 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1498 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1499 "pmuludq {$src2, $dst|$dst, $src2}",
1500 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1503 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1504 "pmulhuw {$src2, $dst|$dst, $src2}",
1505 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1506 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1507 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1508 "pmulhw {$src2, $dst|$dst, $src2}",
1509 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1510 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1511 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1512 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1513 "pmullw {$src2, $dst|$dst, $src2}",
1514 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1515 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1516 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1517 "pmuludq {$src2, $dst|$dst, $src2}",
1518 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1519 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1521 let isCommutable = 1 in {
1522 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1523 "pmaddwd {$src2, $dst|$dst, $src2}",
1524 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1527 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1528 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1529 "pmaddwd {$src2, $dst|$dst, $src2}",
1530 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1531 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1533 let isCommutable = 1 in {
1534 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1535 "pavgb {$src2, $dst|$dst, $src2}",
1536 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1538 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1539 "pavgw {$src2, $dst|$dst, $src2}",
1540 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1543 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1544 "pavgb {$src2, $dst|$dst, $src2}",
1545 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1546 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1547 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1548 "pavgw {$src2, $dst|$dst, $src2}",
1549 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1550 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1552 let isCommutable = 1 in {
1553 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1554 "pmaxub {$src2, $dst|$dst, $src2}",
1555 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1557 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1558 "pmaxsw {$src2, $dst|$dst, $src2}",
1559 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1562 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1563 "pmaxub {$src2, $dst|$dst, $src2}",
1564 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1565 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1566 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1567 "pmaxsw {$src2, $dst|$dst, $src2}",
1568 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1569 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1571 let isCommutable = 1 in {
1572 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1573 "pminub {$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1576 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1577 "pminsw {$src2, $dst|$dst, $src2}",
1578 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1581 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1582 "pminub {$src2, $dst|$dst, $src2}",
1583 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1584 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1585 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1586 "pminsw {$src2, $dst|$dst, $src2}",
1587 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1588 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1591 let isCommutable = 1 in {
1592 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1593 "psadbw {$src2, $dst|$dst, $src2}",
1594 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1597 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1598 "psadbw {$src2, $dst|$dst, $src2}",
1599 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1600 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1603 let isTwoAddress = 1 in {
1604 def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1605 "psllw {$src2, $dst|$dst, $src2}",
1606 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1608 def PSLLWrm : PDIi8<0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1609 "psllw {$src2, $dst|$dst, $src2}",
1610 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1611 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1612 def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1613 "psllw {$src2, $dst|$dst, $src2}",
1614 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1615 (scalar_to_vector (i32 imm:$src2))))]>;
1616 def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1617 "pslld {$src2, $dst|$dst, $src2}",
1618 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1620 def PSLLDrm : PDIi8<0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1621 "pslld {$src2, $dst|$dst, $src2}",
1622 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1623 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1624 def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1625 "pslld {$src2, $dst|$dst, $src2}",
1626 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1627 (scalar_to_vector (i32 imm:$src2))))]>;
1628 def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1629 "psllq {$src2, $dst|$dst, $src2}",
1630 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1632 def PSLLQrm : PDIi8<0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1633 "psllq {$src2, $dst|$dst, $src2}",
1634 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1635 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1636 def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1637 "psllq {$src2, $dst|$dst, $src2}",
1638 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1639 (scalar_to_vector (i32 imm:$src2))))]>;
1640 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1641 "pslldq {$src2, $dst|$dst, $src2}", []>;
1643 def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1644 "psrlw {$src2, $dst|$dst, $src2}",
1645 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1647 def PSRLWrm : PDIi8<0xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1648 "psrlw {$src2, $dst|$dst, $src2}",
1649 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1650 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1651 def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1652 "psrlw {$src2, $dst|$dst, $src2}",
1653 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1654 (scalar_to_vector (i32 imm:$src2))))]>;
1655 def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1656 "psrld {$src2, $dst|$dst, $src2}",
1657 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1659 def PSRLDrm : PDIi8<0xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1660 "psrld {$src2, $dst|$dst, $src2}",
1661 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1662 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1663 def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1664 "psrld {$src2, $dst|$dst, $src2}",
1665 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1666 (scalar_to_vector (i32 imm:$src2))))]>;
1667 def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1668 "psrlq {$src2, $dst|$dst, $src2}",
1669 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1671 def PSRLQrm : PDIi8<0xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1672 "psrlq {$src2, $dst|$dst, $src2}",
1673 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1674 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1675 def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1676 "psrlq {$src2, $dst|$dst, $src2}",
1677 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1678 (scalar_to_vector (i32 imm:$src2))))]>;
1679 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1680 "psrldq {$src2, $dst|$dst, $src2}", []>;
1682 def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1683 "psraw {$src2, $dst|$dst, $src2}",
1684 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1686 def PSRAWrm : PDIi8<0xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1687 "psraw {$src2, $dst|$dst, $src2}",
1688 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1689 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1690 def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1691 "psraw {$src2, $dst|$dst, $src2}",
1692 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1693 (scalar_to_vector (i32 imm:$src2))))]>;
1694 def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1695 "psrad {$src2, $dst|$dst, $src2}",
1696 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1698 def PSRADrm : PDIi8<0xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1699 "psrad {$src2, $dst|$dst, $src2}",
1700 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1701 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1702 def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1703 "psrad {$src2, $dst|$dst, $src2}",
1704 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1705 (scalar_to_vector (i32 imm:$src2))))]>;
1709 let isTwoAddress = 1 in {
1710 let isCommutable = 1 in {
1711 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1712 "pand {$src2, $dst|$dst, $src2}",
1713 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1714 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1715 "por {$src2, $dst|$dst, $src2}",
1716 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1717 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1718 "pxor {$src2, $dst|$dst, $src2}",
1719 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1722 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1723 "pand {$src2, $dst|$dst, $src2}",
1724 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1725 (load addr:$src2))))]>;
1726 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1727 "por {$src2, $dst|$dst, $src2}",
1728 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1729 (load addr:$src2))))]>;
1730 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1731 "pxor {$src2, $dst|$dst, $src2}",
1732 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1733 (load addr:$src2))))]>;
1735 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1736 "pandn {$src2, $dst|$dst, $src2}",
1737 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1740 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1741 "pandn {$src2, $dst|$dst, $src2}",
1742 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1743 (load addr:$src2))))]>;
1746 // SSE2 Integer comparison
1747 let isTwoAddress = 1 in {
1748 def PCMPEQBrr : PDI<0x74, MRMSrcReg,
1749 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1750 "pcmpeqb {$src2, $dst|$dst, $src2}",
1751 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1753 def PCMPEQBrm : PDI<0x74, MRMSrcMem,
1754 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1755 "pcmpeqb {$src2, $dst|$dst, $src2}",
1756 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1757 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1758 def PCMPEQWrr : PDI<0x75, MRMSrcReg,
1759 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1760 "pcmpeqw {$src2, $dst|$dst, $src2}",
1761 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1763 def PCMPEQWrm : PDI<0x75, MRMSrcMem,
1764 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1765 "pcmpeqw {$src2, $dst|$dst, $src2}",
1766 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1767 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1768 def PCMPEQDrr : PDI<0x76, MRMSrcReg,
1769 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1770 "pcmpeqd {$src2, $dst|$dst, $src2}",
1771 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1773 def PCMPEQDrm : PDI<0x76, MRMSrcMem,
1774 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1775 "pcmpeqd {$src2, $dst|$dst, $src2}",
1776 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1777 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1779 def PCMPGTBrr : PDI<0x64, MRMSrcReg,
1780 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1781 "pcmpgtb {$src2, $dst|$dst, $src2}",
1782 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1784 def PCMPGTBrm : PDI<0x64, MRMSrcMem,
1785 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1786 "pcmpgtb {$src2, $dst|$dst, $src2}",
1787 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1788 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1789 def PCMPGTWrr : PDI<0x65, MRMSrcReg,
1790 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1791 "pcmpgtw {$src2, $dst|$dst, $src2}",
1792 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1794 def PCMPGTWrm : PDI<0x65, MRMSrcMem,
1795 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1796 "pcmpgtw {$src2, $dst|$dst, $src2}",
1797 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1798 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1799 def PCMPGTDrr : PDI<0x66, MRMSrcReg,
1800 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1801 "pcmpgtd {$src2, $dst|$dst, $src2}",
1802 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1804 def PCMPGTDrm : PDI<0x66, MRMSrcMem,
1805 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1806 "pcmpgtd {$src2, $dst|$dst, $src2}",
1807 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1808 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1811 // Pack instructions
1812 let isTwoAddress = 1 in {
1813 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1815 "packsswb {$src2, $dst|$dst, $src2}",
1816 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1819 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1821 "packsswb {$src2, $dst|$dst, $src2}",
1822 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1824 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1825 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1827 "packssdw {$src2, $dst|$dst, $src2}",
1828 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1831 def PACKSSDWrm : PDI<0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1833 "packssdw {$src2, $dst|$dst, $src2}",
1834 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1836 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1837 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1839 "packuswb {$src2, $dst|$dst, $src2}",
1840 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1843 def PACKUSWBrm : PDI<0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1845 "packuswb {$src2, $dst|$dst, $src2}",
1846 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1848 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1851 // Shuffle and unpack instructions
1852 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1853 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1854 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1855 [(set VR128:$dst, (v4i32 (vector_shuffle
1856 VR128:$src1, (undef),
1857 PSHUFD_shuffle_mask:$src2)))]>;
1858 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1859 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1860 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1861 [(set VR128:$dst, (v4i32 (vector_shuffle
1862 (bc_v4i32 (loadv2i64 addr:$src1)),
1864 PSHUFD_shuffle_mask:$src2)))]>;
1866 // SSE2 with ImmT == Imm8 and XS prefix.
1867 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1868 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1869 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1870 [(set VR128:$dst, (v8i16 (vector_shuffle
1871 VR128:$src1, (undef),
1872 PSHUFHW_shuffle_mask:$src2)))]>,
1873 XS, Requires<[HasSSE2]>;
1874 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1875 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1876 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1877 [(set VR128:$dst, (v8i16 (vector_shuffle
1878 (bc_v8i16 (loadv2i64 addr:$src1)),
1880 PSHUFHW_shuffle_mask:$src2)))]>,
1881 XS, Requires<[HasSSE2]>;
1883 // SSE2 with ImmT == Imm8 and XD prefix.
1884 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1885 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1886 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1887 [(set VR128:$dst, (v8i16 (vector_shuffle
1888 VR128:$src1, (undef),
1889 PSHUFLW_shuffle_mask:$src2)))]>,
1890 XD, Requires<[HasSSE2]>;
1891 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1892 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1893 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1894 [(set VR128:$dst, (v8i16 (vector_shuffle
1895 (bc_v8i16 (loadv2i64 addr:$src1)),
1897 PSHUFLW_shuffle_mask:$src2)))]>,
1898 XD, Requires<[HasSSE2]>;
1900 let isTwoAddress = 1 in {
1901 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1902 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1903 "punpcklbw {$src2, $dst|$dst, $src2}",
1905 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1906 UNPCKL_shuffle_mask)))]>;
1907 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1908 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1909 "punpcklbw {$src2, $dst|$dst, $src2}",
1911 (v16i8 (vector_shuffle VR128:$src1,
1912 (bc_v16i8 (loadv2i64 addr:$src2)),
1913 UNPCKL_shuffle_mask)))]>;
1914 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1915 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1916 "punpcklwd {$src2, $dst|$dst, $src2}",
1918 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1919 UNPCKL_shuffle_mask)))]>;
1920 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1921 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1922 "punpcklwd {$src2, $dst|$dst, $src2}",
1924 (v8i16 (vector_shuffle VR128:$src1,
1925 (bc_v8i16 (loadv2i64 addr:$src2)),
1926 UNPCKL_shuffle_mask)))]>;
1927 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1928 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1929 "punpckldq {$src2, $dst|$dst, $src2}",
1931 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1932 UNPCKL_shuffle_mask)))]>;
1933 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1934 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1935 "punpckldq {$src2, $dst|$dst, $src2}",
1937 (v4i32 (vector_shuffle VR128:$src1,
1938 (bc_v4i32 (loadv2i64 addr:$src2)),
1939 UNPCKL_shuffle_mask)))]>;
1940 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1941 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1942 "punpcklqdq {$src2, $dst|$dst, $src2}",
1944 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1945 UNPCKL_shuffle_mask)))]>;
1946 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1947 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1948 "punpcklqdq {$src2, $dst|$dst, $src2}",
1950 (v2i64 (vector_shuffle VR128:$src1,
1951 (loadv2i64 addr:$src2),
1952 UNPCKL_shuffle_mask)))]>;
1954 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1955 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1956 "punpckhbw {$src2, $dst|$dst, $src2}",
1958 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1959 UNPCKH_shuffle_mask)))]>;
1960 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1961 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1962 "punpckhbw {$src2, $dst|$dst, $src2}",
1964 (v16i8 (vector_shuffle VR128:$src1,
1965 (bc_v16i8 (loadv2i64 addr:$src2)),
1966 UNPCKH_shuffle_mask)))]>;
1967 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1968 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1969 "punpckhwd {$src2, $dst|$dst, $src2}",
1971 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1972 UNPCKH_shuffle_mask)))]>;
1973 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1974 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1975 "punpckhwd {$src2, $dst|$dst, $src2}",
1977 (v8i16 (vector_shuffle VR128:$src1,
1978 (bc_v8i16 (loadv2i64 addr:$src2)),
1979 UNPCKH_shuffle_mask)))]>;
1980 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1981 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1982 "punpckhdq {$src2, $dst|$dst, $src2}",
1984 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1985 UNPCKH_shuffle_mask)))]>;
1986 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1987 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1988 "punpckhdq {$src2, $dst|$dst, $src2}",
1990 (v4i32 (vector_shuffle VR128:$src1,
1991 (bc_v4i32 (loadv2i64 addr:$src2)),
1992 UNPCKH_shuffle_mask)))]>;
1993 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1994 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1995 "punpckhdq {$src2, $dst|$dst, $src2}",
1997 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1998 UNPCKH_shuffle_mask)))]>;
1999 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2000 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
2001 "punpckhqdq {$src2, $dst|$dst, $src2}",
2003 (v2i64 (vector_shuffle VR128:$src1,
2004 (loadv2i64 addr:$src2),
2005 UNPCKH_shuffle_mask)))]>;
2009 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2010 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
2011 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2012 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
2013 (i32 imm:$src2)))]>;
2014 let isTwoAddress = 1 in {
2015 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2016 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
2017 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2018 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2019 R32:$src2, (i32 imm:$src3))))]>;
2020 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2021 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
2022 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2024 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2025 (i32 (anyext (loadi16 addr:$src2))),
2026 (i32 imm:$src3))))]>;
2029 //===----------------------------------------------------------------------===//
2030 // Miscellaneous Instructions
2031 //===----------------------------------------------------------------------===//
2034 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2035 "movmskps {$src, $dst|$dst, $src}",
2036 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
2037 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2038 "movmskpd {$src, $dst|$dst, $src}",
2039 [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
2041 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
2042 "pmovmskb {$src, $dst|$dst, $src}",
2043 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2045 // Conditional store
2046 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
2047 "maskmovdqu {$mask, $src|$src, $mask}",
2048 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2051 // Prefetching loads
2052 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
2053 "prefetcht0 $src", []>;
2054 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
2055 "prefetcht1 $src", []>;
2056 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
2057 "prefetcht2 $src", []>;
2058 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
2059 "prefetchtnta $src", []>;
2061 // Non-temporal stores
2062 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2063 "movntps {$src, $dst|$dst, $src}",
2064 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2065 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2066 "movntpd {$src, $dst|$dst, $src}",
2067 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2068 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2069 "movntdq {$src, $dst|$dst, $src}",
2070 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2071 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
2072 "movnti {$src, $dst|$dst, $src}",
2073 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
2074 TB, Requires<[HasSSE2]>;
2077 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2078 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2079 TB, Requires<[HasSSE2]>;
2081 // Load, store, and memory fence
2082 def SFENCE : I<0xAE, MRM7m, (ops),
2083 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
2084 def LFENCE : I<0xAE, MRM5m, (ops),
2085 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2086 def MFENCE : I<0xAE, MRM6m, (ops),
2087 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2090 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
2092 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
2093 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
2095 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
2097 // Thread synchronization
2098 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2099 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
2100 TB, Requires<[HasSSE3]>;
2101 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2102 [(int_x86_sse3_mwait ECX, EAX)]>,
2103 TB, Requires<[HasSSE3]>;
2105 //===----------------------------------------------------------------------===//
2106 // Alias Instructions
2107 //===----------------------------------------------------------------------===//
2109 // Alias instructions that map zero vector to pxor / xorp* for sse.
2110 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2111 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
2113 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
2114 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
2116 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2117 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
2119 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2121 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2122 "pcmpeqd $dst, $dst",
2123 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2125 // FR32 / FR64 to 128-bit vector conversion.
2126 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
2127 "movss {$src, $dst|$dst, $src}",
2129 (v4f32 (scalar_to_vector FR32:$src)))]>;
2130 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2131 "movss {$src, $dst|$dst, $src}",
2133 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
2134 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2135 "movsd {$src, $dst|$dst, $src}",
2137 (v2f64 (scalar_to_vector FR64:$src)))]>;
2138 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2139 "movsd {$src, $dst|$dst, $src}",
2141 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2143 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
2144 "movd {$src, $dst|$dst, $src}",
2146 (v4i32 (scalar_to_vector R32:$src)))]>;
2147 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2148 "movd {$src, $dst|$dst, $src}",
2150 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2151 // SSE2 instructions with XS prefix
2152 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
2153 "movq {$src, $dst|$dst, $src}",
2155 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
2156 Requires<[HasSSE2]>;
2157 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2158 "movq {$src, $dst|$dst, $src}",
2160 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2161 Requires<[HasSSE2]>;
2162 // FIXME: may not be able to eliminate this movss with coalescing the src and
2163 // dest register classes are different. We really want to write this pattern
2165 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
2166 // (f32 FR32:$src)>;
2167 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
2168 "movss {$src, $dst|$dst, $src}",
2169 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
2171 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
2172 "movss {$src, $dst|$dst, $src}",
2173 [(store (f32 (vector_extract (v4f32 VR128:$src),
2174 (i32 0))), addr:$dst)]>;
2175 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2176 "movsd {$src, $dst|$dst, $src}",
2177 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2179 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
2180 "movsd {$src, $dst|$dst, $src}",
2181 [(store (f64 (vector_extract (v2f64 VR128:$src),
2182 (i32 0))), addr:$dst)]>;
2183 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops R32:$dst, VR128:$src),
2184 "movd {$src, $dst|$dst, $src}",
2185 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
2187 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2188 "movd {$src, $dst|$dst, $src}",
2189 [(store (i32 (vector_extract (v4i32 VR128:$src),
2190 (i32 0))), addr:$dst)]>;
2192 // Move to lower bits of a VR128, leaving upper bits alone.
2193 // Three operand (but two address) aliases.
2194 let isTwoAddress = 1 in {
2195 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
2196 "movss {$src2, $dst|$dst, $src2}", []>;
2197 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
2198 "movsd {$src2, $dst|$dst, $src2}", []>;
2199 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
2200 "movd {$src2, $dst|$dst, $src2}", []>;
2202 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2203 "movss {$src2, $dst|$dst, $src2}",
2205 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2206 MOVS_shuffle_mask)))]>;
2207 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2208 "movsd {$src2, $dst|$dst, $src2}",
2210 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2211 MOVS_shuffle_mask)))]>;
2214 // Store / copy lower 64-bits of a XMM register.
2215 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2216 "movq {$src, $dst|$dst, $src}",
2217 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2219 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2220 def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2221 "movq {$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
2224 // Move to lower bits of a VR128 and zeroing upper bits.
2225 // Loading from memory automatically zeroing upper bits.
2226 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2227 "movss {$src, $dst|$dst, $src}",
2229 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
2230 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2231 "movsd {$src, $dst|$dst, $src}",
2233 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
2234 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2235 "movd {$src, $dst|$dst, $src}",
2237 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
2238 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2239 "movq {$src, $dst|$dst, $src}",
2241 (bc_v2i64 (v2f64 (X86zexts2vec
2242 (loadf64 addr:$src)))))]>;
2244 //===----------------------------------------------------------------------===//
2245 // Non-Instruction Patterns
2246 //===----------------------------------------------------------------------===//
2248 // 128-bit vector undef's.
2249 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2250 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2251 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2252 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2253 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2255 // 128-bit vector all zero's.
2256 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
2257 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
2258 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
2260 // 128-bit vector all one's.
2261 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
2262 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
2263 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
2264 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
2265 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
2267 // Store 128-bit integer vector values.
2268 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2269 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2270 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2271 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2272 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2273 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2275 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
2277 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2278 Requires<[HasSSE2]>;
2279 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2280 Requires<[HasSSE2]>;
2283 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
2284 Requires<[HasSSE2]>;
2285 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
2286 Requires<[HasSSE2]>;
2287 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
2288 Requires<[HasSSE2]>;
2289 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
2290 Requires<[HasSSE2]>;
2291 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
2292 Requires<[HasSSE2]>;
2293 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2294 Requires<[HasSSE2]>;
2295 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2296 Requires<[HasSSE2]>;
2297 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2298 Requires<[HasSSE2]>;
2299 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
2300 Requires<[HasSSE2]>;
2301 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
2302 Requires<[HasSSE2]>;
2303 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2304 Requires<[HasSSE2]>;
2305 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2306 Requires<[HasSSE2]>;
2307 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2308 Requires<[HasSSE2]>;
2309 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
2310 Requires<[HasSSE2]>;
2311 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
2312 Requires<[HasSSE2]>;
2313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2314 Requires<[HasSSE2]>;
2315 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2316 Requires<[HasSSE2]>;
2317 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2318 Requires<[HasSSE2]>;
2319 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
2320 Requires<[HasSSE2]>;
2321 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
2322 Requires<[HasSSE2]>;
2323 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
2324 Requires<[HasSSE2]>;
2325 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
2326 Requires<[HasSSE2]>;
2327 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
2328 Requires<[HasSSE2]>;
2329 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
2330 Requires<[HasSSE2]>;
2331 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
2332 Requires<[HasSSE2]>;
2333 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
2334 Requires<[HasSSE2]>;
2335 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
2336 Requires<[HasSSE2]>;
2337 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
2338 Requires<[HasSSE2]>;
2339 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
2340 Requires<[HasSSE2]>;
2341 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
2342 Requires<[HasSSE2]>;
2344 // Zeroing a VR128 then do a MOVS* to the lower bits.
2345 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
2346 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
2347 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
2348 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
2349 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
2350 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
2351 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
2352 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
2353 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
2354 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
2356 // MOVLP{S|D}rm / MOVHP{S|D}rm.
2357 let AddedCost = 10 in {
2358 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2359 MOVLP_shuffle_mask)),
2360 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2361 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2362 MOVLP_shuffle_mask)),
2363 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2364 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2365 MOVHP_shuffle_mask)),
2366 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2367 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2368 MOVHP_shuffle_mask)),
2369 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2372 // Splat v2f64 / v2i64
2373 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2374 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2375 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2376 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2379 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2380 (v4f32 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
2381 Requires<[HasSSE1]>;
2383 // Special unary SHUFPSrri case.
2384 // FIXME: when we want non two-address code, then we should use PSHUFD?
2385 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2386 SHUFP_unary_shuffle_mask:$sm),
2387 (v4f32 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2388 Requires<[HasSSE1]>;
2389 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2390 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2391 SHUFP_unary_shuffle_mask:$sm),
2392 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2393 Requires<[HasSSE2]>;
2394 // Special binary v4i32 shuffle cases with SHUFPS.
2395 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2396 PSHUFD_binary_shuffle_mask:$sm),
2397 (v4i32 (SHUFPSrri VR128:$src1, VR128:$src2,
2398 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2399 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2400 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2401 (v4i32 (SHUFPSrmi VR128:$src1, addr:$src2,
2402 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2404 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2405 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2406 UNPCKL_v_undef_shuffle_mask)),
2407 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2408 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2409 UNPCKL_v_undef_shuffle_mask)),
2410 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2411 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2412 UNPCKL_v_undef_shuffle_mask)),
2413 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2414 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2415 UNPCKL_v_undef_shuffle_mask)),
2416 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2418 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2419 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2420 MOVSHDUP_shuffle_mask)),
2421 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2422 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2423 MOVSHDUP_shuffle_mask)),
2424 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2426 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2427 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2428 MOVSLDUP_shuffle_mask)),
2429 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2430 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2431 MOVSLDUP_shuffle_mask)),
2432 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2434 // vector_shuffle v1, v2 <4, 1, 2, 3>
2435 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2436 MOVS_shuffle_mask)),
2437 (MOVLPSrr VR128:$src1, VR128:$src2)>;
2438 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2439 MOVS_shuffle_mask)),
2440 (MOVLPDrr VR128:$src1, VR128:$src2)>;
2442 // 128-bit logical shifts
2443 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2444 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2445 Requires<[HasSSE2]>;
2446 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2447 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2448 Requires<[HasSSE2]>;
2450 // Some special case pandn patterns.
2451 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2453 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2454 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2456 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2457 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2459 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2461 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2462 (load addr:$src2))),
2463 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2464 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2465 (load addr:$src2))),
2466 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2467 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2468 (load addr:$src2))),
2469 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;