1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (st node:$val, node:$ptr), [{
102 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
103 return !ST->isTruncatingStore() &&
104 ST->getAddressingMode() == ISD::UNINDEXED &&
105 ST->getAlignment() >= 16;
109 // Like 'load', but always requires vector alignment.
110 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
111 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
112 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
113 LD->getAddressingMode() == ISD::UNINDEXED &&
114 LD->getAlignment() >= 16;
118 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
119 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
120 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
121 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
122 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
123 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
125 // Like 'load', but uses special alignment checks suitable for use in
126 // memory operands in most SSE instructions, which are required to
127 // be naturally aligned on some targets but not on others.
128 // FIXME: Actually implement support for targets that don't require the
129 // alignment. This probably wants a subtarget predicate.
130 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
131 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
132 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
133 LD->getAddressingMode() == ISD::UNINDEXED &&
134 LD->getAlignment() >= 16;
138 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
139 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
140 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
141 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
142 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
143 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
144 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
146 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
148 // FIXME: 8 byte alignment for mmx reads is not required
149 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
150 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
151 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
152 LD->getAddressingMode() == ISD::UNINDEXED &&
153 LD->getAlignment() >= 8;
157 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
158 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
159 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
160 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
162 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
163 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
164 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
165 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
166 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
167 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
169 def fp32imm0 : PatLeaf<(f32 fpimm), [{
170 return N->isExactlyValue(+0.0);
173 def PSxLDQ_imm : SDNodeXForm<imm, [{
174 // Transformation function: imm >> 3
175 return getI32Imm(N->getValue() >> 3);
178 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
180 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
181 return getI8Imm(X86::getShuffleSHUFImmediate(N));
184 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
186 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
187 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
190 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
192 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
193 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
196 def SSE_splat_mask : PatLeaf<(build_vector), [{
197 return X86::isSplatMask(N);
198 }], SHUFFLE_get_shuf_imm>;
200 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
201 return X86::isSplatLoMask(N);
204 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
205 return X86::isMOVHLPSMask(N);
208 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
209 return X86::isMOVHLPS_v_undef_Mask(N);
212 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
213 return X86::isMOVHPMask(N);
216 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
217 return X86::isMOVLPMask(N);
220 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
221 return X86::isMOVLMask(N);
224 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
225 return X86::isMOVSHDUPMask(N);
228 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
229 return X86::isMOVSLDUPMask(N);
232 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
233 return X86::isUNPCKLMask(N);
236 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
237 return X86::isUNPCKHMask(N);
240 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
241 return X86::isUNPCKL_v_undef_Mask(N);
244 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
245 return X86::isUNPCKH_v_undef_Mask(N);
248 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
249 return X86::isPSHUFDMask(N);
250 }], SHUFFLE_get_shuf_imm>;
252 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
253 return X86::isPSHUFHWMask(N);
254 }], SHUFFLE_get_pshufhw_imm>;
256 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
257 return X86::isPSHUFLWMask(N);
258 }], SHUFFLE_get_pshuflw_imm>;
260 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
261 return X86::isPSHUFDMask(N);
262 }], SHUFFLE_get_shuf_imm>;
264 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
265 return X86::isSHUFPMask(N);
266 }], SHUFFLE_get_shuf_imm>;
268 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
269 return X86::isSHUFPMask(N);
270 }], SHUFFLE_get_shuf_imm>;
273 //===----------------------------------------------------------------------===//
274 // SSE scalar FP Instructions
275 //===----------------------------------------------------------------------===//
277 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
278 // scheduler into a branch sequence.
279 // These are expanded by the scheduler.
280 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
281 def CMOV_FR32 : I<0, Pseudo,
282 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
283 "#CMOV_FR32 PSEUDO!",
284 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
286 def CMOV_FR64 : I<0, Pseudo,
287 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
288 "#CMOV_FR64 PSEUDO!",
289 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
291 def CMOV_V4F32 : I<0, Pseudo,
292 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
293 "#CMOV_V4F32 PSEUDO!",
295 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
297 def CMOV_V2F64 : I<0, Pseudo,
298 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
299 "#CMOV_V2F64 PSEUDO!",
301 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
303 def CMOV_V2I64 : I<0, Pseudo,
304 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
305 "#CMOV_V2I64 PSEUDO!",
307 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
311 //===----------------------------------------------------------------------===//
313 //===----------------------------------------------------------------------===//
316 let neverHasSideEffects = 1 in
317 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
318 "movss\t{$src, $dst|$dst, $src}", []>;
319 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
320 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
321 "movss\t{$src, $dst|$dst, $src}",
322 [(set FR32:$dst, (loadf32 addr:$src))]>;
323 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
324 "movss\t{$src, $dst|$dst, $src}",
325 [(store FR32:$src, addr:$dst)]>;
327 // Conversion instructions
328 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
329 "cvttss2si\t{$src, $dst|$dst, $src}",
330 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
331 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
332 "cvttss2si\t{$src, $dst|$dst, $src}",
333 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
334 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
335 "cvtsi2ss\t{$src, $dst|$dst, $src}",
336 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
337 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
338 "cvtsi2ss\t{$src, $dst|$dst, $src}",
339 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
341 // Match intrinsics which expect XMM operand(s).
342 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
343 "cvtss2si\t{$src, $dst|$dst, $src}",
344 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
345 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
346 "cvtss2si\t{$src, $dst|$dst, $src}",
347 [(set GR32:$dst, (int_x86_sse_cvtss2si
348 (load addr:$src)))]>;
350 // Match intrinisics which expect MM and XMM operand(s).
351 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
352 "cvtps2pi\t{$src, $dst|$dst, $src}",
353 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
354 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
355 "cvtps2pi\t{$src, $dst|$dst, $src}",
356 [(set VR64:$dst, (int_x86_sse_cvtps2pi
357 (load addr:$src)))]>;
358 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
359 "cvttps2pi\t{$src, $dst|$dst, $src}",
360 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
361 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
362 "cvttps2pi\t{$src, $dst|$dst, $src}",
363 [(set VR64:$dst, (int_x86_sse_cvttps2pi
364 (load addr:$src)))]>;
365 let Constraints = "$src1 = $dst" in {
366 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
367 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
368 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
369 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
371 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
372 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
373 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
374 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
375 (load addr:$src2)))]>;
378 // Aliases for intrinsics
379 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
380 "cvttss2si\t{$src, $dst|$dst, $src}",
382 (int_x86_sse_cvttss2si VR128:$src))]>;
383 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
384 "cvttss2si\t{$src, $dst|$dst, $src}",
386 (int_x86_sse_cvttss2si(load addr:$src)))]>;
388 let Constraints = "$src1 = $dst" in {
389 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
390 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
391 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
392 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
394 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
395 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
396 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
397 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
398 (loadi32 addr:$src2)))]>;
401 // Comparison instructions
402 let Constraints = "$src1 = $dst" in {
403 let neverHasSideEffects = 1 in
404 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
405 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
406 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
407 let neverHasSideEffects = 1, mayLoad = 1 in
408 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
409 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
410 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
413 let Defs = [EFLAGS] in {
414 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
415 "ucomiss\t{$src2, $src1|$src1, $src2}",
416 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
417 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
418 "ucomiss\t{$src2, $src1|$src1, $src2}",
419 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
423 // Aliases to match intrinsics which expect XMM operand(s).
424 let Constraints = "$src1 = $dst" in {
425 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
426 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
427 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
428 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
429 VR128:$src, imm:$cc))]>;
430 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
431 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
432 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
433 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
434 (load addr:$src), imm:$cc))]>;
437 let Defs = [EFLAGS] in {
438 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
439 (ins VR128:$src1, VR128:$src2),
440 "ucomiss\t{$src2, $src1|$src1, $src2}",
441 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
443 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
444 (ins VR128:$src1, f128mem:$src2),
445 "ucomiss\t{$src2, $src1|$src1, $src2}",
446 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
449 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
450 (ins VR128:$src1, VR128:$src2),
451 "comiss\t{$src2, $src1|$src1, $src2}",
452 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
454 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
455 (ins VR128:$src1, f128mem:$src2),
456 "comiss\t{$src2, $src1|$src1, $src2}",
457 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
461 // Aliases of packed SSE1 instructions for scalar use. These all have names that
464 // Alias instructions that map fld0 to pxor for sse.
465 let isReMaterializable = 1 in
466 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
467 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
468 Requires<[HasSSE1]>, TB, OpSize;
470 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
472 let neverHasSideEffects = 1 in
473 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
474 "movaps\t{$src, $dst|$dst, $src}", []>;
476 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
478 let isSimpleLoad = 1 in
479 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
480 "movaps\t{$src, $dst|$dst, $src}",
481 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
483 // Alias bitwise logical operations using SSE logical ops on packed FP values.
484 let Constraints = "$src1 = $dst" in {
485 let isCommutable = 1 in {
486 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
487 "andps\t{$src2, $dst|$dst, $src2}",
488 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
489 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
490 "orps\t{$src2, $dst|$dst, $src2}",
491 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
492 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
493 "xorps\t{$src2, $dst|$dst, $src2}",
494 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
497 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
498 "andps\t{$src2, $dst|$dst, $src2}",
499 [(set FR32:$dst, (X86fand FR32:$src1,
500 (memopfsf32 addr:$src2)))]>;
501 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
502 "orps\t{$src2, $dst|$dst, $src2}",
503 [(set FR32:$dst, (X86for FR32:$src1,
504 (memopfsf32 addr:$src2)))]>;
505 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
506 "xorps\t{$src2, $dst|$dst, $src2}",
507 [(set FR32:$dst, (X86fxor FR32:$src1,
508 (memopfsf32 addr:$src2)))]>;
509 let neverHasSideEffects = 1 in {
510 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
511 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
512 "andnps\t{$src2, $dst|$dst, $src2}", []>;
515 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
516 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
517 "andnps\t{$src2, $dst|$dst, $src2}", []>;
521 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
523 /// In addition, we also have a special variant of the scalar form here to
524 /// represent the associated intrinsic operation. This form is unlike the
525 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
526 /// and leaves the top elements undefined.
528 /// These three forms can each be reg+reg or reg+mem, so there are a total of
529 /// six "instructions".
531 let Constraints = "$src1 = $dst" in {
532 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
533 SDNode OpNode, Intrinsic F32Int,
534 bit Commutable = 0> {
535 // Scalar operation, reg+reg.
536 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
537 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
538 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
539 let isCommutable = Commutable;
542 // Scalar operation, reg+mem.
543 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
544 (ins FR32:$src1, f32mem:$src2),
545 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
546 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
548 // Vector operation, reg+reg.
549 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
550 (ins VR128:$src1, VR128:$src2),
551 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
552 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
553 let isCommutable = Commutable;
556 // Vector operation, reg+mem.
557 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
558 (ins VR128:$src1, f128mem:$src2),
559 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
562 // Intrinsic operation, reg+reg.
563 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
564 (ins VR128:$src1, VR128:$src2),
565 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
566 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
567 let isCommutable = Commutable;
570 // Intrinsic operation, reg+mem.
571 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
572 (ins VR128:$src1, ssmem:$src2),
573 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
574 [(set VR128:$dst, (F32Int VR128:$src1,
575 sse_load_f32:$src2))]>;
579 // Arithmetic instructions
580 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
581 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
582 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
583 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
585 /// sse1_fp_binop_rm - Other SSE1 binops
587 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
588 /// instructions for a full-vector intrinsic form. Operations that map
589 /// onto C operators don't use this form since they just use the plain
590 /// vector form instead of having a separate vector intrinsic form.
592 /// This provides a total of eight "instructions".
594 let Constraints = "$src1 = $dst" in {
595 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
599 bit Commutable = 0> {
601 // Scalar operation, reg+reg.
602 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
603 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
604 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
605 let isCommutable = Commutable;
608 // Scalar operation, reg+mem.
609 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
610 (ins FR32:$src1, f32mem:$src2),
611 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
612 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
614 // Vector operation, reg+reg.
615 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
616 (ins VR128:$src1, VR128:$src2),
617 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
618 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
619 let isCommutable = Commutable;
622 // Vector operation, reg+mem.
623 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
624 (ins VR128:$src1, f128mem:$src2),
625 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
626 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
628 // Intrinsic operation, reg+reg.
629 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
630 (ins VR128:$src1, VR128:$src2),
631 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
632 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
633 let isCommutable = Commutable;
636 // Intrinsic operation, reg+mem.
637 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
638 (ins VR128:$src1, ssmem:$src2),
639 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
640 [(set VR128:$dst, (F32Int VR128:$src1,
641 sse_load_f32:$src2))]>;
643 // Vector intrinsic operation, reg+reg.
644 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
645 (ins VR128:$src1, VR128:$src2),
646 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
647 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
648 let isCommutable = Commutable;
651 // Vector intrinsic operation, reg+mem.
652 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
653 (ins VR128:$src1, f128mem:$src2),
654 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
655 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
659 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
660 int_x86_sse_max_ss, int_x86_sse_max_ps>;
661 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
662 int_x86_sse_min_ss, int_x86_sse_min_ps>;
664 //===----------------------------------------------------------------------===//
665 // SSE packed FP Instructions
668 let neverHasSideEffects = 1 in
669 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
670 "movaps\t{$src, $dst|$dst, $src}", []>;
671 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
672 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
673 "movaps\t{$src, $dst|$dst, $src}",
674 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
676 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
677 "movaps\t{$src, $dst|$dst, $src}",
678 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
680 let neverHasSideEffects = 1 in
681 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
682 "movups\t{$src, $dst|$dst, $src}", []>;
683 let isSimpleLoad = 1 in
684 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
685 "movups\t{$src, $dst|$dst, $src}",
686 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
687 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
688 "movups\t{$src, $dst|$dst, $src}",
689 [(store (v4f32 VR128:$src), addr:$dst)]>;
691 // Intrinsic forms of MOVUPS load and store
692 let isSimpleLoad = 1 in
693 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
694 "movups\t{$src, $dst|$dst, $src}",
695 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
696 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
697 "movups\t{$src, $dst|$dst, $src}",
698 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
700 let Constraints = "$src1 = $dst" in {
701 let AddedComplexity = 20 in {
702 def MOVLPSrm : PSI<0x12, MRMSrcMem,
703 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
704 "movlps\t{$src2, $dst|$dst, $src2}",
706 (v4f32 (vector_shuffle VR128:$src1,
707 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
708 MOVLP_shuffle_mask)))]>;
709 def MOVHPSrm : PSI<0x16, MRMSrcMem,
710 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
711 "movhps\t{$src2, $dst|$dst, $src2}",
713 (v4f32 (vector_shuffle VR128:$src1,
714 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
715 MOVHP_shuffle_mask)))]>;
717 } // Constraints = "$src1 = $dst"
720 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
721 "movlps\t{$src, $dst|$dst, $src}",
722 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
723 (iPTR 0))), addr:$dst)]>;
725 // v2f64 extract element 1 is always custom lowered to unpack high to low
726 // and extract element 0 so the non-store version isn't too horrible.
727 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
728 "movhps\t{$src, $dst|$dst, $src}",
729 [(store (f64 (vector_extract
730 (v2f64 (vector_shuffle
731 (bc_v2f64 (v4f32 VR128:$src)), (undef),
732 UNPCKH_shuffle_mask)), (iPTR 0))),
735 let Constraints = "$src1 = $dst" in {
736 let AddedComplexity = 15 in {
737 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
738 "movlhps\t{$src2, $dst|$dst, $src2}",
740 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
741 MOVHP_shuffle_mask)))]>;
743 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
744 "movhlps\t{$src2, $dst|$dst, $src2}",
746 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
747 MOVHLPS_shuffle_mask)))]>;
749 } // Constraints = "$src1 = $dst"
755 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
757 /// In addition, we also have a special variant of the scalar form here to
758 /// represent the associated intrinsic operation. This form is unlike the
759 /// plain scalar form, in that it takes an entire vector (instead of a
760 /// scalar) and leaves the top elements undefined.
762 /// And, we have a special variant form for a full-vector intrinsic form.
764 /// These four forms can each have a reg or a mem operand, so there are a
765 /// total of eight "instructions".
767 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
771 bit Commutable = 0> {
772 // Scalar operation, reg.
773 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
774 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
775 [(set FR32:$dst, (OpNode FR32:$src))]> {
776 let isCommutable = Commutable;
779 // Scalar operation, mem.
780 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
781 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
782 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
784 // Vector operation, reg.
785 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
786 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
787 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
788 let isCommutable = Commutable;
791 // Vector operation, mem.
792 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
793 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
794 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
796 // Intrinsic operation, reg.
797 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
798 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
799 [(set VR128:$dst, (F32Int VR128:$src))]> {
800 let isCommutable = Commutable;
803 // Intrinsic operation, mem.
804 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
805 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
806 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
808 // Vector intrinsic operation, reg
809 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
810 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
811 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
812 let isCommutable = Commutable;
815 // Vector intrinsic operation, mem
816 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
817 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
818 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
822 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
823 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
825 // Reciprocal approximations. Note that these typically require refinement
826 // in order to obtain suitable precision.
827 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
828 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
829 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
830 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
833 let Constraints = "$src1 = $dst" in {
834 let isCommutable = 1 in {
835 def ANDPSrr : PSI<0x54, MRMSrcReg,
836 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
837 "andps\t{$src2, $dst|$dst, $src2}",
838 [(set VR128:$dst, (v2i64
839 (and VR128:$src1, VR128:$src2)))]>;
840 def ORPSrr : PSI<0x56, MRMSrcReg,
841 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
842 "orps\t{$src2, $dst|$dst, $src2}",
843 [(set VR128:$dst, (v2i64
844 (or VR128:$src1, VR128:$src2)))]>;
845 def XORPSrr : PSI<0x57, MRMSrcReg,
846 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
847 "xorps\t{$src2, $dst|$dst, $src2}",
848 [(set VR128:$dst, (v2i64
849 (xor VR128:$src1, VR128:$src2)))]>;
852 def ANDPSrm : PSI<0x54, MRMSrcMem,
853 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
854 "andps\t{$src2, $dst|$dst, $src2}",
855 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
856 (memopv2i64 addr:$src2)))]>;
857 def ORPSrm : PSI<0x56, MRMSrcMem,
858 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
859 "orps\t{$src2, $dst|$dst, $src2}",
860 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
861 (memopv2i64 addr:$src2)))]>;
862 def XORPSrm : PSI<0x57, MRMSrcMem,
863 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
864 "xorps\t{$src2, $dst|$dst, $src2}",
865 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
866 (memopv2i64 addr:$src2)))]>;
867 def ANDNPSrr : PSI<0x55, MRMSrcReg,
868 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
869 "andnps\t{$src2, $dst|$dst, $src2}",
871 (v2i64 (and (xor VR128:$src1,
872 (bc_v2i64 (v4i32 immAllOnesV))),
874 def ANDNPSrm : PSI<0x55, MRMSrcMem,
875 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
876 "andnps\t{$src2, $dst|$dst, $src2}",
878 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
879 (bc_v2i64 (v4i32 immAllOnesV))),
880 (memopv2i64 addr:$src2))))]>;
883 let Constraints = "$src1 = $dst" in {
884 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
885 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
886 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
888 VR128:$src, imm:$cc))]>;
889 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
890 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
891 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
892 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
893 (memop addr:$src), imm:$cc))]>;
895 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
896 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
897 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
898 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
900 // Shuffle and unpack instructions
901 let Constraints = "$src1 = $dst" in {
902 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
903 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
904 (outs VR128:$dst), (ins VR128:$src1,
905 VR128:$src2, i32i8imm:$src3),
906 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
908 (v4f32 (vector_shuffle
909 VR128:$src1, VR128:$src2,
910 SHUFP_shuffle_mask:$src3)))]>;
911 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
912 (outs VR128:$dst), (ins VR128:$src1,
913 f128mem:$src2, i32i8imm:$src3),
914 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
916 (v4f32 (vector_shuffle
917 VR128:$src1, (memopv4f32 addr:$src2),
918 SHUFP_shuffle_mask:$src3)))]>;
920 let AddedComplexity = 10 in {
921 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
922 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
923 "unpckhps\t{$src2, $dst|$dst, $src2}",
925 (v4f32 (vector_shuffle
926 VR128:$src1, VR128:$src2,
927 UNPCKH_shuffle_mask)))]>;
928 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
929 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
930 "unpckhps\t{$src2, $dst|$dst, $src2}",
932 (v4f32 (vector_shuffle
933 VR128:$src1, (memopv4f32 addr:$src2),
934 UNPCKH_shuffle_mask)))]>;
936 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
937 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
938 "unpcklps\t{$src2, $dst|$dst, $src2}",
940 (v4f32 (vector_shuffle
941 VR128:$src1, VR128:$src2,
942 UNPCKL_shuffle_mask)))]>;
943 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
944 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
945 "unpcklps\t{$src2, $dst|$dst, $src2}",
947 (v4f32 (vector_shuffle
948 VR128:$src1, (memopv4f32 addr:$src2),
949 UNPCKL_shuffle_mask)))]>;
951 } // Constraints = "$src1 = $dst"
954 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
955 "movmskps\t{$src, $dst|$dst, $src}",
956 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
957 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
958 "movmskpd\t{$src, $dst|$dst, $src}",
959 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
961 // Prefetch intrinsic.
962 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
963 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
964 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
965 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
966 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
967 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
968 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
969 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
971 // Non-temporal stores
972 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
973 "movntps\t{$src, $dst|$dst, $src}",
974 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
976 // Load, store, and memory fence
977 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
980 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
981 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
982 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
983 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
985 // Alias instructions that map zero vector to pxor / xorp* for sse.
986 let isReMaterializable = 1 in
987 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
989 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
991 let Predicates = [HasSSE1] in {
992 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
993 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
994 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
995 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
996 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
999 // FR32 to 128-bit vector conversion.
1000 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
1001 "movss\t{$src, $dst|$dst, $src}",
1003 (v4f32 (scalar_to_vector FR32:$src)))]>;
1004 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1005 "movss\t{$src, $dst|$dst, $src}",
1007 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1009 // FIXME: may not be able to eliminate this movss with coalescing the src and
1010 // dest register classes are different. We really want to write this pattern
1012 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1013 // (f32 FR32:$src)>;
1014 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1015 "movss\t{$src, $dst|$dst, $src}",
1016 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1018 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1019 "movss\t{$src, $dst|$dst, $src}",
1020 [(store (f32 (vector_extract (v4f32 VR128:$src),
1021 (iPTR 0))), addr:$dst)]>;
1024 // Move to lower bits of a VR128, leaving upper bits alone.
1025 // Three operand (but two address) aliases.
1026 let Constraints = "$src1 = $dst" in {
1027 let neverHasSideEffects = 1 in
1028 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1029 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1030 "movss\t{$src2, $dst|$dst, $src2}", []>;
1032 let AddedComplexity = 15 in
1033 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1034 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1035 "movss\t{$src2, $dst|$dst, $src2}",
1037 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1038 MOVL_shuffle_mask)))]>;
1041 // Move to lower bits of a VR128 and zeroing upper bits.
1042 // Loading from memory automatically zeroing upper bits.
1043 let AddedComplexity = 20 in
1044 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1045 "movss\t{$src, $dst|$dst, $src}",
1046 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1047 (loadf32 addr:$src))))))]>;
1049 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1050 (MOVZSS2PSrm addr:$src)>;
1052 //===----------------------------------------------------------------------===//
1053 // SSE2 Instructions
1054 //===----------------------------------------------------------------------===//
1056 // Move Instructions
1057 let neverHasSideEffects = 1 in
1058 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1059 "movsd\t{$src, $dst|$dst, $src}", []>;
1060 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1061 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1062 "movsd\t{$src, $dst|$dst, $src}",
1063 [(set FR64:$dst, (loadf64 addr:$src))]>;
1064 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1065 "movsd\t{$src, $dst|$dst, $src}",
1066 [(store FR64:$src, addr:$dst)]>;
1068 // Conversion instructions
1069 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1070 "cvttsd2si\t{$src, $dst|$dst, $src}",
1071 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1072 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1073 "cvttsd2si\t{$src, $dst|$dst, $src}",
1074 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1075 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1076 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1077 [(set FR32:$dst, (fround FR64:$src))]>;
1078 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1079 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1080 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1081 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1082 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1083 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1084 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1085 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1086 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1088 // SSE2 instructions with XS prefix
1089 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1090 "cvtss2sd\t{$src, $dst|$dst, $src}",
1091 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1092 Requires<[HasSSE2]>;
1093 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1094 "cvtss2sd\t{$src, $dst|$dst, $src}",
1095 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1096 Requires<[HasSSE2]>;
1098 // Match intrinsics which expect XMM operand(s).
1099 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1100 "cvtsd2si\t{$src, $dst|$dst, $src}",
1101 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1102 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1103 "cvtsd2si\t{$src, $dst|$dst, $src}",
1104 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1105 (load addr:$src)))]>;
1107 // Match intrinisics which expect MM and XMM operand(s).
1108 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1109 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1110 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1111 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1112 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1113 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1114 (memop addr:$src)))]>;
1115 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1116 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1117 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1118 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1119 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1120 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1121 (memop addr:$src)))]>;
1122 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1123 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1124 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1125 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1126 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1127 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1128 (load addr:$src)))]>;
1130 // Aliases for intrinsics
1131 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1132 "cvttsd2si\t{$src, $dst|$dst, $src}",
1134 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1135 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1136 "cvttsd2si\t{$src, $dst|$dst, $src}",
1137 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1138 (load addr:$src)))]>;
1140 // Comparison instructions
1141 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1142 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1143 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1144 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1146 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1147 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1148 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1151 let Defs = [EFLAGS] in {
1152 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1153 "ucomisd\t{$src2, $src1|$src1, $src2}",
1154 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1155 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1156 "ucomisd\t{$src2, $src1|$src1, $src2}",
1157 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1158 (implicit EFLAGS)]>;
1161 // Aliases to match intrinsics which expect XMM operand(s).
1162 let Constraints = "$src1 = $dst" in {
1163 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1164 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1165 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1166 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1167 VR128:$src, imm:$cc))]>;
1168 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1169 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1170 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1171 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1172 (load addr:$src), imm:$cc))]>;
1175 let Defs = [EFLAGS] in {
1176 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1177 "ucomisd\t{$src2, $src1|$src1, $src2}",
1178 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1179 (implicit EFLAGS)]>;
1180 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1181 "ucomisd\t{$src2, $src1|$src1, $src2}",
1182 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1183 (implicit EFLAGS)]>;
1185 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1186 "comisd\t{$src2, $src1|$src1, $src2}",
1187 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1188 (implicit EFLAGS)]>;
1189 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1190 "comisd\t{$src2, $src1|$src1, $src2}",
1191 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1192 (implicit EFLAGS)]>;
1195 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1198 // Alias instructions that map fld0 to pxor for sse.
1199 let isReMaterializable = 1 in
1200 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1201 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1202 Requires<[HasSSE2]>, TB, OpSize;
1204 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1206 let neverHasSideEffects = 1 in
1207 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1208 "movapd\t{$src, $dst|$dst, $src}", []>;
1210 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1212 let isSimpleLoad = 1 in
1213 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1214 "movapd\t{$src, $dst|$dst, $src}",
1215 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1217 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1218 let Constraints = "$src1 = $dst" in {
1219 let isCommutable = 1 in {
1220 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1221 (ins FR64:$src1, FR64:$src2),
1222 "andpd\t{$src2, $dst|$dst, $src2}",
1223 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1224 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1225 (ins FR64:$src1, FR64:$src2),
1226 "orpd\t{$src2, $dst|$dst, $src2}",
1227 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1228 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1229 (ins FR64:$src1, FR64:$src2),
1230 "xorpd\t{$src2, $dst|$dst, $src2}",
1231 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1234 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1235 (ins FR64:$src1, f128mem:$src2),
1236 "andpd\t{$src2, $dst|$dst, $src2}",
1237 [(set FR64:$dst, (X86fand FR64:$src1,
1238 (memopfsf64 addr:$src2)))]>;
1239 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1240 (ins FR64:$src1, f128mem:$src2),
1241 "orpd\t{$src2, $dst|$dst, $src2}",
1242 [(set FR64:$dst, (X86for FR64:$src1,
1243 (memopfsf64 addr:$src2)))]>;
1244 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1245 (ins FR64:$src1, f128mem:$src2),
1246 "xorpd\t{$src2, $dst|$dst, $src2}",
1247 [(set FR64:$dst, (X86fxor FR64:$src1,
1248 (memopfsf64 addr:$src2)))]>;
1250 let neverHasSideEffects = 1 in {
1251 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1252 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1253 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1255 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1256 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1257 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1261 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1263 /// In addition, we also have a special variant of the scalar form here to
1264 /// represent the associated intrinsic operation. This form is unlike the
1265 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1266 /// and leaves the top elements undefined.
1268 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1269 /// six "instructions".
1271 let Constraints = "$src1 = $dst" in {
1272 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1273 SDNode OpNode, Intrinsic F64Int,
1274 bit Commutable = 0> {
1275 // Scalar operation, reg+reg.
1276 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1277 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1278 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1279 let isCommutable = Commutable;
1282 // Scalar operation, reg+mem.
1283 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1284 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1285 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1287 // Vector operation, reg+reg.
1288 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1289 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1290 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1291 let isCommutable = Commutable;
1294 // Vector operation, reg+mem.
1295 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1296 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1297 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1299 // Intrinsic operation, reg+reg.
1300 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1301 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1302 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1303 let isCommutable = Commutable;
1306 // Intrinsic operation, reg+mem.
1307 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1308 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1309 [(set VR128:$dst, (F64Int VR128:$src1,
1310 sse_load_f64:$src2))]>;
1314 // Arithmetic instructions
1315 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1316 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1317 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1318 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1320 /// sse2_fp_binop_rm - Other SSE2 binops
1322 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1323 /// instructions for a full-vector intrinsic form. Operations that map
1324 /// onto C operators don't use this form since they just use the plain
1325 /// vector form instead of having a separate vector intrinsic form.
1327 /// This provides a total of eight "instructions".
1329 let Constraints = "$src1 = $dst" in {
1330 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1334 bit Commutable = 0> {
1336 // Scalar operation, reg+reg.
1337 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1338 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1339 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1340 let isCommutable = Commutable;
1343 // Scalar operation, reg+mem.
1344 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1345 (ins FR64:$src1, f64mem:$src2),
1346 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1347 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1349 // Vector operation, reg+reg.
1350 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1351 (ins VR128:$src1, VR128:$src2),
1352 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1353 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1354 let isCommutable = Commutable;
1357 // Vector operation, reg+mem.
1358 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1359 (ins VR128:$src1, f128mem:$src2),
1360 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1361 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1363 // Intrinsic operation, reg+reg.
1364 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1365 (ins VR128:$src1, VR128:$src2),
1366 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1367 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1368 let isCommutable = Commutable;
1371 // Intrinsic operation, reg+mem.
1372 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1373 (ins VR128:$src1, sdmem:$src2),
1374 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1375 [(set VR128:$dst, (F64Int VR128:$src1,
1376 sse_load_f64:$src2))]>;
1378 // Vector intrinsic operation, reg+reg.
1379 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1380 (ins VR128:$src1, VR128:$src2),
1381 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1382 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1383 let isCommutable = Commutable;
1386 // Vector intrinsic operation, reg+mem.
1387 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1388 (ins VR128:$src1, f128mem:$src2),
1389 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1390 [(set VR128:$dst, (V2F64Int VR128:$src1,
1391 (memopv2f64 addr:$src2)))]>;
1395 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1396 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1397 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1398 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1400 //===----------------------------------------------------------------------===//
1401 // SSE packed FP Instructions
1403 // Move Instructions
1404 let neverHasSideEffects = 1 in
1405 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1406 "movapd\t{$src, $dst|$dst, $src}", []>;
1407 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1408 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1409 "movapd\t{$src, $dst|$dst, $src}",
1410 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1412 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1413 "movapd\t{$src, $dst|$dst, $src}",
1414 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1416 let neverHasSideEffects = 1 in
1417 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1418 "movupd\t{$src, $dst|$dst, $src}", []>;
1419 let isSimpleLoad = 1 in
1420 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1421 "movupd\t{$src, $dst|$dst, $src}",
1422 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1423 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1424 "movupd\t{$src, $dst|$dst, $src}",
1425 [(store (v2f64 VR128:$src), addr:$dst)]>;
1427 // Intrinsic forms of MOVUPD load and store
1428 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1429 "movupd\t{$src, $dst|$dst, $src}",
1430 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1431 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1432 "movupd\t{$src, $dst|$dst, $src}",
1433 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1435 let Constraints = "$src1 = $dst" in {
1436 let AddedComplexity = 20 in {
1437 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1438 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1439 "movlpd\t{$src2, $dst|$dst, $src2}",
1441 (v2f64 (vector_shuffle VR128:$src1,
1442 (scalar_to_vector (loadf64 addr:$src2)),
1443 MOVLP_shuffle_mask)))]>;
1444 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1445 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1446 "movhpd\t{$src2, $dst|$dst, $src2}",
1448 (v2f64 (vector_shuffle VR128:$src1,
1449 (scalar_to_vector (loadf64 addr:$src2)),
1450 MOVHP_shuffle_mask)))]>;
1451 } // AddedComplexity
1452 } // Constraints = "$src1 = $dst"
1454 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1455 "movlpd\t{$src, $dst|$dst, $src}",
1456 [(store (f64 (vector_extract (v2f64 VR128:$src),
1457 (iPTR 0))), addr:$dst)]>;
1459 // v2f64 extract element 1 is always custom lowered to unpack high to low
1460 // and extract element 0 so the non-store version isn't too horrible.
1461 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1462 "movhpd\t{$src, $dst|$dst, $src}",
1463 [(store (f64 (vector_extract
1464 (v2f64 (vector_shuffle VR128:$src, (undef),
1465 UNPCKH_shuffle_mask)), (iPTR 0))),
1468 // SSE2 instructions without OpSize prefix
1469 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1470 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1471 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1472 TB, Requires<[HasSSE2]>;
1473 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1474 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1475 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1476 (bitconvert (memopv2i64 addr:$src))))]>,
1477 TB, Requires<[HasSSE2]>;
1479 // SSE2 instructions with XS prefix
1480 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1481 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1482 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1483 XS, Requires<[HasSSE2]>;
1484 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1485 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1486 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1487 (bitconvert (memopv2i64 addr:$src))))]>,
1488 XS, Requires<[HasSSE2]>;
1490 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1491 "cvtps2dq\t{$src, $dst|$dst, $src}",
1492 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1493 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1494 "cvtps2dq\t{$src, $dst|$dst, $src}",
1495 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1496 (memop addr:$src)))]>;
1497 // SSE2 packed instructions with XS prefix
1498 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1499 "cvttps2dq\t{$src, $dst|$dst, $src}",
1500 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1501 XS, Requires<[HasSSE2]>;
1502 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1503 "cvttps2dq\t{$src, $dst|$dst, $src}",
1504 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1505 (memop addr:$src)))]>,
1506 XS, Requires<[HasSSE2]>;
1508 // SSE2 packed instructions with XD prefix
1509 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1510 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1511 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1512 XD, Requires<[HasSSE2]>;
1513 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1514 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1515 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1516 (memop addr:$src)))]>,
1517 XD, Requires<[HasSSE2]>;
1519 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1520 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1521 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1522 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1523 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1524 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1525 (memop addr:$src)))]>;
1527 // SSE2 instructions without OpSize prefix
1528 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1529 "cvtps2pd\t{$src, $dst|$dst, $src}",
1530 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1531 TB, Requires<[HasSSE2]>;
1532 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1533 "cvtps2pd\t{$src, $dst|$dst, $src}",
1534 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1535 (load addr:$src)))]>,
1536 TB, Requires<[HasSSE2]>;
1538 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1539 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1540 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1541 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1542 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1543 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1544 (memop addr:$src)))]>;
1546 // Match intrinsics which expect XMM operand(s).
1547 // Aliases for intrinsics
1548 let Constraints = "$src1 = $dst" in {
1549 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1550 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1551 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1552 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1554 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1555 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1556 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1557 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1558 (loadi32 addr:$src2)))]>;
1559 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1560 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1561 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1562 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1564 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1565 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1566 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1567 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1568 (load addr:$src2)))]>;
1569 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1570 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1571 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1572 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1573 VR128:$src2))]>, XS,
1574 Requires<[HasSSE2]>;
1575 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1576 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1577 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1578 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1579 (load addr:$src2)))]>, XS,
1580 Requires<[HasSSE2]>;
1585 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1587 /// In addition, we also have a special variant of the scalar form here to
1588 /// represent the associated intrinsic operation. This form is unlike the
1589 /// plain scalar form, in that it takes an entire vector (instead of a
1590 /// scalar) and leaves the top elements undefined.
1592 /// And, we have a special variant form for a full-vector intrinsic form.
1594 /// These four forms can each have a reg or a mem operand, so there are a
1595 /// total of eight "instructions".
1597 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1601 bit Commutable = 0> {
1602 // Scalar operation, reg.
1603 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1604 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1605 [(set FR64:$dst, (OpNode FR64:$src))]> {
1606 let isCommutable = Commutable;
1609 // Scalar operation, mem.
1610 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1611 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1612 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1614 // Vector operation, reg.
1615 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1616 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1617 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1618 let isCommutable = Commutable;
1621 // Vector operation, mem.
1622 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1623 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1624 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1626 // Intrinsic operation, reg.
1627 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1628 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1629 [(set VR128:$dst, (F64Int VR128:$src))]> {
1630 let isCommutable = Commutable;
1633 // Intrinsic operation, mem.
1634 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1635 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1636 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1638 // Vector intrinsic operation, reg
1639 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1640 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1641 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1642 let isCommutable = Commutable;
1645 // Vector intrinsic operation, mem
1646 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1647 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1648 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1652 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1653 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1655 // There is no f64 version of the reciprocal approximation instructions.
1658 let Constraints = "$src1 = $dst" in {
1659 let isCommutable = 1 in {
1660 def ANDPDrr : PDI<0x54, MRMSrcReg,
1661 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1662 "andpd\t{$src2, $dst|$dst, $src2}",
1664 (and (bc_v2i64 (v2f64 VR128:$src1)),
1665 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1666 def ORPDrr : PDI<0x56, MRMSrcReg,
1667 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1668 "orpd\t{$src2, $dst|$dst, $src2}",
1670 (or (bc_v2i64 (v2f64 VR128:$src1)),
1671 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1672 def XORPDrr : PDI<0x57, MRMSrcReg,
1673 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1674 "xorpd\t{$src2, $dst|$dst, $src2}",
1676 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1677 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1680 def ANDPDrm : PDI<0x54, MRMSrcMem,
1681 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1682 "andpd\t{$src2, $dst|$dst, $src2}",
1684 (and (bc_v2i64 (v2f64 VR128:$src1)),
1685 (memopv2i64 addr:$src2)))]>;
1686 def ORPDrm : PDI<0x56, MRMSrcMem,
1687 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1688 "orpd\t{$src2, $dst|$dst, $src2}",
1690 (or (bc_v2i64 (v2f64 VR128:$src1)),
1691 (memopv2i64 addr:$src2)))]>;
1692 def XORPDrm : PDI<0x57, MRMSrcMem,
1693 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1694 "xorpd\t{$src2, $dst|$dst, $src2}",
1696 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1697 (memopv2i64 addr:$src2)))]>;
1698 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1699 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1700 "andnpd\t{$src2, $dst|$dst, $src2}",
1702 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1703 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1704 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1705 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1706 "andnpd\t{$src2, $dst|$dst, $src2}",
1708 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1709 (memopv2i64 addr:$src2)))]>;
1712 let Constraints = "$src1 = $dst" in {
1713 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1714 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1715 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1716 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1717 VR128:$src, imm:$cc))]>;
1718 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1719 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1720 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1721 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1722 (memop addr:$src), imm:$cc))]>;
1724 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1725 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1726 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1727 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1729 // Shuffle and unpack instructions
1730 let Constraints = "$src1 = $dst" in {
1731 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1732 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1733 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1734 [(set VR128:$dst, (v2f64 (vector_shuffle
1735 VR128:$src1, VR128:$src2,
1736 SHUFP_shuffle_mask:$src3)))]>;
1737 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1738 (outs VR128:$dst), (ins VR128:$src1,
1739 f128mem:$src2, i8imm:$src3),
1740 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1742 (v2f64 (vector_shuffle
1743 VR128:$src1, (memopv2f64 addr:$src2),
1744 SHUFP_shuffle_mask:$src3)))]>;
1746 let AddedComplexity = 10 in {
1747 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1748 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1749 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1751 (v2f64 (vector_shuffle
1752 VR128:$src1, VR128:$src2,
1753 UNPCKH_shuffle_mask)))]>;
1754 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1755 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1756 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1758 (v2f64 (vector_shuffle
1759 VR128:$src1, (memopv2f64 addr:$src2),
1760 UNPCKH_shuffle_mask)))]>;
1762 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1763 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1764 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1766 (v2f64 (vector_shuffle
1767 VR128:$src1, VR128:$src2,
1768 UNPCKL_shuffle_mask)))]>;
1769 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1770 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1771 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1773 (v2f64 (vector_shuffle
1774 VR128:$src1, (memopv2f64 addr:$src2),
1775 UNPCKL_shuffle_mask)))]>;
1776 } // AddedComplexity
1777 } // Constraints = "$src1 = $dst"
1780 //===----------------------------------------------------------------------===//
1781 // SSE integer instructions
1783 // Move Instructions
1784 let neverHasSideEffects = 1 in
1785 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1786 "movdqa\t{$src, $dst|$dst, $src}", []>;
1787 let isSimpleLoad = 1, mayLoad = 1 in
1788 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1789 "movdqa\t{$src, $dst|$dst, $src}",
1790 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1792 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1793 "movdqa\t{$src, $dst|$dst, $src}",
1794 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1795 let isSimpleLoad = 1, mayLoad = 1 in
1796 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1797 "movdqu\t{$src, $dst|$dst, $src}",
1798 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1799 XS, Requires<[HasSSE2]>;
1801 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1802 "movdqu\t{$src, $dst|$dst, $src}",
1803 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1804 XS, Requires<[HasSSE2]>;
1806 // Intrinsic forms of MOVDQU load and store
1807 let isSimpleLoad = 1 in
1808 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1809 "movdqu\t{$src, $dst|$dst, $src}",
1810 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1811 XS, Requires<[HasSSE2]>;
1812 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1813 "movdqu\t{$src, $dst|$dst, $src}",
1814 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1815 XS, Requires<[HasSSE2]>;
1817 let Constraints = "$src1 = $dst" in {
1819 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1820 bit Commutable = 0> {
1821 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1822 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1823 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1824 let isCommutable = Commutable;
1826 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1827 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1828 [(set VR128:$dst, (IntId VR128:$src1,
1829 (bitconvert (memopv2i64 addr:$src2))))]>;
1832 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1834 Intrinsic IntId, Intrinsic IntId2> {
1835 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1836 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1837 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1838 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1839 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1840 [(set VR128:$dst, (IntId VR128:$src1,
1841 (bitconvert (memopv2i64 addr:$src2))))]>;
1842 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1844 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1847 /// PDI_binop_rm - Simple SSE2 binary operator.
1848 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1849 ValueType OpVT, bit Commutable = 0> {
1850 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1852 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1853 let isCommutable = Commutable;
1855 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1856 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1857 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1858 (bitconvert (memopv2i64 addr:$src2)))))]>;
1861 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1863 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1864 /// to collapse (bitconvert VT to VT) into its operand.
1866 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1867 bit Commutable = 0> {
1868 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1869 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1870 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1871 let isCommutable = Commutable;
1873 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1874 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1875 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1878 } // Constraints = "$src1 = $dst"
1880 // 128-bit Integer Arithmetic
1882 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1883 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1884 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1885 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1887 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1888 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1889 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1890 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1892 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1893 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1894 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1895 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1897 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1898 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1899 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1900 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1902 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1904 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1905 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1906 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1908 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1910 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1911 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1914 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1915 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1916 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1917 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1918 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1921 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1922 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1923 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1924 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1925 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1926 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1928 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1929 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1930 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1931 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1932 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1933 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1935 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1936 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1937 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1938 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1940 // 128-bit logical shifts.
1941 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1942 def PSLLDQri : PDIi8<0x73, MRM7r,
1943 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1944 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1945 def PSRLDQri : PDIi8<0x73, MRM3r,
1946 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1947 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1948 // PSRADQri doesn't exist in SSE[1-3].
1951 let Predicates = [HasSSE2] in {
1952 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1953 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1954 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1955 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1956 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1957 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1959 // Shift up / down and insert zero's.
1960 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1961 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1962 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1963 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1967 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1968 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1969 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1971 let Constraints = "$src1 = $dst" in {
1972 def PANDNrr : PDI<0xDF, MRMSrcReg,
1973 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1974 "pandn\t{$src2, $dst|$dst, $src2}",
1975 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1978 def PANDNrm : PDI<0xDF, MRMSrcMem,
1979 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1980 "pandn\t{$src2, $dst|$dst, $src2}",
1981 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1982 (memopv2i64 addr:$src2))))]>;
1985 // SSE2 Integer comparison
1986 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1987 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1988 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1989 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1990 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1991 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1993 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
1994 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
1995 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
1996 (PCMPEQBrm VR128:$src1, addr:$src2)>;
1997 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
1998 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
1999 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2000 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2001 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2002 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2003 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2004 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2006 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2007 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2008 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2009 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2010 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2011 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2012 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2013 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2014 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2015 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2016 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2017 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2020 // Pack instructions
2021 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2022 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2023 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2025 // Shuffle and unpack instructions
2026 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2027 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2028 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2029 [(set VR128:$dst, (v4i32 (vector_shuffle
2030 VR128:$src1, (undef),
2031 PSHUFD_shuffle_mask:$src2)))]>;
2032 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2033 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2034 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2035 [(set VR128:$dst, (v4i32 (vector_shuffle
2036 (bc_v4i32(memopv2i64 addr:$src1)),
2038 PSHUFD_shuffle_mask:$src2)))]>;
2040 // SSE2 with ImmT == Imm8 and XS prefix.
2041 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2042 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2043 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2044 [(set VR128:$dst, (v8i16 (vector_shuffle
2045 VR128:$src1, (undef),
2046 PSHUFHW_shuffle_mask:$src2)))]>,
2047 XS, Requires<[HasSSE2]>;
2048 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2049 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2050 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2051 [(set VR128:$dst, (v8i16 (vector_shuffle
2052 (bc_v8i16 (memopv2i64 addr:$src1)),
2054 PSHUFHW_shuffle_mask:$src2)))]>,
2055 XS, Requires<[HasSSE2]>;
2057 // SSE2 with ImmT == Imm8 and XD prefix.
2058 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2059 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2060 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2061 [(set VR128:$dst, (v8i16 (vector_shuffle
2062 VR128:$src1, (undef),
2063 PSHUFLW_shuffle_mask:$src2)))]>,
2064 XD, Requires<[HasSSE2]>;
2065 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2066 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2067 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2068 [(set VR128:$dst, (v8i16 (vector_shuffle
2069 (bc_v8i16 (memopv2i64 addr:$src1)),
2071 PSHUFLW_shuffle_mask:$src2)))]>,
2072 XD, Requires<[HasSSE2]>;
2075 let Constraints = "$src1 = $dst" in {
2076 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2077 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2078 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2080 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2081 UNPCKL_shuffle_mask)))]>;
2082 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2083 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2084 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2086 (v16i8 (vector_shuffle VR128:$src1,
2087 (bc_v16i8 (memopv2i64 addr:$src2)),
2088 UNPCKL_shuffle_mask)))]>;
2089 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2090 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2091 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2093 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2094 UNPCKL_shuffle_mask)))]>;
2095 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2096 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2097 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2099 (v8i16 (vector_shuffle VR128:$src1,
2100 (bc_v8i16 (memopv2i64 addr:$src2)),
2101 UNPCKL_shuffle_mask)))]>;
2102 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2103 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2104 "punpckldq\t{$src2, $dst|$dst, $src2}",
2106 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2107 UNPCKL_shuffle_mask)))]>;
2108 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2109 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2110 "punpckldq\t{$src2, $dst|$dst, $src2}",
2112 (v4i32 (vector_shuffle VR128:$src1,
2113 (bc_v4i32 (memopv2i64 addr:$src2)),
2114 UNPCKL_shuffle_mask)))]>;
2115 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2116 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2117 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2119 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2120 UNPCKL_shuffle_mask)))]>;
2121 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2122 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2123 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2125 (v2i64 (vector_shuffle VR128:$src1,
2126 (memopv2i64 addr:$src2),
2127 UNPCKL_shuffle_mask)))]>;
2129 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2130 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2131 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2133 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2134 UNPCKH_shuffle_mask)))]>;
2135 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2136 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2137 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2139 (v16i8 (vector_shuffle VR128:$src1,
2140 (bc_v16i8 (memopv2i64 addr:$src2)),
2141 UNPCKH_shuffle_mask)))]>;
2142 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2143 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2144 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2146 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2147 UNPCKH_shuffle_mask)))]>;
2148 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2149 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2150 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2152 (v8i16 (vector_shuffle VR128:$src1,
2153 (bc_v8i16 (memopv2i64 addr:$src2)),
2154 UNPCKH_shuffle_mask)))]>;
2155 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2156 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2157 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2159 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2160 UNPCKH_shuffle_mask)))]>;
2161 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2162 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2163 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2165 (v4i32 (vector_shuffle VR128:$src1,
2166 (bc_v4i32 (memopv2i64 addr:$src2)),
2167 UNPCKH_shuffle_mask)))]>;
2168 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2169 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2170 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2172 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2173 UNPCKH_shuffle_mask)))]>;
2174 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2175 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2176 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2178 (v2i64 (vector_shuffle VR128:$src1,
2179 (memopv2i64 addr:$src2),
2180 UNPCKH_shuffle_mask)))]>;
2184 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2185 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2186 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2187 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2189 let Constraints = "$src1 = $dst" in {
2190 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2191 (outs VR128:$dst), (ins VR128:$src1,
2192 GR32:$src2, i32i8imm:$src3),
2193 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2195 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2196 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2197 (outs VR128:$dst), (ins VR128:$src1,
2198 i16mem:$src2, i32i8imm:$src3),
2199 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2201 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2206 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2207 "pmovmskb\t{$src, $dst|$dst, $src}",
2208 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2210 // Conditional store
2212 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2213 "maskmovdqu\t{$mask, $src|$src, $mask}",
2214 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2216 // Non-temporal stores
2217 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2218 "movntpd\t{$src, $dst|$dst, $src}",
2219 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2220 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2221 "movntdq\t{$src, $dst|$dst, $src}",
2222 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2223 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2224 "movnti\t{$src, $dst|$dst, $src}",
2225 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2226 TB, Requires<[HasSSE2]>;
2229 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2230 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2231 TB, Requires<[HasSSE2]>;
2233 // Load, store, and memory fence
2234 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2235 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2236 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2237 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2239 //TODO: custom lower this so as to never even generate the noop
2240 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2242 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2243 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2244 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2247 // Alias instructions that map zero vector to pxor / xorp* for sse.
2248 let isReMaterializable = 1 in
2249 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2250 "pcmpeqd\t$dst, $dst",
2251 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2253 // FR64 to 128-bit vector conversion.
2254 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2255 "movsd\t{$src, $dst|$dst, $src}",
2257 (v2f64 (scalar_to_vector FR64:$src)))]>;
2258 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2259 "movsd\t{$src, $dst|$dst, $src}",
2261 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2263 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2264 "movd\t{$src, $dst|$dst, $src}",
2266 (v4i32 (scalar_to_vector GR32:$src)))]>;
2267 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2268 "movd\t{$src, $dst|$dst, $src}",
2270 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2272 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2273 "movd\t{$src, $dst|$dst, $src}",
2274 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2276 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2277 "movd\t{$src, $dst|$dst, $src}",
2278 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2280 // SSE2 instructions with XS prefix
2281 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2282 "movq\t{$src, $dst|$dst, $src}",
2284 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2285 Requires<[HasSSE2]>;
2286 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2287 "movq\t{$src, $dst|$dst, $src}",
2288 [(store (i64 (vector_extract (v2i64 VR128:$src),
2289 (iPTR 0))), addr:$dst)]>;
2291 // FIXME: may not be able to eliminate this movss with coalescing the src and
2292 // dest register classes are different. We really want to write this pattern
2294 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2295 // (f32 FR32:$src)>;
2296 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2297 "movsd\t{$src, $dst|$dst, $src}",
2298 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2300 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2301 "movsd\t{$src, $dst|$dst, $src}",
2302 [(store (f64 (vector_extract (v2f64 VR128:$src),
2303 (iPTR 0))), addr:$dst)]>;
2304 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2305 "movd\t{$src, $dst|$dst, $src}",
2306 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2308 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2309 "movd\t{$src, $dst|$dst, $src}",
2310 [(store (i32 (vector_extract (v4i32 VR128:$src),
2311 (iPTR 0))), addr:$dst)]>;
2313 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2314 "movd\t{$src, $dst|$dst, $src}",
2315 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2316 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2317 "movd\t{$src, $dst|$dst, $src}",
2318 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2321 // Move to lower bits of a VR128, leaving upper bits alone.
2322 // Three operand (but two address) aliases.
2323 let Constraints = "$src1 = $dst" in {
2324 let neverHasSideEffects = 1 in
2325 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2326 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2327 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2329 let AddedComplexity = 15 in
2330 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2331 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2332 "movsd\t{$src2, $dst|$dst, $src2}",
2334 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2335 MOVL_shuffle_mask)))]>;
2338 // Store / copy lower 64-bits of a XMM register.
2339 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2340 "movq\t{$src, $dst|$dst, $src}",
2341 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2343 // Move to lower bits of a VR128 and zeroing upper bits.
2344 // Loading from memory automatically zeroing upper bits.
2345 let AddedComplexity = 20 in {
2346 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2347 "movsd\t{$src, $dst|$dst, $src}",
2349 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2350 (loadf64 addr:$src))))))]>;
2352 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2353 (MOVZSD2PDrm addr:$src)>;
2354 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2355 (MOVZSD2PDrm addr:$src)>;
2356 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2359 // movd / movq to XMM register zero-extends
2360 let AddedComplexity = 15 in {
2361 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2362 "movd\t{$src, $dst|$dst, $src}",
2363 [(set VR128:$dst, (v4i32 (X86vzmovl
2364 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2365 // This is X86-64 only.
2366 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2367 "mov{d|q}\t{$src, $dst|$dst, $src}",
2368 [(set VR128:$dst, (v2i64 (X86vzmovl
2369 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2372 let AddedComplexity = 20 in {
2373 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2374 "movd\t{$src, $dst|$dst, $src}",
2376 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2377 (loadi32 addr:$src))))))]>;
2379 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2380 (MOVZDI2PDIrm addr:$src)>;
2381 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2382 (MOVZDI2PDIrm addr:$src)>;
2383 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2384 (MOVZDI2PDIrm addr:$src)>;
2386 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2387 "movq\t{$src, $dst|$dst, $src}",
2389 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2390 (loadi64 addr:$src))))))]>, XS,
2391 Requires<[HasSSE2]>;
2393 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2394 (MOVZQI2PQIrm addr:$src)>;
2395 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2396 (MOVZQI2PQIrm addr:$src)>;
2397 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2400 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2401 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2402 let AddedComplexity = 15 in
2403 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2404 "movq\t{$src, $dst|$dst, $src}",
2405 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2406 XS, Requires<[HasSSE2]>;
2408 let AddedComplexity = 20 in {
2409 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2410 "movq\t{$src, $dst|$dst, $src}",
2411 [(set VR128:$dst, (v2i64 (X86vzmovl
2412 (loadv2i64 addr:$src))))]>,
2413 XS, Requires<[HasSSE2]>;
2415 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2416 (MOVZPQILo2PQIrm addr:$src)>;
2419 //===----------------------------------------------------------------------===//
2420 // SSE3 Instructions
2421 //===----------------------------------------------------------------------===//
2423 // Move Instructions
2424 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2425 "movshdup\t{$src, $dst|$dst, $src}",
2426 [(set VR128:$dst, (v4f32 (vector_shuffle
2427 VR128:$src, (undef),
2428 MOVSHDUP_shuffle_mask)))]>;
2429 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2430 "movshdup\t{$src, $dst|$dst, $src}",
2431 [(set VR128:$dst, (v4f32 (vector_shuffle
2432 (memopv4f32 addr:$src), (undef),
2433 MOVSHDUP_shuffle_mask)))]>;
2435 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2436 "movsldup\t{$src, $dst|$dst, $src}",
2437 [(set VR128:$dst, (v4f32 (vector_shuffle
2438 VR128:$src, (undef),
2439 MOVSLDUP_shuffle_mask)))]>;
2440 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2441 "movsldup\t{$src, $dst|$dst, $src}",
2442 [(set VR128:$dst, (v4f32 (vector_shuffle
2443 (memopv4f32 addr:$src), (undef),
2444 MOVSLDUP_shuffle_mask)))]>;
2446 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2447 "movddup\t{$src, $dst|$dst, $src}",
2448 [(set VR128:$dst, (v2f64 (vector_shuffle
2449 VR128:$src, (undef),
2450 SSE_splat_lo_mask)))]>;
2451 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2452 "movddup\t{$src, $dst|$dst, $src}",
2454 (v2f64 (vector_shuffle
2455 (scalar_to_vector (loadf64 addr:$src)),
2457 SSE_splat_lo_mask)))]>;
2460 let Constraints = "$src1 = $dst" in {
2461 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2462 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2463 "addsubps\t{$src2, $dst|$dst, $src2}",
2464 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2466 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2467 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2468 "addsubps\t{$src2, $dst|$dst, $src2}",
2469 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2470 (memop addr:$src2)))]>;
2471 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2472 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2473 "addsubpd\t{$src2, $dst|$dst, $src2}",
2474 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2476 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2477 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2478 "addsubpd\t{$src2, $dst|$dst, $src2}",
2479 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2480 (memop addr:$src2)))]>;
2483 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2484 "lddqu\t{$src, $dst|$dst, $src}",
2485 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2488 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2489 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2490 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2491 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2492 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2493 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2494 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2495 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2496 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2497 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2498 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2499 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2500 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2501 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2502 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2503 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2505 let Constraints = "$src1 = $dst" in {
2506 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2507 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2508 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2509 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2510 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2511 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2512 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2513 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2516 // Thread synchronization
2517 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2518 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2519 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2520 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2522 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2523 let AddedComplexity = 15 in
2524 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2525 MOVSHDUP_shuffle_mask)),
2526 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2527 let AddedComplexity = 20 in
2528 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2529 MOVSHDUP_shuffle_mask)),
2530 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2532 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2533 let AddedComplexity = 15 in
2534 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2535 MOVSLDUP_shuffle_mask)),
2536 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2537 let AddedComplexity = 20 in
2538 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2539 MOVSLDUP_shuffle_mask)),
2540 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2542 //===----------------------------------------------------------------------===//
2543 // SSSE3 Instructions
2544 //===----------------------------------------------------------------------===//
2546 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2547 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2548 Intrinsic IntId64, Intrinsic IntId128> {
2549 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2551 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2553 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2554 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2556 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2558 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2560 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2561 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2564 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2566 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2569 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2572 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2573 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2574 Intrinsic IntId64, Intrinsic IntId128> {
2575 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2577 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2578 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2580 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2582 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2585 (bitconvert (memopv4i16 addr:$src))))]>;
2587 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2590 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2593 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2595 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2598 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2601 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2602 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2603 Intrinsic IntId64, Intrinsic IntId128> {
2604 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2606 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2607 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2609 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2611 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2614 (bitconvert (memopv2i32 addr:$src))))]>;
2616 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2618 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2619 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2622 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2624 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2627 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2630 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2631 int_x86_ssse3_pabs_b,
2632 int_x86_ssse3_pabs_b_128>;
2633 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2634 int_x86_ssse3_pabs_w,
2635 int_x86_ssse3_pabs_w_128>;
2636 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2637 int_x86_ssse3_pabs_d,
2638 int_x86_ssse3_pabs_d_128>;
2640 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2641 let Constraints = "$src1 = $dst" in {
2642 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2643 Intrinsic IntId64, Intrinsic IntId128,
2644 bit Commutable = 0> {
2645 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2646 (ins VR64:$src1, VR64:$src2),
2647 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2648 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2649 let isCommutable = Commutable;
2651 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2652 (ins VR64:$src1, i64mem:$src2),
2653 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2655 (IntId64 VR64:$src1,
2656 (bitconvert (memopv8i8 addr:$src2))))]>;
2658 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2659 (ins VR128:$src1, VR128:$src2),
2660 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2661 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2663 let isCommutable = Commutable;
2665 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2666 (ins VR128:$src1, i128mem:$src2),
2667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2669 (IntId128 VR128:$src1,
2670 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2674 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2675 let Constraints = "$src1 = $dst" in {
2676 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2677 Intrinsic IntId64, Intrinsic IntId128,
2678 bit Commutable = 0> {
2679 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2680 (ins VR64:$src1, VR64:$src2),
2681 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2682 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2683 let isCommutable = Commutable;
2685 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2686 (ins VR64:$src1, i64mem:$src2),
2687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2689 (IntId64 VR64:$src1,
2690 (bitconvert (memopv4i16 addr:$src2))))]>;
2692 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2693 (ins VR128:$src1, VR128:$src2),
2694 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2695 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2697 let isCommutable = Commutable;
2699 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2700 (ins VR128:$src1, i128mem:$src2),
2701 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2703 (IntId128 VR128:$src1,
2704 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2708 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2709 let Constraints = "$src1 = $dst" in {
2710 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2711 Intrinsic IntId64, Intrinsic IntId128,
2712 bit Commutable = 0> {
2713 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2714 (ins VR64:$src1, VR64:$src2),
2715 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2716 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2717 let isCommutable = Commutable;
2719 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2720 (ins VR64:$src1, i64mem:$src2),
2721 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2723 (IntId64 VR64:$src1,
2724 (bitconvert (memopv2i32 addr:$src2))))]>;
2726 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2727 (ins VR128:$src1, VR128:$src2),
2728 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2729 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2731 let isCommutable = Commutable;
2733 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2734 (ins VR128:$src1, i128mem:$src2),
2735 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2737 (IntId128 VR128:$src1,
2738 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2742 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2743 int_x86_ssse3_phadd_w,
2744 int_x86_ssse3_phadd_w_128>;
2745 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2746 int_x86_ssse3_phadd_d,
2747 int_x86_ssse3_phadd_d_128>;
2748 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2749 int_x86_ssse3_phadd_sw,
2750 int_x86_ssse3_phadd_sw_128>;
2751 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2752 int_x86_ssse3_phsub_w,
2753 int_x86_ssse3_phsub_w_128>;
2754 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2755 int_x86_ssse3_phsub_d,
2756 int_x86_ssse3_phsub_d_128>;
2757 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2758 int_x86_ssse3_phsub_sw,
2759 int_x86_ssse3_phsub_sw_128>;
2760 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2761 int_x86_ssse3_pmadd_ub_sw,
2762 int_x86_ssse3_pmadd_ub_sw_128>;
2763 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2764 int_x86_ssse3_pmul_hr_sw,
2765 int_x86_ssse3_pmul_hr_sw_128, 1>;
2766 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2767 int_x86_ssse3_pshuf_b,
2768 int_x86_ssse3_pshuf_b_128>;
2769 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2770 int_x86_ssse3_psign_b,
2771 int_x86_ssse3_psign_b_128>;
2772 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2773 int_x86_ssse3_psign_w,
2774 int_x86_ssse3_psign_w_128>;
2775 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2776 int_x86_ssse3_psign_d,
2777 int_x86_ssse3_psign_d_128>;
2779 let Constraints = "$src1 = $dst" in {
2780 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2781 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2782 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2784 (int_x86_ssse3_palign_r
2785 VR64:$src1, VR64:$src2,
2787 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2788 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2789 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2791 (int_x86_ssse3_palign_r
2793 (bitconvert (memopv2i32 addr:$src2)),
2796 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2797 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2798 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2800 (int_x86_ssse3_palign_r_128
2801 VR128:$src1, VR128:$src2,
2802 imm:$src3))]>, OpSize;
2803 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2804 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2805 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2807 (int_x86_ssse3_palign_r_128
2809 (bitconvert (memopv4i32 addr:$src2)),
2810 imm:$src3))]>, OpSize;
2813 //===----------------------------------------------------------------------===//
2814 // Non-Instruction Patterns
2815 //===----------------------------------------------------------------------===//
2817 // extload f32 -> f64. This matches load+fextend because we have a hack in
2818 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2819 // Since these loads aren't folded into the fextend, we have to match it
2821 let Predicates = [HasSSE2] in
2822 def : Pat<(fextend (loadf32 addr:$src)),
2823 (CVTSS2SDrm addr:$src)>;
2826 let Predicates = [HasSSE2] in {
2827 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2828 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2829 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2830 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2831 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2832 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2833 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2834 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2835 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2836 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2837 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2838 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2839 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2840 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2841 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2842 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2843 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2844 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2845 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2846 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2847 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2848 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2849 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2850 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2851 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2852 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2853 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2854 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2855 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2856 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2859 // Move scalar to XMM zero-extended
2860 // movd to XMM register zero-extends
2861 let AddedComplexity = 15 in {
2862 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2863 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2864 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2865 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2866 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2867 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2868 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2869 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2870 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2873 // Splat v2f64 / v2i64
2874 let AddedComplexity = 10 in {
2875 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2876 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2877 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2878 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2879 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2880 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2881 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2882 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2885 // Special unary SHUFPSrri case.
2886 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2887 SHUFP_unary_shuffle_mask:$sm)),
2888 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2889 Requires<[HasSSE1]>;
2890 // Special unary SHUFPDrri case.
2891 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2892 SHUFP_unary_shuffle_mask:$sm)),
2893 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2894 Requires<[HasSSE2]>;
2895 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2896 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2897 SHUFP_unary_shuffle_mask:$sm),
2898 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2899 Requires<[HasSSE2]>;
2900 // Special binary v4i32 shuffle cases with SHUFPS.
2901 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2902 PSHUFD_binary_shuffle_mask:$sm)),
2903 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2904 Requires<[HasSSE2]>;
2905 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2906 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2907 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2908 Requires<[HasSSE2]>;
2909 // Special binary v2i64 shuffle cases using SHUFPDrri.
2910 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2911 SHUFP_shuffle_mask:$sm)),
2912 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2913 Requires<[HasSSE2]>;
2914 // Special unary SHUFPDrri case.
2915 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2916 SHUFP_unary_shuffle_mask:$sm)),
2917 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2918 Requires<[HasSSE2]>;
2920 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2921 let AddedComplexity = 10 in {
2922 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2923 UNPCKL_v_undef_shuffle_mask)),
2924 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2925 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2926 UNPCKL_v_undef_shuffle_mask)),
2927 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2928 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2929 UNPCKL_v_undef_shuffle_mask)),
2930 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2931 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2932 UNPCKL_v_undef_shuffle_mask)),
2933 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2936 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2937 let AddedComplexity = 10 in {
2938 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2939 UNPCKH_v_undef_shuffle_mask)),
2940 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2941 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2942 UNPCKH_v_undef_shuffle_mask)),
2943 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2944 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2945 UNPCKH_v_undef_shuffle_mask)),
2946 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2947 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2948 UNPCKH_v_undef_shuffle_mask)),
2949 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2952 let AddedComplexity = 15 in {
2953 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2954 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2955 MOVHP_shuffle_mask)),
2956 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2958 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2959 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2960 MOVHLPS_shuffle_mask)),
2961 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2963 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2964 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2965 MOVHLPS_v_undef_shuffle_mask)),
2966 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2967 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2968 MOVHLPS_v_undef_shuffle_mask)),
2969 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2972 let AddedComplexity = 20 in {
2973 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2974 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2975 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2976 MOVLP_shuffle_mask)),
2977 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2978 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2979 MOVLP_shuffle_mask)),
2980 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2981 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2982 MOVHP_shuffle_mask)),
2983 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2984 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2985 MOVHP_shuffle_mask)),
2986 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2988 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2989 (bc_v4i32 (memopv2i64 addr:$src2)),
2990 MOVLP_shuffle_mask)),
2991 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2992 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2993 MOVLP_shuffle_mask)),
2994 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2995 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2996 (bc_v4i32 (memopv2i64 addr:$src2)),
2997 MOVHP_shuffle_mask)),
2998 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2999 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
3000 MOVHP_shuffle_mask)),
3001 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3004 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3005 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3006 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3007 MOVLP_shuffle_mask)), addr:$src1),
3008 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3009 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3010 MOVLP_shuffle_mask)), addr:$src1),
3011 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3012 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3013 MOVHP_shuffle_mask)), addr:$src1),
3014 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3015 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3016 MOVHP_shuffle_mask)), addr:$src1),
3017 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3019 def : Pat<(store (v4i32 (vector_shuffle
3020 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3021 MOVLP_shuffle_mask)), addr:$src1),
3022 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3023 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3024 MOVLP_shuffle_mask)), addr:$src1),
3025 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3026 def : Pat<(store (v4i32 (vector_shuffle
3027 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3028 MOVHP_shuffle_mask)), addr:$src1),
3029 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3030 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3031 MOVHP_shuffle_mask)), addr:$src1),
3032 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3035 let AddedComplexity = 15 in {
3036 // Setting the lowest element in the vector.
3037 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3038 MOVL_shuffle_mask)),
3039 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3040 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3041 MOVL_shuffle_mask)),
3042 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3044 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3045 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3046 MOVLP_shuffle_mask)),
3047 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3048 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3049 MOVLP_shuffle_mask)),
3050 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3053 // Set lowest element and zero upper elements.
3054 let AddedComplexity = 15 in
3055 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3056 MOVL_shuffle_mask)),
3057 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3058 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3059 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3061 // Some special case pandn patterns.
3062 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3064 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3065 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3067 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3068 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3070 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3072 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3073 (memop addr:$src2))),
3074 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3075 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3076 (memop addr:$src2))),
3077 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3078 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3079 (memop addr:$src2))),
3080 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3082 // vector -> vector casts
3083 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3084 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3085 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3086 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3088 // Use movaps / movups for SSE integer load / store (one byte shorter).
3089 def : Pat<(alignedloadv4i32 addr:$src),
3090 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3091 def : Pat<(loadv4i32 addr:$src),
3092 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3093 def : Pat<(alignedloadv2i64 addr:$src),
3094 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3095 def : Pat<(loadv2i64 addr:$src),
3096 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3098 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3099 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3100 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3101 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3102 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3103 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3104 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3105 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3106 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3107 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3108 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3109 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3110 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3111 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3112 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3113 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3115 //===----------------------------------------------------------------------===//
3116 // SSE4.1 Instructions
3117 //===----------------------------------------------------------------------===//
3119 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3120 bits<8> opcsd, bits<8> opcpd,
3125 Intrinsic V2F64Int> {
3126 // Intrinsic operation, reg.
3127 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3128 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3129 !strconcat(OpcodeStr,
3130 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3131 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3134 // Intrinsic operation, mem.
3135 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3136 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3137 !strconcat(OpcodeStr,
3138 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3139 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3142 // Vector intrinsic operation, reg
3143 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3144 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3145 !strconcat(OpcodeStr,
3146 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3147 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3150 // Vector intrinsic operation, mem
3151 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3152 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3153 !strconcat(OpcodeStr,
3154 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3156 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3159 // Intrinsic operation, reg.
3160 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3161 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3162 !strconcat(OpcodeStr,
3163 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3164 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3167 // Intrinsic operation, mem.
3168 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3169 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3170 !strconcat(OpcodeStr,
3171 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3175 // Vector intrinsic operation, reg
3176 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3177 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3178 !strconcat(OpcodeStr,
3179 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3180 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3183 // Vector intrinsic operation, mem
3184 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3185 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3186 !strconcat(OpcodeStr,
3187 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3189 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3193 // FP round - roundss, roundps, roundsd, roundpd
3194 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3195 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3196 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3198 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3199 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3200 Intrinsic IntId128> {
3201 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3203 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3205 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3207 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3210 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3213 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3214 int_x86_sse41_phminposuw>;
3216 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3217 let Constraints = "$src1 = $dst" in {
3218 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3219 Intrinsic IntId128, bit Commutable = 0> {
3220 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3221 (ins VR128:$src1, VR128:$src2),
3222 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3223 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3225 let isCommutable = Commutable;
3227 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3228 (ins VR128:$src1, i128mem:$src2),
3229 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3231 (IntId128 VR128:$src1,
3232 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3236 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3237 int_x86_sse41_pcmpeqq, 1>;
3238 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3239 int_x86_sse41_packusdw, 0>;
3240 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3241 int_x86_sse41_pminsb, 1>;
3242 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3243 int_x86_sse41_pminsd, 1>;
3244 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3245 int_x86_sse41_pminud, 1>;
3246 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3247 int_x86_sse41_pminuw, 1>;
3248 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3249 int_x86_sse41_pmaxsb, 1>;
3250 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3251 int_x86_sse41_pmaxsd, 1>;
3252 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3253 int_x86_sse41_pmaxud, 1>;
3254 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3255 int_x86_sse41_pmaxuw, 1>;
3257 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3258 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3259 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3260 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3263 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3264 let Constraints = "$src1 = $dst" in {
3265 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3266 SDNode OpNode, Intrinsic IntId128,
3267 bit Commutable = 0> {
3268 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3269 (ins VR128:$src1, VR128:$src2),
3270 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3271 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3272 VR128:$src2))]>, OpSize {
3273 let isCommutable = Commutable;
3275 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3276 (ins VR128:$src1, VR128:$src2),
3277 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3278 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3280 let isCommutable = Commutable;
3282 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3283 (ins VR128:$src1, i128mem:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3286 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3287 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3288 (ins VR128:$src1, i128mem:$src2),
3289 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3291 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3295 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3296 int_x86_sse41_pmulld, 1>;
3297 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3298 int_x86_sse41_pmuldq, 1>;
3301 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3302 let Constraints = "$src1 = $dst" in {
3303 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3304 Intrinsic IntId128, bit Commutable = 0> {
3305 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3306 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3307 !strconcat(OpcodeStr,
3308 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3310 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3312 let isCommutable = Commutable;
3314 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3315 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3316 !strconcat(OpcodeStr,
3317 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3319 (IntId128 VR128:$src1,
3320 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3325 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3326 int_x86_sse41_blendps, 0>;
3327 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3328 int_x86_sse41_blendpd, 0>;
3329 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3330 int_x86_sse41_pblendw, 0>;
3331 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3332 int_x86_sse41_dpps, 1>;
3333 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3334 int_x86_sse41_dppd, 1>;
3335 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3336 int_x86_sse41_mpsadbw, 1>;
3339 /// SS41I_ternary_int - SSE 4.1 ternary operator
3340 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3341 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3342 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3343 (ins VR128:$src1, VR128:$src2),
3344 !strconcat(OpcodeStr,
3345 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3346 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3349 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3350 (ins VR128:$src1, i128mem:$src2),
3351 !strconcat(OpcodeStr,
3352 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3355 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3359 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3360 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3361 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3364 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3365 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3366 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3367 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3369 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3370 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3372 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3375 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3376 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3377 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3378 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3379 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3380 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3382 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3383 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3384 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3385 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3387 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3388 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3390 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3393 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3394 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3395 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3396 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3398 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3399 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3400 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3401 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3403 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3404 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3406 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3409 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3410 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3413 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3414 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3415 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3416 (ins VR128:$src1, i32i8imm:$src2),
3417 !strconcat(OpcodeStr,
3418 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3419 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3421 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3422 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3423 !strconcat(OpcodeStr,
3424 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3427 // There's an AssertZext in the way of writing the store pattern
3428 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3431 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3434 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3435 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3436 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3437 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3438 !strconcat(OpcodeStr,
3439 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3442 // There's an AssertZext in the way of writing the store pattern
3443 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3446 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3449 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3450 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3451 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3452 (ins VR128:$src1, i32i8imm:$src2),
3453 !strconcat(OpcodeStr,
3454 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3456 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3457 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3458 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3459 !strconcat(OpcodeStr,
3460 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3461 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3462 addr:$dst)]>, OpSize;
3465 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3468 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3470 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3471 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3472 (ins VR128:$src1, i32i8imm:$src2),
3473 !strconcat(OpcodeStr,
3474 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3476 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3478 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3479 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3480 !strconcat(OpcodeStr,
3481 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3482 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3483 addr:$dst)]>, OpSize;
3486 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3488 let Constraints = "$src1 = $dst" in {
3489 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3490 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3491 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3492 !strconcat(OpcodeStr,
3493 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3495 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3496 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3497 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3498 !strconcat(OpcodeStr,
3499 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3501 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3502 imm:$src3))]>, OpSize;
3506 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3508 let Constraints = "$src1 = $dst" in {
3509 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3510 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3511 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3512 !strconcat(OpcodeStr,
3513 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3515 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3517 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3518 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3519 !strconcat(OpcodeStr,
3520 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3522 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3523 imm:$src3)))]>, OpSize;
3527 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3529 let Constraints = "$src1 = $dst" in {
3530 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3531 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3532 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3533 !strconcat(OpcodeStr,
3534 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3536 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3537 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3538 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3539 !strconcat(OpcodeStr,
3540 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3542 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3543 imm:$src3))]>, OpSize;
3547 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3549 let Defs = [EFLAGS] in {
3550 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3551 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3552 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3553 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3556 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3557 "movntdqa\t{$src, $dst|$dst, $src}",
3558 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3560 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3561 let Constraints = "$src1 = $dst" in {
3562 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3563 Intrinsic IntId128, bit Commutable = 0> {
3564 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3565 (ins VR128:$src1, VR128:$src2),
3566 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3567 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3569 let isCommutable = Commutable;
3571 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3572 (ins VR128:$src1, i128mem:$src2),
3573 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3575 (IntId128 VR128:$src1,
3576 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3580 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3582 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3583 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3584 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3585 (PCMPGTQrm VR128:$src1, addr:$src2)>;