1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad, [SDNPHasChain]>;
22 def X86loadu : SDNode<"X86ISD::LOAD_UA", SDTLoad, [SDNPHasChain]>;
23 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
24 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
25 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
26 [SDNPCommutative, SDNPAssociative]>;
27 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
28 [SDNPCommutative, SDNPAssociative]>;
29 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
30 [SDNPHasChain, SDNPOutFlag]>;
31 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
32 [SDNPHasChain, SDNPOutFlag]>;
33 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
35 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
37 //===----------------------------------------------------------------------===//
38 // SSE Complex Patterns
39 //===----------------------------------------------------------------------===//
41 // These are 'extloads' from a scalar to the low element of a vector, zeroing
42 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
44 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
46 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
49 def ssmem : Operand<v4f32> {
50 let PrintMethod = "printf32mem";
51 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
53 def sdmem : Operand<v2f64> {
54 let PrintMethod = "printf64mem";
55 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
58 //===----------------------------------------------------------------------===//
59 // SSE pattern fragments
60 //===----------------------------------------------------------------------===//
62 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
63 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
65 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
66 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
67 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
69 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
70 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
71 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
72 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
73 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
74 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
76 def fp32imm0 : PatLeaf<(f32 fpimm), [{
77 return N->isExactlyValue(+0.0);
80 def PSxLDQ_imm : SDNodeXForm<imm, [{
81 // Transformation function: imm >> 3
82 return getI32Imm(N->getValue() >> 3);
85 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
87 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
88 return getI8Imm(X86::getShuffleSHUFImmediate(N));
91 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
93 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
94 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
97 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
99 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
100 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
103 def SSE_splat_mask : PatLeaf<(build_vector), [{
104 return X86::isSplatMask(N);
105 }], SHUFFLE_get_shuf_imm>;
107 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
108 return X86::isSplatLoMask(N);
111 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVHLPSMask(N);
115 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVHLPS_v_undef_Mask(N);
119 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isMOVHPMask(N);
123 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isMOVLPMask(N);
127 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isMOVLMask(N);
131 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isMOVSHDUPMask(N);
135 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isMOVSLDUPMask(N);
139 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isUNPCKLMask(N);
143 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isUNPCKHMask(N);
147 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isUNPCKL_v_undef_Mask(N);
151 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isPSHUFDMask(N);
153 }], SHUFFLE_get_shuf_imm>;
155 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
156 return X86::isPSHUFHWMask(N);
157 }], SHUFFLE_get_pshufhw_imm>;
159 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
160 return X86::isPSHUFLWMask(N);
161 }], SHUFFLE_get_pshuflw_imm>;
163 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
164 return X86::isPSHUFDMask(N);
165 }], SHUFFLE_get_shuf_imm>;
167 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
168 return X86::isSHUFPMask(N);
169 }], SHUFFLE_get_shuf_imm>;
171 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
172 return X86::isSHUFPMask(N);
173 }], SHUFFLE_get_shuf_imm>;
175 //===----------------------------------------------------------------------===//
176 // SSE scalar FP Instructions
177 //===----------------------------------------------------------------------===//
179 // Instruction templates
180 // SSI - SSE1 instructions with XS prefix.
181 // SDI - SSE2 instructions with XD prefix.
182 // PSI - SSE1 instructions with TB prefix.
183 // PDI - SSE2 instructions with TB and OpSize prefixes.
184 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
185 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
186 // S3I - SSE3 instructions with TB and OpSize prefixes.
187 // S3SI - SSE3 instructions with XS prefix.
188 // S3DI - SSE3 instructions with XD prefix.
189 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
190 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
191 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
192 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
193 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
194 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
195 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
196 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
197 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
198 : Ii8<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
199 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
200 : Ii8<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
202 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
203 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
204 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
205 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
206 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
207 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
209 //===----------------------------------------------------------------------===//
210 // Helpers for defining instructions that directly correspond to intrinsics.
212 multiclass SS_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
213 def r : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
214 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
215 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
216 def m : SSI<o, MRMSrcMem, (ops VR128:$dst, ssmem:$src),
217 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
218 [(set VR128:$dst, (v4f32 (IntId sse_load_f32:$src)))]>;
221 multiclass SD_IntUnary<bits<8> o, string OpcodeStr, Intrinsic IntId> {
222 def r : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
223 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
224 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
225 def m : SDI<o, MRMSrcMem, (ops VR128:$dst, sdmem:$src),
226 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src"),
227 [(set VR128:$dst, (v2f64 (IntId sse_load_f64:$src)))]>;
230 class PS_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
231 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
232 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
233 [(set VR128:$dst, (IntId VR128:$src))]>;
234 class PS_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
235 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
236 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
237 [(set VR128:$dst, (IntId (load addr:$src)))]>;
238 class PD_Intr<bits<8> o, string OpcodeStr, Intrinsic IntId>
239 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src),
240 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
241 [(set VR128:$dst, (IntId VR128:$src))]>;
242 class PD_Intm<bits<8> o, string OpcodeStr, Intrinsic IntId>
243 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
244 !strconcat(OpcodeStr, " {$src, $dst|$dst, $src}"),
245 [(set VR128:$dst, (IntId (load addr:$src)))]>;
247 class PS_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
248 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
249 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
250 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
251 class PS_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
252 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2),
253 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
254 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
255 class PD_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
256 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
257 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
258 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
259 class PD_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
260 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
261 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
262 [(set VR128:$dst, (IntId VR128:$src1, (load addr:$src2)))]>;
264 // Some 'special' instructions
265 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
266 "#IMPLICIT_DEF $dst",
267 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
268 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
269 "#IMPLICIT_DEF $dst",
270 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
272 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
273 // scheduler into a branch sequence.
274 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
275 def CMOV_FR32 : I<0, Pseudo,
276 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
277 "#CMOV_FR32 PSEUDO!",
278 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
279 def CMOV_FR64 : I<0, Pseudo,
280 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
281 "#CMOV_FR64 PSEUDO!",
282 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
283 def CMOV_V4F32 : I<0, Pseudo,
284 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
285 "#CMOV_V4F32 PSEUDO!",
287 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
288 def CMOV_V2F64 : I<0, Pseudo,
289 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
290 "#CMOV_V2F64 PSEUDO!",
292 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
293 def CMOV_V2I64 : I<0, Pseudo,
294 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
295 "#CMOV_V2I64 PSEUDO!",
297 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
301 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
302 "movss {$src, $dst|$dst, $src}", []>;
303 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
304 "movss {$src, $dst|$dst, $src}",
305 [(set FR32:$dst, (loadf32 addr:$src))]>;
306 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
307 "movsd {$src, $dst|$dst, $src}", []>;
308 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
309 "movsd {$src, $dst|$dst, $src}",
310 [(set FR64:$dst, (loadf64 addr:$src))]>;
312 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
313 "movss {$src, $dst|$dst, $src}",
314 [(store FR32:$src, addr:$dst)]>;
315 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
316 "movsd {$src, $dst|$dst, $src}",
317 [(store FR64:$src, addr:$dst)]>;
319 /// scalar_sse12_fp_binop_rm - Scalar SSE binops come in four basic forms:
320 /// 1. f32 vs f64 - These come in SSE1/SSE2 forms for float/doubles.
321 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
323 /// In addition, scalar SSE ops have an intrinsic form. This form is unlike the
324 /// normal form, in that they take an entire vector (instead of a scalar) and
325 /// leave the top elements undefined. This adds another two variants of the
326 /// above permutations, giving us 8 forms for 'instruction'.
328 let isTwoAddress = 1 in {
329 multiclass scalar_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
330 SDNode OpNode, Intrinsic F32Int,
331 Intrinsic F64Int, bit Commutable = 0> {
332 // Scalar operation, reg+reg.
333 def SSrr : SSI<opc, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
334 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
335 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
336 let isCommutable = Commutable;
338 def SDrr : SDI<opc, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
339 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
340 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
341 let isCommutable = Commutable;
343 // Scalar operation, reg+mem.
344 def SSrm : SSI<opc, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
345 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
346 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
347 def SDrm : SDI<opc, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
348 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
349 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
351 // Vector intrinsic operation, reg+reg.
352 def SSrr_Int : SSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
353 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
354 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
355 let isCommutable = Commutable;
357 def SDrr_Int : SDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
358 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
359 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
360 let isCommutable = Commutable;
362 // Vector intrinsic operation, reg+mem.
363 def SSrm_Int : SSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, ssmem:$src2),
364 !strconcat(OpcodeStr, "ss {$src2, $dst|$dst, $src2"),
365 [(set VR128:$dst, (F32Int VR128:$src1,
366 sse_load_f32:$src2))]>;
367 def SDrm_Int : SDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, sdmem:$src2),
368 !strconcat(OpcodeStr, "sd {$src2, $dst|$dst, $src2"),
369 [(set VR128:$dst, (F64Int VR128:$src1,
370 sse_load_f64:$src2))]>;
374 // Arithmetic instructions
376 defm ADD : scalar_sse12_fp_binop_rm<0x58, "add", fadd,
377 int_x86_sse_add_ss, int_x86_sse2_add_sd, 1>;
378 defm MUL : scalar_sse12_fp_binop_rm<0x59, "mul", fmul,
379 int_x86_sse_mul_ss, int_x86_sse2_mul_sd, 1>;
380 defm SUB : scalar_sse12_fp_binop_rm<0x5C, "sub", fsub,
381 int_x86_sse_sub_ss, int_x86_sse2_sub_sd>;
382 defm DIV : scalar_sse12_fp_binop_rm<0x5E, "div", fdiv,
383 int_x86_sse_div_ss, int_x86_sse2_div_sd>;
385 defm MAX : scalar_sse12_fp_binop_rm<0x5F, "max", X86fmax,
386 int_x86_sse_max_ss, int_x86_sse2_max_sd>;
387 defm MIN : scalar_sse12_fp_binop_rm<0x5D, "min", X86fmin,
388 int_x86_sse_min_ss, int_x86_sse2_min_sd>;
391 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
392 "sqrtss {$src, $dst|$dst, $src}",
393 [(set FR32:$dst, (fsqrt FR32:$src))]>;
394 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
395 "sqrtss {$src, $dst|$dst, $src}",
396 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
397 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
398 "sqrtsd {$src, $dst|$dst, $src}",
399 [(set FR64:$dst, (fsqrt FR64:$src))]>;
400 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
401 "sqrtsd {$src, $dst|$dst, $src}",
402 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
404 // Aliases to match intrinsics which expect XMM operand(s).
406 defm SQRTSS_Int : SS_IntUnary<0x51, "sqrtss" , int_x86_sse_sqrt_ss>;
407 defm SQRTSD_Int : SD_IntUnary<0x51, "sqrtsd" , int_x86_sse2_sqrt_sd>;
408 defm RSQRTSS_Int : SS_IntUnary<0x52, "rsqrtss", int_x86_sse_rsqrt_ss>;
409 defm RCPSS_Int : SS_IntUnary<0x53, "rcpss" , int_x86_sse_rcp_ss>;
411 // Conversion instructions
412 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, FR32:$src),
413 "cvttss2si {$src, $dst|$dst, $src}",
414 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
415 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
416 "cvttss2si {$src, $dst|$dst, $src}",
417 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
418 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, FR64:$src),
419 "cvttsd2si {$src, $dst|$dst, $src}",
420 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
421 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f64mem:$src),
422 "cvttsd2si {$src, $dst|$dst, $src}",
423 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
424 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
425 "cvtsd2ss {$src, $dst|$dst, $src}",
426 [(set FR32:$dst, (fround FR64:$src))]>;
427 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
428 "cvtsd2ss {$src, $dst|$dst, $src}",
429 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
430 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, GR32:$src),
431 "cvtsi2ss {$src, $dst|$dst, $src}",
432 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
433 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
434 "cvtsi2ss {$src, $dst|$dst, $src}",
435 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
436 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, GR32:$src),
437 "cvtsi2sd {$src, $dst|$dst, $src}",
438 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
439 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
440 "cvtsi2sd {$src, $dst|$dst, $src}",
441 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
443 // SSE2 instructions with XS prefix
444 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
445 "cvtss2sd {$src, $dst|$dst, $src}",
446 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
448 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
449 "cvtss2sd {$src, $dst|$dst, $src}",
450 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
453 // Match intrinsics which expect XMM operand(s).
454 def Int_CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
455 "cvtss2si {$src, $dst|$dst, $src}",
456 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
457 def Int_CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
458 "cvtss2si {$src, $dst|$dst, $src}",
459 [(set GR32:$dst, (int_x86_sse_cvtss2si
460 (load addr:$src)))]>;
461 def Int_CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops GR32:$dst, VR128:$src),
462 "cvtsd2si {$src, $dst|$dst, $src}",
463 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
464 def Int_CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
465 "cvtsd2si {$src, $dst|$dst, $src}",
466 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
467 (load addr:$src)))]>;
469 // Aliases for intrinsics
470 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
471 "cvttss2si {$src, $dst|$dst, $src}",
472 [(set GR32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
473 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops GR32:$dst, f32mem:$src),
474 "cvttss2si {$src, $dst|$dst, $src}",
475 [(set GR32:$dst, (int_x86_sse_cvttss2si(load addr:$src)))]>;
476 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops GR32:$dst, VR128:$src),
477 "cvttsd2si {$src, $dst|$dst, $src}",
478 [(set GR32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
479 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops GR32:$dst, f128mem:$src),
480 "cvttsd2si {$src, $dst|$dst, $src}",
481 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
482 (load addr:$src)))]>;
484 let isTwoAddress = 1 in {
485 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
486 (ops VR128:$dst, VR128:$src1, GR32:$src2),
487 "cvtsi2ss {$src2, $dst|$dst, $src2}",
488 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
490 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
491 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
492 "cvtsi2ss {$src2, $dst|$dst, $src2}",
493 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
494 (loadi32 addr:$src2)))]>;
497 // Comparison instructions
498 let isTwoAddress = 1 in {
499 def CMPSSrr : SSI<0xC2, MRMSrcReg,
500 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
501 "cmp${cc}ss {$src, $dst|$dst, $src}",
503 def CMPSSrm : SSI<0xC2, MRMSrcMem,
504 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
505 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
506 def CMPSDrr : SDI<0xC2, MRMSrcReg,
507 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
508 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
509 def CMPSDrm : SDI<0xC2, MRMSrcMem,
510 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
511 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
514 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
515 "ucomiss {$src2, $src1|$src1, $src2}",
516 [(X86cmp FR32:$src1, FR32:$src2)]>;
517 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
518 "ucomiss {$src2, $src1|$src1, $src2}",
519 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
520 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
521 "ucomisd {$src2, $src1|$src1, $src2}",
522 [(X86cmp FR64:$src1, FR64:$src2)]>;
523 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
524 "ucomisd {$src2, $src1|$src1, $src2}",
525 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
527 // Aliases to match intrinsics which expect XMM operand(s).
528 let isTwoAddress = 1 in {
529 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
530 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
531 "cmp${cc}ss {$src, $dst|$dst, $src}",
532 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
533 VR128:$src, imm:$cc))]>;
534 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
535 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
536 "cmp${cc}ss {$src, $dst|$dst, $src}",
537 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
538 (load addr:$src), imm:$cc))]>;
539 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
540 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
541 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
542 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
543 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
544 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
547 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
548 "ucomiss {$src2, $src1|$src1, $src2}",
549 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
550 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
551 "ucomiss {$src2, $src1|$src1, $src2}",
552 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
553 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
554 "ucomisd {$src2, $src1|$src1, $src2}",
555 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
556 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
557 "ucomisd {$src2, $src1|$src1, $src2}",
558 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
560 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
561 "comiss {$src2, $src1|$src1, $src2}",
562 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
563 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
564 "comiss {$src2, $src1|$src1, $src2}",
565 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
566 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
567 "comisd {$src2, $src1|$src1, $src2}",
568 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
569 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
570 "comisd {$src2, $src1|$src1, $src2}",
571 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
573 // Aliases of packed instructions for scalar use. These all have names that
576 // Alias instructions that map fld0 to pxor for sse.
577 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
578 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
579 Requires<[HasSSE1]>, TB, OpSize;
580 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
581 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
582 Requires<[HasSSE2]>, TB, OpSize;
584 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
585 // Upper bits are disregarded.
586 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
587 "movaps {$src, $dst|$dst, $src}", []>;
588 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
589 "movapd {$src, $dst|$dst, $src}", []>;
591 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
592 // Upper bits are disregarded.
593 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
594 "movaps {$src, $dst|$dst, $src}",
595 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
596 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
597 "movapd {$src, $dst|$dst, $src}",
598 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
600 // Alias bitwise logical operations using SSE logical ops on packed FP values.
601 let isTwoAddress = 1 in {
602 let isCommutable = 1 in {
603 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
604 "andps {$src2, $dst|$dst, $src2}",
605 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
606 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
607 "andpd {$src2, $dst|$dst, $src2}",
608 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
609 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
610 "orps {$src2, $dst|$dst, $src2}", []>;
611 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
612 "orpd {$src2, $dst|$dst, $src2}", []>;
613 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
614 "xorps {$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
616 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
617 "xorpd {$src2, $dst|$dst, $src2}",
618 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
620 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
621 "andps {$src2, $dst|$dst, $src2}",
622 [(set FR32:$dst, (X86fand FR32:$src1,
623 (X86loadpf32 addr:$src2)))]>;
624 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
625 "andpd {$src2, $dst|$dst, $src2}",
626 [(set FR64:$dst, (X86fand FR64:$src1,
627 (X86loadpf64 addr:$src2)))]>;
628 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
629 "orps {$src2, $dst|$dst, $src2}", []>;
630 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
631 "orpd {$src2, $dst|$dst, $src2}", []>;
632 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
633 "xorps {$src2, $dst|$dst, $src2}",
634 [(set FR32:$dst, (X86fxor FR32:$src1,
635 (X86loadpf32 addr:$src2)))]>;
636 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
637 "xorpd {$src2, $dst|$dst, $src2}",
638 [(set FR64:$dst, (X86fxor FR64:$src1,
639 (X86loadpf64 addr:$src2)))]>;
641 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
642 "andnps {$src2, $dst|$dst, $src2}", []>;
643 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
644 "andnps {$src2, $dst|$dst, $src2}", []>;
645 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
646 "andnpd {$src2, $dst|$dst, $src2}", []>;
647 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
648 "andnpd {$src2, $dst|$dst, $src2}", []>;
651 //===----------------------------------------------------------------------===//
652 // SSE packed FP Instructions
653 //===----------------------------------------------------------------------===//
655 // Some 'special' instructions
656 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
657 "#IMPLICIT_DEF $dst",
658 [(set VR128:$dst, (v4f32 (undef)))]>,
662 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
663 "movaps {$src, $dst|$dst, $src}", []>;
664 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
665 "movaps {$src, $dst|$dst, $src}",
666 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
667 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
668 "movapd {$src, $dst|$dst, $src}", []>;
669 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
670 "movapd {$src, $dst|$dst, $src}",
671 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
673 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
674 "movaps {$src, $dst|$dst, $src}",
675 [(store (v4f32 VR128:$src), addr:$dst)]>;
676 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
677 "movapd {$src, $dst|$dst, $src}",
678 [(store (v2f64 VR128:$src), addr:$dst)]>;
680 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
681 "movups {$src, $dst|$dst, $src}", []>;
682 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
683 "movups {$src, $dst|$dst, $src}",
684 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
685 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
686 "movups {$src, $dst|$dst, $src}",
687 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
688 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
689 "movupd {$src, $dst|$dst, $src}", []>;
690 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
691 "movupd {$src, $dst|$dst, $src}",
692 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
693 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
694 "movupd {$src, $dst|$dst, $src}",
695 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
697 let isTwoAddress = 1 in {
698 let AddedComplexity = 20 in {
699 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
700 "movlps {$src2, $dst|$dst, $src2}",
702 (v4f32 (vector_shuffle VR128:$src1,
703 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
704 MOVLP_shuffle_mask)))]>;
705 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
706 "movlpd {$src2, $dst|$dst, $src2}",
708 (v2f64 (vector_shuffle VR128:$src1,
709 (scalar_to_vector (loadf64 addr:$src2)),
710 MOVLP_shuffle_mask)))]>;
711 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
712 "movhps {$src2, $dst|$dst, $src2}",
714 (v4f32 (vector_shuffle VR128:$src1,
715 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
716 MOVHP_shuffle_mask)))]>;
717 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
718 "movhpd {$src2, $dst|$dst, $src2}",
720 (v2f64 (vector_shuffle VR128:$src1,
721 (scalar_to_vector (loadf64 addr:$src2)),
722 MOVHP_shuffle_mask)))]>;
726 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
727 "movlps {$src, $dst|$dst, $src}",
728 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
729 (iPTR 0))), addr:$dst)]>;
730 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
731 "movlpd {$src, $dst|$dst, $src}",
732 [(store (f64 (vector_extract (v2f64 VR128:$src),
733 (iPTR 0))), addr:$dst)]>;
735 // v2f64 extract element 1 is always custom lowered to unpack high to low
736 // and extract element 0 so the non-store version isn't too horrible.
737 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
738 "movhps {$src, $dst|$dst, $src}",
739 [(store (f64 (vector_extract
740 (v2f64 (vector_shuffle
741 (bc_v2f64 (v4f32 VR128:$src)), (undef),
742 UNPCKH_shuffle_mask)), (iPTR 0))),
744 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
745 "movhpd {$src, $dst|$dst, $src}",
746 [(store (f64 (vector_extract
747 (v2f64 (vector_shuffle VR128:$src, (undef),
748 UNPCKH_shuffle_mask)), (iPTR 0))),
751 let isTwoAddress = 1 in {
752 let AddedComplexity = 15 in {
753 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
754 "movlhps {$src2, $dst|$dst, $src2}",
756 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
757 MOVHP_shuffle_mask)))]>;
759 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
760 "movhlps {$src2, $dst|$dst, $src2}",
762 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
763 MOVHLPS_shuffle_mask)))]>;
767 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
768 "movshdup {$src, $dst|$dst, $src}",
769 [(set VR128:$dst, (v4f32 (vector_shuffle
771 MOVSHDUP_shuffle_mask)))]>;
772 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
773 "movshdup {$src, $dst|$dst, $src}",
774 [(set VR128:$dst, (v4f32 (vector_shuffle
775 (loadv4f32 addr:$src), (undef),
776 MOVSHDUP_shuffle_mask)))]>;
778 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
779 "movsldup {$src, $dst|$dst, $src}",
780 [(set VR128:$dst, (v4f32 (vector_shuffle
782 MOVSLDUP_shuffle_mask)))]>;
783 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
784 "movsldup {$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (v4f32 (vector_shuffle
786 (loadv4f32 addr:$src), (undef),
787 MOVSLDUP_shuffle_mask)))]>;
789 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
790 "movddup {$src, $dst|$dst, $src}",
791 [(set VR128:$dst, (v2f64 (vector_shuffle
793 SSE_splat_lo_mask)))]>;
794 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
795 "movddup {$src, $dst|$dst, $src}",
796 [(set VR128:$dst, (v2f64 (vector_shuffle
797 (scalar_to_vector (loadf64 addr:$src)),
799 SSE_splat_lo_mask)))]>;
801 // SSE2 instructions without OpSize prefix
802 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
803 "cvtdq2ps {$src, $dst|$dst, $src}",
804 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
805 TB, Requires<[HasSSE2]>;
806 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
807 "cvtdq2ps {$src, $dst|$dst, $src}",
808 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
809 (bitconvert (loadv2i64 addr:$src))))]>,
810 TB, Requires<[HasSSE2]>;
812 // SSE2 instructions with XS prefix
813 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
814 "cvtdq2pd {$src, $dst|$dst, $src}",
815 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
816 XS, Requires<[HasSSE2]>;
817 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
818 "cvtdq2pd {$src, $dst|$dst, $src}",
819 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
820 (bitconvert (loadv2i64 addr:$src))))]>,
821 XS, Requires<[HasSSE2]>;
823 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
824 "cvtps2dq {$src, $dst|$dst, $src}",
825 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
826 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
827 "cvtps2dq {$src, $dst|$dst, $src}",
828 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
829 (load addr:$src)))]>;
830 // SSE2 packed instructions with XS prefix
831 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
832 "cvttps2dq {$src, $dst|$dst, $src}",
833 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
834 XS, Requires<[HasSSE2]>;
835 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
836 "cvttps2dq {$src, $dst|$dst, $src}",
837 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
838 (load addr:$src)))]>,
839 XS, Requires<[HasSSE2]>;
841 // SSE2 packed instructions with XD prefix
842 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
843 "cvtpd2dq {$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
845 XD, Requires<[HasSSE2]>;
846 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
847 "cvtpd2dq {$src, $dst|$dst, $src}",
848 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
849 (load addr:$src)))]>,
850 XD, Requires<[HasSSE2]>;
851 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
852 "cvttpd2dq {$src, $dst|$dst, $src}",
853 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
854 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
855 "cvttpd2dq {$src, $dst|$dst, $src}",
856 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
857 (load addr:$src)))]>;
859 // SSE2 instructions without OpSize prefix
860 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
861 "cvtps2pd {$src, $dst|$dst, $src}",
862 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
863 TB, Requires<[HasSSE2]>;
864 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
865 "cvtps2pd {$src, $dst|$dst, $src}",
866 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
867 (load addr:$src)))]>,
868 TB, Requires<[HasSSE2]>;
870 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
871 "cvtpd2ps {$src, $dst|$dst, $src}",
872 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
873 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
874 "cvtpd2ps {$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
876 (load addr:$src)))]>;
878 // Match intrinsics which expect XMM operand(s).
879 // Aliases for intrinsics
880 let isTwoAddress = 1 in {
881 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
882 (ops VR128:$dst, VR128:$src1, GR32:$src2),
883 "cvtsi2sd {$src2, $dst|$dst, $src2}",
884 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
886 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
887 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
888 "cvtsi2sd {$src2, $dst|$dst, $src2}",
889 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
890 (loadi32 addr:$src2)))]>;
891 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
892 (ops VR128:$dst, VR128:$src1, VR128:$src2),
893 "cvtsd2ss {$src2, $dst|$dst, $src2}",
894 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
896 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
897 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
898 "cvtsd2ss {$src2, $dst|$dst, $src2}",
899 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
900 (load addr:$src2)))]>;
901 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
902 (ops VR128:$dst, VR128:$src1, VR128:$src2),
903 "cvtss2sd {$src2, $dst|$dst, $src2}",
904 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
907 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
908 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
909 "cvtss2sd {$src2, $dst|$dst, $src2}",
910 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
911 (load addr:$src2)))]>, XS,
915 /// packed_sse12_fp_binop_rm - Packed SSE binops come in four basic forms:
916 /// 1. v4f32 vs v2f64 - These come in SSE1/SSE2 forms for float/doubles.
917 /// 2. rr vs rm - They include a reg+reg form and a ref+mem form.
919 let isTwoAddress = 1 in {
920 multiclass packed_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
921 SDNode OpNode, bit Commutable = 0> {
922 // Packed operation, reg+reg.
923 def PSrr : PSI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
924 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2"),
925 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
926 let isCommutable = Commutable;
928 def PDrr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
929 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2"),
930 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
931 let isCommutable = Commutable;
933 // Packed operation, reg+mem.
934 def PSrm : PSI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
935 !strconcat(OpcodeStr, "ps {$src2, $dst|$dst, $src2"),
936 [(set VR128:$dst, (OpNode VR128:$src1, (loadv4f32 addr:$src2)))]>;
937 def PDrm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
938 !strconcat(OpcodeStr, "pd {$src2, $dst|$dst, $src2"),
939 [(set VR128:$dst, (OpNode VR128:$src1, (loadv2f64 addr:$src2)))]>;
943 defm ADD : packed_sse12_fp_binop_rm<0x58, "add", fadd, 1>;
944 defm MUL : packed_sse12_fp_binop_rm<0x59, "mul", fmul, 1>;
945 defm DIV : packed_sse12_fp_binop_rm<0x5E, "div", fdiv>;
946 defm SUB : packed_sse12_fp_binop_rm<0x5C, "sub", fsub>;
949 let isTwoAddress = 1 in {
950 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
951 (ops VR128:$dst, VR128:$src1, VR128:$src2),
952 "addsubps {$src2, $dst|$dst, $src2}",
953 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
955 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
956 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
957 "addsubps {$src2, $dst|$dst, $src2}",
958 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
959 (load addr:$src2)))]>;
960 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
961 (ops VR128:$dst, VR128:$src1, VR128:$src2),
962 "addsubpd {$src2, $dst|$dst, $src2}",
963 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
965 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
966 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
967 "addsubpd {$src2, $dst|$dst, $src2}",
968 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
969 (load addr:$src2)))]>;
972 def SQRTPSr : PS_Intr<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
973 def SQRTPSm : PS_Intm<0x51, "sqrtps", int_x86_sse_sqrt_ps>;
974 def SQRTPDr : PD_Intr<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
975 def SQRTPDm : PD_Intm<0x51, "sqrtpd", int_x86_sse2_sqrt_pd>;
977 def RSQRTPSr : PS_Intr<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
978 def RSQRTPSm : PS_Intm<0x52, "rsqrtps", int_x86_sse_rsqrt_ps>;
979 def RCPPSr : PS_Intr<0x53, "rcpps", int_x86_sse_rcp_ps>;
980 def RCPPSm : PS_Intm<0x53, "rcpps", int_x86_sse_rcp_ps>;
982 let isTwoAddress = 1 in {
983 let isCommutable = 1 in {
984 def MAXPSrr : PS_Intrr<0x5F, "maxps", int_x86_sse_max_ps>;
985 def MAXPDrr : PD_Intrr<0x5F, "maxpd", int_x86_sse2_max_pd>;
986 def MINPSrr : PS_Intrr<0x5D, "minps", int_x86_sse_min_ps>;
987 def MINPDrr : PD_Intrr<0x5D, "minpd", int_x86_sse2_min_pd>;
989 def MAXPSrm : PS_Intrm<0x5F, "maxps", int_x86_sse_max_ps>;
990 def MAXPDrm : PD_Intrm<0x5F, "maxpd", int_x86_sse2_max_pd>;
991 def MINPSrm : PS_Intrm<0x5D, "minps", int_x86_sse_min_ps>;
992 def MINPDrm : PD_Intrm<0x5D, "minpd", int_x86_sse2_min_pd>;
996 let isTwoAddress = 1 in {
997 let isCommutable = 1 in {
998 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
999 "andps {$src2, $dst|$dst, $src2}",
1000 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1001 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1002 "andpd {$src2, $dst|$dst, $src2}",
1004 (and (bc_v2i64 (v2f64 VR128:$src1)),
1005 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1006 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1007 "orps {$src2, $dst|$dst, $src2}",
1008 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1009 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1010 "orpd {$src2, $dst|$dst, $src2}",
1012 (or (bc_v2i64 (v2f64 VR128:$src1)),
1013 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1014 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1015 "xorps {$src2, $dst|$dst, $src2}",
1016 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1017 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1018 "xorpd {$src2, $dst|$dst, $src2}",
1020 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1021 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1023 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1024 "andps {$src2, $dst|$dst, $src2}",
1025 [(set VR128:$dst, (and VR128:$src1,
1026 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1027 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1028 "andpd {$src2, $dst|$dst, $src2}",
1030 (and (bc_v2i64 (v2f64 VR128:$src1)),
1031 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1032 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1033 "orps {$src2, $dst|$dst, $src2}",
1034 [(set VR128:$dst, (or VR128:$src1,
1035 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1036 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1037 "orpd {$src2, $dst|$dst, $src2}",
1039 (or (bc_v2i64 (v2f64 VR128:$src1)),
1040 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1041 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1042 "xorps {$src2, $dst|$dst, $src2}",
1043 [(set VR128:$dst, (xor VR128:$src1,
1044 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1045 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1046 "xorpd {$src2, $dst|$dst, $src2}",
1048 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1049 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1050 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1051 "andnps {$src2, $dst|$dst, $src2}",
1052 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1053 (bc_v2i64 (v4i32 immAllOnesV))),
1055 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1056 "andnps {$src2, $dst|$dst, $src2}",
1057 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1058 (bc_v2i64 (v4i32 immAllOnesV))),
1059 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1060 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1061 "andnpd {$src2, $dst|$dst, $src2}",
1063 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1064 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1065 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1066 "andnpd {$src2, $dst|$dst, $src2}",
1068 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1069 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1072 let isTwoAddress = 1 in {
1073 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1074 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1075 "cmp${cc}ps {$src, $dst|$dst, $src}",
1076 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1077 VR128:$src, imm:$cc))]>;
1078 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1079 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1080 "cmp${cc}ps {$src, $dst|$dst, $src}",
1081 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1082 (load addr:$src), imm:$cc))]>;
1083 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1084 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1085 "cmp${cc}pd {$src, $dst|$dst, $src}",
1086 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1087 VR128:$src, imm:$cc))]>;
1088 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1089 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1090 "cmp${cc}pd {$src, $dst|$dst, $src}",
1091 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1092 (load addr:$src), imm:$cc))]>;
1095 // Shuffle and unpack instructions
1096 let isTwoAddress = 1 in {
1097 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1098 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1099 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1100 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1101 [(set VR128:$dst, (v4f32 (vector_shuffle
1102 VR128:$src1, VR128:$src2,
1103 SHUFP_shuffle_mask:$src3)))]>;
1104 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1105 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1106 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1107 [(set VR128:$dst, (v4f32 (vector_shuffle
1108 VR128:$src1, (load addr:$src2),
1109 SHUFP_shuffle_mask:$src3)))]>;
1110 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1111 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1112 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1113 [(set VR128:$dst, (v2f64 (vector_shuffle
1114 VR128:$src1, VR128:$src2,
1115 SHUFP_shuffle_mask:$src3)))]>;
1116 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1117 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1118 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1119 [(set VR128:$dst, (v2f64 (vector_shuffle
1120 VR128:$src1, (load addr:$src2),
1121 SHUFP_shuffle_mask:$src3)))]>;
1123 let AddedComplexity = 10 in {
1124 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1125 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1126 "unpckhps {$src2, $dst|$dst, $src2}",
1127 [(set VR128:$dst, (v4f32 (vector_shuffle
1128 VR128:$src1, VR128:$src2,
1129 UNPCKH_shuffle_mask)))]>;
1130 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1131 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1132 "unpckhps {$src2, $dst|$dst, $src2}",
1133 [(set VR128:$dst, (v4f32 (vector_shuffle
1134 VR128:$src1, (load addr:$src2),
1135 UNPCKH_shuffle_mask)))]>;
1136 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1137 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1138 "unpckhpd {$src2, $dst|$dst, $src2}",
1139 [(set VR128:$dst, (v2f64 (vector_shuffle
1140 VR128:$src1, VR128:$src2,
1141 UNPCKH_shuffle_mask)))]>;
1142 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1143 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1144 "unpckhpd {$src2, $dst|$dst, $src2}",
1145 [(set VR128:$dst, (v2f64 (vector_shuffle
1146 VR128:$src1, (load addr:$src2),
1147 UNPCKH_shuffle_mask)))]>;
1149 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1150 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1151 "unpcklps {$src2, $dst|$dst, $src2}",
1152 [(set VR128:$dst, (v4f32 (vector_shuffle
1153 VR128:$src1, VR128:$src2,
1154 UNPCKL_shuffle_mask)))]>;
1155 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1156 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1157 "unpcklps {$src2, $dst|$dst, $src2}",
1158 [(set VR128:$dst, (v4f32 (vector_shuffle
1159 VR128:$src1, (load addr:$src2),
1160 UNPCKL_shuffle_mask)))]>;
1161 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1162 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1163 "unpcklpd {$src2, $dst|$dst, $src2}",
1164 [(set VR128:$dst, (v2f64 (vector_shuffle
1165 VR128:$src1, VR128:$src2,
1166 UNPCKL_shuffle_mask)))]>;
1167 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1168 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1169 "unpcklpd {$src2, $dst|$dst, $src2}",
1170 [(set VR128:$dst, (v2f64 (vector_shuffle
1171 VR128:$src1, (load addr:$src2),
1172 UNPCKL_shuffle_mask)))]>;
1173 } // AddedComplexity
1178 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1179 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1180 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1181 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
1182 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1183 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1184 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1185 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
1186 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
1187 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1188 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1189 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
1190 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
1191 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1192 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2}"),
1193 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
1195 let isTwoAddress = 1 in {
1196 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1197 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
1198 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1199 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
1200 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1201 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
1202 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1203 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
1206 //===----------------------------------------------------------------------===//
1207 // SSE integer instructions
1208 //===----------------------------------------------------------------------===//
1210 // Move Instructions
1211 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1212 "movdqa {$src, $dst|$dst, $src}", []>;
1213 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1214 "movdqa {$src, $dst|$dst, $src}",
1215 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1216 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1217 "movdqa {$src, $dst|$dst, $src}",
1218 [(store (v2i64 VR128:$src), addr:$dst)]>;
1219 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1220 "movdqu {$src, $dst|$dst, $src}",
1221 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1222 XS, Requires<[HasSSE2]>;
1223 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1224 "movdqu {$src, $dst|$dst, $src}",
1225 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1226 XS, Requires<[HasSSE2]>;
1227 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1228 "lddqu {$src, $dst|$dst, $src}",
1229 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1232 let isTwoAddress = 1 in {
1233 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1234 bit Commutable = 0> {
1235 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1236 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1237 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1238 let isCommutable = Commutable;
1240 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1241 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1242 [(set VR128:$dst, (IntId VR128:$src1,
1243 (bitconvert (loadv2i64 addr:$src2))))]>;
1247 let isTwoAddress = 1 in {
1248 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1249 string OpcodeStr, Intrinsic IntId> {
1250 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1251 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1252 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1253 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1254 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1255 [(set VR128:$dst, (IntId VR128:$src1,
1256 (bitconvert (loadv2i64 addr:$src2))))]>;
1257 def ri : PDIi8<opc2, ImmForm, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1258 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1259 [(set VR128:$dst, (IntId VR128:$src1,
1260 (scalar_to_vector (i32 imm:$src2))))]>;
1265 let isTwoAddress = 1 in {
1266 /// PDI_binop_rm - Simple SSE2 binary operator.
1267 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1268 ValueType OpVT, bit Commutable = 0> {
1269 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1270 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1271 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1272 let isCommutable = Commutable;
1274 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1275 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1276 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1277 (bitconvert (loadv2i64 addr:$src2)))))]>;
1280 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1282 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1283 /// to collapse (bitconvert VT to VT) into its operand.
1285 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1286 bit Commutable = 0> {
1287 def rr : PDI<opc, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1288 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1289 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1290 let isCommutable = Commutable;
1292 def rm : PDI<opc, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1293 !strconcat(OpcodeStr, " {$src2, $dst|$dst, $src2"),
1294 [(set VR128:$dst, (OpNode VR128:$src1,(loadv2i64 addr:$src2)))]>;
1299 // 128-bit Integer Arithmetic
1301 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1302 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1303 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1304 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1306 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1307 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1308 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1309 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1311 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1312 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1313 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1314 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1316 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1317 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1318 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1319 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1321 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1323 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1324 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1325 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1327 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1329 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1330 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1333 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1334 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1335 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1336 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1337 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1340 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1341 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1342 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1344 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1345 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1346 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1348 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1349 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1350 // PSRAQ doesn't exist in SSE[1-3].
1353 // 128-bit logical shifts.
1354 let isTwoAddress = 1 in {
1355 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1356 "pslldq {$src2, $dst|$dst, $src2}", []>;
1357 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1358 "psrldq {$src2, $dst|$dst, $src2}", []>;
1359 // PSRADQri doesn't exist in SSE[1-3].
1362 let Predicates = [HasSSE2] in {
1363 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1364 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1365 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1366 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1370 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1371 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1372 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1374 let isTwoAddress = 1 in {
1375 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1376 "pandn {$src2, $dst|$dst, $src2}",
1377 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1380 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1381 "pandn {$src2, $dst|$dst, $src2}",
1382 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1383 (load addr:$src2))))]>;
1386 // SSE2 Integer comparison
1387 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1388 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1389 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1390 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1391 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1392 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1394 // Pack instructions
1395 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1396 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1397 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1399 // Shuffle and unpack instructions
1400 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1401 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1402 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1403 [(set VR128:$dst, (v4i32 (vector_shuffle
1404 VR128:$src1, (undef),
1405 PSHUFD_shuffle_mask:$src2)))]>;
1406 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1407 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1408 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1409 [(set VR128:$dst, (v4i32 (vector_shuffle
1410 (bc_v4i32(loadv2i64 addr:$src1)),
1412 PSHUFD_shuffle_mask:$src2)))]>;
1414 // SSE2 with ImmT == Imm8 and XS prefix.
1415 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1416 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1417 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1418 [(set VR128:$dst, (v8i16 (vector_shuffle
1419 VR128:$src1, (undef),
1420 PSHUFHW_shuffle_mask:$src2)))]>,
1421 XS, Requires<[HasSSE2]>;
1422 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1423 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1424 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1425 [(set VR128:$dst, (v8i16 (vector_shuffle
1426 (bc_v8i16 (loadv2i64 addr:$src1)),
1428 PSHUFHW_shuffle_mask:$src2)))]>,
1429 XS, Requires<[HasSSE2]>;
1431 // SSE2 with ImmT == Imm8 and XD prefix.
1432 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1433 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1434 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1435 [(set VR128:$dst, (v8i16 (vector_shuffle
1436 VR128:$src1, (undef),
1437 PSHUFLW_shuffle_mask:$src2)))]>,
1438 XD, Requires<[HasSSE2]>;
1439 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1440 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1441 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1442 [(set VR128:$dst, (v8i16 (vector_shuffle
1443 (bc_v8i16 (loadv2i64 addr:$src1)),
1445 PSHUFLW_shuffle_mask:$src2)))]>,
1446 XD, Requires<[HasSSE2]>;
1448 let isTwoAddress = 1 in {
1449 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1450 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1451 "punpcklbw {$src2, $dst|$dst, $src2}",
1453 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1454 UNPCKL_shuffle_mask)))]>;
1455 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1456 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1457 "punpcklbw {$src2, $dst|$dst, $src2}",
1459 (v16i8 (vector_shuffle VR128:$src1,
1460 (bc_v16i8 (loadv2i64 addr:$src2)),
1461 UNPCKL_shuffle_mask)))]>;
1462 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1463 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1464 "punpcklwd {$src2, $dst|$dst, $src2}",
1466 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1467 UNPCKL_shuffle_mask)))]>;
1468 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1469 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1470 "punpcklwd {$src2, $dst|$dst, $src2}",
1472 (v8i16 (vector_shuffle VR128:$src1,
1473 (bc_v8i16 (loadv2i64 addr:$src2)),
1474 UNPCKL_shuffle_mask)))]>;
1475 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1476 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1477 "punpckldq {$src2, $dst|$dst, $src2}",
1479 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1480 UNPCKL_shuffle_mask)))]>;
1481 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1482 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1483 "punpckldq {$src2, $dst|$dst, $src2}",
1485 (v4i32 (vector_shuffle VR128:$src1,
1486 (bc_v4i32 (loadv2i64 addr:$src2)),
1487 UNPCKL_shuffle_mask)))]>;
1488 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1489 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1490 "punpcklqdq {$src2, $dst|$dst, $src2}",
1492 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1493 UNPCKL_shuffle_mask)))]>;
1494 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1495 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1496 "punpcklqdq {$src2, $dst|$dst, $src2}",
1498 (v2i64 (vector_shuffle VR128:$src1,
1499 (loadv2i64 addr:$src2),
1500 UNPCKL_shuffle_mask)))]>;
1502 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1503 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1504 "punpckhbw {$src2, $dst|$dst, $src2}",
1506 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1507 UNPCKH_shuffle_mask)))]>;
1508 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1509 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1510 "punpckhbw {$src2, $dst|$dst, $src2}",
1512 (v16i8 (vector_shuffle VR128:$src1,
1513 (bc_v16i8 (loadv2i64 addr:$src2)),
1514 UNPCKH_shuffle_mask)))]>;
1515 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1516 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1517 "punpckhwd {$src2, $dst|$dst, $src2}",
1519 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1520 UNPCKH_shuffle_mask)))]>;
1521 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1522 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1523 "punpckhwd {$src2, $dst|$dst, $src2}",
1525 (v8i16 (vector_shuffle VR128:$src1,
1526 (bc_v8i16 (loadv2i64 addr:$src2)),
1527 UNPCKH_shuffle_mask)))]>;
1528 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1529 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1530 "punpckhdq {$src2, $dst|$dst, $src2}",
1532 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1533 UNPCKH_shuffle_mask)))]>;
1534 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1535 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1536 "punpckhdq {$src2, $dst|$dst, $src2}",
1538 (v4i32 (vector_shuffle VR128:$src1,
1539 (bc_v4i32 (loadv2i64 addr:$src2)),
1540 UNPCKH_shuffle_mask)))]>;
1541 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1542 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1543 "punpckhqdq {$src2, $dst|$dst, $src2}",
1545 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1546 UNPCKH_shuffle_mask)))]>;
1547 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1548 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1549 "punpckhqdq {$src2, $dst|$dst, $src2}",
1551 (v2i64 (vector_shuffle VR128:$src1,
1552 (loadv2i64 addr:$src2),
1553 UNPCKH_shuffle_mask)))]>;
1557 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1558 (ops GR32:$dst, VR128:$src1, i32i8imm:$src2),
1559 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
1560 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1561 (iPTR imm:$src2)))]>;
1562 let isTwoAddress = 1 in {
1563 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1564 (ops VR128:$dst, VR128:$src1, GR32:$src2, i32i8imm:$src3),
1565 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1566 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1567 GR32:$src2, (iPTR imm:$src3))))]>;
1568 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
1569 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
1570 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
1572 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
1573 (i32 (anyext (loadi16 addr:$src2))),
1574 (iPTR imm:$src3))))]>;
1577 //===----------------------------------------------------------------------===//
1578 // Miscellaneous Instructions
1579 //===----------------------------------------------------------------------===//
1582 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1583 "movmskps {$src, $dst|$dst, $src}",
1584 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1585 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1586 "movmskpd {$src, $dst|$dst, $src}",
1587 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1589 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops GR32:$dst, VR128:$src),
1590 "pmovmskb {$src, $dst|$dst, $src}",
1591 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
1593 // Conditional store
1594 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (ops VR128:$src, VR128:$mask),
1595 "maskmovdqu {$mask, $src|$src, $mask}",
1596 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
1599 // Prefetching loads.
1600 // TODO: no intrinsics for these?
1601 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src), "prefetcht0 $src", []>;
1602 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src), "prefetcht1 $src", []>;
1603 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src), "prefetcht2 $src", []>;
1604 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src), "prefetchtnta $src", []>;
1606 // Non-temporal stores
1607 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1608 "movntps {$src, $dst|$dst, $src}",
1609 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1610 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1611 "movntpd {$src, $dst|$dst, $src}",
1612 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1613 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
1614 "movntdq {$src, $dst|$dst, $src}",
1615 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1616 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, GR32:$src),
1617 "movnti {$src, $dst|$dst, $src}",
1618 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1619 TB, Requires<[HasSSE2]>;
1622 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
1623 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
1624 TB, Requires<[HasSSE2]>;
1626 // Load, store, and memory fence
1627 def SFENCE : PSI<0xAE, MRM7m, (ops), "sfence", [(int_x86_sse_sfence)]>;
1628 def LFENCE : I<0xAE, MRM5m, (ops),
1629 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
1630 def MFENCE : I<0xAE, MRM6m, (ops),
1631 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
1634 def LDMXCSR : PSI<0xAE, MRM2m, (ops i32mem:$src),
1635 "ldmxcsr $src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1636 def STMXCSR : PSI<0xAE, MRM3m, (ops i32mem:$dst),
1637 "stmxcsr $dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1639 // Thread synchronization
1640 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
1641 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
1642 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
1643 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
1645 //===----------------------------------------------------------------------===//
1646 // Alias Instructions
1647 //===----------------------------------------------------------------------===//
1649 // Alias instructions that map zero vector to pxor / xorp* for sse.
1650 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1651 def V_SET0 : PSI<0x57, MRMInitReg, (ops VR128:$dst),
1653 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1655 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
1656 "pcmpeqd $dst, $dst",
1657 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
1659 // FR32 / FR64 to 128-bit vector conversion.
1660 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
1661 "movss {$src, $dst|$dst, $src}",
1663 (v4f32 (scalar_to_vector FR32:$src)))]>;
1664 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1665 "movss {$src, $dst|$dst, $src}",
1667 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1668 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
1669 "movsd {$src, $dst|$dst, $src}",
1671 (v2f64 (scalar_to_vector FR64:$src)))]>;
1672 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1673 "movsd {$src, $dst|$dst, $src}",
1675 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
1677 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1678 "movd {$src, $dst|$dst, $src}",
1680 (v4i32 (scalar_to_vector GR32:$src)))]>;
1681 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1682 "movd {$src, $dst|$dst, $src}",
1684 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
1686 // SSE2 instructions with XS prefix
1687 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1688 "movq {$src, $dst|$dst, $src}",
1690 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
1691 Requires<[HasSSE2]>;
1692 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1693 "movq {$src, $dst|$dst, $src}",
1694 [(store (i64 (vector_extract (v2i64 VR128:$src),
1695 (iPTR 0))), addr:$dst)]>;
1697 // FIXME: may not be able to eliminate this movss with coalescing the src and
1698 // dest register classes are different. We really want to write this pattern
1700 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1701 // (f32 FR32:$src)>;
1702 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
1703 "movss {$src, $dst|$dst, $src}",
1704 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1706 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
1707 "movss {$src, $dst|$dst, $src}",
1708 [(store (f32 (vector_extract (v4f32 VR128:$src),
1709 (iPTR 0))), addr:$dst)]>;
1710 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
1711 "movsd {$src, $dst|$dst, $src}",
1712 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
1714 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
1715 "movsd {$src, $dst|$dst, $src}",
1716 [(store (f64 (vector_extract (v2f64 VR128:$src),
1717 (iPTR 0))), addr:$dst)]>;
1718 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops GR32:$dst, VR128:$src),
1719 "movd {$src, $dst|$dst, $src}",
1720 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
1722 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
1723 "movd {$src, $dst|$dst, $src}",
1724 [(store (i32 (vector_extract (v4i32 VR128:$src),
1725 (iPTR 0))), addr:$dst)]>;
1727 // Move to lower bits of a VR128, leaving upper bits alone.
1728 // Three operand (but two address) aliases.
1729 let isTwoAddress = 1 in {
1730 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
1731 "movss {$src2, $dst|$dst, $src2}", []>;
1732 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
1733 "movsd {$src2, $dst|$dst, $src2}", []>;
1735 let AddedComplexity = 15 in {
1736 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1737 "movss {$src2, $dst|$dst, $src2}",
1739 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1740 MOVL_shuffle_mask)))]>;
1741 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1742 "movsd {$src2, $dst|$dst, $src2}",
1744 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
1745 MOVL_shuffle_mask)))]>;
1749 // Store / copy lower 64-bits of a XMM register.
1750 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
1751 "movq {$src, $dst|$dst, $src}",
1752 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
1754 // Move to lower bits of a VR128 and zeroing upper bits.
1755 // Loading from memory automatically zeroing upper bits.
1756 let AddedComplexity = 20 in {
1757 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
1758 "movss {$src, $dst|$dst, $src}",
1759 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
1760 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1761 MOVL_shuffle_mask)))]>;
1762 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
1763 "movsd {$src, $dst|$dst, $src}",
1764 [(set VR128:$dst, (v2f64 (vector_shuffle immAllZerosV,
1765 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
1766 MOVL_shuffle_mask)))]>;
1768 let AddedComplexity = 15 in
1769 // movd / movq to XMM register zero-extends
1770 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, GR32:$src),
1771 "movd {$src, $dst|$dst, $src}",
1772 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1773 (v4i32 (scalar_to_vector GR32:$src)),
1774 MOVL_shuffle_mask)))]>;
1775 let AddedComplexity = 20 in
1776 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
1777 "movd {$src, $dst|$dst, $src}",
1778 [(set VR128:$dst, (v4i32 (vector_shuffle immAllZerosV,
1779 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
1780 MOVL_shuffle_mask)))]>;
1781 // Moving from XMM to XMM but still clear upper 64 bits.
1782 let AddedComplexity = 15 in
1783 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1784 "movq {$src, $dst|$dst, $src}",
1785 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
1786 XS, Requires<[HasSSE2]>;
1787 let AddedComplexity = 20 in
1788 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
1789 "movq {$src, $dst|$dst, $src}",
1790 [(set VR128:$dst, (int_x86_sse2_movl_dq
1791 (bitconvert (loadv2i64 addr:$src))))]>,
1792 XS, Requires<[HasSSE2]>;
1794 //===----------------------------------------------------------------------===//
1795 // Non-Instruction Patterns
1796 //===----------------------------------------------------------------------===//
1798 // 128-bit vector undef's.
1799 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1800 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1801 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1802 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1803 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
1805 // 128-bit vector all zero's.
1806 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1807 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1808 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1809 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1810 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
1812 // 128-bit vector all one's.
1813 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1814 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1815 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1816 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
1817 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
1819 // Store 128-bit integer vector values.
1820 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1821 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1822 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1823 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1824 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1825 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
1827 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
1829 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1830 Requires<[HasSSE2]>;
1831 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
1832 Requires<[HasSSE2]>;
1835 let Predicates = [HasSSE2] in {
1836 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
1837 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
1838 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
1839 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
1840 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
1841 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
1842 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
1843 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
1844 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
1845 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
1846 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
1847 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
1848 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
1849 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
1850 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
1851 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
1852 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
1853 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
1854 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
1855 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
1856 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
1857 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
1858 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
1859 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
1860 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
1861 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
1862 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
1863 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
1864 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
1865 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
1868 // Move scalar to XMM zero-extended
1869 // movd to XMM register zero-extends
1870 let AddedComplexity = 15 in {
1871 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
1872 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1873 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1874 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
1875 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
1876 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
1877 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
1878 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
1879 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
1880 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
1881 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
1882 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
1883 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
1886 // Splat v2f64 / v2i64
1887 let AddedComplexity = 10 in {
1888 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
1889 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1890 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
1891 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1892 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
1893 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1894 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
1895 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1899 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
1900 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
1901 Requires<[HasSSE1]>;
1903 // Special unary SHUFPSrri case.
1904 // FIXME: when we want non two-address code, then we should use PSHUFD?
1905 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
1906 SHUFP_unary_shuffle_mask:$sm),
1907 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1908 Requires<[HasSSE1]>;
1909 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
1910 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
1911 SHUFP_unary_shuffle_mask:$sm),
1912 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
1913 Requires<[HasSSE2]>;
1914 // Special binary v4i32 shuffle cases with SHUFPS.
1915 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
1916 PSHUFD_binary_shuffle_mask:$sm),
1917 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1918 Requires<[HasSSE2]>;
1919 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
1920 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
1921 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
1922 Requires<[HasSSE2]>;
1924 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
1925 let AddedComplexity = 10 in {
1926 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
1927 UNPCKL_v_undef_shuffle_mask)),
1928 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1929 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
1930 UNPCKL_v_undef_shuffle_mask)),
1931 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1932 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
1933 UNPCKL_v_undef_shuffle_mask)),
1934 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
1935 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1936 UNPCKL_v_undef_shuffle_mask)),
1937 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
1940 let AddedComplexity = 15 in
1941 // vector_shuffle v1, <undef> <1, 1, 3, 3>
1942 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1943 MOVSHDUP_shuffle_mask)),
1944 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
1945 let AddedComplexity = 20 in
1946 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
1947 MOVSHDUP_shuffle_mask)),
1948 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
1950 // vector_shuffle v1, <undef> <0, 0, 2, 2>
1951 let AddedComplexity = 15 in
1952 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
1953 MOVSLDUP_shuffle_mask)),
1954 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
1955 let AddedComplexity = 20 in
1956 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
1957 MOVSLDUP_shuffle_mask)),
1958 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
1960 let AddedComplexity = 15 in {
1961 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
1962 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1963 MOVHP_shuffle_mask)),
1964 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1966 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
1967 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1968 MOVHLPS_shuffle_mask)),
1969 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1971 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
1972 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
1973 MOVHLPS_v_undef_shuffle_mask)),
1974 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1975 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
1976 MOVHLPS_v_undef_shuffle_mask)),
1977 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
1980 let AddedComplexity = 20 in {
1981 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
1982 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
1983 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
1984 MOVLP_shuffle_mask)),
1985 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
1986 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
1987 MOVLP_shuffle_mask)),
1988 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
1989 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
1990 MOVHP_shuffle_mask)),
1991 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
1992 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
1993 MOVHP_shuffle_mask)),
1994 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
1996 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
1997 MOVLP_shuffle_mask)),
1998 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
1999 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2000 MOVLP_shuffle_mask)),
2001 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2002 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2003 MOVHP_shuffle_mask)),
2004 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2005 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2006 MOVLP_shuffle_mask)),
2007 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2010 let AddedComplexity = 15 in {
2011 // Setting the lowest element in the vector.
2012 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2013 MOVL_shuffle_mask)),
2014 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2015 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2016 MOVL_shuffle_mask)),
2017 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2019 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2020 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2021 MOVLP_shuffle_mask)),
2022 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2023 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2024 MOVLP_shuffle_mask)),
2025 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2028 // Set lowest element and zero upper elements.
2029 let AddedComplexity = 20 in
2030 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2031 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2032 MOVL_shuffle_mask)),
2033 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2035 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2036 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2037 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2038 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2039 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2040 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2041 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2042 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2043 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2044 Requires<[HasSSE2]>;
2045 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2046 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2047 Requires<[HasSSE2]>;
2048 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2049 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2050 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2051 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2052 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2053 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2054 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2055 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2056 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2057 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2058 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2059 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2060 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2061 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2062 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2063 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2065 // Some special case pandn patterns.
2066 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2068 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2069 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2071 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2072 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2074 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2076 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2077 (load addr:$src2))),
2078 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2079 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2080 (load addr:$src2))),
2081 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2082 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2083 (load addr:$src2))),
2084 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2087 def : Pat<(v4f32 (X86loadu addr:$src)), (MOVUPSrm addr:$src)>,
2088 Requires<[HasSSE1]>;