1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE 1 & 2 Instructions Classes
19 //===----------------------------------------------------------------------===//
21 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
22 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
23 RegisterClass RC, X86MemOperand x86memop,
25 let isCommutable = 1 in {
26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
32 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
34 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
35 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
36 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
39 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
40 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
41 string asm, string SSEVer, string FPSizeStr,
42 Operand memopr, ComplexPattern mem_cpat,
44 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
46 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
47 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
48 [(set RC:$dst, (!cast<Intrinsic>(
49 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
50 RC:$src1, RC:$src2))]>;
51 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
53 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
54 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
55 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
56 SSEVer, "_", OpcodeStr, FPSizeStr))
57 RC:$src1, mem_cpat:$src2))]>;
60 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
61 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
62 RegisterClass RC, ValueType vt,
63 X86MemOperand x86memop, PatFrag mem_frag,
64 Domain d, bit Is2Addr = 1> {
65 let isCommutable = 1 in
66 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
68 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
69 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
70 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
72 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
74 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
75 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
76 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
79 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
80 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
81 string OpcodeStr, X86MemOperand x86memop,
82 list<dag> pat_rr, list<dag> pat_rm,
84 let isCommutable = 1 in
85 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
87 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
88 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
90 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
92 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
93 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
97 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
98 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
99 string asm, string SSEVer, string FPSizeStr,
100 X86MemOperand x86memop, PatFrag mem_frag,
101 Domain d, bit Is2Addr = 1> {
102 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
104 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
105 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
106 [(set RC:$dst, (!cast<Intrinsic>(
107 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
108 RC:$src1, RC:$src2))], d>;
109 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
111 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
112 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
113 [(set RC:$dst, (!cast<Intrinsic>(
114 !strconcat("int_x86_", SSEVer, "_", OpcodeStr, FPSizeStr))
115 RC:$src1, (mem_frag addr:$src2)))], d>;
118 //===----------------------------------------------------------------------===//
119 // SSE 1 & 2 - Move Instructions
120 //===----------------------------------------------------------------------===//
122 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
123 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
124 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
126 // Loading from memory automatically zeroing upper bits.
127 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
128 PatFrag mem_pat, string OpcodeStr> :
129 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
130 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
131 [(set RC:$dst, (mem_pat addr:$src))]>;
133 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
134 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
135 // is used instead. Register-to-register movss/movsd is not modeled as an
136 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
137 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
138 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
139 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
140 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
141 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
143 let canFoldAsLoad = 1, isReMaterializable = 1 in {
144 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
146 let AddedComplexity = 20 in
147 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
150 let Constraints = "$src1 = $dst" in {
151 def MOVSSrr : sse12_move_rr<FR32, v4f32,
152 "movss\t{$src2, $dst|$dst, $src2}">, XS;
153 def MOVSDrr : sse12_move_rr<FR64, v2f64,
154 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
157 let canFoldAsLoad = 1, isReMaterializable = 1 in {
158 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
160 let AddedComplexity = 20 in
161 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
164 let AddedComplexity = 15 in {
165 // Extract the low 32-bit value from one vector and insert it into another.
166 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
167 (MOVSSrr (v4f32 VR128:$src1),
168 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
169 // Extract the low 64-bit value from one vector and insert it into another.
170 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
171 (MOVSDrr (v2f64 VR128:$src1),
172 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
175 // Implicitly promote a 32-bit scalar to a vector.
176 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
177 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
178 // Implicitly promote a 64-bit scalar to a vector.
179 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
180 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
181 // Implicitly promote a 32-bit scalar to a vector.
182 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
183 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
184 // Implicitly promote a 64-bit scalar to a vector.
185 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
186 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
188 let AddedComplexity = 20 in {
189 // MOVSSrm zeros the high parts of the register; represent this
190 // with SUBREG_TO_REG.
191 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
192 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
193 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
194 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
195 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
196 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
197 // MOVSDrm zeros the high parts of the register; represent this
198 // with SUBREG_TO_REG.
199 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
200 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
201 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
202 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
203 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
204 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
205 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
206 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
207 def : Pat<(v2f64 (X86vzload addr:$src)),
208 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
211 // Store scalar value to memory.
212 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
213 "movss\t{$src, $dst|$dst, $src}",
214 [(store FR32:$src, addr:$dst)]>;
215 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
216 "movsd\t{$src, $dst|$dst, $src}",
217 [(store FR64:$src, addr:$dst)]>;
219 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
220 "movss\t{$src, $dst|$dst, $src}",
221 [(store FR32:$src, addr:$dst)]>, XS, VEX;
222 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
223 "movsd\t{$src, $dst|$dst, $src}",
224 [(store FR64:$src, addr:$dst)]>, XD, VEX;
226 // Extract and store.
227 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
230 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
231 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
234 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
236 // Move Aligned/Unaligned floating point values
237 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
238 X86MemOperand x86memop, PatFrag ld_frag,
239 string asm, Domain d,
240 bit IsReMaterializable = 1> {
241 let neverHasSideEffects = 1 in
242 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
243 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
244 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
245 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
246 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
247 [(set RC:$dst, (ld_frag addr:$src))], d>;
250 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
251 "movaps", SSEPackedSingle>, VEX;
252 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
253 "movapd", SSEPackedDouble>, OpSize, VEX;
254 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
255 "movups", SSEPackedSingle>, VEX;
256 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
259 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
260 "movaps", SSEPackedSingle>, VEX;
261 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
262 "movapd", SSEPackedDouble>, OpSize, VEX;
263 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
264 "movups", SSEPackedSingle>, VEX;
265 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
267 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
268 "movaps", SSEPackedSingle>, TB;
269 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
270 "movapd", SSEPackedDouble>, TB, OpSize;
271 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
272 "movups", SSEPackedSingle>, TB;
273 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
276 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
277 "movaps\t{$src, $dst|$dst, $src}",
278 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
279 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
280 "movapd\t{$src, $dst|$dst, $src}",
281 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
282 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
283 "movups\t{$src, $dst|$dst, $src}",
284 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
285 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
286 "movupd\t{$src, $dst|$dst, $src}",
287 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
288 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
289 "movaps\t{$src, $dst|$dst, $src}",
290 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
291 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
292 "movapd\t{$src, $dst|$dst, $src}",
293 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
294 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
295 "movups\t{$src, $dst|$dst, $src}",
296 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
297 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
298 "movupd\t{$src, $dst|$dst, $src}",
299 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
301 def : Pat<(int_x86_avx_loadu_ps_256 addr:$src), (VMOVUPSYrm addr:$src)>;
302 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
303 (VMOVUPSYmr addr:$dst, VR256:$src)>;
305 def : Pat<(int_x86_avx_loadu_pd_256 addr:$src), (VMOVUPDYrm addr:$src)>;
306 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
307 (VMOVUPDYmr addr:$dst, VR256:$src)>;
309 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
310 "movaps\t{$src, $dst|$dst, $src}",
311 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
312 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
313 "movapd\t{$src, $dst|$dst, $src}",
314 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
315 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
316 "movups\t{$src, $dst|$dst, $src}",
317 [(store (v4f32 VR128:$src), addr:$dst)]>;
318 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movupd\t{$src, $dst|$dst, $src}",
320 [(store (v2f64 VR128:$src), addr:$dst)]>;
322 // Intrinsic forms of MOVUPS/D load and store
323 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
324 (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
327 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
328 (ins f128mem:$dst, VR128:$src),
329 "movupd\t{$src, $dst|$dst, $src}",
330 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
332 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
333 "movups\t{$src, $dst|$dst, $src}",
334 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
335 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
336 "movupd\t{$src, $dst|$dst, $src}",
337 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
339 // Move Low/High packed floating point values
340 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
341 PatFrag mov_frag, string base_opc,
343 def PSrm : PI<opc, MRMSrcMem,
344 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
345 !strconcat(base_opc, "s", asm_opr),
348 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
349 SSEPackedSingle>, TB;
351 def PDrm : PI<opc, MRMSrcMem,
352 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
353 !strconcat(base_opc, "d", asm_opr),
354 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
355 (scalar_to_vector (loadf64 addr:$src2)))))],
356 SSEPackedDouble>, TB, OpSize;
359 let AddedComplexity = 20 in {
360 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
361 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
362 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
363 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
365 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
366 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
367 "\t{$src2, $dst|$dst, $src2}">;
368 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
369 "\t{$src2, $dst|$dst, $src2}">;
372 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
373 "movlps\t{$src, $dst|$dst, $src}",
374 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
375 (iPTR 0))), addr:$dst)]>, VEX;
376 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
377 "movlpd\t{$src, $dst|$dst, $src}",
378 [(store (f64 (vector_extract (v2f64 VR128:$src),
379 (iPTR 0))), addr:$dst)]>, VEX;
380 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
381 "movlps\t{$src, $dst|$dst, $src}",
382 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
383 (iPTR 0))), addr:$dst)]>;
384 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
385 "movlpd\t{$src, $dst|$dst, $src}",
386 [(store (f64 (vector_extract (v2f64 VR128:$src),
387 (iPTR 0))), addr:$dst)]>;
389 // v2f64 extract element 1 is always custom lowered to unpack high to low
390 // and extract element 0 so the non-store version isn't too horrible.
391 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
392 "movhps\t{$src, $dst|$dst, $src}",
393 [(store (f64 (vector_extract
394 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
395 (undef)), (iPTR 0))), addr:$dst)]>,
397 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
398 "movhpd\t{$src, $dst|$dst, $src}",
399 [(store (f64 (vector_extract
400 (v2f64 (unpckh VR128:$src, (undef))),
401 (iPTR 0))), addr:$dst)]>,
403 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
404 "movhps\t{$src, $dst|$dst, $src}",
405 [(store (f64 (vector_extract
406 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
407 (undef)), (iPTR 0))), addr:$dst)]>;
408 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
409 "movhpd\t{$src, $dst|$dst, $src}",
410 [(store (f64 (vector_extract
411 (v2f64 (unpckh VR128:$src, (undef))),
412 (iPTR 0))), addr:$dst)]>;
414 let AddedComplexity = 20 in {
415 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
416 (ins VR128:$src1, VR128:$src2),
417 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
421 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
422 (ins VR128:$src1, VR128:$src2),
423 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
425 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
428 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
429 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
430 (ins VR128:$src1, VR128:$src2),
431 "movlhps\t{$src2, $dst|$dst, $src2}",
433 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
434 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
435 (ins VR128:$src1, VR128:$src2),
436 "movhlps\t{$src2, $dst|$dst, $src2}",
438 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
441 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
442 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
443 let AddedComplexity = 20 in {
444 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
445 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
446 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
447 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
450 //===----------------------------------------------------------------------===//
451 // SSE 1 & 2 - Conversion Instructions
452 //===----------------------------------------------------------------------===//
454 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
455 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
457 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
458 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
459 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
460 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
463 multiclass sse12_cvt_s_np<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
464 X86MemOperand x86memop, string asm> {
465 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
467 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
471 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
472 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
473 string asm, Domain d> {
474 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
475 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
476 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
477 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
480 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
481 X86MemOperand x86memop, string asm> {
482 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
483 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
485 (ins DstRC:$src1, x86memop:$src),
486 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>;
489 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
490 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
491 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
492 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
494 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
495 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
496 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
497 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD,
500 // The assembler can recognize rr 64-bit instructions by seeing a rxx
501 // register, but the same isn't true when only using memory operands,
502 // provide other assembly "l" and "q" forms to address this explicitly
503 // where appropriate to do so.
504 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss">, XS,
506 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">, XS,
508 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd">, XD,
510 defm VCVTSI2SDL : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">, XD,
512 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">, XD,
515 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
516 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
517 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
518 "cvttss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
519 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
520 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
521 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
522 "cvttsd2si{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
523 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
524 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
525 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
526 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
527 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
528 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
529 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
530 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}">, XD, REX_W;
532 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
533 // and/or XMM operand(s).
535 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
536 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
538 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
539 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
540 [(set DstRC:$dst, (Int SrcRC:$src))]>;
541 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
542 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
543 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
546 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
547 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
548 PatFrag ld_frag, string asm, bit Is2Addr = 1> {
549 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
551 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
552 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
553 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
554 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
555 (ins DstRC:$src1, x86memop:$src2),
557 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
558 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
559 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
562 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
563 f32mem, load, "cvtss2si">, XS, VEX;
564 defm Int_VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
565 int_x86_sse_cvtss2si64, f32mem, load, "cvtss2si">,
567 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
568 f128mem, load, "cvtsd2si">, XD, VEX;
569 defm Int_VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
570 int_x86_sse2_cvtsd2si64, f128mem, load, "cvtsd2si">,
573 // FIXME: The asm matcher has a hack to ignore instructions with _Int and Int_
574 // Get rid of this hack or rename the intrinsics, there are several
575 // intructions that only match with the intrinsic form, why create duplicates
576 // to let them be recognized by the assembler?
577 defm VCVTSD2SI_alt : sse12_cvt_s_np<0x2D, FR64, GR32, f64mem,
578 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
579 defm VCVTSD2SI64 : sse12_cvt_s_np<0x2D, FR64, GR64, f64mem,
580 "cvtsd2si\t{$src, $dst|$dst, $src}">, XD, VEX, VEX_W;
581 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
582 f32mem, load, "cvtss2si">, XS;
583 defm Int_CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
584 f32mem, load, "cvtss2si{q}">, XS, REX_W;
585 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
586 f128mem, load, "cvtsd2si{l}">, XD;
587 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
588 f128mem, load, "cvtsd2si{q}">, XD, REX_W;
591 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
592 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss", 0>, XS, VEX_4V;
593 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
594 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss", 0>, XS, VEX_4V,
596 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
597 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd", 0>, XD, VEX_4V;
598 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
599 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd", 0>, XD,
602 let Constraints = "$src1 = $dst" in {
603 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
604 int_x86_sse_cvtsi2ss, i32mem, loadi32,
606 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
607 int_x86_sse_cvtsi642ss, i64mem, loadi64,
608 "cvtsi2ss{q}">, XS, REX_W;
609 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
610 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
612 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
613 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
614 "cvtsi2sd">, XD, REX_W;
619 // Aliases for intrinsics
620 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
621 f32mem, load, "cvttss2si">, XS, VEX;
622 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
623 int_x86_sse_cvttss2si64, f32mem, load,
624 "cvttss2si">, XS, VEX, VEX_W;
625 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
626 f128mem, load, "cvttsd2si">, XD, VEX;
627 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
628 int_x86_sse2_cvttsd2si64, f128mem, load,
629 "cvttsd2si">, XD, VEX, VEX_W;
630 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
631 f32mem, load, "cvttss2si">, XS;
632 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
633 int_x86_sse_cvttss2si64, f32mem, load,
634 "cvttss2si{q}">, XS, REX_W;
635 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
636 f128mem, load, "cvttsd2si">, XD;
637 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
638 int_x86_sse2_cvttsd2si64, f128mem, load,
639 "cvttsd2si{q}">, XD, REX_W;
641 let Pattern = []<dag> in {
642 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
643 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
644 defm VCVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load,
645 "cvtss2si\t{$src, $dst|$dst, $src}">, XS, VEX,
647 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load,
648 "cvtdq2ps\t{$src, $dst|$dst, $src}",
649 SSEPackedSingle>, TB, VEX;
650 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, undef, i256mem, load,
651 "cvtdq2ps\t{$src, $dst|$dst, $src}",
652 SSEPackedSingle>, TB, VEX;
654 let Pattern = []<dag> in {
655 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
656 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
657 defm CVTSS2SI64 : sse12_cvt_s<0x2D, FR32, GR64, undef, f32mem, load /*dummy*/,
658 "cvtss2si{q}\t{$src, $dst|$dst, $src}">, XS, REX_W;
659 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, i128mem, load /*dummy*/,
660 "cvtdq2ps\t{$src, $dst|$dst, $src}",
661 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
666 // Convert scalar double to scalar single
667 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
668 (ins FR64:$src1, FR64:$src2),
669 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
671 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
672 (ins FR64:$src1, f64mem:$src2),
673 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
674 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
675 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
678 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
679 "cvtsd2ss\t{$src, $dst|$dst, $src}",
680 [(set FR32:$dst, (fround FR64:$src))]>;
681 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
682 "cvtsd2ss\t{$src, $dst|$dst, $src}",
683 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
684 Requires<[HasSSE2, OptForSize]>;
686 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
687 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss", 0>,
689 let Constraints = "$src1 = $dst" in
690 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
691 int_x86_sse2_cvtsd2ss, f64mem, load, "cvtsd2ss">, XS;
693 // Convert scalar single to scalar double
694 // SSE2 instructions with XS prefix
695 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
696 (ins FR32:$src1, FR32:$src2),
697 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 []>, XS, Requires<[HasAVX]>, VEX_4V;
699 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
700 (ins FR32:$src1, f32mem:$src2),
701 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
702 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
703 def : Pat<(f64 (fextend FR32:$src)), (VCVTSS2SDrr FR32:$src, FR32:$src)>,
706 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
707 "cvtss2sd\t{$src, $dst|$dst, $src}",
708 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
710 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
711 "cvtss2sd\t{$src, $dst|$dst, $src}",
712 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
713 Requires<[HasSSE2, OptForSize]>;
715 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
716 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
719 VR128:$src2))]>, XS, VEX_4V,
721 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
722 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
723 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
724 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
725 (load addr:$src2)))]>, XS, VEX_4V,
727 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
728 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
729 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
730 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
731 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
734 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
735 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
736 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
737 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
738 (load addr:$src2)))]>, XS,
742 def : Pat<(extloadf32 addr:$src),
743 (CVTSS2SDrr (MOVSSrm addr:$src))>,
744 Requires<[HasSSE2, OptForSpeed]>;
746 // Convert doubleword to packed single/double fp
747 // SSE2 instructions without OpSize prefix
748 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
749 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
750 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
751 TB, VEX, Requires<[HasAVX]>;
752 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
753 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
754 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
755 (bitconvert (memopv2i64 addr:$src))))]>,
756 TB, VEX, Requires<[HasAVX]>;
757 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
758 "cvtdq2ps\t{$src, $dst|$dst, $src}",
759 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
760 TB, Requires<[HasSSE2]>;
761 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
762 "cvtdq2ps\t{$src, $dst|$dst, $src}",
763 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
764 (bitconvert (memopv2i64 addr:$src))))]>,
765 TB, Requires<[HasSSE2]>;
767 // FIXME: why the non-intrinsic version is described as SSE3?
768 // SSE2 instructions with XS prefix
769 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
770 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
771 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
772 XS, VEX, Requires<[HasAVX]>;
773 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
774 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
775 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
776 (bitconvert (memopv2i64 addr:$src))))]>,
777 XS, VEX, Requires<[HasAVX]>;
778 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
779 "cvtdq2pd\t{$src, $dst|$dst, $src}",
780 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
781 XS, Requires<[HasSSE2]>;
782 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
783 "cvtdq2pd\t{$src, $dst|$dst, $src}",
784 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
785 (bitconvert (memopv2i64 addr:$src))))]>,
786 XS, Requires<[HasSSE2]>;
789 // Convert packed single/double fp to doubleword
790 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
791 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
792 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
793 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
794 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
795 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
796 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
797 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
798 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
799 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
800 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
801 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
803 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
804 "cvtps2dq\t{$src, $dst|$dst, $src}",
805 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
807 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
809 "cvtps2dq\t{$src, $dst|$dst, $src}",
810 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
811 (memop addr:$src)))]>, VEX;
812 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
813 "cvtps2dq\t{$src, $dst|$dst, $src}",
814 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
815 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
816 "cvtps2dq\t{$src, $dst|$dst, $src}",
817 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
818 (memop addr:$src)))]>;
820 // SSE2 packed instructions with XD prefix
821 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
822 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
823 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
824 XD, VEX, Requires<[HasAVX]>;
825 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
826 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
827 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
828 (memop addr:$src)))]>,
829 XD, VEX, Requires<[HasAVX]>;
830 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
831 "cvtpd2dq\t{$src, $dst|$dst, $src}",
832 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
833 XD, Requires<[HasSSE2]>;
834 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
835 "cvtpd2dq\t{$src, $dst|$dst, $src}",
836 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
837 (memop addr:$src)))]>,
838 XD, Requires<[HasSSE2]>;
841 // Convert with truncation packed single/double fp to doubleword
842 // SSE2 packed instructions with XS prefix
843 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
844 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
845 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
846 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
847 def VCVTTPS2DQYrr : VSSI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
848 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
849 def VCVTTPS2DQYrm : VSSI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
850 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
851 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
852 "cvttps2dq\t{$src, $dst|$dst, $src}",
854 (int_x86_sse2_cvttps2dq VR128:$src))]>;
855 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
856 "cvttps2dq\t{$src, $dst|$dst, $src}",
858 (int_x86_sse2_cvttps2dq (memop addr:$src)))]>;
861 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
862 "vcvttps2dq\t{$src, $dst|$dst, $src}",
864 (int_x86_sse2_cvttps2dq VR128:$src))]>,
865 XS, VEX, Requires<[HasAVX]>;
866 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
867 "vcvttps2dq\t{$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
869 (memop addr:$src)))]>,
870 XS, VEX, Requires<[HasAVX]>;
872 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
874 "cvttpd2dq\t{$src, $dst|$dst, $src}",
875 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
877 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
879 "cvttpd2dq\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
881 (memop addr:$src)))]>, VEX;
882 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
883 "cvttpd2dq\t{$src, $dst|$dst, $src}",
884 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
885 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
886 "cvttpd2dq\t{$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
888 (memop addr:$src)))]>;
890 // The assembler can recognize rr 256-bit instructions by seeing a ymm
891 // register, but the same isn't true when using memory operands instead.
892 // Provide other assembly rr and rm forms to address this explicitly.
893 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
894 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
895 def VCVTTPD2DQXrYr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
896 "cvttpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
899 def VCVTTPD2DQXrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
900 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
901 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
902 "cvttpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
905 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
906 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
907 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
908 "cvttpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
910 // Convert packed single to packed double
911 let Predicates = [HasAVX] in {
912 // SSE2 instructions without OpSize prefix
913 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
914 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
915 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
916 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
917 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
918 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
919 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
920 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX;
922 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
923 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
924 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
925 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
927 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 "vcvtps2pd\t{$src, $dst|$dst, $src}",
929 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
930 VEX, Requires<[HasAVX]>;
931 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
932 "vcvtps2pd\t{$src, $dst|$dst, $src}",
933 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
934 (load addr:$src)))]>,
935 VEX, Requires<[HasAVX]>;
936 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
937 "cvtps2pd\t{$src, $dst|$dst, $src}",
938 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
939 TB, Requires<[HasSSE2]>;
940 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
941 "cvtps2pd\t{$src, $dst|$dst, $src}",
942 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
943 (load addr:$src)))]>,
944 TB, Requires<[HasSSE2]>;
946 // Convert packed double to packed single
947 // The assembler can recognize rr 256-bit instructions by seeing a ymm
948 // register, but the same isn't true when using memory operands instead.
949 // Provide other assembly rr and rm forms to address this explicitly.
950 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
951 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
952 def VCVTPD2PSXrYr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
953 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
956 def VCVTPD2PSXrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
957 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
958 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
959 "cvtpd2psx\t{$src, $dst|$dst, $src}", []>, VEX;
962 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
963 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX;
964 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
965 "cvtpd2psy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
966 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
967 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
968 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
969 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
972 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
973 "cvtpd2ps\t{$src, $dst|$dst, $src}",
974 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
975 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
977 "cvtpd2ps\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
979 (memop addr:$src)))]>;
980 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
981 "cvtpd2ps\t{$src, $dst|$dst, $src}",
982 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
983 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
984 "cvtpd2ps\t{$src, $dst|$dst, $src}",
985 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
986 (memop addr:$src)))]>;
988 // AVX 256-bit register conversion intrinsics
989 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
990 // whenever possible to avoid declaring two versions of each one.
991 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
992 (VCVTDQ2PSYrr VR256:$src)>;
993 def : Pat<(int_x86_avx_cvtdq2_ps_256 (memopv8i32 addr:$src)),
994 (VCVTDQ2PSYrm addr:$src)>;
996 def : Pat<(int_x86_avx_cvt_pd2_ps_256 VR256:$src),
997 (VCVTPD2PSYrr VR256:$src)>;
998 def : Pat<(int_x86_avx_cvt_pd2_ps_256 (memopv4f64 addr:$src)),
999 (VCVTPD2PSYrm addr:$src)>;
1001 def : Pat<(int_x86_avx_cvt_ps2dq_256 VR256:$src),
1002 (VCVTPS2DQYrr VR256:$src)>;
1003 def : Pat<(int_x86_avx_cvt_ps2dq_256 (memopv8f32 addr:$src)),
1004 (VCVTPS2DQYrm addr:$src)>;
1006 def : Pat<(int_x86_avx_cvt_ps2_pd_256 VR128:$src),
1007 (VCVTPS2PDYrr VR128:$src)>;
1008 def : Pat<(int_x86_avx_cvt_ps2_pd_256 (memopv4f32 addr:$src)),
1009 (VCVTPS2PDYrm addr:$src)>;
1011 def : Pat<(int_x86_avx_cvtt_pd2dq_256 VR256:$src),
1012 (VCVTTPD2DQYrr VR256:$src)>;
1013 def : Pat<(int_x86_avx_cvtt_pd2dq_256 (memopv4f64 addr:$src)),
1014 (VCVTTPD2DQYrm addr:$src)>;
1016 def : Pat<(int_x86_avx_cvtt_ps2dq_256 VR256:$src),
1017 (VCVTTPS2DQYrr VR256:$src)>;
1018 def : Pat<(int_x86_avx_cvtt_ps2dq_256 (memopv8f32 addr:$src)),
1019 (VCVTTPS2DQYrm addr:$src)>;
1021 //===----------------------------------------------------------------------===//
1022 // SSE 1 & 2 - Compare Instructions
1023 //===----------------------------------------------------------------------===//
1025 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
1026 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
1027 string asm, string asm_alt> {
1028 let isAsmParserOnly = 1 in {
1029 def rr : SIi8<0xC2, MRMSrcReg,
1030 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
1033 def rm : SIi8<0xC2, MRMSrcMem,
1034 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
1038 // Accept explicit immediate argument form instead of comparison code.
1039 def rr_alt : SIi8<0xC2, MRMSrcReg,
1040 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1043 def rm_alt : SIi8<0xC2, MRMSrcMem,
1044 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1048 let neverHasSideEffects = 1 in {
1049 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1050 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1051 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1053 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1054 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1055 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1059 let Constraints = "$src1 = $dst" in {
1060 def CMPSSrr : SIi8<0xC2, MRMSrcReg,
1061 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc),
1062 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1063 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS;
1064 def CMPSSrm : SIi8<0xC2, MRMSrcMem,
1065 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc),
1066 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
1067 [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS;
1068 def CMPSDrr : SIi8<0xC2, MRMSrcReg,
1069 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc),
1070 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1071 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD;
1072 def CMPSDrm : SIi8<0xC2, MRMSrcMem,
1073 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc),
1074 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
1075 [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD;
1077 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1078 def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg,
1079 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
1080 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1081 def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem,
1082 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
1083 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS;
1084 def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg,
1085 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1086 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1087 def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem,
1088 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1089 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD;
1092 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1093 Intrinsic Int, string asm> {
1094 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1095 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1096 [(set VR128:$dst, (Int VR128:$src1,
1097 VR128:$src, imm:$cc))]>;
1098 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1099 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1100 [(set VR128:$dst, (Int VR128:$src1,
1101 (load addr:$src), imm:$cc))]>;
1104 // Aliases to match intrinsics which expect XMM operand(s).
1105 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1106 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1108 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1109 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1111 let Constraints = "$src1 = $dst" in {
1112 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1113 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1114 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1115 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1119 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1120 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1121 ValueType vt, X86MemOperand x86memop,
1122 PatFrag ld_frag, string OpcodeStr, Domain d> {
1123 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1124 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1125 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1126 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1127 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1128 [(set EFLAGS, (OpNode (vt RC:$src1),
1129 (ld_frag addr:$src2)))], d>;
1132 let Defs = [EFLAGS] in {
1133 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1134 "ucomiss", SSEPackedSingle>, VEX;
1135 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1136 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1137 let Pattern = []<dag> in {
1138 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1139 "comiss", SSEPackedSingle>, VEX;
1140 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1141 "comisd", SSEPackedDouble>, OpSize, VEX;
1144 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1145 load, "ucomiss", SSEPackedSingle>, VEX;
1146 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1147 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1149 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1150 load, "comiss", SSEPackedSingle>, VEX;
1151 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1152 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1153 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1154 "ucomiss", SSEPackedSingle>, TB;
1155 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1156 "ucomisd", SSEPackedDouble>, TB, OpSize;
1158 let Pattern = []<dag> in {
1159 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1160 "comiss", SSEPackedSingle>, TB;
1161 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1162 "comisd", SSEPackedDouble>, TB, OpSize;
1165 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1166 load, "ucomiss", SSEPackedSingle>, TB;
1167 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1168 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1170 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1171 "comiss", SSEPackedSingle>, TB;
1172 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1173 "comisd", SSEPackedDouble>, TB, OpSize;
1174 } // Defs = [EFLAGS]
1176 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1177 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1178 Intrinsic Int, string asm, string asm_alt,
1180 let isAsmParserOnly = 1 in {
1181 def rri : PIi8<0xC2, MRMSrcReg,
1182 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1183 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1184 def rmi : PIi8<0xC2, MRMSrcMem,
1185 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1186 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1189 // Accept explicit immediate argument form instead of comparison code.
1190 def rri_alt : PIi8<0xC2, MRMSrcReg,
1191 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1193 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1194 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1198 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1199 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1200 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1201 SSEPackedSingle>, VEX_4V;
1202 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1203 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1204 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1205 SSEPackedDouble>, OpSize, VEX_4V;
1206 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_ps_256,
1207 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1208 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1209 SSEPackedSingle>, VEX_4V;
1210 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, int_x86_avx_cmp_pd_256,
1211 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1212 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1213 SSEPackedDouble>, OpSize, VEX_4V;
1214 let Constraints = "$src1 = $dst" in {
1215 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1216 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1217 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1218 SSEPackedSingle>, TB;
1219 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1220 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1221 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1222 SSEPackedDouble>, TB, OpSize;
1225 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1226 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1227 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1228 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1229 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1230 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1231 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1232 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1234 //===----------------------------------------------------------------------===//
1235 // SSE 1 & 2 - Shuffle Instructions
1236 //===----------------------------------------------------------------------===//
1238 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1239 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1240 ValueType vt, string asm, PatFrag mem_frag,
1241 Domain d, bit IsConvertibleToThreeAddress = 0> {
1242 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
1243 (ins RC:$src1, f128mem:$src2, i8imm:$src3), asm,
1244 [(set RC:$dst, (vt (shufp:$src3
1245 RC:$src1, (mem_frag addr:$src2))))], d>;
1246 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1247 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
1248 (ins RC:$src1, RC:$src2, i8imm:$src3), asm,
1250 (vt (shufp:$src3 RC:$src1, RC:$src2)))], d>;
1253 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1254 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1255 memopv4f32, SSEPackedSingle>, TB, VEX_4V;
1256 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
1257 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1258 memopv8f32, SSEPackedSingle>, TB, VEX_4V;
1259 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1260 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1261 memopv2f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1262 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
1263 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1264 memopv4f64, SSEPackedDouble>, TB, OpSize, VEX_4V;
1266 let Constraints = "$src1 = $dst" in {
1267 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1268 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1269 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1271 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1272 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1273 memopv2f64, SSEPackedDouble>, TB, OpSize;
1276 //===----------------------------------------------------------------------===//
1277 // SSE 1 & 2 - Unpack Instructions
1278 //===----------------------------------------------------------------------===//
1280 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1281 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1282 PatFrag mem_frag, RegisterClass RC,
1283 X86MemOperand x86memop, string asm,
1285 def rr : PI<opc, MRMSrcReg,
1286 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1288 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1289 def rm : PI<opc, MRMSrcMem,
1290 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1292 (vt (OpNode RC:$src1,
1293 (mem_frag addr:$src2))))], d>;
1296 let AddedComplexity = 10 in {
1297 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1298 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1299 SSEPackedSingle>, VEX_4V;
1300 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1301 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1302 SSEPackedDouble>, OpSize, VEX_4V;
1303 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1304 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1305 SSEPackedSingle>, VEX_4V;
1306 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1307 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1308 SSEPackedDouble>, OpSize, VEX_4V;
1310 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1311 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1312 SSEPackedSingle>, VEX_4V;
1313 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1314 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1315 SSEPackedDouble>, OpSize, VEX_4V;
1316 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1317 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1318 SSEPackedSingle>, VEX_4V;
1319 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1320 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1321 SSEPackedDouble>, OpSize, VEX_4V;
1323 let Constraints = "$src1 = $dst" in {
1324 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1325 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1326 SSEPackedSingle>, TB;
1327 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1328 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1329 SSEPackedDouble>, TB, OpSize;
1330 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1331 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1332 SSEPackedSingle>, TB;
1333 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1334 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1335 SSEPackedDouble>, TB, OpSize;
1336 } // Constraints = "$src1 = $dst"
1337 } // AddedComplexity
1339 //===----------------------------------------------------------------------===//
1340 // SSE 1 & 2 - Extract Floating-Point Sign mask
1341 //===----------------------------------------------------------------------===//
1343 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1344 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1346 def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1347 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1348 [(set GR32:$dst, (Int RC:$src))], d>;
1349 def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),
1350 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>, REX_W;
1354 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1355 "movmskps", SSEPackedSingle>, VEX;
1356 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1357 "movmskpd", SSEPackedDouble>, OpSize,
1359 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
1360 "movmskps", SSEPackedSingle>, VEX;
1361 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
1362 "movmskpd", SSEPackedDouble>, OpSize,
1364 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1365 SSEPackedSingle>, TB;
1366 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1367 SSEPackedDouble>, TB, OpSize;
1370 def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1371 "movmskpd\t{$src, $dst|$dst, $src}",
1372 [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1373 def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
1374 "movmskpd\t{$src, $dst|$dst, $src}",
1375 [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize;
1376 def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
1377 "movmskps\t{$src, $dst|$dst, $src}",
1378 [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1379 def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1380 "movmskps\t{$src, $dst|$dst, $src}",
1381 [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB;
1384 def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1385 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1386 def VMOVMSKPDr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1387 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1389 def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1390 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1391 def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),
1392 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1395 //===----------------------------------------------------------------------===//
1396 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1397 //===----------------------------------------------------------------------===//
1399 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1400 // names that start with 'Fs'.
1402 // Alias instructions that map fld0 to pxor for sse.
1403 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1404 canFoldAsLoad = 1 in {
1405 // FIXME: Set encoding to pseudo!
1406 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1407 [(set FR32:$dst, fp32imm0)]>,
1408 Requires<[HasSSE1]>, TB, OpSize;
1409 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1410 [(set FR64:$dst, fpimm0)]>,
1411 Requires<[HasSSE2]>, TB, OpSize;
1412 def VFsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1413 [(set FR32:$dst, fp32imm0)]>,
1414 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1415 def VFsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1416 [(set FR64:$dst, fpimm0)]>,
1417 Requires<[HasAVX]>, TB, OpSize, VEX_4V;
1420 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1421 // bits are disregarded.
1422 let neverHasSideEffects = 1 in {
1423 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1424 "movaps\t{$src, $dst|$dst, $src}", []>;
1425 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1426 "movapd\t{$src, $dst|$dst, $src}", []>;
1429 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1430 // bits are disregarded.
1431 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1432 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1433 "movaps\t{$src, $dst|$dst, $src}",
1434 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1435 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1436 "movapd\t{$src, $dst|$dst, $src}",
1437 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1440 //===----------------------------------------------------------------------===//
1441 // SSE 1 & 2 - Logical Instructions
1442 //===----------------------------------------------------------------------===//
1444 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1446 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1448 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1449 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1451 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1452 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1454 let Constraints = "$src1 = $dst" in {
1455 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1456 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1458 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1459 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1463 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1464 let mayLoad = 0 in {
1465 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1466 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1467 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1470 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1471 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1473 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1475 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1476 SDNode OpNode, int HasPat = 0,
1477 list<list<dag>> Pattern = []> {
1478 let Pattern = []<dag> in {
1479 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1480 !strconcat(OpcodeStr, "ps"), f128mem,
1481 !if(HasPat, Pattern[0], // rr
1482 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1484 !if(HasPat, Pattern[2], // rm
1485 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1486 (memopv2i64 addr:$src2)))]), 0>,
1489 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1490 !strconcat(OpcodeStr, "pd"), f128mem,
1491 !if(HasPat, Pattern[1], // rr
1492 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1495 !if(HasPat, Pattern[3], // rm
1496 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1497 (memopv2i64 addr:$src2)))]), 0>,
1500 let Constraints = "$src1 = $dst" in {
1501 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1502 !strconcat(OpcodeStr, "ps"), f128mem,
1503 !if(HasPat, Pattern[0], // rr
1504 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1506 !if(HasPat, Pattern[2], // rm
1507 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1508 (memopv2i64 addr:$src2)))])>, TB;
1510 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1511 !strconcat(OpcodeStr, "pd"), f128mem,
1512 !if(HasPat, Pattern[1], // rr
1513 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1516 !if(HasPat, Pattern[3], // rm
1517 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1518 (memopv2i64 addr:$src2)))])>,
1523 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1525 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1526 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1527 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1529 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1530 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1533 // AVX 256-bit packed logical ops forms
1534 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1535 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1536 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1537 let isCommutable = 0 in
1538 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1540 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1541 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1542 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1543 let isCommutable = 0 in
1544 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1546 [(set VR128:$dst, (X86pandn VR128:$src1, VR128:$src2))],
1550 [(set VR128:$dst, (X86pandn VR128:$src1, (memopv2i64 addr:$src2)))],
1554 //===----------------------------------------------------------------------===//
1555 // SSE 1 & 2 - Arithmetic Instructions
1556 //===----------------------------------------------------------------------===//
1558 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1561 /// In addition, we also have a special variant of the scalar form here to
1562 /// represent the associated intrinsic operation. This form is unlike the
1563 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1564 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1566 /// These three forms can each be reg+reg or reg+mem.
1569 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
1571 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1573 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1574 OpNode, FR32, f32mem, Is2Addr>, XS;
1575 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1576 OpNode, FR64, f64mem, Is2Addr>, XD;
1579 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1581 let mayLoad = 0 in {
1582 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1583 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1584 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1585 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1589 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1591 let mayLoad = 0 in {
1592 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1593 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1594 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1595 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1599 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1601 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1602 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1603 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1604 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1607 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1609 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1610 !strconcat(OpcodeStr, "ps"), "sse", "_ps", f128mem, memopv4f32,
1611 SSEPackedSingle, Is2Addr>, TB;
1613 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1614 !strconcat(OpcodeStr, "pd"), "sse2", "_pd", f128mem, memopv2f64,
1615 SSEPackedDouble, Is2Addr>, TB, OpSize;
1618 multiclass basic_sse12_fp_binop_p_y_int<bits<8> opc, string OpcodeStr> {
1619 defm PSY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1620 !strconcat(OpcodeStr, "ps"), "avx", "_ps_256", f256mem, memopv8f32,
1621 SSEPackedSingle, 0>, TB;
1623 defm PDY : sse12_fp_packed_int<opc, OpcodeStr, VR256,
1624 !strconcat(OpcodeStr, "pd"), "avx", "_pd_256", f256mem, memopv4f64,
1625 SSEPackedDouble, 0>, TB, OpSize;
1628 // Binary Arithmetic instructions
1629 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1630 basic_sse12_fp_binop_s_int<0x58, "add", 0>,
1631 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1632 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1633 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1634 basic_sse12_fp_binop_s_int<0x59, "mul", 0>,
1635 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1636 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1638 let isCommutable = 0 in {
1639 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1640 basic_sse12_fp_binop_s_int<0x5C, "sub", 0>,
1641 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1642 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1643 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1644 basic_sse12_fp_binop_s_int<0x5E, "div", 0>,
1645 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1646 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1647 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1648 basic_sse12_fp_binop_s_int<0x5F, "max", 0>,
1649 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1650 basic_sse12_fp_binop_p_int<0x5F, "max", 0>,
1651 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>,
1652 basic_sse12_fp_binop_p_y_int<0x5F, "max">, VEX_4V;
1653 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1654 basic_sse12_fp_binop_s_int<0x5D, "min", 0>,
1655 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1656 basic_sse12_fp_binop_p_int<0x5D, "min", 0>,
1657 basic_sse12_fp_binop_p_y_int<0x5D, "min">,
1658 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1661 let Constraints = "$src1 = $dst" in {
1662 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1663 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1664 basic_sse12_fp_binop_s_int<0x58, "add">;
1665 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1666 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1667 basic_sse12_fp_binop_s_int<0x59, "mul">;
1669 let isCommutable = 0 in {
1670 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1671 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1672 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1673 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1674 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1675 basic_sse12_fp_binop_s_int<0x5E, "div">;
1676 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1677 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1678 basic_sse12_fp_binop_s_int<0x5F, "max">,
1679 basic_sse12_fp_binop_p_int<0x5F, "max">;
1680 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1681 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1682 basic_sse12_fp_binop_s_int<0x5D, "min">,
1683 basic_sse12_fp_binop_p_int<0x5D, "min">;
1688 /// In addition, we also have a special variant of the scalar form here to
1689 /// represent the associated intrinsic operation. This form is unlike the
1690 /// plain scalar form, in that it takes an entire vector (instead of a
1691 /// scalar) and leaves the top elements undefined.
1693 /// And, we have a special variant form for a full-vector intrinsic form.
1695 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1696 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1697 SDNode OpNode, Intrinsic F32Int> {
1698 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1699 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1700 [(set FR32:$dst, (OpNode FR32:$src))]>;
1701 // For scalar unary operations, fold a load into the operation
1702 // only in OptForSize mode. It eliminates an instruction, but it also
1703 // eliminates a whole-register clobber (the load), so it introduces a
1704 // partial register update condition.
1705 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1706 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1707 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1708 Requires<[HasSSE1, OptForSize]>;
1709 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1710 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1711 [(set VR128:$dst, (F32Int VR128:$src))]>;
1712 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1713 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1714 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1717 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1718 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1719 SDNode OpNode, Intrinsic F32Int> {
1720 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1721 !strconcat(OpcodeStr,
1722 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1723 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1724 !strconcat(OpcodeStr,
1725 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1726 []>, XS, Requires<[HasAVX, OptForSize]>;
1727 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1728 !strconcat(OpcodeStr,
1729 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1730 [(set VR128:$dst, (F32Int VR128:$src))]>;
1731 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1732 !strconcat(OpcodeStr,
1733 "ss\t{$src, $dst, $dst|$dst, $dst, $src}"),
1734 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1737 /// sse1_fp_unop_p - SSE1 unops in packed form.
1738 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1739 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1740 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1741 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1742 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1743 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1744 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1747 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1748 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1749 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1750 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1751 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1752 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1753 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1754 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1757 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1758 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1759 Intrinsic V4F32Int> {
1760 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1761 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1762 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1763 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1764 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1765 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1768 /// sse1_fp_unop_p_y_int - AVX 256-bit intrinsics unops in packed forms.
1769 multiclass sse1_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1770 Intrinsic V4F32Int> {
1771 def PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1772 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1773 [(set VR256:$dst, (V4F32Int VR256:$src))]>;
1774 def PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1775 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1776 [(set VR256:$dst, (V4F32Int (memopv8f32 addr:$src)))]>;
1779 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1780 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1781 SDNode OpNode, Intrinsic F64Int> {
1782 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1783 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1784 [(set FR64:$dst, (OpNode FR64:$src))]>;
1785 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1786 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1787 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1788 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1789 Requires<[HasSSE2, OptForSize]>;
1790 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1791 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1792 [(set VR128:$dst, (F64Int VR128:$src))]>;
1793 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1794 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1795 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1798 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1799 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1800 SDNode OpNode, Intrinsic F64Int> {
1801 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1802 !strconcat(OpcodeStr,
1803 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1804 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1805 (ins FR64:$src1, f64mem:$src2),
1806 !strconcat(OpcodeStr,
1807 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1808 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1809 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1810 [(set VR128:$dst, (F64Int VR128:$src))]>;
1811 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1812 !strconcat(OpcodeStr, "sd\t{$src, $dst, $dst|$dst, $dst, $src}"),
1813 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1816 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1817 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1819 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1820 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1821 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1822 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1823 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1824 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1827 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1828 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1829 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1830 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1831 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1832 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1833 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1834 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1837 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1838 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1839 Intrinsic V2F64Int> {
1840 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1841 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1842 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1843 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1844 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1845 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1848 /// sse2_fp_unop_p_y_int - AVX 256-bit intrinsic unops in vector forms.
1849 multiclass sse2_fp_unop_p_y_int<bits<8> opc, string OpcodeStr,
1850 Intrinsic V2F64Int> {
1851 def PDYr_Int : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1852 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1853 [(set VR256:$dst, (V2F64Int VR256:$src))]>;
1854 def PDYm_Int : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1855 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1856 [(set VR256:$dst, (V2F64Int (memopv4f64 addr:$src)))]>;
1859 let Predicates = [HasAVX] in {
1861 defm VSQRT : sse1_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse_sqrt_ss>,
1862 sse2_fp_unop_s_avx<0x51, "vsqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1865 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1866 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1867 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1868 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1869 sse1_fp_unop_p_int<0x51, "vsqrt", int_x86_sse_sqrt_ps>,
1870 sse2_fp_unop_p_int<0x51, "vsqrt", int_x86_sse2_sqrt_pd>,
1871 sse1_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_ps_256>,
1872 sse2_fp_unop_p_y_int<0x51, "vsqrt", int_x86_avx_sqrt_pd_256>,
1875 // Reciprocal approximations. Note that these typically require refinement
1876 // in order to obtain suitable precision.
1877 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "vrsqrt", X86frsqrt,
1878 int_x86_sse_rsqrt_ss>, VEX_4V;
1879 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1880 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>,
1881 sse1_fp_unop_p_y_int<0x52, "vrsqrt", int_x86_avx_rsqrt_ps_256>,
1882 sse1_fp_unop_p_int<0x52, "vrsqrt", int_x86_sse_rsqrt_ps>, VEX;
1884 defm VRCP : sse1_fp_unop_s_avx<0x53, "vrcp", X86frcp, int_x86_sse_rcp_ss>,
1886 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1887 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>,
1888 sse1_fp_unop_p_y_int<0x53, "vrcp", int_x86_avx_rcp_ps_256>,
1889 sse1_fp_unop_p_int<0x53, "vrcp", int_x86_sse_rcp_ps>, VEX;
1893 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1894 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1895 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1896 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1897 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1898 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1900 // Reciprocal approximations. Note that these typically require refinement
1901 // in order to obtain suitable precision.
1902 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1903 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1904 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1905 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1906 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1907 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1909 // There is no f64 version of the reciprocal approximation instructions.
1911 //===----------------------------------------------------------------------===//
1912 // SSE 1 & 2 - Non-temporal stores
1913 //===----------------------------------------------------------------------===//
1915 let AddedComplexity = 400 in { // Prefer non-temporal versions
1916 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1917 (ins f128mem:$dst, VR128:$src),
1918 "movntps\t{$src, $dst|$dst, $src}",
1919 [(alignednontemporalstore (v4f32 VR128:$src),
1921 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1922 (ins f128mem:$dst, VR128:$src),
1923 "movntpd\t{$src, $dst|$dst, $src}",
1924 [(alignednontemporalstore (v2f64 VR128:$src),
1926 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1927 (ins f128mem:$dst, VR128:$src),
1928 "movntdq\t{$src, $dst|$dst, $src}",
1929 [(alignednontemporalstore (v2f64 VR128:$src),
1932 let ExeDomain = SSEPackedInt in
1933 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1934 (ins f128mem:$dst, VR128:$src),
1935 "movntdq\t{$src, $dst|$dst, $src}",
1936 [(alignednontemporalstore (v4f32 VR128:$src),
1939 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1940 (VMOVNTDQmr addr:$dst, VR128:$src)>, Requires<[HasAVX]>;
1942 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1943 (ins f256mem:$dst, VR256:$src),
1944 "movntps\t{$src, $dst|$dst, $src}",
1945 [(alignednontemporalstore (v8f32 VR256:$src),
1947 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1948 (ins f256mem:$dst, VR256:$src),
1949 "movntpd\t{$src, $dst|$dst, $src}",
1950 [(alignednontemporalstore (v4f64 VR256:$src),
1952 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1953 (ins f256mem:$dst, VR256:$src),
1954 "movntdq\t{$src, $dst|$dst, $src}",
1955 [(alignednontemporalstore (v4f64 VR256:$src),
1957 let ExeDomain = SSEPackedInt in
1958 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1959 (ins f256mem:$dst, VR256:$src),
1960 "movntdq\t{$src, $dst|$dst, $src}",
1961 [(alignednontemporalstore (v8f32 VR256:$src),
1965 def : Pat<(int_x86_avx_movnt_dq_256 addr:$dst, VR256:$src),
1966 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
1967 def : Pat<(int_x86_avx_movnt_pd_256 addr:$dst, VR256:$src),
1968 (VMOVNTPDYmr addr:$dst, VR256:$src)>;
1969 def : Pat<(int_x86_avx_movnt_ps_256 addr:$dst, VR256:$src),
1970 (VMOVNTPSYmr addr:$dst, VR256:$src)>;
1972 let AddedComplexity = 400 in { // Prefer non-temporal versions
1973 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1974 "movntps\t{$src, $dst|$dst, $src}",
1975 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1976 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1977 "movntpd\t{$src, $dst|$dst, $src}",
1978 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
1980 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1981 "movntdq\t{$src, $dst|$dst, $src}",
1982 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1984 let ExeDomain = SSEPackedInt in
1985 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1986 "movntdq\t{$src, $dst|$dst, $src}",
1987 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1989 def : Pat<(alignednontemporalstore (v2i64 VR128:$src), addr:$dst),
1990 (MOVNTDQmr addr:$dst, VR128:$src)>;
1992 // There is no AVX form for instructions below this point
1993 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1994 "movnti\t{$src, $dst|$dst, $src}",
1995 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1996 TB, Requires<[HasSSE2]>;
1997 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1998 "movnti\t{$src, $dst|$dst, $src}",
1999 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
2000 TB, Requires<[HasSSE2]>;
2003 //===----------------------------------------------------------------------===//
2004 // SSE 1 & 2 - Misc Instructions (No AVX form)
2005 //===----------------------------------------------------------------------===//
2007 // Prefetch intrinsic.
2008 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
2009 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
2010 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
2011 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
2012 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
2013 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
2014 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
2015 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
2017 // Load, store, and memory fence
2018 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
2019 TB, Requires<[HasSSE1]>;
2020 def : Pat<(X86SFence), (SFENCE)>;
2022 // Alias instructions that map zero vector to pxor / xorp* for sse.
2023 // We set canFoldAsLoad because this can be converted to a constant-pool
2024 // load of an all-zeros value if folding it would be beneficial.
2025 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2026 // JIT implementation, it does not expand the instructions below like
2027 // X86MCInstLower does.
2028 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2029 isCodeGenOnly = 1 in {
2030 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2031 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2032 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2033 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2034 let ExeDomain = SSEPackedInt in
2035 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2036 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2039 // The same as done above but for AVX. The 128-bit versions are the
2040 // same, but re-encoded. The 256-bit does not support PI version.
2041 // FIXME: Change encoding to pseudo! This is blocked right now by the x86
2042 // JIT implementatioan, it does not expand the instructions below like
2043 // X86MCInstLower does.
2044 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2045 isCodeGenOnly = 1, Predicates = [HasAVX] in {
2046 def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2047 [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V;
2048 def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
2049 [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V;
2050 def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2051 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
2052 def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "",
2053 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
2054 let ExeDomain = SSEPackedInt in
2055 def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
2056 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
2059 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
2060 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
2061 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
2063 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2064 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
2066 //===----------------------------------------------------------------------===//
2067 // SSE 1 & 2 - Load/Store XCSR register
2068 //===----------------------------------------------------------------------===//
2070 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2071 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
2072 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2073 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
2075 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
2076 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
2077 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
2078 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
2080 //===---------------------------------------------------------------------===//
2081 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
2082 //===---------------------------------------------------------------------===//
2084 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2086 let neverHasSideEffects = 1 in {
2087 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2088 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2089 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2090 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2092 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2093 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2094 def VMOVDQUYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2095 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
2097 let canFoldAsLoad = 1, mayLoad = 1 in {
2098 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2099 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2100 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2101 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2102 let Predicates = [HasAVX] in {
2103 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2104 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2105 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
2106 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2110 let mayStore = 1 in {
2111 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
2112 (ins i128mem:$dst, VR128:$src),
2113 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2114 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
2115 (ins i256mem:$dst, VR256:$src),
2116 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
2117 let Predicates = [HasAVX] in {
2118 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2119 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2120 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
2121 "vmovdqu\t{$src, $dst|$dst, $src}",[]>, XS, VEX;
2125 let neverHasSideEffects = 1 in
2126 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2127 "movdqa\t{$src, $dst|$dst, $src}", []>;
2129 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2130 "movdqu\t{$src, $dst|$dst, $src}",
2131 []>, XS, Requires<[HasSSE2]>;
2133 let canFoldAsLoad = 1, mayLoad = 1 in {
2134 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2135 "movdqa\t{$src, $dst|$dst, $src}",
2136 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
2137 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2138 "movdqu\t{$src, $dst|$dst, $src}",
2139 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
2140 XS, Requires<[HasSSE2]>;
2143 let mayStore = 1 in {
2144 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2145 "movdqa\t{$src, $dst|$dst, $src}",
2146 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
2147 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2148 "movdqu\t{$src, $dst|$dst, $src}",
2149 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
2150 XS, Requires<[HasSSE2]>;
2153 // Intrinsic forms of MOVDQU load and store
2154 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2155 "vmovdqu\t{$src, $dst|$dst, $src}",
2156 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2157 XS, VEX, Requires<[HasAVX]>;
2159 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2160 "movdqu\t{$src, $dst|$dst, $src}",
2161 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2162 XS, Requires<[HasSSE2]>;
2164 } // ExeDomain = SSEPackedInt
2166 def : Pat<(int_x86_avx_loadu_dq_256 addr:$src), (VMOVDQUYrm addr:$src)>;
2167 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
2168 (VMOVDQUYmr addr:$dst, VR256:$src)>;
2170 //===---------------------------------------------------------------------===//
2171 // SSE2 - Packed Integer Arithmetic Instructions
2172 //===---------------------------------------------------------------------===//
2174 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2176 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2177 bit IsCommutable = 0, bit Is2Addr = 1> {
2178 let isCommutable = IsCommutable in
2179 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2180 (ins VR128:$src1, VR128:$src2),
2182 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2183 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2184 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2185 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2186 (ins VR128:$src1, i128mem:$src2),
2188 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2189 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2190 [(set VR128:$dst, (IntId VR128:$src1,
2191 (bitconvert (memopv2i64 addr:$src2))))]>;
2194 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2195 string OpcodeStr, Intrinsic IntId,
2196 Intrinsic IntId2, bit Is2Addr = 1> {
2197 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2198 (ins VR128:$src1, VR128:$src2),
2200 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2201 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2202 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2203 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2204 (ins VR128:$src1, i128mem:$src2),
2206 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2207 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2208 [(set VR128:$dst, (IntId VR128:$src1,
2209 (bitconvert (memopv2i64 addr:$src2))))]>;
2210 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2211 (ins VR128:$src1, i32i8imm:$src2),
2213 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2214 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2215 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2218 /// PDI_binop_rm - Simple SSE2 binary operator.
2219 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2220 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2221 let isCommutable = IsCommutable in
2222 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2223 (ins VR128:$src1, VR128:$src2),
2225 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2226 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2227 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2228 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2229 (ins VR128:$src1, i128mem:$src2),
2231 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2232 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2233 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2234 (bitconvert (memopv2i64 addr:$src2)))))]>;
2237 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2239 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2240 /// to collapse (bitconvert VT to VT) into its operand.
2242 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2243 bit IsCommutable = 0, bit Is2Addr = 1> {
2244 let isCommutable = IsCommutable in
2245 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2246 (ins VR128:$src1, VR128:$src2),
2248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2250 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2251 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2252 (ins VR128:$src1, i128mem:$src2),
2254 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2255 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2256 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2259 } // ExeDomain = SSEPackedInt
2261 // 128-bit Integer Arithmetic
2263 let Predicates = [HasAVX] in {
2264 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2265 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2266 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2267 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2268 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2269 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2270 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2271 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2272 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2275 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2277 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2279 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2281 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2283 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2285 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2287 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2289 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2291 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2293 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2295 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2297 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2299 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2301 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2303 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2305 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2307 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2309 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2311 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2315 let Constraints = "$src1 = $dst" in {
2316 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2317 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2318 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2319 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2320 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2321 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2322 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2323 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2324 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2327 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2328 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2329 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2330 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2331 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2332 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2333 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2334 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2335 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2336 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2337 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2338 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2339 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2340 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2341 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2342 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2343 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2344 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2345 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2347 } // Constraints = "$src1 = $dst"
2349 //===---------------------------------------------------------------------===//
2350 // SSE2 - Packed Integer Logical Instructions
2351 //===---------------------------------------------------------------------===//
2353 let Predicates = [HasAVX] in {
2354 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2355 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2357 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2358 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2360 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2361 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2364 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2365 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2367 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2368 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2370 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2371 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2374 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2375 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2377 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2378 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2381 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2382 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2383 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2385 let ExeDomain = SSEPackedInt in {
2386 let neverHasSideEffects = 1 in {
2387 // 128-bit logical shifts.
2388 def VPSLLDQri : PDIi8<0x73, MRM7r,
2389 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2390 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2392 def VPSRLDQri : PDIi8<0x73, MRM3r,
2393 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2394 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2396 // PSRADQri doesn't exist in SSE[1-3].
2398 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2399 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2400 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2401 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2402 VR128:$src2)))]>, VEX_4V;
2404 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2405 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2406 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2407 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2408 (memopv2i64 addr:$src2))))]>,
2413 let Constraints = "$src1 = $dst" in {
2414 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2415 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2416 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2417 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2418 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2419 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2421 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2422 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2423 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2424 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2425 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2426 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2428 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2429 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2430 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2431 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2433 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2434 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2435 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2437 let ExeDomain = SSEPackedInt in {
2438 let neverHasSideEffects = 1 in {
2439 // 128-bit logical shifts.
2440 def PSLLDQri : PDIi8<0x73, MRM7r,
2441 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2442 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2443 def PSRLDQri : PDIi8<0x73, MRM3r,
2444 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2445 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2446 // PSRADQri doesn't exist in SSE[1-3].
2448 def PANDNrr : PDI<0xDF, MRMSrcReg,
2449 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2450 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2452 def PANDNrm : PDI<0xDF, MRMSrcMem,
2453 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2454 "pandn\t{$src2, $dst|$dst, $src2}", []>;
2456 } // Constraints = "$src1 = $dst"
2458 let Predicates = [HasAVX] in {
2459 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2460 (v2i64 (VPSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2461 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2462 (v2i64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2463 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2464 (v2i64 (VPSLLDQri VR128:$src1, imm:$src2))>;
2465 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2466 (v2i64 (VPSRLDQri VR128:$src1, imm:$src2))>;
2467 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2468 (v2f64 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2470 // Shift up / down and insert zero's.
2471 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2472 (v2i64 (VPSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2473 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2474 (v2i64 (VPSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2477 let Predicates = [HasSSE2] in {
2478 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2479 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2480 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2481 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2482 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2483 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2484 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2485 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2486 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2487 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2489 // Shift up / down and insert zero's.
2490 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2491 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2492 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2493 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2496 //===---------------------------------------------------------------------===//
2497 // SSE2 - Packed Integer Comparison Instructions
2498 //===---------------------------------------------------------------------===//
2500 let Predicates = [HasAVX] in {
2501 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2503 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2505 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2507 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2509 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2511 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2515 let Constraints = "$src1 = $dst" in {
2516 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2517 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2518 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2519 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2520 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2521 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2522 } // Constraints = "$src1 = $dst"
2524 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2525 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2526 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2527 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2528 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2529 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2530 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2531 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2532 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2533 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2534 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2535 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2537 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2538 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2539 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2540 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2541 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2542 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2543 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2544 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2545 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2546 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2547 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2548 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2550 //===---------------------------------------------------------------------===//
2551 // SSE2 - Packed Integer Pack Instructions
2552 //===---------------------------------------------------------------------===//
2554 let Predicates = [HasAVX] in {
2555 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2557 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2559 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2563 let Constraints = "$src1 = $dst" in {
2564 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2565 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2566 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2567 } // Constraints = "$src1 = $dst"
2569 //===---------------------------------------------------------------------===//
2570 // SSE2 - Packed Integer Shuffle Instructions
2571 //===---------------------------------------------------------------------===//
2573 let ExeDomain = SSEPackedInt in {
2574 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2576 def ri : Ii8<0x70, MRMSrcReg,
2577 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2578 !strconcat(OpcodeStr,
2579 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2580 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2582 def mi : Ii8<0x70, MRMSrcMem,
2583 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2584 !strconcat(OpcodeStr,
2585 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2586 [(set VR128:$dst, (vt (pshuf_frag:$src2
2587 (bc_frag (memopv2i64 addr:$src1)),
2590 } // ExeDomain = SSEPackedInt
2592 let Predicates = [HasAVX] in {
2593 let AddedComplexity = 5 in
2594 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2597 // SSE2 with ImmT == Imm8 and XS prefix.
2598 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2601 // SSE2 with ImmT == Imm8 and XD prefix.
2602 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2606 let Predicates = [HasSSE2] in {
2607 let AddedComplexity = 5 in
2608 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2610 // SSE2 with ImmT == Imm8 and XS prefix.
2611 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2613 // SSE2 with ImmT == Imm8 and XD prefix.
2614 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2617 //===---------------------------------------------------------------------===//
2618 // SSE2 - Packed Integer Unpack Instructions
2619 //===---------------------------------------------------------------------===//
2621 let ExeDomain = SSEPackedInt in {
2622 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2623 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2624 def rr : PDI<opc, MRMSrcReg,
2625 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2627 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2628 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2629 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2630 def rm : PDI<opc, MRMSrcMem,
2631 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2633 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2634 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2635 [(set VR128:$dst, (unp_frag VR128:$src1,
2636 (bc_frag (memopv2i64
2640 let Predicates = [HasAVX] in {
2641 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2643 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2645 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2648 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2649 /// knew to collapse (bitconvert VT to VT) into its operand.
2650 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2651 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2652 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2654 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2655 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2656 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2657 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2659 (v2i64 (unpckl VR128:$src1,
2660 (memopv2i64 addr:$src2))))]>, VEX_4V;
2662 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2664 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2666 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2669 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2670 /// knew to collapse (bitconvert VT to VT) into its operand.
2671 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2672 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2673 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2675 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2676 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2677 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2678 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2680 (v2i64 (unpckh VR128:$src1,
2681 (memopv2i64 addr:$src2))))]>, VEX_4V;
2684 let Constraints = "$src1 = $dst" in {
2685 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2686 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2687 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2689 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2690 /// knew to collapse (bitconvert VT to VT) into its operand.
2691 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2692 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2693 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2695 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2696 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2697 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2698 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2700 (v2i64 (unpckl VR128:$src1,
2701 (memopv2i64 addr:$src2))))]>;
2703 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2704 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2705 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2707 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2708 /// knew to collapse (bitconvert VT to VT) into its operand.
2709 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2710 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2711 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2713 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2714 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2715 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2716 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2718 (v2i64 (unpckh VR128:$src1,
2719 (memopv2i64 addr:$src2))))]>;
2722 } // ExeDomain = SSEPackedInt
2724 //===---------------------------------------------------------------------===//
2725 // SSE2 - Packed Integer Extract and Insert
2726 //===---------------------------------------------------------------------===//
2728 let ExeDomain = SSEPackedInt in {
2729 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2730 def rri : Ii8<0xC4, MRMSrcReg,
2731 (outs VR128:$dst), (ins VR128:$src1,
2732 GR32:$src2, i32i8imm:$src3),
2734 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2735 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2737 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2738 def rmi : Ii8<0xC4, MRMSrcMem,
2739 (outs VR128:$dst), (ins VR128:$src1,
2740 i16mem:$src2, i32i8imm:$src3),
2742 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2743 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2745 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2750 let Predicates = [HasAVX] in
2751 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2752 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2753 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2754 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2755 imm:$src2))]>, OpSize, VEX;
2756 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2757 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2758 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2759 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2763 let Predicates = [HasAVX] in {
2764 defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2765 def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),
2766 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
2767 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2768 []>, OpSize, VEX_4V;
2771 let Constraints = "$src1 = $dst" in
2772 defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>;
2774 } // ExeDomain = SSEPackedInt
2776 //===---------------------------------------------------------------------===//
2777 // SSE2 - Packed Mask Creation
2778 //===---------------------------------------------------------------------===//
2780 let ExeDomain = SSEPackedInt in {
2782 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2783 "pmovmskb\t{$src, $dst|$dst, $src}",
2784 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2785 def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
2786 "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX;
2787 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2788 "pmovmskb\t{$src, $dst|$dst, $src}",
2789 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2791 } // ExeDomain = SSEPackedInt
2793 //===---------------------------------------------------------------------===//
2794 // SSE2 - Conditional Store
2795 //===---------------------------------------------------------------------===//
2797 let ExeDomain = SSEPackedInt in {
2800 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2801 (ins VR128:$src, VR128:$mask),
2802 "maskmovdqu\t{$mask, $src|$src, $mask}",
2803 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2805 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2806 (ins VR128:$src, VR128:$mask),
2807 "maskmovdqu\t{$mask, $src|$src, $mask}",
2808 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2811 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2812 "maskmovdqu\t{$mask, $src|$src, $mask}",
2813 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2815 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2816 "maskmovdqu\t{$mask, $src|$src, $mask}",
2817 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2819 } // ExeDomain = SSEPackedInt
2821 //===---------------------------------------------------------------------===//
2822 // SSE2 - Move Doubleword
2823 //===---------------------------------------------------------------------===//
2825 // Move Int Doubleword to Packed Double Int
2826 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2827 "movd\t{$src, $dst|$dst, $src}",
2829 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2830 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2831 "movd\t{$src, $dst|$dst, $src}",
2833 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2835 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2836 "movd\t{$src, $dst|$dst, $src}",
2838 (v4i32 (scalar_to_vector GR32:$src)))]>;
2839 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2840 "movd\t{$src, $dst|$dst, $src}",
2842 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2843 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2844 "mov{d|q}\t{$src, $dst|$dst, $src}",
2846 (v2i64 (scalar_to_vector GR64:$src)))]>;
2847 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
2848 "mov{d|q}\t{$src, $dst|$dst, $src}",
2849 [(set FR64:$dst, (bitconvert GR64:$src))]>;
2852 // Move Int Doubleword to Single Scalar
2853 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2854 "movd\t{$src, $dst|$dst, $src}",
2855 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2857 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2858 "movd\t{$src, $dst|$dst, $src}",
2859 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2861 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2862 "movd\t{$src, $dst|$dst, $src}",
2863 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2865 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2866 "movd\t{$src, $dst|$dst, $src}",
2867 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2869 // Move Packed Doubleword Int to Packed Double Int
2870 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2871 "movd\t{$src, $dst|$dst, $src}",
2872 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2874 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2875 (ins i32mem:$dst, VR128:$src),
2876 "movd\t{$src, $dst|$dst, $src}",
2877 [(store (i32 (vector_extract (v4i32 VR128:$src),
2878 (iPTR 0))), addr:$dst)]>, VEX;
2879 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2880 "movd\t{$src, $dst|$dst, $src}",
2881 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2883 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2884 "movd\t{$src, $dst|$dst, $src}",
2885 [(store (i32 (vector_extract (v4i32 VR128:$src),
2886 (iPTR 0))), addr:$dst)]>;
2888 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2889 "mov{d|q}\t{$src, $dst|$dst, $src}",
2890 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
2892 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
2893 "movq\t{$src, $dst|$dst, $src}",
2894 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
2896 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2897 "mov{d|q}\t{$src, $dst|$dst, $src}",
2898 [(set GR64:$dst, (bitconvert FR64:$src))]>;
2899 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
2900 "movq\t{$src, $dst|$dst, $src}",
2901 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;
2903 // Move Scalar Single to Double Int
2904 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2905 "movd\t{$src, $dst|$dst, $src}",
2906 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2907 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2908 "movd\t{$src, $dst|$dst, $src}",
2909 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2910 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2911 "movd\t{$src, $dst|$dst, $src}",
2912 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2913 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2914 "movd\t{$src, $dst|$dst, $src}",
2915 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2917 // movd / movq to XMM register zero-extends
2918 let AddedComplexity = 15 in {
2919 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2920 "movd\t{$src, $dst|$dst, $src}",
2921 [(set VR128:$dst, (v4i32 (X86vzmovl
2922 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2924 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2925 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2926 [(set VR128:$dst, (v2i64 (X86vzmovl
2927 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2930 let AddedComplexity = 15 in {
2931 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2932 "movd\t{$src, $dst|$dst, $src}",
2933 [(set VR128:$dst, (v4i32 (X86vzmovl
2934 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2935 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2936 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2937 [(set VR128:$dst, (v2i64 (X86vzmovl
2938 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2941 let AddedComplexity = 20 in {
2942 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2943 "movd\t{$src, $dst|$dst, $src}",
2945 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2946 (loadi32 addr:$src))))))]>,
2948 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2949 "movd\t{$src, $dst|$dst, $src}",
2951 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2952 (loadi32 addr:$src))))))]>;
2954 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2955 (MOVZDI2PDIrm addr:$src)>;
2956 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2957 (MOVZDI2PDIrm addr:$src)>;
2958 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2959 (MOVZDI2PDIrm addr:$src)>;
2962 //===---------------------------------------------------------------------===//
2963 // SSE2 - Move Quadword
2964 //===---------------------------------------------------------------------===//
2966 // Move Quadword Int to Packed Quadword Int
2967 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2968 "vmovq\t{$src, $dst|$dst, $src}",
2970 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2971 VEX, Requires<[HasAVX]>;
2972 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2973 "movq\t{$src, $dst|$dst, $src}",
2975 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2976 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
2978 // Move Packed Quadword Int to Quadword Int
2979 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2980 "movq\t{$src, $dst|$dst, $src}",
2981 [(store (i64 (vector_extract (v2i64 VR128:$src),
2982 (iPTR 0))), addr:$dst)]>, VEX;
2983 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2984 "movq\t{$src, $dst|$dst, $src}",
2985 [(store (i64 (vector_extract (v2i64 VR128:$src),
2986 (iPTR 0))), addr:$dst)]>;
2988 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2989 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2991 // Store / copy lower 64-bits of a XMM register.
2992 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2993 "movq\t{$src, $dst|$dst, $src}",
2994 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
2995 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2996 "movq\t{$src, $dst|$dst, $src}",
2997 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2999 let AddedComplexity = 20 in
3000 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3001 "vmovq\t{$src, $dst|$dst, $src}",
3003 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3004 (loadi64 addr:$src))))))]>,
3005 XS, VEX, Requires<[HasAVX]>;
3007 let AddedComplexity = 20 in {
3008 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3009 "movq\t{$src, $dst|$dst, $src}",
3011 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
3012 (loadi64 addr:$src))))))]>,
3013 XS, Requires<[HasSSE2]>;
3015 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
3016 (MOVZQI2PQIrm addr:$src)>;
3017 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
3018 (MOVZQI2PQIrm addr:$src)>;
3019 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
3022 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
3023 // IA32 document. movq xmm1, xmm2 does clear the high bits.
3024 let AddedComplexity = 15 in
3025 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3026 "vmovq\t{$src, $dst|$dst, $src}",
3027 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3028 XS, VEX, Requires<[HasAVX]>;
3029 let AddedComplexity = 15 in
3030 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3031 "movq\t{$src, $dst|$dst, $src}",
3032 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
3033 XS, Requires<[HasSSE2]>;
3035 let AddedComplexity = 20 in
3036 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3037 "vmovq\t{$src, $dst|$dst, $src}",
3038 [(set VR128:$dst, (v2i64 (X86vzmovl
3039 (loadv2i64 addr:$src))))]>,
3040 XS, VEX, Requires<[HasAVX]>;
3041 let AddedComplexity = 20 in {
3042 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3043 "movq\t{$src, $dst|$dst, $src}",
3044 [(set VR128:$dst, (v2i64 (X86vzmovl
3045 (loadv2i64 addr:$src))))]>,
3046 XS, Requires<[HasSSE2]>;
3048 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
3049 (MOVZPQILo2PQIrm addr:$src)>;
3052 // Instructions to match in the assembler
3053 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
3054 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3055 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3056 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3057 // Recognize "movd" with GR64 destination, but encode as a "movq"
3058 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3059 "movd\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
3061 // Instructions for the disassembler
3062 // xr = XMM register
3065 let Predicates = [HasAVX] in
3066 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3067 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
3068 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3069 "movq\t{$src, $dst|$dst, $src}", []>, XS;
3071 //===---------------------------------------------------------------------===//
3072 // SSE2 - Misc Instructions
3073 //===---------------------------------------------------------------------===//
3076 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3077 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
3078 TB, Requires<[HasSSE2]>;
3080 // Load, store, and memory fence
3081 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3082 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
3083 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3084 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
3085 def : Pat<(X86LFence), (LFENCE)>;
3086 def : Pat<(X86MFence), (MFENCE)>;
3089 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3090 // was introduced with SSE2, it's backward compatible.
3091 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
3093 // Alias instructions that map zero vector to pxor / xorp* for sse.
3094 // We set canFoldAsLoad because this can be converted to a constant-pool
3095 // load of an all-ones value if folding it would be beneficial.
3096 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
3097 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
3098 // FIXME: Change encoding to pseudo.
3099 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
3100 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
3102 //===---------------------------------------------------------------------===//
3103 // SSE3 - Conversion Instructions
3104 //===---------------------------------------------------------------------===//
3106 // Convert Packed Double FP to Packed DW Integers
3107 let Predicates = [HasAVX] in {
3108 // The assembler can recognize rr 256-bit instructions by seeing a ymm
3109 // register, but the same isn't true when using memory operands instead.
3110 // Provide other assembly rr and rm forms to address this explicitly.
3111 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3112 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3113 def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3114 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
3117 def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3118 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3119 def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3120 "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
3123 def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
3124 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX;
3125 def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
3126 "vcvtpd2dqy\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;
3129 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3130 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3131 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3132 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
3134 // Convert Packed DW Integers to Packed Double FP
3135 let Predicates = [HasAVX] in {
3136 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3137 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3138 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3139 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3140 def VCVTDQ2PDYrm : S3SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
3141 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3142 def VCVTDQ2PDYrr : S3SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
3143 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
3146 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3147 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3148 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3149 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
3151 // AVX 256-bit register conversion intrinsics
3152 def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
3153 (VCVTDQ2PDYrr VR128:$src)>;
3154 def : Pat<(int_x86_avx_cvtdq2_pd_256 (memopv4i32 addr:$src)),
3155 (VCVTDQ2PDYrm addr:$src)>;
3157 def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
3158 (VCVTPD2DQYrr VR256:$src)>;
3159 def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
3160 (VCVTPD2DQYrm addr:$src)>;
3162 //===---------------------------------------------------------------------===//
3163 // SSE3 - Move Instructions
3164 //===---------------------------------------------------------------------===//
3166 // Replicate Single FP
3167 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
3168 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3169 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3170 [(set VR128:$dst, (v4f32 (rep_frag
3171 VR128:$src, (undef))))]>;
3172 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3173 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3174 [(set VR128:$dst, (rep_frag
3175 (memopv4f32 addr:$src), (undef)))]>;
3178 multiclass sse3_replicate_sfp_y<bits<8> op, PatFrag rep_frag,
3180 def rr : S3SI<op, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3181 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3182 def rm : S3SI<op, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3183 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
3186 let Predicates = [HasAVX] in {
3187 // FIXME: Merge above classes when we have patterns for the ymm version
3188 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
3189 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
3190 defm VMOVSHDUPY : sse3_replicate_sfp_y<0x16, movshdup, "vmovshdup">, VEX;
3191 defm VMOVSLDUPY : sse3_replicate_sfp_y<0x12, movsldup, "vmovsldup">, VEX;
3193 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
3194 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
3196 // Replicate Double FP
3197 multiclass sse3_replicate_dfp<string OpcodeStr> {
3198 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3199 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3200 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
3201 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
3202 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
3208 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
3209 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3210 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3212 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3213 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3217 let Predicates = [HasAVX] in {
3218 // FIXME: Merge above classes when we have patterns for the ymm version
3219 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
3220 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX;
3222 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
3224 // Move Unaligned Integer
3225 let Predicates = [HasAVX] in {
3226 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3227 "vlddqu\t{$src, $dst|$dst, $src}",
3228 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3229 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3230 "vlddqu\t{$src, $dst|$dst, $src}",
3231 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>, VEX;
3233 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3234 "lddqu\t{$src, $dst|$dst, $src}",
3235 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3237 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3239 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3241 // Several Move patterns
3242 let AddedComplexity = 5 in {
3243 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3244 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3245 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3246 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3247 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3248 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3249 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3250 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3253 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3254 let AddedComplexity = 15 in
3255 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3256 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3257 let AddedComplexity = 20 in
3258 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3259 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3261 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3262 let AddedComplexity = 15 in
3263 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3264 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3265 let AddedComplexity = 20 in
3266 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3267 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3269 //===---------------------------------------------------------------------===//
3270 // SSE3 - Arithmetic
3271 //===---------------------------------------------------------------------===//
3273 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
3274 X86MemOperand x86memop, bit Is2Addr = 1> {
3275 def rr : I<0xD0, MRMSrcReg,
3276 (outs RC:$dst), (ins RC:$src1, RC:$src2),
3278 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3279 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3280 [(set RC:$dst, (Int RC:$src1, RC:$src2))]>;
3281 def rm : I<0xD0, MRMSrcMem,
3282 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3285 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3286 [(set RC:$dst, (Int RC:$src1, (memop addr:$src2)))]>;
3289 let Predicates = [HasAVX],
3290 ExeDomain = SSEPackedDouble in {
3291 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
3292 f128mem, 0>, TB, XD, VEX_4V;
3293 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
3294 f128mem, 0>, TB, OpSize, VEX_4V;
3295 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
3296 f256mem, 0>, TB, XD, VEX_4V;
3297 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
3298 f256mem, 0>, TB, OpSize, VEX_4V;
3300 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3301 ExeDomain = SSEPackedDouble in {
3302 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
3304 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
3305 f128mem>, TB, OpSize;
3308 //===---------------------------------------------------------------------===//
3309 // SSE3 Instructions
3310 //===---------------------------------------------------------------------===//
3313 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3314 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3315 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3317 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3318 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3319 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3321 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3323 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3324 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3325 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3327 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
3328 X86MemOperand x86memop, Intrinsic IntId, bit Is2Addr = 1> {
3329 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3331 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3332 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3333 [(set RC:$dst, (vt (IntId RC:$src1, RC:$src2)))]>;
3335 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3339 [(set RC:$dst, (vt (IntId RC:$src1, (memop addr:$src2))))]>;
3342 let Predicates = [HasAVX] in {
3343 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
3344 int_x86_sse3_hadd_ps, 0>, VEX_4V;
3345 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
3346 int_x86_sse3_hadd_pd, 0>, VEX_4V;
3347 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
3348 int_x86_sse3_hsub_ps, 0>, VEX_4V;
3349 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
3350 int_x86_sse3_hsub_pd, 0>, VEX_4V;
3351 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
3352 int_x86_avx_hadd_ps_256, 0>, VEX_4V;
3353 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
3354 int_x86_avx_hadd_pd_256, 0>, VEX_4V;
3355 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
3356 int_x86_avx_hsub_ps_256, 0>, VEX_4V;
3357 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
3358 int_x86_avx_hsub_pd_256, 0>, VEX_4V;
3361 let Constraints = "$src1 = $dst" in {
3362 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem,
3363 int_x86_sse3_hadd_ps>;
3364 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem,
3365 int_x86_sse3_hadd_pd>;
3366 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem,
3367 int_x86_sse3_hsub_ps>;
3368 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem,
3369 int_x86_sse3_hsub_pd>;
3372 //===---------------------------------------------------------------------===//
3373 // SSSE3 - Packed Absolute Instructions
3374 //===---------------------------------------------------------------------===//
3377 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3378 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3379 PatFrag mem_frag128, Intrinsic IntId128> {
3380 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3382 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3383 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3386 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3388 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3391 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3394 let Predicates = [HasAVX] in {
3395 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv16i8,
3396 int_x86_ssse3_pabs_b_128>, VEX;
3397 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv8i16,
3398 int_x86_ssse3_pabs_w_128>, VEX;
3399 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv4i32,
3400 int_x86_ssse3_pabs_d_128>, VEX;
3403 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv16i8,
3404 int_x86_ssse3_pabs_b_128>;
3405 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv8i16,
3406 int_x86_ssse3_pabs_w_128>;
3407 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv4i32,
3408 int_x86_ssse3_pabs_d_128>;
3410 //===---------------------------------------------------------------------===//
3411 // SSSE3 - Packed Binary Operator Instructions
3412 //===---------------------------------------------------------------------===//
3414 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3415 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3416 PatFrag mem_frag128, Intrinsic IntId128,
3418 let isCommutable = 1 in
3419 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3420 (ins VR128:$src1, VR128:$src2),
3422 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3423 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3424 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3426 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3427 (ins VR128:$src1, i128mem:$src2),
3429 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3430 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3432 (IntId128 VR128:$src1,
3433 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3436 let Predicates = [HasAVX] in {
3437 let isCommutable = 0 in {
3438 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv8i16,
3439 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3440 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv4i32,
3441 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3442 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv8i16,
3443 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3444 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv8i16,
3445 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3446 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv4i32,
3447 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3448 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv8i16,
3449 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3450 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv16i8,
3451 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3452 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv16i8,
3453 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3454 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv16i8,
3455 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3456 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv8i16,
3457 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3458 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv4i32,
3459 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3461 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv8i16,
3462 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3465 // None of these have i8 immediate fields.
3466 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3467 let isCommutable = 0 in {
3468 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv8i16,
3469 int_x86_ssse3_phadd_w_128>;
3470 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv4i32,
3471 int_x86_ssse3_phadd_d_128>;
3472 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv8i16,
3473 int_x86_ssse3_phadd_sw_128>;
3474 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv8i16,
3475 int_x86_ssse3_phsub_w_128>;
3476 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv4i32,
3477 int_x86_ssse3_phsub_d_128>;
3478 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv8i16,
3479 int_x86_ssse3_phsub_sw_128>;
3480 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv16i8,
3481 int_x86_ssse3_pmadd_ub_sw_128>;
3482 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv16i8,
3483 int_x86_ssse3_pshuf_b_128>;
3484 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv16i8,
3485 int_x86_ssse3_psign_b_128>;
3486 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv8i16,
3487 int_x86_ssse3_psign_w_128>;
3488 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv4i32,
3489 int_x86_ssse3_psign_d_128>;
3491 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv8i16,
3492 int_x86_ssse3_pmul_hr_sw_128>;
3495 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3496 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3497 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3498 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3500 def : Pat<(X86psignb VR128:$src1, VR128:$src2),
3501 (PSIGNBrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3502 def : Pat<(X86psignw VR128:$src1, VR128:$src2),
3503 (PSIGNWrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3504 def : Pat<(X86psignd VR128:$src1, VR128:$src2),
3505 (PSIGNDrr128 VR128:$src1, VR128:$src2)>, Requires<[HasSSSE3]>;
3507 //===---------------------------------------------------------------------===//
3508 // SSSE3 - Packed Align Instruction Patterns
3509 //===---------------------------------------------------------------------===//
3511 multiclass ssse3_palign<string asm, bit Is2Addr = 1> {
3512 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3513 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3515 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3517 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3519 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3520 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3522 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3524 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3528 let Predicates = [HasAVX] in
3529 defm VPALIGN : ssse3_palign<"vpalignr", 0>, VEX_4V;
3530 let Constraints = "$src1 = $dst" in
3531 defm PALIGN : ssse3_palign<"palignr">;
3533 let AddedComplexity = 5 in {
3534 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3535 (PALIGNR128rr VR128:$src2, VR128:$src1,
3536 (SHUFFLE_get_palign_imm VR128:$src3))>,
3537 Requires<[HasSSSE3]>;
3538 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3539 (PALIGNR128rr VR128:$src2, VR128:$src1,
3540 (SHUFFLE_get_palign_imm VR128:$src3))>,
3541 Requires<[HasSSSE3]>;
3542 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3543 (PALIGNR128rr VR128:$src2, VR128:$src1,
3544 (SHUFFLE_get_palign_imm VR128:$src3))>,
3545 Requires<[HasSSSE3]>;
3546 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3547 (PALIGNR128rr VR128:$src2, VR128:$src1,
3548 (SHUFFLE_get_palign_imm VR128:$src3))>,
3549 Requires<[HasSSSE3]>;
3552 //===---------------------------------------------------------------------===//
3553 // SSSE3 Misc Instructions
3554 //===---------------------------------------------------------------------===//
3556 // Thread synchronization
3557 let usesCustomInserter = 1 in {
3558 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
3559 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>;
3560 def MWAIT : PseudoI<(outs), (ins GR32:$src1, GR32:$src2),
3561 [(int_x86_sse3_mwait GR32:$src1, GR32:$src2)]>;
3564 let Uses = [EAX, ECX, EDX] in
3565 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", []>, TB,
3566 Requires<[HasSSE3]>;
3567 let Uses = [ECX, EAX] in
3568 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait", []>, TB,
3569 Requires<[HasSSE3]>;
3571 def : InstAlias<"mwait %eax, %ecx", (MWAITrr)>, Requires<[In32BitMode]>;
3572 def : InstAlias<"mwait %rax, %rcx", (MWAITrr)>, Requires<[In64BitMode]>;
3574 def : InstAlias<"monitor %eax, %ecx, %edx", (MONITORrrr)>,
3575 Requires<[In32BitMode]>;
3576 def : InstAlias<"monitor %rax, %rcx, %rdx", (MONITORrrr)>,
3577 Requires<[In64BitMode]>;
3579 //===---------------------------------------------------------------------===//
3580 // Non-Instruction Patterns
3581 //===---------------------------------------------------------------------===//
3583 // extload f32 -> f64. This matches load+fextend because we have a hack in
3584 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3586 // Since these loads aren't folded into the fextend, we have to match it
3588 let Predicates = [HasSSE2] in
3589 def : Pat<(fextend (loadf32 addr:$src)),
3590 (CVTSS2SDrm addr:$src)>;
3593 let Predicates = [HasXMMInt] in {
3594 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3595 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3596 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3597 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3598 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3599 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3600 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3601 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3602 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3603 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3604 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3605 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3606 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3607 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3608 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3609 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3610 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3611 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3612 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3613 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3614 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3615 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3616 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3617 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3618 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3619 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3620 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3621 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3622 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3623 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3626 let Predicates = [HasAVX] in {
3627 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
3630 // Move scalar to XMM zero-extended
3631 // movd to XMM register zero-extends
3632 let AddedComplexity = 15 in {
3633 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3634 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3635 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3636 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3637 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3638 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3639 (MOVSSrr (v4f32 (V_SET0PS)),
3640 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3641 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3642 (MOVSSrr (v4i32 (V_SET0PI)),
3643 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3646 // Splat v2f64 / v2i64
3647 let AddedComplexity = 10 in {
3648 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3649 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3650 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3651 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3652 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3653 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3654 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3655 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3658 // Special unary SHUFPSrri case.
3659 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3660 (SHUFPSrri VR128:$src1, VR128:$src1,
3661 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3662 let AddedComplexity = 5 in
3663 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3664 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3665 Requires<[HasSSE2]>;
3666 // Special unary SHUFPDrri case.
3667 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3668 (SHUFPDrri VR128:$src1, VR128:$src1,
3669 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3670 Requires<[HasSSE2]>;
3671 // Special unary SHUFPDrri case.
3672 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3673 (SHUFPDrri VR128:$src1, VR128:$src1,
3674 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3675 Requires<[HasSSE2]>;
3676 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3677 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3678 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3679 Requires<[HasSSE2]>;
3681 // Special binary v4i32 shuffle cases with SHUFPS.
3682 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3683 (SHUFPSrri VR128:$src1, VR128:$src2,
3684 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3685 Requires<[HasSSE2]>;
3686 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3687 (SHUFPSrmi VR128:$src1, addr:$src2,
3688 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3689 Requires<[HasSSE2]>;
3690 // Special binary v2i64 shuffle cases using SHUFPDrri.
3691 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3692 (SHUFPDrri VR128:$src1, VR128:$src2,
3693 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3694 Requires<[HasSSE2]>;
3696 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3697 let AddedComplexity = 15 in {
3698 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3699 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3700 Requires<[OptForSpeed, HasSSE2]>;
3701 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3702 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3703 Requires<[OptForSpeed, HasSSE2]>;
3705 let AddedComplexity = 10 in {
3706 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3707 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3708 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3709 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3710 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3711 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3712 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3713 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3716 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3717 let AddedComplexity = 15 in {
3718 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3719 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3720 Requires<[OptForSpeed, HasSSE2]>;
3721 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3722 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3723 Requires<[OptForSpeed, HasSSE2]>;
3725 let AddedComplexity = 10 in {
3726 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3727 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3728 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3729 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3730 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3731 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3732 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3733 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3736 let AddedComplexity = 20 in {
3737 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3738 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3739 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3741 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3742 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3743 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3745 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3746 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3747 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3748 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3749 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3752 let AddedComplexity = 20 in {
3753 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3754 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3755 (MOVLPSrm VR128:$src1, addr:$src2)>;
3756 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3757 (MOVLPDrm VR128:$src1, addr:$src2)>;
3758 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3759 (MOVLPSrm VR128:$src1, addr:$src2)>;
3760 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3761 (MOVLPDrm VR128:$src1, addr:$src2)>;
3764 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3765 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3766 (MOVLPSmr addr:$src1, VR128:$src2)>;
3767 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3768 (MOVLPDmr addr:$src1, VR128:$src2)>;
3769 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3771 (MOVLPSmr addr:$src1, VR128:$src2)>;
3772 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3773 (MOVLPDmr addr:$src1, VR128:$src2)>;
3775 let AddedComplexity = 15 in {
3776 // Setting the lowest element in the vector.
3777 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3778 (MOVSSrr (v4i32 VR128:$src1),
3779 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3780 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3781 (MOVSDrr (v2i64 VR128:$src1),
3782 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3784 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3785 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3786 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3787 Requires<[HasSSE2]>;
3788 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3789 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3790 Requires<[HasSSE2]>;
3793 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3794 // fall back to this for SSE1)
3795 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3796 (SHUFPSrri VR128:$src2, VR128:$src1,
3797 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3799 // Set lowest element and zero upper elements.
3800 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3801 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3803 // vector -> vector casts
3804 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3805 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3806 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3807 (CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3809 // Use movaps / movups for SSE integer load / store (one byte shorter).
3810 let Predicates = [HasSSE1] in {
3811 def : Pat<(alignedloadv4i32 addr:$src),
3812 (MOVAPSrm addr:$src)>;
3813 def : Pat<(loadv4i32 addr:$src),
3814 (MOVUPSrm addr:$src)>;
3815 def : Pat<(alignedloadv2i64 addr:$src),
3816 (MOVAPSrm addr:$src)>;
3817 def : Pat<(loadv2i64 addr:$src),
3818 (MOVUPSrm addr:$src)>;
3820 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3821 (MOVAPSmr addr:$dst, VR128:$src)>;
3822 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3823 (MOVAPSmr addr:$dst, VR128:$src)>;
3824 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3825 (MOVAPSmr addr:$dst, VR128:$src)>;
3826 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3827 (MOVAPSmr addr:$dst, VR128:$src)>;
3828 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3829 (MOVUPSmr addr:$dst, VR128:$src)>;
3830 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3831 (MOVUPSmr addr:$dst, VR128:$src)>;
3832 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3833 (MOVUPSmr addr:$dst, VR128:$src)>;
3834 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3835 (MOVUPSmr addr:$dst, VR128:$src)>;
3838 // Use vmovaps/vmovups for AVX 128-bit integer load/store (one byte shorter).
3839 let Predicates = [HasAVX] in {
3840 def : Pat<(alignedloadv4i32 addr:$src),
3841 (VMOVAPSrm addr:$src)>;
3842 def : Pat<(loadv4i32 addr:$src),
3843 (VMOVUPSrm addr:$src)>;
3844 def : Pat<(alignedloadv2i64 addr:$src),
3845 (VMOVAPSrm addr:$src)>;
3846 def : Pat<(loadv2i64 addr:$src),
3847 (VMOVUPSrm addr:$src)>;
3849 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3850 (VMOVAPSmr addr:$dst, VR128:$src)>;
3851 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3852 (VMOVAPSmr addr:$dst, VR128:$src)>;
3853 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3854 (VMOVAPSmr addr:$dst, VR128:$src)>;
3855 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3856 (VMOVAPSmr addr:$dst, VR128:$src)>;
3857 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3858 (VMOVUPSmr addr:$dst, VR128:$src)>;
3859 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3860 (VMOVUPSmr addr:$dst, VR128:$src)>;
3861 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3862 (VMOVUPSmr addr:$dst, VR128:$src)>;
3863 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3864 (VMOVUPSmr addr:$dst, VR128:$src)>;
3867 //===----------------------------------------------------------------------===//
3868 // SSE4.1 - Packed Move with Sign/Zero Extend
3869 //===----------------------------------------------------------------------===//
3871 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3872 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3873 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3874 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3876 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3877 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3879 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3883 let Predicates = [HasAVX] in {
3884 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3886 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3888 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3890 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3892 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3894 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3898 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3899 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3900 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3901 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3902 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3903 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3905 // Common patterns involving scalar load.
3906 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3907 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3908 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3909 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3911 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3912 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3913 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3914 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3916 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3917 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3918 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3919 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3921 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3922 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3923 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3924 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3926 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3927 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3928 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3929 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3931 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3932 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3933 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3934 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3937 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3938 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3939 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3940 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3942 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3943 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3945 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3949 let Predicates = [HasAVX] in {
3950 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
3952 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
3954 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
3956 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
3960 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3961 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3962 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3963 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3965 // Common patterns involving scalar load
3966 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3967 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3968 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3969 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3971 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3972 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3973 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3974 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3977 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3978 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3979 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3980 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3982 // Expecting a i16 load any extended to i32 value.
3983 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3984 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3985 [(set VR128:$dst, (IntId (bitconvert
3986 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3990 let Predicates = [HasAVX] in {
3991 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
3993 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
3996 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3997 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3999 // Common patterns involving scalar load
4000 def : Pat<(int_x86_sse41_pmovsxbq
4001 (bitconvert (v4i32 (X86vzmovl
4002 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4003 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
4005 def : Pat<(int_x86_sse41_pmovzxbq
4006 (bitconvert (v4i32 (X86vzmovl
4007 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
4008 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
4010 //===----------------------------------------------------------------------===//
4011 // SSE4.1 - Extract Instructions
4012 //===----------------------------------------------------------------------===//
4014 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
4015 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
4016 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4017 (ins VR128:$src1, i32i8imm:$src2),
4018 !strconcat(OpcodeStr,
4019 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4020 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
4022 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4023 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
4024 !strconcat(OpcodeStr,
4025 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4028 // There's an AssertZext in the way of writing the store pattern
4029 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4032 let Predicates = [HasAVX] in {
4033 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
4034 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
4035 (ins VR128:$src1, i32i8imm:$src2),
4036 "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;
4039 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
4042 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
4043 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
4044 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4045 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
4046 !strconcat(OpcodeStr,
4047 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4050 // There's an AssertZext in the way of writing the store pattern
4051 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
4054 let Predicates = [HasAVX] in
4055 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
4057 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
4060 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4061 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
4062 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4063 (ins VR128:$src1, i32i8imm:$src2),
4064 !strconcat(OpcodeStr,
4065 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4067 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
4068 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4069 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
4070 !strconcat(OpcodeStr,
4071 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4072 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
4073 addr:$dst)]>, OpSize;
4076 let Predicates = [HasAVX] in
4077 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
4079 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
4081 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
4082 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
4083 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
4084 (ins VR128:$src1, i32i8imm:$src2),
4085 !strconcat(OpcodeStr,
4086 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4088 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
4089 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4090 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
4091 !strconcat(OpcodeStr,
4092 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4093 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
4094 addr:$dst)]>, OpSize, REX_W;
4097 let Predicates = [HasAVX] in
4098 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
4100 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
4102 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
4104 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
4105 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4106 (ins VR128:$src1, i32i8imm:$src2),
4107 !strconcat(OpcodeStr,
4108 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4110 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
4112 def mr : SS4AIi8<opc, MRMDestMem, (outs),
4113 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
4114 !strconcat(OpcodeStr,
4115 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4116 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
4117 addr:$dst)]>, OpSize;
4120 let Predicates = [HasAVX] in {
4121 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
4122 def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),
4123 (ins VR128:$src1, i32i8imm:$src2),
4124 "vextractps \t{$src2, $src1, $dst|$dst, $src1, $src2}",
4127 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
4129 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
4130 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
4133 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
4134 Requires<[HasSSE41]>;
4136 //===----------------------------------------------------------------------===//
4137 // SSE4.1 - Insert Instructions
4138 //===----------------------------------------------------------------------===//
4140 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
4141 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4142 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4144 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4146 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4148 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
4149 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4150 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
4152 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4154 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4156 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
4157 imm:$src3))]>, OpSize;
4160 let Predicates = [HasAVX] in
4161 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
4162 let Constraints = "$src1 = $dst" in
4163 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
4165 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
4166 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4167 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
4169 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4171 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4173 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
4175 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4176 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
4178 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4180 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4182 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
4183 imm:$src3)))]>, OpSize;
4186 let Predicates = [HasAVX] in
4187 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
4188 let Constraints = "$src1 = $dst" in
4189 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
4191 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
4192 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4193 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
4195 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4197 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4199 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
4201 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4202 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4204 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4206 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4208 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4209 imm:$src3)))]>, OpSize;
4212 let Predicates = [HasAVX] in
4213 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4214 let Constraints = "$src1 = $dst" in
4215 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4217 // insertps has a few different modes, there's the first two here below which
4218 // are optimized inserts that won't zero arbitrary elements in the destination
4219 // vector. The next one matches the intrinsic and could zero arbitrary elements
4220 // in the target vector.
4221 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4222 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4223 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4225 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4227 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4229 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4231 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4232 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4234 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4236 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4238 (X86insrtps VR128:$src1,
4239 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4240 imm:$src3))]>, OpSize;
4243 let Constraints = "$src1 = $dst" in
4244 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4245 let Predicates = [HasAVX] in
4246 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4248 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4249 (VINSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4251 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4252 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>,
4253 Requires<[HasSSE41]>;
4255 //===----------------------------------------------------------------------===//
4256 // SSE4.1 - Round Instructions
4257 //===----------------------------------------------------------------------===//
4259 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4260 X86MemOperand x86memop, RegisterClass RC,
4261 PatFrag mem_frag32, PatFrag mem_frag64,
4262 Intrinsic V4F32Int, Intrinsic V2F64Int> {
4263 // Intrinsic operation, reg.
4264 // Vector intrinsic operation, reg
4265 def PSr : SS4AIi8<opcps, MRMSrcReg,
4266 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4267 !strconcat(OpcodeStr,
4268 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4269 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>,
4272 // Vector intrinsic operation, mem
4273 def PSm : Ii8<opcps, MRMSrcMem,
4274 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4275 !strconcat(OpcodeStr,
4276 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4278 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4280 Requires<[HasSSE41]>;
4282 // Vector intrinsic operation, reg
4283 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4284 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4285 !strconcat(OpcodeStr,
4286 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4287 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>,
4290 // Vector intrinsic operation, mem
4291 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4292 (outs RC:$dst), (ins f256mem:$src1, i32i8imm:$src2),
4293 !strconcat(OpcodeStr,
4294 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4296 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4300 multiclass sse41_fp_unop_rm_avx_p<bits<8> opcps, bits<8> opcpd,
4301 RegisterClass RC, X86MemOperand x86memop, string OpcodeStr> {
4302 // Intrinsic operation, reg.
4303 // Vector intrinsic operation, reg
4304 def PSr_AVX : SS4AIi8<opcps, MRMSrcReg,
4305 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4306 !strconcat(OpcodeStr,
4307 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4310 // Vector intrinsic operation, mem
4311 def PSm_AVX : Ii8<opcps, MRMSrcMem,
4312 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4313 !strconcat(OpcodeStr,
4314 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4315 []>, TA, OpSize, Requires<[HasSSE41]>;
4317 // Vector intrinsic operation, reg
4318 def PDr_AVX : SS4AIi8<opcpd, MRMSrcReg,
4319 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4320 !strconcat(OpcodeStr,
4321 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4324 // Vector intrinsic operation, mem
4325 def PDm_AVX : SS4AIi8<opcpd, MRMSrcMem,
4326 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4327 !strconcat(OpcodeStr,
4328 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4332 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4335 Intrinsic F64Int, bit Is2Addr = 1> {
4336 // Intrinsic operation, reg.
4337 def SSr : SS4AIi8<opcss, MRMSrcReg,
4338 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4340 !strconcat(OpcodeStr,
4341 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4342 !strconcat(OpcodeStr,
4343 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4344 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4347 // Intrinsic operation, mem.
4348 def SSm : SS4AIi8<opcss, MRMSrcMem,
4349 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4351 !strconcat(OpcodeStr,
4352 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4353 !strconcat(OpcodeStr,
4354 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4356 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4359 // Intrinsic operation, reg.
4360 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4361 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4363 !strconcat(OpcodeStr,
4364 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4365 !strconcat(OpcodeStr,
4366 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4367 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4370 // Intrinsic operation, mem.
4371 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4372 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4374 !strconcat(OpcodeStr,
4375 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4376 !strconcat(OpcodeStr,
4377 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4379 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4383 multiclass sse41_fp_binop_rm_avx_s<bits<8> opcss, bits<8> opcsd,
4385 // Intrinsic operation, reg.
4386 def SSr_AVX : SS4AIi8<opcss, MRMSrcReg,
4387 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4388 !strconcat(OpcodeStr,
4389 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4392 // Intrinsic operation, mem.
4393 def SSm_AVX : SS4AIi8<opcss, MRMSrcMem,
4394 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4395 !strconcat(OpcodeStr,
4396 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4399 // Intrinsic operation, reg.
4400 def SDr_AVX : SS4AIi8<opcsd, MRMSrcReg,
4401 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4402 !strconcat(OpcodeStr,
4403 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4406 // Intrinsic operation, mem.
4407 def SDm_AVX : SS4AIi8<opcsd, MRMSrcMem,
4408 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4409 !strconcat(OpcodeStr,
4410 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4414 // FP round - roundss, roundps, roundsd, roundpd
4415 let Predicates = [HasAVX] in {
4417 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
4418 memopv4f32, memopv2f64,
4419 int_x86_sse41_round_ps,
4420 int_x86_sse41_round_pd>, VEX;
4421 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
4422 memopv8f32, memopv4f64,
4423 int_x86_avx_round_ps_256,
4424 int_x86_avx_round_pd_256>, VEX;
4425 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4426 int_x86_sse41_round_ss,
4427 int_x86_sse41_round_sd, 0>, VEX_4V;
4429 // Instructions for the assembler
4430 defm VROUND : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR128, f128mem, "vround">,
4432 defm VROUNDY : sse41_fp_unop_rm_avx_p<0x08, 0x09, VR256, f256mem, "vround">,
4434 defm VROUND : sse41_fp_binop_rm_avx_s<0x0A, 0x0B, "vround">, VEX_4V;
4437 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
4438 memopv4f32, memopv2f64,
4439 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4440 let Constraints = "$src1 = $dst" in
4441 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4442 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4444 //===----------------------------------------------------------------------===//
4445 // SSE4.1 - Packed Bit Test
4446 //===----------------------------------------------------------------------===//
4448 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4449 // the intel intrinsic that corresponds to this.
4450 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4451 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4452 "vptest\t{$src2, $src1|$src1, $src2}",
4453 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4455 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4456 "vptest\t{$src2, $src1|$src1, $src2}",
4457 [(set EFLAGS,(X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4460 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
4461 "vptest\t{$src2, $src1|$src1, $src2}",
4462 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
4464 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
4465 "vptest\t{$src2, $src1|$src1, $src2}",
4466 [(set EFLAGS,(X86ptest VR256:$src1, (memopv4i64 addr:$src2)))]>,
4470 let Defs = [EFLAGS] in {
4471 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4472 "ptest \t{$src2, $src1|$src1, $src2}",
4473 [(set EFLAGS, (X86ptest VR128:$src1, (v4f32 VR128:$src2)))]>,
4475 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
4476 "ptest \t{$src2, $src1|$src1, $src2}",
4477 [(set EFLAGS, (X86ptest VR128:$src1, (memopv4f32 addr:$src2)))]>,
4481 // The bit test instructions below are AVX only
4482 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
4483 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
4484 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
4485 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4486 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>, OpSize, VEX;
4487 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
4488 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
4489 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
4493 let Defs = [EFLAGS], Predicates = [HasAVX] in {
4494 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, memopv4f32, v4f32>;
4495 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, memopv8f32, v8f32>;
4496 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, memopv2f64, v2f64>;
4497 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, memopv4f64, v4f64>;
4500 //===----------------------------------------------------------------------===//
4501 // SSE4.1 - Misc Instructions
4502 //===----------------------------------------------------------------------===//
4504 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
4505 "popcnt{w}\t{$src, $dst|$dst, $src}",
4506 [(set GR16:$dst, (ctpop GR16:$src))]>, OpSize, XS;
4507 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
4508 "popcnt{w}\t{$src, $dst|$dst, $src}",
4509 [(set GR16:$dst, (ctpop (loadi16 addr:$src)))]>, OpSize, XS;
4511 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
4512 "popcnt{l}\t{$src, $dst|$dst, $src}",
4513 [(set GR32:$dst, (ctpop GR32:$src))]>, XS;
4514 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
4515 "popcnt{l}\t{$src, $dst|$dst, $src}",
4516 [(set GR32:$dst, (ctpop (loadi32 addr:$src)))]>, XS;
4518 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
4519 "popcnt{q}\t{$src, $dst|$dst, $src}",
4520 [(set GR64:$dst, (ctpop GR64:$src))]>, XS;
4521 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
4522 "popcnt{q}\t{$src, $dst|$dst, $src}",
4523 [(set GR64:$dst, (ctpop (loadi64 addr:$src)))]>, XS;
4527 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4528 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4529 Intrinsic IntId128> {
4530 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4532 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4533 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4534 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4536 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4539 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4542 let Predicates = [HasAVX] in
4543 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4544 int_x86_sse41_phminposuw>, VEX;
4545 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4546 int_x86_sse41_phminposuw>;
4548 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4549 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4550 Intrinsic IntId128, bit Is2Addr = 1> {
4551 let isCommutable = 1 in
4552 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4553 (ins VR128:$src1, VR128:$src2),
4555 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4556 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4557 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4558 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4559 (ins VR128:$src1, i128mem:$src2),
4561 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4562 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4564 (IntId128 VR128:$src1,
4565 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4568 let Predicates = [HasAVX] in {
4569 let isCommutable = 0 in
4570 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4572 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4574 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4576 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4578 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4580 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4582 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4584 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4586 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4588 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4590 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4594 let Constraints = "$src1 = $dst" in {
4595 let isCommutable = 0 in
4596 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4597 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4598 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4599 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4600 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4601 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4602 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4603 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4604 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4605 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4606 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4609 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4610 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4611 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4612 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4614 /// SS48I_binop_rm - Simple SSE41 binary operator.
4615 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4616 ValueType OpVT, bit Is2Addr = 1> {
4617 let isCommutable = 1 in
4618 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4619 (ins VR128:$src1, VR128:$src2),
4621 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4622 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4623 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4625 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4626 (ins VR128:$src1, i128mem:$src2),
4628 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4629 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4630 [(set VR128:$dst, (OpNode VR128:$src1,
4631 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4635 let Predicates = [HasAVX] in
4636 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4637 let Constraints = "$src1 = $dst" in
4638 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4640 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4641 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4642 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
4643 X86MemOperand x86memop, bit Is2Addr = 1> {
4644 let isCommutable = 1 in
4645 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
4646 (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4648 !strconcat(OpcodeStr,
4649 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4650 !strconcat(OpcodeStr,
4651 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4652 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,
4654 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
4655 (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4657 !strconcat(OpcodeStr,
4658 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4659 !strconcat(OpcodeStr,
4660 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4663 (bitconvert (memop_frag addr:$src2)), imm:$src3))]>,
4667 let Predicates = [HasAVX] in {
4668 let isCommutable = 0 in {
4669 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4670 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4671 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4672 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4673 defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",
4674 int_x86_avx_blend_ps_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4675 defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",
4676 int_x86_avx_blend_pd_256, VR256, memopv32i8, i256mem, 0>, VEX_4V;
4677 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4678 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4679 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4680 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4682 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4683 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4684 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4685 VR128, memopv16i8, i128mem, 0>, VEX_4V;
4686 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
4687 VR256, memopv32i8, i256mem, 0>, VEX_4V;
4690 let Constraints = "$src1 = $dst" in {
4691 let isCommutable = 0 in {
4692 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,
4693 VR128, memopv16i8, i128mem>;
4694 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd,
4695 VR128, memopv16i8, i128mem>;
4696 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,
4697 VR128, memopv16i8, i128mem>;
4698 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
4699 VR128, memopv16i8, i128mem>;
4701 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
4702 VR128, memopv16i8, i128mem>;
4703 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
4704 VR128, memopv16i8, i128mem>;
4707 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4708 let Predicates = [HasAVX] in {
4709 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
4710 RegisterClass RC, X86MemOperand x86memop,
4711 PatFrag mem_frag, Intrinsic IntId> {
4712 def rr : I<opc, MRMSrcReg, (outs RC:$dst),
4713 (ins RC:$src1, RC:$src2, RC:$src3),
4714 !strconcat(OpcodeStr,
4715 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4716 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
4717 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4719 def rm : I<opc, MRMSrcMem, (outs RC:$dst),
4720 (ins RC:$src1, x86memop:$src2, RC:$src3),
4721 !strconcat(OpcodeStr,
4722 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4724 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
4726 SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4730 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, i128mem,
4731 memopv16i8, int_x86_sse41_blendvpd>;
4732 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, i128mem,
4733 memopv16i8, int_x86_sse41_blendvps>;
4734 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
4735 memopv16i8, int_x86_sse41_pblendvb>;
4736 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, i256mem,
4737 memopv32i8, int_x86_avx_blendv_pd_256>;
4738 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, i256mem,
4739 memopv32i8, int_x86_avx_blendv_ps_256>;
4741 /// SS41I_ternary_int - SSE 4.1 ternary operator
4742 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4743 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4744 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4745 (ins VR128:$src1, VR128:$src2),
4746 !strconcat(OpcodeStr,
4747 "\t{$src2, $dst|$dst, $src2}"),
4748 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4751 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4752 (ins VR128:$src1, i128mem:$src2),
4753 !strconcat(OpcodeStr,
4754 "\t{$src2, $dst|$dst, $src2}"),
4757 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4761 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4762 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4763 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4765 def : Pat<(X86pblendv VR128:$src1, VR128:$src2, XMM0),
4766 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
4768 let Predicates = [HasAVX] in
4769 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4770 "vmovntdqa\t{$src, $dst|$dst, $src}",
4771 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4773 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4774 "movntdqa\t{$src, $dst|$dst, $src}",
4775 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4778 //===----------------------------------------------------------------------===//
4779 // SSE4.2 - Compare Instructions
4780 //===----------------------------------------------------------------------===//
4782 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4783 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4784 Intrinsic IntId128, bit Is2Addr = 1> {
4785 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4786 (ins VR128:$src1, VR128:$src2),
4788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4790 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4792 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4793 (ins VR128:$src1, i128mem:$src2),
4795 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4796 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4798 (IntId128 VR128:$src1,
4799 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4802 let Predicates = [HasAVX] in
4803 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4805 let Constraints = "$src1 = $dst" in
4806 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4808 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4809 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4810 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4811 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4813 //===----------------------------------------------------------------------===//
4814 // SSE4.2 - String/text Processing Instructions
4815 //===----------------------------------------------------------------------===//
4817 // Packed Compare Implicit Length Strings, Return Mask
4818 multiclass pseudo_pcmpistrm<string asm> {
4819 def REG : PseudoI<(outs VR128:$dst),
4820 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4821 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4823 def MEM : PseudoI<(outs VR128:$dst),
4824 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4825 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4826 VR128:$src1, (load addr:$src2), imm:$src3))]>;
4829 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4830 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128">, Requires<[HasSSE42]>;
4831 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128">, Requires<[HasAVX]>;
4834 let Defs = [XMM0, EFLAGS], Predicates = [HasAVX] in {
4835 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4836 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4837 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4838 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4839 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4840 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4843 let Defs = [XMM0, EFLAGS] in {
4844 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4845 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4846 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4847 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4848 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4849 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4852 // Packed Compare Explicit Length Strings, Return Mask
4853 multiclass pseudo_pcmpestrm<string asm> {
4854 def REG : PseudoI<(outs VR128:$dst),
4855 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4856 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4857 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
4858 def MEM : PseudoI<(outs VR128:$dst),
4859 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4860 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4861 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>;
4864 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4865 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128">, Requires<[HasSSE42]>;
4866 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128">, Requires<[HasAVX]>;
4869 let Predicates = [HasAVX],
4870 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4871 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4872 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4873 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4874 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4875 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4876 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4879 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4880 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4881 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4882 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4883 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4884 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4885 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4888 // Packed Compare Implicit Length Strings, Return Index
4889 let Defs = [ECX, EFLAGS] in {
4890 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4891 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4892 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4893 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4894 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4895 (implicit EFLAGS)]>, OpSize;
4896 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4897 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4898 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4899 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4900 (implicit EFLAGS)]>, OpSize;
4904 let Predicates = [HasAVX] in {
4905 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4907 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4909 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4911 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4913 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4915 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4919 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4920 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4921 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4922 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4923 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4924 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4926 // Packed Compare Explicit Length Strings, Return Index
4927 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
4928 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
4929 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4930 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4931 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4932 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4933 (implicit EFLAGS)]>, OpSize;
4934 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4935 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4936 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4938 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4939 (implicit EFLAGS)]>, OpSize;
4943 let Predicates = [HasAVX] in {
4944 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
4946 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
4948 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
4950 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
4952 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
4954 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
4958 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4959 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4960 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4961 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4962 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4963 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4965 //===----------------------------------------------------------------------===//
4966 // SSE4.2 - CRC Instructions
4967 //===----------------------------------------------------------------------===//
4969 // No CRC instructions have AVX equivalents
4971 // crc intrinsic instruction
4972 // This set of instructions are only rm, the only difference is the size
4974 let Constraints = "$src1 = $dst" in {
4975 def CRC32r32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4976 (ins GR32:$src1, i8mem:$src2),
4977 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4979 (int_x86_sse42_crc32_32_8 GR32:$src1,
4980 (load addr:$src2)))]>;
4981 def CRC32r32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4982 (ins GR32:$src1, GR8:$src2),
4983 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4985 (int_x86_sse42_crc32_32_8 GR32:$src1, GR8:$src2))]>;
4986 def CRC32r32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4987 (ins GR32:$src1, i16mem:$src2),
4988 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4990 (int_x86_sse42_crc32_32_16 GR32:$src1,
4991 (load addr:$src2)))]>,
4993 def CRC32r32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4994 (ins GR32:$src1, GR16:$src2),
4995 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4997 (int_x86_sse42_crc32_32_16 GR32:$src1, GR16:$src2))]>,
4999 def CRC32r32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
5000 (ins GR32:$src1, i32mem:$src2),
5001 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5003 (int_x86_sse42_crc32_32_32 GR32:$src1,
5004 (load addr:$src2)))]>;
5005 def CRC32r32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
5006 (ins GR32:$src1, GR32:$src2),
5007 "crc32{l} \t{$src2, $src1|$src1, $src2}",
5009 (int_x86_sse42_crc32_32_32 GR32:$src1, GR32:$src2))]>;
5010 def CRC32r64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
5011 (ins GR64:$src1, i8mem:$src2),
5012 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5014 (int_x86_sse42_crc32_64_8 GR64:$src1,
5015 (load addr:$src2)))]>,
5017 def CRC32r64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
5018 (ins GR64:$src1, GR8:$src2),
5019 "crc32{b} \t{$src2, $src1|$src1, $src2}",
5021 (int_x86_sse42_crc32_64_8 GR64:$src1, GR8:$src2))]>,
5023 def CRC32r64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
5024 (ins GR64:$src1, i64mem:$src2),
5025 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5027 (int_x86_sse42_crc32_64_64 GR64:$src1,
5028 (load addr:$src2)))]>,
5030 def CRC32r64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
5031 (ins GR64:$src1, GR64:$src2),
5032 "crc32{q} \t{$src2, $src1|$src1, $src2}",
5034 (int_x86_sse42_crc32_64_64 GR64:$src1, GR64:$src2))]>,
5038 //===----------------------------------------------------------------------===//
5039 // AES-NI Instructions
5040 //===----------------------------------------------------------------------===//
5042 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
5043 Intrinsic IntId128, bit Is2Addr = 1> {
5044 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
5045 (ins VR128:$src1, VR128:$src2),
5047 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5048 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5049 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5051 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
5052 (ins VR128:$src1, i128mem:$src2),
5054 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5055 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5057 (IntId128 VR128:$src1,
5058 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
5061 // Perform One Round of an AES Encryption/Decryption Flow
5062 let Predicates = [HasAVX, HasAES] in {
5063 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
5064 int_x86_aesni_aesenc, 0>, VEX_4V;
5065 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
5066 int_x86_aesni_aesenclast, 0>, VEX_4V;
5067 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
5068 int_x86_aesni_aesdec, 0>, VEX_4V;
5069 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
5070 int_x86_aesni_aesdeclast, 0>, VEX_4V;
5073 let Constraints = "$src1 = $dst" in {
5074 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
5075 int_x86_aesni_aesenc>;
5076 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
5077 int_x86_aesni_aesenclast>;
5078 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
5079 int_x86_aesni_aesdec>;
5080 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
5081 int_x86_aesni_aesdeclast>;
5084 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
5085 (AESENCrr VR128:$src1, VR128:$src2)>;
5086 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
5087 (AESENCrm VR128:$src1, addr:$src2)>;
5088 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
5089 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
5090 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
5091 (AESENCLASTrm VR128:$src1, addr:$src2)>;
5092 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
5093 (AESDECrr VR128:$src1, VR128:$src2)>;
5094 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
5095 (AESDECrm VR128:$src1, addr:$src2)>;
5096 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
5097 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
5098 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
5099 (AESDECLASTrm VR128:$src1, addr:$src2)>;
5101 // Perform the AES InvMixColumn Transformation
5102 let Predicates = [HasAVX, HasAES] in {
5103 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5105 "vaesimc\t{$src1, $dst|$dst, $src1}",
5107 (int_x86_aesni_aesimc VR128:$src1))]>,
5109 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5110 (ins i128mem:$src1),
5111 "vaesimc\t{$src1, $dst|$dst, $src1}",
5113 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5116 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
5118 "aesimc\t{$src1, $dst|$dst, $src1}",
5120 (int_x86_aesni_aesimc VR128:$src1))]>,
5122 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
5123 (ins i128mem:$src1),
5124 "aesimc\t{$src1, $dst|$dst, $src1}",
5126 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
5129 // AES Round Key Generation Assist
5130 let Predicates = [HasAVX, HasAES] in {
5131 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5132 (ins VR128:$src1, i8imm:$src2),
5133 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5135 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5137 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5138 (ins i128mem:$src1, i8imm:$src2),
5139 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5141 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5145 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
5146 (ins VR128:$src1, i8imm:$src2),
5147 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5149 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
5151 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
5152 (ins i128mem:$src1, i8imm:$src2),
5153 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5155 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
5159 //===----------------------------------------------------------------------===//
5160 // CLMUL Instructions
5161 //===----------------------------------------------------------------------===//
5163 // Only the AVX version of CLMUL instructions are described here.
5165 // Carry-less Multiplication instructions
5166 def VPCLMULQDQrr : CLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
5167 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
5168 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5171 def VPCLMULQDQrm : CLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
5172 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
5173 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5177 multiclass avx_vpclmul<string asm> {
5178 def rr : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
5179 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5182 def rm : I<0, Pseudo, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
5183 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5186 defm VPCLMULHQHQDQ : avx_vpclmul<"vpclmulhqhqdq">;
5187 defm VPCLMULHQLQDQ : avx_vpclmul<"vpclmulhqlqdq">;
5188 defm VPCLMULLQHQDQ : avx_vpclmul<"vpclmullqhqdq">;
5189 defm VPCLMULLQLQDQ : avx_vpclmul<"vpclmullqlqdq">;
5191 //===----------------------------------------------------------------------===//
5193 //===----------------------------------------------------------------------===//
5196 // Load from memory and broadcast to all elements of the destination operand
5197 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
5198 X86MemOperand x86memop, Intrinsic Int> :
5199 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5200 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5201 [(set RC:$dst, (Int addr:$src))]>, VEX;
5203 def VBROADCASTSS : avx_broadcast<0x18, "vbroadcastss", VR128, f32mem,
5204 int_x86_avx_vbroadcastss>;
5205 def VBROADCASTSSY : avx_broadcast<0x18, "vbroadcastss", VR256, f32mem,
5206 int_x86_avx_vbroadcastss_256>;
5207 def VBROADCASTSD : avx_broadcast<0x19, "vbroadcastsd", VR256, f64mem,
5208 int_x86_avx_vbroadcast_sd_256>;
5209 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
5210 int_x86_avx_vbroadcastf128_pd_256>;
5212 // Insert packed floating-point values
5213 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
5214 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
5215 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5217 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
5218 (ins VR256:$src1, f128mem:$src2, i8imm:$src3),
5219 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5222 // Extract packed floating-point values
5223 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
5224 (ins VR256:$src1, i8imm:$src2),
5225 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5227 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
5228 (ins f128mem:$dst, VR256:$src1, i8imm:$src2),
5229 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
5232 // Conditional SIMD Packed Loads and Stores
5233 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
5234 Intrinsic IntLd, Intrinsic IntLd256,
5235 Intrinsic IntSt, Intrinsic IntSt256,
5236 PatFrag pf128, PatFrag pf256> {
5237 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
5238 (ins VR128:$src1, f128mem:$src2),
5239 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5240 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
5242 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
5243 (ins VR256:$src1, f256mem:$src2),
5244 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5245 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
5247 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
5248 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
5249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5250 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
5251 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
5252 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
5253 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5254 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V;
5257 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
5258 int_x86_avx_maskload_ps,
5259 int_x86_avx_maskload_ps_256,
5260 int_x86_avx_maskstore_ps,
5261 int_x86_avx_maskstore_ps_256,
5262 memopv4f32, memopv8f32>;
5263 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
5264 int_x86_avx_maskload_pd,
5265 int_x86_avx_maskload_pd_256,
5266 int_x86_avx_maskstore_pd,
5267 int_x86_avx_maskstore_pd_256,
5268 memopv2f64, memopv4f64>;
5270 // Permute Floating-Point Values
5271 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
5272 RegisterClass RC, X86MemOperand x86memop_f,
5273 X86MemOperand x86memop_i, PatFrag f_frag, PatFrag i_frag,
5274 Intrinsic IntVar, Intrinsic IntImm> {
5275 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
5276 (ins RC:$src1, RC:$src2),
5277 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5278 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V;
5279 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
5280 (ins RC:$src1, x86memop_i:$src2),
5281 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5282 [(set RC:$dst, (IntVar RC:$src1, (i_frag addr:$src2)))]>, VEX_4V;
5284 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
5285 (ins RC:$src1, i8imm:$src2),
5286 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5287 [(set RC:$dst, (IntImm RC:$src1, imm:$src2))]>, VEX;
5288 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
5289 (ins x86memop_f:$src1, i8imm:$src2),
5290 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5291 [(set RC:$dst, (IntImm (f_frag addr:$src1), imm:$src2))]>, VEX;
5294 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
5295 memopv4f32, memopv4i32,
5296 int_x86_avx_vpermilvar_ps,
5297 int_x86_avx_vpermil_ps>;
5298 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
5299 memopv8f32, memopv8i32,
5300 int_x86_avx_vpermilvar_ps_256,
5301 int_x86_avx_vpermil_ps_256>;
5302 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
5303 memopv2f64, memopv2i64,
5304 int_x86_avx_vpermilvar_pd,
5305 int_x86_avx_vpermil_pd>;
5306 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
5307 memopv4f64, memopv4i64,
5308 int_x86_avx_vpermilvar_pd_256,
5309 int_x86_avx_vpermil_pd_256>;
5311 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
5312 (ins VR256:$src1, VR256:$src2, i8imm:$src3),
5313 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5315 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
5316 (ins VR256:$src1, f256mem:$src2, i8imm:$src3),
5317 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
5320 // Zero All YMM registers
5321 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
5322 [(int_x86_avx_vzeroall)]>, VEX, VEX_L, Requires<[HasAVX]>;
5324 // Zero Upper bits of YMM registers
5325 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
5326 [(int_x86_avx_vzeroupper)]>, VEX, Requires<[HasAVX]>;
5328 def : Pat<(int_x86_avx_vinsertf128_pd_256 VR256:$src1, VR128:$src2, imm:$src3),
5329 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5330 def : Pat<(int_x86_avx_vinsertf128_ps_256 VR256:$src1, VR128:$src2, imm:$src3),
5331 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5332 def : Pat<(int_x86_avx_vinsertf128_si_256 VR256:$src1, VR128:$src2, imm:$src3),
5333 (VINSERTF128rr VR256:$src1, VR128:$src2, imm:$src3)>;
5335 def : Pat<(vinsertf128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
5337 (VINSERTF128rr VR256:$src1, VR128:$src2,
5338 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5339 def : Pat<(vinsertf128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
5341 (VINSERTF128rr VR256:$src1, VR128:$src2,
5342 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5343 def : Pat<(vinsertf128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
5345 (VINSERTF128rr VR256:$src1, VR128:$src2,
5346 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5347 def : Pat<(vinsertf128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
5349 (VINSERTF128rr VR256:$src1, VR128:$src2,
5350 (INSERT_get_vinsertf128_imm VR256:$ins))>;
5352 def : Pat<(int_x86_avx_vextractf128_pd_256 VR256:$src1, imm:$src2),
5353 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5354 def : Pat<(int_x86_avx_vextractf128_ps_256 VR256:$src1, imm:$src2),
5355 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5356 def : Pat<(int_x86_avx_vextractf128_si_256 VR256:$src1, imm:$src2),
5357 (VEXTRACTF128rr VR256:$src1, imm:$src2)>;
5359 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5360 (v4f32 (VEXTRACTF128rr
5361 (v8f32 VR256:$src1),
5362 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5363 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5364 (v2f64 (VEXTRACTF128rr
5365 (v4f64 VR256:$src1),
5366 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5367 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5368 (v4i32 (VEXTRACTF128rr
5369 (v8i32 VR256:$src1),
5370 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5371 def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
5372 (v2i64 (VEXTRACTF128rr
5373 (v4i64 VR256:$src1),
5374 (EXTRACT_get_vextractf128_imm VR128:$ext)))>;
5376 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
5377 (VBROADCASTF128 addr:$src)>;
5379 def : Pat<(int_x86_avx_vperm2f128_ps_256 VR256:$src1, VR256:$src2, imm:$src3),
5380 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5381 def : Pat<(int_x86_avx_vperm2f128_pd_256 VR256:$src1, VR256:$src2, imm:$src3),
5382 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5383 def : Pat<(int_x86_avx_vperm2f128_si_256 VR256:$src1, VR256:$src2, imm:$src3),
5384 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$src3)>;
5386 def : Pat<(int_x86_avx_vperm2f128_ps_256
5387 VR256:$src1, (memopv8f32 addr:$src2), imm:$src3),
5388 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5389 def : Pat<(int_x86_avx_vperm2f128_pd_256
5390 VR256:$src1, (memopv4f64 addr:$src2), imm:$src3),
5391 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5392 def : Pat<(int_x86_avx_vperm2f128_si_256
5393 VR256:$src1, (memopv8i32 addr:$src2), imm:$src3),
5394 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$src3)>;
5396 //===----------------------------------------------------------------------===//
5397 // SSE Shuffle pattern fragments
5398 //===----------------------------------------------------------------------===//
5400 // This is part of a "work in progress" refactoring. The idea is that all
5401 // vector shuffles are going to be translated into target specific nodes and
5402 // directly matched by the patterns below (which can be changed along the way)
5403 // The AVX version of some but not all of them are described here, and more
5404 // should come in a near future.
5406 // Shuffle with PSHUFD instruction folding loads. The first two patterns match
5407 // SSE2 loads, which are always promoted to v2i64. The last one should match
5408 // the SSE1 case, where the only legal load is v4f32, but there is no PSHUFD
5409 // in SSE2, how does it ever worked? Anyway, the pattern will remain here until
5410 // we investigate further.
5411 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5413 (VPSHUFDmi addr:$src1, imm:$imm)>, Requires<[HasAVX]>;
5414 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv2i64 addr:$src1)),
5416 (PSHUFDmi addr:$src1, imm:$imm)>;
5417 def : Pat<(v4i32 (X86PShufd (bc_v4i32 (memopv4f32 addr:$src1)),
5419 (PSHUFDmi addr:$src1, imm:$imm)>; // FIXME: has this ever worked?
5421 // Shuffle with PSHUFD instruction.
5422 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5423 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5424 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5425 (PSHUFDri VR128:$src1, imm:$imm)>;
5427 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5428 (VPSHUFDri VR128:$src1, imm:$imm)>, Requires<[HasAVX]>;
5429 def : Pat<(v4i32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
5430 (PSHUFDri VR128:$src1, imm:$imm)>;
5432 // Shuffle with SHUFPD instruction.
5433 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5434 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5435 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5436 def : Pat<(v2f64 (X86Shufps VR128:$src1,
5437 (memopv2f64 addr:$src2), (i8 imm:$imm))),
5438 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
5440 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5441 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5442 def : Pat<(v2i64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5443 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5445 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5446 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5447 def : Pat<(v2f64 (X86Shufpd VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5448 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
5450 // Shuffle with SHUFPS instruction.
5451 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5452 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5453 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5454 def : Pat<(v4f32 (X86Shufps VR128:$src1,
5455 (memopv4f32 addr:$src2), (i8 imm:$imm))),
5456 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5458 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5459 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5460 def : Pat<(v4f32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5461 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5463 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5464 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5465 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>, Requires<[HasAVX]>;
5466 def : Pat<(v4i32 (X86Shufps VR128:$src1,
5467 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
5468 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
5470 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5471 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>, Requires<[HasAVX]>;
5472 def : Pat<(v4i32 (X86Shufps VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5473 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
5475 // Shuffle with MOVHLPS instruction
5476 def : Pat<(v4f32 (X86Movhlps VR128:$src1, VR128:$src2)),
5477 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5478 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
5479 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
5481 // Shuffle with MOVDDUP instruction
5482 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5483 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5484 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5485 (MOVDDUPrm addr:$src)>;
5487 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5488 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5489 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5490 (MOVDDUPrm addr:$src)>;
5492 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5493 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5494 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5495 (MOVDDUPrm addr:$src)>;
5497 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5498 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5499 def : Pat<(X86Movddup (v2f64 (scalar_to_vector (loadf64 addr:$src)))),
5500 (MOVDDUPrm addr:$src)>;
5502 def : Pat<(X86Movddup (bc_v2f64
5503 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5504 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5505 def : Pat<(X86Movddup (bc_v2f64
5506 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5507 (MOVDDUPrm addr:$src)>;
5510 // Shuffle with UNPCKLPS
5511 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5512 (VUNPCKLPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5513 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, (memopv8f32 addr:$src2))),
5514 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5515 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, (memopv4f32 addr:$src2))),
5516 (UNPCKLPSrm VR128:$src1, addr:$src2)>;
5518 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5519 (VUNPCKLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5520 def : Pat<(v8f32 (X86Unpcklpsy VR256:$src1, VR256:$src2)),
5521 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5522 def : Pat<(v4f32 (X86Unpcklps VR128:$src1, VR128:$src2)),
5523 (UNPCKLPSrr VR128:$src1, VR128:$src2)>;
5525 // Shuffle with UNPCKHPS
5526 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5527 (VUNPCKHPSrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5528 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, (memopv4f32 addr:$src2))),
5529 (UNPCKHPSrm VR128:$src1, addr:$src2)>;
5531 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5532 (VUNPCKHPSrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5533 def : Pat<(v4f32 (X86Unpckhps VR128:$src1, VR128:$src2)),
5534 (UNPCKHPSrr VR128:$src1, VR128:$src2)>;
5536 // Shuffle with UNPCKLPD
5537 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5538 (VUNPCKLPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5539 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, (memopv4f64 addr:$src2))),
5540 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>, Requires<[HasAVX]>;
5541 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, (memopv2f64 addr:$src2))),
5542 (UNPCKLPDrm VR128:$src1, addr:$src2)>;
5544 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5545 (VUNPCKLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5546 def : Pat<(v4f64 (X86Unpcklpdy VR256:$src1, VR256:$src2)),
5547 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>, Requires<[HasAVX]>;
5548 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1, VR128:$src2)),
5549 (UNPCKLPDrr VR128:$src1, VR128:$src2)>;
5551 // Shuffle with UNPCKHPD
5552 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5553 (VUNPCKHPDrm VR128:$src1, addr:$src2)>, Requires<[HasAVX]>;
5554 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, (memopv2f64 addr:$src2))),
5555 (UNPCKHPDrm VR128:$src1, addr:$src2)>;
5557 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5558 (VUNPCKHPDrr VR128:$src1, VR128:$src2)>, Requires<[HasAVX]>;
5559 def : Pat<(v2f64 (X86Unpckhpd VR128:$src1, VR128:$src2)),
5560 (UNPCKHPDrr VR128:$src1, VR128:$src2)>;
5562 // Shuffle with PUNPCKLBW
5563 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1,
5564 (bc_v16i8 (memopv2i64 addr:$src2)))),
5565 (PUNPCKLBWrm VR128:$src1, addr:$src2)>;
5566 def : Pat<(v16i8 (X86Punpcklbw VR128:$src1, VR128:$src2)),
5567 (PUNPCKLBWrr VR128:$src1, VR128:$src2)>;
5569 // Shuffle with PUNPCKLWD
5570 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1,
5571 (bc_v8i16 (memopv2i64 addr:$src2)))),
5572 (PUNPCKLWDrm VR128:$src1, addr:$src2)>;
5573 def : Pat<(v8i16 (X86Punpcklwd VR128:$src1, VR128:$src2)),
5574 (PUNPCKLWDrr VR128:$src1, VR128:$src2)>;
5576 // Shuffle with PUNPCKLDQ
5577 def : Pat<(v4i32 (X86Punpckldq VR128:$src1,
5578 (bc_v4i32 (memopv2i64 addr:$src2)))),
5579 (PUNPCKLDQrm VR128:$src1, addr:$src2)>;
5580 def : Pat<(v4i32 (X86Punpckldq VR128:$src1, VR128:$src2)),
5581 (PUNPCKLDQrr VR128:$src1, VR128:$src2)>;
5583 // Shuffle with PUNPCKLQDQ
5584 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, (memopv2i64 addr:$src2))),
5585 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>;
5586 def : Pat<(v2i64 (X86Punpcklqdq VR128:$src1, VR128:$src2)),
5587 (PUNPCKLQDQrr VR128:$src1, VR128:$src2)>;
5589 // Shuffle with PUNPCKHBW
5590 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1,
5591 (bc_v16i8 (memopv2i64 addr:$src2)))),
5592 (PUNPCKHBWrm VR128:$src1, addr:$src2)>;
5593 def : Pat<(v16i8 (X86Punpckhbw VR128:$src1, VR128:$src2)),
5594 (PUNPCKHBWrr VR128:$src1, VR128:$src2)>;
5596 // Shuffle with PUNPCKHWD
5597 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1,
5598 (bc_v8i16 (memopv2i64 addr:$src2)))),
5599 (PUNPCKHWDrm VR128:$src1, addr:$src2)>;
5600 def : Pat<(v8i16 (X86Punpckhwd VR128:$src1, VR128:$src2)),
5601 (PUNPCKHWDrr VR128:$src1, VR128:$src2)>;
5603 // Shuffle with PUNPCKHDQ
5604 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1,
5605 (bc_v4i32 (memopv2i64 addr:$src2)))),
5606 (PUNPCKHDQrm VR128:$src1, addr:$src2)>;
5607 def : Pat<(v4i32 (X86Punpckhdq VR128:$src1, VR128:$src2)),
5608 (PUNPCKHDQrr VR128:$src1, VR128:$src2)>;
5610 // Shuffle with PUNPCKHQDQ
5611 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, (memopv2i64 addr:$src2))),
5612 (PUNPCKHQDQrm VR128:$src1, addr:$src2)>;
5613 def : Pat<(v2i64 (X86Punpckhqdq VR128:$src1, VR128:$src2)),
5614 (PUNPCKHQDQrr VR128:$src1, VR128:$src2)>;
5616 // Shuffle with MOVLHPS
5617 def : Pat<(X86Movlhps VR128:$src1,
5618 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5619 (MOVHPSrm VR128:$src1, addr:$src2)>;
5620 def : Pat<(X86Movlhps VR128:$src1,
5621 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
5622 (MOVHPSrm VR128:$src1, addr:$src2)>;
5623 def : Pat<(v4f32 (X86Movlhps VR128:$src1, VR128:$src2)),
5624 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5625 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
5626 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
5627 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
5628 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
5630 // FIXME: Instead of X86Movddup, there should be a X86Unpcklpd here, the problem
5631 // is during lowering, where it's not possible to recognize the load fold cause
5632 // it has two uses through a bitcast. One use disappears at isel time and the
5633 // fold opportunity reappears.
5634 def : Pat<(v2f64 (X86Movddup VR128:$src)),
5635 (UNPCKLPDrr VR128:$src, VR128:$src)>;
5637 // Shuffle with MOVLHPD
5638 def : Pat<(v2f64 (X86Movlhpd VR128:$src1,
5639 (scalar_to_vector (loadf64 addr:$src2)))),
5640 (MOVHPDrm VR128:$src1, addr:$src2)>;
5642 // FIXME: Instead of X86Unpcklpd, there should be a X86Movlhpd here, the problem
5643 // is during lowering, where it's not possible to recognize the load fold cause
5644 // it has two uses through a bitcast. One use disappears at isel time and the
5645 // fold opportunity reappears.
5646 def : Pat<(v2f64 (X86Unpcklpd VR128:$src1,
5647 (scalar_to_vector (loadf64 addr:$src2)))),
5648 (MOVHPDrm VR128:$src1, addr:$src2)>;
5650 // Shuffle with MOVSS
5651 def : Pat<(v4f32 (X86Movss VR128:$src1, (scalar_to_vector FR32:$src2))),
5652 (MOVSSrr VR128:$src1, FR32:$src2)>;
5653 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
5654 (MOVSSrr (v4i32 VR128:$src1),
5655 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
5656 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
5657 (MOVSSrr (v4f32 VR128:$src1),
5658 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
5659 // FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
5660 // is during lowering, where it's not possible to recognize the load fold cause
5661 // it has two uses through a bitcast. One use disappears at isel time and the
5662 // fold opportunity reappears.
5663 def : Pat<(X86Movss VR128:$src1,
5664 (bc_v4i32 (v2i64 (load addr:$src2)))),
5665 (MOVLPSrm VR128:$src1, addr:$src2)>;
5667 // Shuffle with MOVSD
5668 def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
5669 (MOVSDrr VR128:$src1, FR64:$src2)>;
5670 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
5671 (MOVSDrr (v2i64 VR128:$src1),
5672 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
5673 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
5674 (MOVSDrr (v2f64 VR128:$src1),
5675 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
5676 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
5677 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5678 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
5679 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5681 // Shuffle with MOVSHDUP
5682 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5683 (MOVSHDUPrr VR128:$src)>;
5684 def : Pat<(X86Movshdup (bc_v4i32 (memopv2i64 addr:$src))),
5685 (MOVSHDUPrm addr:$src)>;
5687 def : Pat<(v4f32 (X86Movshdup VR128:$src)),
5688 (MOVSHDUPrr VR128:$src)>;
5689 def : Pat<(X86Movshdup (memopv4f32 addr:$src)),
5690 (MOVSHDUPrm addr:$src)>;
5692 // Shuffle with MOVSLDUP
5693 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5694 (MOVSLDUPrr VR128:$src)>;
5695 def : Pat<(X86Movsldup (bc_v4i32 (memopv2i64 addr:$src))),
5696 (MOVSLDUPrm addr:$src)>;
5698 def : Pat<(v4f32 (X86Movsldup VR128:$src)),
5699 (MOVSLDUPrr VR128:$src)>;
5700 def : Pat<(X86Movsldup (memopv4f32 addr:$src)),
5701 (MOVSLDUPrm addr:$src)>;
5703 // Shuffle with PSHUFHW
5704 def : Pat<(v8i16 (X86PShufhw VR128:$src, (i8 imm:$imm))),
5705 (PSHUFHWri VR128:$src, imm:$imm)>;
5706 def : Pat<(v8i16 (X86PShufhw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5707 (PSHUFHWmi addr:$src, imm:$imm)>;
5709 // Shuffle with PSHUFLW
5710 def : Pat<(v8i16 (X86PShuflw VR128:$src, (i8 imm:$imm))),
5711 (PSHUFLWri VR128:$src, imm:$imm)>;
5712 def : Pat<(v8i16 (X86PShuflw (bc_v8i16 (memopv2i64 addr:$src)), (i8 imm:$imm))),
5713 (PSHUFLWmi addr:$src, imm:$imm)>;
5715 // Shuffle with PALIGN
5716 def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5717 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5718 def : Pat<(v4f32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5719 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5720 def : Pat<(v8i16 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5721 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5722 def : Pat<(v16i8 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5723 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5725 // Shuffle with MOVLPS
5726 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
5727 (MOVLPSrm VR128:$src1, addr:$src2)>;
5728 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
5729 (MOVLPSrm VR128:$src1, addr:$src2)>;
5730 def : Pat<(X86Movlps VR128:$src1,
5731 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
5732 (MOVLPSrm VR128:$src1, addr:$src2)>;
5733 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
5734 // is during lowering, where it's not possible to recognize the load fold cause
5735 // it has two uses through a bitcast. One use disappears at isel time and the
5736 // fold opportunity reappears.
5737 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
5738 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_sd))>;
5740 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
5741 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_sd))>;
5743 // Shuffle with MOVLPD
5744 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5745 (MOVLPDrm VR128:$src1, addr:$src2)>;
5746 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
5747 (MOVLPDrm VR128:$src1, addr:$src2)>;
5748 def : Pat<(v2f64 (X86Movlpd VR128:$src1,
5749 (scalar_to_vector (loadf64 addr:$src2)))),
5750 (MOVLPDrm VR128:$src1, addr:$src2)>;
5752 // Extra patterns to match stores with MOVHPS/PD and MOVLPS/PD
5753 def : Pat<(store (f64 (vector_extract
5754 (v2f64 (X86Unpckhps VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5755 (MOVHPSmr addr:$dst, VR128:$src)>;
5756 def : Pat<(store (f64 (vector_extract
5757 (v2f64 (X86Unpckhpd VR128:$src, (undef))), (iPTR 0))),addr:$dst),
5758 (MOVHPDmr addr:$dst, VR128:$src)>;
5760 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),addr:$src1),
5761 (MOVLPSmr addr:$src1, VR128:$src2)>;
5762 def : Pat<(store (v4i32 (X86Movlps
5763 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
5764 (MOVLPSmr addr:$src1, VR128:$src2)>;
5766 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5767 (MOVLPDmr addr:$src1, VR128:$src2)>;
5768 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),addr:$src1),
5769 (MOVLPDmr addr:$src1, VR128:$src2)>;