1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Move Instructions. Register-to-register movss is not used for FR32
375 // register copies because it's a partial register update; FsMOVAPSrr is
376 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
377 // because INSERT_SUBREG requires that the insert be implementable in terms of
378 // a copy, and just mentioned, we don't use movss for copies.
379 let Constraints = "$src1 = $dst" in
380 def MOVSSrr : SSI<0x10, MRMSrcReg,
381 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
382 "movss\t{$src2, $dst|$dst, $src2}",
383 [(set (v4f32 VR128:$dst),
384 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
386 // Extract the low 32-bit value from one vector and insert it into another.
387 let AddedComplexity = 15 in
388 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
389 (MOVSSrr (v4f32 VR128:$src1),
390 (EXTRACT_SUBREG (v4f32 VR128:$src2), x86_subreg_ss))>;
392 // Implicitly promote a 32-bit scalar to a vector.
393 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
394 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, x86_subreg_ss)>;
396 // Loading from memory automatically zeroing upper bits.
397 let canFoldAsLoad = 1, isReMaterializable = 1 in
398 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
399 "movss\t{$src, $dst|$dst, $src}",
400 [(set FR32:$dst, (loadf32 addr:$src))]>;
402 // MOVSSrm zeros the high parts of the register; represent this
403 // with SUBREG_TO_REG.
404 let AddedComplexity = 20 in {
405 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
406 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
407 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
408 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
409 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
410 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), x86_subreg_ss)>;
413 // Store scalar value to memory.
414 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
415 "movss\t{$src, $dst|$dst, $src}",
416 [(store FR32:$src, addr:$dst)]>;
418 // Extract and store.
419 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
422 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
424 // Conversion instructions
425 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
426 "cvttss2si\t{$src, $dst|$dst, $src}",
427 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
428 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
429 "cvttss2si\t{$src, $dst|$dst, $src}",
430 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
431 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
432 "cvtsi2ss\t{$src, $dst|$dst, $src}",
433 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
434 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
435 "cvtsi2ss\t{$src, $dst|$dst, $src}",
436 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
438 // Match intrinsics which expect XMM operand(s).
439 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
440 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
441 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
442 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
444 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
445 "cvtss2si\t{$src, $dst|$dst, $src}",
446 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
447 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (int_x86_sse_cvtss2si
450 (load addr:$src)))]>;
452 // Match intrinisics which expect MM and XMM operand(s).
453 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
454 "cvtps2pi\t{$src, $dst|$dst, $src}",
455 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
456 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
457 "cvtps2pi\t{$src, $dst|$dst, $src}",
458 [(set VR64:$dst, (int_x86_sse_cvtps2pi
459 (load addr:$src)))]>;
460 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttps2pi\t{$src, $dst|$dst, $src}",
462 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
463 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
464 "cvttps2pi\t{$src, $dst|$dst, $src}",
465 [(set VR64:$dst, (int_x86_sse_cvttps2pi
466 (load addr:$src)))]>;
467 let Constraints = "$src1 = $dst" in {
468 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
469 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
470 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
471 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
473 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
474 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
477 (load addr:$src2)))]>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
505 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
506 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
509 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
510 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
514 let Defs = [EFLAGS] in {
515 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
516 "ucomiss\t{$src2, $src1|$src1, $src2}",
517 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
518 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
519 "ucomiss\t{$src2, $src1|$src1, $src2}",
520 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
522 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
523 "comiss\t{$src2, $src1|$src1, $src2}", []>;
524 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
525 "comiss\t{$src2, $src1|$src1, $src2}", []>;
529 // Aliases to match intrinsics which expect XMM operand(s).
530 let Constraints = "$src1 = $dst" in {
531 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
533 (ins VR128:$src1, VR128:$src, SSECC:$cc),
534 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
535 [(set VR128:$dst, (int_x86_sse_cmp_ss
537 VR128:$src, imm:$cc))]>;
538 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
540 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
541 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
542 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
543 (load addr:$src), imm:$cc))]>;
546 let Defs = [EFLAGS] in {
547 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
548 "ucomiss\t{$src2, $src1|$src1, $src2}",
549 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
551 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
552 "ucomiss\t{$src2, $src1|$src1, $src2}",
553 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
554 (load addr:$src2)))]>;
556 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
557 "comiss\t{$src2, $src1|$src1, $src2}",
558 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
560 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
561 "comiss\t{$src2, $src1|$src1, $src2}",
562 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
563 (load addr:$src2)))]>;
566 // Aliases of packed SSE1 instructions for scalar use. These all have names
567 // that start with 'Fs'.
569 // Alias instructions that map fld0 to pxor for sse.
570 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
572 // FIXME: Set encoding to pseudo!
573 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
574 [(set FR32:$dst, fp32imm0)]>,
575 Requires<[HasSSE1]>, TB, OpSize;
577 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
579 let neverHasSideEffects = 1 in
580 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
581 "movaps\t{$src, $dst|$dst, $src}", []>;
583 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
585 let canFoldAsLoad = 1, isReMaterializable = 1 in
586 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
587 "movaps\t{$src, $dst|$dst, $src}",
588 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
590 // Alias bitwise logical operations using SSE logical ops on packed FP values.
591 let Constraints = "$src1 = $dst" in {
592 let isCommutable = 1 in {
593 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst),
594 (ins FR32:$src1, FR32:$src2),
595 "andps\t{$src2, $dst|$dst, $src2}",
596 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
597 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst),
598 (ins FR32:$src1, FR32:$src2),
599 "orps\t{$src2, $dst|$dst, $src2}",
600 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
601 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst),
602 (ins FR32:$src1, FR32:$src2),
603 "xorps\t{$src2, $dst|$dst, $src2}",
604 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
607 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst),
608 (ins FR32:$src1, f128mem:$src2),
609 "andps\t{$src2, $dst|$dst, $src2}",
610 [(set FR32:$dst, (X86fand FR32:$src1,
611 (memopfsf32 addr:$src2)))]>;
612 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst),
613 (ins FR32:$src1, f128mem:$src2),
614 "orps\t{$src2, $dst|$dst, $src2}",
615 [(set FR32:$dst, (X86for FR32:$src1,
616 (memopfsf32 addr:$src2)))]>;
617 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst),
618 (ins FR32:$src1, f128mem:$src2),
619 "xorps\t{$src2, $dst|$dst, $src2}",
620 [(set FR32:$dst, (X86fxor FR32:$src1,
621 (memopfsf32 addr:$src2)))]>;
623 let neverHasSideEffects = 1 in {
624 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
625 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
626 "andnps\t{$src2, $dst|$dst, $src2}", []>;
628 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
629 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
630 "andnps\t{$src2, $dst|$dst, $src2}", []>;
634 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
636 /// In addition, we also have a special variant of the scalar form here to
637 /// represent the associated intrinsic operation. This form is unlike the
638 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
639 /// and leaves the top elements unmodified (therefore these cannot be commuted).
641 /// These three forms can each be reg+reg or reg+mem, so there are a total of
642 /// six "instructions".
644 let Constraints = "$src1 = $dst" in {
645 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
646 SDNode OpNode, Intrinsic F32Int,
647 bit Commutable = 0> {
648 // Scalar operation, reg+reg.
649 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
650 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
651 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
652 let isCommutable = Commutable;
655 // Scalar operation, reg+mem.
656 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
657 (ins FR32:$src1, f32mem:$src2),
658 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
659 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
661 // Vector operation, reg+reg.
662 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
663 (ins VR128:$src1, VR128:$src2),
664 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
665 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
666 let isCommutable = Commutable;
669 // Vector operation, reg+mem.
670 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
671 (ins VR128:$src1, f128mem:$src2),
672 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
673 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
675 // Intrinsic operation, reg+reg.
676 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
677 (ins VR128:$src1, VR128:$src2),
678 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
679 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]>;
681 // Intrinsic operation, reg+mem.
682 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
683 (ins VR128:$src1, ssmem:$src2),
684 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
685 [(set VR128:$dst, (F32Int VR128:$src1,
686 sse_load_f32:$src2))]>;
690 // Arithmetic instructions
691 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
692 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
693 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
694 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
696 /// sse1_fp_binop_rm - Other SSE1 binops
698 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
699 /// instructions for a full-vector intrinsic form. Operations that map
700 /// onto C operators don't use this form since they just use the plain
701 /// vector form instead of having a separate vector intrinsic form.
703 /// This provides a total of eight "instructions".
705 let Constraints = "$src1 = $dst" in {
706 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
710 bit Commutable = 0> {
712 // Scalar operation, reg+reg.
713 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
714 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
715 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
716 let isCommutable = Commutable;
719 // Scalar operation, reg+mem.
720 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
721 (ins FR32:$src1, f32mem:$src2),
722 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
723 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
725 // Vector operation, reg+reg.
726 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
727 (ins VR128:$src1, VR128:$src2),
728 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
729 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
730 let isCommutable = Commutable;
733 // Vector operation, reg+mem.
734 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
735 (ins VR128:$src1, f128mem:$src2),
736 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
737 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
739 // Intrinsic operation, reg+reg.
740 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
741 (ins VR128:$src1, VR128:$src2),
742 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
743 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
744 let isCommutable = Commutable;
747 // Intrinsic operation, reg+mem.
748 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
749 (ins VR128:$src1, ssmem:$src2),
750 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
751 [(set VR128:$dst, (F32Int VR128:$src1,
752 sse_load_f32:$src2))]>;
754 // Vector intrinsic operation, reg+reg.
755 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
756 (ins VR128:$src1, VR128:$src2),
757 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
758 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
759 let isCommutable = Commutable;
762 // Vector intrinsic operation, reg+mem.
763 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
764 (ins VR128:$src1, f128mem:$src2),
765 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
766 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
770 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
771 int_x86_sse_max_ss, int_x86_sse_max_ps>;
772 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
773 int_x86_sse_min_ss, int_x86_sse_min_ps>;
775 //===----------------------------------------------------------------------===//
776 // SSE packed FP Instructions
779 let neverHasSideEffects = 1 in
780 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
781 "movaps\t{$src, $dst|$dst, $src}", []>;
782 let canFoldAsLoad = 1, isReMaterializable = 1 in
783 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
784 "movaps\t{$src, $dst|$dst, $src}",
785 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
787 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
788 "movaps\t{$src, $dst|$dst, $src}",
789 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
791 let neverHasSideEffects = 1 in
792 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
793 "movups\t{$src, $dst|$dst, $src}", []>;
794 let canFoldAsLoad = 1, isReMaterializable = 1 in
795 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
796 "movups\t{$src, $dst|$dst, $src}",
797 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
798 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
799 "movups\t{$src, $dst|$dst, $src}",
800 [(store (v4f32 VR128:$src), addr:$dst)]>;
802 // Intrinsic forms of MOVUPS load and store
803 let canFoldAsLoad = 1, isReMaterializable = 1 in
804 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
805 "movups\t{$src, $dst|$dst, $src}",
806 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
807 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
808 "movups\t{$src, $dst|$dst, $src}",
809 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
811 let Constraints = "$src1 = $dst" in {
812 let AddedComplexity = 20 in {
813 def MOVLPSrm : PSI<0x12, MRMSrcMem,
814 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
815 "movlps\t{$src2, $dst|$dst, $src2}",
818 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
819 def MOVHPSrm : PSI<0x16, MRMSrcMem,
820 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
821 "movhps\t{$src2, $dst|$dst, $src2}",
823 (movlhps VR128:$src1,
824 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
826 } // Constraints = "$src1 = $dst"
829 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
830 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
832 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
833 "movlps\t{$src, $dst|$dst, $src}",
834 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
835 (iPTR 0))), addr:$dst)]>;
837 // v2f64 extract element 1 is always custom lowered to unpack high to low
838 // and extract element 0 so the non-store version isn't too horrible.
839 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
840 "movhps\t{$src, $dst|$dst, $src}",
841 [(store (f64 (vector_extract
842 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
843 (undef)), (iPTR 0))), addr:$dst)]>;
845 let Constraints = "$src1 = $dst" in {
846 let AddedComplexity = 20 in {
847 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
848 (ins VR128:$src1, VR128:$src2),
849 "movlhps\t{$src2, $dst|$dst, $src2}",
851 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
853 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
854 (ins VR128:$src1, VR128:$src2),
855 "movhlps\t{$src2, $dst|$dst, $src2}",
857 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
859 } // Constraints = "$src1 = $dst"
861 let AddedComplexity = 20 in {
862 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
863 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
864 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
865 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
872 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
874 /// In addition, we also have a special variant of the scalar form here to
875 /// represent the associated intrinsic operation. This form is unlike the
876 /// plain scalar form, in that it takes an entire vector (instead of a
877 /// scalar) and leaves the top elements undefined.
879 /// And, we have a special variant form for a full-vector intrinsic form.
881 /// These four forms can each have a reg or a mem operand, so there are a
882 /// total of eight "instructions".
884 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
888 bit Commutable = 0> {
889 // Scalar operation, reg.
890 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
891 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
892 [(set FR32:$dst, (OpNode FR32:$src))]> {
893 let isCommutable = Commutable;
896 // Scalar operation, mem.
897 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
898 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
899 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
900 Requires<[HasSSE1, OptForSize]>;
902 // Vector operation, reg.
903 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
904 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
905 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
906 let isCommutable = Commutable;
909 // Vector operation, mem.
910 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
911 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
912 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
914 // Intrinsic operation, reg.
915 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
916 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
917 [(set VR128:$dst, (F32Int VR128:$src))]> {
918 let isCommutable = Commutable;
921 // Intrinsic operation, mem.
922 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
923 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
924 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
926 // Vector intrinsic operation, reg
927 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
928 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
929 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
930 let isCommutable = Commutable;
933 // Vector intrinsic operation, mem
934 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
935 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
936 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
940 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
941 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
943 // Reciprocal approximations. Note that these typically require refinement
944 // in order to obtain suitable precision.
945 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
946 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
947 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
948 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
951 let Constraints = "$src1 = $dst" in {
952 let isCommutable = 1 in {
953 def ANDPSrr : PSI<0x54, MRMSrcReg,
954 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
955 "andps\t{$src2, $dst|$dst, $src2}",
956 [(set VR128:$dst, (v2i64
957 (and VR128:$src1, VR128:$src2)))]>;
958 def ORPSrr : PSI<0x56, MRMSrcReg,
959 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
960 "orps\t{$src2, $dst|$dst, $src2}",
961 [(set VR128:$dst, (v2i64
962 (or VR128:$src1, VR128:$src2)))]>;
963 def XORPSrr : PSI<0x57, MRMSrcReg,
964 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
965 "xorps\t{$src2, $dst|$dst, $src2}",
966 [(set VR128:$dst, (v2i64
967 (xor VR128:$src1, VR128:$src2)))]>;
970 def ANDPSrm : PSI<0x54, MRMSrcMem,
971 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
972 "andps\t{$src2, $dst|$dst, $src2}",
973 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
974 (memopv2i64 addr:$src2)))]>;
975 def ORPSrm : PSI<0x56, MRMSrcMem,
976 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
977 "orps\t{$src2, $dst|$dst, $src2}",
978 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
979 (memopv2i64 addr:$src2)))]>;
980 def XORPSrm : PSI<0x57, MRMSrcMem,
981 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
982 "xorps\t{$src2, $dst|$dst, $src2}",
983 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
984 (memopv2i64 addr:$src2)))]>;
985 def ANDNPSrr : PSI<0x55, MRMSrcReg,
986 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
987 "andnps\t{$src2, $dst|$dst, $src2}",
989 (v2i64 (and (xor VR128:$src1,
990 (bc_v2i64 (v4i32 immAllOnesV))),
992 def ANDNPSrm : PSI<0x55, MRMSrcMem,
993 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
994 "andnps\t{$src2, $dst|$dst, $src2}",
996 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
997 (bc_v2i64 (v4i32 immAllOnesV))),
998 (memopv2i64 addr:$src2))))]>;
1001 let Constraints = "$src1 = $dst" in {
1002 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1003 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1004 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1005 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1006 VR128:$src, imm:$cc))]>;
1007 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1008 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1009 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1010 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1011 (memop addr:$src), imm:$cc))]>;
1013 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1014 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1015 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1016 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1018 // Shuffle and unpack instructions
1019 let Constraints = "$src1 = $dst" in {
1020 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1021 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1022 (outs VR128:$dst), (ins VR128:$src1,
1023 VR128:$src2, i8imm:$src3),
1024 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1026 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1027 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1028 (outs VR128:$dst), (ins VR128:$src1,
1029 f128mem:$src2, i8imm:$src3),
1030 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1033 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1035 let AddedComplexity = 10 in {
1036 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1037 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1038 "unpckhps\t{$src2, $dst|$dst, $src2}",
1040 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1041 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1042 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1043 "unpckhps\t{$src2, $dst|$dst, $src2}",
1045 (v4f32 (unpckh VR128:$src1,
1046 (memopv4f32 addr:$src2))))]>;
1048 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1049 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1050 "unpcklps\t{$src2, $dst|$dst, $src2}",
1052 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1053 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1054 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1055 "unpcklps\t{$src2, $dst|$dst, $src2}",
1057 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1058 } // AddedComplexity
1059 } // Constraints = "$src1 = $dst"
1062 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1063 "movmskps\t{$src, $dst|$dst, $src}",
1064 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1065 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1066 "movmskpd\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1069 // Prefetch intrinsic.
1070 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1071 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1072 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1073 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1074 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1075 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1076 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1077 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1079 // Non-temporal stores
1080 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1081 "movntps\t{$src, $dst|$dst, $src}",
1082 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1084 let AddedComplexity = 400 in { // Prefer non-temporal versions
1085 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1086 "movntps\t{$src, $dst|$dst, $src}",
1087 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1089 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1090 "movntdq\t{$src, $dst|$dst, $src}",
1091 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1093 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1094 "movnti\t{$src, $dst|$dst, $src}",
1095 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1096 TB, Requires<[HasSSE2]>;
1098 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1099 "movnti\t{$src, $dst|$dst, $src}",
1100 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1101 TB, Requires<[HasSSE2]>;
1104 // Load, store, and memory fence
1105 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1106 TB, Requires<[HasSSE1]>;
1109 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1110 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1111 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1112 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1114 // Alias instructions that map zero vector to pxor / xorp* for sse.
1115 // We set canFoldAsLoad because this can be converted to a constant-pool
1116 // load of an all-zeros value if folding it would be beneficial.
1117 // FIXME: Change encoding to pseudo!
1118 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1119 isCodeGenOnly = 1 in {
1120 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1121 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1122 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1123 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1124 let ExeDomain = SSEPackedInt in
1125 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1126 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1129 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1130 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1131 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1133 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1134 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss))>;
1136 //===---------------------------------------------------------------------===//
1137 // SSE2 Instructions
1138 //===---------------------------------------------------------------------===//
1140 // Move Instructions. Register-to-register movsd is not used for FR64
1141 // register copies because it's a partial register update; FsMOVAPDrr is
1142 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1143 // because INSERT_SUBREG requires that the insert be implementable in terms of
1144 // a copy, and just mentioned, we don't use movsd for copies.
1145 let Constraints = "$src1 = $dst" in
1146 def MOVSDrr : SDI<0x10, MRMSrcReg,
1147 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1148 "movsd\t{$src2, $dst|$dst, $src2}",
1149 [(set (v2f64 VR128:$dst),
1150 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1152 // Extract the low 64-bit value from one vector and insert it into another.
1153 let AddedComplexity = 15 in
1154 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1155 (MOVSDrr (v2f64 VR128:$src1),
1156 (EXTRACT_SUBREG (v2f64 VR128:$src2), x86_subreg_sd))>;
1158 // Implicitly promote a 64-bit scalar to a vector.
1159 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1160 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, x86_subreg_sd)>;
1162 // Loading from memory automatically zeroing upper bits.
1163 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1164 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1165 "movsd\t{$src, $dst|$dst, $src}",
1166 [(set FR64:$dst, (loadf64 addr:$src))]>;
1168 // MOVSDrm zeros the high parts of the register; represent this
1169 // with SUBREG_TO_REG.
1170 let AddedComplexity = 20 in {
1171 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1172 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1173 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1174 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1175 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1176 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1177 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1178 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1179 def : Pat<(v2f64 (X86vzload addr:$src)),
1180 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), x86_subreg_sd)>;
1183 // Store scalar value to memory.
1184 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1185 "movsd\t{$src, $dst|$dst, $src}",
1186 [(store FR64:$src, addr:$dst)]>;
1188 // Extract and store.
1189 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1192 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
1194 // Conversion instructions
1195 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1196 "cvttsd2si\t{$src, $dst|$dst, $src}",
1197 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1198 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1199 "cvttsd2si\t{$src, $dst|$dst, $src}",
1200 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1201 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1202 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1203 [(set FR32:$dst, (fround FR64:$src))]>;
1204 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1205 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1206 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1207 Requires<[HasSSE2, OptForSize]>;
1208 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1209 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1210 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1211 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1212 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1213 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1215 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1216 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1217 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1218 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1219 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1220 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1221 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1222 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1223 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1224 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1225 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1226 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1227 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1228 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1229 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1230 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1231 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1232 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1233 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1234 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1236 // SSE2 instructions with XS prefix
1237 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1238 "cvtss2sd\t{$src, $dst|$dst, $src}",
1239 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1240 Requires<[HasSSE2]>;
1241 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1242 "cvtss2sd\t{$src, $dst|$dst, $src}",
1243 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1244 Requires<[HasSSE2, OptForSize]>;
1246 def : Pat<(extloadf32 addr:$src),
1247 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1248 Requires<[HasSSE2, OptForSpeed]>;
1250 // Match intrinsics which expect XMM operand(s).
1251 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1252 "cvtsd2si\t{$src, $dst|$dst, $src}",
1253 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1254 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1255 "cvtsd2si\t{$src, $dst|$dst, $src}",
1256 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1257 (load addr:$src)))]>;
1259 // Match intrinisics which expect MM and XMM operand(s).
1260 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1261 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1262 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1263 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1264 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1265 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1266 (memop addr:$src)))]>;
1267 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1268 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1269 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1270 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1271 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1272 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1273 (memop addr:$src)))]>;
1274 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1275 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1276 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1277 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1278 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1279 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1280 (load addr:$src)))]>;
1282 // Aliases for intrinsics
1283 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1284 "cvttsd2si\t{$src, $dst|$dst, $src}",
1286 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1287 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1288 "cvttsd2si\t{$src, $dst|$dst, $src}",
1289 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1290 (load addr:$src)))]>;
1292 // Comparison instructions
1293 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1294 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1295 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1296 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1298 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1299 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1300 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1303 let Defs = [EFLAGS] in {
1304 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1305 "ucomisd\t{$src2, $src1|$src1, $src2}",
1306 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1307 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1308 "ucomisd\t{$src2, $src1|$src1, $src2}",
1309 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1310 } // Defs = [EFLAGS]
1312 // Aliases to match intrinsics which expect XMM operand(s).
1313 let Constraints = "$src1 = $dst" in {
1314 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1316 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1317 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1318 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1319 VR128:$src, imm:$cc))]>;
1320 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1322 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1323 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1324 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1325 (load addr:$src), imm:$cc))]>;
1328 let Defs = [EFLAGS] in {
1329 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1330 "ucomisd\t{$src2, $src1|$src1, $src2}",
1331 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1333 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1334 "ucomisd\t{$src2, $src1|$src1, $src2}",
1335 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1336 (load addr:$src2)))]>;
1338 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1339 "comisd\t{$src2, $src1|$src1, $src2}",
1340 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1342 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1343 "comisd\t{$src2, $src1|$src1, $src2}",
1344 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1345 (load addr:$src2)))]>;
1346 } // Defs = [EFLAGS]
1348 // Aliases of packed SSE2 instructions for scalar use. These all have names
1349 // that start with 'Fs'.
1351 // Alias instructions that map fld0 to pxor for sse.
1352 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1353 canFoldAsLoad = 1 in
1354 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1355 [(set FR64:$dst, fpimm0)]>,
1356 Requires<[HasSSE2]>, TB, OpSize;
1358 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1360 let neverHasSideEffects = 1 in
1361 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1362 "movapd\t{$src, $dst|$dst, $src}", []>;
1364 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1366 let canFoldAsLoad = 1, isReMaterializable = 1 in
1367 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1368 "movapd\t{$src, $dst|$dst, $src}",
1369 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1371 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1372 let Constraints = "$src1 = $dst" in {
1373 let isCommutable = 1 in {
1374 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1375 (ins FR64:$src1, FR64:$src2),
1376 "andpd\t{$src2, $dst|$dst, $src2}",
1377 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1378 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1379 (ins FR64:$src1, FR64:$src2),
1380 "orpd\t{$src2, $dst|$dst, $src2}",
1381 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1382 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1383 (ins FR64:$src1, FR64:$src2),
1384 "xorpd\t{$src2, $dst|$dst, $src2}",
1385 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1388 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1389 (ins FR64:$src1, f128mem:$src2),
1390 "andpd\t{$src2, $dst|$dst, $src2}",
1391 [(set FR64:$dst, (X86fand FR64:$src1,
1392 (memopfsf64 addr:$src2)))]>;
1393 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1394 (ins FR64:$src1, f128mem:$src2),
1395 "orpd\t{$src2, $dst|$dst, $src2}",
1396 [(set FR64:$dst, (X86for FR64:$src1,
1397 (memopfsf64 addr:$src2)))]>;
1398 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1399 (ins FR64:$src1, f128mem:$src2),
1400 "xorpd\t{$src2, $dst|$dst, $src2}",
1401 [(set FR64:$dst, (X86fxor FR64:$src1,
1402 (memopfsf64 addr:$src2)))]>;
1404 let neverHasSideEffects = 1 in {
1405 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1406 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1407 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1409 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1410 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1411 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1415 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1417 /// In addition, we also have a special variant of the scalar form here to
1418 /// represent the associated intrinsic operation. This form is unlike the
1419 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1420 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1422 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1423 /// six "instructions".
1425 let Constraints = "$src1 = $dst" in {
1426 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1427 SDNode OpNode, Intrinsic F64Int,
1428 bit Commutable = 0> {
1429 // Scalar operation, reg+reg.
1430 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1431 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1432 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1433 let isCommutable = Commutable;
1436 // Scalar operation, reg+mem.
1437 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1438 (ins FR64:$src1, f64mem:$src2),
1439 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1440 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1442 // Vector operation, reg+reg.
1443 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1444 (ins VR128:$src1, VR128:$src2),
1445 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1446 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1447 let isCommutable = Commutable;
1450 // Vector operation, reg+mem.
1451 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1452 (ins VR128:$src1, f128mem:$src2),
1453 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1454 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1456 // Intrinsic operation, reg+reg.
1457 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1458 (ins VR128:$src1, VR128:$src2),
1459 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1460 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]>;
1462 // Intrinsic operation, reg+mem.
1463 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1464 (ins VR128:$src1, sdmem:$src2),
1465 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1466 [(set VR128:$dst, (F64Int VR128:$src1,
1467 sse_load_f64:$src2))]>;
1471 // Arithmetic instructions
1472 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1473 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1474 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1475 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1477 /// sse2_fp_binop_rm - Other SSE2 binops
1479 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1480 /// instructions for a full-vector intrinsic form. Operations that map
1481 /// onto C operators don't use this form since they just use the plain
1482 /// vector form instead of having a separate vector intrinsic form.
1484 /// This provides a total of eight "instructions".
1486 let Constraints = "$src1 = $dst" in {
1487 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1491 bit Commutable = 0> {
1493 // Scalar operation, reg+reg.
1494 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1495 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1496 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1497 let isCommutable = Commutable;
1500 // Scalar operation, reg+mem.
1501 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1502 (ins FR64:$src1, f64mem:$src2),
1503 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1504 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1506 // Vector operation, reg+reg.
1507 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1508 (ins VR128:$src1, VR128:$src2),
1509 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1510 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1511 let isCommutable = Commutable;
1514 // Vector operation, reg+mem.
1515 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1516 (ins VR128:$src1, f128mem:$src2),
1517 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1518 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1520 // Intrinsic operation, reg+reg.
1521 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1522 (ins VR128:$src1, VR128:$src2),
1523 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1524 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1525 let isCommutable = Commutable;
1528 // Intrinsic operation, reg+mem.
1529 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1530 (ins VR128:$src1, sdmem:$src2),
1531 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1532 [(set VR128:$dst, (F64Int VR128:$src1,
1533 sse_load_f64:$src2))]>;
1535 // Vector intrinsic operation, reg+reg.
1536 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1537 (ins VR128:$src1, VR128:$src2),
1538 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1539 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1540 let isCommutable = Commutable;
1543 // Vector intrinsic operation, reg+mem.
1544 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1545 (ins VR128:$src1, f128mem:$src2),
1546 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1547 [(set VR128:$dst, (V2F64Int VR128:$src1,
1548 (memopv2f64 addr:$src2)))]>;
1552 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1553 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1554 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1555 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1557 //===---------------------------------------------------------------------===//
1558 // SSE packed FP Instructions
1560 // Move Instructions
1561 let neverHasSideEffects = 1 in
1562 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1563 "movapd\t{$src, $dst|$dst, $src}", []>;
1564 let canFoldAsLoad = 1, isReMaterializable = 1 in
1565 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1566 "movapd\t{$src, $dst|$dst, $src}",
1567 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1569 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1570 "movapd\t{$src, $dst|$dst, $src}",
1571 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1573 let neverHasSideEffects = 1 in
1574 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1575 "movupd\t{$src, $dst|$dst, $src}", []>;
1576 let canFoldAsLoad = 1 in
1577 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1578 "movupd\t{$src, $dst|$dst, $src}",
1579 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1580 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1581 "movupd\t{$src, $dst|$dst, $src}",
1582 [(store (v2f64 VR128:$src), addr:$dst)]>;
1584 // Intrinsic forms of MOVUPD load and store
1585 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1586 "movupd\t{$src, $dst|$dst, $src}",
1587 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1588 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1589 "movupd\t{$src, $dst|$dst, $src}",
1590 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1592 let Constraints = "$src1 = $dst" in {
1593 let AddedComplexity = 20 in {
1594 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1595 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1596 "movlpd\t{$src2, $dst|$dst, $src2}",
1598 (v2f64 (movlp VR128:$src1,
1599 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1600 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1601 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1602 "movhpd\t{$src2, $dst|$dst, $src2}",
1604 (v2f64 (movlhps VR128:$src1,
1605 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1606 } // AddedComplexity
1607 } // Constraints = "$src1 = $dst"
1609 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1610 "movlpd\t{$src, $dst|$dst, $src}",
1611 [(store (f64 (vector_extract (v2f64 VR128:$src),
1612 (iPTR 0))), addr:$dst)]>;
1614 // v2f64 extract element 1 is always custom lowered to unpack high to low
1615 // and extract element 0 so the non-store version isn't too horrible.
1616 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1617 "movhpd\t{$src, $dst|$dst, $src}",
1618 [(store (f64 (vector_extract
1619 (v2f64 (unpckh VR128:$src, (undef))),
1620 (iPTR 0))), addr:$dst)]>;
1622 // SSE2 instructions without OpSize prefix
1623 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1624 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1625 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1626 TB, Requires<[HasSSE2]>;
1627 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1628 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1629 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1630 (bitconvert (memopv2i64 addr:$src))))]>,
1631 TB, Requires<[HasSSE2]>;
1633 // SSE2 instructions with XS prefix
1634 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1635 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1636 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1637 XS, Requires<[HasSSE2]>;
1638 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1639 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1640 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1641 (bitconvert (memopv2i64 addr:$src))))]>,
1642 XS, Requires<[HasSSE2]>;
1644 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1645 "cvtps2dq\t{$src, $dst|$dst, $src}",
1646 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1647 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1648 "cvtps2dq\t{$src, $dst|$dst, $src}",
1649 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1650 (memop addr:$src)))]>;
1651 // SSE2 packed instructions with XS prefix
1652 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1653 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1654 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1655 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1657 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1658 "cvttps2dq\t{$src, $dst|$dst, $src}",
1660 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1661 XS, Requires<[HasSSE2]>;
1662 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1663 "cvttps2dq\t{$src, $dst|$dst, $src}",
1664 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1665 (memop addr:$src)))]>,
1666 XS, Requires<[HasSSE2]>;
1668 // SSE2 packed instructions with XD prefix
1669 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1670 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1671 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1672 XD, Requires<[HasSSE2]>;
1673 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1674 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1675 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1676 (memop addr:$src)))]>,
1677 XD, Requires<[HasSSE2]>;
1679 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1680 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1681 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1682 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1683 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1684 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1685 (memop addr:$src)))]>;
1687 // SSE2 instructions without OpSize prefix
1688 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1689 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1690 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1691 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1693 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1694 "cvtps2pd\t{$src, $dst|$dst, $src}",
1695 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1696 TB, Requires<[HasSSE2]>;
1697 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1698 "cvtps2pd\t{$src, $dst|$dst, $src}",
1699 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1700 (load addr:$src)))]>,
1701 TB, Requires<[HasSSE2]>;
1703 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1704 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1705 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1706 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1709 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1710 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1711 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1712 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1713 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1714 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1715 (memop addr:$src)))]>;
1717 // Match intrinsics which expect XMM operand(s).
1718 // Aliases for intrinsics
1719 let Constraints = "$src1 = $dst" in {
1720 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1721 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1722 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1725 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1726 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1727 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1728 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1729 (loadi32 addr:$src2)))]>;
1730 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1731 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1732 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1733 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1735 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1736 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1737 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1738 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1739 (load addr:$src2)))]>;
1740 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1741 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1742 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1743 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1744 VR128:$src2))]>, XS,
1745 Requires<[HasSSE2]>;
1746 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1747 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1748 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1749 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1750 (load addr:$src2)))]>, XS,
1751 Requires<[HasSSE2]>;
1756 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1758 /// In addition, we also have a special variant of the scalar form here to
1759 /// represent the associated intrinsic operation. This form is unlike the
1760 /// plain scalar form, in that it takes an entire vector (instead of a
1761 /// scalar) and leaves the top elements undefined.
1763 /// And, we have a special variant form for a full-vector intrinsic form.
1765 /// These four forms can each have a reg or a mem operand, so there are a
1766 /// total of eight "instructions".
1768 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1772 bit Commutable = 0> {
1773 // Scalar operation, reg.
1774 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1775 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1776 [(set FR64:$dst, (OpNode FR64:$src))]> {
1777 let isCommutable = Commutable;
1780 // Scalar operation, mem.
1781 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1782 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1783 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1785 // Vector operation, reg.
1786 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1787 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1788 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1789 let isCommutable = Commutable;
1792 // Vector operation, mem.
1793 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1794 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1795 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1797 // Intrinsic operation, reg.
1798 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1799 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1800 [(set VR128:$dst, (F64Int VR128:$src))]> {
1801 let isCommutable = Commutable;
1804 // Intrinsic operation, mem.
1805 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1806 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1807 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1809 // Vector intrinsic operation, reg
1810 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1811 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1812 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1813 let isCommutable = Commutable;
1816 // Vector intrinsic operation, mem
1817 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1818 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1819 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1823 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1824 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1826 // There is no f64 version of the reciprocal approximation instructions.
1829 let Constraints = "$src1 = $dst" in {
1830 let isCommutable = 1 in {
1831 def ANDPDrr : PDI<0x54, MRMSrcReg,
1832 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1833 "andpd\t{$src2, $dst|$dst, $src2}",
1835 (and (bc_v2i64 (v2f64 VR128:$src1)),
1836 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1837 def ORPDrr : PDI<0x56, MRMSrcReg,
1838 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1839 "orpd\t{$src2, $dst|$dst, $src2}",
1841 (or (bc_v2i64 (v2f64 VR128:$src1)),
1842 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1843 def XORPDrr : PDI<0x57, MRMSrcReg,
1844 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1845 "xorpd\t{$src2, $dst|$dst, $src2}",
1847 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1848 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1851 def ANDPDrm : PDI<0x54, MRMSrcMem,
1852 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1853 "andpd\t{$src2, $dst|$dst, $src2}",
1855 (and (bc_v2i64 (v2f64 VR128:$src1)),
1856 (memopv2i64 addr:$src2)))]>;
1857 def ORPDrm : PDI<0x56, MRMSrcMem,
1858 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1859 "orpd\t{$src2, $dst|$dst, $src2}",
1861 (or (bc_v2i64 (v2f64 VR128:$src1)),
1862 (memopv2i64 addr:$src2)))]>;
1863 def XORPDrm : PDI<0x57, MRMSrcMem,
1864 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1865 "xorpd\t{$src2, $dst|$dst, $src2}",
1867 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1868 (memopv2i64 addr:$src2)))]>;
1869 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1870 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1871 "andnpd\t{$src2, $dst|$dst, $src2}",
1873 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1874 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1875 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1876 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1877 "andnpd\t{$src2, $dst|$dst, $src2}",
1879 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1880 (memopv2i64 addr:$src2)))]>;
1883 let Constraints = "$src1 = $dst" in {
1884 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1885 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1886 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1887 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1888 VR128:$src, imm:$cc))]>;
1889 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1890 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1891 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1892 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1893 (memop addr:$src), imm:$cc))]>;
1895 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1896 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1897 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1898 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1900 // Shuffle and unpack instructions
1901 let Constraints = "$src1 = $dst" in {
1902 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1903 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1904 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1906 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1907 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1908 (outs VR128:$dst), (ins VR128:$src1,
1909 f128mem:$src2, i8imm:$src3),
1910 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1913 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1915 let AddedComplexity = 10 in {
1916 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1917 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1918 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1920 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1921 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1922 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1923 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1925 (v2f64 (unpckh VR128:$src1,
1926 (memopv2f64 addr:$src2))))]>;
1928 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1929 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1930 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1932 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1933 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1934 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1935 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1937 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1938 } // AddedComplexity
1939 } // Constraints = "$src1 = $dst"
1942 //===---------------------------------------------------------------------===//
1943 // SSE integer instructions
1944 let ExeDomain = SSEPackedInt in {
1946 // Move Instructions
1947 let neverHasSideEffects = 1 in
1948 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1949 "movdqa\t{$src, $dst|$dst, $src}", []>;
1950 let canFoldAsLoad = 1, mayLoad = 1 in
1951 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1952 "movdqa\t{$src, $dst|$dst, $src}",
1953 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1955 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1956 "movdqa\t{$src, $dst|$dst, $src}",
1957 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1958 let canFoldAsLoad = 1, mayLoad = 1 in
1959 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1960 "movdqu\t{$src, $dst|$dst, $src}",
1961 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1962 XS, Requires<[HasSSE2]>;
1964 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1965 "movdqu\t{$src, $dst|$dst, $src}",
1966 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1967 XS, Requires<[HasSSE2]>;
1969 // Intrinsic forms of MOVDQU load and store
1970 let canFoldAsLoad = 1 in
1971 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1972 "movdqu\t{$src, $dst|$dst, $src}",
1973 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1974 XS, Requires<[HasSSE2]>;
1975 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1976 "movdqu\t{$src, $dst|$dst, $src}",
1977 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1978 XS, Requires<[HasSSE2]>;
1980 let Constraints = "$src1 = $dst" in {
1982 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1983 bit Commutable = 0> {
1984 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1985 (ins VR128:$src1, VR128:$src2),
1986 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1987 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1988 let isCommutable = Commutable;
1990 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1991 (ins VR128:$src1, i128mem:$src2),
1992 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1993 [(set VR128:$dst, (IntId VR128:$src1,
1994 (bitconvert (memopv2i64
1998 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2000 Intrinsic IntId, Intrinsic IntId2> {
2001 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2002 (ins VR128:$src1, VR128:$src2),
2003 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2004 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2005 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2006 (ins VR128:$src1, i128mem:$src2),
2007 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2008 [(set VR128:$dst, (IntId VR128:$src1,
2009 (bitconvert (memopv2i64 addr:$src2))))]>;
2010 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2011 (ins VR128:$src1, i32i8imm:$src2),
2012 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2013 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2016 /// PDI_binop_rm - Simple SSE2 binary operator.
2017 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2018 ValueType OpVT, bit Commutable = 0> {
2019 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2020 (ins VR128:$src1, VR128:$src2),
2021 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2022 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
2023 let isCommutable = Commutable;
2025 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2026 (ins VR128:$src1, i128mem:$src2),
2027 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2028 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2029 (bitconvert (memopv2i64 addr:$src2)))))]>;
2032 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2034 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2035 /// to collapse (bitconvert VT to VT) into its operand.
2037 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2038 bit Commutable = 0> {
2039 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2040 (ins VR128:$src1, VR128:$src2),
2041 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2042 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
2043 let isCommutable = Commutable;
2045 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2046 (ins VR128:$src1, i128mem:$src2),
2047 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2048 [(set VR128:$dst, (OpNode VR128:$src1,
2049 (memopv2i64 addr:$src2)))]>;
2052 } // Constraints = "$src1 = $dst"
2053 } // ExeDomain = SSEPackedInt
2055 // 128-bit Integer Arithmetic
2057 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2058 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2059 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2060 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2062 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2063 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2064 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2065 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2067 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2068 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2069 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2070 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2072 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2073 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2074 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2075 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2077 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2079 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2080 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2081 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2083 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2085 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2086 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2089 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2090 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2091 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2092 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2093 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2096 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2097 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2098 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2099 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2100 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2101 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2103 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2104 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2105 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2106 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2107 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2108 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2110 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2111 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2112 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2113 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2115 // 128-bit logical shifts.
2116 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2117 ExeDomain = SSEPackedInt in {
2118 def PSLLDQri : PDIi8<0x73, MRM7r,
2119 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2120 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2121 def PSRLDQri : PDIi8<0x73, MRM3r,
2122 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2123 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2124 // PSRADQri doesn't exist in SSE[1-3].
2127 let Predicates = [HasSSE2] in {
2128 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2129 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2130 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2131 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2132 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2133 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2134 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2135 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2136 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2137 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2139 // Shift up / down and insert zero's.
2140 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2141 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2142 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2143 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2147 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2148 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2149 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2151 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2152 def PANDNrr : PDI<0xDF, MRMSrcReg,
2153 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2154 "pandn\t{$src2, $dst|$dst, $src2}",
2155 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2158 def PANDNrm : PDI<0xDF, MRMSrcMem,
2159 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2160 "pandn\t{$src2, $dst|$dst, $src2}",
2161 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2162 (memopv2i64 addr:$src2))))]>;
2165 // SSE2 Integer comparison
2166 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2167 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2168 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2169 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2170 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2171 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2173 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2174 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2175 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2176 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2177 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2178 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2179 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2180 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2181 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2182 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2183 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2184 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2186 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2187 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2188 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2189 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2190 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2191 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2192 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2193 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2194 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2195 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2196 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2197 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2200 // Pack instructions
2201 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2202 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2203 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2205 let ExeDomain = SSEPackedInt in {
2207 // Shuffle and unpack instructions
2208 let AddedComplexity = 5 in {
2209 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2210 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2211 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2212 [(set VR128:$dst, (v4i32 (pshufd:$src2
2213 VR128:$src1, (undef))))]>;
2214 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2215 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2216 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2217 [(set VR128:$dst, (v4i32 (pshufd:$src2
2218 (bc_v4i32 (memopv2i64 addr:$src1)),
2222 // SSE2 with ImmT == Imm8 and XS prefix.
2223 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2224 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2225 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2226 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2228 XS, Requires<[HasSSE2]>;
2229 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2230 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2231 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2232 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2233 (bc_v8i16 (memopv2i64 addr:$src1)),
2235 XS, Requires<[HasSSE2]>;
2237 // SSE2 with ImmT == Imm8 and XD prefix.
2238 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2239 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2240 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2241 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2243 XD, Requires<[HasSSE2]>;
2244 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2245 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2246 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2247 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2248 (bc_v8i16 (memopv2i64 addr:$src1)),
2250 XD, Requires<[HasSSE2]>;
2253 let Constraints = "$src1 = $dst" in {
2254 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2255 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2256 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2258 (v16i8 (unpckl VR128:$src1, VR128:$src2)))]>;
2259 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2260 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2261 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2263 (unpckl VR128:$src1,
2264 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2265 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2266 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2267 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2269 (v8i16 (unpckl VR128:$src1, VR128:$src2)))]>;
2270 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2271 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2272 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2274 (unpckl VR128:$src1,
2275 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2276 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2277 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2278 "punpckldq\t{$src2, $dst|$dst, $src2}",
2280 (v4i32 (unpckl VR128:$src1, VR128:$src2)))]>;
2281 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2282 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2283 "punpckldq\t{$src2, $dst|$dst, $src2}",
2285 (unpckl VR128:$src1,
2286 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2287 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2288 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2289 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2291 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2292 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2293 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2294 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2296 (v2i64 (unpckl VR128:$src1,
2297 (memopv2i64 addr:$src2))))]>;
2299 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2300 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2301 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2303 (v16i8 (unpckh VR128:$src1, VR128:$src2)))]>;
2304 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2305 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2306 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2308 (unpckh VR128:$src1,
2309 (bc_v16i8 (memopv2i64 addr:$src2))))]>;
2310 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2311 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2312 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2314 (v8i16 (unpckh VR128:$src1, VR128:$src2)))]>;
2315 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2316 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2317 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2319 (unpckh VR128:$src1,
2320 (bc_v8i16 (memopv2i64 addr:$src2))))]>;
2321 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2322 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2323 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2325 (v4i32 (unpckh VR128:$src1, VR128:$src2)))]>;
2326 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2327 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2328 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2330 (unpckh VR128:$src1,
2331 (bc_v4i32 (memopv2i64 addr:$src2))))]>;
2332 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2333 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2334 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2336 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2337 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2338 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2339 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2341 (v2i64 (unpckh VR128:$src1,
2342 (memopv2i64 addr:$src2))))]>;
2346 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2347 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2348 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2349 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2351 let Constraints = "$src1 = $dst" in {
2352 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2353 (outs VR128:$dst), (ins VR128:$src1,
2354 GR32:$src2, i32i8imm:$src3),
2355 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2357 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2358 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2359 (outs VR128:$dst), (ins VR128:$src1,
2360 i16mem:$src2, i32i8imm:$src3),
2361 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2363 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2368 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2369 "pmovmskb\t{$src, $dst|$dst, $src}",
2370 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2372 // Conditional store
2374 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2375 "maskmovdqu\t{$mask, $src|$src, $mask}",
2376 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2379 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2380 "maskmovdqu\t{$mask, $src|$src, $mask}",
2381 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2383 } // ExeDomain = SSEPackedInt
2385 // Non-temporal stores
2386 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2387 "movntpd\t{$src, $dst|$dst, $src}",
2388 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2389 let ExeDomain = SSEPackedInt in
2390 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2391 "movntdq\t{$src, $dst|$dst, $src}",
2392 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2393 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2394 "movnti\t{$src, $dst|$dst, $src}",
2395 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2396 TB, Requires<[HasSSE2]>;
2398 let AddedComplexity = 400 in { // Prefer non-temporal versions
2399 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2400 "movntpd\t{$src, $dst|$dst, $src}",
2401 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2403 let ExeDomain = SSEPackedInt in
2404 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2405 "movntdq\t{$src, $dst|$dst, $src}",
2406 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2410 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2411 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2412 TB, Requires<[HasSSE2]>;
2414 // Load, store, and memory fence
2415 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2416 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2417 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2418 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2420 //TODO: custom lower this so as to never even generate the noop
2421 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2423 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2424 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2425 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2428 // Alias instructions that map zero vector to pxor / xorp* for sse.
2429 // We set canFoldAsLoad because this can be converted to a constant-pool
2430 // load of an all-ones value if folding it would be beneficial.
2431 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2432 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2433 // FIXME: Change encoding to pseudo.
2434 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2435 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2437 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2438 "movd\t{$src, $dst|$dst, $src}",
2440 (v4i32 (scalar_to_vector GR32:$src)))]>;
2441 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2442 "movd\t{$src, $dst|$dst, $src}",
2444 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2446 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2447 "movd\t{$src, $dst|$dst, $src}",
2448 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2450 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2451 "movd\t{$src, $dst|$dst, $src}",
2452 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2454 // SSE2 instructions with XS prefix
2455 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2456 "movq\t{$src, $dst|$dst, $src}",
2458 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2459 Requires<[HasSSE2]>;
2460 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2461 "movq\t{$src, $dst|$dst, $src}",
2462 [(store (i64 (vector_extract (v2i64 VR128:$src),
2463 (iPTR 0))), addr:$dst)]>;
2465 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2466 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), x86_subreg_sd))>;
2468 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2469 "movd\t{$src, $dst|$dst, $src}",
2470 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2472 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2473 "movd\t{$src, $dst|$dst, $src}",
2474 [(store (i32 (vector_extract (v4i32 VR128:$src),
2475 (iPTR 0))), addr:$dst)]>;
2477 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2478 "movd\t{$src, $dst|$dst, $src}",
2479 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2480 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2481 "movd\t{$src, $dst|$dst, $src}",
2482 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2484 // Store / copy lower 64-bits of a XMM register.
2485 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2486 "movq\t{$src, $dst|$dst, $src}",
2487 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2489 // movd / movq to XMM register zero-extends
2490 let AddedComplexity = 15 in {
2491 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2492 "movd\t{$src, $dst|$dst, $src}",
2493 [(set VR128:$dst, (v4i32 (X86vzmovl
2494 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2495 // This is X86-64 only.
2496 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2497 "mov{d|q}\t{$src, $dst|$dst, $src}",
2498 [(set VR128:$dst, (v2i64 (X86vzmovl
2499 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2502 let AddedComplexity = 20 in {
2503 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2504 "movd\t{$src, $dst|$dst, $src}",
2506 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2507 (loadi32 addr:$src))))))]>;
2509 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2510 (MOVZDI2PDIrm addr:$src)>;
2511 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2512 (MOVZDI2PDIrm addr:$src)>;
2513 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2514 (MOVZDI2PDIrm addr:$src)>;
2516 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2517 "movq\t{$src, $dst|$dst, $src}",
2519 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2520 (loadi64 addr:$src))))))]>, XS,
2521 Requires<[HasSSE2]>;
2523 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2524 (MOVZQI2PQIrm addr:$src)>;
2525 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2526 (MOVZQI2PQIrm addr:$src)>;
2527 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2530 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2531 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2532 let AddedComplexity = 15 in
2533 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2534 "movq\t{$src, $dst|$dst, $src}",
2535 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2536 XS, Requires<[HasSSE2]>;
2538 let AddedComplexity = 20 in {
2539 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2540 "movq\t{$src, $dst|$dst, $src}",
2541 [(set VR128:$dst, (v2i64 (X86vzmovl
2542 (loadv2i64 addr:$src))))]>,
2543 XS, Requires<[HasSSE2]>;
2545 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2546 (MOVZPQILo2PQIrm addr:$src)>;
2549 // Instructions for the disassembler
2550 // xr = XMM register
2553 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2554 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2556 //===---------------------------------------------------------------------===//
2557 // SSE3 Instructions
2558 //===---------------------------------------------------------------------===//
2560 // Move Instructions
2561 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2562 "movshdup\t{$src, $dst|$dst, $src}",
2563 [(set VR128:$dst, (v4f32 (movshdup
2564 VR128:$src, (undef))))]>;
2565 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2566 "movshdup\t{$src, $dst|$dst, $src}",
2567 [(set VR128:$dst, (movshdup
2568 (memopv4f32 addr:$src), (undef)))]>;
2570 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2571 "movsldup\t{$src, $dst|$dst, $src}",
2572 [(set VR128:$dst, (v4f32 (movsldup
2573 VR128:$src, (undef))))]>;
2574 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2575 "movsldup\t{$src, $dst|$dst, $src}",
2576 [(set VR128:$dst, (movsldup
2577 (memopv4f32 addr:$src), (undef)))]>;
2579 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2580 "movddup\t{$src, $dst|$dst, $src}",
2581 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2582 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2583 "movddup\t{$src, $dst|$dst, $src}",
2585 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2588 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2590 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2592 let AddedComplexity = 5 in {
2593 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2594 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2595 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2596 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2597 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2598 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2599 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2600 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2604 let Constraints = "$src1 = $dst" in {
2605 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2606 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2607 "addsubps\t{$src2, $dst|$dst, $src2}",
2608 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2610 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2611 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2612 "addsubps\t{$src2, $dst|$dst, $src2}",
2613 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2614 (memop addr:$src2)))]>;
2615 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2616 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2617 "addsubpd\t{$src2, $dst|$dst, $src2}",
2618 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2620 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2621 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2622 "addsubpd\t{$src2, $dst|$dst, $src2}",
2623 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2624 (memop addr:$src2)))]>;
2627 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2628 "lddqu\t{$src, $dst|$dst, $src}",
2629 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2632 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2633 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2634 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2635 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2636 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2637 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2638 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2639 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2640 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2641 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2642 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2643 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2644 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2645 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2646 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2647 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2649 let Constraints = "$src1 = $dst" in {
2650 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2651 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2652 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2653 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2654 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2655 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2656 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2657 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2660 // Thread synchronization
2661 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2662 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2663 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2664 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2666 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2667 let AddedComplexity = 15 in
2668 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2669 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2670 let AddedComplexity = 20 in
2671 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2672 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2674 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2675 let AddedComplexity = 15 in
2676 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2677 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2678 let AddedComplexity = 20 in
2679 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2680 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2682 //===---------------------------------------------------------------------===//
2683 // SSSE3 Instructions
2684 //===---------------------------------------------------------------------===//
2686 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2687 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2688 Intrinsic IntId64, Intrinsic IntId128> {
2689 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2690 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2691 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2693 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2694 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2696 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2698 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2700 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2701 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2704 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2706 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2709 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2712 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2713 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2714 Intrinsic IntId64, Intrinsic IntId128> {
2715 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2717 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2718 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2720 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2725 (bitconvert (memopv4i16 addr:$src))))]>;
2727 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2729 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2730 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2733 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2735 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2738 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2741 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2742 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2743 Intrinsic IntId64, Intrinsic IntId128> {
2744 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2746 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2747 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2749 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2751 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2754 (bitconvert (memopv2i32 addr:$src))))]>;
2756 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2758 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2759 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2762 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2764 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2767 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2770 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2771 int_x86_ssse3_pabs_b,
2772 int_x86_ssse3_pabs_b_128>;
2773 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2774 int_x86_ssse3_pabs_w,
2775 int_x86_ssse3_pabs_w_128>;
2776 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2777 int_x86_ssse3_pabs_d,
2778 int_x86_ssse3_pabs_d_128>;
2780 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2781 let Constraints = "$src1 = $dst" in {
2782 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2783 Intrinsic IntId64, Intrinsic IntId128,
2784 bit Commutable = 0> {
2785 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2786 (ins VR64:$src1, VR64:$src2),
2787 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2788 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2789 let isCommutable = Commutable;
2791 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2792 (ins VR64:$src1, i64mem:$src2),
2793 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2795 (IntId64 VR64:$src1,
2796 (bitconvert (memopv8i8 addr:$src2))))]>;
2798 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2799 (ins VR128:$src1, VR128:$src2),
2800 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2801 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2803 let isCommutable = Commutable;
2805 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2806 (ins VR128:$src1, i128mem:$src2),
2807 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2809 (IntId128 VR128:$src1,
2810 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2814 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2815 let Constraints = "$src1 = $dst" in {
2816 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2817 Intrinsic IntId64, Intrinsic IntId128,
2818 bit Commutable = 0> {
2819 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2820 (ins VR64:$src1, VR64:$src2),
2821 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2822 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2823 let isCommutable = Commutable;
2825 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2826 (ins VR64:$src1, i64mem:$src2),
2827 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2829 (IntId64 VR64:$src1,
2830 (bitconvert (memopv4i16 addr:$src2))))]>;
2832 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2833 (ins VR128:$src1, VR128:$src2),
2834 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2835 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2837 let isCommutable = Commutable;
2839 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2840 (ins VR128:$src1, i128mem:$src2),
2841 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2843 (IntId128 VR128:$src1,
2844 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2848 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2849 let Constraints = "$src1 = $dst" in {
2850 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2851 Intrinsic IntId64, Intrinsic IntId128,
2852 bit Commutable = 0> {
2853 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2854 (ins VR64:$src1, VR64:$src2),
2855 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2856 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2857 let isCommutable = Commutable;
2859 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2860 (ins VR64:$src1, i64mem:$src2),
2861 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2863 (IntId64 VR64:$src1,
2864 (bitconvert (memopv2i32 addr:$src2))))]>;
2866 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2867 (ins VR128:$src1, VR128:$src2),
2868 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2869 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2871 let isCommutable = Commutable;
2873 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2874 (ins VR128:$src1, i128mem:$src2),
2875 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2877 (IntId128 VR128:$src1,
2878 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2882 let ImmT = NoImm in { // None of these have i8 immediate fields.
2883 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2884 int_x86_ssse3_phadd_w,
2885 int_x86_ssse3_phadd_w_128>;
2886 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2887 int_x86_ssse3_phadd_d,
2888 int_x86_ssse3_phadd_d_128>;
2889 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2890 int_x86_ssse3_phadd_sw,
2891 int_x86_ssse3_phadd_sw_128>;
2892 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2893 int_x86_ssse3_phsub_w,
2894 int_x86_ssse3_phsub_w_128>;
2895 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2896 int_x86_ssse3_phsub_d,
2897 int_x86_ssse3_phsub_d_128>;
2898 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2899 int_x86_ssse3_phsub_sw,
2900 int_x86_ssse3_phsub_sw_128>;
2901 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2902 int_x86_ssse3_pmadd_ub_sw,
2903 int_x86_ssse3_pmadd_ub_sw_128>;
2904 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2905 int_x86_ssse3_pmul_hr_sw,
2906 int_x86_ssse3_pmul_hr_sw_128, 1>;
2908 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2909 int_x86_ssse3_pshuf_b,
2910 int_x86_ssse3_pshuf_b_128>;
2911 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2912 int_x86_ssse3_psign_b,
2913 int_x86_ssse3_psign_b_128>;
2914 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2915 int_x86_ssse3_psign_w,
2916 int_x86_ssse3_psign_w_128>;
2917 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2918 int_x86_ssse3_psign_d,
2919 int_x86_ssse3_psign_d_128>;
2922 // palignr patterns.
2923 let Constraints = "$src1 = $dst" in {
2924 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2925 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2926 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2928 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2929 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2930 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2933 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2934 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2935 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2937 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2938 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2939 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2943 let AddedComplexity = 5 in {
2945 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2946 (PALIGNR64rr VR64:$src2, VR64:$src1,
2947 (SHUFFLE_get_palign_imm VR64:$src3))>,
2948 Requires<[HasSSSE3]>;
2949 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2950 (PALIGNR64rr VR64:$src2, VR64:$src1,
2951 (SHUFFLE_get_palign_imm VR64:$src3))>,
2952 Requires<[HasSSSE3]>;
2953 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2954 (PALIGNR64rr VR64:$src2, VR64:$src1,
2955 (SHUFFLE_get_palign_imm VR64:$src3))>,
2956 Requires<[HasSSSE3]>;
2957 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2958 (PALIGNR64rr VR64:$src2, VR64:$src1,
2959 (SHUFFLE_get_palign_imm VR64:$src3))>,
2960 Requires<[HasSSSE3]>;
2961 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2962 (PALIGNR64rr VR64:$src2, VR64:$src1,
2963 (SHUFFLE_get_palign_imm VR64:$src3))>,
2964 Requires<[HasSSSE3]>;
2966 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2967 (PALIGNR128rr VR128:$src2, VR128:$src1,
2968 (SHUFFLE_get_palign_imm VR128:$src3))>,
2969 Requires<[HasSSSE3]>;
2970 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2971 (PALIGNR128rr VR128:$src2, VR128:$src1,
2972 (SHUFFLE_get_palign_imm VR128:$src3))>,
2973 Requires<[HasSSSE3]>;
2974 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2975 (PALIGNR128rr VR128:$src2, VR128:$src1,
2976 (SHUFFLE_get_palign_imm VR128:$src3))>,
2977 Requires<[HasSSSE3]>;
2978 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2979 (PALIGNR128rr VR128:$src2, VR128:$src1,
2980 (SHUFFLE_get_palign_imm VR128:$src3))>,
2981 Requires<[HasSSSE3]>;
2984 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2985 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2986 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2987 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2989 //===---------------------------------------------------------------------===//
2990 // Non-Instruction Patterns
2991 //===---------------------------------------------------------------------===//
2993 // extload f32 -> f64. This matches load+fextend because we have a hack in
2994 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2996 // Since these loads aren't folded into the fextend, we have to match it
2998 let Predicates = [HasSSE2] in
2999 def : Pat<(fextend (loadf32 addr:$src)),
3000 (CVTSS2SDrm addr:$src)>;
3003 let Predicates = [HasSSE2] in {
3004 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3005 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3006 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3007 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3008 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3009 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3010 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3011 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3012 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3013 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3014 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3015 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3016 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3017 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3018 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3019 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3020 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3021 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3022 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3023 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3024 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3025 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3026 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3027 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3028 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3029 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3030 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3031 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3032 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3033 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3036 // Move scalar to XMM zero-extended
3037 // movd to XMM register zero-extends
3038 let AddedComplexity = 15 in {
3039 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3040 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3041 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3042 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3043 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3044 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3045 (MOVSSrr (v4f32 (V_SET0PS)),
3046 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), x86_subreg_ss)))>;
3047 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3048 (MOVSSrr (v4i32 (V_SET0PI)),
3049 (EXTRACT_SUBREG (v4i32 VR128:$src), x86_subreg_ss))>;
3052 // Splat v2f64 / v2i64
3053 let AddedComplexity = 10 in {
3054 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3055 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3056 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3057 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3058 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3059 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3060 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3061 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3064 // Special unary SHUFPSrri case.
3065 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3066 (SHUFPSrri VR128:$src1, VR128:$src1,
3067 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3068 let AddedComplexity = 5 in
3069 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3070 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3071 Requires<[HasSSE2]>;
3072 // Special unary SHUFPDrri case.
3073 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3074 (SHUFPDrri VR128:$src1, VR128:$src1,
3075 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3076 Requires<[HasSSE2]>;
3077 // Special unary SHUFPDrri case.
3078 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3079 (SHUFPDrri VR128:$src1, VR128:$src1,
3080 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3081 Requires<[HasSSE2]>;
3082 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3083 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3084 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3085 Requires<[HasSSE2]>;
3087 // Special binary v4i32 shuffle cases with SHUFPS.
3088 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3089 (SHUFPSrri VR128:$src1, VR128:$src2,
3090 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3091 Requires<[HasSSE2]>;
3092 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3093 (SHUFPSrmi VR128:$src1, addr:$src2,
3094 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3095 Requires<[HasSSE2]>;
3096 // Special binary v2i64 shuffle cases using SHUFPDrri.
3097 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3098 (SHUFPDrri VR128:$src1, VR128:$src2,
3099 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3100 Requires<[HasSSE2]>;
3102 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3103 let AddedComplexity = 15 in {
3104 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3105 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3106 Requires<[OptForSpeed, HasSSE2]>;
3107 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3108 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3109 Requires<[OptForSpeed, HasSSE2]>;
3111 let AddedComplexity = 10 in {
3112 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3113 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3114 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3115 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3116 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3117 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3118 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3119 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3122 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3123 let AddedComplexity = 15 in {
3124 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3125 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3126 Requires<[OptForSpeed, HasSSE2]>;
3127 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3128 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3129 Requires<[OptForSpeed, HasSSE2]>;
3131 let AddedComplexity = 10 in {
3132 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3133 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3134 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3135 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3136 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3137 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3138 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3139 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3142 let AddedComplexity = 20 in {
3143 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3144 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3145 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3147 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3148 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3149 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3151 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3152 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3153 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3154 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3155 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3158 let AddedComplexity = 20 in {
3159 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3160 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3161 (MOVLPSrm VR128:$src1, addr:$src2)>;
3162 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3163 (MOVLPDrm VR128:$src1, addr:$src2)>;
3164 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3165 (MOVLPSrm VR128:$src1, addr:$src2)>;
3166 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3167 (MOVLPDrm VR128:$src1, addr:$src2)>;
3170 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3171 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3172 (MOVLPSmr addr:$src1, VR128:$src2)>;
3173 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3174 (MOVLPDmr addr:$src1, VR128:$src2)>;
3175 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3177 (MOVLPSmr addr:$src1, VR128:$src2)>;
3178 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3179 (MOVLPDmr addr:$src1, VR128:$src2)>;
3181 let AddedComplexity = 15 in {
3182 // Setting the lowest element in the vector.
3183 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3184 (MOVSSrr (v4i32 VR128:$src1),
3185 (EXTRACT_SUBREG (v4i32 VR128:$src2), x86_subreg_ss))>;
3186 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3187 (MOVSDrr (v2i64 VR128:$src1),
3188 (EXTRACT_SUBREG (v2i64 VR128:$src2), x86_subreg_sd))>;
3190 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3191 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3192 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3193 Requires<[HasSSE2]>;
3194 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3195 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, x86_subreg_sd))>,
3196 Requires<[HasSSE2]>;
3199 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3200 // fall back to this for SSE1)
3201 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3202 (SHUFPSrri VR128:$src2, VR128:$src1,
3203 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3205 // Set lowest element and zero upper elements.
3206 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3207 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3209 // Some special case pandn patterns.
3210 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3212 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3213 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3215 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3216 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3218 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3220 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3221 (memop addr:$src2))),
3222 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3223 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3224 (memop addr:$src2))),
3225 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3226 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3227 (memop addr:$src2))),
3228 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3230 // vector -> vector casts
3231 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3232 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3233 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3234 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3235 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3236 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3237 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3238 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3240 // Use movaps / movups for SSE integer load / store (one byte shorter).
3241 def : Pat<(alignedloadv4i32 addr:$src),
3242 (MOVAPSrm addr:$src)>;
3243 def : Pat<(loadv4i32 addr:$src),
3244 (MOVUPSrm addr:$src)>;
3245 def : Pat<(alignedloadv2i64 addr:$src),
3246 (MOVAPSrm addr:$src)>;
3247 def : Pat<(loadv2i64 addr:$src),
3248 (MOVUPSrm addr:$src)>;
3250 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3251 (MOVAPSmr addr:$dst, VR128:$src)>;
3252 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3253 (MOVAPSmr addr:$dst, VR128:$src)>;
3254 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3255 (MOVAPSmr addr:$dst, VR128:$src)>;
3256 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3257 (MOVAPSmr addr:$dst, VR128:$src)>;
3258 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3259 (MOVUPSmr addr:$dst, VR128:$src)>;
3260 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3261 (MOVUPSmr addr:$dst, VR128:$src)>;
3262 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3263 (MOVUPSmr addr:$dst, VR128:$src)>;
3264 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3265 (MOVUPSmr addr:$dst, VR128:$src)>;
3267 //===----------------------------------------------------------------------===//
3268 // SSE4.1 Instructions
3269 //===----------------------------------------------------------------------===//
3271 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3274 Intrinsic V2F64Int> {
3275 // Intrinsic operation, reg.
3276 // Vector intrinsic operation, reg
3277 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3278 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3279 !strconcat(OpcodeStr,
3280 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3281 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3284 // Vector intrinsic operation, mem
3285 def PSm_Int : Ii8<opcps, MRMSrcMem,
3286 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3287 !strconcat(OpcodeStr,
3288 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3290 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3292 Requires<[HasSSE41]>;
3294 // Vector intrinsic operation, reg
3295 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3296 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3297 !strconcat(OpcodeStr,
3298 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3299 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3302 // Vector intrinsic operation, mem
3303 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3304 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3305 !strconcat(OpcodeStr,
3306 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3308 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3312 let Constraints = "$src1 = $dst" in {
3313 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3317 // Intrinsic operation, reg.
3318 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3320 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3321 !strconcat(OpcodeStr,
3322 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3324 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3327 // Intrinsic operation, mem.
3328 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3330 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3331 !strconcat(OpcodeStr,
3332 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3334 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3337 // Intrinsic operation, reg.
3338 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3340 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3341 !strconcat(OpcodeStr,
3342 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3344 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3347 // Intrinsic operation, mem.
3348 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3350 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3351 !strconcat(OpcodeStr,
3352 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3354 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3359 // FP round - roundss, roundps, roundsd, roundpd
3360 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3361 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3362 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3363 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3365 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3366 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3367 Intrinsic IntId128> {
3368 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3370 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3371 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3372 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3374 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3377 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3380 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3381 int_x86_sse41_phminposuw>;
3383 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3384 let Constraints = "$src1 = $dst" in {
3385 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3386 Intrinsic IntId128, bit Commutable = 0> {
3387 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3388 (ins VR128:$src1, VR128:$src2),
3389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3390 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3392 let isCommutable = Commutable;
3394 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3395 (ins VR128:$src1, i128mem:$src2),
3396 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3398 (IntId128 VR128:$src1,
3399 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3403 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3404 int_x86_sse41_pcmpeqq, 1>;
3405 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3406 int_x86_sse41_packusdw, 0>;
3407 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3408 int_x86_sse41_pminsb, 1>;
3409 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3410 int_x86_sse41_pminsd, 1>;
3411 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3412 int_x86_sse41_pminud, 1>;
3413 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3414 int_x86_sse41_pminuw, 1>;
3415 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3416 int_x86_sse41_pmaxsb, 1>;
3417 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3418 int_x86_sse41_pmaxsd, 1>;
3419 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3420 int_x86_sse41_pmaxud, 1>;
3421 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3422 int_x86_sse41_pmaxuw, 1>;
3424 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3426 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3427 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3428 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3429 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3431 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3432 let Constraints = "$src1 = $dst" in {
3433 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3434 SDNode OpNode, Intrinsic IntId128,
3435 bit Commutable = 0> {
3436 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3437 (ins VR128:$src1, VR128:$src2),
3438 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3439 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3440 VR128:$src2))]>, OpSize {
3441 let isCommutable = Commutable;
3443 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3444 (ins VR128:$src1, VR128:$src2),
3445 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3446 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3448 let isCommutable = Commutable;
3450 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3451 (ins VR128:$src1, i128mem:$src2),
3452 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3454 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3455 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3456 (ins VR128:$src1, i128mem:$src2),
3457 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3459 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3464 /// SS48I_binop_rm - Simple SSE41 binary operator.
3465 let Constraints = "$src1 = $dst" in {
3466 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3467 ValueType OpVT, bit Commutable = 0> {
3468 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3469 (ins VR128:$src1, VR128:$src2),
3470 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3471 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3473 let isCommutable = Commutable;
3475 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3476 (ins VR128:$src1, i128mem:$src2),
3477 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3478 [(set VR128:$dst, (OpNode VR128:$src1,
3479 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3484 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3486 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3487 let Constraints = "$src1 = $dst" in {
3488 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3489 Intrinsic IntId128, bit Commutable = 0> {
3490 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3491 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3492 !strconcat(OpcodeStr,
3493 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3495 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3497 let isCommutable = Commutable;
3499 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3500 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3501 !strconcat(OpcodeStr,
3502 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3504 (IntId128 VR128:$src1,
3505 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3510 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3511 int_x86_sse41_blendps, 0>;
3512 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3513 int_x86_sse41_blendpd, 0>;
3514 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3515 int_x86_sse41_pblendw, 0>;
3516 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3517 int_x86_sse41_dpps, 1>;
3518 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3519 int_x86_sse41_dppd, 1>;
3520 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3521 int_x86_sse41_mpsadbw, 0>;
3524 /// SS41I_ternary_int - SSE 4.1 ternary operator
3525 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3526 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3527 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3528 (ins VR128:$src1, VR128:$src2),
3529 !strconcat(OpcodeStr,
3530 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3531 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3534 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3535 (ins VR128:$src1, i128mem:$src2),
3536 !strconcat(OpcodeStr,
3537 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3540 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3544 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3545 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3546 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3549 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3550 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3551 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3552 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3554 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3555 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3557 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3561 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3562 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3563 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3564 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3565 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3566 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3568 // Common patterns involving scalar load.
3569 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3570 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3571 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3572 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3574 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3575 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3576 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3577 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3579 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3580 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3581 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3582 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3584 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3585 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3586 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3587 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3589 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3590 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3591 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3592 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3594 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3595 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3596 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3597 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3600 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3601 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3602 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3603 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3605 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3606 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3608 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3612 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3613 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3614 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3615 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3617 // Common patterns involving scalar load
3618 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3619 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3620 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3621 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3623 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3624 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3625 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3626 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3629 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3630 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3631 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3632 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3634 // Expecting a i16 load any extended to i32 value.
3635 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3636 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3637 [(set VR128:$dst, (IntId (bitconvert
3638 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3642 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3643 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3645 // Common patterns involving scalar load
3646 def : Pat<(int_x86_sse41_pmovsxbq
3647 (bitconvert (v4i32 (X86vzmovl
3648 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3649 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3651 def : Pat<(int_x86_sse41_pmovzxbq
3652 (bitconvert (v4i32 (X86vzmovl
3653 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3654 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3657 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3658 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3659 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3660 (ins VR128:$src1, i32i8imm:$src2),
3661 !strconcat(OpcodeStr,
3662 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3663 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3665 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3666 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3667 !strconcat(OpcodeStr,
3668 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3671 // There's an AssertZext in the way of writing the store pattern
3672 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3675 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3678 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3679 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3680 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3681 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3682 !strconcat(OpcodeStr,
3683 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3686 // There's an AssertZext in the way of writing the store pattern
3687 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3690 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3693 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3694 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3695 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3696 (ins VR128:$src1, i32i8imm:$src2),
3697 !strconcat(OpcodeStr,
3698 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3700 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3701 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3702 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3703 !strconcat(OpcodeStr,
3704 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3705 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3706 addr:$dst)]>, OpSize;
3709 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3712 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3714 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3715 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3716 (ins VR128:$src1, i32i8imm:$src2),
3717 !strconcat(OpcodeStr,
3718 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3720 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3722 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3723 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3724 !strconcat(OpcodeStr,
3725 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3726 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3727 addr:$dst)]>, OpSize;
3730 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3732 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3733 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3736 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3737 Requires<[HasSSE41]>;
3739 let Constraints = "$src1 = $dst" in {
3740 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3741 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3742 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3743 !strconcat(OpcodeStr,
3744 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3746 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3747 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3748 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3749 !strconcat(OpcodeStr,
3750 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3752 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3753 imm:$src3))]>, OpSize;
3757 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3759 let Constraints = "$src1 = $dst" in {
3760 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3761 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3762 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3763 !strconcat(OpcodeStr,
3764 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3766 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3768 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3769 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3770 !strconcat(OpcodeStr,
3771 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3773 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3774 imm:$src3)))]>, OpSize;
3778 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3780 // insertps has a few different modes, there's the first two here below which
3781 // are optimized inserts that won't zero arbitrary elements in the destination
3782 // vector. The next one matches the intrinsic and could zero arbitrary elements
3783 // in the target vector.
3784 let Constraints = "$src1 = $dst" in {
3785 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3786 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3787 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3788 !strconcat(OpcodeStr,
3789 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3791 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3793 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3794 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3795 !strconcat(OpcodeStr,
3796 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3798 (X86insrtps VR128:$src1,
3799 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3800 imm:$src3))]>, OpSize;
3804 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3806 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3807 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3809 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3810 // the intel intrinsic that corresponds to this.
3811 let Defs = [EFLAGS] in {
3812 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3813 "ptest \t{$src2, $src1|$src1, $src2}",
3814 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3816 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3817 "ptest \t{$src2, $src1|$src1, $src2}",
3818 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3822 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3823 "movntdqa\t{$src, $dst|$dst, $src}",
3824 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3828 //===----------------------------------------------------------------------===//
3829 // SSE4.2 Instructions
3830 //===----------------------------------------------------------------------===//
3832 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3833 let Constraints = "$src1 = $dst" in {
3834 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3835 Intrinsic IntId128, bit Commutable = 0> {
3836 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3837 (ins VR128:$src1, VR128:$src2),
3838 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3839 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3841 let isCommutable = Commutable;
3843 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3844 (ins VR128:$src1, i128mem:$src2),
3845 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3847 (IntId128 VR128:$src1,
3848 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3852 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3854 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3855 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3856 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3857 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3859 // crc intrinsic instruction
3860 // This set of instructions are only rm, the only difference is the size
3862 let Constraints = "$src1 = $dst" in {
3863 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3864 (ins GR32:$src1, i8mem:$src2),
3865 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3867 (int_x86_sse42_crc32_8 GR32:$src1,
3868 (load addr:$src2)))]>;
3869 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3870 (ins GR32:$src1, GR8:$src2),
3871 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3873 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3874 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3875 (ins GR32:$src1, i16mem:$src2),
3876 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3878 (int_x86_sse42_crc32_16 GR32:$src1,
3879 (load addr:$src2)))]>,
3881 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3882 (ins GR32:$src1, GR16:$src2),
3883 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3885 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3887 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3888 (ins GR32:$src1, i32mem:$src2),
3889 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3891 (int_x86_sse42_crc32_32 GR32:$src1,
3892 (load addr:$src2)))]>;
3893 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3894 (ins GR32:$src1, GR32:$src2),
3895 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3897 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3898 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3899 (ins GR64:$src1, i8mem:$src2),
3900 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3902 (int_x86_sse42_crc64_8 GR64:$src1,
3903 (load addr:$src2)))]>,
3905 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3906 (ins GR64:$src1, GR8:$src2),
3907 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3909 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3911 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3912 (ins GR64:$src1, i64mem:$src2),
3913 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3915 (int_x86_sse42_crc64_64 GR64:$src1,
3916 (load addr:$src2)))]>,
3918 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3919 (ins GR64:$src1, GR64:$src2),
3920 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3922 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3926 // String/text processing instructions.
3927 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3928 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3929 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3930 "#PCMPISTRM128rr PSEUDO!",
3931 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3932 imm:$src3))]>, OpSize;
3933 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3934 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3935 "#PCMPISTRM128rm PSEUDO!",
3936 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3937 imm:$src3))]>, OpSize;
3940 let Defs = [XMM0, EFLAGS] in {
3941 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3942 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3943 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3944 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3945 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3946 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3949 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3950 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3951 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3952 "#PCMPESTRM128rr PSEUDO!",
3954 (int_x86_sse42_pcmpestrm128
3955 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3957 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3958 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3959 "#PCMPESTRM128rm PSEUDO!",
3960 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3961 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3965 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3966 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3967 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3968 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3969 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3970 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3971 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3974 let Defs = [ECX, EFLAGS] in {
3975 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3976 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3977 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3978 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3979 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3980 (implicit EFLAGS)]>, OpSize;
3981 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3982 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3983 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3984 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3985 (implicit EFLAGS)]>, OpSize;
3989 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3990 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3991 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3992 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3993 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3994 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3996 let Defs = [ECX, EFLAGS] in {
3997 let Uses = [EAX, EDX] in {
3998 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3999 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4000 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4001 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4002 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4003 (implicit EFLAGS)]>, OpSize;
4004 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4005 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4006 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
4008 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4009 (implicit EFLAGS)]>, OpSize;
4014 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4015 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4016 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4017 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4018 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4019 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4021 //===----------------------------------------------------------------------===//
4022 // AES-NI Instructions
4023 //===----------------------------------------------------------------------===//
4025 let Constraints = "$src1 = $dst" in {
4026 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4027 Intrinsic IntId128, bit Commutable = 0> {
4028 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4029 (ins VR128:$src1, VR128:$src2),
4030 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4031 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4033 let isCommutable = Commutable;
4035 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4036 (ins VR128:$src1, i128mem:$src2),
4037 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4039 (IntId128 VR128:$src1,
4040 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4044 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4045 int_x86_aesni_aesenc>;
4046 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4047 int_x86_aesni_aesenclast>;
4048 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4049 int_x86_aesni_aesdec>;
4050 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4051 int_x86_aesni_aesdeclast>;
4053 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4054 (AESENCrr VR128:$src1, VR128:$src2)>;
4055 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4056 (AESENCrm VR128:$src1, addr:$src2)>;
4057 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4058 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4059 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4060 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4061 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4062 (AESDECrr VR128:$src1, VR128:$src2)>;
4063 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4064 (AESDECrm VR128:$src1, addr:$src2)>;
4065 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4066 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4067 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4068 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4070 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4072 "aesimc\t{$src1, $dst|$dst, $src1}",
4074 (int_x86_aesni_aesimc VR128:$src1))]>,
4077 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4078 (ins i128mem:$src1),
4079 "aesimc\t{$src1, $dst|$dst, $src1}",
4081 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4084 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4085 (ins VR128:$src1, i32i8imm:$src2),
4086 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4088 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4090 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4091 (ins i128mem:$src1, i32i8imm:$src2),
4092 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4094 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),