1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under the University
6 // of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
36 [SDNPHasChain, SDNPOutFlag]>;
37 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
38 [SDNPHasChain, SDNPOutFlag]>;
39 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
40 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
41 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
43 //===----------------------------------------------------------------------===//
44 // SSE 'Special' Instructions
45 //===----------------------------------------------------------------------===//
47 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
49 [(set VR128:$dst, (v4f32 (undef)))]>,
51 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
53 [(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
54 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
56 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
58 //===----------------------------------------------------------------------===//
59 // SSE Complex Patterns
60 //===----------------------------------------------------------------------===//
62 // These are 'extloads' from a scalar to the low element of a vector, zeroing
63 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
65 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
67 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
70 def ssmem : Operand<v4f32> {
71 let PrintMethod = "printf32mem";
72 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
74 def sdmem : Operand<v2f64> {
75 let PrintMethod = "printf64mem";
76 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79 //===----------------------------------------------------------------------===//
80 // SSE pattern fragments
81 //===----------------------------------------------------------------------===//
83 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
84 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
85 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
86 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
88 // Like 'store', but always requires vector alignment.
89 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
90 (st node:$val, node:$ptr), [{
91 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
92 return !ST->isTruncatingStore() &&
93 ST->getAddressingMode() == ISD::UNINDEXED &&
94 ST->getAlignment() >= 16;
98 // Like 'load', but always requires vector alignment.
99 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
100 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
101 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
102 LD->getAddressingMode() == ISD::UNINDEXED &&
103 LD->getAlignment() >= 16;
107 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
108 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
109 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
110 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
111 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
112 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
114 // Like 'load', but uses special alignment checks suitable for use in
115 // memory operands in most SSE instructions, which are required to
116 // be naturally aligned on some targets but not on others.
117 // FIXME: Actually implement support for targets that don't require the
118 // alignment. This probably wants a subtarget predicate.
119 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
121 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
122 LD->getAddressingMode() == ISD::UNINDEXED &&
123 LD->getAlignment() >= 16;
127 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
128 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
129 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
130 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
131 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
132 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
134 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
136 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
137 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
138 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
139 LD->getAddressingMode() == ISD::UNINDEXED &&
140 LD->getAlignment() >= 8;
144 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
145 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop64 node:$ptr))>;
146 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
147 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
148 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
150 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
151 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
152 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
153 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
154 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
155 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
157 def fp32imm0 : PatLeaf<(f32 fpimm), [{
158 return N->isExactlyValue(+0.0);
161 def PSxLDQ_imm : SDNodeXForm<imm, [{
162 // Transformation function: imm >> 3
163 return getI32Imm(N->getValue() >> 3);
166 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
168 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
169 return getI8Imm(X86::getShuffleSHUFImmediate(N));
172 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
174 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
175 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
178 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
180 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
181 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
184 def SSE_splat_mask : PatLeaf<(build_vector), [{
185 return X86::isSplatMask(N);
186 }], SHUFFLE_get_shuf_imm>;
188 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
189 return X86::isSplatLoMask(N);
192 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
193 return X86::isMOVHLPSMask(N);
196 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
197 return X86::isMOVHLPS_v_undef_Mask(N);
200 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
201 return X86::isMOVHPMask(N);
204 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
205 return X86::isMOVLPMask(N);
208 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
209 return X86::isMOVLMask(N);
212 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
213 return X86::isMOVSHDUPMask(N);
216 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
217 return X86::isMOVSLDUPMask(N);
220 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
221 return X86::isUNPCKLMask(N);
224 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
225 return X86::isUNPCKHMask(N);
228 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
229 return X86::isUNPCKL_v_undef_Mask(N);
232 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
233 return X86::isUNPCKH_v_undef_Mask(N);
236 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
237 return X86::isPSHUFDMask(N);
238 }], SHUFFLE_get_shuf_imm>;
240 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
241 return X86::isPSHUFHWMask(N);
242 }], SHUFFLE_get_pshufhw_imm>;
244 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
245 return X86::isPSHUFLWMask(N);
246 }], SHUFFLE_get_pshuflw_imm>;
248 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
249 return X86::isPSHUFDMask(N);
250 }], SHUFFLE_get_shuf_imm>;
252 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
253 return X86::isSHUFPMask(N);
254 }], SHUFFLE_get_shuf_imm>;
256 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
257 return X86::isSHUFPMask(N);
258 }], SHUFFLE_get_shuf_imm>;
260 //===----------------------------------------------------------------------===//
261 // SSE scalar FP Instructions
262 //===----------------------------------------------------------------------===//
264 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
265 // scheduler into a branch sequence.
266 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
267 def CMOV_FR32 : I<0, Pseudo,
268 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
269 "#CMOV_FR32 PSEUDO!",
270 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
271 def CMOV_FR64 : I<0, Pseudo,
272 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
273 "#CMOV_FR64 PSEUDO!",
274 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
275 def CMOV_V4F32 : I<0, Pseudo,
276 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
277 "#CMOV_V4F32 PSEUDO!",
279 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
280 def CMOV_V2F64 : I<0, Pseudo,
281 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
282 "#CMOV_V2F64 PSEUDO!",
284 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
285 def CMOV_V2I64 : I<0, Pseudo,
286 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
287 "#CMOV_V2I64 PSEUDO!",
289 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
292 //===----------------------------------------------------------------------===//
294 //===----------------------------------------------------------------------===//
297 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
298 "movss\t{$src, $dst|$dst, $src}", []>;
299 let isLoad = 1, isReMaterializable = 1 in
300 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
301 "movss\t{$src, $dst|$dst, $src}",
302 [(set FR32:$dst, (loadf32 addr:$src))]>;
303 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
304 "movss\t{$src, $dst|$dst, $src}",
305 [(store FR32:$src, addr:$dst)]>;
307 // Conversion instructions
308 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
309 "cvttss2si\t{$src, $dst|$dst, $src}",
310 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
311 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
312 "cvttss2si\t{$src, $dst|$dst, $src}",
313 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
314 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
315 "cvtsi2ss\t{$src, $dst|$dst, $src}",
316 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
317 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
318 "cvtsi2ss\t{$src, $dst|$dst, $src}",
319 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
321 // Match intrinsics which expect XMM operand(s).
322 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
323 "cvtss2si\t{$src, $dst|$dst, $src}",
324 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
325 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
326 "cvtss2si\t{$src, $dst|$dst, $src}",
327 [(set GR32:$dst, (int_x86_sse_cvtss2si
328 (load addr:$src)))]>;
330 // Aliases for intrinsics
331 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
332 "cvttss2si\t{$src, $dst|$dst, $src}",
334 (int_x86_sse_cvttss2si VR128:$src))]>;
335 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
336 "cvttss2si\t{$src, $dst|$dst, $src}",
338 (int_x86_sse_cvttss2si(load addr:$src)))]>;
340 let isTwoAddress = 1 in {
341 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
342 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
343 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
344 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
346 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
347 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
348 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
349 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
350 (loadi32 addr:$src2)))]>;
353 // Comparison instructions
354 let isTwoAddress = 1 in {
355 def CMPSSrr : SSI<0xC2, MRMSrcReg,
356 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
357 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
358 def CMPSSrm : SSI<0xC2, MRMSrcMem,
359 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
360 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
363 let Defs = [EFLAGS] in {
364 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
365 "ucomiss\t{$src2, $src1|$src1, $src2}",
366 [(X86cmp FR32:$src1, FR32:$src2)]>;
367 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
368 "ucomiss\t{$src2, $src1|$src1, $src2}",
369 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
372 // Aliases to match intrinsics which expect XMM operand(s).
373 let isTwoAddress = 1 in {
374 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
375 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
376 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
377 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
378 VR128:$src, imm:$cc))]>;
379 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
380 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
381 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
382 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
383 (load addr:$src), imm:$cc))]>;
386 let Defs = [EFLAGS] in {
387 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
388 "ucomiss\t{$src2, $src1|$src1, $src2}",
389 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
390 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
391 "ucomiss\t{$src2, $src1|$src1, $src2}",
392 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2))]>;
394 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
395 "comiss\t{$src2, $src1|$src1, $src2}",
396 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
397 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
398 "comiss\t{$src2, $src1|$src1, $src2}",
399 [(X86comi (v4f32 VR128:$src1), (load addr:$src2))]>;
402 // Aliases of packed SSE1 instructions for scalar use. These all have names that
405 // Alias instructions that map fld0 to pxor for sse.
406 let isReMaterializable = 1 in
407 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
408 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
409 Requires<[HasSSE1]>, TB, OpSize;
411 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
413 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
414 "movaps\t{$src, $dst|$dst, $src}", []>;
416 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
419 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
420 "movaps\t{$src, $dst|$dst, $src}",
421 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
423 // Alias bitwise logical operations using SSE logical ops on packed FP values.
424 let isTwoAddress = 1 in {
425 let isCommutable = 1 in {
426 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
427 "andps\t{$src2, $dst|$dst, $src2}",
428 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
429 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
430 "orps\t{$src2, $dst|$dst, $src2}",
431 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
432 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
433 "xorps\t{$src2, $dst|$dst, $src2}",
434 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
437 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
438 "andps\t{$src2, $dst|$dst, $src2}",
439 [(set FR32:$dst, (X86fand FR32:$src1,
440 (memopfsf32 addr:$src2)))]>;
441 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
442 "orps\t{$src2, $dst|$dst, $src2}",
443 [(set FR32:$dst, (X86for FR32:$src1,
444 (memopfsf32 addr:$src2)))]>;
445 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
446 "xorps\t{$src2, $dst|$dst, $src2}",
447 [(set FR32:$dst, (X86fxor FR32:$src1,
448 (memopfsf32 addr:$src2)))]>;
450 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
451 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
452 "andnps\t{$src2, $dst|$dst, $src2}", []>;
453 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
454 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
455 "andnps\t{$src2, $dst|$dst, $src2}", []>;
458 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
460 /// In addition, we also have a special variant of the scalar form here to
461 /// represent the associated intrinsic operation. This form is unlike the
462 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
463 /// and leaves the top elements undefined.
465 /// These three forms can each be reg+reg or reg+mem, so there are a total of
466 /// six "instructions".
468 let isTwoAddress = 1 in {
469 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
470 SDNode OpNode, Intrinsic F32Int,
471 bit Commutable = 0> {
472 // Scalar operation, reg+reg.
473 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
474 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
475 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
476 let isCommutable = Commutable;
479 // Scalar operation, reg+mem.
480 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
481 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
482 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
484 // Vector operation, reg+reg.
485 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
486 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
487 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
488 let isCommutable = Commutable;
491 // Vector operation, reg+mem.
492 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
493 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
494 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
496 // Intrinsic operation, reg+reg.
497 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
498 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
499 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
500 let isCommutable = Commutable;
503 // Intrinsic operation, reg+mem.
504 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
505 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
506 [(set VR128:$dst, (F32Int VR128:$src1,
507 sse_load_f32:$src2))]>;
511 // Arithmetic instructions
512 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
513 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
514 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
515 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
517 /// sse1_fp_binop_rm - Other SSE1 binops
519 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
520 /// instructions for a full-vector intrinsic form. Operations that map
521 /// onto C operators don't use this form since they just use the plain
522 /// vector form instead of having a separate vector intrinsic form.
524 /// This provides a total of eight "instructions".
526 let isTwoAddress = 1 in {
527 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
531 bit Commutable = 0> {
533 // Scalar operation, reg+reg.
534 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
535 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
536 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
537 let isCommutable = Commutable;
540 // Scalar operation, reg+mem.
541 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
542 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
543 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
545 // Vector operation, reg+reg.
546 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
547 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
548 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
549 let isCommutable = Commutable;
552 // Vector operation, reg+mem.
553 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
554 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
555 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
557 // Intrinsic operation, reg+reg.
558 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
559 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
560 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
561 let isCommutable = Commutable;
564 // Intrinsic operation, reg+mem.
565 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
566 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
567 [(set VR128:$dst, (F32Int VR128:$src1,
568 sse_load_f32:$src2))]>;
570 // Vector intrinsic operation, reg+reg.
571 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
572 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
573 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
574 let isCommutable = Commutable;
577 // Vector intrinsic operation, reg+mem.
578 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
579 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
580 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
584 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
585 int_x86_sse_max_ss, int_x86_sse_max_ps>;
586 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
587 int_x86_sse_min_ss, int_x86_sse_min_ps>;
589 //===----------------------------------------------------------------------===//
590 // SSE packed FP Instructions
593 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
594 "movaps\t{$src, $dst|$dst, $src}", []>;
595 let isLoad = 1, isReMaterializable = 1 in
596 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
597 "movaps\t{$src, $dst|$dst, $src}",
598 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
600 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
601 "movaps\t{$src, $dst|$dst, $src}",
602 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
604 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
605 "movups\t{$src, $dst|$dst, $src}", []>;
607 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
608 "movups\t{$src, $dst|$dst, $src}",
609 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
610 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
611 "movups\t{$src, $dst|$dst, $src}",
612 [(store (v4f32 VR128:$src), addr:$dst)]>;
614 // Intrinsic forms of MOVUPS load and store
616 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
617 "movups\t{$src, $dst|$dst, $src}",
618 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
619 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
620 "movups\t{$src, $dst|$dst, $src}",
621 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
623 let isTwoAddress = 1 in {
624 let AddedComplexity = 20 in {
625 def MOVLPSrm : PSI<0x12, MRMSrcMem,
626 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
627 "movlps\t{$src2, $dst|$dst, $src2}",
629 (v4f32 (vector_shuffle VR128:$src1,
630 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
631 MOVLP_shuffle_mask)))]>;
632 def MOVHPSrm : PSI<0x16, MRMSrcMem,
633 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
634 "movhps\t{$src2, $dst|$dst, $src2}",
636 (v4f32 (vector_shuffle VR128:$src1,
637 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
638 MOVHP_shuffle_mask)))]>;
642 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
643 "movlps\t{$src, $dst|$dst, $src}",
644 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
645 (iPTR 0))), addr:$dst)]>;
647 // v2f64 extract element 1 is always custom lowered to unpack high to low
648 // and extract element 0 so the non-store version isn't too horrible.
649 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
650 "movhps\t{$src, $dst|$dst, $src}",
651 [(store (f64 (vector_extract
652 (v2f64 (vector_shuffle
653 (bc_v2f64 (v4f32 VR128:$src)), (undef),
654 UNPCKH_shuffle_mask)), (iPTR 0))),
657 let isTwoAddress = 1 in {
658 let AddedComplexity = 15 in {
659 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
660 "movlhps\t{$src2, $dst|$dst, $src2}",
662 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
663 MOVHP_shuffle_mask)))]>;
665 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
666 "movhlps\t{$src2, $dst|$dst, $src2}",
668 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
669 MOVHLPS_shuffle_mask)))]>;
677 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
679 /// In addition, we also have a special variant of the scalar form here to
680 /// represent the associated intrinsic operation. This form is unlike the
681 /// plain scalar form, in that it takes an entire vector (instead of a
682 /// scalar) and leaves the top elements undefined.
684 /// And, we have a special variant form for a full-vector intrinsic form.
686 /// These four forms can each have a reg or a mem operand, so there are a
687 /// total of eight "instructions".
689 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
693 bit Commutable = 0> {
694 // Scalar operation, reg.
695 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
696 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
697 [(set FR32:$dst, (OpNode FR32:$src))]> {
698 let isCommutable = Commutable;
701 // Scalar operation, mem.
702 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
703 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
704 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
706 // Vector operation, reg.
707 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
708 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
709 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
710 let isCommutable = Commutable;
713 // Vector operation, mem.
714 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
715 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
716 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
718 // Intrinsic operation, reg.
719 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
720 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
721 [(set VR128:$dst, (F32Int VR128:$src))]> {
722 let isCommutable = Commutable;
725 // Intrinsic operation, mem.
726 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
727 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
728 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
730 // Vector intrinsic operation, reg
731 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
732 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
733 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
734 let isCommutable = Commutable;
737 // Vector intrinsic operation, mem
738 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
739 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
740 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
744 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
745 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
747 // Reciprocal approximations. Note that these typically require refinement
748 // in order to obtain suitable precision.
749 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
750 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
751 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
752 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
755 let isTwoAddress = 1 in {
756 let isCommutable = 1 in {
757 def ANDPSrr : PSI<0x54, MRMSrcReg,
758 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
759 "andps\t{$src2, $dst|$dst, $src2}",
760 [(set VR128:$dst, (v2i64
761 (and VR128:$src1, VR128:$src2)))]>;
762 def ORPSrr : PSI<0x56, MRMSrcReg,
763 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
764 "orps\t{$src2, $dst|$dst, $src2}",
765 [(set VR128:$dst, (v2i64
766 (or VR128:$src1, VR128:$src2)))]>;
767 def XORPSrr : PSI<0x57, MRMSrcReg,
768 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
769 "xorps\t{$src2, $dst|$dst, $src2}",
770 [(set VR128:$dst, (v2i64
771 (xor VR128:$src1, VR128:$src2)))]>;
774 def ANDPSrm : PSI<0x54, MRMSrcMem,
775 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
776 "andps\t{$src2, $dst|$dst, $src2}",
777 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
778 (memopv2i64 addr:$src2)))]>;
779 def ORPSrm : PSI<0x56, MRMSrcMem,
780 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
781 "orps\t{$src2, $dst|$dst, $src2}",
782 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
783 (memopv2i64 addr:$src2)))]>;
784 def XORPSrm : PSI<0x57, MRMSrcMem,
785 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
786 "xorps\t{$src2, $dst|$dst, $src2}",
787 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
788 (memopv2i64 addr:$src2)))]>;
789 def ANDNPSrr : PSI<0x55, MRMSrcReg,
790 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
791 "andnps\t{$src2, $dst|$dst, $src2}",
793 (v2i64 (and (xor VR128:$src1,
794 (bc_v2i64 (v4i32 immAllOnesV))),
796 def ANDNPSrm : PSI<0x55, MRMSrcMem,
797 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
798 "andnps\t{$src2, $dst|$dst, $src2}",
800 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
801 (bc_v2i64 (v4i32 immAllOnesV))),
802 (memopv2i64 addr:$src2))))]>;
805 let isTwoAddress = 1 in {
806 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
807 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
808 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
809 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
810 VR128:$src, imm:$cc))]>;
811 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
812 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
813 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
814 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
815 (load addr:$src), imm:$cc))]>;
818 // Shuffle and unpack instructions
819 let isTwoAddress = 1 in {
820 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
821 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
822 (outs VR128:$dst), (ins VR128:$src1,
823 VR128:$src2, i32i8imm:$src3),
824 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
826 (v4f32 (vector_shuffle
827 VR128:$src1, VR128:$src2,
828 SHUFP_shuffle_mask:$src3)))]>;
829 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
830 (outs VR128:$dst), (ins VR128:$src1,
831 f128mem:$src2, i32i8imm:$src3),
832 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
834 (v4f32 (vector_shuffle
835 VR128:$src1, (memopv4f32 addr:$src2),
836 SHUFP_shuffle_mask:$src3)))]>;
838 let AddedComplexity = 10 in {
839 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
840 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
841 "unpckhps\t{$src2, $dst|$dst, $src2}",
843 (v4f32 (vector_shuffle
844 VR128:$src1, VR128:$src2,
845 UNPCKH_shuffle_mask)))]>;
846 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
847 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
848 "unpckhps\t{$src2, $dst|$dst, $src2}",
850 (v4f32 (vector_shuffle
851 VR128:$src1, (memopv4f32 addr:$src2),
852 UNPCKH_shuffle_mask)))]>;
854 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
855 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
856 "unpcklps\t{$src2, $dst|$dst, $src2}",
858 (v4f32 (vector_shuffle
859 VR128:$src1, VR128:$src2,
860 UNPCKL_shuffle_mask)))]>;
861 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
862 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
863 "unpcklps\t{$src2, $dst|$dst, $src2}",
865 (v4f32 (vector_shuffle
866 VR128:$src1, (memopv4f32 addr:$src2),
867 UNPCKL_shuffle_mask)))]>;
872 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
873 "movmskps\t{$src, $dst|$dst, $src}",
874 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
875 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
876 "movmskpd\t{$src, $dst|$dst, $src}",
877 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
879 // Prefetching loads.
880 // TODO: no intrinsics for these?
881 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0\t$src", []>;
882 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1\t$src", []>;
883 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2\t$src", []>;
884 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta\t$src", []>;
886 // Non-temporal stores
887 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
888 "movntps\t{$src, $dst|$dst, $src}",
889 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
891 // Load, store, and memory fence
892 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
895 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
896 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
897 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
898 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
900 // Alias instructions that map zero vector to pxor / xorp* for sse.
901 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
902 let isReMaterializable = 1 in
903 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
905 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
907 // FR32 to 128-bit vector conversion.
908 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
909 "movss\t{$src, $dst|$dst, $src}",
911 (v4f32 (scalar_to_vector FR32:$src)))]>;
912 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
913 "movss\t{$src, $dst|$dst, $src}",
915 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
917 // FIXME: may not be able to eliminate this movss with coalescing the src and
918 // dest register classes are different. We really want to write this pattern
920 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
922 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
923 "movss\t{$src, $dst|$dst, $src}",
924 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
926 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
927 "movss\t{$src, $dst|$dst, $src}",
928 [(store (f32 (vector_extract (v4f32 VR128:$src),
929 (iPTR 0))), addr:$dst)]>;
932 // Move to lower bits of a VR128, leaving upper bits alone.
933 // Three operand (but two address) aliases.
934 let isTwoAddress = 1 in {
935 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
936 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
937 "movss\t{$src2, $dst|$dst, $src2}", []>;
939 let AddedComplexity = 15 in
940 def MOVLPSrr : SSI<0x10, MRMSrcReg,
941 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
942 "movss\t{$src2, $dst|$dst, $src2}",
944 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
945 MOVL_shuffle_mask)))]>;
948 // Move to lower bits of a VR128 and zeroing upper bits.
949 // Loading from memory automatically zeroing upper bits.
950 let AddedComplexity = 20 in
951 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
952 "movss\t{$src, $dst|$dst, $src}",
953 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV,
954 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
955 MOVL_shuffle_mask)))]>;
958 //===----------------------------------------------------------------------===//
960 //===----------------------------------------------------------------------===//
963 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
964 "movsd\t{$src, $dst|$dst, $src}", []>;
965 let isLoad = 1, isReMaterializable = 1 in
966 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
967 "movsd\t{$src, $dst|$dst, $src}",
968 [(set FR64:$dst, (loadf64 addr:$src))]>;
969 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
970 "movsd\t{$src, $dst|$dst, $src}",
971 [(store FR64:$src, addr:$dst)]>;
973 // Conversion instructions
974 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
975 "cvttsd2si\t{$src, $dst|$dst, $src}",
976 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
977 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
978 "cvttsd2si\t{$src, $dst|$dst, $src}",
979 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
980 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
981 "cvtsd2ss\t{$src, $dst|$dst, $src}",
982 [(set FR32:$dst, (fround FR64:$src))]>;
983 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
984 "cvtsd2ss\t{$src, $dst|$dst, $src}",
985 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
986 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
987 "cvtsi2sd\t{$src, $dst|$dst, $src}",
988 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
989 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
990 "cvtsi2sd\t{$src, $dst|$dst, $src}",
991 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
993 // SSE2 instructions with XS prefix
994 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
995 "cvtss2sd\t{$src, $dst|$dst, $src}",
996 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
998 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
999 "cvtss2sd\t{$src, $dst|$dst, $src}",
1000 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1001 Requires<[HasSSE2]>;
1003 // Match intrinsics which expect XMM operand(s).
1004 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1005 "cvtsd2si\t{$src, $dst|$dst, $src}",
1006 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1007 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1008 "cvtsd2si\t{$src, $dst|$dst, $src}",
1009 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1010 (load addr:$src)))]>;
1012 // Aliases for intrinsics
1013 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1014 "cvttsd2si\t{$src, $dst|$dst, $src}",
1016 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1017 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1018 "cvttsd2si\t{$src, $dst|$dst, $src}",
1019 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1020 (load addr:$src)))]>;
1022 // Comparison instructions
1023 let isTwoAddress = 1 in {
1024 def CMPSDrr : SDI<0xC2, MRMSrcReg,
1025 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1026 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1027 def CMPSDrm : SDI<0xC2, MRMSrcMem,
1028 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1029 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1032 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1033 "ucomisd\t{$src2, $src1|$src1, $src2}",
1034 [(X86cmp FR64:$src1, FR64:$src2)]>;
1035 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1036 "ucomisd\t{$src2, $src1|$src1, $src2}",
1037 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
1039 // Aliases to match intrinsics which expect XMM operand(s).
1040 let isTwoAddress = 1 in {
1041 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
1042 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1043 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1044 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1045 VR128:$src, imm:$cc))]>;
1046 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
1047 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1048 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1049 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1050 (load addr:$src), imm:$cc))]>;
1053 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1054 "ucomisd\t{$src2, $src1|$src1, $src2}",
1055 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1056 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1057 "ucomisd\t{$src2, $src1|$src1, $src2}",
1058 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2))]>;
1060 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1061 "comisd\t{$src2, $src1|$src1, $src2}",
1062 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
1063 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1064 "comisd\t{$src2, $src1|$src1, $src2}",
1065 [(X86comi (v2f64 VR128:$src1), (load addr:$src2))]>;
1067 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1070 // Alias instructions that map fld0 to pxor for sse.
1071 let isReMaterializable = 1 in
1072 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1073 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1074 Requires<[HasSSE2]>, TB, OpSize;
1076 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1078 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1079 "movapd\t{$src, $dst|$dst, $src}", []>;
1081 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1084 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1085 "movapd\t{$src, $dst|$dst, $src}",
1086 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1088 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1089 let isTwoAddress = 1 in {
1090 let isCommutable = 1 in {
1091 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1092 "andpd\t{$src2, $dst|$dst, $src2}",
1093 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1094 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1095 "orpd\t{$src2, $dst|$dst, $src2}",
1096 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1097 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1098 "xorpd\t{$src2, $dst|$dst, $src2}",
1099 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1102 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1103 "andpd\t{$src2, $dst|$dst, $src2}",
1104 [(set FR64:$dst, (X86fand FR64:$src1,
1105 (memopfsf64 addr:$src2)))]>;
1106 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1107 "orpd\t{$src2, $dst|$dst, $src2}",
1108 [(set FR64:$dst, (X86for FR64:$src1,
1109 (memopfsf64 addr:$src2)))]>;
1110 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1111 "xorpd\t{$src2, $dst|$dst, $src2}",
1112 [(set FR64:$dst, (X86fxor FR64:$src1,
1113 (memopfsf64 addr:$src2)))]>;
1115 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1116 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1117 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1118 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1119 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1120 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1123 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1125 /// In addition, we also have a special variant of the scalar form here to
1126 /// represent the associated intrinsic operation. This form is unlike the
1127 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1128 /// and leaves the top elements undefined.
1130 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1131 /// six "instructions".
1133 let isTwoAddress = 1 in {
1134 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1135 SDNode OpNode, Intrinsic F64Int,
1136 bit Commutable = 0> {
1137 // Scalar operation, reg+reg.
1138 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1139 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1140 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1141 let isCommutable = Commutable;
1144 // Scalar operation, reg+mem.
1145 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1146 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1147 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1149 // Vector operation, reg+reg.
1150 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1151 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1152 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1153 let isCommutable = Commutable;
1156 // Vector operation, reg+mem.
1157 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1158 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1159 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1161 // Intrinsic operation, reg+reg.
1162 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1163 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1164 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1165 let isCommutable = Commutable;
1168 // Intrinsic operation, reg+mem.
1169 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1170 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1171 [(set VR128:$dst, (F64Int VR128:$src1,
1172 sse_load_f64:$src2))]>;
1176 // Arithmetic instructions
1177 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1178 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1179 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1180 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1182 /// sse2_fp_binop_rm - Other SSE2 binops
1184 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1185 /// instructions for a full-vector intrinsic form. Operations that map
1186 /// onto C operators don't use this form since they just use the plain
1187 /// vector form instead of having a separate vector intrinsic form.
1189 /// This provides a total of eight "instructions".
1191 let isTwoAddress = 1 in {
1192 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1196 bit Commutable = 0> {
1198 // Scalar operation, reg+reg.
1199 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1200 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1201 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1202 let isCommutable = Commutable;
1205 // Scalar operation, reg+mem.
1206 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1207 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1208 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1210 // Vector operation, reg+reg.
1211 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1212 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1213 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1214 let isCommutable = Commutable;
1217 // Vector operation, reg+mem.
1218 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1219 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1220 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1222 // Intrinsic operation, reg+reg.
1223 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1224 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1225 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1226 let isCommutable = Commutable;
1229 // Intrinsic operation, reg+mem.
1230 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1231 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1232 [(set VR128:$dst, (F64Int VR128:$src1,
1233 sse_load_f64:$src2))]>;
1235 // Vector intrinsic operation, reg+reg.
1236 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1237 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1238 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1239 let isCommutable = Commutable;
1242 // Vector intrinsic operation, reg+mem.
1243 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1244 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1245 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1249 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1250 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1251 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1252 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1254 //===----------------------------------------------------------------------===//
1255 // SSE packed FP Instructions
1257 // Move Instructions
1258 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1259 "movapd\t{$src, $dst|$dst, $src}", []>;
1260 let isLoad = 1, isReMaterializable = 1 in
1261 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1262 "movapd\t{$src, $dst|$dst, $src}",
1263 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1265 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1266 "movapd\t{$src, $dst|$dst, $src}",
1267 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1269 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1270 "movupd\t{$src, $dst|$dst, $src}", []>;
1272 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1273 "movupd\t{$src, $dst|$dst, $src}",
1274 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1275 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1276 "movupd\t{$src, $dst|$dst, $src}",
1277 [(store (v2f64 VR128:$src), addr:$dst)]>;
1279 // Intrinsic forms of MOVUPD load and store
1280 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1281 "movupd\t{$src, $dst|$dst, $src}",
1282 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1283 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1284 "movupd\t{$src, $dst|$dst, $src}",
1285 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1287 let isTwoAddress = 1 in {
1288 let AddedComplexity = 20 in {
1289 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1290 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1291 "movlpd\t{$src2, $dst|$dst, $src2}",
1293 (v2f64 (vector_shuffle VR128:$src1,
1294 (scalar_to_vector (loadf64 addr:$src2)),
1295 MOVLP_shuffle_mask)))]>;
1296 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1297 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1298 "movhpd\t{$src2, $dst|$dst, $src2}",
1300 (v2f64 (vector_shuffle VR128:$src1,
1301 (scalar_to_vector (loadf64 addr:$src2)),
1302 MOVHP_shuffle_mask)))]>;
1303 } // AddedComplexity
1306 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movlpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract (v2f64 VR128:$src),
1309 (iPTR 0))), addr:$dst)]>;
1311 // v2f64 extract element 1 is always custom lowered to unpack high to low
1312 // and extract element 0 so the non-store version isn't too horrible.
1313 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1314 "movhpd\t{$src, $dst|$dst, $src}",
1315 [(store (f64 (vector_extract
1316 (v2f64 (vector_shuffle VR128:$src, (undef),
1317 UNPCKH_shuffle_mask)), (iPTR 0))),
1320 // SSE2 instructions without OpSize prefix
1321 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1322 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1323 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1324 TB, Requires<[HasSSE2]>;
1325 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1326 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1327 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1328 (bitconvert (memopv2i64 addr:$src))))]>,
1329 TB, Requires<[HasSSE2]>;
1331 // SSE2 instructions with XS prefix
1332 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1333 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1334 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1335 XS, Requires<[HasSSE2]>;
1336 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1337 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1338 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1339 (bitconvert (memopv2i64 addr:$src))))]>,
1340 XS, Requires<[HasSSE2]>;
1342 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1343 "cvtps2dq\t{$src, $dst|$dst, $src}",
1344 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1345 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1346 "cvtps2dq\t{$src, $dst|$dst, $src}",
1347 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1348 (load addr:$src)))]>;
1349 // SSE2 packed instructions with XS prefix
1350 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1351 "cvttps2dq\t{$src, $dst|$dst, $src}",
1352 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1353 XS, Requires<[HasSSE2]>;
1354 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1355 "cvttps2dq\t{$src, $dst|$dst, $src}",
1356 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1357 (load addr:$src)))]>,
1358 XS, Requires<[HasSSE2]>;
1360 // SSE2 packed instructions with XD prefix
1361 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1362 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1363 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1364 XD, Requires<[HasSSE2]>;
1365 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1366 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1367 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1368 (load addr:$src)))]>,
1369 XD, Requires<[HasSSE2]>;
1371 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1372 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1373 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1374 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1375 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1376 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1377 (load addr:$src)))]>;
1379 // SSE2 instructions without OpSize prefix
1380 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1381 "cvtps2pd\t{$src, $dst|$dst, $src}",
1382 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1383 TB, Requires<[HasSSE2]>;
1384 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1385 "cvtps2pd\t{$src, $dst|$dst, $src}",
1386 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1387 (load addr:$src)))]>,
1388 TB, Requires<[HasSSE2]>;
1390 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1391 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1392 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1393 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1394 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1395 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1396 (load addr:$src)))]>;
1398 // Match intrinsics which expect XMM operand(s).
1399 // Aliases for intrinsics
1400 let isTwoAddress = 1 in {
1401 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1402 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1403 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1404 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1406 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1407 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1408 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1409 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1410 (loadi32 addr:$src2)))]>;
1411 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1412 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1413 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1414 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1416 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1417 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1418 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1419 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1420 (load addr:$src2)))]>;
1421 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1422 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1423 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1424 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1425 VR128:$src2))]>, XS,
1426 Requires<[HasSSE2]>;
1427 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1428 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1429 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1430 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1431 (load addr:$src2)))]>, XS,
1432 Requires<[HasSSE2]>;
1437 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1439 /// In addition, we also have a special variant of the scalar form here to
1440 /// represent the associated intrinsic operation. This form is unlike the
1441 /// plain scalar form, in that it takes an entire vector (instead of a
1442 /// scalar) and leaves the top elements undefined.
1444 /// And, we have a special variant form for a full-vector intrinsic form.
1446 /// These four forms can each have a reg or a mem operand, so there are a
1447 /// total of eight "instructions".
1449 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1453 bit Commutable = 0> {
1454 // Scalar operation, reg.
1455 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1456 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1457 [(set FR64:$dst, (OpNode FR64:$src))]> {
1458 let isCommutable = Commutable;
1461 // Scalar operation, mem.
1462 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1463 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1464 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1466 // Vector operation, reg.
1467 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1468 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1469 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1470 let isCommutable = Commutable;
1473 // Vector operation, mem.
1474 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1475 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1476 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1478 // Intrinsic operation, reg.
1479 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1480 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1481 [(set VR128:$dst, (F64Int VR128:$src))]> {
1482 let isCommutable = Commutable;
1485 // Intrinsic operation, mem.
1486 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1487 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1488 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1490 // Vector intrinsic operation, reg
1491 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1492 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1493 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1494 let isCommutable = Commutable;
1497 // Vector intrinsic operation, mem
1498 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1499 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1500 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1504 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1505 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1507 // There is no f64 version of the reciprocal approximation instructions.
1510 let isTwoAddress = 1 in {
1511 let isCommutable = 1 in {
1512 def ANDPDrr : PDI<0x54, MRMSrcReg,
1513 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1514 "andpd\t{$src2, $dst|$dst, $src2}",
1516 (and (bc_v2i64 (v2f64 VR128:$src1)),
1517 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1518 def ORPDrr : PDI<0x56, MRMSrcReg,
1519 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1520 "orpd\t{$src2, $dst|$dst, $src2}",
1522 (or (bc_v2i64 (v2f64 VR128:$src1)),
1523 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1524 def XORPDrr : PDI<0x57, MRMSrcReg,
1525 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1526 "xorpd\t{$src2, $dst|$dst, $src2}",
1528 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1529 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1532 def ANDPDrm : PDI<0x54, MRMSrcMem,
1533 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1534 "andpd\t{$src2, $dst|$dst, $src2}",
1536 (and (bc_v2i64 (v2f64 VR128:$src1)),
1537 (memopv2i64 addr:$src2)))]>;
1538 def ORPDrm : PDI<0x56, MRMSrcMem,
1539 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1540 "orpd\t{$src2, $dst|$dst, $src2}",
1542 (or (bc_v2i64 (v2f64 VR128:$src1)),
1543 (memopv2i64 addr:$src2)))]>;
1544 def XORPDrm : PDI<0x57, MRMSrcMem,
1545 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1546 "xorpd\t{$src2, $dst|$dst, $src2}",
1548 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1549 (memopv2i64 addr:$src2)))]>;
1550 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1551 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1552 "andnpd\t{$src2, $dst|$dst, $src2}",
1554 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1555 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1556 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1557 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1558 "andnpd\t{$src2, $dst|$dst, $src2}",
1560 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1561 (memopv2i64 addr:$src2)))]>;
1564 let isTwoAddress = 1 in {
1565 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1566 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1567 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1568 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1569 VR128:$src, imm:$cc))]>;
1570 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1571 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1572 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1573 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1574 (load addr:$src), imm:$cc))]>;
1577 // Shuffle and unpack instructions
1578 let isTwoAddress = 1 in {
1579 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1580 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1581 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1582 [(set VR128:$dst, (v2f64 (vector_shuffle
1583 VR128:$src1, VR128:$src2,
1584 SHUFP_shuffle_mask:$src3)))]>;
1585 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1586 (outs VR128:$dst), (ins VR128:$src1,
1587 f128mem:$src2, i8imm:$src3),
1588 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1590 (v2f64 (vector_shuffle
1591 VR128:$src1, (memopv2f64 addr:$src2),
1592 SHUFP_shuffle_mask:$src3)))]>;
1594 let AddedComplexity = 10 in {
1595 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1596 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1597 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1599 (v2f64 (vector_shuffle
1600 VR128:$src1, VR128:$src2,
1601 UNPCKH_shuffle_mask)))]>;
1602 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1603 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1604 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1606 (v2f64 (vector_shuffle
1607 VR128:$src1, (memopv2f64 addr:$src2),
1608 UNPCKH_shuffle_mask)))]>;
1610 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1611 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1612 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1614 (v2f64 (vector_shuffle
1615 VR128:$src1, VR128:$src2,
1616 UNPCKL_shuffle_mask)))]>;
1617 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1618 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1619 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1621 (v2f64 (vector_shuffle
1622 VR128:$src1, (memopv2f64 addr:$src2),
1623 UNPCKL_shuffle_mask)))]>;
1624 } // AddedComplexity
1628 //===----------------------------------------------------------------------===//
1629 // SSE integer instructions
1631 // Move Instructions
1632 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1633 "movdqa\t{$src, $dst|$dst, $src}", []>;
1635 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1636 "movdqa\t{$src, $dst|$dst, $src}",
1637 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1638 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1639 "movdqa\t{$src, $dst|$dst, $src}",
1640 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1642 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1643 "movdqu\t{$src, $dst|$dst, $src}",
1644 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1645 XS, Requires<[HasSSE2]>;
1646 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1647 "movdqu\t{$src, $dst|$dst, $src}",
1648 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1649 XS, Requires<[HasSSE2]>;
1651 // Intrinsic forms of MOVDQU load and store
1653 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1654 "movdqu\t{$src, $dst|$dst, $src}",
1655 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1656 XS, Requires<[HasSSE2]>;
1657 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1658 "movdqu\t{$src, $dst|$dst, $src}",
1659 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1660 XS, Requires<[HasSSE2]>;
1662 let isTwoAddress = 1 in {
1664 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1665 bit Commutable = 0> {
1666 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1667 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1668 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1669 let isCommutable = Commutable;
1671 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1672 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1673 [(set VR128:$dst, (IntId VR128:$src1,
1674 (bitconvert (memopv2i64 addr:$src2))))]>;
1677 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1678 string OpcodeStr, Intrinsic IntId> {
1679 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1680 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1681 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1682 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1684 [(set VR128:$dst, (IntId VR128:$src1,
1685 (bitconvert (memopv2i64 addr:$src2))))]>;
1686 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1687 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1688 [(set VR128:$dst, (IntId VR128:$src1,
1689 (scalar_to_vector (i32 imm:$src2))))]>;
1693 /// PDI_binop_rm - Simple SSE2 binary operator.
1694 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1695 ValueType OpVT, bit Commutable = 0> {
1696 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1697 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1698 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1699 let isCommutable = Commutable;
1701 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1702 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1703 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1704 (bitconvert (memopv2i64 addr:$src2)))))]>;
1707 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1709 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1710 /// to collapse (bitconvert VT to VT) into its operand.
1712 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1713 bit Commutable = 0> {
1714 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1715 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1716 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1717 let isCommutable = Commutable;
1719 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1721 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1726 // 128-bit Integer Arithmetic
1728 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1729 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1730 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1731 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1733 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1734 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1735 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1736 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1738 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1739 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1740 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1741 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1743 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1744 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1745 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1746 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1748 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1750 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1751 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1752 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1754 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1756 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1757 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1760 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1761 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1762 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1763 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1764 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1767 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1768 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1769 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1771 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1772 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1773 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1775 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1776 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1777 // PSRAQ doesn't exist in SSE[1-3].
1779 // 128-bit logical shifts.
1780 let isTwoAddress = 1 in {
1781 def PSLLDQri : PDIi8<0x73, MRM7r,
1782 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1783 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1784 def PSRLDQri : PDIi8<0x73, MRM3r,
1785 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1786 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1787 // PSRADQri doesn't exist in SSE[1-3].
1790 let Predicates = [HasSSE2] in {
1791 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1792 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1793 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1794 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1795 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1796 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1800 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1801 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1802 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1804 let isTwoAddress = 1 in {
1805 def PANDNrr : PDI<0xDF, MRMSrcReg,
1806 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1807 "pandn\t{$src2, $dst|$dst, $src2}",
1808 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1811 def PANDNrm : PDI<0xDF, MRMSrcMem,
1812 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1813 "pandn\t{$src2, $dst|$dst, $src2}",
1814 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1815 (memopv2i64 addr:$src2))))]>;
1818 // SSE2 Integer comparison
1819 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1820 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1821 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1822 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1823 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1824 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1826 // Pack instructions
1827 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1828 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1829 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1831 // Shuffle and unpack instructions
1832 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1833 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1834 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1835 [(set VR128:$dst, (v4i32 (vector_shuffle
1836 VR128:$src1, (undef),
1837 PSHUFD_shuffle_mask:$src2)))]>;
1838 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1839 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1840 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1841 [(set VR128:$dst, (v4i32 (vector_shuffle
1842 (bc_v4i32(memopv2i64 addr:$src1)),
1844 PSHUFD_shuffle_mask:$src2)))]>;
1846 // SSE2 with ImmT == Imm8 and XS prefix.
1847 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1848 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1849 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1850 [(set VR128:$dst, (v8i16 (vector_shuffle
1851 VR128:$src1, (undef),
1852 PSHUFHW_shuffle_mask:$src2)))]>,
1853 XS, Requires<[HasSSE2]>;
1854 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1855 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1856 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1857 [(set VR128:$dst, (v8i16 (vector_shuffle
1858 (bc_v8i16 (memopv2i64 addr:$src1)),
1860 PSHUFHW_shuffle_mask:$src2)))]>,
1861 XS, Requires<[HasSSE2]>;
1863 // SSE2 with ImmT == Imm8 and XD prefix.
1864 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1865 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1866 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1867 [(set VR128:$dst, (v8i16 (vector_shuffle
1868 VR128:$src1, (undef),
1869 PSHUFLW_shuffle_mask:$src2)))]>,
1870 XD, Requires<[HasSSE2]>;
1871 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1872 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
1873 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1874 [(set VR128:$dst, (v8i16 (vector_shuffle
1875 (bc_v8i16 (memopv2i64 addr:$src1)),
1877 PSHUFLW_shuffle_mask:$src2)))]>,
1878 XD, Requires<[HasSSE2]>;
1881 let isTwoAddress = 1 in {
1882 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1883 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1884 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1886 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1887 UNPCKL_shuffle_mask)))]>;
1888 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1889 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1890 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1892 (v16i8 (vector_shuffle VR128:$src1,
1893 (bc_v16i8 (memopv2i64 addr:$src2)),
1894 UNPCKL_shuffle_mask)))]>;
1895 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1896 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1897 "punpcklwd\t{$src2, $dst|$dst, $src2}",
1899 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1900 UNPCKL_shuffle_mask)))]>;
1901 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1902 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1903 "punpcklwd\t{$src2, $dst|$dst, $src2}",
1905 (v8i16 (vector_shuffle VR128:$src1,
1906 (bc_v8i16 (memopv2i64 addr:$src2)),
1907 UNPCKL_shuffle_mask)))]>;
1908 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1909 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1910 "punpckldq\t{$src2, $dst|$dst, $src2}",
1912 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1913 UNPCKL_shuffle_mask)))]>;
1914 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1915 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1916 "punpckldq\t{$src2, $dst|$dst, $src2}",
1918 (v4i32 (vector_shuffle VR128:$src1,
1919 (bc_v4i32 (memopv2i64 addr:$src2)),
1920 UNPCKL_shuffle_mask)))]>;
1921 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1922 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1923 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
1925 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1926 UNPCKL_shuffle_mask)))]>;
1927 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1928 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1929 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
1931 (v2i64 (vector_shuffle VR128:$src1,
1932 (memopv2i64 addr:$src2),
1933 UNPCKL_shuffle_mask)))]>;
1935 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1936 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1937 "punpckhbw\t{$src2, $dst|$dst, $src2}",
1939 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1940 UNPCKH_shuffle_mask)))]>;
1941 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1943 "punpckhbw\t{$src2, $dst|$dst, $src2}",
1945 (v16i8 (vector_shuffle VR128:$src1,
1946 (bc_v16i8 (memopv2i64 addr:$src2)),
1947 UNPCKH_shuffle_mask)))]>;
1948 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1949 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1950 "punpckhwd\t{$src2, $dst|$dst, $src2}",
1952 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1953 UNPCKH_shuffle_mask)))]>;
1954 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1955 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1956 "punpckhwd\t{$src2, $dst|$dst, $src2}",
1958 (v8i16 (vector_shuffle VR128:$src1,
1959 (bc_v8i16 (memopv2i64 addr:$src2)),
1960 UNPCKH_shuffle_mask)))]>;
1961 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1962 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1963 "punpckhdq\t{$src2, $dst|$dst, $src2}",
1965 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1966 UNPCKH_shuffle_mask)))]>;
1967 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1968 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1969 "punpckhdq\t{$src2, $dst|$dst, $src2}",
1971 (v4i32 (vector_shuffle VR128:$src1,
1972 (bc_v4i32 (memopv2i64 addr:$src2)),
1973 UNPCKH_shuffle_mask)))]>;
1974 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1975 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1976 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
1978 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1979 UNPCKH_shuffle_mask)))]>;
1980 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1981 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1982 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
1984 (v2i64 (vector_shuffle VR128:$src1,
1985 (memopv2i64 addr:$src2),
1986 UNPCKH_shuffle_mask)))]>;
1990 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
1991 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
1992 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1993 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
1994 (iPTR imm:$src2)))]>;
1995 let isTwoAddress = 1 in {
1996 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
1997 (outs VR128:$dst), (ins VR128:$src1,
1998 GR32:$src2, i32i8imm:$src3),
1999 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2001 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2002 GR32:$src2, (iPTR imm:$src3))))]>;
2003 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2004 (outs VR128:$dst), (ins VR128:$src1,
2005 i16mem:$src2, i32i8imm:$src3),
2006 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2008 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2009 (i32 (anyext (loadi16 addr:$src2))),
2010 (iPTR imm:$src3))))]>;
2014 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2015 "pmovmskb\t{$src, $dst|$dst, $src}",
2016 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2018 // Conditional store
2020 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2021 "maskmovdqu\t{$mask, $src|$src, $mask}",
2022 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2024 // Non-temporal stores
2025 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2026 "movntpd\t{$src, $dst|$dst, $src}",
2027 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2028 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2029 "movntdq\t{$src, $dst|$dst, $src}",
2030 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2031 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2032 "movnti\t{$src, $dst|$dst, $src}",
2033 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2034 TB, Requires<[HasSSE2]>;
2037 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2038 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2039 TB, Requires<[HasSSE2]>;
2041 // Load, store, and memory fence
2042 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2043 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2044 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2045 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2048 // Alias instructions that map zero vector to pxor / xorp* for sse.
2049 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2050 let isReMaterializable = 1 in
2051 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2052 "pcmpeqd\t$dst, $dst",
2053 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2055 // FR64 to 128-bit vector conversion.
2056 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2057 "movsd\t{$src, $dst|$dst, $src}",
2059 (v2f64 (scalar_to_vector FR64:$src)))]>;
2060 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2061 "movsd\t{$src, $dst|$dst, $src}",
2063 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2065 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2066 "movd\t{$src, $dst|$dst, $src}",
2068 (v4i32 (scalar_to_vector GR32:$src)))]>;
2069 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2070 "movd\t{$src, $dst|$dst, $src}",
2072 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2074 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2075 "movd\t{$src, $dst|$dst, $src}",
2076 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2078 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2079 "movd\t{$src, $dst|$dst, $src}",
2080 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2082 // SSE2 instructions with XS prefix
2083 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2084 "movq\t{$src, $dst|$dst, $src}",
2086 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2087 Requires<[HasSSE2]>;
2088 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2089 "movq\t{$src, $dst|$dst, $src}",
2090 [(store (i64 (vector_extract (v2i64 VR128:$src),
2091 (iPTR 0))), addr:$dst)]>;
2093 // FIXME: may not be able to eliminate this movss with coalescing the src and
2094 // dest register classes are different. We really want to write this pattern
2096 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2097 // (f32 FR32:$src)>;
2098 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2099 "movsd\t{$src, $dst|$dst, $src}",
2100 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2102 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2103 "movsd\t{$src, $dst|$dst, $src}",
2104 [(store (f64 (vector_extract (v2f64 VR128:$src),
2105 (iPTR 0))), addr:$dst)]>;
2106 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2107 "movd\t{$src, $dst|$dst, $src}",
2108 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2110 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2111 "movd\t{$src, $dst|$dst, $src}",
2112 [(store (i32 (vector_extract (v4i32 VR128:$src),
2113 (iPTR 0))), addr:$dst)]>;
2115 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2116 "movd\t{$src, $dst|$dst, $src}",
2117 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2118 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2119 "movd\t{$src, $dst|$dst, $src}",
2120 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2123 // Move to lower bits of a VR128, leaving upper bits alone.
2124 // Three operand (but two address) aliases.
2125 let isTwoAddress = 1 in {
2126 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2127 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2128 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2130 let AddedComplexity = 15 in
2131 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2132 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2133 "movsd\t{$src2, $dst|$dst, $src2}",
2135 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2136 MOVL_shuffle_mask)))]>;
2139 // Store / copy lower 64-bits of a XMM register.
2140 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2141 "movq\t{$src, $dst|$dst, $src}",
2142 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2144 // Move to lower bits of a VR128 and zeroing upper bits.
2145 // Loading from memory automatically zeroing upper bits.
2146 let AddedComplexity = 20 in
2147 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2148 "movsd\t{$src, $dst|$dst, $src}",
2150 (v2f64 (vector_shuffle immAllZerosV,
2151 (v2f64 (scalar_to_vector
2152 (loadf64 addr:$src))),
2153 MOVL_shuffle_mask)))]>;
2155 let AddedComplexity = 15 in
2156 // movd / movq to XMM register zero-extends
2157 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2158 "movd\t{$src, $dst|$dst, $src}",
2160 (v4i32 (vector_shuffle immAllZerosV,
2161 (v4i32 (scalar_to_vector GR32:$src)),
2162 MOVL_shuffle_mask)))]>;
2163 let AddedComplexity = 20 in
2164 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2165 "movd\t{$src, $dst|$dst, $src}",
2167 (v4i32 (vector_shuffle immAllZerosV,
2168 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2169 MOVL_shuffle_mask)))]>;
2171 // Moving from XMM to XMM but still clear upper 64 bits.
2172 let AddedComplexity = 15 in
2173 def MOVZQI2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "movq\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>,
2176 XS, Requires<[HasSSE2]>;
2177 let AddedComplexity = 20 in
2178 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2179 "movq\t{$src, $dst|$dst, $src}",
2180 [(set VR128:$dst, (int_x86_sse2_movl_dq
2181 (bitconvert (memopv2i64 addr:$src))))]>,
2182 XS, Requires<[HasSSE2]>;
2185 //===----------------------------------------------------------------------===//
2186 // SSE3 Instructions
2187 //===----------------------------------------------------------------------===//
2189 // Move Instructions
2190 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2191 "movshdup\t{$src, $dst|$dst, $src}",
2192 [(set VR128:$dst, (v4f32 (vector_shuffle
2193 VR128:$src, (undef),
2194 MOVSHDUP_shuffle_mask)))]>;
2195 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2196 "movshdup\t{$src, $dst|$dst, $src}",
2197 [(set VR128:$dst, (v4f32 (vector_shuffle
2198 (memopv4f32 addr:$src), (undef),
2199 MOVSHDUP_shuffle_mask)))]>;
2201 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2202 "movsldup\t{$src, $dst|$dst, $src}",
2203 [(set VR128:$dst, (v4f32 (vector_shuffle
2204 VR128:$src, (undef),
2205 MOVSLDUP_shuffle_mask)))]>;
2206 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2207 "movsldup\t{$src, $dst|$dst, $src}",
2208 [(set VR128:$dst, (v4f32 (vector_shuffle
2209 (memopv4f32 addr:$src), (undef),
2210 MOVSLDUP_shuffle_mask)))]>;
2212 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2213 "movddup\t{$src, $dst|$dst, $src}",
2214 [(set VR128:$dst, (v2f64 (vector_shuffle
2215 VR128:$src, (undef),
2216 SSE_splat_lo_mask)))]>;
2217 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2218 "movddup\t{$src, $dst|$dst, $src}",
2220 (v2f64 (vector_shuffle
2221 (scalar_to_vector (loadf64 addr:$src)),
2223 SSE_splat_lo_mask)))]>;
2226 let isTwoAddress = 1 in {
2227 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2228 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2229 "addsubps\t{$src2, $dst|$dst, $src2}",
2230 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2232 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2233 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2234 "addsubps\t{$src2, $dst|$dst, $src2}",
2235 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2236 (load addr:$src2)))]>;
2237 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2238 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2239 "addsubpd\t{$src2, $dst|$dst, $src2}",
2240 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2242 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2243 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2244 "addsubpd\t{$src2, $dst|$dst, $src2}",
2245 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2246 (load addr:$src2)))]>;
2249 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2250 "lddqu\t{$src, $dst|$dst, $src}",
2251 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2254 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2255 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2256 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2257 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2258 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2259 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2260 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2261 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2262 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2263 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2264 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2265 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2266 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2267 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2268 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2269 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2271 let isTwoAddress = 1 in {
2272 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2273 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2274 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2275 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2276 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2277 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2278 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2279 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2282 // Thread synchronization
2283 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2284 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2285 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2286 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2288 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2289 let AddedComplexity = 15 in
2290 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2291 MOVSHDUP_shuffle_mask)),
2292 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2293 let AddedComplexity = 20 in
2294 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2295 MOVSHDUP_shuffle_mask)),
2296 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2298 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2299 let AddedComplexity = 15 in
2300 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2301 MOVSLDUP_shuffle_mask)),
2302 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2303 let AddedComplexity = 20 in
2304 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2305 MOVSLDUP_shuffle_mask)),
2306 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2308 //===----------------------------------------------------------------------===//
2309 // SSSE3 Instructions
2310 //===----------------------------------------------------------------------===//
2312 // SSSE3 Instruction Templates:
2314 // SS38I - SSSE3 instructions with T8 prefix.
2315 // SS3AI - SSSE3 instructions with TA prefix.
2317 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
2318 // uses the MMX registers. We put those instructions here because they better
2319 // fit into the SSSE3 instruction category rather than the MMX category.
2321 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
2323 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
2324 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
2326 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
2328 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2329 let isTwoAddress = 1 in {
2330 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2331 Intrinsic IntId64, Intrinsic IntId128,
2332 bit Commutable = 0> {
2333 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2334 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2335 [(set VR64:$dst, (IntId64 VR64:$src))]> {
2336 let isCommutable = Commutable;
2338 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2339 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2341 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2343 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2345 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2346 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2348 let isCommutable = Commutable;
2350 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2352 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2355 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2359 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2360 let isTwoAddress = 1 in {
2361 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2362 Intrinsic IntId64, Intrinsic IntId128,
2363 bit Commutable = 0> {
2364 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2366 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2367 [(set VR64:$dst, (IntId64 VR64:$src))]> {
2368 let isCommutable = Commutable;
2370 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2375 (bitconvert (memopv4i16 addr:$src))))]>;
2377 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2379 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2380 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2382 let isCommutable = Commutable;
2384 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2386 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2389 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2393 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2394 let isTwoAddress = 1 in {
2395 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2396 Intrinsic IntId64, Intrinsic IntId128,
2397 bit Commutable = 0> {
2398 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2400 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2401 [(set VR64:$dst, (IntId64 VR64:$src))]> {
2402 let isCommutable = Commutable;
2404 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2406 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2409 (bitconvert (memopv2i32 addr:$src))))]>;
2411 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2413 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2414 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2416 let isCommutable = Commutable;
2418 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2420 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2423 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2427 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2428 int_x86_ssse3_pabs_b,
2429 int_x86_ssse3_pabs_b_128>;
2430 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2431 int_x86_ssse3_pabs_w,
2432 int_x86_ssse3_pabs_w_128>;
2433 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2434 int_x86_ssse3_pabs_d,
2435 int_x86_ssse3_pabs_d_128>;
2437 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2438 let isTwoAddress = 1 in {
2439 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2440 Intrinsic IntId64, Intrinsic IntId128,
2441 bit Commutable = 0> {
2442 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2443 (ins VR64:$src1, VR64:$src2),
2444 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2445 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2446 let isCommutable = Commutable;
2448 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2449 (ins VR64:$src1, i64mem:$src2),
2450 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2452 (IntId64 VR64:$src1,
2453 (bitconvert (memopv8i8 addr:$src2))))]>;
2455 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2456 (ins VR128:$src1, VR128:$src2),
2457 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2458 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2460 let isCommutable = Commutable;
2462 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2463 (ins VR128:$src1, i128mem:$src2),
2464 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2466 (IntId128 VR128:$src1,
2467 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2471 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2472 let isTwoAddress = 1 in {
2473 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2474 Intrinsic IntId64, Intrinsic IntId128,
2475 bit Commutable = 0> {
2476 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2477 (ins VR64:$src1, VR64:$src2),
2478 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2479 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2480 let isCommutable = Commutable;
2482 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2483 (ins VR64:$src1, i64mem:$src2),
2484 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2486 (IntId64 VR64:$src1,
2487 (bitconvert (memopv4i16 addr:$src2))))]>;
2489 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2490 (ins VR128:$src1, VR128:$src2),
2491 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2492 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2494 let isCommutable = Commutable;
2496 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2497 (ins VR128:$src1, i128mem:$src2),
2498 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2500 (IntId128 VR128:$src1,
2501 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2505 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2506 let isTwoAddress = 1 in {
2507 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2508 Intrinsic IntId64, Intrinsic IntId128,
2509 bit Commutable = 0> {
2510 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2511 (ins VR64:$src1, VR64:$src2),
2512 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2513 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2514 let isCommutable = Commutable;
2516 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2517 (ins VR64:$src1, i64mem:$src2),
2518 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2520 (IntId64 VR64:$src1,
2521 (bitconvert (memopv2i32 addr:$src2))))]>;
2523 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2524 (ins VR128:$src1, VR128:$src2),
2525 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2526 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2528 let isCommutable = Commutable;
2530 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2531 (ins VR128:$src1, i128mem:$src2),
2532 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2534 (IntId128 VR128:$src1,
2535 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2539 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2540 int_x86_ssse3_phadd_w,
2541 int_x86_ssse3_phadd_w_128, 1>;
2542 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2543 int_x86_ssse3_phadd_d,
2544 int_x86_ssse3_phadd_d_128, 1>;
2545 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2546 int_x86_ssse3_phadd_sw,
2547 int_x86_ssse3_phadd_sw_128, 1>;
2548 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2549 int_x86_ssse3_phsub_w,
2550 int_x86_ssse3_phsub_w_128>;
2551 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2552 int_x86_ssse3_phsub_d,
2553 int_x86_ssse3_phsub_d_128>;
2554 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2555 int_x86_ssse3_phsub_sw,
2556 int_x86_ssse3_phsub_sw_128>;
2557 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2558 int_x86_ssse3_pmadd_ub_sw,
2559 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2560 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2561 int_x86_ssse3_pmul_hr_sw,
2562 int_x86_ssse3_pmul_hr_sw_128, 1>;
2563 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2564 int_x86_ssse3_pshuf_b,
2565 int_x86_ssse3_pshuf_b_128>;
2566 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2567 int_x86_ssse3_psign_b,
2568 int_x86_ssse3_psign_b_128>;
2569 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2570 int_x86_ssse3_psign_w,
2571 int_x86_ssse3_psign_w_128>;
2572 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2573 int_x86_ssse3_psign_d,
2574 int_x86_ssse3_psign_d_128>;
2576 let isTwoAddress = 1 in {
2577 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2578 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2579 "palignr\t{$src2, $dst|$dst, $src2}",
2581 (int_x86_ssse3_palign_r
2582 VR64:$src1, VR64:$src2,
2584 def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2585 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2586 "palignr\t{$src2, $dst|$dst, $src2}",
2588 (int_x86_ssse3_palign_r
2590 (bitconvert (memopv2i32 addr:$src2)),
2593 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2594 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2595 "palignr\t{$src2, $dst|$dst, $src2}",
2597 (int_x86_ssse3_palign_r_128
2598 VR128:$src1, VR128:$src2,
2599 imm:$src3))]>, OpSize;
2600 def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2601 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2602 "palignr\t{$src2, $dst|$dst, $src2}",
2604 (int_x86_ssse3_palign_r_128
2606 (bitconvert (memopv4i32 addr:$src2)),
2607 imm:$src3))]>, OpSize;
2610 //===----------------------------------------------------------------------===//
2611 // Non-Instruction Patterns
2612 //===----------------------------------------------------------------------===//
2614 // 128-bit vector undef's.
2615 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2616 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2617 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2618 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2619 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2620 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2622 // 128-bit vector all zero's.
2623 def : Pat<(v16i8 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2624 def : Pat<(v8i16 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2625 def : Pat<(v4i32 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2626 def : Pat<(v2i64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2627 def : Pat<(v2f64 immAllZerosV), (V_SET0)>, Requires<[HasSSE2]>;
2629 // 128-bit vector all one's.
2630 def : Pat<(v16i8 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2631 def : Pat<(v8i16 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2632 def : Pat<(v4i32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2633 def : Pat<(v2i64 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE2]>;
2634 def : Pat<(v4f32 immAllOnesV), (V_SETALLONES)>, Requires<[HasSSE1]>;
2637 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2639 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2640 Requires<[HasSSE2]>;
2641 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2642 Requires<[HasSSE2]>;
2645 let Predicates = [HasSSE2] in {
2646 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2647 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2648 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2649 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2650 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2651 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2652 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2653 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2654 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2655 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2656 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2657 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2658 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2659 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2660 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2661 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2662 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2663 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2664 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2665 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2666 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2667 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2668 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2669 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2670 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2671 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2672 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2673 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2674 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2675 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2678 // Move scalar to XMM zero-extended
2679 // movd to XMM register zero-extends
2680 let AddedComplexity = 15 in {
2681 def : Pat<(v8i16 (vector_shuffle immAllZerosV,
2682 (v8i16 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2683 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2684 def : Pat<(v16i8 (vector_shuffle immAllZerosV,
2685 (v16i8 (X86s2vec GR32:$src)), MOVL_shuffle_mask)),
2686 (MOVZDI2PDIrr GR32:$src)>, Requires<[HasSSE2]>;
2687 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2688 def : Pat<(v2f64 (vector_shuffle immAllZerosV,
2689 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2690 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2691 def : Pat<(v4f32 (vector_shuffle immAllZerosV,
2692 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2693 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2696 // Splat v2f64 / v2i64
2697 let AddedComplexity = 10 in {
2698 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2699 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2700 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2701 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2702 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2703 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2704 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2705 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2709 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2710 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2711 Requires<[HasSSE1]>;
2713 // Special unary SHUFPSrri case.
2714 // FIXME: when we want non two-address code, then we should use PSHUFD?
2715 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2716 SHUFP_unary_shuffle_mask:$sm),
2717 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2718 Requires<[HasSSE1]>;
2719 // Special unary SHUFPDrri case.
2720 def : Pat<(vector_shuffle (v2f64 VR128:$src1), (undef),
2721 SHUFP_unary_shuffle_mask:$sm),
2722 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2723 Requires<[HasSSE2]>;
2724 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2725 def : Pat<(vector_shuffle (memopv4f32 addr:$src1), (undef),
2726 SHUFP_unary_shuffle_mask:$sm),
2727 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2728 Requires<[HasSSE2]>;
2729 // Special binary v4i32 shuffle cases with SHUFPS.
2730 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2731 PSHUFD_binary_shuffle_mask:$sm),
2732 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2733 Requires<[HasSSE2]>;
2734 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2735 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2736 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2737 Requires<[HasSSE2]>;
2739 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2740 let AddedComplexity = 10 in {
2741 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2742 UNPCKL_v_undef_shuffle_mask)),
2743 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2744 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2745 UNPCKL_v_undef_shuffle_mask)),
2746 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2747 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2748 UNPCKL_v_undef_shuffle_mask)),
2749 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2750 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2751 UNPCKL_v_undef_shuffle_mask)),
2752 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2755 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2756 let AddedComplexity = 10 in {
2757 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2758 UNPCKH_v_undef_shuffle_mask)),
2759 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2760 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2761 UNPCKH_v_undef_shuffle_mask)),
2762 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2763 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2764 UNPCKH_v_undef_shuffle_mask)),
2765 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2766 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2767 UNPCKH_v_undef_shuffle_mask)),
2768 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2771 let AddedComplexity = 15 in {
2772 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2773 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2774 MOVHP_shuffle_mask)),
2775 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2777 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2778 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2779 MOVHLPS_shuffle_mask)),
2780 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2782 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2783 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2784 MOVHLPS_v_undef_shuffle_mask)),
2785 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2786 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2787 MOVHLPS_v_undef_shuffle_mask)),
2788 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2791 let AddedComplexity = 20 in {
2792 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2793 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2794 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2795 MOVLP_shuffle_mask)),
2796 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2797 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2798 MOVLP_shuffle_mask)),
2799 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2800 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2801 MOVHP_shuffle_mask)),
2802 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2803 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2804 MOVHP_shuffle_mask)),
2805 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2807 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2808 MOVLP_shuffle_mask)),
2809 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2810 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2811 MOVLP_shuffle_mask)),
2812 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2813 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2814 MOVHP_shuffle_mask)),
2815 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2816 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2817 MOVLP_shuffle_mask)),
2818 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2821 let AddedComplexity = 15 in {
2822 // Setting the lowest element in the vector.
2823 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2824 MOVL_shuffle_mask)),
2825 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2826 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2827 MOVL_shuffle_mask)),
2828 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2830 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2831 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2832 MOVLP_shuffle_mask)),
2833 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2834 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2835 MOVLP_shuffle_mask)),
2836 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2839 // Set lowest element and zero upper elements.
2840 let AddedComplexity = 20 in
2841 def : Pat<(bc_v2i64 (vector_shuffle immAllZerosV,
2842 (v2f64 (scalar_to_vector (loadf64 addr:$src))),
2843 MOVL_shuffle_mask)),
2844 (MOVZQI2PQIrm addr:$src)>, Requires<[HasSSE2]>;
2846 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2847 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2848 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2849 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2850 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2851 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2852 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2853 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2854 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2855 Requires<[HasSSE2]>;
2856 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2857 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2858 Requires<[HasSSE2]>;
2859 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2860 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2861 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2862 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2863 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2864 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2865 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2866 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2867 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2868 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2869 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2870 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2871 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2872 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2873 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2874 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2876 // Some special case pandn patterns.
2877 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2879 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2880 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2882 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2883 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2885 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2887 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2888 (memopv2i64 addr:$src2))),
2889 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2890 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2891 (memopv2i64 addr:$src2))),
2892 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2893 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2894 (memopv2i64 addr:$src2))),
2895 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2897 // Use movaps / movups for SSE integer load / store (one byte shorter).
2898 def : Pat<(alignedloadv4i32 addr:$src),
2899 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
2900 def : Pat<(loadv4i32 addr:$src),
2901 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
2902 def : Pat<(alignedloadv2i64 addr:$src),
2903 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
2904 def : Pat<(loadv2i64 addr:$src),
2905 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
2907 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
2908 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2909 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
2910 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2911 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
2912 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2913 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
2914 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2915 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
2916 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2917 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2918 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2919 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2920 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2921 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2922 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2924 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr)
2925 def : Pat<(vector_extract
2926 (bc_v4i32 (v4f32 (scalar_to_vector (loadf32 addr:$src)))), (iPTR 0)),
2927 (MOV32rm addr:$src)>, Requires<[HasSSE2]>;
2928 def : Pat<(vector_extract
2929 (bc_v2i64 (v2f64 (scalar_to_vector (loadf64 addr:$src)))), (iPTR 0)),
2930 (MOV64rm addr:$src)>, Requires<[HasSSE2, In64BitMode]>;