1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pextrb : SDNode<"X86ISD::PEXTRB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
41 def X86pextrw : SDNode<"X86ISD::PEXTRW",
42 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
43 def X86pinsrb : SDNode<"X86ISD::PINSRB",
44 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
45 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
46 def X86pinsrw : SDNode<"X86ISD::PINSRW",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86insrtps : SDNode<"X86ISD::INSERTPS",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, f32>, SDTCisPtrTy<3>]>>;
52 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
53 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
54 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
55 [SDNPHasChain, SDNPMayLoad]>;
56 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
57 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
58 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
59 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
60 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
61 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
62 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
63 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
65 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
66 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
67 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
69 //===----------------------------------------------------------------------===//
70 // SSE Complex Patterns
71 //===----------------------------------------------------------------------===//
73 // These are 'extloads' from a scalar to the low element of a vector, zeroing
74 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
76 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
77 [SDNPHasChain, SDNPMayLoad]>;
78 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
79 [SDNPHasChain, SDNPMayLoad]>;
81 def ssmem : Operand<v4f32> {
82 let PrintMethod = "printf32mem";
83 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
85 def sdmem : Operand<v2f64> {
86 let PrintMethod = "printf64mem";
87 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
90 //===----------------------------------------------------------------------===//
91 // SSE pattern fragments
92 //===----------------------------------------------------------------------===//
94 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
95 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
96 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
97 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
99 // Like 'store', but always requires vector alignment.
100 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
101 (st node:$val, node:$ptr), [{
102 StoreSDNode *ST = cast<StoreSDNode>(N);
103 return !ST->isTruncatingStore() &&
104 ST->getAddressingMode() == ISD::UNINDEXED &&
105 ST->getAlignment() >= 16;
108 // Like 'load', but always requires vector alignment.
109 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
110 LoadSDNode *LD = cast<LoadSDNode>(N);
111 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
112 LD->getAddressingMode() == ISD::UNINDEXED &&
113 LD->getAlignment() >= 16;
116 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
117 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
118 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
119 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
120 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
121 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
123 // Like 'load', but uses special alignment checks suitable for use in
124 // memory operands in most SSE instructions, which are required to
125 // be naturally aligned on some targets but not on others.
126 // FIXME: Actually implement support for targets that don't require the
127 // alignment. This probably wants a subtarget predicate.
128 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
129 LoadSDNode *LD = cast<LoadSDNode>(N);
130 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
131 LD->getAddressingMode() == ISD::UNINDEXED &&
132 LD->getAlignment() >= 16;
135 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
136 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
137 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
138 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
139 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
140 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
141 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
143 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
145 // FIXME: 8 byte alignment for mmx reads is not required
146 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
147 LoadSDNode *LD = cast<LoadSDNode>(N);
148 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
149 LD->getAddressingMode() == ISD::UNINDEXED &&
150 LD->getAlignment() >= 8;
153 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
154 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
155 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
156 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
158 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
159 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
160 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
161 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
162 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
163 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
165 def fp32imm0 : PatLeaf<(f32 fpimm), [{
166 return N->isExactlyValue(+0.0);
169 def PSxLDQ_imm : SDNodeXForm<imm, [{
170 // Transformation function: imm >> 3
171 return getI32Imm(N->getZExtValue() >> 3);
174 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
176 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
177 return getI8Imm(X86::getShuffleSHUFImmediate(N));
180 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
182 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
183 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
186 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
188 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
189 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
192 def SSE_splat_mask : PatLeaf<(build_vector), [{
193 return X86::isSplatMask(N);
194 }], SHUFFLE_get_shuf_imm>;
196 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
197 return X86::isSplatLoMask(N);
200 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
201 return X86::isMOVHLPSMask(N);
204 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
205 return X86::isMOVHLPS_v_undef_Mask(N);
208 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
209 return X86::isMOVHPMask(N);
212 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
213 return X86::isMOVLPMask(N);
216 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
217 return X86::isMOVLMask(N);
220 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
221 return X86::isMOVSHDUPMask(N);
224 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
225 return X86::isMOVSLDUPMask(N);
228 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
229 return X86::isUNPCKLMask(N);
232 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
233 return X86::isUNPCKHMask(N);
236 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
237 return X86::isUNPCKL_v_undef_Mask(N);
240 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
241 return X86::isUNPCKH_v_undef_Mask(N);
244 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
245 return X86::isPSHUFDMask(N);
246 }], SHUFFLE_get_shuf_imm>;
248 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
249 return X86::isPSHUFHWMask(N);
250 }], SHUFFLE_get_pshufhw_imm>;
252 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
253 return X86::isPSHUFLWMask(N);
254 }], SHUFFLE_get_pshuflw_imm>;
256 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
257 return X86::isPSHUFDMask(N);
258 }], SHUFFLE_get_shuf_imm>;
260 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
261 return X86::isSHUFPMask(N);
262 }], SHUFFLE_get_shuf_imm>;
264 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
265 return X86::isSHUFPMask(N);
266 }], SHUFFLE_get_shuf_imm>;
269 //===----------------------------------------------------------------------===//
270 // SSE scalar FP Instructions
271 //===----------------------------------------------------------------------===//
273 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
274 // scheduler into a branch sequence.
275 // These are expanded by the scheduler.
276 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
277 def CMOV_FR32 : I<0, Pseudo,
278 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
279 "#CMOV_FR32 PSEUDO!",
280 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
282 def CMOV_FR64 : I<0, Pseudo,
283 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
284 "#CMOV_FR64 PSEUDO!",
285 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
287 def CMOV_V4F32 : I<0, Pseudo,
288 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
289 "#CMOV_V4F32 PSEUDO!",
291 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
293 def CMOV_V2F64 : I<0, Pseudo,
294 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
295 "#CMOV_V2F64 PSEUDO!",
297 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
299 def CMOV_V2I64 : I<0, Pseudo,
300 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
301 "#CMOV_V2I64 PSEUDO!",
303 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
307 //===----------------------------------------------------------------------===//
309 //===----------------------------------------------------------------------===//
312 let neverHasSideEffects = 1 in
313 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
314 "movss\t{$src, $dst|$dst, $src}", []>;
315 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
316 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
317 "movss\t{$src, $dst|$dst, $src}",
318 [(set FR32:$dst, (loadf32 addr:$src))]>;
319 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
320 "movss\t{$src, $dst|$dst, $src}",
321 [(store FR32:$src, addr:$dst)]>;
323 // Conversion instructions
324 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
325 "cvttss2si\t{$src, $dst|$dst, $src}",
326 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
327 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
328 "cvttss2si\t{$src, $dst|$dst, $src}",
329 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
330 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
331 "cvtsi2ss\t{$src, $dst|$dst, $src}",
332 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
333 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
334 "cvtsi2ss\t{$src, $dst|$dst, $src}",
335 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
337 // Match intrinsics which expect XMM operand(s).
338 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
339 "cvtss2si\t{$src, $dst|$dst, $src}",
340 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
341 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
342 "cvtss2si\t{$src, $dst|$dst, $src}",
343 [(set GR32:$dst, (int_x86_sse_cvtss2si
344 (load addr:$src)))]>;
346 // Match intrinisics which expect MM and XMM operand(s).
347 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
348 "cvtps2pi\t{$src, $dst|$dst, $src}",
349 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
350 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
351 "cvtps2pi\t{$src, $dst|$dst, $src}",
352 [(set VR64:$dst, (int_x86_sse_cvtps2pi
353 (load addr:$src)))]>;
354 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
355 "cvttps2pi\t{$src, $dst|$dst, $src}",
356 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
357 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
358 "cvttps2pi\t{$src, $dst|$dst, $src}",
359 [(set VR64:$dst, (int_x86_sse_cvttps2pi
360 (load addr:$src)))]>;
361 let Constraints = "$src1 = $dst" in {
362 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
363 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
364 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
365 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
367 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
368 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
369 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
370 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
371 (load addr:$src2)))]>;
374 // Aliases for intrinsics
375 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
376 "cvttss2si\t{$src, $dst|$dst, $src}",
378 (int_x86_sse_cvttss2si VR128:$src))]>;
379 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
380 "cvttss2si\t{$src, $dst|$dst, $src}",
382 (int_x86_sse_cvttss2si(load addr:$src)))]>;
384 let Constraints = "$src1 = $dst" in {
385 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
386 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
387 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
388 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
390 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
391 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
392 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
393 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
394 (loadi32 addr:$src2)))]>;
397 // Comparison instructions
398 let Constraints = "$src1 = $dst" in {
399 let neverHasSideEffects = 1 in
400 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
401 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
402 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
403 let neverHasSideEffects = 1, mayLoad = 1 in
404 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
405 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
406 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
409 let Defs = [EFLAGS] in {
410 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
411 "ucomiss\t{$src2, $src1|$src1, $src2}",
412 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
413 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
414 "ucomiss\t{$src2, $src1|$src1, $src2}",
415 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
419 // Aliases to match intrinsics which expect XMM operand(s).
420 let Constraints = "$src1 = $dst" in {
421 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
422 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
423 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
424 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
425 VR128:$src, imm:$cc))]>;
426 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
427 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
428 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
429 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
430 (load addr:$src), imm:$cc))]>;
433 let Defs = [EFLAGS] in {
434 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
435 (ins VR128:$src1, VR128:$src2),
436 "ucomiss\t{$src2, $src1|$src1, $src2}",
437 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
439 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
440 (ins VR128:$src1, f128mem:$src2),
441 "ucomiss\t{$src2, $src1|$src1, $src2}",
442 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
445 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
446 (ins VR128:$src1, VR128:$src2),
447 "comiss\t{$src2, $src1|$src1, $src2}",
448 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
450 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
451 (ins VR128:$src1, f128mem:$src2),
452 "comiss\t{$src2, $src1|$src1, $src2}",
453 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
457 // Aliases of packed SSE1 instructions for scalar use. These all have names that
460 // Alias instructions that map fld0 to pxor for sse.
461 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
462 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
463 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
464 Requires<[HasSSE1]>, TB, OpSize;
466 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
468 let neverHasSideEffects = 1 in
469 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
470 "movaps\t{$src, $dst|$dst, $src}", []>;
472 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
474 let isSimpleLoad = 1 in
475 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
476 "movaps\t{$src, $dst|$dst, $src}",
477 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
479 // Alias bitwise logical operations using SSE logical ops on packed FP values.
480 let Constraints = "$src1 = $dst" in {
481 let isCommutable = 1 in {
482 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
483 "andps\t{$src2, $dst|$dst, $src2}",
484 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
485 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
486 "orps\t{$src2, $dst|$dst, $src2}",
487 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
488 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
489 "xorps\t{$src2, $dst|$dst, $src2}",
490 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
493 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
494 "andps\t{$src2, $dst|$dst, $src2}",
495 [(set FR32:$dst, (X86fand FR32:$src1,
496 (memopfsf32 addr:$src2)))]>;
497 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
498 "orps\t{$src2, $dst|$dst, $src2}",
499 [(set FR32:$dst, (X86for FR32:$src1,
500 (memopfsf32 addr:$src2)))]>;
501 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
502 "xorps\t{$src2, $dst|$dst, $src2}",
503 [(set FR32:$dst, (X86fxor FR32:$src1,
504 (memopfsf32 addr:$src2)))]>;
505 let neverHasSideEffects = 1 in {
506 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
507 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
508 "andnps\t{$src2, $dst|$dst, $src2}", []>;
511 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
512 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
513 "andnps\t{$src2, $dst|$dst, $src2}", []>;
517 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
519 /// In addition, we also have a special variant of the scalar form here to
520 /// represent the associated intrinsic operation. This form is unlike the
521 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
522 /// and leaves the top elements undefined.
524 /// These three forms can each be reg+reg or reg+mem, so there are a total of
525 /// six "instructions".
527 let Constraints = "$src1 = $dst" in {
528 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
529 SDNode OpNode, Intrinsic F32Int,
530 bit Commutable = 0> {
531 // Scalar operation, reg+reg.
532 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
533 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
534 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
535 let isCommutable = Commutable;
538 // Scalar operation, reg+mem.
539 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
540 (ins FR32:$src1, f32mem:$src2),
541 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
542 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
544 // Vector operation, reg+reg.
545 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
546 (ins VR128:$src1, VR128:$src2),
547 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
548 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
549 let isCommutable = Commutable;
552 // Vector operation, reg+mem.
553 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
554 (ins VR128:$src1, f128mem:$src2),
555 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
556 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
558 // Intrinsic operation, reg+reg.
559 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
560 (ins VR128:$src1, VR128:$src2),
561 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
562 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
563 let isCommutable = Commutable;
566 // Intrinsic operation, reg+mem.
567 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
568 (ins VR128:$src1, ssmem:$src2),
569 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
570 [(set VR128:$dst, (F32Int VR128:$src1,
571 sse_load_f32:$src2))]>;
575 // Arithmetic instructions
576 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
577 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
578 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
579 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
581 /// sse1_fp_binop_rm - Other SSE1 binops
583 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
584 /// instructions for a full-vector intrinsic form. Operations that map
585 /// onto C operators don't use this form since they just use the plain
586 /// vector form instead of having a separate vector intrinsic form.
588 /// This provides a total of eight "instructions".
590 let Constraints = "$src1 = $dst" in {
591 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
595 bit Commutable = 0> {
597 // Scalar operation, reg+reg.
598 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
599 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
600 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
601 let isCommutable = Commutable;
604 // Scalar operation, reg+mem.
605 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
606 (ins FR32:$src1, f32mem:$src2),
607 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
608 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
610 // Vector operation, reg+reg.
611 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
612 (ins VR128:$src1, VR128:$src2),
613 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
614 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
615 let isCommutable = Commutable;
618 // Vector operation, reg+mem.
619 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
620 (ins VR128:$src1, f128mem:$src2),
621 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
622 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
624 // Intrinsic operation, reg+reg.
625 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
626 (ins VR128:$src1, VR128:$src2),
627 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
628 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
629 let isCommutable = Commutable;
632 // Intrinsic operation, reg+mem.
633 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
634 (ins VR128:$src1, ssmem:$src2),
635 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
636 [(set VR128:$dst, (F32Int VR128:$src1,
637 sse_load_f32:$src2))]>;
639 // Vector intrinsic operation, reg+reg.
640 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
641 (ins VR128:$src1, VR128:$src2),
642 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
643 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
644 let isCommutable = Commutable;
647 // Vector intrinsic operation, reg+mem.
648 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
649 (ins VR128:$src1, f128mem:$src2),
650 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
651 [(set VR128:$dst, (V4F32Int VR128:$src1, (memopv4f32 addr:$src2)))]>;
655 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
656 int_x86_sse_max_ss, int_x86_sse_max_ps>;
657 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
658 int_x86_sse_min_ss, int_x86_sse_min_ps>;
660 //===----------------------------------------------------------------------===//
661 // SSE packed FP Instructions
664 let neverHasSideEffects = 1 in
665 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
666 "movaps\t{$src, $dst|$dst, $src}", []>;
667 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
668 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
669 "movaps\t{$src, $dst|$dst, $src}",
670 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
672 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
673 "movaps\t{$src, $dst|$dst, $src}",
674 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
676 let neverHasSideEffects = 1 in
677 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
678 "movups\t{$src, $dst|$dst, $src}", []>;
679 let isSimpleLoad = 1 in
680 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
681 "movups\t{$src, $dst|$dst, $src}",
682 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
683 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
684 "movups\t{$src, $dst|$dst, $src}",
685 [(store (v4f32 VR128:$src), addr:$dst)]>;
687 // Intrinsic forms of MOVUPS load and store
688 let isSimpleLoad = 1 in
689 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
690 "movups\t{$src, $dst|$dst, $src}",
691 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
692 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
693 "movups\t{$src, $dst|$dst, $src}",
694 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
696 let Constraints = "$src1 = $dst" in {
697 let AddedComplexity = 20 in {
698 def MOVLPSrm : PSI<0x12, MRMSrcMem,
699 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
700 "movlps\t{$src2, $dst|$dst, $src2}",
702 (v4f32 (vector_shuffle VR128:$src1,
703 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
704 MOVLP_shuffle_mask)))]>;
705 def MOVHPSrm : PSI<0x16, MRMSrcMem,
706 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
707 "movhps\t{$src2, $dst|$dst, $src2}",
709 (v4f32 (vector_shuffle VR128:$src1,
710 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
711 MOVHP_shuffle_mask)))]>;
713 } // Constraints = "$src1 = $dst"
716 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
717 "movlps\t{$src, $dst|$dst, $src}",
718 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
719 (iPTR 0))), addr:$dst)]>;
721 // v2f64 extract element 1 is always custom lowered to unpack high to low
722 // and extract element 0 so the non-store version isn't too horrible.
723 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
724 "movhps\t{$src, $dst|$dst, $src}",
725 [(store (f64 (vector_extract
726 (v2f64 (vector_shuffle
727 (bc_v2f64 (v4f32 VR128:$src)), (undef),
728 UNPCKH_shuffle_mask)), (iPTR 0))),
731 let Constraints = "$src1 = $dst" in {
732 let AddedComplexity = 15 in {
733 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
734 "movlhps\t{$src2, $dst|$dst, $src2}",
736 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
737 MOVHP_shuffle_mask)))]>;
739 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
740 "movhlps\t{$src2, $dst|$dst, $src2}",
742 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
743 MOVHLPS_shuffle_mask)))]>;
745 } // Constraints = "$src1 = $dst"
751 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
753 /// In addition, we also have a special variant of the scalar form here to
754 /// represent the associated intrinsic operation. This form is unlike the
755 /// plain scalar form, in that it takes an entire vector (instead of a
756 /// scalar) and leaves the top elements undefined.
758 /// And, we have a special variant form for a full-vector intrinsic form.
760 /// These four forms can each have a reg or a mem operand, so there are a
761 /// total of eight "instructions".
763 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
767 bit Commutable = 0> {
768 // Scalar operation, reg.
769 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
770 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
771 [(set FR32:$dst, (OpNode FR32:$src))]> {
772 let isCommutable = Commutable;
775 // Scalar operation, mem.
776 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
777 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
778 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
780 // Vector operation, reg.
781 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
782 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
783 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
784 let isCommutable = Commutable;
787 // Vector operation, mem.
788 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
789 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
790 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
792 // Intrinsic operation, reg.
793 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
794 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
795 [(set VR128:$dst, (F32Int VR128:$src))]> {
796 let isCommutable = Commutable;
799 // Intrinsic operation, mem.
800 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
801 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
802 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
804 // Vector intrinsic operation, reg
805 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
806 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
807 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
808 let isCommutable = Commutable;
811 // Vector intrinsic operation, mem
812 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
813 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
814 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
818 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
819 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
821 // Reciprocal approximations. Note that these typically require refinement
822 // in order to obtain suitable precision.
823 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
824 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
825 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
826 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
829 let Constraints = "$src1 = $dst" in {
830 let isCommutable = 1 in {
831 def ANDPSrr : PSI<0x54, MRMSrcReg,
832 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
833 "andps\t{$src2, $dst|$dst, $src2}",
834 [(set VR128:$dst, (v2i64
835 (and VR128:$src1, VR128:$src2)))]>;
836 def ORPSrr : PSI<0x56, MRMSrcReg,
837 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
838 "orps\t{$src2, $dst|$dst, $src2}",
839 [(set VR128:$dst, (v2i64
840 (or VR128:$src1, VR128:$src2)))]>;
841 def XORPSrr : PSI<0x57, MRMSrcReg,
842 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
843 "xorps\t{$src2, $dst|$dst, $src2}",
844 [(set VR128:$dst, (v2i64
845 (xor VR128:$src1, VR128:$src2)))]>;
848 def ANDPSrm : PSI<0x54, MRMSrcMem,
849 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
850 "andps\t{$src2, $dst|$dst, $src2}",
851 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
852 (memopv2i64 addr:$src2)))]>;
853 def ORPSrm : PSI<0x56, MRMSrcMem,
854 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
855 "orps\t{$src2, $dst|$dst, $src2}",
856 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
857 (memopv2i64 addr:$src2)))]>;
858 def XORPSrm : PSI<0x57, MRMSrcMem,
859 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
860 "xorps\t{$src2, $dst|$dst, $src2}",
861 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
862 (memopv2i64 addr:$src2)))]>;
863 def ANDNPSrr : PSI<0x55, MRMSrcReg,
864 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
865 "andnps\t{$src2, $dst|$dst, $src2}",
867 (v2i64 (and (xor VR128:$src1,
868 (bc_v2i64 (v4i32 immAllOnesV))),
870 def ANDNPSrm : PSI<0x55, MRMSrcMem,
871 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
872 "andnps\t{$src2, $dst|$dst, $src2}",
874 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
875 (bc_v2i64 (v4i32 immAllOnesV))),
876 (memopv2i64 addr:$src2))))]>;
879 let Constraints = "$src1 = $dst" in {
880 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
881 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
882 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
883 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
884 VR128:$src, imm:$cc))]>;
885 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
886 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
887 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
888 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
889 (memop addr:$src), imm:$cc))]>;
891 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
892 (CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
893 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
894 (CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
896 // Shuffle and unpack instructions
897 let Constraints = "$src1 = $dst" in {
898 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
899 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
900 (outs VR128:$dst), (ins VR128:$src1,
901 VR128:$src2, i32i8imm:$src3),
902 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
904 (v4f32 (vector_shuffle
905 VR128:$src1, VR128:$src2,
906 SHUFP_shuffle_mask:$src3)))]>;
907 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
908 (outs VR128:$dst), (ins VR128:$src1,
909 f128mem:$src2, i32i8imm:$src3),
910 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
912 (v4f32 (vector_shuffle
913 VR128:$src1, (memopv4f32 addr:$src2),
914 SHUFP_shuffle_mask:$src3)))]>;
916 let AddedComplexity = 10 in {
917 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
918 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
919 "unpckhps\t{$src2, $dst|$dst, $src2}",
921 (v4f32 (vector_shuffle
922 VR128:$src1, VR128:$src2,
923 UNPCKH_shuffle_mask)))]>;
924 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
925 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
926 "unpckhps\t{$src2, $dst|$dst, $src2}",
928 (v4f32 (vector_shuffle
929 VR128:$src1, (memopv4f32 addr:$src2),
930 UNPCKH_shuffle_mask)))]>;
932 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
933 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
934 "unpcklps\t{$src2, $dst|$dst, $src2}",
936 (v4f32 (vector_shuffle
937 VR128:$src1, VR128:$src2,
938 UNPCKL_shuffle_mask)))]>;
939 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
940 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
941 "unpcklps\t{$src2, $dst|$dst, $src2}",
943 (v4f32 (vector_shuffle
944 VR128:$src1, (memopv4f32 addr:$src2),
945 UNPCKL_shuffle_mask)))]>;
947 } // Constraints = "$src1 = $dst"
950 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
951 "movmskps\t{$src, $dst|$dst, $src}",
952 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
953 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
954 "movmskpd\t{$src, $dst|$dst, $src}",
955 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
957 // Prefetch intrinsic.
958 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
959 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
960 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
961 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
962 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
963 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
964 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
965 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
967 // Non-temporal stores
968 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
969 "movntps\t{$src, $dst|$dst, $src}",
970 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
972 // Load, store, and memory fence
973 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
976 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
977 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
978 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
979 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
981 // Alias instructions that map zero vector to pxor / xorp* for sse.
982 let isReMaterializable = 1 in
983 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
985 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
987 let Predicates = [HasSSE1] in {
988 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
989 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
990 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
991 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
992 def : Pat<(v4f32 immAllZerosV), (V_SET0)>;
995 // FR32 to 128-bit vector conversion.
996 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
997 "movss\t{$src, $dst|$dst, $src}",
999 (v4f32 (scalar_to_vector FR32:$src)))]>;
1000 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1001 "movss\t{$src, $dst|$dst, $src}",
1003 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
1005 // FIXME: may not be able to eliminate this movss with coalescing the src and
1006 // dest register classes are different. We really want to write this pattern
1008 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1009 // (f32 FR32:$src)>;
1010 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
1011 "movss\t{$src, $dst|$dst, $src}",
1012 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
1014 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
1015 "movss\t{$src, $dst|$dst, $src}",
1016 [(store (f32 (vector_extract (v4f32 VR128:$src),
1017 (iPTR 0))), addr:$dst)]>;
1020 // Move to lower bits of a VR128, leaving upper bits alone.
1021 // Three operand (but two address) aliases.
1022 let Constraints = "$src1 = $dst" in {
1023 let neverHasSideEffects = 1 in
1024 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
1025 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
1026 "movss\t{$src2, $dst|$dst, $src2}", []>;
1028 let AddedComplexity = 15 in
1029 def MOVLPSrr : SSI<0x10, MRMSrcReg,
1030 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1031 "movss\t{$src2, $dst|$dst, $src2}",
1033 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
1034 MOVL_shuffle_mask)))]>;
1037 // Move to lower bits of a VR128 and zeroing upper bits.
1038 // Loading from memory automatically zeroing upper bits.
1039 let AddedComplexity = 20 in
1040 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1041 "movss\t{$src, $dst|$dst, $src}",
1042 [(set VR128:$dst, (v4f32 (X86vzmovl (v4f32 (scalar_to_vector
1043 (loadf32 addr:$src))))))]>;
1045 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1046 (MOVZSS2PSrm addr:$src)>;
1048 //===----------------------------------------------------------------------===//
1049 // SSE2 Instructions
1050 //===----------------------------------------------------------------------===//
1052 // Move Instructions
1053 let neverHasSideEffects = 1 in
1054 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1055 "movsd\t{$src, $dst|$dst, $src}", []>;
1056 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1057 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1058 "movsd\t{$src, $dst|$dst, $src}",
1059 [(set FR64:$dst, (loadf64 addr:$src))]>;
1060 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1061 "movsd\t{$src, $dst|$dst, $src}",
1062 [(store FR64:$src, addr:$dst)]>;
1064 // Conversion instructions
1065 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1066 "cvttsd2si\t{$src, $dst|$dst, $src}",
1067 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1068 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1069 "cvttsd2si\t{$src, $dst|$dst, $src}",
1070 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1071 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1072 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1073 [(set FR32:$dst, (fround FR64:$src))]>;
1074 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1075 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1076 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1077 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1078 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1079 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1080 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1081 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1082 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1084 // SSE2 instructions with XS prefix
1085 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1086 "cvtss2sd\t{$src, $dst|$dst, $src}",
1087 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1088 Requires<[HasSSE2]>;
1089 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1090 "cvtss2sd\t{$src, $dst|$dst, $src}",
1091 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1092 Requires<[HasSSE2]>;
1094 // Match intrinsics which expect XMM operand(s).
1095 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1096 "cvtsd2si\t{$src, $dst|$dst, $src}",
1097 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1098 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1099 "cvtsd2si\t{$src, $dst|$dst, $src}",
1100 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1101 (load addr:$src)))]>;
1103 // Match intrinisics which expect MM and XMM operand(s).
1104 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1105 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1106 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1107 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1108 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1109 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1110 (memop addr:$src)))]>;
1111 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1112 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1113 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1114 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1115 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1116 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1117 (memop addr:$src)))]>;
1118 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1119 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1120 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1121 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1122 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1123 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1124 (load addr:$src)))]>;
1126 // Aliases for intrinsics
1127 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1128 "cvttsd2si\t{$src, $dst|$dst, $src}",
1130 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1131 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1132 "cvttsd2si\t{$src, $dst|$dst, $src}",
1133 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1134 (load addr:$src)))]>;
1136 // Comparison instructions
1137 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1138 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1139 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1140 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1142 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1143 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1144 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1147 let Defs = [EFLAGS] in {
1148 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1149 "ucomisd\t{$src2, $src1|$src1, $src2}",
1150 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1151 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1152 "ucomisd\t{$src2, $src1|$src1, $src2}",
1153 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1154 (implicit EFLAGS)]>;
1157 // Aliases to match intrinsics which expect XMM operand(s).
1158 let Constraints = "$src1 = $dst" in {
1159 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1160 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1161 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1162 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1163 VR128:$src, imm:$cc))]>;
1164 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1165 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1166 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1167 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1168 (load addr:$src), imm:$cc))]>;
1171 let Defs = [EFLAGS] in {
1172 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1173 "ucomisd\t{$src2, $src1|$src1, $src2}",
1174 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1175 (implicit EFLAGS)]>;
1176 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1177 "ucomisd\t{$src2, $src1|$src1, $src2}",
1178 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1179 (implicit EFLAGS)]>;
1181 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1182 "comisd\t{$src2, $src1|$src1, $src2}",
1183 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1184 (implicit EFLAGS)]>;
1185 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1186 "comisd\t{$src2, $src1|$src1, $src2}",
1187 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1188 (implicit EFLAGS)]>;
1191 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1194 // Alias instructions that map fld0 to pxor for sse.
1195 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
1196 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1197 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1198 Requires<[HasSSE2]>, TB, OpSize;
1200 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1202 let neverHasSideEffects = 1 in
1203 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1204 "movapd\t{$src, $dst|$dst, $src}", []>;
1206 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1208 let isSimpleLoad = 1 in
1209 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1210 "movapd\t{$src, $dst|$dst, $src}",
1211 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1213 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1214 let Constraints = "$src1 = $dst" in {
1215 let isCommutable = 1 in {
1216 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst),
1217 (ins FR64:$src1, FR64:$src2),
1218 "andpd\t{$src2, $dst|$dst, $src2}",
1219 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1220 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst),
1221 (ins FR64:$src1, FR64:$src2),
1222 "orpd\t{$src2, $dst|$dst, $src2}",
1223 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1224 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst),
1225 (ins FR64:$src1, FR64:$src2),
1226 "xorpd\t{$src2, $dst|$dst, $src2}",
1227 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1230 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst),
1231 (ins FR64:$src1, f128mem:$src2),
1232 "andpd\t{$src2, $dst|$dst, $src2}",
1233 [(set FR64:$dst, (X86fand FR64:$src1,
1234 (memopfsf64 addr:$src2)))]>;
1235 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst),
1236 (ins FR64:$src1, f128mem:$src2),
1237 "orpd\t{$src2, $dst|$dst, $src2}",
1238 [(set FR64:$dst, (X86for FR64:$src1,
1239 (memopfsf64 addr:$src2)))]>;
1240 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst),
1241 (ins FR64:$src1, f128mem:$src2),
1242 "xorpd\t{$src2, $dst|$dst, $src2}",
1243 [(set FR64:$dst, (X86fxor FR64:$src1,
1244 (memopfsf64 addr:$src2)))]>;
1246 let neverHasSideEffects = 1 in {
1247 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1248 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1249 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1251 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1252 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1253 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1257 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1259 /// In addition, we also have a special variant of the scalar form here to
1260 /// represent the associated intrinsic operation. This form is unlike the
1261 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1262 /// and leaves the top elements undefined.
1264 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1265 /// six "instructions".
1267 let Constraints = "$src1 = $dst" in {
1268 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1269 SDNode OpNode, Intrinsic F64Int,
1270 bit Commutable = 0> {
1271 // Scalar operation, reg+reg.
1272 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1273 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1274 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1275 let isCommutable = Commutable;
1278 // Scalar operation, reg+mem.
1279 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1280 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1281 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1283 // Vector operation, reg+reg.
1284 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1285 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1286 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1287 let isCommutable = Commutable;
1290 // Vector operation, reg+mem.
1291 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1292 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1293 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1295 // Intrinsic operation, reg+reg.
1296 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1297 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1298 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1299 let isCommutable = Commutable;
1302 // Intrinsic operation, reg+mem.
1303 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1304 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1305 [(set VR128:$dst, (F64Int VR128:$src1,
1306 sse_load_f64:$src2))]>;
1310 // Arithmetic instructions
1311 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1312 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1313 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1314 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1316 /// sse2_fp_binop_rm - Other SSE2 binops
1318 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1319 /// instructions for a full-vector intrinsic form. Operations that map
1320 /// onto C operators don't use this form since they just use the plain
1321 /// vector form instead of having a separate vector intrinsic form.
1323 /// This provides a total of eight "instructions".
1325 let Constraints = "$src1 = $dst" in {
1326 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1330 bit Commutable = 0> {
1332 // Scalar operation, reg+reg.
1333 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1334 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1335 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1336 let isCommutable = Commutable;
1339 // Scalar operation, reg+mem.
1340 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
1341 (ins FR64:$src1, f64mem:$src2),
1342 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1343 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1345 // Vector operation, reg+reg.
1346 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1347 (ins VR128:$src1, VR128:$src2),
1348 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1349 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1350 let isCommutable = Commutable;
1353 // Vector operation, reg+mem.
1354 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1355 (ins VR128:$src1, f128mem:$src2),
1356 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1357 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1359 // Intrinsic operation, reg+reg.
1360 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
1361 (ins VR128:$src1, VR128:$src2),
1362 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1363 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1364 let isCommutable = Commutable;
1367 // Intrinsic operation, reg+mem.
1368 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
1369 (ins VR128:$src1, sdmem:$src2),
1370 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1371 [(set VR128:$dst, (F64Int VR128:$src1,
1372 sse_load_f64:$src2))]>;
1374 // Vector intrinsic operation, reg+reg.
1375 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1376 (ins VR128:$src1, VR128:$src2),
1377 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1378 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1379 let isCommutable = Commutable;
1382 // Vector intrinsic operation, reg+mem.
1383 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1384 (ins VR128:$src1, f128mem:$src2),
1385 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1386 [(set VR128:$dst, (V2F64Int VR128:$src1,
1387 (memopv2f64 addr:$src2)))]>;
1391 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1392 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1393 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1394 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1396 //===----------------------------------------------------------------------===//
1397 // SSE packed FP Instructions
1399 // Move Instructions
1400 let neverHasSideEffects = 1 in
1401 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1402 "movapd\t{$src, $dst|$dst, $src}", []>;
1403 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1404 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1405 "movapd\t{$src, $dst|$dst, $src}",
1406 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1408 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1409 "movapd\t{$src, $dst|$dst, $src}",
1410 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1412 let neverHasSideEffects = 1 in
1413 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1414 "movupd\t{$src, $dst|$dst, $src}", []>;
1415 let isSimpleLoad = 1 in
1416 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1417 "movupd\t{$src, $dst|$dst, $src}",
1418 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1419 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1420 "movupd\t{$src, $dst|$dst, $src}",
1421 [(store (v2f64 VR128:$src), addr:$dst)]>;
1423 // Intrinsic forms of MOVUPD load and store
1424 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1425 "movupd\t{$src, $dst|$dst, $src}",
1426 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1427 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1428 "movupd\t{$src, $dst|$dst, $src}",
1429 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1431 let Constraints = "$src1 = $dst" in {
1432 let AddedComplexity = 20 in {
1433 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1434 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1435 "movlpd\t{$src2, $dst|$dst, $src2}",
1437 (v2f64 (vector_shuffle VR128:$src1,
1438 (scalar_to_vector (loadf64 addr:$src2)),
1439 MOVLP_shuffle_mask)))]>;
1440 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1441 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1442 "movhpd\t{$src2, $dst|$dst, $src2}",
1444 (v2f64 (vector_shuffle VR128:$src1,
1445 (scalar_to_vector (loadf64 addr:$src2)),
1446 MOVHP_shuffle_mask)))]>;
1447 } // AddedComplexity
1448 } // Constraints = "$src1 = $dst"
1450 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1451 "movlpd\t{$src, $dst|$dst, $src}",
1452 [(store (f64 (vector_extract (v2f64 VR128:$src),
1453 (iPTR 0))), addr:$dst)]>;
1455 // v2f64 extract element 1 is always custom lowered to unpack high to low
1456 // and extract element 0 so the non-store version isn't too horrible.
1457 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1458 "movhpd\t{$src, $dst|$dst, $src}",
1459 [(store (f64 (vector_extract
1460 (v2f64 (vector_shuffle VR128:$src, (undef),
1461 UNPCKH_shuffle_mask)), (iPTR 0))),
1464 // SSE2 instructions without OpSize prefix
1465 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1466 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1467 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1468 TB, Requires<[HasSSE2]>;
1469 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1470 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1471 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1472 (bitconvert (memopv2i64 addr:$src))))]>,
1473 TB, Requires<[HasSSE2]>;
1475 // SSE2 instructions with XS prefix
1476 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1477 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1478 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1479 XS, Requires<[HasSSE2]>;
1480 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1481 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1482 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1483 (bitconvert (memopv2i64 addr:$src))))]>,
1484 XS, Requires<[HasSSE2]>;
1486 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1487 "cvtps2dq\t{$src, $dst|$dst, $src}",
1488 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1489 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1490 "cvtps2dq\t{$src, $dst|$dst, $src}",
1491 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1492 (memop addr:$src)))]>;
1493 // SSE2 packed instructions with XS prefix
1494 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1495 "cvttps2dq\t{$src, $dst|$dst, $src}",
1496 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1497 XS, Requires<[HasSSE2]>;
1498 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1499 "cvttps2dq\t{$src, $dst|$dst, $src}",
1500 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1501 (memop addr:$src)))]>,
1502 XS, Requires<[HasSSE2]>;
1504 // SSE2 packed instructions with XD prefix
1505 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1506 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1507 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1508 XD, Requires<[HasSSE2]>;
1509 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1510 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1511 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1512 (memop addr:$src)))]>,
1513 XD, Requires<[HasSSE2]>;
1515 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1516 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1517 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1518 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1519 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1520 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1521 (memop addr:$src)))]>;
1523 // SSE2 instructions without OpSize prefix
1524 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1525 "cvtps2pd\t{$src, $dst|$dst, $src}",
1526 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1527 TB, Requires<[HasSSE2]>;
1528 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1529 "cvtps2pd\t{$src, $dst|$dst, $src}",
1530 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1531 (load addr:$src)))]>,
1532 TB, Requires<[HasSSE2]>;
1534 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1535 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1536 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1537 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1538 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1539 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1540 (memop addr:$src)))]>;
1542 // Match intrinsics which expect XMM operand(s).
1543 // Aliases for intrinsics
1544 let Constraints = "$src1 = $dst" in {
1545 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1546 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1547 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1548 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1550 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1551 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1552 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1553 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1554 (loadi32 addr:$src2)))]>;
1555 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1556 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1557 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1558 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1560 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1561 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1562 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1563 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1564 (load addr:$src2)))]>;
1565 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1566 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1567 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1568 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1569 VR128:$src2))]>, XS,
1570 Requires<[HasSSE2]>;
1571 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1572 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1573 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1574 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1575 (load addr:$src2)))]>, XS,
1576 Requires<[HasSSE2]>;
1581 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1583 /// In addition, we also have a special variant of the scalar form here to
1584 /// represent the associated intrinsic operation. This form is unlike the
1585 /// plain scalar form, in that it takes an entire vector (instead of a
1586 /// scalar) and leaves the top elements undefined.
1588 /// And, we have a special variant form for a full-vector intrinsic form.
1590 /// These four forms can each have a reg or a mem operand, so there are a
1591 /// total of eight "instructions".
1593 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1597 bit Commutable = 0> {
1598 // Scalar operation, reg.
1599 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1600 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1601 [(set FR64:$dst, (OpNode FR64:$src))]> {
1602 let isCommutable = Commutable;
1605 // Scalar operation, mem.
1606 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1607 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1608 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1610 // Vector operation, reg.
1611 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1612 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1613 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1614 let isCommutable = Commutable;
1617 // Vector operation, mem.
1618 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1619 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1620 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1622 // Intrinsic operation, reg.
1623 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1624 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1625 [(set VR128:$dst, (F64Int VR128:$src))]> {
1626 let isCommutable = Commutable;
1629 // Intrinsic operation, mem.
1630 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1631 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1632 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1634 // Vector intrinsic operation, reg
1635 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1636 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1637 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1638 let isCommutable = Commutable;
1641 // Vector intrinsic operation, mem
1642 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1643 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1644 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1648 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1649 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1651 // There is no f64 version of the reciprocal approximation instructions.
1654 let Constraints = "$src1 = $dst" in {
1655 let isCommutable = 1 in {
1656 def ANDPDrr : PDI<0x54, MRMSrcReg,
1657 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1658 "andpd\t{$src2, $dst|$dst, $src2}",
1660 (and (bc_v2i64 (v2f64 VR128:$src1)),
1661 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1662 def ORPDrr : PDI<0x56, MRMSrcReg,
1663 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1664 "orpd\t{$src2, $dst|$dst, $src2}",
1666 (or (bc_v2i64 (v2f64 VR128:$src1)),
1667 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1668 def XORPDrr : PDI<0x57, MRMSrcReg,
1669 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1670 "xorpd\t{$src2, $dst|$dst, $src2}",
1672 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1673 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1676 def ANDPDrm : PDI<0x54, MRMSrcMem,
1677 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1678 "andpd\t{$src2, $dst|$dst, $src2}",
1680 (and (bc_v2i64 (v2f64 VR128:$src1)),
1681 (memopv2i64 addr:$src2)))]>;
1682 def ORPDrm : PDI<0x56, MRMSrcMem,
1683 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1684 "orpd\t{$src2, $dst|$dst, $src2}",
1686 (or (bc_v2i64 (v2f64 VR128:$src1)),
1687 (memopv2i64 addr:$src2)))]>;
1688 def XORPDrm : PDI<0x57, MRMSrcMem,
1689 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1690 "xorpd\t{$src2, $dst|$dst, $src2}",
1692 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1693 (memopv2i64 addr:$src2)))]>;
1694 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1695 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1696 "andnpd\t{$src2, $dst|$dst, $src2}",
1698 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1699 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1700 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1701 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1702 "andnpd\t{$src2, $dst|$dst, $src2}",
1704 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1705 (memopv2i64 addr:$src2)))]>;
1708 let Constraints = "$src1 = $dst" in {
1709 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1710 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1711 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1712 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1713 VR128:$src, imm:$cc))]>;
1714 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1715 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1716 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1717 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1718 (memop addr:$src), imm:$cc))]>;
1720 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1721 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1722 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1723 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1725 // Shuffle and unpack instructions
1726 let Constraints = "$src1 = $dst" in {
1727 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1728 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1729 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1730 [(set VR128:$dst, (v2f64 (vector_shuffle
1731 VR128:$src1, VR128:$src2,
1732 SHUFP_shuffle_mask:$src3)))]>;
1733 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1734 (outs VR128:$dst), (ins VR128:$src1,
1735 f128mem:$src2, i8imm:$src3),
1736 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1738 (v2f64 (vector_shuffle
1739 VR128:$src1, (memopv2f64 addr:$src2),
1740 SHUFP_shuffle_mask:$src3)))]>;
1742 let AddedComplexity = 10 in {
1743 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1744 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1745 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1747 (v2f64 (vector_shuffle
1748 VR128:$src1, VR128:$src2,
1749 UNPCKH_shuffle_mask)))]>;
1750 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1751 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1752 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1754 (v2f64 (vector_shuffle
1755 VR128:$src1, (memopv2f64 addr:$src2),
1756 UNPCKH_shuffle_mask)))]>;
1758 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1759 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1760 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1762 (v2f64 (vector_shuffle
1763 VR128:$src1, VR128:$src2,
1764 UNPCKL_shuffle_mask)))]>;
1765 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1766 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1767 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1769 (v2f64 (vector_shuffle
1770 VR128:$src1, (memopv2f64 addr:$src2),
1771 UNPCKL_shuffle_mask)))]>;
1772 } // AddedComplexity
1773 } // Constraints = "$src1 = $dst"
1776 //===----------------------------------------------------------------------===//
1777 // SSE integer instructions
1779 // Move Instructions
1780 let neverHasSideEffects = 1 in
1781 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1782 "movdqa\t{$src, $dst|$dst, $src}", []>;
1783 let isSimpleLoad = 1, mayLoad = 1 in
1784 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1785 "movdqa\t{$src, $dst|$dst, $src}",
1786 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1788 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1789 "movdqa\t{$src, $dst|$dst, $src}",
1790 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1791 let isSimpleLoad = 1, mayLoad = 1 in
1792 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1793 "movdqu\t{$src, $dst|$dst, $src}",
1794 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1795 XS, Requires<[HasSSE2]>;
1797 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1798 "movdqu\t{$src, $dst|$dst, $src}",
1799 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1800 XS, Requires<[HasSSE2]>;
1802 // Intrinsic forms of MOVDQU load and store
1803 let isSimpleLoad = 1 in
1804 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1805 "movdqu\t{$src, $dst|$dst, $src}",
1806 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1807 XS, Requires<[HasSSE2]>;
1808 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1809 "movdqu\t{$src, $dst|$dst, $src}",
1810 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1811 XS, Requires<[HasSSE2]>;
1813 let Constraints = "$src1 = $dst" in {
1815 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1816 bit Commutable = 0> {
1817 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1818 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1819 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1820 let isCommutable = Commutable;
1822 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1823 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1824 [(set VR128:$dst, (IntId VR128:$src1,
1825 (bitconvert (memopv2i64 addr:$src2))))]>;
1828 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1830 Intrinsic IntId, Intrinsic IntId2> {
1831 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1832 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1833 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1834 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1835 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1836 [(set VR128:$dst, (IntId VR128:$src1,
1837 (bitconvert (memopv2i64 addr:$src2))))]>;
1838 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1839 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1840 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1843 /// PDI_binop_rm - Simple SSE2 binary operator.
1844 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1845 ValueType OpVT, bit Commutable = 0> {
1846 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1847 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1848 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1849 let isCommutable = Commutable;
1851 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1852 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1853 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1854 (bitconvert (memopv2i64 addr:$src2)))))]>;
1857 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1859 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1860 /// to collapse (bitconvert VT to VT) into its operand.
1862 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1863 bit Commutable = 0> {
1864 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1865 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1866 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1867 let isCommutable = Commutable;
1869 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1870 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1871 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1874 } // Constraints = "$src1 = $dst"
1876 // 128-bit Integer Arithmetic
1878 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1879 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1880 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1881 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1883 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1884 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1885 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1886 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1888 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1889 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1890 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1891 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1893 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1894 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1895 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1896 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1898 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1900 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1901 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1902 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1904 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1906 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1907 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1910 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1911 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1912 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1913 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1914 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1917 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
1918 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
1919 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
1920 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
1921 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
1922 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
1924 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
1925 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
1926 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
1927 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
1928 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
1929 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
1931 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
1932 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
1933 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
1934 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
1936 // 128-bit logical shifts.
1937 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1938 def PSLLDQri : PDIi8<0x73, MRM7r,
1939 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1940 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1941 def PSRLDQri : PDIi8<0x73, MRM3r,
1942 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1943 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1944 // PSRADQri doesn't exist in SSE[1-3].
1947 let Predicates = [HasSSE2] in {
1948 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1949 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1950 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1951 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1952 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1953 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1955 // Shift up / down and insert zero's.
1956 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
1957 (v2i64 (PSLLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1958 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
1959 (v2i64 (PSRLDQri VR128:$src, (PSxLDQ_imm imm:$amt)))>;
1963 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1964 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1965 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1967 let Constraints = "$src1 = $dst" in {
1968 def PANDNrr : PDI<0xDF, MRMSrcReg,
1969 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1970 "pandn\t{$src2, $dst|$dst, $src2}",
1971 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1974 def PANDNrm : PDI<0xDF, MRMSrcMem,
1975 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1976 "pandn\t{$src2, $dst|$dst, $src2}",
1977 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1978 (memopv2i64 addr:$src2))))]>;
1981 // SSE2 Integer comparison
1982 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1983 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1984 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1985 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1986 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1987 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1989 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
1990 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
1991 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
1992 (PCMPEQBrm VR128:$src1, addr:$src2)>;
1993 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
1994 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
1995 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
1996 (PCMPEQWrm VR128:$src1, addr:$src2)>;
1997 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
1998 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
1999 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2000 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2002 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2003 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2004 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2005 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2006 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2007 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2008 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2009 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2010 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2011 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2012 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2013 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2016 // Pack instructions
2017 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2018 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2019 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2021 // Shuffle and unpack instructions
2022 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2023 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2024 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2025 [(set VR128:$dst, (v4i32 (vector_shuffle
2026 VR128:$src1, (undef),
2027 PSHUFD_shuffle_mask:$src2)))]>;
2028 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2029 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2030 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2031 [(set VR128:$dst, (v4i32 (vector_shuffle
2032 (bc_v4i32(memopv2i64 addr:$src1)),
2034 PSHUFD_shuffle_mask:$src2)))]>;
2036 // SSE2 with ImmT == Imm8 and XS prefix.
2037 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2038 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2039 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2040 [(set VR128:$dst, (v8i16 (vector_shuffle
2041 VR128:$src1, (undef),
2042 PSHUFHW_shuffle_mask:$src2)))]>,
2043 XS, Requires<[HasSSE2]>;
2044 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2045 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2046 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2047 [(set VR128:$dst, (v8i16 (vector_shuffle
2048 (bc_v8i16 (memopv2i64 addr:$src1)),
2050 PSHUFHW_shuffle_mask:$src2)))]>,
2051 XS, Requires<[HasSSE2]>;
2053 // SSE2 with ImmT == Imm8 and XD prefix.
2054 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2055 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2056 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2057 [(set VR128:$dst, (v8i16 (vector_shuffle
2058 VR128:$src1, (undef),
2059 PSHUFLW_shuffle_mask:$src2)))]>,
2060 XD, Requires<[HasSSE2]>;
2061 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2062 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
2063 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2064 [(set VR128:$dst, (v8i16 (vector_shuffle
2065 (bc_v8i16 (memopv2i64 addr:$src1)),
2067 PSHUFLW_shuffle_mask:$src2)))]>,
2068 XD, Requires<[HasSSE2]>;
2071 let Constraints = "$src1 = $dst" in {
2072 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
2073 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2074 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2076 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2077 UNPCKL_shuffle_mask)))]>;
2078 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
2079 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2080 "punpcklbw\t{$src2, $dst|$dst, $src2}",
2082 (v16i8 (vector_shuffle VR128:$src1,
2083 (bc_v16i8 (memopv2i64 addr:$src2)),
2084 UNPCKL_shuffle_mask)))]>;
2085 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
2086 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2087 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2089 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2090 UNPCKL_shuffle_mask)))]>;
2091 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
2092 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2093 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2095 (v8i16 (vector_shuffle VR128:$src1,
2096 (bc_v8i16 (memopv2i64 addr:$src2)),
2097 UNPCKL_shuffle_mask)))]>;
2098 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2099 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2100 "punpckldq\t{$src2, $dst|$dst, $src2}",
2102 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2103 UNPCKL_shuffle_mask)))]>;
2104 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2105 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2106 "punpckldq\t{$src2, $dst|$dst, $src2}",
2108 (v4i32 (vector_shuffle VR128:$src1,
2109 (bc_v4i32 (memopv2i64 addr:$src2)),
2110 UNPCKL_shuffle_mask)))]>;
2111 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2112 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2113 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2115 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2116 UNPCKL_shuffle_mask)))]>;
2117 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2118 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2119 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2121 (v2i64 (vector_shuffle VR128:$src1,
2122 (memopv2i64 addr:$src2),
2123 UNPCKL_shuffle_mask)))]>;
2125 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2126 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2127 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2129 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2130 UNPCKH_shuffle_mask)))]>;
2131 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2132 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2133 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2135 (v16i8 (vector_shuffle VR128:$src1,
2136 (bc_v16i8 (memopv2i64 addr:$src2)),
2137 UNPCKH_shuffle_mask)))]>;
2138 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2139 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2140 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2142 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2143 UNPCKH_shuffle_mask)))]>;
2144 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2145 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2146 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2148 (v8i16 (vector_shuffle VR128:$src1,
2149 (bc_v8i16 (memopv2i64 addr:$src2)),
2150 UNPCKH_shuffle_mask)))]>;
2151 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2152 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2153 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2155 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2156 UNPCKH_shuffle_mask)))]>;
2157 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2158 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2159 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2161 (v4i32 (vector_shuffle VR128:$src1,
2162 (bc_v4i32 (memopv2i64 addr:$src2)),
2163 UNPCKH_shuffle_mask)))]>;
2164 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2165 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2166 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2168 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2169 UNPCKH_shuffle_mask)))]>;
2170 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2171 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2172 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2174 (v2i64 (vector_shuffle VR128:$src1,
2175 (memopv2i64 addr:$src2),
2176 UNPCKH_shuffle_mask)))]>;
2180 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2181 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2182 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2183 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2185 let Constraints = "$src1 = $dst" in {
2186 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2187 (outs VR128:$dst), (ins VR128:$src1,
2188 GR32:$src2, i32i8imm:$src3),
2189 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2191 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2192 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2193 (outs VR128:$dst), (ins VR128:$src1,
2194 i16mem:$src2, i32i8imm:$src3),
2195 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2197 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2202 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2203 "pmovmskb\t{$src, $dst|$dst, $src}",
2204 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2206 // Conditional store
2208 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2209 "maskmovdqu\t{$mask, $src|$src, $mask}",
2210 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2212 // Non-temporal stores
2213 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2214 "movntpd\t{$src, $dst|$dst, $src}",
2215 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2216 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2217 "movntdq\t{$src, $dst|$dst, $src}",
2218 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2219 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2220 "movnti\t{$src, $dst|$dst, $src}",
2221 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2222 TB, Requires<[HasSSE2]>;
2225 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2226 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2227 TB, Requires<[HasSSE2]>;
2229 // Load, store, and memory fence
2230 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2231 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2232 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2233 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2235 //TODO: custom lower this so as to never even generate the noop
2236 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2238 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2239 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2240 def : Pat<(membarrier (i8 imm:$ll), (i8 imm:$ls), (i8 imm:$sl), (i8 imm:$ss),
2243 // Alias instructions that map zero vector to pxor / xorp* for sse.
2244 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
2245 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2246 "pcmpeqd\t$dst, $dst",
2247 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2249 // FR64 to 128-bit vector conversion.
2250 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2251 "movsd\t{$src, $dst|$dst, $src}",
2253 (v2f64 (scalar_to_vector FR64:$src)))]>;
2254 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2255 "movsd\t{$src, $dst|$dst, $src}",
2257 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2259 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2260 "movd\t{$src, $dst|$dst, $src}",
2262 (v4i32 (scalar_to_vector GR32:$src)))]>;
2263 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2264 "movd\t{$src, $dst|$dst, $src}",
2266 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2268 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2269 "movd\t{$src, $dst|$dst, $src}",
2270 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2272 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2273 "movd\t{$src, $dst|$dst, $src}",
2274 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2276 // SSE2 instructions with XS prefix
2277 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2278 "movq\t{$src, $dst|$dst, $src}",
2280 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2281 Requires<[HasSSE2]>;
2282 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2283 "movq\t{$src, $dst|$dst, $src}",
2284 [(store (i64 (vector_extract (v2i64 VR128:$src),
2285 (iPTR 0))), addr:$dst)]>;
2287 // FIXME: may not be able to eliminate this movss with coalescing the src and
2288 // dest register classes are different. We really want to write this pattern
2290 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2291 // (f32 FR32:$src)>;
2292 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2293 "movsd\t{$src, $dst|$dst, $src}",
2294 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2296 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2297 "movsd\t{$src, $dst|$dst, $src}",
2298 [(store (f64 (vector_extract (v2f64 VR128:$src),
2299 (iPTR 0))), addr:$dst)]>;
2300 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2301 "movd\t{$src, $dst|$dst, $src}",
2302 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2304 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2305 "movd\t{$src, $dst|$dst, $src}",
2306 [(store (i32 (vector_extract (v4i32 VR128:$src),
2307 (iPTR 0))), addr:$dst)]>;
2309 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2310 "movd\t{$src, $dst|$dst, $src}",
2311 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2312 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2313 "movd\t{$src, $dst|$dst, $src}",
2314 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2317 // Move to lower bits of a VR128, leaving upper bits alone.
2318 // Three operand (but two address) aliases.
2319 let Constraints = "$src1 = $dst" in {
2320 let neverHasSideEffects = 1 in
2321 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2322 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2323 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2325 let AddedComplexity = 15 in
2326 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2327 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2328 "movsd\t{$src2, $dst|$dst, $src2}",
2330 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2331 MOVL_shuffle_mask)))]>;
2334 // Store / copy lower 64-bits of a XMM register.
2335 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2336 "movq\t{$src, $dst|$dst, $src}",
2337 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2339 // Move to lower bits of a VR128 and zeroing upper bits.
2340 // Loading from memory automatically zeroing upper bits.
2341 let AddedComplexity = 20 in {
2342 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2343 "movsd\t{$src, $dst|$dst, $src}",
2345 (v2f64 (X86vzmovl (v2f64 (scalar_to_vector
2346 (loadf64 addr:$src))))))]>;
2348 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2349 (MOVZSD2PDrm addr:$src)>;
2350 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2351 (MOVZSD2PDrm addr:$src)>;
2352 def : Pat<(v2f64 (X86vzload addr:$src)), (MOVZSD2PDrm addr:$src)>;
2355 // movd / movq to XMM register zero-extends
2356 let AddedComplexity = 15 in {
2357 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2358 "movd\t{$src, $dst|$dst, $src}",
2359 [(set VR128:$dst, (v4i32 (X86vzmovl
2360 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2361 // This is X86-64 only.
2362 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2363 "mov{d|q}\t{$src, $dst|$dst, $src}",
2364 [(set VR128:$dst, (v2i64 (X86vzmovl
2365 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2368 let AddedComplexity = 20 in {
2369 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2370 "movd\t{$src, $dst|$dst, $src}",
2372 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2373 (loadi32 addr:$src))))))]>;
2375 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2376 (MOVZDI2PDIrm addr:$src)>;
2377 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2378 (MOVZDI2PDIrm addr:$src)>;
2379 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2380 (MOVZDI2PDIrm addr:$src)>;
2382 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2383 "movq\t{$src, $dst|$dst, $src}",
2385 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2386 (loadi64 addr:$src))))))]>, XS,
2387 Requires<[HasSSE2]>;
2389 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2390 (MOVZQI2PQIrm addr:$src)>;
2391 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2392 (MOVZQI2PQIrm addr:$src)>;
2393 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2396 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2397 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2398 let AddedComplexity = 15 in
2399 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2400 "movq\t{$src, $dst|$dst, $src}",
2401 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2402 XS, Requires<[HasSSE2]>;
2404 let AddedComplexity = 20 in {
2405 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2406 "movq\t{$src, $dst|$dst, $src}",
2407 [(set VR128:$dst, (v2i64 (X86vzmovl
2408 (loadv2i64 addr:$src))))]>,
2409 XS, Requires<[HasSSE2]>;
2411 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2412 (MOVZPQILo2PQIrm addr:$src)>;
2415 //===----------------------------------------------------------------------===//
2416 // SSE3 Instructions
2417 //===----------------------------------------------------------------------===//
2419 // Move Instructions
2420 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2421 "movshdup\t{$src, $dst|$dst, $src}",
2422 [(set VR128:$dst, (v4f32 (vector_shuffle
2423 VR128:$src, (undef),
2424 MOVSHDUP_shuffle_mask)))]>;
2425 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2426 "movshdup\t{$src, $dst|$dst, $src}",
2427 [(set VR128:$dst, (v4f32 (vector_shuffle
2428 (memopv4f32 addr:$src), (undef),
2429 MOVSHDUP_shuffle_mask)))]>;
2431 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2432 "movsldup\t{$src, $dst|$dst, $src}",
2433 [(set VR128:$dst, (v4f32 (vector_shuffle
2434 VR128:$src, (undef),
2435 MOVSLDUP_shuffle_mask)))]>;
2436 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2437 "movsldup\t{$src, $dst|$dst, $src}",
2438 [(set VR128:$dst, (v4f32 (vector_shuffle
2439 (memopv4f32 addr:$src), (undef),
2440 MOVSLDUP_shuffle_mask)))]>;
2442 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2443 "movddup\t{$src, $dst|$dst, $src}",
2444 [(set VR128:$dst, (v2f64 (vector_shuffle
2445 VR128:$src, (undef),
2446 SSE_splat_lo_mask)))]>;
2447 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2448 "movddup\t{$src, $dst|$dst, $src}",
2450 (v2f64 (vector_shuffle
2451 (scalar_to_vector (loadf64 addr:$src)),
2453 SSE_splat_lo_mask)))]>;
2456 let Constraints = "$src1 = $dst" in {
2457 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2458 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2459 "addsubps\t{$src2, $dst|$dst, $src2}",
2460 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2462 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2463 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2464 "addsubps\t{$src2, $dst|$dst, $src2}",
2465 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2466 (memop addr:$src2)))]>;
2467 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2468 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2469 "addsubpd\t{$src2, $dst|$dst, $src2}",
2470 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2472 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2473 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2474 "addsubpd\t{$src2, $dst|$dst, $src2}",
2475 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2476 (memop addr:$src2)))]>;
2479 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2480 "lddqu\t{$src, $dst|$dst, $src}",
2481 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2484 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2485 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2486 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2487 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2488 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2489 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2490 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2491 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2492 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2493 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2494 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2495 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2496 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2497 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2498 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2499 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2501 let Constraints = "$src1 = $dst" in {
2502 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2503 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2504 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2505 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2506 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2507 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2508 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2509 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2512 // Thread synchronization
2513 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2514 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2515 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2516 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2518 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2519 let AddedComplexity = 15 in
2520 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2521 MOVSHDUP_shuffle_mask)),
2522 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2523 let AddedComplexity = 20 in
2524 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2525 MOVSHDUP_shuffle_mask)),
2526 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2528 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2529 let AddedComplexity = 15 in
2530 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2531 MOVSLDUP_shuffle_mask)),
2532 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2533 let AddedComplexity = 20 in
2534 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2535 MOVSLDUP_shuffle_mask)),
2536 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2538 //===----------------------------------------------------------------------===//
2539 // SSSE3 Instructions
2540 //===----------------------------------------------------------------------===//
2542 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2543 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2544 Intrinsic IntId64, Intrinsic IntId128> {
2545 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2546 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2547 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2549 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2550 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2552 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2554 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2556 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2557 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2560 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2562 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2565 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2568 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2569 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2570 Intrinsic IntId64, Intrinsic IntId128> {
2571 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2573 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2574 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2576 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2578 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2581 (bitconvert (memopv4i16 addr:$src))))]>;
2583 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2585 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2586 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2589 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2591 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2594 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2597 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2598 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2599 Intrinsic IntId64, Intrinsic IntId128> {
2600 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2602 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2603 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2605 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2607 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2610 (bitconvert (memopv2i32 addr:$src))))]>;
2612 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2614 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2615 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2618 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2620 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2623 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2626 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2627 int_x86_ssse3_pabs_b,
2628 int_x86_ssse3_pabs_b_128>;
2629 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2630 int_x86_ssse3_pabs_w,
2631 int_x86_ssse3_pabs_w_128>;
2632 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2633 int_x86_ssse3_pabs_d,
2634 int_x86_ssse3_pabs_d_128>;
2636 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2637 let Constraints = "$src1 = $dst" in {
2638 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2639 Intrinsic IntId64, Intrinsic IntId128,
2640 bit Commutable = 0> {
2641 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2642 (ins VR64:$src1, VR64:$src2),
2643 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2644 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2645 let isCommutable = Commutable;
2647 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2648 (ins VR64:$src1, i64mem:$src2),
2649 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2651 (IntId64 VR64:$src1,
2652 (bitconvert (memopv8i8 addr:$src2))))]>;
2654 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2655 (ins VR128:$src1, VR128:$src2),
2656 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2657 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2659 let isCommutable = Commutable;
2661 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2662 (ins VR128:$src1, i128mem:$src2),
2663 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2665 (IntId128 VR128:$src1,
2666 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2670 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2671 let Constraints = "$src1 = $dst" in {
2672 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2673 Intrinsic IntId64, Intrinsic IntId128,
2674 bit Commutable = 0> {
2675 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2676 (ins VR64:$src1, VR64:$src2),
2677 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2678 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2679 let isCommutable = Commutable;
2681 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2682 (ins VR64:$src1, i64mem:$src2),
2683 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2685 (IntId64 VR64:$src1,
2686 (bitconvert (memopv4i16 addr:$src2))))]>;
2688 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2689 (ins VR128:$src1, VR128:$src2),
2690 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2691 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2693 let isCommutable = Commutable;
2695 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2696 (ins VR128:$src1, i128mem:$src2),
2697 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2699 (IntId128 VR128:$src1,
2700 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2704 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2705 let Constraints = "$src1 = $dst" in {
2706 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2707 Intrinsic IntId64, Intrinsic IntId128,
2708 bit Commutable = 0> {
2709 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2710 (ins VR64:$src1, VR64:$src2),
2711 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2712 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2713 let isCommutable = Commutable;
2715 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2716 (ins VR64:$src1, i64mem:$src2),
2717 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2719 (IntId64 VR64:$src1,
2720 (bitconvert (memopv2i32 addr:$src2))))]>;
2722 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2723 (ins VR128:$src1, VR128:$src2),
2724 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2725 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2727 let isCommutable = Commutable;
2729 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2730 (ins VR128:$src1, i128mem:$src2),
2731 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2733 (IntId128 VR128:$src1,
2734 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2738 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2739 int_x86_ssse3_phadd_w,
2740 int_x86_ssse3_phadd_w_128>;
2741 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2742 int_x86_ssse3_phadd_d,
2743 int_x86_ssse3_phadd_d_128>;
2744 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2745 int_x86_ssse3_phadd_sw,
2746 int_x86_ssse3_phadd_sw_128>;
2747 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2748 int_x86_ssse3_phsub_w,
2749 int_x86_ssse3_phsub_w_128>;
2750 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2751 int_x86_ssse3_phsub_d,
2752 int_x86_ssse3_phsub_d_128>;
2753 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2754 int_x86_ssse3_phsub_sw,
2755 int_x86_ssse3_phsub_sw_128>;
2756 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2757 int_x86_ssse3_pmadd_ub_sw,
2758 int_x86_ssse3_pmadd_ub_sw_128>;
2759 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2760 int_x86_ssse3_pmul_hr_sw,
2761 int_x86_ssse3_pmul_hr_sw_128, 1>;
2762 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2763 int_x86_ssse3_pshuf_b,
2764 int_x86_ssse3_pshuf_b_128>;
2765 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2766 int_x86_ssse3_psign_b,
2767 int_x86_ssse3_psign_b_128>;
2768 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2769 int_x86_ssse3_psign_w,
2770 int_x86_ssse3_psign_w_128>;
2771 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2772 int_x86_ssse3_psign_d,
2773 int_x86_ssse3_psign_d_128>;
2775 let Constraints = "$src1 = $dst" in {
2776 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2777 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2778 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2780 (int_x86_ssse3_palign_r
2781 VR64:$src1, VR64:$src2,
2783 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2784 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2785 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2787 (int_x86_ssse3_palign_r
2789 (bitconvert (memopv2i32 addr:$src2)),
2792 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2793 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2794 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2796 (int_x86_ssse3_palign_r_128
2797 VR128:$src1, VR128:$src2,
2798 imm:$src3))]>, OpSize;
2799 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2800 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2801 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2803 (int_x86_ssse3_palign_r_128
2805 (bitconvert (memopv4i32 addr:$src2)),
2806 imm:$src3))]>, OpSize;
2809 //===----------------------------------------------------------------------===//
2810 // Non-Instruction Patterns
2811 //===----------------------------------------------------------------------===//
2813 // extload f32 -> f64. This matches load+fextend because we have a hack in
2814 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2815 // Since these loads aren't folded into the fextend, we have to match it
2817 let Predicates = [HasSSE2] in
2818 def : Pat<(fextend (loadf32 addr:$src)),
2819 (CVTSS2SDrm addr:$src)>;
2822 let Predicates = [HasSSE2] in {
2823 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2824 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2825 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2826 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2827 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2828 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2829 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2830 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2831 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2832 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2833 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2834 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2835 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2836 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2837 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2838 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2839 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2840 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2841 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2842 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2843 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2844 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2845 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2846 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2847 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2848 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2849 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2850 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2851 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2852 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2855 // Move scalar to XMM zero-extended
2856 // movd to XMM register zero-extends
2857 let AddedComplexity = 15 in {
2858 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2859 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2860 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2861 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2862 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2863 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2864 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2865 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2866 (MOVLPSrr (V_SET0), VR128:$src)>, Requires<[HasSSE2]>;
2869 // Splat v2f64 / v2i64
2870 let AddedComplexity = 10 in {
2871 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2872 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2873 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2874 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2875 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2876 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2877 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2878 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2881 // Special unary SHUFPSrri case.
2882 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2883 SHUFP_unary_shuffle_mask:$sm)),
2884 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2885 Requires<[HasSSE1]>;
2886 // Special unary SHUFPDrri case.
2887 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2888 SHUFP_unary_shuffle_mask:$sm)),
2889 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2890 Requires<[HasSSE2]>;
2891 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2892 def : Pat<(vector_shuffle (bc_v4i32 (memopv4f32 addr:$src1)), (undef),
2893 SHUFP_unary_shuffle_mask:$sm),
2894 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2895 Requires<[HasSSE2]>;
2896 // Special binary v4i32 shuffle cases with SHUFPS.
2897 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2898 PSHUFD_binary_shuffle_mask:$sm)),
2899 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2900 Requires<[HasSSE2]>;
2901 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2902 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2903 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2904 Requires<[HasSSE2]>;
2905 // Special binary v2i64 shuffle cases using SHUFPDrri.
2906 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2907 SHUFP_shuffle_mask:$sm)),
2908 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2909 Requires<[HasSSE2]>;
2910 // Special unary SHUFPDrri case.
2911 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2912 SHUFP_unary_shuffle_mask:$sm)),
2913 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2914 Requires<[HasSSE2]>;
2916 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2917 let AddedComplexity = 10 in {
2918 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2919 UNPCKL_v_undef_shuffle_mask)),
2920 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2921 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2922 UNPCKL_v_undef_shuffle_mask)),
2923 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2924 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2925 UNPCKL_v_undef_shuffle_mask)),
2926 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2927 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2928 UNPCKL_v_undef_shuffle_mask)),
2929 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2932 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2933 let AddedComplexity = 10 in {
2934 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2935 UNPCKH_v_undef_shuffle_mask)),
2936 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2937 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2938 UNPCKH_v_undef_shuffle_mask)),
2939 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2940 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2941 UNPCKH_v_undef_shuffle_mask)),
2942 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2943 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2944 UNPCKH_v_undef_shuffle_mask)),
2945 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2948 let AddedComplexity = 15 in {
2949 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2950 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2951 MOVHP_shuffle_mask)),
2952 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2954 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2955 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2956 MOVHLPS_shuffle_mask)),
2957 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2959 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2960 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2961 MOVHLPS_v_undef_shuffle_mask)),
2962 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2963 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2964 MOVHLPS_v_undef_shuffle_mask)),
2965 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2968 let AddedComplexity = 20 in {
2969 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2970 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2971 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2972 MOVLP_shuffle_mask)),
2973 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2974 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2975 MOVLP_shuffle_mask)),
2976 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2977 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memop addr:$src2),
2978 MOVHP_shuffle_mask)),
2979 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2980 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2981 MOVHP_shuffle_mask)),
2982 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2984 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2985 (bc_v4i32 (memopv2i64 addr:$src2)),
2986 MOVLP_shuffle_mask)),
2987 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2988 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2989 MOVLP_shuffle_mask)),
2990 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2991 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2992 (bc_v4i32 (memopv2i64 addr:$src2)),
2993 MOVHP_shuffle_mask)),
2994 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2995 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memop addr:$src2),
2996 MOVHP_shuffle_mask)),
2997 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3000 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3001 // (store (vector_shuffle (load addr), v2, <0, 1, 4, 5>), addr) using MOVHPS
3002 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3003 MOVLP_shuffle_mask)), addr:$src1),
3004 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3005 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3006 MOVLP_shuffle_mask)), addr:$src1),
3007 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3008 def : Pat<(store (v4f32 (vector_shuffle (memop addr:$src1), VR128:$src2,
3009 MOVHP_shuffle_mask)), addr:$src1),
3010 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3011 def : Pat<(store (v2f64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3012 MOVHP_shuffle_mask)), addr:$src1),
3013 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3015 def : Pat<(store (v4i32 (vector_shuffle
3016 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3017 MOVLP_shuffle_mask)), addr:$src1),
3018 (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3019 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3020 MOVLP_shuffle_mask)), addr:$src1),
3021 (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3022 def : Pat<(store (v4i32 (vector_shuffle
3023 (bc_v4i32 (memopv2i64 addr:$src1)), VR128:$src2,
3024 MOVHP_shuffle_mask)), addr:$src1),
3025 (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
3026 def : Pat<(store (v2i64 (vector_shuffle (memop addr:$src1), VR128:$src2,
3027 MOVHP_shuffle_mask)), addr:$src1),
3028 (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3031 let AddedComplexity = 15 in {
3032 // Setting the lowest element in the vector.
3033 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3034 MOVL_shuffle_mask)),
3035 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3036 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
3037 MOVL_shuffle_mask)),
3038 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3040 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
3041 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
3042 MOVLP_shuffle_mask)),
3043 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3044 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
3045 MOVLP_shuffle_mask)),
3046 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3049 // Set lowest element and zero upper elements.
3050 let AddedComplexity = 15 in
3051 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
3052 MOVL_shuffle_mask)),
3053 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3054 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3055 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3057 // Some special case pandn patterns.
3058 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3060 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3061 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3063 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3064 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3066 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3068 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3069 (memop addr:$src2))),
3070 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3071 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3072 (memop addr:$src2))),
3073 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3074 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3075 (memop addr:$src2))),
3076 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3078 // vector -> vector casts
3079 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3080 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3081 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3082 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3083 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3084 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3085 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3086 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3088 // Use movaps / movups for SSE integer load / store (one byte shorter).
3089 def : Pat<(alignedloadv4i32 addr:$src),
3090 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3091 def : Pat<(loadv4i32 addr:$src),
3092 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3093 def : Pat<(alignedloadv2i64 addr:$src),
3094 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3095 def : Pat<(loadv2i64 addr:$src),
3096 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3098 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3099 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3100 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3101 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3102 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3103 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3104 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3105 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3106 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3107 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3108 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3109 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3110 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3111 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3112 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3113 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3115 //===----------------------------------------------------------------------===//
3116 // SSE4.1 Instructions
3117 //===----------------------------------------------------------------------===//
3119 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3120 bits<8> opcsd, bits<8> opcpd,
3125 Intrinsic V2F64Int> {
3126 // Intrinsic operation, reg.
3127 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3128 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3129 !strconcat(OpcodeStr,
3130 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3131 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3134 // Intrinsic operation, mem.
3135 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3136 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3137 !strconcat(OpcodeStr,
3138 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3139 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3142 // Vector intrinsic operation, reg
3143 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3144 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3145 !strconcat(OpcodeStr,
3146 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3147 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3150 // Vector intrinsic operation, mem
3151 def PSm_Int : SS4AIi8<opcps, MRMSrcMem,
3152 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3153 !strconcat(OpcodeStr,
3154 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3156 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3159 // Intrinsic operation, reg.
3160 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3161 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3162 !strconcat(OpcodeStr,
3163 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3164 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3167 // Intrinsic operation, mem.
3168 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3169 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3170 !strconcat(OpcodeStr,
3171 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3172 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3175 // Vector intrinsic operation, reg
3176 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3177 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3178 !strconcat(OpcodeStr,
3179 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3180 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3183 // Vector intrinsic operation, mem
3184 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3185 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3186 !strconcat(OpcodeStr,
3187 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3189 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3193 // FP round - roundss, roundps, roundsd, roundpd
3194 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3195 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3196 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3198 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3199 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3200 Intrinsic IntId128> {
3201 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3203 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3204 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3205 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3207 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3210 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3213 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3214 int_x86_sse41_phminposuw>;
3216 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3217 let Constraints = "$src1 = $dst" in {
3218 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3219 Intrinsic IntId128, bit Commutable = 0> {
3220 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3221 (ins VR128:$src1, VR128:$src2),
3222 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3223 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3225 let isCommutable = Commutable;
3227 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3228 (ins VR128:$src1, i128mem:$src2),
3229 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3231 (IntId128 VR128:$src1,
3232 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3236 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3237 int_x86_sse41_pcmpeqq, 1>;
3238 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3239 int_x86_sse41_packusdw, 0>;
3240 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3241 int_x86_sse41_pminsb, 1>;
3242 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3243 int_x86_sse41_pminsd, 1>;
3244 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3245 int_x86_sse41_pminud, 1>;
3246 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3247 int_x86_sse41_pminuw, 1>;
3248 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3249 int_x86_sse41_pmaxsb, 1>;
3250 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3251 int_x86_sse41_pmaxsd, 1>;
3252 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3253 int_x86_sse41_pmaxud, 1>;
3254 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3255 int_x86_sse41_pmaxuw, 1>;
3257 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3258 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3259 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3260 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3263 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3264 let Constraints = "$src1 = $dst" in {
3265 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3266 SDNode OpNode, Intrinsic IntId128,
3267 bit Commutable = 0> {
3268 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3269 (ins VR128:$src1, VR128:$src2),
3270 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3271 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3272 VR128:$src2))]>, OpSize {
3273 let isCommutable = Commutable;
3275 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3276 (ins VR128:$src1, VR128:$src2),
3277 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3278 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3280 let isCommutable = Commutable;
3282 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3283 (ins VR128:$src1, i128mem:$src2),
3284 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3286 (OpNode VR128:$src1, (memop addr:$src2)))]>, OpSize;
3287 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3288 (ins VR128:$src1, i128mem:$src2),
3289 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3291 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3295 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
3296 int_x86_sse41_pmulld, 1>;
3297 defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
3298 int_x86_sse41_pmuldq, 1>;
3301 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3302 let Constraints = "$src1 = $dst" in {
3303 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3304 Intrinsic IntId128, bit Commutable = 0> {
3305 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3306 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3307 !strconcat(OpcodeStr,
3308 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3310 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3312 let isCommutable = Commutable;
3314 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3315 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3316 !strconcat(OpcodeStr,
3317 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3319 (IntId128 VR128:$src1,
3320 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3325 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3326 int_x86_sse41_blendps, 0>;
3327 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3328 int_x86_sse41_blendpd, 0>;
3329 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3330 int_x86_sse41_pblendw, 0>;
3331 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3332 int_x86_sse41_dpps, 1>;
3333 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3334 int_x86_sse41_dppd, 1>;
3335 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3336 int_x86_sse41_mpsadbw, 1>;
3339 /// SS41I_ternary_int - SSE 4.1 ternary operator
3340 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3341 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3342 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3343 (ins VR128:$src1, VR128:$src2),
3344 !strconcat(OpcodeStr,
3345 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3346 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3349 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3350 (ins VR128:$src1, i128mem:$src2),
3351 !strconcat(OpcodeStr,
3352 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3355 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3359 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3360 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3361 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3364 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3365 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3366 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3367 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3369 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3370 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3372 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3375 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3376 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3377 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3378 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3379 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3380 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3382 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3383 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3384 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3385 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3387 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3388 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3390 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3393 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3394 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3395 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3396 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3398 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3399 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3400 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3401 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3403 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3404 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3406 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3409 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3410 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3413 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3414 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3415 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3416 (ins VR128:$src1, i32i8imm:$src2),
3417 !strconcat(OpcodeStr,
3418 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3419 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3421 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3422 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3423 !strconcat(OpcodeStr,
3424 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3427 // There's an AssertZext in the way of writing the store pattern
3428 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3431 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3434 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3435 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3436 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3437 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3438 !strconcat(OpcodeStr,
3439 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3442 // There's an AssertZext in the way of writing the store pattern
3443 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3446 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3449 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3450 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3451 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3452 (ins VR128:$src1, i32i8imm:$src2),
3453 !strconcat(OpcodeStr,
3454 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3456 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3457 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3458 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3459 !strconcat(OpcodeStr,
3460 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3461 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3462 addr:$dst)]>, OpSize;
3465 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3468 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3470 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3471 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3472 (ins VR128:$src1, i32i8imm:$src2),
3473 !strconcat(OpcodeStr,
3474 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3476 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3478 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3479 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3480 !strconcat(OpcodeStr,
3481 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3482 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3483 addr:$dst)]>, OpSize;
3486 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3488 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3489 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3492 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3493 Requires<[HasSSE41]>;
3495 let Constraints = "$src1 = $dst" in {
3496 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3497 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3498 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3499 !strconcat(OpcodeStr,
3500 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3502 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3503 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3504 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3505 !strconcat(OpcodeStr,
3506 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3508 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3509 imm:$src3))]>, OpSize;
3513 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3515 let Constraints = "$src1 = $dst" in {
3516 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3517 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3518 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3519 !strconcat(OpcodeStr,
3520 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3522 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3524 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3525 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3526 !strconcat(OpcodeStr,
3527 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3529 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3530 imm:$src3)))]>, OpSize;
3534 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3536 let Constraints = "$src1 = $dst" in {
3537 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3538 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3539 (ins VR128:$src1, FR32:$src2, i32i8imm:$src3),
3540 !strconcat(OpcodeStr,
3541 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3543 (X86insrtps VR128:$src1, FR32:$src2, imm:$src3))]>, OpSize;
3544 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3545 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3546 !strconcat(OpcodeStr,
3547 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3549 (X86insrtps VR128:$src1, (loadf32 addr:$src2),
3550 imm:$src3))]>, OpSize;
3554 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3556 let Defs = [EFLAGS] in {
3557 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3558 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3559 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3560 "ptest \t{$src2, $src1|$src1, $src2}", []>, OpSize;
3563 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3564 "movntdqa\t{$src, $dst|$dst, $src}",
3565 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
3567 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3568 let Constraints = "$src1 = $dst" in {
3569 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3570 Intrinsic IntId128, bit Commutable = 0> {
3571 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3572 (ins VR128:$src1, VR128:$src2),
3573 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3574 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3576 let isCommutable = Commutable;
3578 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3579 (ins VR128:$src1, i128mem:$src2),
3580 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3582 (IntId128 VR128:$src1,
3583 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3587 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3589 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3590 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3591 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3592 (PCMPGTQrm VR128:$src1, addr:$src2)>;