1 //====- X86InstrSSE.td - Describe the X86 Instruction Set -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // SSE specific DAG Nodes.
18 //===----------------------------------------------------------------------===//
20 def X86loadp : SDNode<"X86ISD::LOAD_PACK", SDTLoad,
22 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
23 [SDNPCommutative, SDNPAssociative]>;
24 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
25 [SDNPCommutative, SDNPAssociative]>;
26 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest,
28 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest,
30 def X86s2vec : SDNode<"X86ISD::S2VEC",
31 SDTypeProfile<1, 1, []>, []>;
32 def X86zexts2vec : SDNode<"X86ISD::ZEXT_S2VEC",
33 SDTypeProfile<1, 1, []>, []>;
34 def X86pextrw : SDNode<"X86ISD::PEXTRW",
35 SDTypeProfile<1, 2, []>, []>;
36 def X86pinsrw : SDNode<"X86ISD::PINSRW",
37 SDTypeProfile<1, 3, []>, []>;
39 //===----------------------------------------------------------------------===//
40 // SSE pattern fragments
41 //===----------------------------------------------------------------------===//
43 def X86loadpf32 : PatFrag<(ops node:$ptr), (f32 (X86loadp node:$ptr))>;
44 def X86loadpf64 : PatFrag<(ops node:$ptr), (f64 (X86loadp node:$ptr))>;
46 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
47 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
48 def loadv16i8 : PatFrag<(ops node:$ptr), (v16i8 (load node:$ptr))>;
49 def loadv8i16 : PatFrag<(ops node:$ptr), (v8i16 (load node:$ptr))>;
50 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
51 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
53 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
54 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
55 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
56 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
57 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
58 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
60 def fp32imm0 : PatLeaf<(f32 fpimm), [{
61 return N->isExactlyValue(+0.0);
64 def PSxLDQ_imm : SDNodeXForm<imm, [{
65 // Transformation function: imm >> 3
66 return getI32Imm(N->getValue() >> 3);
69 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
71 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
72 return getI8Imm(X86::getShuffleSHUFImmediate(N));
75 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
77 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
78 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
81 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
83 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
84 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
87 def SSE_splat_mask : PatLeaf<(build_vector), [{
88 return X86::isSplatMask(N);
89 }], SHUFFLE_get_shuf_imm>;
91 def SSE_splat_v2_mask : PatLeaf<(build_vector), [{
92 return X86::isSplatMask(N);
95 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
96 return X86::isMOVHLPSMask(N);
99 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
100 return X86::isMOVHPMask(N);
103 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
104 return X86::isMOVLPMask(N);
107 def MOVS_shuffle_mask : PatLeaf<(build_vector), [{
108 return X86::isMOVSMask(N);
111 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
112 return X86::isMOVSHDUPMask(N);
115 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
116 return X86::isMOVSLDUPMask(N);
119 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
120 return X86::isUNPCKLMask(N);
123 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
124 return X86::isUNPCKHMask(N);
127 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
128 return X86::isUNPCKL_v_undef_Mask(N);
131 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
132 return X86::isPSHUFDMask(N);
133 }], SHUFFLE_get_shuf_imm>;
135 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
136 return X86::isPSHUFHWMask(N);
137 }], SHUFFLE_get_pshufhw_imm>;
139 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
140 return X86::isPSHUFLWMask(N);
141 }], SHUFFLE_get_pshuflw_imm>;
143 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
144 return X86::isPSHUFDMask(N);
145 }], SHUFFLE_get_shuf_imm>;
147 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
148 return X86::isSHUFPMask(N);
149 }], SHUFFLE_get_shuf_imm>;
151 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
152 return X86::isSHUFPMask(N);
153 }], SHUFFLE_get_shuf_imm>;
155 //===----------------------------------------------------------------------===//
156 // SSE scalar FP Instructions
157 //===----------------------------------------------------------------------===//
159 // Instruction templates
160 // SSI - SSE1 instructions with XS prefix.
161 // SDI - SSE2 instructions with XD prefix.
162 // PSI - SSE1 instructions with TB prefix.
163 // PDI - SSE2 instructions with TB and OpSize prefixes.
164 // PSIi8 - SSE1 instructions with ImmT == Imm8 and TB prefix.
165 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
166 // S3I - SSE3 instructions with TB and OpSize prefixes.
167 // S3SI - SSE3 instructions with XS prefix.
168 // S3DI - SSE3 instructions with XD prefix.
169 class SSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
170 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE1]>;
171 class SDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
172 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE2]>;
173 class PSI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
174 : I<o, F, ops, asm, pattern>, TB, Requires<[HasSSE1]>;
175 class PDI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
176 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE2]>;
177 class PSIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
178 : X86Inst<o, F, Imm8, ops, asm>, TB, Requires<[HasSSE1]> {
179 let Pattern = pattern;
181 class PDIi8<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
182 : X86Inst<o, F, Imm8, ops, asm>, TB, OpSize, Requires<[HasSSE2]> {
183 let Pattern = pattern;
185 class S3SI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
186 : I<o, F, ops, asm, pattern>, XS, Requires<[HasSSE3]>;
187 class S3DI<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
188 : I<o, F, ops, asm, pattern>, XD, Requires<[HasSSE3]>;
189 class S3I<bits<8> o, Format F, dag ops, string asm, list<dag> pattern>
190 : I<o, F, ops, asm, pattern>, TB, OpSize, Requires<[HasSSE3]>;
192 //===----------------------------------------------------------------------===//
193 // Helpers for defining instructions that directly correspond to intrinsics.
194 class SS_Intr<bits<8> o, string asm, Intrinsic IntId>
195 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
196 [(set VR128:$dst, (v4f32 (IntId VR128:$src)))]>;
197 class SS_Intm<bits<8> o, string asm, Intrinsic IntId>
198 : SSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
199 [(set VR128:$dst, (v4f32 (IntId (load addr:$src))))]>;
200 class SD_Intr<bits<8> o, string asm, Intrinsic IntId>
201 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
202 [(set VR128:$dst, (v2f64 (IntId VR128:$src)))]>;
203 class SD_Intm<bits<8> o, string asm, Intrinsic IntId>
204 : SDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
205 [(set VR128:$dst, (v2f64 (IntId (load addr:$src))))]>;
207 class SS_Intrr<bits<8> o, string asm, Intrinsic IntId>
208 : SSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
209 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
210 class SS_Intrm<bits<8> o, string asm, Intrinsic IntId>
211 : SSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
212 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
213 class SD_Intrr<bits<8> o, string asm, Intrinsic IntId>
214 : SDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
215 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
216 class SD_Intrm<bits<8> o, string asm, Intrinsic IntId>
217 : SDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
218 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
220 class PS_Intr<bits<8> o, string asm, Intrinsic IntId>
221 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
222 [(set VR128:$dst, (IntId VR128:$src))]>;
223 class PS_Intm<bits<8> o, string asm, Intrinsic IntId>
224 : PSI<o, MRMSrcMem, (ops VR128:$dst, f32mem:$src), asm,
225 [(set VR128:$dst, (IntId (loadv4f32 addr:$src)))]>;
226 class PD_Intr<bits<8> o, string asm, Intrinsic IntId>
227 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src), asm,
228 [(set VR128:$dst, (IntId VR128:$src))]>;
229 class PD_Intm<bits<8> o, string asm, Intrinsic IntId>
230 : PDI<o, MRMSrcMem, (ops VR128:$dst, f64mem:$src), asm,
231 [(set VR128:$dst, (IntId (loadv2f64 addr:$src)))]>;
233 class PS_Intrr<bits<8> o, string asm, Intrinsic IntId>
234 : PSI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
235 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
236 class PS_Intrm<bits<8> o, string asm, Intrinsic IntId>
237 : PSI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f32mem:$src2), asm,
238 [(set VR128:$dst, (IntId VR128:$src1, (loadv4f32 addr:$src2)))]>;
239 class PD_Intrr<bits<8> o, string asm, Intrinsic IntId>
240 : PDI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
241 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
242 class PD_Intrm<bits<8> o, string asm, Intrinsic IntId>
243 : PDI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2), asm,
244 [(set VR128:$dst, (IntId VR128:$src1, (loadv2f64 addr:$src2)))]>;
246 class S3D_Intrr<bits<8> o, string asm, Intrinsic IntId>
247 : S3DI<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
248 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
249 class S3D_Intrm<bits<8> o, string asm, Intrinsic IntId>
250 : S3DI<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
251 [(set VR128:$dst, (v4f32 (IntId VR128:$src1,
252 (loadv4f32 addr:$src2))))]>;
253 class S3_Intrr<bits<8> o, string asm, Intrinsic IntId>
254 : S3I<o, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2), asm,
255 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
256 class S3_Intrm<bits<8> o, string asm, Intrinsic IntId>
257 : S3I<o, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2), asm,
258 [(set VR128:$dst, (v2f64 (IntId VR128:$src1,
259 (loadv2f64 addr:$src2))))]>;
261 // Some 'special' instructions
262 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (ops FR32:$dst),
263 "#IMPLICIT_DEF $dst",
264 [(set FR32:$dst, (undef))]>, Requires<[HasSSE2]>;
265 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (ops FR64:$dst),
266 "#IMPLICIT_DEF $dst",
267 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
269 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
270 // scheduler into a branch sequence.
271 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
272 def CMOV_FR32 : I<0, Pseudo,
273 (ops FR32:$dst, FR32:$t, FR32:$f, i8imm:$cond),
274 "#CMOV_FR32 PSEUDO!",
275 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond))]>;
276 def CMOV_FR64 : I<0, Pseudo,
277 (ops FR64:$dst, FR64:$t, FR64:$f, i8imm:$cond),
278 "#CMOV_FR64 PSEUDO!",
279 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond))]>;
280 def CMOV_V4F32 : I<0, Pseudo,
281 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
282 "#CMOV_V4F32 PSEUDO!",
284 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
285 def CMOV_V2F64 : I<0, Pseudo,
286 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
287 "#CMOV_V2F64 PSEUDO!",
289 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
290 def CMOV_V2I64 : I<0, Pseudo,
291 (ops VR128:$dst, VR128:$t, VR128:$f, i8imm:$cond),
292 "#CMOV_V2I64 PSEUDO!",
294 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond)))]>;
298 def MOVSSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, FR32:$src),
299 "movss {$src, $dst|$dst, $src}", []>;
300 def MOVSSrm : SSI<0x10, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
301 "movss {$src, $dst|$dst, $src}",
302 [(set FR32:$dst, (loadf32 addr:$src))]>;
303 def MOVSDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, FR64:$src),
304 "movsd {$src, $dst|$dst, $src}", []>;
305 def MOVSDrm : SDI<0x10, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
306 "movsd {$src, $dst|$dst, $src}",
307 [(set FR64:$dst, (loadf64 addr:$src))]>;
309 def MOVSSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, FR32:$src),
310 "movss {$src, $dst|$dst, $src}",
311 [(store FR32:$src, addr:$dst)]>;
312 def MOVSDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, FR64:$src),
313 "movsd {$src, $dst|$dst, $src}",
314 [(store FR64:$src, addr:$dst)]>;
316 // Arithmetic instructions
317 let isTwoAddress = 1 in {
318 let isCommutable = 1 in {
319 def ADDSSrr : SSI<0x58, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
320 "addss {$src2, $dst|$dst, $src2}",
321 [(set FR32:$dst, (fadd FR32:$src1, FR32:$src2))]>;
322 def ADDSDrr : SDI<0x58, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
323 "addsd {$src2, $dst|$dst, $src2}",
324 [(set FR64:$dst, (fadd FR64:$src1, FR64:$src2))]>;
325 def MULSSrr : SSI<0x59, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
326 "mulss {$src2, $dst|$dst, $src2}",
327 [(set FR32:$dst, (fmul FR32:$src1, FR32:$src2))]>;
328 def MULSDrr : SDI<0x59, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
329 "mulsd {$src2, $dst|$dst, $src2}",
330 [(set FR64:$dst, (fmul FR64:$src1, FR64:$src2))]>;
333 def ADDSSrm : SSI<0x58, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
334 "addss {$src2, $dst|$dst, $src2}",
335 [(set FR32:$dst, (fadd FR32:$src1, (loadf32 addr:$src2)))]>;
336 def ADDSDrm : SDI<0x58, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
337 "addsd {$src2, $dst|$dst, $src2}",
338 [(set FR64:$dst, (fadd FR64:$src1, (loadf64 addr:$src2)))]>;
339 def MULSSrm : SSI<0x59, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
340 "mulss {$src2, $dst|$dst, $src2}",
341 [(set FR32:$dst, (fmul FR32:$src1, (loadf32 addr:$src2)))]>;
342 def MULSDrm : SDI<0x59, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
343 "mulsd {$src2, $dst|$dst, $src2}",
344 [(set FR64:$dst, (fmul FR64:$src1, (loadf64 addr:$src2)))]>;
346 def DIVSSrr : SSI<0x5E, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
347 "divss {$src2, $dst|$dst, $src2}",
348 [(set FR32:$dst, (fdiv FR32:$src1, FR32:$src2))]>;
349 def DIVSSrm : SSI<0x5E, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
350 "divss {$src2, $dst|$dst, $src2}",
351 [(set FR32:$dst, (fdiv FR32:$src1, (loadf32 addr:$src2)))]>;
352 def DIVSDrr : SDI<0x5E, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
353 "divsd {$src2, $dst|$dst, $src2}",
354 [(set FR64:$dst, (fdiv FR64:$src1, FR64:$src2))]>;
355 def DIVSDrm : SDI<0x5E, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
356 "divsd {$src2, $dst|$dst, $src2}",
357 [(set FR64:$dst, (fdiv FR64:$src1, (loadf64 addr:$src2)))]>;
359 def SUBSSrr : SSI<0x5C, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
360 "subss {$src2, $dst|$dst, $src2}",
361 [(set FR32:$dst, (fsub FR32:$src1, FR32:$src2))]>;
362 def SUBSSrm : SSI<0x5C, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
363 "subss {$src2, $dst|$dst, $src2}",
364 [(set FR32:$dst, (fsub FR32:$src1, (loadf32 addr:$src2)))]>;
365 def SUBSDrr : SDI<0x5C, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
366 "subsd {$src2, $dst|$dst, $src2}",
367 [(set FR64:$dst, (fsub FR64:$src1, FR64:$src2))]>;
368 def SUBSDrm : SDI<0x5C, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f64mem:$src2),
369 "subsd {$src2, $dst|$dst, $src2}",
370 [(set FR64:$dst, (fsub FR64:$src1, (loadf64 addr:$src2)))]>;
373 def SQRTSSr : SSI<0x51, MRMSrcReg, (ops FR32:$dst, FR32:$src),
374 "sqrtss {$src, $dst|$dst, $src}",
375 [(set FR32:$dst, (fsqrt FR32:$src))]>;
376 def SQRTSSm : SSI<0x51, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
377 "sqrtss {$src, $dst|$dst, $src}",
378 [(set FR32:$dst, (fsqrt (loadf32 addr:$src)))]>;
379 def SQRTSDr : SDI<0x51, MRMSrcReg, (ops FR64:$dst, FR64:$src),
380 "sqrtsd {$src, $dst|$dst, $src}",
381 [(set FR64:$dst, (fsqrt FR64:$src))]>;
382 def SQRTSDm : SDI<0x51, MRMSrcMem, (ops FR64:$dst, f64mem:$src),
383 "sqrtsd {$src, $dst|$dst, $src}",
384 [(set FR64:$dst, (fsqrt (loadf64 addr:$src)))]>;
386 def RSQRTSSr : SSI<0x52, MRMSrcReg, (ops FR32:$dst, FR32:$src),
387 "rsqrtss {$src, $dst|$dst, $src}", []>;
388 def RSQRTSSm : SSI<0x52, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
389 "rsqrtss {$src, $dst|$dst, $src}", []>;
390 def RCPSSr : SSI<0x53, MRMSrcReg, (ops FR32:$dst, FR32:$src),
391 "rcpss {$src, $dst|$dst, $src}", []>;
392 def RCPSSm : SSI<0x53, MRMSrcMem, (ops FR32:$dst, f32mem:$src),
393 "rcpss {$src, $dst|$dst, $src}", []>;
395 let isTwoAddress = 1 in {
396 def MAXSSrr : SSI<0x5F, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
397 "maxss {$src2, $dst|$dst, $src2}", []>;
398 def MAXSSrm : SSI<0x5F, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
399 "maxss {$src2, $dst|$dst, $src2}", []>;
400 def MAXSDrr : SDI<0x5F, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
401 "maxsd {$src2, $dst|$dst, $src2}", []>;
402 def MAXSDrm : SDI<0x5F, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
403 "maxsd {$src2, $dst|$dst, $src2}", []>;
404 def MINSSrr : SSI<0x5D, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
405 "minss {$src2, $dst|$dst, $src2}", []>;
406 def MINSSrm : SSI<0x5D, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f32mem:$src2),
407 "minss {$src2, $dst|$dst, $src2}", []>;
408 def MINSDrr : SDI<0x5D, MRMSrcReg, (ops FR64:$dst, FR32:$src1, FR64:$src2),
409 "minsd {$src2, $dst|$dst, $src2}", []>;
410 def MINSDrm : SDI<0x5D, MRMSrcMem, (ops FR64:$dst, FR32:$src1, f64mem:$src2),
411 "minsd {$src2, $dst|$dst, $src2}", []>;
414 // Aliases to match intrinsics which expect XMM operand(s).
415 let isTwoAddress = 1 in {
416 let isCommutable = 1 in {
417 def Int_ADDSSrr : SS_Intrr<0x58, "addss {$src2, $dst|$dst, $src2}",
419 def Int_ADDSDrr : SD_Intrr<0x58, "addsd {$src2, $dst|$dst, $src2}",
420 int_x86_sse2_add_sd>;
421 def Int_MULSSrr : SS_Intrr<0x59, "mulss {$src2, $dst|$dst, $src2}",
423 def Int_MULSDrr : SD_Intrr<0x59, "mulsd {$src2, $dst|$dst, $src2}",
424 int_x86_sse2_mul_sd>;
427 def Int_ADDSSrm : SS_Intrm<0x58, "addss {$src2, $dst|$dst, $src2}",
429 def Int_ADDSDrm : SD_Intrm<0x58, "addsd {$src2, $dst|$dst, $src2}",
430 int_x86_sse2_add_sd>;
431 def Int_MULSSrm : SS_Intrm<0x59, "mulss {$src2, $dst|$dst, $src2}",
433 def Int_MULSDrm : SD_Intrm<0x59, "mulsd {$src2, $dst|$dst, $src2}",
434 int_x86_sse2_mul_sd>;
436 def Int_DIVSSrr : SS_Intrr<0x5E, "divss {$src2, $dst|$dst, $src2}",
438 def Int_DIVSSrm : SS_Intrm<0x5E, "divss {$src2, $dst|$dst, $src2}",
440 def Int_DIVSDrr : SD_Intrr<0x5E, "divsd {$src2, $dst|$dst, $src2}",
441 int_x86_sse2_div_sd>;
442 def Int_DIVSDrm : SD_Intrm<0x5E, "divsd {$src2, $dst|$dst, $src2}",
443 int_x86_sse2_div_sd>;
445 def Int_SUBSSrr : SS_Intrr<0x5C, "subss {$src2, $dst|$dst, $src2}",
447 def Int_SUBSSrm : SS_Intrm<0x5C, "subss {$src2, $dst|$dst, $src2}",
449 def Int_SUBSDrr : SD_Intrr<0x5C, "subsd {$src2, $dst|$dst, $src2}",
450 int_x86_sse2_sub_sd>;
451 def Int_SUBSDrm : SD_Intrm<0x5C, "subsd {$src2, $dst|$dst, $src2}",
452 int_x86_sse2_sub_sd>;
455 def Int_SQRTSSr : SS_Intr<0x51, "sqrtss {$src, $dst|$dst, $src}",
456 int_x86_sse_sqrt_ss>;
457 def Int_SQRTSSm : SS_Intm<0x51, "sqrtss {$src, $dst|$dst, $src}",
458 int_x86_sse_sqrt_ss>;
459 def Int_SQRTSDr : SD_Intr<0x51, "sqrtsd {$src, $dst|$dst, $src}",
460 int_x86_sse2_sqrt_sd>;
461 def Int_SQRTSDm : SD_Intm<0x51, "sqrtsd {$src, $dst|$dst, $src}",
462 int_x86_sse2_sqrt_sd>;
464 def Int_RSQRTSSr : SS_Intr<0x52, "rsqrtss {$src, $dst|$dst, $src}",
465 int_x86_sse_rsqrt_ss>;
466 def Int_RSQRTSSm : SS_Intm<0x52, "rsqrtss {$src, $dst|$dst, $src}",
467 int_x86_sse_rsqrt_ss>;
468 def Int_RCPSSr : SS_Intr<0x53, "rcpss {$src, $dst|$dst, $src}",
470 def Int_RCPSSm : SS_Intm<0x53, "rcpss {$src, $dst|$dst, $src}",
473 let isTwoAddress = 1 in {
474 def Int_MAXSSrr : SS_Intrr<0x5F, "maxss {$src2, $dst|$dst, $src2}",
476 def Int_MAXSSrm : SS_Intrm<0x5F, "maxss {$src2, $dst|$dst, $src2}",
478 def Int_MAXSDrr : SD_Intrr<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
479 int_x86_sse2_max_sd>;
480 def Int_MAXSDrm : SD_Intrm<0x5F, "maxsd {$src2, $dst|$dst, $src2}",
481 int_x86_sse2_max_sd>;
482 def Int_MINSSrr : SS_Intrr<0x5D, "minss {$src2, $dst|$dst, $src2}",
484 def Int_MINSSrm : SS_Intrm<0x5D, "minss {$src2, $dst|$dst, $src2}",
486 def Int_MINSDrr : SD_Intrr<0x5D, "minsd {$src2, $dst|$dst, $src2}",
487 int_x86_sse2_min_sd>;
488 def Int_MINSDrm : SD_Intrm<0x5D, "minsd {$src2, $dst|$dst, $src2}",
489 int_x86_sse2_min_sd>;
492 // Conversion instructions
493 def CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, FR32:$src),
494 "cvttss2si {$src, $dst|$dst, $src}",
495 [(set R32:$dst, (fp_to_sint FR32:$src))]>;
496 def CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
497 "cvttss2si {$src, $dst|$dst, $src}",
498 [(set R32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
499 def CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, FR64:$src),
500 "cvttsd2si {$src, $dst|$dst, $src}",
501 [(set R32:$dst, (fp_to_sint FR64:$src))]>;
502 def CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src),
503 "cvttsd2si {$src, $dst|$dst, $src}",
504 [(set R32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
505 def CVTSD2SSrr: SDI<0x5A, MRMSrcReg, (ops FR32:$dst, FR64:$src),
506 "cvtsd2ss {$src, $dst|$dst, $src}",
507 [(set FR32:$dst, (fround FR64:$src))]>;
508 def CVTSD2SSrm: SDI<0x5A, MRMSrcMem, (ops FR32:$dst, f64mem:$src),
509 "cvtsd2ss {$src, $dst|$dst, $src}",
510 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
511 def CVTSI2SSrr: SSI<0x2A, MRMSrcReg, (ops FR32:$dst, R32:$src),
512 "cvtsi2ss {$src, $dst|$dst, $src}",
513 [(set FR32:$dst, (sint_to_fp R32:$src))]>;
514 def CVTSI2SSrm: SSI<0x2A, MRMSrcMem, (ops FR32:$dst, i32mem:$src),
515 "cvtsi2ss {$src, $dst|$dst, $src}",
516 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
517 def CVTSI2SDrr: SDI<0x2A, MRMSrcReg, (ops FR64:$dst, R32:$src),
518 "cvtsi2sd {$src, $dst|$dst, $src}",
519 [(set FR64:$dst, (sint_to_fp R32:$src))]>;
520 def CVTSI2SDrm: SDI<0x2A, MRMSrcMem, (ops FR64:$dst, i32mem:$src),
521 "cvtsi2sd {$src, $dst|$dst, $src}",
522 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
524 // SSE2 instructions with XS prefix
525 def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops FR64:$dst, FR32:$src),
526 "cvtss2sd {$src, $dst|$dst, $src}",
527 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
529 def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops FR64:$dst, f32mem:$src),
530 "cvtss2sd {$src, $dst|$dst, $src}",
531 [(set FR64:$dst, (fextend (loadf32 addr:$src)))]>, XS,
534 // Match intrinsics which expect XMM operand(s).
535 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
536 "cvtss2si {$src, $dst|$dst, $src}",
537 [(set R32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
538 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (ops R32:$dst, f32mem:$src),
539 "cvtss2si {$src, $dst|$dst, $src}",
540 [(set R32:$dst, (int_x86_sse_cvtss2si
541 (loadv4f32 addr:$src)))]>;
542 def CVTSD2SIrr: SDI<0x2D, MRMSrcReg, (ops R32:$dst, VR128:$src),
543 "cvtsd2si {$src, $dst|$dst, $src}",
544 [(set R32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
545 def CVTSD2SIrm: SDI<0x2D, MRMSrcMem, (ops R32:$dst, f128mem:$src),
546 "cvtsd2si {$src, $dst|$dst, $src}",
547 [(set R32:$dst, (int_x86_sse2_cvtsd2si
548 (loadv2f64 addr:$src)))]>;
550 // Aliases for intrinsics
551 def Int_CVTTSS2SIrr: SSI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
552 "cvttss2si {$src, $dst|$dst, $src}",
553 [(set R32:$dst, (int_x86_sse_cvttss2si VR128:$src))]>;
554 def Int_CVTTSS2SIrm: SSI<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src),
555 "cvttss2si {$src, $dst|$dst, $src}",
556 [(set R32:$dst, (int_x86_sse_cvttss2si
557 (loadv4f32 addr:$src)))]>;
558 def Int_CVTTSD2SIrr: SDI<0x2C, MRMSrcReg, (ops R32:$dst, VR128:$src),
559 "cvttsd2si {$src, $dst|$dst, $src}",
560 [(set R32:$dst, (int_x86_sse2_cvttsd2si VR128:$src))]>;
561 def Int_CVTTSD2SIrm: SDI<0x2C, MRMSrcMem, (ops R32:$dst, f128mem:$src),
562 "cvttsd2si {$src, $dst|$dst, $src}",
563 [(set R32:$dst, (int_x86_sse2_cvttsd2si
564 (loadv2f64 addr:$src)))]>;
566 let isTwoAddress = 1 in {
567 def Int_CVTSI2SSrr: SSI<0x2A, MRMSrcReg,
568 (ops VR128:$dst, VR128:$src1, R32:$src2),
569 "cvtsi2ss {$src2, $dst|$dst, $src2}",
570 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
572 def Int_CVTSI2SSrm: SSI<0x2A, MRMSrcMem,
573 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
574 "cvtsi2ss {$src2, $dst|$dst, $src2}",
575 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
576 (loadi32 addr:$src2)))]>;
579 // Comparison instructions
580 let isTwoAddress = 1 in {
581 def CMPSSrr : SSI<0xC2, MRMSrcReg,
582 (ops FR32:$dst, FR32:$src1, FR32:$src, SSECC:$cc),
583 "cmp${cc}ss {$src, $dst|$dst, $src}",
585 def CMPSSrm : SSI<0xC2, MRMSrcMem,
586 (ops FR32:$dst, FR32:$src1, f32mem:$src, SSECC:$cc),
587 "cmp${cc}ss {$src, $dst|$dst, $src}", []>;
588 def CMPSDrr : SDI<0xC2, MRMSrcReg,
589 (ops FR64:$dst, FR64:$src1, FR64:$src, SSECC:$cc),
590 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
591 def CMPSDrm : SDI<0xC2, MRMSrcMem,
592 (ops FR64:$dst, FR64:$src1, f64mem:$src, SSECC:$cc),
593 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
596 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops FR32:$src1, FR32:$src2),
597 "ucomiss {$src2, $src1|$src1, $src2}",
598 [(X86cmp FR32:$src1, FR32:$src2)]>;
599 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops FR32:$src1, f32mem:$src2),
600 "ucomiss {$src2, $src1|$src1, $src2}",
601 [(X86cmp FR32:$src1, (loadf32 addr:$src2))]>;
602 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops FR64:$src1, FR64:$src2),
603 "ucomisd {$src2, $src1|$src1, $src2}",
604 [(X86cmp FR64:$src1, FR64:$src2)]>;
605 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops FR64:$src1, f64mem:$src2),
606 "ucomisd {$src2, $src1|$src1, $src2}",
607 [(X86cmp FR64:$src1, (loadf64 addr:$src2))]>;
609 // Aliases to match intrinsics which expect XMM operand(s).
610 let isTwoAddress = 1 in {
611 def Int_CMPSSrr : SSI<0xC2, MRMSrcReg,
612 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
613 "cmp${cc}ss {$src, $dst|$dst, $src}",
614 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
615 VR128:$src, imm:$cc))]>;
616 def Int_CMPSSrm : SSI<0xC2, MRMSrcMem,
617 (ops VR128:$dst, VR128:$src1, f32mem:$src, SSECC:$cc),
618 "cmp${cc}ss {$src, $dst|$dst, $src}",
619 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
620 (load addr:$src), imm:$cc))]>;
621 def Int_CMPSDrr : SDI<0xC2, MRMSrcReg,
622 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
623 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
624 def Int_CMPSDrm : SDI<0xC2, MRMSrcMem,
625 (ops VR128:$dst, VR128:$src1, f64mem:$src, SSECC:$cc),
626 "cmp${cc}sd {$src, $dst|$dst, $src}", []>;
629 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
630 "ucomiss {$src2, $src1|$src1, $src2}",
631 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2)]>;
632 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
633 "ucomiss {$src2, $src1|$src1, $src2}",
634 [(X86ucomi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
635 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
636 "ucomisd {$src2, $src1|$src1, $src2}",
637 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
638 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
639 "ucomisd {$src2, $src1|$src1, $src2}",
640 [(X86ucomi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
642 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
643 "comiss {$src2, $src1|$src1, $src2}",
644 [(X86comi (v4f32 VR128:$src1), VR128:$src2)]>;
645 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
646 "comiss {$src2, $src1|$src1, $src2}",
647 [(X86comi (v4f32 VR128:$src1), (loadv4f32 addr:$src2))]>;
648 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (ops VR128:$src1, VR128:$src2),
649 "comisd {$src2, $src1|$src1, $src2}",
650 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2))]>;
651 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (ops VR128:$src1, f128mem:$src2),
652 "comisd {$src2, $src1|$src1, $src2}",
653 [(X86comi (v2f64 VR128:$src1), (loadv2f64 addr:$src2))]>;
655 // Aliases of packed instructions for scalar use. These all have names that
658 // Alias instructions that map fld0 to pxor for sse.
659 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
660 def FsFLD0SS : I<0xEF, MRMInitReg, (ops FR32:$dst),
661 "pxor $dst, $dst", [(set FR32:$dst, fp32imm0)]>,
662 Requires<[HasSSE1]>, TB, OpSize;
663 def FsFLD0SD : I<0xEF, MRMInitReg, (ops FR64:$dst),
664 "pxor $dst, $dst", [(set FR64:$dst, fp64imm0)]>,
665 Requires<[HasSSE2]>, TB, OpSize;
667 // Alias instructions to do FR32 / FR64 reg-to-reg copy using movaps / movapd.
668 // Upper bits are disregarded.
669 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (ops FR32:$dst, FR32:$src),
670 "movaps {$src, $dst|$dst, $src}", []>;
671 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (ops FR64:$dst, FR64:$src),
672 "movapd {$src, $dst|$dst, $src}", []>;
674 // Alias instructions to load FR32 / FR64 from f128mem using movaps / movapd.
675 // Upper bits are disregarded.
676 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (ops FR32:$dst, f128mem:$src),
677 "movaps {$src, $dst|$dst, $src}",
678 [(set FR32:$dst, (X86loadpf32 addr:$src))]>;
679 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (ops FR64:$dst, f128mem:$src),
680 "movapd {$src, $dst|$dst, $src}",
681 [(set FR64:$dst, (X86loadpf64 addr:$src))]>;
683 // Alias bitwise logical operations using SSE logical ops on packed FP values.
684 let isTwoAddress = 1 in {
685 let isCommutable = 1 in {
686 def FsANDPSrr : PSI<0x54, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
687 "andps {$src2, $dst|$dst, $src2}",
688 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
689 def FsANDPDrr : PDI<0x54, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
690 "andpd {$src2, $dst|$dst, $src2}",
691 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
692 def FsORPSrr : PSI<0x56, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
693 "orps {$src2, $dst|$dst, $src2}", []>;
694 def FsORPDrr : PDI<0x56, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
695 "orpd {$src2, $dst|$dst, $src2}", []>;
696 def FsXORPSrr : PSI<0x57, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
697 "xorps {$src2, $dst|$dst, $src2}",
698 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
699 def FsXORPDrr : PDI<0x57, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
700 "xorpd {$src2, $dst|$dst, $src2}",
701 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
703 def FsANDPSrm : PSI<0x54, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
704 "andps {$src2, $dst|$dst, $src2}",
705 [(set FR32:$dst, (X86fand FR32:$src1,
706 (X86loadpf32 addr:$src2)))]>;
707 def FsANDPDrm : PDI<0x54, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
708 "andpd {$src2, $dst|$dst, $src2}",
709 [(set FR64:$dst, (X86fand FR64:$src1,
710 (X86loadpf64 addr:$src2)))]>;
711 def FsORPSrm : PSI<0x56, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
712 "orps {$src2, $dst|$dst, $src2}", []>;
713 def FsORPDrm : PDI<0x56, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
714 "orpd {$src2, $dst|$dst, $src2}", []>;
715 def FsXORPSrm : PSI<0x57, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
716 "xorps {$src2, $dst|$dst, $src2}",
717 [(set FR32:$dst, (X86fxor FR32:$src1,
718 (X86loadpf32 addr:$src2)))]>;
719 def FsXORPDrm : PDI<0x57, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
720 "xorpd {$src2, $dst|$dst, $src2}",
721 [(set FR64:$dst, (X86fxor FR64:$src1,
722 (X86loadpf64 addr:$src2)))]>;
724 def FsANDNPSrr : PSI<0x55, MRMSrcReg, (ops FR32:$dst, FR32:$src1, FR32:$src2),
725 "andnps {$src2, $dst|$dst, $src2}", []>;
726 def FsANDNPSrm : PSI<0x55, MRMSrcMem, (ops FR32:$dst, FR32:$src1, f128mem:$src2),
727 "andnps {$src2, $dst|$dst, $src2}", []>;
728 def FsANDNPDrr : PDI<0x55, MRMSrcReg, (ops FR64:$dst, FR64:$src1, FR64:$src2),
729 "andnpd {$src2, $dst|$dst, $src2}", []>;
730 def FsANDNPDrm : PDI<0x55, MRMSrcMem, (ops FR64:$dst, FR64:$src1, f128mem:$src2),
731 "andnpd {$src2, $dst|$dst, $src2}", []>;
734 //===----------------------------------------------------------------------===//
735 // SSE packed FP Instructions
736 //===----------------------------------------------------------------------===//
738 // Some 'special' instructions
739 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (ops VR128:$dst),
740 "#IMPLICIT_DEF $dst",
741 [(set VR128:$dst, (v4f32 (undef)))]>,
745 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
746 "movaps {$src, $dst|$dst, $src}", []>;
747 def MOVAPSrm : PSI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
748 "movaps {$src, $dst|$dst, $src}",
749 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
750 def MOVAPDrr : PDI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
751 "movapd {$src, $dst|$dst, $src}", []>;
752 def MOVAPDrm : PDI<0x28, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
753 "movapd {$src, $dst|$dst, $src}",
754 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
756 def MOVAPSmr : PSI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
757 "movaps {$src, $dst|$dst, $src}",
758 [(store (v4f32 VR128:$src), addr:$dst)]>;
759 def MOVAPDmr : PDI<0x29, MRMDestMem, (ops f128mem:$dst, VR128:$src),
760 "movapd {$src, $dst|$dst, $src}",
761 [(store (v2f64 VR128:$src), addr:$dst)]>;
763 def MOVUPSrr : PSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
764 "movups {$src, $dst|$dst, $src}", []>;
765 def MOVUPSrm : PSI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
766 "movups {$src, $dst|$dst, $src}",
767 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
768 def MOVUPSmr : PSI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
769 "movups {$src, $dst|$dst, $src}",
770 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
771 def MOVUPDrr : PDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src),
772 "movupd {$src, $dst|$dst, $src}", []>;
773 def MOVUPDrm : PDI<0x10, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
774 "movupd {$src, $dst|$dst, $src}",
775 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
776 def MOVUPDmr : PDI<0x11, MRMDestMem, (ops f128mem:$dst, VR128:$src),
777 "movupd {$src, $dst|$dst, $src}",
778 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
780 let isTwoAddress = 1 in {
781 let AddedComplexity = 20 in {
782 def MOVLPSrm : PSI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
783 "movlps {$src2, $dst|$dst, $src2}",
785 (v4f32 (vector_shuffle VR128:$src1,
786 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
787 MOVLP_shuffle_mask)))]>;
788 def MOVLPDrm : PDI<0x12, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
789 "movlpd {$src2, $dst|$dst, $src2}",
791 (v2f64 (vector_shuffle VR128:$src1,
792 (scalar_to_vector (loadf64 addr:$src2)),
793 MOVLP_shuffle_mask)))]>;
794 def MOVHPSrm : PSI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
795 "movhps {$src2, $dst|$dst, $src2}",
797 (v4f32 (vector_shuffle VR128:$src1,
798 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
799 MOVHP_shuffle_mask)))]>;
800 def MOVHPDrm : PDI<0x16, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f64mem:$src2),
801 "movhpd {$src2, $dst|$dst, $src2}",
803 (v2f64 (vector_shuffle VR128:$src1,
804 (scalar_to_vector (loadf64 addr:$src2)),
805 MOVHP_shuffle_mask)))]>;
809 def MOVLPSmr : PSI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
810 "movlps {$src, $dst|$dst, $src}",
811 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
812 (i32 0))), addr:$dst)]>;
813 def MOVLPDmr : PDI<0x13, MRMDestMem, (ops f64mem:$dst, VR128:$src),
814 "movlpd {$src, $dst|$dst, $src}",
815 [(store (f64 (vector_extract (v2f64 VR128:$src),
816 (i32 0))), addr:$dst)]>;
818 // v2f64 extract element 1 is always custom lowered to unpack high to low
819 // and extract element 0 so the non-store version isn't too horrible.
820 def MOVHPSmr : PSI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
821 "movhps {$src, $dst|$dst, $src}",
822 [(store (f64 (vector_extract
823 (v2f64 (vector_shuffle
824 (bc_v2f64 (v4f32 VR128:$src)), (undef),
825 UNPCKH_shuffle_mask)), (i32 0))),
827 def MOVHPDmr : PDI<0x17, MRMDestMem, (ops f64mem:$dst, VR128:$src),
828 "movhpd {$src, $dst|$dst, $src}",
829 [(store (f64 (vector_extract
830 (v2f64 (vector_shuffle VR128:$src, (undef),
831 UNPCKH_shuffle_mask)), (i32 0))),
834 let isTwoAddress = 1 in {
835 let AddedComplexity = 20 in {
836 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
837 "movlhps {$src2, $dst|$dst, $src2}",
839 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
840 MOVHP_shuffle_mask)))]>;
842 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
843 "movhlps {$src2, $dst|$dst, $src2}",
845 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
846 MOVHLPS_shuffle_mask)))]>;
850 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (ops VR128:$dst, VR128:$src),
851 "movshdup {$src, $dst|$dst, $src}",
852 [(set VR128:$dst, (v4f32 (vector_shuffle
854 MOVSHDUP_shuffle_mask)))]>;
855 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
856 "movshdup {$src, $dst|$dst, $src}",
857 [(set VR128:$dst, (v4f32 (vector_shuffle
858 (loadv4f32 addr:$src), (undef),
859 MOVSHDUP_shuffle_mask)))]>;
861 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
862 "movsldup {$src, $dst|$dst, $src}",
863 [(set VR128:$dst, (v4f32 (vector_shuffle
865 MOVSLDUP_shuffle_mask)))]>;
866 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
867 "movsldup {$src, $dst|$dst, $src}",
868 [(set VR128:$dst, (v4f32 (vector_shuffle
869 (loadv4f32 addr:$src), (undef),
870 MOVSLDUP_shuffle_mask)))]>;
872 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (ops VR128:$dst, VR128:$src),
873 "movddup {$src, $dst|$dst, $src}",
874 [(set VR128:$dst, (v2f64 (vector_shuffle
876 SSE_splat_v2_mask)))]>;
877 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
878 "movddup {$src, $dst|$dst, $src}",
879 [(set VR128:$dst, (v2f64 (vector_shuffle
880 (scalar_to_vector (loadf64 addr:$src)),
882 SSE_splat_v2_mask)))]>;
884 // SSE2 instructions without OpSize prefix
885 def CVTDQ2PSrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
886 "cvtdq2ps {$src, $dst|$dst, $src}",
887 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
888 TB, Requires<[HasSSE2]>;
889 def CVTDQ2PSrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
890 "cvtdq2ps {$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
892 (bc_v4i32 (loadv2i64 addr:$src))))]>,
893 TB, Requires<[HasSSE2]>;
895 // SSE2 instructions with XS prefix
896 def CVTDQ2PDrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
897 "cvtdq2pd {$src, $dst|$dst, $src}",
898 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
899 XS, Requires<[HasSSE2]>;
900 def CVTDQ2PDrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
901 "cvtdq2pd {$src, $dst|$dst, $src}",
902 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
903 (bc_v4i32 (loadv2i64 addr:$src))))]>,
904 XS, Requires<[HasSSE2]>;
906 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
907 "cvtps2dq {$src, $dst|$dst, $src}",
908 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
909 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
910 "cvtps2dq {$src, $dst|$dst, $src}",
911 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
912 (loadv4f32 addr:$src)))]>;
913 // SSE2 packed instructions with XS prefix
914 def CVTTPS2DQrr : I<0x5B, MRMSrcReg, (ops VR128:$dst, VR128:$src),
915 "cvttps2dq {$src, $dst|$dst, $src}",
916 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
917 XS, Requires<[HasSSE2]>;
918 def CVTTPS2DQrm : I<0x5B, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
919 "cvttps2dq {$src, $dst|$dst, $src}",
920 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
921 (loadv4f32 addr:$src)))]>,
922 XS, Requires<[HasSSE2]>;
924 // SSE2 packed instructions with XD prefix
925 def CVTPD2DQrr : I<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
926 "cvtpd2dq {$src, $dst|$dst, $src}",
927 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
928 XD, Requires<[HasSSE2]>;
929 def CVTPD2DQrm : I<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
930 "cvtpd2dq {$src, $dst|$dst, $src}",
931 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
932 (loadv2f64 addr:$src)))]>,
933 XD, Requires<[HasSSE2]>;
934 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
935 "cvttpd2dq {$src, $dst|$dst, $src}",
936 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
937 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (ops VR128:$dst, f128mem:$src),
938 "cvttpd2dq {$src, $dst|$dst, $src}",
939 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
940 (loadv2f64 addr:$src)))]>;
942 // SSE2 instructions without OpSize prefix
943 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
944 "cvtps2pd {$src, $dst|$dst, $src}",
945 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
946 TB, Requires<[HasSSE2]>;
947 def CVTPS2PDrm : I<0x5A, MRMSrcReg, (ops VR128:$dst, f64mem:$src),
948 "cvtps2pd {$src, $dst|$dst, $src}",
949 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
950 (loadv4f32 addr:$src)))]>,
951 TB, Requires<[HasSSE2]>;
953 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, VR128:$src),
954 "cvtpd2ps {$src, $dst|$dst, $src}",
955 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
956 def CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (ops VR128:$dst, f128mem:$src),
957 "cvtpd2ps {$src, $dst|$dst, $src}",
958 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
959 (loadv2f64 addr:$src)))]>;
961 // Match intrinsics which expect XMM operand(s).
962 // Aliases for intrinsics
963 let isTwoAddress = 1 in {
964 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
965 (ops VR128:$dst, VR128:$src1, R32:$src2),
966 "cvtsi2sd {$src2, $dst|$dst, $src2}",
967 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
969 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
970 (ops VR128:$dst, VR128:$src1, i32mem:$src2),
971 "cvtsi2sd {$src2, $dst|$dst, $src2}",
972 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
973 (loadi32 addr:$src2)))]>;
974 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
975 (ops VR128:$dst, VR128:$src1, VR128:$src2),
976 "cvtsd2ss {$src2, $dst|$dst, $src2}",
977 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
979 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
980 (ops VR128:$dst, VR128:$src1, f64mem:$src2),
981 "cvtsd2ss {$src2, $dst|$dst, $src2}",
982 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
983 (loadv2f64 addr:$src2)))]>;
984 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
985 (ops VR128:$dst, VR128:$src1, VR128:$src2),
986 "cvtss2sd {$src2, $dst|$dst, $src2}",
987 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
990 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
991 (ops VR128:$dst, VR128:$src1, f32mem:$src2),
992 "cvtss2sd {$src2, $dst|$dst, $src2}",
993 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
994 (loadv4f32 addr:$src2)))]>, XS,
999 let isTwoAddress = 1 in {
1000 let isCommutable = 1 in {
1001 def ADDPSrr : PSI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1002 "addps {$src2, $dst|$dst, $src2}",
1003 [(set VR128:$dst, (v4f32 (fadd VR128:$src1, VR128:$src2)))]>;
1004 def ADDPDrr : PDI<0x58, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1005 "addpd {$src2, $dst|$dst, $src2}",
1006 [(set VR128:$dst, (v2f64 (fadd VR128:$src1, VR128:$src2)))]>;
1007 def MULPSrr : PSI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1008 "mulps {$src2, $dst|$dst, $src2}",
1009 [(set VR128:$dst, (v4f32 (fmul VR128:$src1, VR128:$src2)))]>;
1010 def MULPDrr : PDI<0x59, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1011 "mulpd {$src2, $dst|$dst, $src2}",
1012 [(set VR128:$dst, (v2f64 (fmul VR128:$src1, VR128:$src2)))]>;
1015 def ADDPSrm : PSI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1016 "addps {$src2, $dst|$dst, $src2}",
1017 [(set VR128:$dst, (v4f32 (fadd VR128:$src1,
1018 (load addr:$src2))))]>;
1019 def ADDPDrm : PDI<0x58, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1020 "addpd {$src2, $dst|$dst, $src2}",
1021 [(set VR128:$dst, (v2f64 (fadd VR128:$src1,
1022 (load addr:$src2))))]>;
1023 def MULPSrm : PSI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1024 "mulps {$src2, $dst|$dst, $src2}",
1025 [(set VR128:$dst, (v4f32 (fmul VR128:$src1,
1026 (load addr:$src2))))]>;
1027 def MULPDrm : PDI<0x59, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1028 "mulpd {$src2, $dst|$dst, $src2}",
1029 [(set VR128:$dst, (v2f64 (fmul VR128:$src1,
1030 (load addr:$src2))))]>;
1032 def DIVPSrr : PSI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1033 "divps {$src2, $dst|$dst, $src2}",
1034 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1, VR128:$src2)))]>;
1035 def DIVPSrm : PSI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1036 "divps {$src2, $dst|$dst, $src2}",
1037 [(set VR128:$dst, (v4f32 (fdiv VR128:$src1,
1038 (load addr:$src2))))]>;
1039 def DIVPDrr : PDI<0x5E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1040 "divpd {$src2, $dst|$dst, $src2}",
1041 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1, VR128:$src2)))]>;
1042 def DIVPDrm : PDI<0x5E, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1043 "divpd {$src2, $dst|$dst, $src2}",
1044 [(set VR128:$dst, (v2f64 (fdiv VR128:$src1,
1045 (load addr:$src2))))]>;
1047 def SUBPSrr : PSI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1048 "subps {$src2, $dst|$dst, $src2}",
1049 [(set VR128:$dst, (v4f32 (fsub VR128:$src1, VR128:$src2)))]>;
1050 def SUBPSrm : PSI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1051 "subps {$src2, $dst|$dst, $src2}",
1052 [(set VR128:$dst, (v4f32 (fsub VR128:$src1,
1053 (load addr:$src2))))]>;
1054 def SUBPDrr : PDI<0x5C, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1055 "subpd {$src2, $dst|$dst, $src2}",
1056 [(set VR128:$dst, (v2f64 (fsub VR128:$src1, VR128:$src2)))]>;
1057 def SUBPDrm : PDI<0x5C, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1058 "subpd {$src2, $dst|$dst, $src2}",
1059 [(set VR128:$dst, (v2f64 (fsub VR128:$src1,
1060 (load addr:$src2))))]>;
1062 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
1063 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1064 "addsubps {$src2, $dst|$dst, $src2}",
1065 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1067 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
1068 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1069 "addsubps {$src2, $dst|$dst, $src2}",
1070 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
1071 (loadv4f32 addr:$src2)))]>;
1072 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
1073 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1074 "addsubpd {$src2, $dst|$dst, $src2}",
1075 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1077 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
1078 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1079 "addsubpd {$src2, $dst|$dst, $src2}",
1080 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
1081 (loadv2f64 addr:$src2)))]>;
1084 def SQRTPSr : PS_Intr<0x51, "sqrtps {$src, $dst|$dst, $src}",
1085 int_x86_sse_sqrt_ps>;
1086 def SQRTPSm : PS_Intm<0x51, "sqrtps {$src, $dst|$dst, $src}",
1087 int_x86_sse_sqrt_ps>;
1088 def SQRTPDr : PD_Intr<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1089 int_x86_sse2_sqrt_pd>;
1090 def SQRTPDm : PD_Intm<0x51, "sqrtpd {$src, $dst|$dst, $src}",
1091 int_x86_sse2_sqrt_pd>;
1093 def RSQRTPSr : PS_Intr<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1094 int_x86_sse_rsqrt_ps>;
1095 def RSQRTPSm : PS_Intm<0x52, "rsqrtps {$src, $dst|$dst, $src}",
1096 int_x86_sse_rsqrt_ps>;
1097 def RCPPSr : PS_Intr<0x53, "rcpps {$src, $dst|$dst, $src}",
1098 int_x86_sse_rcp_ps>;
1099 def RCPPSm : PS_Intm<0x53, "rcpps {$src, $dst|$dst, $src}",
1100 int_x86_sse_rcp_ps>;
1102 let isTwoAddress = 1 in {
1103 def MAXPSrr : PS_Intrr<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1104 int_x86_sse_max_ps>;
1105 def MAXPSrm : PS_Intrm<0x5F, "maxps {$src2, $dst|$dst, $src2}",
1106 int_x86_sse_max_ps>;
1107 def MAXPDrr : PD_Intrr<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1108 int_x86_sse2_max_pd>;
1109 def MAXPDrm : PD_Intrm<0x5F, "maxpd {$src2, $dst|$dst, $src2}",
1110 int_x86_sse2_max_pd>;
1111 def MINPSrr : PS_Intrr<0x5D, "minps {$src2, $dst|$dst, $src2}",
1112 int_x86_sse_min_ps>;
1113 def MINPSrm : PS_Intrm<0x5D, "minps {$src2, $dst|$dst, $src2}",
1114 int_x86_sse_min_ps>;
1115 def MINPDrr : PD_Intrr<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1116 int_x86_sse2_min_pd>;
1117 def MINPDrm : PD_Intrm<0x5D, "minpd {$src2, $dst|$dst, $src2}",
1118 int_x86_sse2_min_pd>;
1122 let isTwoAddress = 1 in {
1123 let isCommutable = 1 in {
1124 def ANDPSrr : PSI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1125 "andps {$src2, $dst|$dst, $src2}",
1126 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1127 def ANDPDrr : PDI<0x54, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1128 "andpd {$src2, $dst|$dst, $src2}",
1130 (and (bc_v2i64 (v2f64 VR128:$src1)),
1131 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1132 def ORPSrr : PSI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1133 "orps {$src2, $dst|$dst, $src2}",
1134 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1135 def ORPDrr : PDI<0x56, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1136 "orpd {$src2, $dst|$dst, $src2}",
1138 (or (bc_v2i64 (v2f64 VR128:$src1)),
1139 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1140 def XORPSrr : PSI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1141 "xorps {$src2, $dst|$dst, $src2}",
1142 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1143 def XORPDrr : PDI<0x57, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1144 "xorpd {$src2, $dst|$dst, $src2}",
1146 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1147 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1149 def ANDPSrm : PSI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1150 "andps {$src2, $dst|$dst, $src2}",
1151 [(set VR128:$dst, (and VR128:$src1,
1152 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1153 def ANDPDrm : PDI<0x54, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1154 "andpd {$src2, $dst|$dst, $src2}",
1156 (and (bc_v2i64 (v2f64 VR128:$src1)),
1157 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1158 def ORPSrm : PSI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1159 "orps {$src2, $dst|$dst, $src2}",
1160 [(set VR128:$dst, (or VR128:$src1,
1161 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1162 def ORPDrm : PDI<0x56, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1163 "orpd {$src2, $dst|$dst, $src2}",
1165 (or (bc_v2i64 (v2f64 VR128:$src1)),
1166 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1167 def XORPSrm : PSI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1168 "xorps {$src2, $dst|$dst, $src2}",
1169 [(set VR128:$dst, (xor VR128:$src1,
1170 (bc_v2i64 (loadv4f32 addr:$src2))))]>;
1171 def XORPDrm : PDI<0x57, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1172 "xorpd {$src2, $dst|$dst, $src2}",
1174 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1175 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1176 def ANDNPSrr : PSI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1177 "andnps {$src2, $dst|$dst, $src2}",
1178 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1179 (bc_v2i64 (v4i32 immAllOnesV))),
1181 def ANDNPSrm : PSI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1182 "andnps {$src2, $dst|$dst, $src2}",
1183 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1184 (bc_v2i64 (v4i32 immAllOnesV))),
1185 (bc_v2i64 (loadv4f32 addr:$src2)))))]>;
1186 def ANDNPDrr : PDI<0x55, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1187 "andnpd {$src2, $dst|$dst, $src2}",
1189 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1190 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1191 def ANDNPDrm : PDI<0x55, MRMSrcMem, (ops VR128:$dst, VR128:$src1,f128mem:$src2),
1192 "andnpd {$src2, $dst|$dst, $src2}",
1194 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1195 (bc_v2i64 (loadv2f64 addr:$src2))))]>;
1198 let isTwoAddress = 1 in {
1199 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1200 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1201 "cmp${cc}ps {$src, $dst|$dst, $src}",
1202 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1203 VR128:$src, imm:$cc))]>;
1204 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1205 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1206 "cmp${cc}ps {$src, $dst|$dst, $src}",
1207 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1208 (load addr:$src), imm:$cc))]>;
1209 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1210 (ops VR128:$dst, VR128:$src1, VR128:$src, SSECC:$cc),
1211 "cmp${cc}pd {$src, $dst|$dst, $src}",
1212 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1213 VR128:$src, imm:$cc))]>;
1214 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1215 (ops VR128:$dst, VR128:$src1, f128mem:$src, SSECC:$cc),
1216 "cmp${cc}pd {$src, $dst|$dst, $src}",
1217 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1218 (load addr:$src), imm:$cc))]>;
1221 // Shuffle and unpack instructions
1222 let isTwoAddress = 1 in {
1223 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1224 (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
1225 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1226 [(set VR128:$dst, (v4f32 (vector_shuffle
1227 VR128:$src1, VR128:$src2,
1228 SHUFP_shuffle_mask:$src3)))]>;
1229 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1230 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i32i8imm:$src3),
1231 "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
1232 [(set VR128:$dst, (v4f32 (vector_shuffle
1233 VR128:$src1, (load addr:$src2),
1234 SHUFP_shuffle_mask:$src3)))]>;
1235 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1236 (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
1237 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1238 [(set VR128:$dst, (v2f64 (vector_shuffle
1239 VR128:$src1, VR128:$src2,
1240 SHUFP_shuffle_mask:$src3)))]>;
1241 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1242 (ops VR128:$dst, VR128:$src1, f128mem:$src2, i8imm:$src3),
1243 "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",
1244 [(set VR128:$dst, (v2f64 (vector_shuffle
1245 VR128:$src1, (load addr:$src2),
1246 SHUFP_shuffle_mask:$src3)))]>;
1248 let AddedComplexity = 10 in {
1249 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1250 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1251 "unpckhps {$src2, $dst|$dst, $src2}",
1252 [(set VR128:$dst, (v4f32 (vector_shuffle
1253 VR128:$src1, VR128:$src2,
1254 UNPCKH_shuffle_mask)))]>;
1255 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1256 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1257 "unpckhps {$src2, $dst|$dst, $src2}",
1258 [(set VR128:$dst, (v4f32 (vector_shuffle
1259 VR128:$src1, (load addr:$src2),
1260 UNPCKH_shuffle_mask)))]>;
1261 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1262 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1263 "unpckhpd {$src2, $dst|$dst, $src2}",
1264 [(set VR128:$dst, (v2f64 (vector_shuffle
1265 VR128:$src1, VR128:$src2,
1266 UNPCKH_shuffle_mask)))]>;
1267 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1268 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1269 "unpckhpd {$src2, $dst|$dst, $src2}",
1270 [(set VR128:$dst, (v2f64 (vector_shuffle
1271 VR128:$src1, (load addr:$src2),
1272 UNPCKH_shuffle_mask)))]>;
1274 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1275 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1276 "unpcklps {$src2, $dst|$dst, $src2}",
1277 [(set VR128:$dst, (v4f32 (vector_shuffle
1278 VR128:$src1, VR128:$src2,
1279 UNPCKL_shuffle_mask)))]>;
1280 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1281 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1282 "unpcklps {$src2, $dst|$dst, $src2}",
1283 [(set VR128:$dst, (v4f32 (vector_shuffle
1284 VR128:$src1, (load addr:$src2),
1285 UNPCKL_shuffle_mask)))]>;
1286 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1287 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1288 "unpcklpd {$src2, $dst|$dst, $src2}",
1289 [(set VR128:$dst, (v2f64 (vector_shuffle
1290 VR128:$src1, VR128:$src2,
1291 UNPCKL_shuffle_mask)))]>;
1292 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1293 (ops VR128:$dst, VR128:$src1, f128mem:$src2),
1294 "unpcklpd {$src2, $dst|$dst, $src2}",
1295 [(set VR128:$dst, (v2f64 (vector_shuffle
1296 VR128:$src1, (load addr:$src2),
1297 UNPCKL_shuffle_mask)))]>;
1298 } // AddedComplexity
1302 let isTwoAddress = 1 in {
1303 def HADDPSrr : S3D_Intrr<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1304 int_x86_sse3_hadd_ps>;
1305 def HADDPSrm : S3D_Intrm<0x7C, "haddps {$src2, $dst|$dst, $src2}",
1306 int_x86_sse3_hadd_ps>;
1307 def HADDPDrr : S3_Intrr<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1308 int_x86_sse3_hadd_pd>;
1309 def HADDPDrm : S3_Intrm<0x7C, "haddpd {$src2, $dst|$dst, $src2}",
1310 int_x86_sse3_hadd_pd>;
1311 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1312 int_x86_sse3_hsub_ps>;
1313 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps {$src2, $dst|$dst, $src2}",
1314 int_x86_sse3_hsub_ps>;
1315 def HSUBPDrr : S3_Intrr<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1316 int_x86_sse3_hsub_pd>;
1317 def HSUBPDrm : S3_Intrm<0x7D, "hsubpd {$src2, $dst|$dst, $src2}",
1318 int_x86_sse3_hsub_pd>;
1321 //===----------------------------------------------------------------------===//
1322 // SSE integer instructions
1323 //===----------------------------------------------------------------------===//
1325 // Move Instructions
1326 def MOVDQArr : PDI<0x6F, MRMSrcReg, (ops VR128:$dst, VR128:$src),
1327 "movdqa {$src, $dst|$dst, $src}", []>;
1328 def MOVDQArm : PDI<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1329 "movdqa {$src, $dst|$dst, $src}",
1330 [(set VR128:$dst, (loadv2i64 addr:$src))]>;
1331 def MOVDQAmr : PDI<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1332 "movdqa {$src, $dst|$dst, $src}",
1333 [(store (v2i64 VR128:$src), addr:$dst)]>;
1334 def MOVDQUrm : I<0x6F, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1335 "movdqu {$src, $dst|$dst, $src}",
1336 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1337 XS, Requires<[HasSSE2]>;
1338 def MOVDQUmr : I<0x7F, MRMDestMem, (ops i128mem:$dst, VR128:$src),
1339 "movdqu {$src, $dst|$dst, $src}",
1340 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1341 XS, Requires<[HasSSE2]>;
1342 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (ops VR128:$dst, i128mem:$src),
1343 "lddqu {$src, $dst|$dst, $src}",
1344 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
1346 // 128-bit Integer Arithmetic
1347 let isTwoAddress = 1 in {
1348 let isCommutable = 1 in {
1349 def PADDBrr : PDI<0xFC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1350 "paddb {$src2, $dst|$dst, $src2}",
1351 [(set VR128:$dst, (v16i8 (add VR128:$src1, VR128:$src2)))]>;
1352 def PADDWrr : PDI<0xFD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1353 "paddw {$src2, $dst|$dst, $src2}",
1354 [(set VR128:$dst, (v8i16 (add VR128:$src1, VR128:$src2)))]>;
1355 def PADDDrr : PDI<0xFE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1356 "paddd {$src2, $dst|$dst, $src2}",
1357 [(set VR128:$dst, (v4i32 (add VR128:$src1, VR128:$src2)))]>;
1359 def PADDQrr : PDI<0xD4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1360 "paddq {$src2, $dst|$dst, $src2}",
1361 [(set VR128:$dst, (v2i64 (add VR128:$src1, VR128:$src2)))]>;
1363 def PADDBrm : PDI<0xFC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1364 "paddb {$src2, $dst|$dst, $src2}",
1365 [(set VR128:$dst, (add VR128:$src1,
1366 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1367 def PADDWrm : PDI<0xFD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1368 "paddw {$src2, $dst|$dst, $src2}",
1369 [(set VR128:$dst, (add VR128:$src1,
1370 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1371 def PADDDrm : PDI<0xFE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1372 "paddd {$src2, $dst|$dst, $src2}",
1373 [(set VR128:$dst, (add VR128:$src1,
1374 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1375 def PADDQrm : PDI<0xD4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1376 "paddd {$src2, $dst|$dst, $src2}",
1377 [(set VR128:$dst, (add VR128:$src1,
1378 (loadv2i64 addr:$src2)))]>;
1380 let isCommutable = 1 in {
1381 def PADDSBrr : PDI<0xEC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1382 "paddsb {$src2, $dst|$dst, $src2}",
1383 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1385 def PADDSWrr : PDI<0xED, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1386 "paddsw {$src2, $dst|$dst, $src2}",
1387 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1389 def PADDUSBrr : PDI<0xDC, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1390 "paddusb {$src2, $dst|$dst, $src2}",
1391 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1393 def PADDUSWrr : PDI<0xDD, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1394 "paddusw {$src2, $dst|$dst, $src2}",
1395 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1398 def PADDSBrm : PDI<0xEC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1399 "paddsb {$src2, $dst|$dst, $src2}",
1400 [(set VR128:$dst, (int_x86_sse2_padds_b VR128:$src1,
1401 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1402 def PADDSWrm : PDI<0xED, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1403 "paddsw {$src2, $dst|$dst, $src2}",
1404 [(set VR128:$dst, (int_x86_sse2_padds_w VR128:$src1,
1405 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1406 def PADDUSBrm : PDI<0xDC, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1407 "paddusb {$src2, $dst|$dst, $src2}",
1408 [(set VR128:$dst, (int_x86_sse2_paddus_b VR128:$src1,
1409 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1410 def PADDUSWrm : PDI<0xDD, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1411 "paddusw {$src2, $dst|$dst, $src2}",
1412 [(set VR128:$dst, (int_x86_sse2_paddus_w VR128:$src1,
1413 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1416 def PSUBBrr : PDI<0xF8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1417 "psubb {$src2, $dst|$dst, $src2}",
1418 [(set VR128:$dst, (v16i8 (sub VR128:$src1, VR128:$src2)))]>;
1419 def PSUBWrr : PDI<0xF9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1420 "psubw {$src2, $dst|$dst, $src2}",
1421 [(set VR128:$dst, (v8i16 (sub VR128:$src1, VR128:$src2)))]>;
1422 def PSUBDrr : PDI<0xFA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1423 "psubd {$src2, $dst|$dst, $src2}",
1424 [(set VR128:$dst, (v4i32 (sub VR128:$src1, VR128:$src2)))]>;
1425 def PSUBQrr : PDI<0xFB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1426 "psubq {$src2, $dst|$dst, $src2}",
1427 [(set VR128:$dst, (v2i64 (sub VR128:$src1, VR128:$src2)))]>;
1429 def PSUBBrm : PDI<0xF8, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1430 "psubb {$src2, $dst|$dst, $src2}",
1431 [(set VR128:$dst, (sub VR128:$src1,
1432 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1433 def PSUBWrm : PDI<0xF9, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1434 "psubw {$src2, $dst|$dst, $src2}",
1435 [(set VR128:$dst, (sub VR128:$src1,
1436 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1437 def PSUBDrm : PDI<0xFA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1438 "psubd {$src2, $dst|$dst, $src2}",
1439 [(set VR128:$dst, (sub VR128:$src1,
1440 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1441 def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1442 "psubd {$src2, $dst|$dst, $src2}",
1443 [(set VR128:$dst, (sub VR128:$src1,
1444 (loadv2i64 addr:$src2)))]>;
1446 def PSUBSBrr : PDI<0xE8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1447 "psubsb {$src2, $dst|$dst, $src2}",
1448 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1450 def PSUBSWrr : PDI<0xE9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1451 "psubsw {$src2, $dst|$dst, $src2}",
1452 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1454 def PSUBUSBrr : PDI<0xD8, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1455 "psubusb {$src2, $dst|$dst, $src2}",
1456 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1458 def PSUBUSWrr : PDI<0xD9, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1459 "psubusw {$src2, $dst|$dst, $src2}",
1460 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1463 def PSUBSBrm : PDI<0xE8, MRMSrcMem,
1464 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1465 "psubsb {$src2, $dst|$dst, $src2}",
1466 [(set VR128:$dst, (int_x86_sse2_psubs_b VR128:$src1,
1467 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1468 def PSUBSWrm : PDI<0xE9, MRMSrcMem,
1469 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1470 "psubsw {$src2, $dst|$dst, $src2}",
1471 [(set VR128:$dst, (int_x86_sse2_psubs_w VR128:$src1,
1472 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1473 def PSUBUSBrm : PDI<0xD8, MRMSrcMem,
1474 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1475 "psubusb {$src2, $dst|$dst, $src2}",
1476 [(set VR128:$dst, (int_x86_sse2_psubus_b VR128:$src1,
1477 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1478 def PSUBUSWrm : PDI<0xD9, MRMSrcMem,
1479 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1480 "psubusw {$src2, $dst|$dst, $src2}",
1481 [(set VR128:$dst, (int_x86_sse2_psubus_w VR128:$src1,
1482 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1484 let isCommutable = 1 in {
1485 def PMULHUWrr : PDI<0xE4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1486 "pmulhuw {$src2, $dst|$dst, $src2}",
1487 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1489 def PMULHWrr : PDI<0xE5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1490 "pmulhw {$src2, $dst|$dst, $src2}",
1491 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1493 def PMULLWrr : PDI<0xD5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1494 "pmullw {$src2, $dst|$dst, $src2}",
1495 [(set VR128:$dst, (v8i16 (mul VR128:$src1, VR128:$src2)))]>;
1496 def PMULUDQrr : PDI<0xF4, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1497 "pmuludq {$src2, $dst|$dst, $src2}",
1498 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1501 def PMULHUWrm : PDI<0xE4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1502 "pmulhuw {$src2, $dst|$dst, $src2}",
1503 [(set VR128:$dst, (int_x86_sse2_pmulhu_w VR128:$src1,
1504 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1505 def PMULHWrm : PDI<0xE5, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1506 "pmulhw {$src2, $dst|$dst, $src2}",
1507 [(set VR128:$dst, (int_x86_sse2_pmulh_w VR128:$src1,
1508 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1509 def PMULLWrm : PDI<0xD5, MRMSrcMem,
1510 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1511 "pmullw {$src2, $dst|$dst, $src2}",
1512 [(set VR128:$dst, (v8i16 (mul VR128:$src1,
1513 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1514 def PMULUDQrm : PDI<0xF4, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1515 "pmuludq {$src2, $dst|$dst, $src2}",
1516 [(set VR128:$dst, (int_x86_sse2_pmulu_dq VR128:$src1,
1517 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1519 let isCommutable = 1 in {
1520 def PMADDWDrr : PDI<0xF5, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1521 "pmaddwd {$src2, $dst|$dst, $src2}",
1522 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1525 def PMADDWDrm : PDI<0xF5, MRMSrcMem,
1526 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1527 "pmaddwd {$src2, $dst|$dst, $src2}",
1528 [(set VR128:$dst, (int_x86_sse2_pmadd_wd VR128:$src1,
1529 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1531 let isCommutable = 1 in {
1532 def PAVGBrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1533 "pavgb {$src2, $dst|$dst, $src2}",
1534 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1536 def PAVGWrr : PDI<0xE3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1537 "pavgw {$src2, $dst|$dst, $src2}",
1538 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1541 def PAVGBrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1542 "pavgb {$src2, $dst|$dst, $src2}",
1543 [(set VR128:$dst, (int_x86_sse2_pavg_b VR128:$src1,
1544 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1545 def PAVGWrm : PDI<0xE3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1546 "pavgw {$src2, $dst|$dst, $src2}",
1547 [(set VR128:$dst, (int_x86_sse2_pavg_w VR128:$src1,
1548 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1550 let isCommutable = 1 in {
1551 def PMAXUBrr : PDI<0xDE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1552 "pmaxub {$src2, $dst|$dst, $src2}",
1553 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1555 def PMAXSWrr : PDI<0xEE, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1556 "pmaxsw {$src2, $dst|$dst, $src2}",
1557 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1560 def PMAXUBrm : PDI<0xDE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1561 "pmaxub {$src2, $dst|$dst, $src2}",
1562 [(set VR128:$dst, (int_x86_sse2_pmaxu_b VR128:$src1,
1563 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1564 def PMAXSWrm : PDI<0xEE, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1565 "pmaxsw {$src2, $dst|$dst, $src2}",
1566 [(set VR128:$dst, (int_x86_sse2_pmaxs_w VR128:$src1,
1567 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1569 let isCommutable = 1 in {
1570 def PMINUBrr : PDI<0xDA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1571 "pminub {$src2, $dst|$dst, $src2}",
1572 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1574 def PMINSWrr : PDI<0xEA, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1575 "pminsw {$src2, $dst|$dst, $src2}",
1576 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1579 def PMINUBrm : PDI<0xDA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1580 "pminub {$src2, $dst|$dst, $src2}",
1581 [(set VR128:$dst, (int_x86_sse2_pminu_b VR128:$src1,
1582 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1583 def PMINSWrm : PDI<0xEA, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1584 "pminsw {$src2, $dst|$dst, $src2}",
1585 [(set VR128:$dst, (int_x86_sse2_pmins_w VR128:$src1,
1586 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1589 let isCommutable = 1 in {
1590 def PSADBWrr : PDI<0xE0, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1591 "psadbw {$src2, $dst|$dst, $src2}",
1592 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1595 def PSADBWrm : PDI<0xE0, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1596 "psadbw {$src2, $dst|$dst, $src2}",
1597 [(set VR128:$dst, (int_x86_sse2_psad_bw VR128:$src1,
1598 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1601 let isTwoAddress = 1 in {
1602 def PSLLWrr : PDIi8<0xF1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1603 "psllw {$src2, $dst|$dst, $src2}",
1604 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1606 def PSLLWrm : PDIi8<0xF1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1607 "psllw {$src2, $dst|$dst, $src2}",
1608 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1609 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1610 def PSLLWri : PDIi8<0x71, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1611 "psllw {$src2, $dst|$dst, $src2}",
1612 [(set VR128:$dst, (int_x86_sse2_psll_w VR128:$src1,
1613 (scalar_to_vector (i32 imm:$src2))))]>;
1614 def PSLLDrr : PDIi8<0xF2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1615 "pslld {$src2, $dst|$dst, $src2}",
1616 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1618 def PSLLDrm : PDIi8<0xF2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1619 "pslld {$src2, $dst|$dst, $src2}",
1620 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1621 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1622 def PSLLDri : PDIi8<0x72, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1623 "pslld {$src2, $dst|$dst, $src2}",
1624 [(set VR128:$dst, (int_x86_sse2_psll_d VR128:$src1,
1625 (scalar_to_vector (i32 imm:$src2))))]>;
1626 def PSLLQrr : PDIi8<0xF3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1627 "psllq {$src2, $dst|$dst, $src2}",
1628 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1630 def PSLLQrm : PDIi8<0xF3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1631 "psllq {$src2, $dst|$dst, $src2}",
1632 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1633 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1634 def PSLLQri : PDIi8<0x73, MRM6r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1635 "psllq {$src2, $dst|$dst, $src2}",
1636 [(set VR128:$dst, (int_x86_sse2_psll_q VR128:$src1,
1637 (scalar_to_vector (i32 imm:$src2))))]>;
1638 def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1639 "pslldq {$src2, $dst|$dst, $src2}", []>;
1641 def PSRLWrr : PDIi8<0xD1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1642 "psrlw {$src2, $dst|$dst, $src2}",
1643 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1645 def PSRLWrm : PDIi8<0xD1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1646 "psrlw {$src2, $dst|$dst, $src2}",
1647 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1648 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1649 def PSRLWri : PDIi8<0x71, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1650 "psrlw {$src2, $dst|$dst, $src2}",
1651 [(set VR128:$dst, (int_x86_sse2_psrl_w VR128:$src1,
1652 (scalar_to_vector (i32 imm:$src2))))]>;
1653 def PSRLDrr : PDIi8<0xD2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1654 "psrld {$src2, $dst|$dst, $src2}",
1655 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1657 def PSRLDrm : PDIi8<0xD2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1658 "psrld {$src2, $dst|$dst, $src2}",
1659 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1660 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1661 def PSRLDri : PDIi8<0x72, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1662 "psrld {$src2, $dst|$dst, $src2}",
1663 [(set VR128:$dst, (int_x86_sse2_psrl_d VR128:$src1,
1664 (scalar_to_vector (i32 imm:$src2))))]>;
1665 def PSRLQrr : PDIi8<0xD3, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1666 "psrlq {$src2, $dst|$dst, $src2}",
1667 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1669 def PSRLQrm : PDIi8<0xD3, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1670 "psrlq {$src2, $dst|$dst, $src2}",
1671 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1672 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1673 def PSRLQri : PDIi8<0x73, MRM2r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1674 "psrlq {$src2, $dst|$dst, $src2}",
1675 [(set VR128:$dst, (int_x86_sse2_psrl_q VR128:$src1,
1676 (scalar_to_vector (i32 imm:$src2))))]>;
1677 def PSRLDQri : PDIi8<0x73, MRM3r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1678 "psrldq {$src2, $dst|$dst, $src2}", []>;
1680 def PSRAWrr : PDIi8<0xE1, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1681 "psraw {$src2, $dst|$dst, $src2}",
1682 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1684 def PSRAWrm : PDIi8<0xE1, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1685 "psraw {$src2, $dst|$dst, $src2}",
1686 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1687 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1688 def PSRAWri : PDIi8<0x71, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1689 "psraw {$src2, $dst|$dst, $src2}",
1690 [(set VR128:$dst, (int_x86_sse2_psra_w VR128:$src1,
1691 (scalar_to_vector (i32 imm:$src2))))]>;
1692 def PSRADrr : PDIi8<0xE2, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1693 "psrad {$src2, $dst|$dst, $src2}",
1694 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1696 def PSRADrm : PDIi8<0xE2, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1697 "psrad {$src2, $dst|$dst, $src2}",
1698 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1699 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1700 def PSRADri : PDIi8<0x72, MRM4r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1701 "psrad {$src2, $dst|$dst, $src2}",
1702 [(set VR128:$dst, (int_x86_sse2_psra_d VR128:$src1,
1703 (scalar_to_vector (i32 imm:$src2))))]>;
1707 let isTwoAddress = 1 in {
1708 let isCommutable = 1 in {
1709 def PANDrr : PDI<0xDB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1710 "pand {$src2, $dst|$dst, $src2}",
1711 [(set VR128:$dst, (v2i64 (and VR128:$src1, VR128:$src2)))]>;
1712 def PORrr : PDI<0xEB, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1713 "por {$src2, $dst|$dst, $src2}",
1714 [(set VR128:$dst, (v2i64 (or VR128:$src1, VR128:$src2)))]>;
1715 def PXORrr : PDI<0xEF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1716 "pxor {$src2, $dst|$dst, $src2}",
1717 [(set VR128:$dst, (v2i64 (xor VR128:$src1, VR128:$src2)))]>;
1720 def PANDrm : PDI<0xDB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1721 "pand {$src2, $dst|$dst, $src2}",
1722 [(set VR128:$dst, (v2i64 (and VR128:$src1,
1723 (load addr:$src2))))]>;
1724 def PORrm : PDI<0xEB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1725 "por {$src2, $dst|$dst, $src2}",
1726 [(set VR128:$dst, (v2i64 (or VR128:$src1,
1727 (load addr:$src2))))]>;
1728 def PXORrm : PDI<0xEF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1729 "pxor {$src2, $dst|$dst, $src2}",
1730 [(set VR128:$dst, (v2i64 (xor VR128:$src1,
1731 (load addr:$src2))))]>;
1733 def PANDNrr : PDI<0xDF, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
1734 "pandn {$src2, $dst|$dst, $src2}",
1735 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1738 def PANDNrm : PDI<0xDF, MRMSrcMem, (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1739 "pandn {$src2, $dst|$dst, $src2}",
1740 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1741 (load addr:$src2))))]>;
1744 // SSE2 Integer comparison
1745 let isTwoAddress = 1 in {
1746 def PCMPEQBrr : PDI<0x74, MRMSrcReg,
1747 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1748 "pcmpeqb {$src2, $dst|$dst, $src2}",
1749 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1751 def PCMPEQBrm : PDI<0x74, MRMSrcMem,
1752 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1753 "pcmpeqb {$src2, $dst|$dst, $src2}",
1754 [(set VR128:$dst, (int_x86_sse2_pcmpeq_b VR128:$src1,
1755 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1756 def PCMPEQWrr : PDI<0x75, MRMSrcReg,
1757 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1758 "pcmpeqw {$src2, $dst|$dst, $src2}",
1759 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1761 def PCMPEQWrm : PDI<0x75, MRMSrcMem,
1762 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1763 "pcmpeqw {$src2, $dst|$dst, $src2}",
1764 [(set VR128:$dst, (int_x86_sse2_pcmpeq_w VR128:$src1,
1765 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1766 def PCMPEQDrr : PDI<0x76, MRMSrcReg,
1767 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1768 "pcmpeqd {$src2, $dst|$dst, $src2}",
1769 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1771 def PCMPEQDrm : PDI<0x76, MRMSrcMem,
1772 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1773 "pcmpeqd {$src2, $dst|$dst, $src2}",
1774 [(set VR128:$dst, (int_x86_sse2_pcmpeq_d VR128:$src1,
1775 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1777 def PCMPGTBrr : PDI<0x64, MRMSrcReg,
1778 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1779 "pcmpgtb {$src2, $dst|$dst, $src2}",
1780 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1782 def PCMPGTBrm : PDI<0x64, MRMSrcMem,
1783 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1784 "pcmpgtb {$src2, $dst|$dst, $src2}",
1785 [(set VR128:$dst, (int_x86_sse2_pcmpgt_b VR128:$src1,
1786 (bc_v16i8 (loadv2i64 addr:$src2))))]>;
1787 def PCMPGTWrr : PDI<0x65, MRMSrcReg,
1788 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1789 "pcmpgtw {$src2, $dst|$dst, $src2}",
1790 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1792 def PCMPGTWrm : PDI<0x65, MRMSrcMem,
1793 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1794 "pcmpgtw {$src2, $dst|$dst, $src2}",
1795 [(set VR128:$dst, (int_x86_sse2_pcmpgt_w VR128:$src1,
1796 (bc_v8i16 (loadv2i64 addr:$src2))))]>;
1797 def PCMPGTDrr : PDI<0x66, MRMSrcReg,
1798 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1799 "pcmpgtd {$src2, $dst|$dst, $src2}",
1800 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1802 def PCMPGTDrm : PDI<0x66, MRMSrcMem,
1803 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1804 "pcmpgtd {$src2, $dst|$dst, $src2}",
1805 [(set VR128:$dst, (int_x86_sse2_pcmpgt_d VR128:$src1,
1806 (bc_v4i32 (loadv2i64 addr:$src2))))]>;
1809 // Pack instructions
1810 let isTwoAddress = 1 in {
1811 def PACKSSWBrr : PDI<0x63, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1813 "packsswb {$src2, $dst|$dst, $src2}",
1814 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1817 def PACKSSWBrm : PDI<0x63, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1819 "packsswb {$src2, $dst|$dst, $src2}",
1820 [(set VR128:$dst, (v8i16 (int_x86_sse2_packsswb_128
1822 (bc_v8i16 (loadv2f64 addr:$src2)))))]>;
1823 def PACKSSDWrr : PDI<0x6B, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1825 "packssdw {$src2, $dst|$dst, $src2}",
1826 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1829 def PACKSSDWrm : PDI<0x6B, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1831 "packssdw {$src2, $dst|$dst, $src2}",
1832 [(set VR128:$dst, (v4i32 (int_x86_sse2_packssdw_128
1834 (bc_v4i32 (loadv2i64 addr:$src2)))))]>;
1835 def PACKUSWBrr : PDI<0x67, MRMSrcReg, (ops VR128:$dst, VR128:$src1,
1837 "packuswb {$src2, $dst|$dst, $src2}",
1838 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1841 def PACKUSWBrm : PDI<0x67, MRMSrcMem, (ops VR128:$dst, VR128:$src1,
1843 "packuswb {$src2, $dst|$dst, $src2}",
1844 [(set VR128:$dst, (v8i16 (int_x86_sse2_packuswb_128
1846 (bc_v8i16 (loadv2i64 addr:$src2)))))]>;
1849 // Shuffle and unpack instructions
1850 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1851 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1852 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1853 [(set VR128:$dst, (v4i32 (vector_shuffle
1854 VR128:$src1, (undef),
1855 PSHUFD_shuffle_mask:$src2)))]>;
1856 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1857 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1858 "pshufd {$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (v4i32 (vector_shuffle
1860 (bc_v4i32 (loadv2i64 addr:$src1)),
1862 PSHUFD_shuffle_mask:$src2)))]>;
1864 // SSE2 with ImmT == Imm8 and XS prefix.
1865 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1866 (ops VR128:$dst, VR128:$src1, i8imm:$src2),
1867 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1868 [(set VR128:$dst, (v8i16 (vector_shuffle
1869 VR128:$src1, (undef),
1870 PSHUFHW_shuffle_mask:$src2)))]>,
1871 XS, Requires<[HasSSE2]>;
1872 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1873 (ops VR128:$dst, i128mem:$src1, i8imm:$src2),
1874 "pshufhw {$src2, $src1, $dst|$dst, $src1, $src2}",
1875 [(set VR128:$dst, (v8i16 (vector_shuffle
1876 (bc_v8i16 (loadv2i64 addr:$src1)),
1878 PSHUFHW_shuffle_mask:$src2)))]>,
1879 XS, Requires<[HasSSE2]>;
1881 // SSE2 with ImmT == Imm8 and XD prefix.
1882 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1883 (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
1884 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1885 [(set VR128:$dst, (v8i16 (vector_shuffle
1886 VR128:$src1, (undef),
1887 PSHUFLW_shuffle_mask:$src2)))]>,
1888 XD, Requires<[HasSSE2]>;
1889 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1890 (ops VR128:$dst, i128mem:$src1, i32i8imm:$src2),
1891 "pshuflw {$src2, $src1, $dst|$dst, $src1, $src2}",
1892 [(set VR128:$dst, (v8i16 (vector_shuffle
1893 (bc_v8i16 (loadv2i64 addr:$src1)),
1895 PSHUFLW_shuffle_mask:$src2)))]>,
1896 XD, Requires<[HasSSE2]>;
1898 let isTwoAddress = 1 in {
1899 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1900 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1901 "punpcklbw {$src2, $dst|$dst, $src2}",
1903 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1904 UNPCKL_shuffle_mask)))]>;
1905 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1906 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1907 "punpcklbw {$src2, $dst|$dst, $src2}",
1909 (v16i8 (vector_shuffle VR128:$src1,
1910 (bc_v16i8 (loadv2i64 addr:$src2)),
1911 UNPCKL_shuffle_mask)))]>;
1912 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1913 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1914 "punpcklwd {$src2, $dst|$dst, $src2}",
1916 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1917 UNPCKL_shuffle_mask)))]>;
1918 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1919 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1920 "punpcklwd {$src2, $dst|$dst, $src2}",
1922 (v8i16 (vector_shuffle VR128:$src1,
1923 (bc_v8i16 (loadv2i64 addr:$src2)),
1924 UNPCKL_shuffle_mask)))]>;
1925 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
1926 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1927 "punpckldq {$src2, $dst|$dst, $src2}",
1929 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1930 UNPCKL_shuffle_mask)))]>;
1931 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
1932 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1933 "punpckldq {$src2, $dst|$dst, $src2}",
1935 (v4i32 (vector_shuffle VR128:$src1,
1936 (bc_v4i32 (loadv2i64 addr:$src2)),
1937 UNPCKL_shuffle_mask)))]>;
1938 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
1939 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1940 "punpcklqdq {$src2, $dst|$dst, $src2}",
1942 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1943 UNPCKL_shuffle_mask)))]>;
1944 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
1945 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1946 "punpcklqdq {$src2, $dst|$dst, $src2}",
1948 (v2i64 (vector_shuffle VR128:$src1,
1949 (loadv2i64 addr:$src2),
1950 UNPCKL_shuffle_mask)))]>;
1952 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
1953 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1954 "punpckhbw {$src2, $dst|$dst, $src2}",
1956 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1957 UNPCKH_shuffle_mask)))]>;
1958 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
1959 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1960 "punpckhbw {$src2, $dst|$dst, $src2}",
1962 (v16i8 (vector_shuffle VR128:$src1,
1963 (bc_v16i8 (loadv2i64 addr:$src2)),
1964 UNPCKH_shuffle_mask)))]>;
1965 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
1966 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1967 "punpckhwd {$src2, $dst|$dst, $src2}",
1969 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1970 UNPCKH_shuffle_mask)))]>;
1971 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
1972 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1973 "punpckhwd {$src2, $dst|$dst, $src2}",
1975 (v8i16 (vector_shuffle VR128:$src1,
1976 (bc_v8i16 (loadv2i64 addr:$src2)),
1977 UNPCKH_shuffle_mask)))]>;
1978 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
1979 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1980 "punpckhdq {$src2, $dst|$dst, $src2}",
1982 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
1983 UNPCKH_shuffle_mask)))]>;
1984 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
1985 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1986 "punpckhdq {$src2, $dst|$dst, $src2}",
1988 (v4i32 (vector_shuffle VR128:$src1,
1989 (bc_v4i32 (loadv2i64 addr:$src2)),
1990 UNPCKH_shuffle_mask)))]>;
1991 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
1992 (ops VR128:$dst, VR128:$src1, VR128:$src2),
1993 "punpckhdq {$src2, $dst|$dst, $src2}",
1995 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
1996 UNPCKH_shuffle_mask)))]>;
1997 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
1998 (ops VR128:$dst, VR128:$src1, i128mem:$src2),
1999 "punpckhqdq {$src2, $dst|$dst, $src2}",
2001 (v2i64 (vector_shuffle VR128:$src1,
2002 (loadv2i64 addr:$src2),
2003 UNPCKH_shuffle_mask)))]>;
2007 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2008 (ops R32:$dst, VR128:$src1, i32i8imm:$src2),
2009 "pextrw {$src2, $src1, $dst|$dst, $src1, $src2}",
2010 [(set R32:$dst, (X86pextrw (v8i16 VR128:$src1),
2011 (i32 imm:$src2)))]>;
2012 let isTwoAddress = 1 in {
2013 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2014 (ops VR128:$dst, VR128:$src1, R32:$src2, i32i8imm:$src3),
2015 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2016 [(set VR128:$dst, (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2017 R32:$src2, (i32 imm:$src3))))]>;
2018 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2019 (ops VR128:$dst, VR128:$src1, i16mem:$src2, i32i8imm:$src3),
2020 "pinsrw {$src3, $src2, $dst|$dst, $src2, $src3}",
2022 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2023 (i32 (anyext (loadi16 addr:$src2))),
2024 (i32 imm:$src3))))]>;
2027 //===----------------------------------------------------------------------===//
2028 // Miscellaneous Instructions
2029 //===----------------------------------------------------------------------===//
2032 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2033 "movmskps {$src, $dst|$dst, $src}",
2034 [(set R32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
2035 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (ops R32:$dst, VR128:$src),
2036 "movmskpd {$src, $dst|$dst, $src}",
2037 [(set R32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
2039 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (ops R32:$dst, VR128:$src),
2040 "pmovmskb {$src, $dst|$dst, $src}",
2041 [(set R32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2043 // Conditional store
2044 def MASKMOVDQU : PDI<0xF7, RawFrm, (ops VR128:$src, VR128:$mask),
2045 "maskmovdqu {$mask, $src|$src, $mask}",
2046 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>,
2049 // Prefetching loads
2050 def PREFETCHT0 : PSI<0x18, MRM1m, (ops i8mem:$src),
2051 "prefetcht0 $src", []>;
2052 def PREFETCHT1 : PSI<0x18, MRM2m, (ops i8mem:$src),
2053 "prefetcht1 $src", []>;
2054 def PREFETCHT2 : PSI<0x18, MRM3m, (ops i8mem:$src),
2055 "prefetcht2 $src", []>;
2056 def PREFETCHTNTA : PSI<0x18, MRM0m, (ops i8mem:$src),
2057 "prefetchtnta $src", []>;
2059 // Non-temporal stores
2060 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2061 "movntps {$src, $dst|$dst, $src}",
2062 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
2063 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (ops i128mem:$dst, VR128:$src),
2064 "movntpd {$src, $dst|$dst, $src}",
2065 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2066 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (ops f128mem:$dst, VR128:$src),
2067 "movntdq {$src, $dst|$dst, $src}",
2068 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2069 def MOVNTImr : I<0xC3, MRMDestMem, (ops i32mem:$dst, R32:$src),
2070 "movnti {$src, $dst|$dst, $src}",
2071 [(int_x86_sse2_movnt_i addr:$dst, R32:$src)]>,
2072 TB, Requires<[HasSSE2]>;
2075 def CLFLUSH : I<0xAE, MRM7m, (ops i8mem:$src),
2076 "clflush $src", [(int_x86_sse2_clflush addr:$src)]>,
2077 TB, Requires<[HasSSE2]>;
2079 // Load, store, and memory fence
2080 def SFENCE : I<0xAE, MRM7m, (ops),
2081 "sfence", [(int_x86_sse_sfence)]>, TB, Requires<[HasSSE1]>;
2082 def LFENCE : I<0xAE, MRM5m, (ops),
2083 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2084 def MFENCE : I<0xAE, MRM6m, (ops),
2085 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2088 def LDMXCSR : I<0xAE, MRM5m, (ops i32mem:$src),
2090 [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
2091 def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
2093 [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
2095 // Thread synchronization
2096 def MONITOR : I<0xC8, RawFrm, (ops), "monitor",
2097 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,
2098 TB, Requires<[HasSSE3]>;
2099 def MWAIT : I<0xC9, RawFrm, (ops), "mwait",
2100 [(int_x86_sse3_mwait ECX, EAX)]>,
2101 TB, Requires<[HasSSE3]>;
2103 //===----------------------------------------------------------------------===//
2104 // Alias Instructions
2105 //===----------------------------------------------------------------------===//
2107 // Alias instructions that map zero vector to pxor / xorp* for sse.
2108 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
2109 def V_SET0_PI : PDI<0xEF, MRMInitReg, (ops VR128:$dst),
2111 [(set VR128:$dst, (v2i64 immAllZerosV))]>;
2112 def V_SET0_PS : PSI<0x57, MRMInitReg, (ops VR128:$dst),
2114 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
2115 def V_SET0_PD : PDI<0x57, MRMInitReg, (ops VR128:$dst),
2117 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
2119 def V_SETALLONES : PDI<0x76, MRMInitReg, (ops VR128:$dst),
2120 "pcmpeqd $dst, $dst",
2121 [(set VR128:$dst, (v2f64 immAllOnesV))]>;
2123 // FR32 / FR64 to 128-bit vector conversion.
2124 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, FR32:$src),
2125 "movss {$src, $dst|$dst, $src}",
2127 (v4f32 (scalar_to_vector FR32:$src)))]>;
2128 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2129 "movss {$src, $dst|$dst, $src}",
2131 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
2132 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, FR64:$src),
2133 "movsd {$src, $dst|$dst, $src}",
2135 (v2f64 (scalar_to_vector FR64:$src)))]>;
2136 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2137 "movsd {$src, $dst|$dst, $src}",
2139 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2141 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, R32:$src),
2142 "movd {$src, $dst|$dst, $src}",
2144 (v4i32 (scalar_to_vector R32:$src)))]>;
2145 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2146 "movd {$src, $dst|$dst, $src}",
2148 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2149 // SSE2 instructions with XS prefix
2150 def MOVQI2PQIrr : I<0x7E, MRMSrcReg, (ops VR128:$dst, VR64:$src),
2151 "movq {$src, $dst|$dst, $src}",
2153 (v2i64 (scalar_to_vector VR64:$src)))]>, XS,
2154 Requires<[HasSSE2]>;
2155 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2156 "movq {$src, $dst|$dst, $src}",
2158 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2159 Requires<[HasSSE2]>;
2160 // FIXME: may not be able to eliminate this movss with coalescing the src and
2161 // dest register classes are different. We really want to write this pattern
2163 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (i32 0))),
2164 // (f32 FR32:$src)>;
2165 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (ops FR32:$dst, VR128:$src),
2166 "movss {$src, $dst|$dst, $src}",
2167 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
2169 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (ops f32mem:$dst, VR128:$src),
2170 "movss {$src, $dst|$dst, $src}",
2171 [(store (f32 (vector_extract (v4f32 VR128:$src),
2172 (i32 0))), addr:$dst)]>;
2173 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (ops FR64:$dst, VR128:$src),
2174 "movsd {$src, $dst|$dst, $src}",
2175 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2177 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (ops f64mem:$dst, VR128:$src),
2178 "movsd {$src, $dst|$dst, $src}",
2179 [(store (f64 (vector_extract (v2f64 VR128:$src),
2180 (i32 0))), addr:$dst)]>;
2181 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (ops R32:$dst, VR128:$src),
2182 "movd {$src, $dst|$dst, $src}",
2183 [(set R32:$dst, (vector_extract (v4i32 VR128:$src),
2185 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (ops i32mem:$dst, VR128:$src),
2186 "movd {$src, $dst|$dst, $src}",
2187 [(store (i32 (vector_extract (v4i32 VR128:$src),
2188 (i32 0))), addr:$dst)]>;
2190 // Move to lower bits of a VR128, leaving upper bits alone.
2191 // Three operand (but two address) aliases.
2192 let isTwoAddress = 1 in {
2193 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR32:$src2),
2194 "movss {$src2, $dst|$dst, $src2}", []>;
2195 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, FR64:$src2),
2196 "movsd {$src2, $dst|$dst, $src2}", []>;
2197 def MOVLDI2PDIrr : PDI<0x6E, MRMSrcReg, (ops VR128:$dst, VR128:$src1, R32:$src2),
2198 "movd {$src2, $dst|$dst, $src2}", []>;
2200 let AddedComplexity = 20 in {
2201 def MOVLPSrr : SSI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2202 "movss {$src2, $dst|$dst, $src2}",
2204 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2205 MOVS_shuffle_mask)))]>;
2206 def MOVLPDrr : SDI<0x10, MRMSrcReg, (ops VR128:$dst, VR128:$src1, VR128:$src2),
2207 "movsd {$src2, $dst|$dst, $src2}",
2209 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2210 MOVS_shuffle_mask)))]>;
2214 // Store / copy lower 64-bits of a XMM register.
2215 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (ops i64mem:$dst, VR128:$src),
2216 "movq {$src, $dst|$dst, $src}",
2217 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2219 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2220 def MOVLQ128rr : PDI<0xD6, MRMSrcReg, (ops VR128:$dst, VR128:$src),
2221 "movq {$src, $dst|$dst, $src}",
2222 [(set VR128:$dst, (int_x86_sse2_movl_dq VR128:$src))]>;
2224 // Move to lower bits of a VR128 and zeroing upper bits.
2225 // Loading from memory automatically zeroing upper bits.
2226 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (ops VR128:$dst, f32mem:$src),
2227 "movss {$src, $dst|$dst, $src}",
2229 (v4f32 (X86zexts2vec (loadf32 addr:$src))))]>;
2230 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (ops VR128:$dst, f64mem:$src),
2231 "movsd {$src, $dst|$dst, $src}",
2233 (v2f64 (X86zexts2vec (loadf64 addr:$src))))]>;
2234 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (ops VR128:$dst, i32mem:$src),
2235 "movd {$src, $dst|$dst, $src}",
2237 (v4i32 (X86zexts2vec (loadi32 addr:$src))))]>;
2238 def MOVZQI2PQIrm : PDI<0x7E, MRMSrcMem, (ops VR128:$dst, i64mem:$src),
2239 "movq {$src, $dst|$dst, $src}",
2241 (bc_v2i64 (v2f64 (X86zexts2vec
2242 (loadf64 addr:$src)))))]>;
2244 //===----------------------------------------------------------------------===//
2245 // Non-Instruction Patterns
2246 //===----------------------------------------------------------------------===//
2248 // 128-bit vector undef's.
2249 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2250 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2251 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2252 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2253 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2255 // 128-bit vector all zero's.
2256 def : Pat<(v16i8 immAllZerosV), (v16i8 (V_SET0_PI))>, Requires<[HasSSE2]>;
2257 def : Pat<(v8i16 immAllZerosV), (v8i16 (V_SET0_PI))>, Requires<[HasSSE2]>;
2258 def : Pat<(v4i32 immAllZerosV), (v4i32 (V_SET0_PI))>, Requires<[HasSSE2]>;
2260 // 128-bit vector all one's.
2261 def : Pat<(v16i8 immAllOnesV), (v16i8 (V_SETALLONES))>, Requires<[HasSSE2]>;
2262 def : Pat<(v8i16 immAllOnesV), (v8i16 (V_SETALLONES))>, Requires<[HasSSE2]>;
2263 def : Pat<(v4i32 immAllOnesV), (v4i32 (V_SETALLONES))>, Requires<[HasSSE2]>;
2264 def : Pat<(v2i64 immAllOnesV), (v2i64 (V_SETALLONES))>, Requires<[HasSSE2]>;
2265 def : Pat<(v4f32 immAllOnesV), (v4f32 (V_SETALLONES))>, Requires<[HasSSE1]>;
2267 // Store 128-bit integer vector values.
2268 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
2269 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2270 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
2271 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2272 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
2273 (MOVDQAmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
2275 // Scalar to v8i16 / v16i8. The source may be a R32, but only the lower 8 or
2277 def : Pat<(v8i16 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2278 Requires<[HasSSE2]>;
2279 def : Pat<(v16i8 (X86s2vec R32:$src)), (MOVDI2PDIrr R32:$src)>,
2280 Requires<[HasSSE2]>;
2283 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>,
2284 Requires<[HasSSE2]>;
2285 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>,
2286 Requires<[HasSSE2]>;
2287 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>,
2288 Requires<[HasSSE2]>;
2289 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>,
2290 Requires<[HasSSE2]>;
2291 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>,
2292 Requires<[HasSSE2]>;
2293 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2294 Requires<[HasSSE2]>;
2295 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2296 Requires<[HasSSE2]>;
2297 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2298 Requires<[HasSSE2]>;
2299 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>,
2300 Requires<[HasSSE2]>;
2301 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>,
2302 Requires<[HasSSE2]>;
2303 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2304 Requires<[HasSSE2]>;
2305 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2306 Requires<[HasSSE2]>;
2307 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>,
2308 Requires<[HasSSE2]>;
2309 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>,
2310 Requires<[HasSSE2]>;
2311 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>,
2312 Requires<[HasSSE2]>;
2313 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>,
2314 Requires<[HasSSE2]>;
2315 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v4i32 VR128:$src)>,
2316 Requires<[HasSSE2]>;
2317 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>,
2318 Requires<[HasSSE2]>;
2319 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>,
2320 Requires<[HasSSE2]>;
2321 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>,
2322 Requires<[HasSSE2]>;
2323 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>,
2324 Requires<[HasSSE2]>;
2325 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>,
2326 Requires<[HasSSE2]>;
2327 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>,
2328 Requires<[HasSSE2]>;
2329 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>,
2330 Requires<[HasSSE2]>;
2331 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>,
2332 Requires<[HasSSE2]>;
2333 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>,
2334 Requires<[HasSSE2]>;
2335 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>,
2336 Requires<[HasSSE2]>;
2337 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>,
2338 Requires<[HasSSE2]>;
2339 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>,
2340 Requires<[HasSSE2]>;
2341 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>,
2342 Requires<[HasSSE2]>;
2344 // Zeroing a VR128 then do a MOVS* to the lower bits.
2345 def : Pat<(v2f64 (X86zexts2vec FR64:$src)),
2346 (MOVLSD2PDrr (V_SET0_PD), FR64:$src)>, Requires<[HasSSE2]>;
2347 def : Pat<(v4f32 (X86zexts2vec FR32:$src)),
2348 (MOVLSS2PSrr (V_SET0_PS), FR32:$src)>, Requires<[HasSSE2]>;
2349 def : Pat<(v4i32 (X86zexts2vec R32:$src)),
2350 (MOVLDI2PDIrr (V_SET0_PI), R32:$src)>, Requires<[HasSSE2]>;
2351 def : Pat<(v8i16 (X86zexts2vec R16:$src)),
2352 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr16 R16:$src))>, Requires<[HasSSE2]>;
2353 def : Pat<(v16i8 (X86zexts2vec R8:$src)),
2354 (MOVLDI2PDIrr (V_SET0_PI), (MOVZX32rr8 R8:$src))>, Requires<[HasSSE2]>;
2356 // Splat v2f64 / v2i64
2357 let AddedComplexity = 10 in {
2358 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2359 (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2360 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_v2_mask:$sm),
2361 (v2i64 (PUNPCKLQDQrr VR128:$src, VR128:$src))>, Requires<[HasSSE2]>;
2365 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2366 (v4f32 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm))>,
2367 Requires<[HasSSE1]>;
2369 // Special unary SHUFPSrri case.
2370 // FIXME: when we want non two-address code, then we should use PSHUFD?
2371 def : Pat<(vector_shuffle (v4f32 VR128:$src1), (undef),
2372 SHUFP_unary_shuffle_mask:$sm),
2373 (v4f32 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2374 Requires<[HasSSE1]>;
2375 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2376 def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
2377 SHUFP_unary_shuffle_mask:$sm),
2378 (v4f32 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm))>,
2379 Requires<[HasSSE2]>;
2380 // Special binary v4i32 shuffle cases with SHUFPS.
2381 def : Pat<(vector_shuffle (v4i32 VR128:$src1), (v4i32 VR128:$src2),
2382 PSHUFD_binary_shuffle_mask:$sm),
2383 (v4i32 (SHUFPSrri VR128:$src1, VR128:$src2,
2384 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2385 def : Pat<(vector_shuffle (v4i32 VR128:$src1),
2386 (bc_v4i32 (loadv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm),
2387 (v4i32 (SHUFPSrmi VR128:$src1, addr:$src2,
2388 PSHUFD_binary_shuffle_mask:$sm))>, Requires<[HasSSE2]>;
2390 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2391 let AddedComplexity = 10 in {
2392 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2393 UNPCKL_v_undef_shuffle_mask)),
2394 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2395 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2396 UNPCKL_v_undef_shuffle_mask)),
2397 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2398 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2399 UNPCKL_v_undef_shuffle_mask)),
2400 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2401 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2402 UNPCKL_v_undef_shuffle_mask)),
2403 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2406 let AddedComplexity = 20 in {
2407 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2408 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2409 MOVSHDUP_shuffle_mask)),
2410 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2411 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2412 MOVSHDUP_shuffle_mask)),
2413 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2415 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2416 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2417 MOVSLDUP_shuffle_mask)),
2418 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2419 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (loadv2i64 addr:$src)), (undef),
2420 MOVSLDUP_shuffle_mask)),
2421 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2424 let AddedComplexity = 20 in {
2425 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2426 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2427 MOVHP_shuffle_mask)),
2428 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2430 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2431 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2432 MOVHLPS_shuffle_mask)),
2433 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2435 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2436 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2437 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2438 MOVLP_shuffle_mask)),
2439 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2440 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2441 MOVLP_shuffle_mask)),
2442 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2443 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (loadv4f32 addr:$src2),
2444 MOVHP_shuffle_mask)),
2445 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2446 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (loadv2f64 addr:$src2),
2447 MOVHP_shuffle_mask)),
2448 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2450 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2451 MOVS_shuffle_mask)),
2452 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2453 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)),
2454 MOVLP_shuffle_mask)),
2455 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2456 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2457 MOVS_shuffle_mask)),
2458 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2459 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (loadv2i64 addr:$src2),
2460 MOVHP_shuffle_mask)),
2461 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2464 // 128-bit logical shifts
2465 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2466 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2467 Requires<[HasSSE2]>;
2468 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2469 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>,
2470 Requires<[HasSSE2]>;
2472 // Some special case pandn patterns.
2473 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2475 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2476 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2478 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2479 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2481 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2483 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2484 (load addr:$src2))),
2485 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2486 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2487 (load addr:$src2))),
2488 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2489 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2490 (load addr:$src2))),
2491 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;