1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 class OpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm> {
17 InstrItinClass rr = arg_rr;
18 InstrItinClass rm = arg_rm;
19 // InstrSchedModel info.
20 X86FoldableSchedWrite Sched = WriteFAdd;
23 class SizeItins<OpndItins arg_s, OpndItins arg_d> {
29 class ShiftOpndItins<InstrItinClass arg_rr, InstrItinClass arg_rm,
30 InstrItinClass arg_ri> {
31 InstrItinClass rr = arg_rr;
32 InstrItinClass rm = arg_rm;
33 InstrItinClass ri = arg_ri;
38 let Sched = WriteFAdd in {
39 def SSE_ALU_F32S : OpndItins<
40 IIC_SSE_ALU_F32S_RR, IIC_SSE_ALU_F32S_RM
43 def SSE_ALU_F64S : OpndItins<
44 IIC_SSE_ALU_F64S_RR, IIC_SSE_ALU_F64S_RM
48 def SSE_ALU_ITINS_S : SizeItins<
49 SSE_ALU_F32S, SSE_ALU_F64S
52 let Sched = WriteFMul in {
53 def SSE_MUL_F32S : OpndItins<
54 IIC_SSE_MUL_F32S_RR, IIC_SSE_MUL_F64S_RM
57 def SSE_MUL_F64S : OpndItins<
58 IIC_SSE_MUL_F64S_RR, IIC_SSE_MUL_F64S_RM
62 def SSE_MUL_ITINS_S : SizeItins<
63 SSE_MUL_F32S, SSE_MUL_F64S
66 let Sched = WriteFDiv in {
67 def SSE_DIV_F32S : OpndItins<
68 IIC_SSE_DIV_F32S_RR, IIC_SSE_DIV_F64S_RM
71 def SSE_DIV_F64S : OpndItins<
72 IIC_SSE_DIV_F64S_RR, IIC_SSE_DIV_F64S_RM
76 def SSE_DIV_ITINS_S : SizeItins<
77 SSE_DIV_F32S, SSE_DIV_F64S
81 let Sched = WriteFAdd in {
82 def SSE_ALU_F32P : OpndItins<
83 IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
86 def SSE_ALU_F64P : OpndItins<
87 IIC_SSE_ALU_F64P_RR, IIC_SSE_ALU_F64P_RM
91 def SSE_ALU_ITINS_P : SizeItins<
92 SSE_ALU_F32P, SSE_ALU_F64P
95 let Sched = WriteFMul in {
96 def SSE_MUL_F32P : OpndItins<
97 IIC_SSE_MUL_F32P_RR, IIC_SSE_MUL_F64P_RM
100 def SSE_MUL_F64P : OpndItins<
101 IIC_SSE_MUL_F64P_RR, IIC_SSE_MUL_F64P_RM
105 def SSE_MUL_ITINS_P : SizeItins<
106 SSE_MUL_F32P, SSE_MUL_F64P
109 let Sched = WriteFDiv in {
110 def SSE_DIV_F32P : OpndItins<
111 IIC_SSE_DIV_F32P_RR, IIC_SSE_DIV_F64P_RM
114 def SSE_DIV_F64P : OpndItins<
115 IIC_SSE_DIV_F64P_RR, IIC_SSE_DIV_F64P_RM
119 def SSE_DIV_ITINS_P : SizeItins<
120 SSE_DIV_F32P, SSE_DIV_F64P
123 let Sched = WriteVecLogic in
124 def SSE_VEC_BIT_ITINS_P : OpndItins<
125 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
128 def SSE_BIT_ITINS_P : OpndItins<
129 IIC_SSE_BIT_P_RR, IIC_SSE_BIT_P_RM
132 let Sched = WriteVecALU in {
133 def SSE_INTALU_ITINS_P : OpndItins<
134 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
137 def SSE_INTALUQ_ITINS_P : OpndItins<
138 IIC_SSE_INTALUQ_P_RR, IIC_SSE_INTALUQ_P_RM
142 let Sched = WriteVecIMul in
143 def SSE_INTMUL_ITINS_P : OpndItins<
144 IIC_SSE_INTMUL_P_RR, IIC_SSE_INTMUL_P_RM
147 def SSE_INTSHIFT_ITINS_P : ShiftOpndItins<
148 IIC_SSE_INTSH_P_RR, IIC_SSE_INTSH_P_RM, IIC_SSE_INTSH_P_RI
151 def SSE_MOVA_ITINS : OpndItins<
152 IIC_SSE_MOVA_P_RR, IIC_SSE_MOVA_P_RM
155 def SSE_MOVU_ITINS : OpndItins<
156 IIC_SSE_MOVU_P_RR, IIC_SSE_MOVU_P_RM
159 def SSE_DPPD_ITINS : OpndItins<
160 IIC_SSE_DPPD_RR, IIC_SSE_DPPD_RM
163 def SSE_DPPS_ITINS : OpndItins<
164 IIC_SSE_DPPS_RR, IIC_SSE_DPPD_RM
167 def DEFAULT_ITINS : OpndItins<
168 IIC_ALU_NONMEM, IIC_ALU_MEM
171 def SSE_EXTRACT_ITINS : OpndItins<
172 IIC_SSE_EXTRACTPS_RR, IIC_SSE_EXTRACTPS_RM
175 def SSE_INSERT_ITINS : OpndItins<
176 IIC_SSE_INSERTPS_RR, IIC_SSE_INSERTPS_RM
179 let Sched = WriteMPSAD in
180 def SSE_MPSADBW_ITINS : OpndItins<
181 IIC_SSE_MPSADBW_RR, IIC_SSE_MPSADBW_RM
184 let Sched = WriteVecIMul in
185 def SSE_PMULLD_ITINS : OpndItins<
186 IIC_SSE_PMULLD_RR, IIC_SSE_PMULLD_RM
189 // Definitions for backward compatibility.
190 // The instructions mapped on these definitions uses a different itinerary
191 // than the actual scheduling model.
192 let Sched = WriteShuffle in
193 def DEFAULT_ITINS_SHUFFLESCHED : OpndItins<
194 IIC_ALU_NONMEM, IIC_ALU_MEM
197 let Sched = WriteVecIMul in
198 def DEFAULT_ITINS_VECIMULSCHED : OpndItins<
199 IIC_ALU_NONMEM, IIC_ALU_MEM
202 let Sched = WriteShuffle in
203 def SSE_INTALU_ITINS_SHUFF_P : OpndItins<
204 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
207 let Sched = WriteMPSAD in
208 def DEFAULT_ITINS_MPSADSCHED : OpndItins<
209 IIC_ALU_NONMEM, IIC_ALU_MEM
212 let Sched = WriteFBlend in
213 def DEFAULT_ITINS_FBLENDSCHED : OpndItins<
214 IIC_ALU_NONMEM, IIC_ALU_MEM
217 let Sched = WriteBlend in
218 def DEFAULT_ITINS_BLENDSCHED : OpndItins<
219 IIC_ALU_NONMEM, IIC_ALU_MEM
222 let Sched = WriteVarBlend in
223 def DEFAULT_ITINS_VARBLENDSCHED : OpndItins<
224 IIC_ALU_NONMEM, IIC_ALU_MEM
227 let Sched = WriteFBlend in
228 def SSE_INTALU_ITINS_FBLEND_P : OpndItins<
229 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
232 let Sched = WriteBlend in
233 def SSE_INTALU_ITINS_BLEND_P : OpndItins<
234 IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
237 //===----------------------------------------------------------------------===//
238 // SSE 1 & 2 Instructions Classes
239 //===----------------------------------------------------------------------===//
241 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
242 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
243 RegisterClass RC, X86MemOperand x86memop,
244 Domain d, OpndItins itins, bit Is2Addr = 1> {
245 let isCommutable = 1 in {
246 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
248 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
249 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
250 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], itins.rr, d>,
251 Sched<[itins.Sched]>;
253 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
255 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
256 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
257 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], itins.rm, d>,
258 Sched<[itins.Sched.Folded, ReadAfterLd]>;
261 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
262 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
263 string asm, string SSEVer, string FPSizeStr,
264 Operand memopr, ComplexPattern mem_cpat,
265 Domain d, OpndItins itins, bit Is2Addr = 1> {
266 let isCodeGenOnly = 1 in {
267 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
269 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
270 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
271 [(set RC:$dst, (!cast<Intrinsic>(
272 !strconcat("int_x86_sse", SSEVer, "_", OpcodeStr, FPSizeStr))
273 RC:$src1, RC:$src2))], itins.rr, d>,
274 Sched<[itins.Sched]>;
275 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
277 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
278 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
279 [(set RC:$dst, (!cast<Intrinsic>(!strconcat("int_x86_sse",
280 SSEVer, "_", OpcodeStr, FPSizeStr))
281 RC:$src1, mem_cpat:$src2))], itins.rm, d>,
282 Sched<[itins.Sched.Folded, ReadAfterLd]>;
286 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
287 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
288 RegisterClass RC, ValueType vt,
289 X86MemOperand x86memop, PatFrag mem_frag,
290 Domain d, OpndItins itins, bit Is2Addr = 1> {
291 let isCommutable = 1 in
292 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
294 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
295 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
296 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
297 Sched<[itins.Sched]>;
299 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
301 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
302 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
303 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
305 Sched<[itins.Sched.Folded, ReadAfterLd]>;
308 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
309 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
310 string OpcodeStr, X86MemOperand x86memop,
311 list<dag> pat_rr, list<dag> pat_rm,
313 let isCommutable = 1, hasSideEffects = 0 in
314 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
316 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
317 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
318 pat_rr, NoItinerary, d>,
319 Sched<[WriteVecLogic]>;
320 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
322 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
323 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
324 pat_rm, NoItinerary, d>,
325 Sched<[WriteVecLogicLd, ReadAfterLd]>;
328 //===----------------------------------------------------------------------===//
329 // Non-instruction patterns
330 //===----------------------------------------------------------------------===//
332 // A vector extract of the first f32/f64 position is a subregister copy
333 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
334 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
335 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
336 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
338 // A 128-bit subvector extract from the first 256-bit vector position
339 // is a subregister copy that needs no instruction.
340 def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (iPTR 0))),
341 (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
342 def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (iPTR 0))),
343 (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
345 def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (iPTR 0))),
346 (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
347 def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (iPTR 0))),
348 (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
350 def : Pat<(v8i16 (extract_subvector (v16i16 VR256:$src), (iPTR 0))),
351 (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src), sub_xmm))>;
352 def : Pat<(v16i8 (extract_subvector (v32i8 VR256:$src), (iPTR 0))),
353 (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src), sub_xmm))>;
355 // A 128-bit subvector insert to the first 256-bit vector position
356 // is a subregister copy that needs no instruction.
357 let AddedComplexity = 25 in { // to give priority over vinsertf128rm
358 def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)),
359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
360 def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)),
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
362 def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)),
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
364 def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)),
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
366 def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (iPTR 0)),
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
368 def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (iPTR 0)),
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
372 // Implicitly promote a 32-bit scalar to a vector.
373 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
374 (COPY_TO_REGCLASS FR32:$src, VR128)>;
375 def : Pat<(v8f32 (scalar_to_vector FR32:$src)),
376 (COPY_TO_REGCLASS FR32:$src, VR128)>;
377 // Implicitly promote a 64-bit scalar to a vector.
378 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
379 (COPY_TO_REGCLASS FR64:$src, VR128)>;
380 def : Pat<(v4f64 (scalar_to_vector FR64:$src)),
381 (COPY_TO_REGCLASS FR64:$src, VR128)>;
383 // Bitcasts between 128-bit vector types. Return the original type since
384 // no instruction is needed for the conversion
385 let Predicates = [HasSSE2] in {
386 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
387 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
388 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
389 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
390 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
391 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
392 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
393 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
394 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
395 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
396 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
397 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
398 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
399 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
400 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
401 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
402 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
403 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
404 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
405 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
406 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
407 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
408 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
409 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
410 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
411 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
412 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
413 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
414 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
415 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
418 // Bitcasts between 256-bit vector types. Return the original type since
419 // no instruction is needed for the conversion
420 let Predicates = [HasAVX] in {
421 def : Pat<(v4f64 (bitconvert (v8f32 VR256:$src))), (v4f64 VR256:$src)>;
422 def : Pat<(v4f64 (bitconvert (v8i32 VR256:$src))), (v4f64 VR256:$src)>;
423 def : Pat<(v4f64 (bitconvert (v4i64 VR256:$src))), (v4f64 VR256:$src)>;
424 def : Pat<(v4f64 (bitconvert (v16i16 VR256:$src))), (v4f64 VR256:$src)>;
425 def : Pat<(v4f64 (bitconvert (v32i8 VR256:$src))), (v4f64 VR256:$src)>;
426 def : Pat<(v8f32 (bitconvert (v8i32 VR256:$src))), (v8f32 VR256:$src)>;
427 def : Pat<(v8f32 (bitconvert (v4i64 VR256:$src))), (v8f32 VR256:$src)>;
428 def : Pat<(v8f32 (bitconvert (v4f64 VR256:$src))), (v8f32 VR256:$src)>;
429 def : Pat<(v8f32 (bitconvert (v32i8 VR256:$src))), (v8f32 VR256:$src)>;
430 def : Pat<(v8f32 (bitconvert (v16i16 VR256:$src))), (v8f32 VR256:$src)>;
431 def : Pat<(v4i64 (bitconvert (v8f32 VR256:$src))), (v4i64 VR256:$src)>;
432 def : Pat<(v4i64 (bitconvert (v8i32 VR256:$src))), (v4i64 VR256:$src)>;
433 def : Pat<(v4i64 (bitconvert (v4f64 VR256:$src))), (v4i64 VR256:$src)>;
434 def : Pat<(v4i64 (bitconvert (v32i8 VR256:$src))), (v4i64 VR256:$src)>;
435 def : Pat<(v4i64 (bitconvert (v16i16 VR256:$src))), (v4i64 VR256:$src)>;
436 def : Pat<(v32i8 (bitconvert (v4f64 VR256:$src))), (v32i8 VR256:$src)>;
437 def : Pat<(v32i8 (bitconvert (v4i64 VR256:$src))), (v32i8 VR256:$src)>;
438 def : Pat<(v32i8 (bitconvert (v8f32 VR256:$src))), (v32i8 VR256:$src)>;
439 def : Pat<(v32i8 (bitconvert (v8i32 VR256:$src))), (v32i8 VR256:$src)>;
440 def : Pat<(v32i8 (bitconvert (v16i16 VR256:$src))), (v32i8 VR256:$src)>;
441 def : Pat<(v8i32 (bitconvert (v32i8 VR256:$src))), (v8i32 VR256:$src)>;
442 def : Pat<(v8i32 (bitconvert (v16i16 VR256:$src))), (v8i32 VR256:$src)>;
443 def : Pat<(v8i32 (bitconvert (v8f32 VR256:$src))), (v8i32 VR256:$src)>;
444 def : Pat<(v8i32 (bitconvert (v4i64 VR256:$src))), (v8i32 VR256:$src)>;
445 def : Pat<(v8i32 (bitconvert (v4f64 VR256:$src))), (v8i32 VR256:$src)>;
446 def : Pat<(v16i16 (bitconvert (v8f32 VR256:$src))), (v16i16 VR256:$src)>;
447 def : Pat<(v16i16 (bitconvert (v8i32 VR256:$src))), (v16i16 VR256:$src)>;
448 def : Pat<(v16i16 (bitconvert (v4i64 VR256:$src))), (v16i16 VR256:$src)>;
449 def : Pat<(v16i16 (bitconvert (v4f64 VR256:$src))), (v16i16 VR256:$src)>;
450 def : Pat<(v16i16 (bitconvert (v32i8 VR256:$src))), (v16i16 VR256:$src)>;
453 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
454 // This is expanded by ExpandPostRAPseudos.
455 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
456 isPseudo = 1, SchedRW = [WriteZero] in {
457 def FsFLD0SS : I<0, Pseudo, (outs FR32:$dst), (ins), "",
458 [(set FR32:$dst, fp32imm0)]>, Requires<[HasSSE1]>;
459 def FsFLD0SD : I<0, Pseudo, (outs FR64:$dst), (ins), "",
460 [(set FR64:$dst, fpimm0)]>, Requires<[HasSSE2]>;
463 //===----------------------------------------------------------------------===//
464 // AVX & SSE - Zero/One Vectors
465 //===----------------------------------------------------------------------===//
467 // Alias instruction that maps zero vector to pxor / xorp* for sse.
468 // This is expanded by ExpandPostRAPseudos to an xorps / vxorps, and then
469 // swizzled by ExecutionDepsFix to pxor.
470 // We set canFoldAsLoad because this can be converted to a constant-pool
471 // load of an all-zeros value if folding it would be beneficial.
472 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
473 isPseudo = 1, SchedRW = [WriteZero] in {
474 def V_SET0 : I<0, Pseudo, (outs VR128:$dst), (ins), "",
475 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
478 def : Pat<(v2f64 immAllZerosV), (V_SET0)>;
479 def : Pat<(v4i32 immAllZerosV), (V_SET0)>;
480 def : Pat<(v2i64 immAllZerosV), (V_SET0)>;
481 def : Pat<(v8i16 immAllZerosV), (V_SET0)>;
482 def : Pat<(v16i8 immAllZerosV), (V_SET0)>;
485 // The same as done above but for AVX. The 256-bit AVX1 ISA doesn't support PI,
486 // and doesn't need it because on sandy bridge the register is set to zero
487 // at the rename stage without using any execution unit, so SET0PSY
488 // and SET0PDY can be used for vector int instructions without penalty
489 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
490 isPseudo = 1, Predicates = [HasAVX], SchedRW = [WriteZero] in {
491 def AVX_SET0 : I<0, Pseudo, (outs VR256:$dst), (ins), "",
492 [(set VR256:$dst, (v8f32 immAllZerosV))]>;
495 let Predicates = [HasAVX] in
496 def : Pat<(v4f64 immAllZerosV), (AVX_SET0)>;
498 let Predicates = [HasAVX2] in {
499 def : Pat<(v4i64 immAllZerosV), (AVX_SET0)>;
500 def : Pat<(v8i32 immAllZerosV), (AVX_SET0)>;
501 def : Pat<(v16i16 immAllZerosV), (AVX_SET0)>;
502 def : Pat<(v32i8 immAllZerosV), (AVX_SET0)>;
505 // AVX1 has no support for 256-bit integer instructions, but since the 128-bit
506 // VPXOR instruction writes zero to its upper part, it's safe build zeros.
507 let Predicates = [HasAVX1Only] in {
508 def : Pat<(v32i8 immAllZerosV), (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
509 def : Pat<(bc_v32i8 (v8f32 immAllZerosV)),
510 (SUBREG_TO_REG (i8 0), (V_SET0), sub_xmm)>;
512 def : Pat<(v16i16 immAllZerosV), (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
513 def : Pat<(bc_v16i16 (v8f32 immAllZerosV)),
514 (SUBREG_TO_REG (i16 0), (V_SET0), sub_xmm)>;
516 def : Pat<(v8i32 immAllZerosV), (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
517 def : Pat<(bc_v8i32 (v8f32 immAllZerosV)),
518 (SUBREG_TO_REG (i32 0), (V_SET0), sub_xmm)>;
520 def : Pat<(v4i64 immAllZerosV), (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
521 def : Pat<(bc_v4i64 (v8f32 immAllZerosV)),
522 (SUBREG_TO_REG (i64 0), (V_SET0), sub_xmm)>;
525 // We set canFoldAsLoad because this can be converted to a constant-pool
526 // load of an all-ones value if folding it would be beneficial.
527 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
528 isPseudo = 1, SchedRW = [WriteZero] in {
529 def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "",
530 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
531 let Predicates = [HasAVX2] in
532 def AVX2_SETALLONES : I<0, Pseudo, (outs VR256:$dst), (ins), "",
533 [(set VR256:$dst, (v8i32 immAllOnesV))]>;
537 //===----------------------------------------------------------------------===//
538 // SSE 1 & 2 - Move FP Scalar Instructions
540 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
541 // register copies because it's a partial register update; Register-to-register
542 // movss/movsd is not modeled as an INSERT_SUBREG because INSERT_SUBREG requires
543 // that the insert be implementable in terms of a copy, and just mentioned, we
544 // don't use movss/movsd for copies.
545 //===----------------------------------------------------------------------===//
547 multiclass sse12_move_rr<RegisterClass RC, SDNode OpNode, ValueType vt,
548 X86MemOperand x86memop, string base_opc,
549 string asm_opr, Domain d = GenericDomain> {
550 def rr : SI<0x10, MRMSrcReg, (outs VR128:$dst),
551 (ins VR128:$src1, RC:$src2),
552 !strconcat(base_opc, asm_opr),
553 [(set VR128:$dst, (vt (OpNode VR128:$src1,
554 (scalar_to_vector RC:$src2))))],
555 IIC_SSE_MOV_S_RR, d>, Sched<[WriteFShuffle]>;
557 // For the disassembler
558 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
559 def rr_REV : SI<0x11, MRMDestReg, (outs VR128:$dst),
560 (ins VR128:$src1, RC:$src2),
561 !strconcat(base_opc, asm_opr),
562 [], IIC_SSE_MOV_S_RR>, Sched<[WriteFShuffle]>;
565 multiclass sse12_move<RegisterClass RC, SDNode OpNode, ValueType vt,
566 X86MemOperand x86memop, string OpcodeStr,
567 Domain d = GenericDomain> {
569 defm V#NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
570 "\t{$src2, $src1, $dst|$dst, $src1, $src2}", d>,
573 def V#NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
574 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
575 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
576 VEX, VEX_LIG, Sched<[WriteStore]>;
578 let Constraints = "$src1 = $dst" in {
579 defm NAME : sse12_move_rr<RC, OpNode, vt, x86memop, OpcodeStr,
580 "\t{$src2, $dst|$dst, $src2}", d>;
583 def NAME#mr : SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
584 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
585 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR, d>,
589 // Loading from memory automatically zeroing upper bits.
590 multiclass sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
591 PatFrag mem_pat, string OpcodeStr,
592 Domain d = GenericDomain> {
593 def V#NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
594 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
595 [(set RC:$dst, (mem_pat addr:$src))],
596 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
597 def NAME#rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
598 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
599 [(set RC:$dst, (mem_pat addr:$src))],
600 IIC_SSE_MOV_S_RM, d>, Sched<[WriteLoad]>;
603 defm MOVSS : sse12_move<FR32, X86Movss, v4f32, f32mem, "movss",
604 SSEPackedSingle>, XS;
605 defm MOVSD : sse12_move<FR64, X86Movsd, v2f64, f64mem, "movsd",
606 SSEPackedDouble>, XD;
608 let canFoldAsLoad = 1, isReMaterializable = 1 in {
609 defm MOVSS : sse12_move_rm<FR32, f32mem, loadf32, "movss",
610 SSEPackedSingle>, XS;
612 let AddedComplexity = 20 in
613 defm MOVSD : sse12_move_rm<FR64, f64mem, loadf64, "movsd",
614 SSEPackedDouble>, XD;
618 let Predicates = [UseAVX] in {
619 let AddedComplexity = 20 in {
620 // MOVSSrm zeros the high parts of the register; represent this
621 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
622 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
623 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
624 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
625 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
626 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
627 (COPY_TO_REGCLASS (VMOVSSrm addr:$src), VR128)>;
629 // MOVSDrm zeros the high parts of the register; represent this
630 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
631 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
632 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
633 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
634 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
635 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
636 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
637 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
638 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
639 def : Pat<(v2f64 (X86vzload addr:$src)),
640 (COPY_TO_REGCLASS (VMOVSDrm addr:$src), VR128)>;
642 // Represent the same patterns above but in the form they appear for
644 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
645 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
646 (SUBREG_TO_REG (i32 0), (VMOVSSrm addr:$src), sub_xmm)>;
647 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
648 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
649 (SUBREG_TO_REG (i32 0), (VMOVSDrm addr:$src), sub_xmm)>;
652 // Extract and store.
653 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
655 (VMOVSSmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32))>;
656 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
658 (VMOVSDmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64))>;
660 // Shuffle with VMOVSS
661 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
662 (VMOVSSrr (v4i32 VR128:$src1),
663 (COPY_TO_REGCLASS (v4i32 VR128:$src2), FR32))>;
664 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
665 (VMOVSSrr (v4f32 VR128:$src1),
666 (COPY_TO_REGCLASS (v4f32 VR128:$src2), FR32))>;
669 def : Pat<(v8i32 (X86Movss VR256:$src1, VR256:$src2)),
670 (SUBREG_TO_REG (i32 0),
671 (VMOVSSrr (EXTRACT_SUBREG (v8i32 VR256:$src1), sub_xmm),
672 (EXTRACT_SUBREG (v8i32 VR256:$src2), sub_xmm)),
674 def : Pat<(v8f32 (X86Movss VR256:$src1, VR256:$src2)),
675 (SUBREG_TO_REG (i32 0),
676 (VMOVSSrr (EXTRACT_SUBREG (v8f32 VR256:$src1), sub_xmm),
677 (EXTRACT_SUBREG (v8f32 VR256:$src2), sub_xmm)),
680 // Shuffle with VMOVSD
681 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
682 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
683 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
684 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
685 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
686 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
687 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
688 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
691 def : Pat<(v4i64 (X86Movsd VR256:$src1, VR256:$src2)),
692 (SUBREG_TO_REG (i32 0),
693 (VMOVSDrr (EXTRACT_SUBREG (v4i64 VR256:$src1), sub_xmm),
694 (EXTRACT_SUBREG (v4i64 VR256:$src2), sub_xmm)),
696 def : Pat<(v4f64 (X86Movsd VR256:$src1, VR256:$src2)),
697 (SUBREG_TO_REG (i32 0),
698 (VMOVSDrr (EXTRACT_SUBREG (v4f64 VR256:$src1), sub_xmm),
699 (EXTRACT_SUBREG (v4f64 VR256:$src2), sub_xmm)),
702 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
703 // is during lowering, where it's not possible to recognize the fold cause
704 // it has two uses through a bitcast. One use disappears at isel time and the
705 // fold opportunity reappears.
706 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
707 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
708 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
709 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
710 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
711 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
712 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
713 (VMOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
716 let Predicates = [UseSSE1] in {
717 let Predicates = [NoSSE41], AddedComplexity = 15 in {
718 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
719 // MOVSS to the lower bits.
720 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
721 (MOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
722 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
723 (MOVSSrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
724 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
725 (MOVSSrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128:$src, FR32))>;
728 let AddedComplexity = 20 in {
729 // MOVSSrm already zeros the high parts of the register.
730 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
731 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
732 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
733 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
734 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
735 (COPY_TO_REGCLASS (MOVSSrm addr:$src), VR128)>;
738 // Extract and store.
739 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
741 (MOVSSmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR32))>;
743 // Shuffle with MOVSS
744 def : Pat<(v4i32 (X86Movss VR128:$src1, VR128:$src2)),
745 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
746 def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
747 (MOVSSrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR32))>;
750 let Predicates = [UseSSE2] in {
751 let Predicates = [NoSSE41], AddedComplexity = 15 in {
752 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
753 // MOVSD to the lower bits.
754 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
755 (MOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
758 let AddedComplexity = 20 in {
759 // MOVSDrm already zeros the high parts of the register.
760 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
761 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
762 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
763 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
764 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
765 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
766 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
767 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
768 def : Pat<(v2f64 (X86vzload addr:$src)),
769 (COPY_TO_REGCLASS (MOVSDrm addr:$src), VR128)>;
772 // Extract and store.
773 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
775 (MOVSDmr addr:$dst, (COPY_TO_REGCLASS VR128:$src, FR64))>;
777 // Shuffle with MOVSD
778 def : Pat<(v2i64 (X86Movsd VR128:$src1, VR128:$src2)),
779 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
780 def : Pat<(v2f64 (X86Movsd VR128:$src1, VR128:$src2)),
781 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
782 def : Pat<(v4f32 (X86Movsd VR128:$src1, VR128:$src2)),
783 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
784 def : Pat<(v4i32 (X86Movsd VR128:$src1, VR128:$src2)),
785 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
787 // FIXME: Instead of a X86Movlps there should be a X86Movsd here, the problem
788 // is during lowering, where it's not possible to recognize the fold because
789 // it has two uses through a bitcast. One use disappears at isel time and the
790 // fold opportunity reappears.
791 def : Pat<(v2f64 (X86Movlpd VR128:$src1, VR128:$src2)),
792 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
793 def : Pat<(v2i64 (X86Movlpd VR128:$src1, VR128:$src2)),
794 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
795 def : Pat<(v4f32 (X86Movlps VR128:$src1, VR128:$src2)),
796 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
797 def : Pat<(v4i32 (X86Movlps VR128:$src1, VR128:$src2)),
798 (MOVSDrr VR128:$src1, (COPY_TO_REGCLASS VR128:$src2, FR64))>;
801 //===----------------------------------------------------------------------===//
802 // SSE 1 & 2 - Move Aligned/Unaligned FP Instructions
803 //===----------------------------------------------------------------------===//
805 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
806 X86MemOperand x86memop, PatFrag ld_frag,
807 string asm, Domain d,
809 bit IsReMaterializable = 1> {
810 let hasSideEffects = 0 in
811 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
812 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], itins.rr, d>,
813 Sched<[WriteFShuffle]>;
814 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
815 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
816 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
817 [(set RC:$dst, (ld_frag addr:$src))], itins.rm, d>,
821 let Predicates = [HasAVX, NoVLX] in {
822 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
823 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
825 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
826 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
828 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
829 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
831 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
832 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
835 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
836 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
838 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
839 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
841 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
842 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
844 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
845 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
849 let Predicates = [UseSSE1] in {
850 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
851 "movaps", SSEPackedSingle, SSE_MOVA_ITINS>,
853 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
854 "movups", SSEPackedSingle, SSE_MOVU_ITINS>,
857 let Predicates = [UseSSE2] in {
858 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
859 "movapd", SSEPackedDouble, SSE_MOVA_ITINS>,
861 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
862 "movupd", SSEPackedDouble, SSE_MOVU_ITINS, 0>,
866 let SchedRW = [WriteStore], Predicates = [HasAVX, NoVLX] in {
867 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
868 "movaps\t{$src, $dst|$dst, $src}",
869 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
870 IIC_SSE_MOVA_P_MR>, VEX;
871 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
872 "movapd\t{$src, $dst|$dst, $src}",
873 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
874 IIC_SSE_MOVA_P_MR>, VEX;
875 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
876 "movups\t{$src, $dst|$dst, $src}",
877 [(store (v4f32 VR128:$src), addr:$dst)],
878 IIC_SSE_MOVU_P_MR>, VEX;
879 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
880 "movupd\t{$src, $dst|$dst, $src}",
881 [(store (v2f64 VR128:$src), addr:$dst)],
882 IIC_SSE_MOVU_P_MR>, VEX;
883 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
884 "movaps\t{$src, $dst|$dst, $src}",
885 [(alignedstore256 (v8f32 VR256:$src), addr:$dst)],
886 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
887 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
888 "movapd\t{$src, $dst|$dst, $src}",
889 [(alignedstore256 (v4f64 VR256:$src), addr:$dst)],
890 IIC_SSE_MOVA_P_MR>, VEX, VEX_L;
891 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
892 "movups\t{$src, $dst|$dst, $src}",
893 [(store (v8f32 VR256:$src), addr:$dst)],
894 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
895 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
896 "movupd\t{$src, $dst|$dst, $src}",
897 [(store (v4f64 VR256:$src), addr:$dst)],
898 IIC_SSE_MOVU_P_MR>, VEX, VEX_L;
902 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
903 SchedRW = [WriteFShuffle] in {
904 def VMOVAPSrr_REV : VPSI<0x29, MRMDestReg, (outs VR128:$dst),
906 "movaps\t{$src, $dst|$dst, $src}", [],
907 IIC_SSE_MOVA_P_RR>, VEX;
908 def VMOVAPDrr_REV : VPDI<0x29, MRMDestReg, (outs VR128:$dst),
910 "movapd\t{$src, $dst|$dst, $src}", [],
911 IIC_SSE_MOVA_P_RR>, VEX;
912 def VMOVUPSrr_REV : VPSI<0x11, MRMDestReg, (outs VR128:$dst),
914 "movups\t{$src, $dst|$dst, $src}", [],
915 IIC_SSE_MOVU_P_RR>, VEX;
916 def VMOVUPDrr_REV : VPDI<0x11, MRMDestReg, (outs VR128:$dst),
918 "movupd\t{$src, $dst|$dst, $src}", [],
919 IIC_SSE_MOVU_P_RR>, VEX;
920 def VMOVAPSYrr_REV : VPSI<0x29, MRMDestReg, (outs VR256:$dst),
922 "movaps\t{$src, $dst|$dst, $src}", [],
923 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
924 def VMOVAPDYrr_REV : VPDI<0x29, MRMDestReg, (outs VR256:$dst),
926 "movapd\t{$src, $dst|$dst, $src}", [],
927 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
928 def VMOVUPSYrr_REV : VPSI<0x11, MRMDestReg, (outs VR256:$dst),
930 "movups\t{$src, $dst|$dst, $src}", [],
931 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
932 def VMOVUPDYrr_REV : VPDI<0x11, MRMDestReg, (outs VR256:$dst),
934 "movupd\t{$src, $dst|$dst, $src}", [],
935 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
938 let Predicates = [HasAVX] in {
939 def : Pat<(v8i32 (X86vzmovl
940 (insert_subvector undef, (v4i32 VR128:$src), (iPTR 0)))),
941 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
942 def : Pat<(v4i64 (X86vzmovl
943 (insert_subvector undef, (v2i64 VR128:$src), (iPTR 0)))),
944 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
945 def : Pat<(v8f32 (X86vzmovl
946 (insert_subvector undef, (v4f32 VR128:$src), (iPTR 0)))),
947 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
948 def : Pat<(v4f64 (X86vzmovl
949 (insert_subvector undef, (v2f64 VR128:$src), (iPTR 0)))),
950 (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
954 def : Pat<(int_x86_avx_storeu_ps_256 addr:$dst, VR256:$src),
955 (VMOVUPSYmr addr:$dst, VR256:$src)>;
956 def : Pat<(int_x86_avx_storeu_pd_256 addr:$dst, VR256:$src),
957 (VMOVUPDYmr addr:$dst, VR256:$src)>;
959 let SchedRW = [WriteStore] in {
960 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
961 "movaps\t{$src, $dst|$dst, $src}",
962 [(alignedstore (v4f32 VR128:$src), addr:$dst)],
964 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
965 "movapd\t{$src, $dst|$dst, $src}",
966 [(alignedstore (v2f64 VR128:$src), addr:$dst)],
968 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
969 "movups\t{$src, $dst|$dst, $src}",
970 [(store (v4f32 VR128:$src), addr:$dst)],
972 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
973 "movupd\t{$src, $dst|$dst, $src}",
974 [(store (v2f64 VR128:$src), addr:$dst)],
979 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
980 SchedRW = [WriteFShuffle] in {
981 def MOVAPSrr_REV : PSI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
982 "movaps\t{$src, $dst|$dst, $src}", [],
984 def MOVAPDrr_REV : PDI<0x29, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
985 "movapd\t{$src, $dst|$dst, $src}", [],
987 def MOVUPSrr_REV : PSI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
988 "movups\t{$src, $dst|$dst, $src}", [],
990 def MOVUPDrr_REV : PDI<0x11, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
991 "movupd\t{$src, $dst|$dst, $src}", [],
995 let Predicates = [HasAVX] in {
996 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
997 (VMOVUPSmr addr:$dst, VR128:$src)>;
998 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
999 (VMOVUPDmr addr:$dst, VR128:$src)>;
1002 let Predicates = [UseSSE1] in
1003 def : Pat<(int_x86_sse_storeu_ps addr:$dst, VR128:$src),
1004 (MOVUPSmr addr:$dst, VR128:$src)>;
1005 let Predicates = [UseSSE2] in
1006 def : Pat<(int_x86_sse2_storeu_pd addr:$dst, VR128:$src),
1007 (MOVUPDmr addr:$dst, VR128:$src)>;
1009 // Use vmovaps/vmovups for AVX integer load/store.
1010 let Predicates = [HasAVX, NoVLX] in {
1011 // 128-bit load/store
1012 def : Pat<(alignedloadv2i64 addr:$src),
1013 (VMOVAPSrm addr:$src)>;
1014 def : Pat<(loadv2i64 addr:$src),
1015 (VMOVUPSrm addr:$src)>;
1017 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1018 (VMOVAPSmr addr:$dst, VR128:$src)>;
1019 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1020 (VMOVAPSmr addr:$dst, VR128:$src)>;
1021 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1022 (VMOVAPSmr addr:$dst, VR128:$src)>;
1023 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1024 (VMOVAPSmr addr:$dst, VR128:$src)>;
1025 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1026 (VMOVUPSmr addr:$dst, VR128:$src)>;
1027 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1028 (VMOVUPSmr addr:$dst, VR128:$src)>;
1029 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1030 (VMOVUPSmr addr:$dst, VR128:$src)>;
1031 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1032 (VMOVUPSmr addr:$dst, VR128:$src)>;
1034 // 256-bit load/store
1035 def : Pat<(alignedloadv4i64 addr:$src),
1036 (VMOVAPSYrm addr:$src)>;
1037 def : Pat<(loadv4i64 addr:$src),
1038 (VMOVUPSYrm addr:$src)>;
1039 def : Pat<(alignedstore256 (v4i64 VR256:$src), addr:$dst),
1040 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1041 def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
1042 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1043 def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
1044 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1045 def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
1046 (VMOVAPSYmr addr:$dst, VR256:$src)>;
1047 def : Pat<(store (v4i64 VR256:$src), addr:$dst),
1048 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1049 def : Pat<(store (v8i32 VR256:$src), addr:$dst),
1050 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1051 def : Pat<(store (v16i16 VR256:$src), addr:$dst),
1052 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1053 def : Pat<(store (v32i8 VR256:$src), addr:$dst),
1054 (VMOVUPSYmr addr:$dst, VR256:$src)>;
1056 // Special patterns for storing subvector extracts of lower 128-bits
1057 // Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
1058 def : Pat<(alignedstore (v2f64 (extract_subvector
1059 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1060 (VMOVAPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1061 def : Pat<(alignedstore (v4f32 (extract_subvector
1062 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1063 (VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1064 def : Pat<(alignedstore (v2i64 (extract_subvector
1065 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1066 (VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1067 def : Pat<(alignedstore (v4i32 (extract_subvector
1068 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1069 (VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1070 def : Pat<(alignedstore (v8i16 (extract_subvector
1071 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1072 (VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1073 def : Pat<(alignedstore (v16i8 (extract_subvector
1074 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1075 (VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1077 def : Pat<(store (v2f64 (extract_subvector
1078 (v4f64 VR256:$src), (iPTR 0))), addr:$dst),
1079 (VMOVUPDmr addr:$dst, (v2f64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1080 def : Pat<(store (v4f32 (extract_subvector
1081 (v8f32 VR256:$src), (iPTR 0))), addr:$dst),
1082 (VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1083 def : Pat<(store (v2i64 (extract_subvector
1084 (v4i64 VR256:$src), (iPTR 0))), addr:$dst),
1085 (VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1086 def : Pat<(store (v4i32 (extract_subvector
1087 (v8i32 VR256:$src), (iPTR 0))), addr:$dst),
1088 (VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1089 def : Pat<(store (v8i16 (extract_subvector
1090 (v16i16 VR256:$src), (iPTR 0))), addr:$dst),
1091 (VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1092 def : Pat<(store (v16i8 (extract_subvector
1093 (v32i8 VR256:$src), (iPTR 0))), addr:$dst),
1094 (VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
1097 // Use movaps / movups for SSE integer load / store (one byte shorter).
1098 // The instructions selected below are then converted to MOVDQA/MOVDQU
1099 // during the SSE domain pass.
1100 let Predicates = [UseSSE1] in {
1101 def : Pat<(alignedloadv2i64 addr:$src),
1102 (MOVAPSrm addr:$src)>;
1103 def : Pat<(loadv2i64 addr:$src),
1104 (MOVUPSrm addr:$src)>;
1106 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
1107 (MOVAPSmr addr:$dst, VR128:$src)>;
1108 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
1109 (MOVAPSmr addr:$dst, VR128:$src)>;
1110 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
1111 (MOVAPSmr addr:$dst, VR128:$src)>;
1112 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
1113 (MOVAPSmr addr:$dst, VR128:$src)>;
1114 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
1115 (MOVUPSmr addr:$dst, VR128:$src)>;
1116 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
1117 (MOVUPSmr addr:$dst, VR128:$src)>;
1118 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
1119 (MOVUPSmr addr:$dst, VR128:$src)>;
1120 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
1121 (MOVUPSmr addr:$dst, VR128:$src)>;
1124 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1125 // bits are disregarded. FIXME: Set encoding to pseudo!
1126 let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in {
1127 let isCodeGenOnly = 1 in {
1128 def FsVMOVAPSrm : VPSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1129 "movaps\t{$src, $dst|$dst, $src}",
1130 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1131 IIC_SSE_MOVA_P_RM>, VEX;
1132 def FsVMOVAPDrm : VPDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1133 "movapd\t{$src, $dst|$dst, $src}",
1134 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1135 IIC_SSE_MOVA_P_RM>, VEX;
1136 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1137 "movaps\t{$src, $dst|$dst, $src}",
1138 [(set FR32:$dst, (alignedloadfsf32 addr:$src))],
1140 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1141 "movapd\t{$src, $dst|$dst, $src}",
1142 [(set FR64:$dst, (alignedloadfsf64 addr:$src))],
1147 //===----------------------------------------------------------------------===//
1148 // SSE 1 & 2 - Move Low packed FP Instructions
1149 //===----------------------------------------------------------------------===//
1151 multiclass sse12_mov_hilo_packed_base<bits<8>opc, SDNode psnode, SDNode pdnode,
1152 string base_opc, string asm_opr,
1153 InstrItinClass itin> {
1154 def PSrm : PI<opc, MRMSrcMem,
1155 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1156 !strconcat(base_opc, "s", asm_opr),
1158 (psnode VR128:$src1,
1159 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
1160 itin, SSEPackedSingle>, PS,
1161 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1163 def PDrm : PI<opc, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1165 !strconcat(base_opc, "d", asm_opr),
1166 [(set VR128:$dst, (v2f64 (pdnode VR128:$src1,
1167 (scalar_to_vector (loadf64 addr:$src2)))))],
1168 itin, SSEPackedDouble>, PD,
1169 Sched<[WriteFShuffleLd, ReadAfterLd]>;
1173 multiclass sse12_mov_hilo_packed<bits<8>opc, SDNode psnode, SDNode pdnode,
1174 string base_opc, InstrItinClass itin> {
1175 defm V#NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1176 "\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1179 let Constraints = "$src1 = $dst" in
1180 defm NAME : sse12_mov_hilo_packed_base<opc, psnode, pdnode, base_opc,
1181 "\t{$src2, $dst|$dst, $src2}",
1185 let AddedComplexity = 20 in {
1186 defm MOVL : sse12_mov_hilo_packed<0x12, X86Movlps, X86Movlpd, "movlp",
1190 let SchedRW = [WriteStore] in {
1191 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1192 "movlps\t{$src, $dst|$dst, $src}",
1193 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1194 (iPTR 0))), addr:$dst)],
1195 IIC_SSE_MOV_LH>, VEX;
1196 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1197 "movlpd\t{$src, $dst|$dst, $src}",
1198 [(store (f64 (vector_extract (v2f64 VR128:$src),
1199 (iPTR 0))), addr:$dst)],
1200 IIC_SSE_MOV_LH>, VEX;
1201 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1202 "movlps\t{$src, $dst|$dst, $src}",
1203 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
1204 (iPTR 0))), addr:$dst)],
1206 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1207 "movlpd\t{$src, $dst|$dst, $src}",
1208 [(store (f64 (vector_extract (v2f64 VR128:$src),
1209 (iPTR 0))), addr:$dst)],
1213 let Predicates = [HasAVX] in {
1214 // Shuffle with VMOVLPS
1215 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1216 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1217 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1218 (VMOVLPSrm VR128:$src1, addr:$src2)>;
1220 // Shuffle with VMOVLPD
1221 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1222 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1223 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1224 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1225 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1226 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1227 (VMOVLPDrm VR128:$src1, addr:$src2)>;
1230 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1232 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1233 def : Pat<(store (v4i32 (X86Movlps
1234 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)), addr:$src1),
1235 (VMOVLPSmr addr:$src1, VR128:$src2)>;
1236 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1238 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1239 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1241 (VMOVLPDmr addr:$src1, VR128:$src2)>;
1244 let Predicates = [UseSSE1] in {
1245 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
1246 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v4f32 VR128:$src2)),
1247 (iPTR 0))), addr:$src1),
1248 (MOVLPSmr addr:$src1, VR128:$src2)>;
1250 // Shuffle with MOVLPS
1251 def : Pat<(v4f32 (X86Movlps VR128:$src1, (load addr:$src2))),
1252 (MOVLPSrm VR128:$src1, addr:$src2)>;
1253 def : Pat<(v4i32 (X86Movlps VR128:$src1, (load addr:$src2))),
1254 (MOVLPSrm VR128:$src1, addr:$src2)>;
1255 def : Pat<(X86Movlps VR128:$src1,
1256 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1257 (MOVLPSrm VR128:$src1, addr:$src2)>;
1260 def : Pat<(store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)),
1262 (MOVLPSmr addr:$src1, VR128:$src2)>;
1263 def : Pat<(store (v4i32 (X86Movlps
1264 (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
1266 (MOVLPSmr addr:$src1, VR128:$src2)>;
1269 let Predicates = [UseSSE2] in {
1270 // Shuffle with MOVLPD
1271 def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1272 (MOVLPDrm VR128:$src1, addr:$src2)>;
1273 def : Pat<(v2i64 (X86Movlpd VR128:$src1, (load addr:$src2))),
1274 (MOVLPDrm VR128:$src1, addr:$src2)>;
1275 def : Pat<(v2f64 (X86Movsd VR128:$src1,
1276 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
1277 (MOVLPDrm VR128:$src1, addr:$src2)>;
1280 def : Pat<(store (v2f64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1282 (MOVLPDmr addr:$src1, VR128:$src2)>;
1283 def : Pat<(store (v2i64 (X86Movlpd (load addr:$src1), VR128:$src2)),
1285 (MOVLPDmr addr:$src1, VR128:$src2)>;
1288 //===----------------------------------------------------------------------===//
1289 // SSE 1 & 2 - Move Hi packed FP Instructions
1290 //===----------------------------------------------------------------------===//
1292 let AddedComplexity = 20 in {
1293 defm MOVH : sse12_mov_hilo_packed<0x16, X86Movlhps, X86Movlhpd, "movhp",
1297 let SchedRW = [WriteStore] in {
1298 // v2f64 extract element 1 is always custom lowered to unpack high to low
1299 // and extract element 0 so the non-store version isn't too horrible.
1300 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1301 "movhps\t{$src, $dst|$dst, $src}",
1302 [(store (f64 (vector_extract
1303 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1304 (bc_v2f64 (v4f32 VR128:$src))),
1305 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1306 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1307 "movhpd\t{$src, $dst|$dst, $src}",
1308 [(store (f64 (vector_extract
1309 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1310 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>, VEX;
1311 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1312 "movhps\t{$src, $dst|$dst, $src}",
1313 [(store (f64 (vector_extract
1314 (X86Unpckh (bc_v2f64 (v4f32 VR128:$src)),
1315 (bc_v2f64 (v4f32 VR128:$src))),
1316 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1317 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1318 "movhpd\t{$src, $dst|$dst, $src}",
1319 [(store (f64 (vector_extract
1320 (v2f64 (X86Unpckh VR128:$src, VR128:$src)),
1321 (iPTR 0))), addr:$dst)], IIC_SSE_MOV_LH>;
1324 let Predicates = [HasAVX] in {
1326 def : Pat<(X86Movlhps VR128:$src1,
1327 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1328 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1329 def : Pat<(X86Movlhps VR128:$src1,
1330 (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
1331 (VMOVHPSrm VR128:$src1, addr:$src2)>;
1335 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1336 // is during lowering, where it's not possible to recognize the load fold
1337 // cause it has two uses through a bitcast. One use disappears at isel time
1338 // and the fold opportunity reappears.
1339 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1340 (scalar_to_vector (loadf64 addr:$src2)))),
1341 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1342 // Also handle an i64 load because that may get selected as a faster way to
1344 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1345 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1346 (VMOVHPDrm VR128:$src1, addr:$src2)>;
1348 def : Pat<(store (f64 (vector_extract
1349 (v2f64 (X86VPermilpi VR128:$src, (i8 1))),
1350 (iPTR 0))), addr:$dst),
1351 (VMOVHPDmr addr:$dst, VR128:$src)>;
1354 let Predicates = [UseSSE1] in {
1356 def : Pat<(X86Movlhps VR128:$src1,
1357 (bc_v4f32 (v2i64 (scalar_to_vector (loadi64 addr:$src2))))),
1358 (MOVHPSrm VR128:$src1, addr:$src2)>;
1359 def : Pat<(X86Movlhps VR128:$src1,
1360 (bc_v4f32 (v2i64 (X86vzload addr:$src2)))),
1361 (MOVHPSrm VR128:$src1, addr:$src2)>;
1364 let Predicates = [UseSSE2] in {
1367 // FIXME: Instead of X86Unpckl, there should be a X86Movlhpd here, the problem
1368 // is during lowering, where it's not possible to recognize the load fold
1369 // cause it has two uses through a bitcast. One use disappears at isel time
1370 // and the fold opportunity reappears.
1371 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1372 (scalar_to_vector (loadf64 addr:$src2)))),
1373 (MOVHPDrm VR128:$src1, addr:$src2)>;
1374 // Also handle an i64 load because that may get selected as a faster way to
1376 def : Pat<(v2f64 (X86Unpckl VR128:$src1,
1377 (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src2)))))),
1378 (MOVHPDrm VR128:$src1, addr:$src2)>;
1380 def : Pat<(store (f64 (vector_extract
1381 (v2f64 (X86Shufp VR128:$src, VR128:$src, (i8 1))),
1382 (iPTR 0))), addr:$dst),
1383 (MOVHPDmr addr:$dst, VR128:$src)>;
1386 //===----------------------------------------------------------------------===//
1387 // SSE 1 & 2 - Move Low to High and High to Low packed FP Instructions
1388 //===----------------------------------------------------------------------===//
1390 let AddedComplexity = 20, Predicates = [UseAVX] in {
1391 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
1392 (ins VR128:$src1, VR128:$src2),
1393 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1395 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1397 VEX_4V, Sched<[WriteFShuffle]>;
1398 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
1399 (ins VR128:$src1, VR128:$src2),
1400 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1402 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1404 VEX_4V, Sched<[WriteFShuffle]>;
1406 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
1407 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
1408 (ins VR128:$src1, VR128:$src2),
1409 "movlhps\t{$src2, $dst|$dst, $src2}",
1411 (v4f32 (X86Movlhps VR128:$src1, VR128:$src2)))],
1412 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1413 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
1414 (ins VR128:$src1, VR128:$src2),
1415 "movhlps\t{$src2, $dst|$dst, $src2}",
1417 (v4f32 (X86Movhlps VR128:$src1, VR128:$src2)))],
1418 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
1421 let Predicates = [UseAVX] in {
1423 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1424 (VMOVLHPSrr VR128:$src1, VR128:$src2)>;
1425 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1426 (VMOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1429 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1430 (VMOVHLPSrr VR128:$src1, VR128:$src2)>;
1433 let Predicates = [UseSSE1] in {
1435 def : Pat<(v4i32 (X86Movlhps VR128:$src1, VR128:$src2)),
1436 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
1437 def : Pat<(v2i64 (X86Movlhps VR128:$src1, VR128:$src2)),
1438 (MOVLHPSrr (v2i64 VR128:$src1), VR128:$src2)>;
1441 def : Pat<(v4i32 (X86Movhlps VR128:$src1, VR128:$src2)),
1442 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
1445 //===----------------------------------------------------------------------===//
1446 // SSE 1 & 2 - Conversion Instructions
1447 //===----------------------------------------------------------------------===//
1449 def SSE_CVT_PD : OpndItins<
1450 IIC_SSE_CVT_PD_RR, IIC_SSE_CVT_PD_RM
1453 let Sched = WriteCvtI2F in
1454 def SSE_CVT_PS : OpndItins<
1455 IIC_SSE_CVT_PS_RR, IIC_SSE_CVT_PS_RM
1458 let Sched = WriteCvtI2F in
1459 def SSE_CVT_Scalar : OpndItins<
1460 IIC_SSE_CVT_Scalar_RR, IIC_SSE_CVT_Scalar_RM
1463 let Sched = WriteCvtF2I in
1464 def SSE_CVT_SS2SI_32 : OpndItins<
1465 IIC_SSE_CVT_SS2SI32_RR, IIC_SSE_CVT_SS2SI32_RM
1468 let Sched = WriteCvtF2I in
1469 def SSE_CVT_SS2SI_64 : OpndItins<
1470 IIC_SSE_CVT_SS2SI64_RR, IIC_SSE_CVT_SS2SI64_RM
1473 let Sched = WriteCvtF2I in
1474 def SSE_CVT_SD2SI : OpndItins<
1475 IIC_SSE_CVT_SD2SI_RR, IIC_SSE_CVT_SD2SI_RM
1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1479 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
1480 string asm, OpndItins itins> {
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1483 itins.rr>, Sched<[itins.Sched]>;
1484 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1485 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))],
1486 itins.rm>, Sched<[itins.Sched.Folded]>;
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1490 X86MemOperand x86memop, string asm, Domain d,
1492 let hasSideEffects = 0 in {
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1494 [], itins.rr, d>, Sched<[itins.Sched]>;
1496 def rm : I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
1497 [], itins.rm, d>, Sched<[itins.Sched.Folded]>;
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1502 X86MemOperand x86memop, string asm> {
1503 let hasSideEffects = 0, Predicates = [UseAVX] in {
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1505 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1506 Sched<[WriteCvtI2F]>;
1508 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1509 (ins DstRC:$src1, x86memop:$src),
1510 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
1511 Sched<[WriteCvtI2FLd, ReadAfterLd]>;
1512 } // hasSideEffects = 0
1515 let Predicates = [UseAVX] in {
1516 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1517 "cvttss2si\t{$src, $dst|$dst, $src}",
1520 defm VCVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1521 "cvttss2si\t{$src, $dst|$dst, $src}",
1523 XS, VEX, VEX_W, VEX_LIG;
1524 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1525 "cvttsd2si\t{$src, $dst|$dst, $src}",
1528 defm VCVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1529 "cvttsd2si\t{$src, $dst|$dst, $src}",
1531 XD, VEX, VEX_W, VEX_LIG;
1533 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1534 (VCVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1535 def : InstAlias<"vcvttss2si{l}\t{$src, $dst|$dst, $src}",
1536 (VCVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1537 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1538 (VCVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1539 def : InstAlias<"vcvttsd2si{l}\t{$src, $dst|$dst, $src}",
1540 (VCVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1541 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1542 (VCVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1543 def : InstAlias<"vcvttss2si{q}\t{$src, $dst|$dst, $src}",
1544 (VCVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1545 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1546 (VCVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1547 def : InstAlias<"vcvttsd2si{q}\t{$src, $dst|$dst, $src}",
1548 (VCVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1550 // The assembler can recognize rr 64-bit instructions by seeing a rxx
1551 // register, but the same isn't true when only using memory operands,
1552 // provide other assembly "l" and "q" forms to address this explicitly
1553 // where appropriate to do so.
1554 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, i32mem, "cvtsi2ss{l}">,
1555 XS, VEX_4V, VEX_LIG;
1556 defm VCVTSI2SS64 : sse12_vcvt_avx<0x2A, GR64, FR32, i64mem, "cvtsi2ss{q}">,
1557 XS, VEX_4V, VEX_W, VEX_LIG;
1558 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, i32mem, "cvtsi2sd{l}">,
1559 XD, VEX_4V, VEX_LIG;
1560 defm VCVTSI2SD64 : sse12_vcvt_avx<0x2A, GR64, FR64, i64mem, "cvtsi2sd{q}">,
1561 XD, VEX_4V, VEX_W, VEX_LIG;
1563 let Predicates = [UseAVX] in {
1564 def : InstAlias<"vcvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1565 (VCVTSI2SSrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1566 def : InstAlias<"vcvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1567 (VCVTSI2SDrm FR64:$dst, FR64:$src1, i32mem:$src), 0>;
1569 def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1571 def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1573 def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1575 def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
1578 def : Pat<(f32 (sint_to_fp GR32:$src)),
1579 (VCVTSI2SSrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
1580 def : Pat<(f32 (sint_to_fp GR64:$src)),
1581 (VCVTSI2SS64rr (f32 (IMPLICIT_DEF)), GR64:$src)>;
1582 def : Pat<(f64 (sint_to_fp GR32:$src)),
1583 (VCVTSI2SDrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
1584 def : Pat<(f64 (sint_to_fp GR64:$src)),
1585 (VCVTSI2SD64rr (f64 (IMPLICIT_DEF)), GR64:$src)>;
1588 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
1589 "cvttss2si\t{$src, $dst|$dst, $src}",
1590 SSE_CVT_SS2SI_32>, XS;
1591 defm CVTTSS2SI64 : sse12_cvt_s<0x2C, FR32, GR64, fp_to_sint, f32mem, loadf32,
1592 "cvttss2si\t{$src, $dst|$dst, $src}",
1593 SSE_CVT_SS2SI_64>, XS, REX_W;
1594 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
1595 "cvttsd2si\t{$src, $dst|$dst, $src}",
1597 defm CVTTSD2SI64 : sse12_cvt_s<0x2C, FR64, GR64, fp_to_sint, f64mem, loadf64,
1598 "cvttsd2si\t{$src, $dst|$dst, $src}",
1599 SSE_CVT_SD2SI>, XD, REX_W;
1600 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
1601 "cvtsi2ss{l}\t{$src, $dst|$dst, $src}",
1602 SSE_CVT_Scalar>, XS;
1603 defm CVTSI2SS64 : sse12_cvt_s<0x2A, GR64, FR32, sint_to_fp, i64mem, loadi64,
1604 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1605 SSE_CVT_Scalar>, XS, REX_W;
1606 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
1607 "cvtsi2sd{l}\t{$src, $dst|$dst, $src}",
1608 SSE_CVT_Scalar>, XD;
1609 defm CVTSI2SD64 : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64,
1610 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1611 SSE_CVT_Scalar>, XD, REX_W;
1613 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1614 (CVTTSS2SIrr GR32:$dst, FR32:$src), 0>;
1615 def : InstAlias<"cvttss2si{l}\t{$src, $dst|$dst, $src}",
1616 (CVTTSS2SIrm GR32:$dst, f32mem:$src), 0>;
1617 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1618 (CVTTSD2SIrr GR32:$dst, FR64:$src), 0>;
1619 def : InstAlias<"cvttsd2si{l}\t{$src, $dst|$dst, $src}",
1620 (CVTTSD2SIrm GR32:$dst, f64mem:$src), 0>;
1621 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1622 (CVTTSS2SI64rr GR64:$dst, FR32:$src), 0>;
1623 def : InstAlias<"cvttss2si{q}\t{$src, $dst|$dst, $src}",
1624 (CVTTSS2SI64rm GR64:$dst, f32mem:$src), 0>;
1625 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1626 (CVTTSD2SI64rr GR64:$dst, FR64:$src), 0>;
1627 def : InstAlias<"cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1628 (CVTTSD2SI64rm GR64:$dst, f64mem:$src), 0>;
1630 def : InstAlias<"cvtsi2ss\t{$src, $dst|$dst, $src}",
1631 (CVTSI2SSrm FR64:$dst, i32mem:$src), 0>;
1632 def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}",
1633 (CVTSI2SDrm FR64:$dst, i32mem:$src), 0>;
1635 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
1636 // and/or XMM operand(s).
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1639 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
1640 string asm, OpndItins itins> {
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1642 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
1644 Sched<[itins.Sched]>;
1645 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
1646 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1647 [(set DstRC:$dst, (Int mem_cpat:$src))], itins.rm>,
1648 Sched<[itins.Sched.Folded]>;
1651 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
1652 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
1653 PatFrag ld_frag, string asm, OpndItins itins,
1655 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
1657 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1658 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1659 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
1660 itins.rr>, Sched<[itins.Sched]>;
1661 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
1662 (ins DstRC:$src1, x86memop:$src2),
1664 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
1665 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
1666 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))],
1667 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
1670 let Predicates = [UseAVX] in {
1671 defm VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32,
1672 int_x86_sse2_cvtsd2si, sdmem, sse_load_f64, "cvtsd2si",
1673 SSE_CVT_SD2SI>, XD, VEX, VEX_LIG;
1674 defm VCVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64,
1675 int_x86_sse2_cvtsd2si64, sdmem, sse_load_f64, "cvtsd2si",
1676 SSE_CVT_SD2SI>, XD, VEX, VEX_W, VEX_LIG;
1678 defm CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
1679 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD;
1680 defm CVTSD2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse2_cvtsd2si64,
1681 sdmem, sse_load_f64, "cvtsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1684 let isCodeGenOnly = 1 in {
1685 let Predicates = [UseAVX] in {
1686 defm Int_VCVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1687 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
1688 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1689 defm Int_VCVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1690 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
1691 SSE_CVT_Scalar, 0>, XS, VEX_4V,
1693 defm Int_VCVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1694 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
1695 SSE_CVT_Scalar, 0>, XD, VEX_4V;
1696 defm Int_VCVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1697 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
1698 SSE_CVT_Scalar, 0>, XD,
1701 let Constraints = "$src1 = $dst" in {
1702 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1703 int_x86_sse_cvtsi2ss, i32mem, loadi32,
1704 "cvtsi2ss{l}", SSE_CVT_Scalar>, XS;
1705 defm Int_CVTSI2SS64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1706 int_x86_sse_cvtsi642ss, i64mem, loadi64,
1707 "cvtsi2ss{q}", SSE_CVT_Scalar>, XS, REX_W;
1708 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
1709 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
1710 "cvtsi2sd{l}", SSE_CVT_Scalar>, XD;
1711 defm Int_CVTSI2SD64 : sse12_cvt_sint_3addr<0x2A, GR64, VR128,
1712 int_x86_sse2_cvtsi642sd, i64mem, loadi64,
1713 "cvtsi2sd{q}", SSE_CVT_Scalar>, XD, REX_W;
1715 } // isCodeGenOnly = 1
1719 // Aliases for intrinsics
1720 let isCodeGenOnly = 1 in {
1721 let Predicates = [UseAVX] in {
1722 defm Int_VCVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1723 ssmem, sse_load_f32, "cvttss2si",
1724 SSE_CVT_SS2SI_32>, XS, VEX;
1725 defm Int_VCVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1726 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1727 "cvttss2si", SSE_CVT_SS2SI_64>,
1729 defm Int_VCVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1730 sdmem, sse_load_f64, "cvttsd2si",
1731 SSE_CVT_SD2SI>, XD, VEX;
1732 defm Int_VCVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1733 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1734 "cvttsd2si", SSE_CVT_SD2SI>,
1737 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
1738 ssmem, sse_load_f32, "cvttss2si",
1739 SSE_CVT_SS2SI_32>, XS;
1740 defm Int_CVTTSS2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1741 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
1742 "cvttss2si", SSE_CVT_SS2SI_64>, XS, REX_W;
1743 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
1744 sdmem, sse_load_f64, "cvttsd2si",
1746 defm Int_CVTTSD2SI64 : sse12_cvt_sint<0x2C, VR128, GR64,
1747 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
1748 "cvttsd2si", SSE_CVT_SD2SI>, XD, REX_W;
1749 } // isCodeGenOnly = 1
1751 let Predicates = [UseAVX] in {
1752 defm VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1753 ssmem, sse_load_f32, "cvtss2si",
1754 SSE_CVT_SS2SI_32>, XS, VEX, VEX_LIG;
1755 defm VCVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1756 ssmem, sse_load_f32, "cvtss2si",
1757 SSE_CVT_SS2SI_64>, XS, VEX, VEX_W, VEX_LIG;
1759 defm CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
1760 ssmem, sse_load_f32, "cvtss2si",
1761 SSE_CVT_SS2SI_32>, XS;
1762 defm CVTSS2SI64 : sse12_cvt_sint<0x2D, VR128, GR64, int_x86_sse_cvtss2si64,
1763 ssmem, sse_load_f32, "cvtss2si",
1764 SSE_CVT_SS2SI_64>, XS, REX_W;
1766 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1767 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1768 SSEPackedSingle, SSE_CVT_PS>,
1769 PS, VEX, Requires<[HasAVX]>;
1770 defm VCVTDQ2PSY : sse12_cvt_p<0x5B, VR256, VR256, i256mem,
1771 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
1772 SSEPackedSingle, SSE_CVT_PS>,
1773 PS, VEX, VEX_L, Requires<[HasAVX]>;
1775 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, i128mem,
1776 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1777 SSEPackedSingle, SSE_CVT_PS>,
1778 PS, Requires<[UseSSE2]>;
1780 let Predicates = [UseAVX] in {
1781 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1782 (VCVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1783 def : InstAlias<"vcvtss2si{l}\t{$src, $dst|$dst, $src}",
1784 (VCVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1785 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1786 (VCVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1787 def : InstAlias<"vcvtsd2si{l}\t{$src, $dst|$dst, $src}",
1788 (VCVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1789 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1790 (VCVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1791 def : InstAlias<"vcvtss2si{q}\t{$src, $dst|$dst, $src}",
1792 (VCVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1793 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1794 (VCVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1795 def : InstAlias<"vcvtsd2si{q}\t{$src, $dst|$dst, $src}",
1796 (VCVTSD2SI64rm GR64:$dst, sdmem:$src), 0>;
1799 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1800 (CVTSS2SIrr GR32:$dst, VR128:$src), 0>;
1801 def : InstAlias<"cvtss2si{l}\t{$src, $dst|$dst, $src}",
1802 (CVTSS2SIrm GR32:$dst, ssmem:$src), 0>;
1803 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1804 (CVTSD2SIrr GR32:$dst, VR128:$src), 0>;
1805 def : InstAlias<"cvtsd2si{l}\t{$src, $dst|$dst, $src}",
1806 (CVTSD2SIrm GR32:$dst, sdmem:$src), 0>;
1807 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1808 (CVTSS2SI64rr GR64:$dst, VR128:$src), 0>;
1809 def : InstAlias<"cvtss2si{q}\t{$src, $dst|$dst, $src}",
1810 (CVTSS2SI64rm GR64:$dst, ssmem:$src), 0>;
1811 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1812 (CVTSD2SI64rr GR64:$dst, VR128:$src), 0>;
1813 def : InstAlias<"cvtsd2si{q}\t{$src, $dst|$dst, $src}",
1814 (CVTSD2SI64rm GR64:$dst, sdmem:$src)>;
1818 // Convert scalar double to scalar single
1819 let hasSideEffects = 0, Predicates = [UseAVX] in {
1820 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
1821 (ins FR64:$src1, FR64:$src2),
1822 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1823 IIC_SSE_CVT_Scalar_RR>, VEX_4V, VEX_LIG,
1824 Sched<[WriteCvtF2F]>;
1826 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
1827 (ins FR64:$src1, f64mem:$src2),
1828 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1829 [], IIC_SSE_CVT_Scalar_RM>,
1830 XD, Requires<[HasAVX, OptForSize]>, VEX_4V, VEX_LIG,
1831 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1834 def : Pat<(f32 (fround FR64:$src)), (VCVTSD2SSrr FR64:$src, FR64:$src)>,
1837 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1838 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1839 [(set FR32:$dst, (fround FR64:$src))],
1840 IIC_SSE_CVT_Scalar_RR>, Sched<[WriteCvtF2F]>;
1841 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1842 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1843 [(set FR32:$dst, (fround (loadf64 addr:$src)))],
1844 IIC_SSE_CVT_Scalar_RM>,
1846 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1848 let isCodeGenOnly = 1 in {
1849 def Int_VCVTSD2SSrr: I<0x5A, MRMSrcReg,
1850 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1851 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1853 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1854 IIC_SSE_CVT_Scalar_RR>, XD, VEX_4V, Requires<[UseAVX]>,
1855 Sched<[WriteCvtF2F]>;
1856 def Int_VCVTSD2SSrm: I<0x5A, MRMSrcReg,
1857 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1858 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1859 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1860 VR128:$src1, sse_load_f64:$src2))],
1861 IIC_SSE_CVT_Scalar_RM>, XD, VEX_4V, Requires<[UseAVX]>,
1862 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1864 let Constraints = "$src1 = $dst" in {
1865 def Int_CVTSD2SSrr: I<0x5A, MRMSrcReg,
1866 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1867 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1869 (int_x86_sse2_cvtsd2ss VR128:$src1, VR128:$src2))],
1870 IIC_SSE_CVT_Scalar_RR>, XD, Requires<[UseSSE2]>,
1871 Sched<[WriteCvtF2F]>;
1872 def Int_CVTSD2SSrm: I<0x5A, MRMSrcReg,
1873 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1874 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1875 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss
1876 VR128:$src1, sse_load_f64:$src2))],
1877 IIC_SSE_CVT_Scalar_RM>, XD, Requires<[UseSSE2]>,
1878 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1880 } // isCodeGenOnly = 1
1882 // Convert scalar single to scalar double
1883 // SSE2 instructions with XS prefix
1884 let hasSideEffects = 0, Predicates = [UseAVX] in {
1885 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
1886 (ins FR32:$src1, FR32:$src2),
1887 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1888 [], IIC_SSE_CVT_Scalar_RR>,
1889 XS, Requires<[HasAVX]>, VEX_4V, VEX_LIG,
1890 Sched<[WriteCvtF2F]>;
1892 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
1893 (ins FR32:$src1, f32mem:$src2),
1894 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1895 [], IIC_SSE_CVT_Scalar_RM>,
1896 XS, VEX_4V, VEX_LIG, Requires<[HasAVX, OptForSize]>,
1897 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1900 def : Pat<(f64 (fextend FR32:$src)),
1901 (VCVTSS2SDrr FR32:$src, FR32:$src)>, Requires<[UseAVX]>;
1902 def : Pat<(fextend (loadf32 addr:$src)),
1903 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[UseAVX]>;
1905 def : Pat<(extloadf32 addr:$src),
1906 (VCVTSS2SDrm (f32 (IMPLICIT_DEF)), addr:$src)>,
1907 Requires<[UseAVX, OptForSize]>;
1908 def : Pat<(extloadf32 addr:$src),
1909 (VCVTSS2SDrr (f32 (IMPLICIT_DEF)), (VMOVSSrm addr:$src))>,
1910 Requires<[UseAVX, OptForSpeed]>;
1912 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1913 "cvtss2sd\t{$src, $dst|$dst, $src}",
1914 [(set FR64:$dst, (fextend FR32:$src))],
1915 IIC_SSE_CVT_Scalar_RR>, XS,
1916 Requires<[UseSSE2]>, Sched<[WriteCvtF2F]>;
1917 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1918 "cvtss2sd\t{$src, $dst|$dst, $src}",
1919 [(set FR64:$dst, (extloadf32 addr:$src))],
1920 IIC_SSE_CVT_Scalar_RM>, XS,
1921 Requires<[UseSSE2, OptForSize]>, Sched<[WriteCvtF2FLd]>;
1923 // extload f32 -> f64. This matches load+fextend because we have a hack in
1924 // the isel (PreprocessForFPConvert) that can introduce loads after dag
1926 // Since these loads aren't folded into the fextend, we have to match it
1928 def : Pat<(fextend (loadf32 addr:$src)),
1929 (CVTSS2SDrm addr:$src)>, Requires<[UseSSE2]>;
1930 def : Pat<(extloadf32 addr:$src),
1931 (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[UseSSE2, OptForSpeed]>;
1933 let isCodeGenOnly = 1 in {
1934 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
1935 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1936 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1938 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1939 IIC_SSE_CVT_Scalar_RR>, XS, VEX_4V, Requires<[UseAVX]>,
1940 Sched<[WriteCvtF2F]>;
1941 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
1942 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1943 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1945 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1946 IIC_SSE_CVT_Scalar_RM>, XS, VEX_4V, Requires<[UseAVX]>,
1947 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
1949 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1950 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1951 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1953 (int_x86_sse2_cvtss2sd VR128:$src1, VR128:$src2))],
1954 IIC_SSE_CVT_Scalar_RR>, XS, Requires<[UseSSE2]>,
1955 Sched<[WriteCvtF2F]>;
1956 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1957 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
1958 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1960 (int_x86_sse2_cvtss2sd VR128:$src1, sse_load_f32:$src2))],
1961 IIC_SSE_CVT_Scalar_RM>, XS, Requires<[UseSSE2]>,
1962 Sched<[WriteCvtF2FLd, ReadAfterLd]>;
1964 } // isCodeGenOnly = 1
1966 // Convert packed single/double fp to doubleword
1967 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1968 "cvtps2dq\t{$src, $dst|$dst, $src}",
1969 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1970 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
1971 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1972 "cvtps2dq\t{$src, $dst|$dst, $src}",
1974 (int_x86_sse2_cvtps2dq (loadv4f32 addr:$src)))],
1975 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
1976 def VCVTPS2DQYrr : VPDI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1977 "cvtps2dq\t{$src, $dst|$dst, $src}",
1979 (int_x86_avx_cvt_ps2dq_256 VR256:$src))],
1980 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
1981 def VCVTPS2DQYrm : VPDI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1982 "cvtps2dq\t{$src, $dst|$dst, $src}",
1984 (int_x86_avx_cvt_ps2dq_256 (loadv8f32 addr:$src)))],
1985 IIC_SSE_CVT_PS_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
1986 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1987 "cvtps2dq\t{$src, $dst|$dst, $src}",
1988 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))],
1989 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
1990 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1991 "cvtps2dq\t{$src, $dst|$dst, $src}",
1993 (int_x86_sse2_cvtps2dq (memopv4f32 addr:$src)))],
1994 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
1997 // Convert Packed Double FP to Packed DW Integers
1998 let Predicates = [HasAVX] in {
1999 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2000 // register, but the same isn't true when using memory operands instead.
2001 // Provide other assembly rr and rm forms to address this explicitly.
2002 def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2003 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
2004 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
2005 VEX, Sched<[WriteCvtF2I]>;
2008 def : InstAlias<"vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2009 (VCVTPD2DQrr VR128:$dst, VR128:$src), 0>;
2010 def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2011 "vcvtpd2dqx\t{$src, $dst|$dst, $src}",
2013 (int_x86_sse2_cvtpd2dq (loadv2f64 addr:$src)))]>, VEX,
2014 Sched<[WriteCvtF2ILd]>;
2017 def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2018 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2020 (int_x86_avx_cvt_pd2dq_256 VR256:$src))]>, VEX, VEX_L,
2021 Sched<[WriteCvtF2I]>;
2022 def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2023 "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}",
2025 (int_x86_avx_cvt_pd2dq_256 (loadv4f64 addr:$src)))]>,
2026 VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2027 def : InstAlias<"vcvtpd2dq\t{$src, $dst|$dst, $src}",
2028 (VCVTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2031 def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2032 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2034 (int_x86_sse2_cvtpd2dq (memopv2f64 addr:$src)))],
2035 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2ILd]>;
2036 def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2037 "cvtpd2dq\t{$src, $dst|$dst, $src}",
2038 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))],
2039 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2041 // Convert with truncation packed single/double fp to doubleword
2042 // SSE2 packed instructions with XS prefix
2043 def VCVTTPS2DQrr : VS2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2044 "cvttps2dq\t{$src, $dst|$dst, $src}",
2046 (int_x86_sse2_cvttps2dq VR128:$src))],
2047 IIC_SSE_CVT_PS_RR>, VEX, Sched<[WriteCvtF2I]>;
2048 def VCVTTPS2DQrm : VS2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2049 "cvttps2dq\t{$src, $dst|$dst, $src}",
2050 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
2051 (loadv4f32 addr:$src)))],
2052 IIC_SSE_CVT_PS_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2053 def VCVTTPS2DQYrr : VS2SI<0x5B, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
2054 "cvttps2dq\t{$src, $dst|$dst, $src}",
2056 (int_x86_avx_cvtt_ps2dq_256 VR256:$src))],
2057 IIC_SSE_CVT_PS_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2058 def VCVTTPS2DQYrm : VS2SI<0x5B, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
2059 "cvttps2dq\t{$src, $dst|$dst, $src}",
2060 [(set VR256:$dst, (int_x86_avx_cvtt_ps2dq_256
2061 (loadv8f32 addr:$src)))],
2062 IIC_SSE_CVT_PS_RM>, VEX, VEX_L,
2063 Sched<[WriteCvtF2ILd]>;
2065 def CVTTPS2DQrr : S2SI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2066 "cvttps2dq\t{$src, $dst|$dst, $src}",
2067 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))],
2068 IIC_SSE_CVT_PS_RR>, Sched<[WriteCvtF2I]>;
2069 def CVTTPS2DQrm : S2SI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2070 "cvttps2dq\t{$src, $dst|$dst, $src}",
2072 (int_x86_sse2_cvttps2dq (memopv4f32 addr:$src)))],
2073 IIC_SSE_CVT_PS_RM>, Sched<[WriteCvtF2ILd]>;
2075 let Predicates = [HasAVX] in {
2076 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2077 (VCVTDQ2PSrr VR128:$src)>;
2078 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2079 (VCVTDQ2PSrm addr:$src)>;
2081 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2082 (VCVTDQ2PSrr VR128:$src)>;
2083 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (loadv2i64 addr:$src))),
2084 (VCVTDQ2PSrm addr:$src)>;
2086 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2087 (VCVTTPS2DQrr VR128:$src)>;
2088 def : Pat<(v4i32 (fp_to_sint (loadv4f32 addr:$src))),
2089 (VCVTTPS2DQrm addr:$src)>;
2091 def : Pat<(v8f32 (sint_to_fp (v8i32 VR256:$src))),
2092 (VCVTDQ2PSYrr VR256:$src)>;
2093 def : Pat<(v8f32 (sint_to_fp (bc_v8i32 (loadv4i64 addr:$src)))),
2094 (VCVTDQ2PSYrm addr:$src)>;
2096 def : Pat<(v8i32 (fp_to_sint (v8f32 VR256:$src))),
2097 (VCVTTPS2DQYrr VR256:$src)>;
2098 def : Pat<(v8i32 (fp_to_sint (loadv8f32 addr:$src))),
2099 (VCVTTPS2DQYrm addr:$src)>;
2102 let Predicates = [UseSSE2] in {
2103 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2104 (CVTDQ2PSrr VR128:$src)>;
2105 def : Pat<(v4f32 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
2106 (CVTDQ2PSrm addr:$src)>;
2108 def : Pat<(int_x86_sse2_cvtdq2ps VR128:$src),
2109 (CVTDQ2PSrr VR128:$src)>;
2110 def : Pat<(int_x86_sse2_cvtdq2ps (bc_v4i32 (memopv2i64 addr:$src))),
2111 (CVTDQ2PSrm addr:$src)>;
2113 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2114 (CVTTPS2DQrr VR128:$src)>;
2115 def : Pat<(v4i32 (fp_to_sint (memopv4f32 addr:$src))),
2116 (CVTTPS2DQrm addr:$src)>;
2119 def VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2120 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2122 (int_x86_sse2_cvttpd2dq VR128:$src))],
2123 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2I]>;
2125 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2126 // register, but the same isn't true when using memory operands instead.
2127 // Provide other assembly rr and rm forms to address this explicitly.
2130 def : InstAlias<"vcvttpd2dqx\t{$src, $dst|$dst, $src}",
2131 (VCVTTPD2DQrr VR128:$dst, VR128:$src), 0>;
2132 def VCVTTPD2DQXrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2133 "cvttpd2dqx\t{$src, $dst|$dst, $src}",
2134 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2135 (loadv2f64 addr:$src)))],
2136 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2ILd]>;
2139 def VCVTTPD2DQYrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2140 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2142 (int_x86_avx_cvtt_pd2dq_256 VR256:$src))],
2143 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2I]>;
2144 def VCVTTPD2DQYrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2145 "cvttpd2dq{y}\t{$src, $dst|$dst, $src}",
2147 (int_x86_avx_cvtt_pd2dq_256 (loadv4f64 addr:$src)))],
2148 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2ILd]>;
2149 def : InstAlias<"vcvttpd2dq\t{$src, $dst|$dst, $src}",
2150 (VCVTTPD2DQYrr VR128:$dst, VR256:$src), 0>;
2152 let Predicates = [HasAVX] in {
2153 def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
2154 (VCVTTPD2DQYrr VR256:$src)>;
2155 def : Pat<(v4i32 (fp_to_sint (loadv4f64 addr:$src))),
2156 (VCVTTPD2DQYrm addr:$src)>;
2157 } // Predicates = [HasAVX]
2159 def CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2160 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2161 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))],
2162 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2I]>;
2163 def CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
2164 "cvttpd2dq\t{$src, $dst|$dst, $src}",
2165 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
2166 (memopv2f64 addr:$src)))],
2168 Sched<[WriteCvtF2ILd]>;
2170 // Convert packed single to packed double
2171 let Predicates = [HasAVX] in {
2172 // SSE2 instructions without OpSize prefix
2173 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2174 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2175 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2176 IIC_SSE_CVT_PD_RR>, PS, VEX, Sched<[WriteCvtF2F]>;
2177 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2178 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2179 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2180 IIC_SSE_CVT_PD_RM>, PS, VEX, Sched<[WriteCvtF2FLd]>;
2181 def VCVTPS2PDYrr : I<0x5A, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2182 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2184 (int_x86_avx_cvt_ps2_pd_256 VR128:$src))],
2185 IIC_SSE_CVT_PD_RR>, PS, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2186 def VCVTPS2PDYrm : I<0x5A, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
2187 "vcvtps2pd\t{$src, $dst|$dst, $src}",
2189 (int_x86_avx_cvt_ps2_pd_256 (loadv4f32 addr:$src)))],
2190 IIC_SSE_CVT_PD_RM>, PS, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2193 let Predicates = [UseSSE2] in {
2194 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2195 "cvtps2pd\t{$src, $dst|$dst, $src}",
2196 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))],
2197 IIC_SSE_CVT_PD_RR>, PS, Sched<[WriteCvtF2F]>;
2198 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2199 "cvtps2pd\t{$src, $dst|$dst, $src}",
2200 [(set VR128:$dst, (v2f64 (extloadv2f32 addr:$src)))],
2201 IIC_SSE_CVT_PD_RM>, PS, Sched<[WriteCvtF2FLd]>;
2204 // Convert Packed DW Integers to Packed Double FP
2205 let Predicates = [HasAVX] in {
2206 let hasSideEffects = 0, mayLoad = 1 in
2207 def VCVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2208 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2209 []>, VEX, Sched<[WriteCvtI2FLd]>;
2210 def VCVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2211 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2213 (int_x86_sse2_cvtdq2pd VR128:$src))]>, VEX,
2214 Sched<[WriteCvtI2F]>;
2215 def VCVTDQ2PDYrm : S2SI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins i128mem:$src),
2216 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2218 (int_x86_avx_cvtdq2_pd_256
2219 (bitconvert (loadv2i64 addr:$src))))]>, VEX, VEX_L,
2220 Sched<[WriteCvtI2FLd]>;
2221 def VCVTDQ2PDYrr : S2SI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
2222 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
2224 (int_x86_avx_cvtdq2_pd_256 VR128:$src))]>, VEX, VEX_L,
2225 Sched<[WriteCvtI2F]>;
2228 let hasSideEffects = 0, mayLoad = 1 in
2229 def CVTDQ2PDrm : S2SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2230 "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
2231 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtI2FLd]>;
2232 def CVTDQ2PDrr : S2SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2233 "cvtdq2pd\t{$src, $dst|$dst, $src}",
2234 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))],
2235 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtI2F]>;
2237 // AVX 256-bit register conversion intrinsics
2238 let Predicates = [HasAVX] in {
2239 def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
2240 (VCVTDQ2PDYrr VR128:$src)>;
2241 def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (loadv2i64 addr:$src)))),
2242 (VCVTDQ2PDYrm addr:$src)>;
2243 } // Predicates = [HasAVX]
2245 // Convert packed double to packed single
2246 // The assembler can recognize rr 256-bit instructions by seeing a ymm
2247 // register, but the same isn't true when using memory operands instead.
2248 // Provide other assembly rr and rm forms to address this explicitly.
2249 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2250 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2251 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2252 IIC_SSE_CVT_PD_RR>, VEX, Sched<[WriteCvtF2F]>;
2255 def : InstAlias<"vcvtpd2psx\t{$src, $dst|$dst, $src}",
2256 (VCVTPD2PSrr VR128:$dst, VR128:$src), 0>;
2257 def VCVTPD2PSXrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2258 "cvtpd2psx\t{$src, $dst|$dst, $src}",
2260 (int_x86_sse2_cvtpd2ps (loadv2f64 addr:$src)))],
2261 IIC_SSE_CVT_PD_RM>, VEX, Sched<[WriteCvtF2FLd]>;
2264 def VCVTPD2PSYrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR256:$src),
2265 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2267 (int_x86_avx_cvt_pd2_ps_256 VR256:$src))],
2268 IIC_SSE_CVT_PD_RR>, VEX, VEX_L, Sched<[WriteCvtF2F]>;
2269 def VCVTPD2PSYrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f256mem:$src),
2270 "cvtpd2ps{y}\t{$src, $dst|$dst, $src}",
2272 (int_x86_avx_cvt_pd2_ps_256 (loadv4f64 addr:$src)))],
2273 IIC_SSE_CVT_PD_RM>, VEX, VEX_L, Sched<[WriteCvtF2FLd]>;
2274 def : InstAlias<"vcvtpd2ps\t{$src, $dst|$dst, $src}",
2275 (VCVTPD2PSYrr VR128:$dst, VR256:$src), 0>;
2277 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2278 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2279 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))],
2280 IIC_SSE_CVT_PD_RR>, Sched<[WriteCvtF2F]>;
2281 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2282 "cvtpd2ps\t{$src, $dst|$dst, $src}",
2284 (int_x86_sse2_cvtpd2ps (memopv2f64 addr:$src)))],
2285 IIC_SSE_CVT_PD_RM>, Sched<[WriteCvtF2FLd]>;
2288 // AVX 256-bit register conversion intrinsics
2289 // FIXME: Migrate SSE conversion intrinsics matching to use patterns as below
2290 // whenever possible to avoid declaring two versions of each one.
2291 let Predicates = [HasAVX] in {
2292 def : Pat<(int_x86_avx_cvtdq2_ps_256 VR256:$src),
2293 (VCVTDQ2PSYrr VR256:$src)>;
2294 def : Pat<(int_x86_avx_cvtdq2_ps_256 (bitconvert (loadv4i64 addr:$src))),
2295 (VCVTDQ2PSYrm addr:$src)>;
2297 // Match fround and fextend for 128/256-bit conversions
2298 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2299 (VCVTPD2PSrr VR128:$src)>;
2300 def : Pat<(v4f32 (X86vfpround (loadv2f64 addr:$src))),
2301 (VCVTPD2PSXrm addr:$src)>;
2302 def : Pat<(v4f32 (fround (v4f64 VR256:$src))),
2303 (VCVTPD2PSYrr VR256:$src)>;
2304 def : Pat<(v4f32 (fround (loadv4f64 addr:$src))),
2305 (VCVTPD2PSYrm addr:$src)>;
2307 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2308 (VCVTPS2PDrr VR128:$src)>;
2309 def : Pat<(v4f64 (fextend (v4f32 VR128:$src))),
2310 (VCVTPS2PDYrr VR128:$src)>;
2311 def : Pat<(v4f64 (extloadv4f32 addr:$src)),
2312 (VCVTPS2PDYrm addr:$src)>;
2315 let Predicates = [UseSSE2] in {
2316 // Match fround and fextend for 128 conversions
2317 def : Pat<(v4f32 (X86vfpround (v2f64 VR128:$src))),
2318 (CVTPD2PSrr VR128:$src)>;
2319 def : Pat<(v4f32 (X86vfpround (memopv2f64 addr:$src))),
2320 (CVTPD2PSrm addr:$src)>;
2322 def : Pat<(v2f64 (X86vfpext (v4f32 VR128:$src))),
2323 (CVTPS2PDrr VR128:$src)>;
2326 //===----------------------------------------------------------------------===//
2327 // SSE 1 & 2 - Compare Instructions
2328 //===----------------------------------------------------------------------===//
2330 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
2331 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
2332 Operand CC, SDNode OpNode, ValueType VT,
2333 PatFrag ld_frag, string asm, string asm_alt,
2334 OpndItins itins, ImmLeaf immLeaf> {
2335 def rr : SIi8<0xC2, MRMSrcReg,
2336 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2337 [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))],
2338 itins.rr>, Sched<[itins.Sched]>;
2339 def rm : SIi8<0xC2, MRMSrcMem,
2340 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2341 [(set RC:$dst, (OpNode (VT RC:$src1),
2342 (ld_frag addr:$src2), immLeaf:$cc))],
2344 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2346 // Accept explicit immediate argument form instead of comparison code.
2347 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2348 def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
2349 (ins RC:$src1, RC:$src2, u8imm:$cc), asm_alt, [],
2350 IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
2352 def rm_alt : SIi8<0xC2, MRMSrcMem, (outs RC:$dst),
2353 (ins RC:$src1, x86memop:$src2, u8imm:$cc), asm_alt, [],
2354 IIC_SSE_ALU_F32S_RM>,
2355 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2359 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
2360 "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2361 "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2362 SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG;
2363 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
2364 "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2365 "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2366 SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare
2367 XD, VEX_4V, VEX_LIG;
2369 let Constraints = "$src1 = $dst" in {
2370 defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
2371 "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
2372 "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S,
2374 defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
2375 "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
2376 "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2377 SSE_ALU_F64S, i8immZExt3>, XD;
2380 multiclass sse12_cmp_scalar_int<X86MemOperand x86memop, Operand CC,
2381 Intrinsic Int, string asm, OpndItins itins,
2383 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
2384 (ins VR128:$src1, VR128:$src, CC:$cc), asm,
2385 [(set VR128:$dst, (Int VR128:$src1,
2386 VR128:$src, immLeaf:$cc))],
2388 Sched<[itins.Sched]>;
2389 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
2390 (ins VR128:$src1, x86memop:$src, CC:$cc), asm,
2391 [(set VR128:$dst, (Int VR128:$src1,
2392 (load addr:$src), immLeaf:$cc))],
2394 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2397 let isCodeGenOnly = 1 in {
2398 // Aliases to match intrinsics which expect XMM operand(s).
2399 defm Int_VCMPSS : sse12_cmp_scalar_int<f32mem, AVXCC, int_x86_sse_cmp_ss,
2400 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
2401 SSE_ALU_F32S, i8immZExt5>,
2403 defm Int_VCMPSD : sse12_cmp_scalar_int<f64mem, AVXCC, int_x86_sse2_cmp_sd,
2404 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
2405 SSE_ALU_F32S, i8immZExt5>, // same latency as f32
2407 let Constraints = "$src1 = $dst" in {
2408 defm Int_CMPSS : sse12_cmp_scalar_int<f32mem, SSECC, int_x86_sse_cmp_ss,
2409 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
2410 SSE_ALU_F32S, i8immZExt3>, XS;
2411 defm Int_CMPSD : sse12_cmp_scalar_int<f64mem, SSECC, int_x86_sse2_cmp_sd,
2412 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
2413 SSE_ALU_F64S, i8immZExt3>,
2419 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
2420 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
2421 ValueType vt, X86MemOperand x86memop,
2422 PatFrag ld_frag, string OpcodeStr> {
2423 def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
2424 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2425 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
2428 def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
2429 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
2430 [(set EFLAGS, (OpNode (vt RC:$src1),
2431 (ld_frag addr:$src2)))],
2433 Sched<[WriteFAddLd, ReadAfterLd]>;
2436 let Defs = [EFLAGS] in {
2437 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2438 "ucomiss">, PS, VEX, VEX_LIG;
2439 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2440 "ucomisd">, PD, VEX, VEX_LIG;
2441 let Pattern = []<dag> in {
2442 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2443 "comiss">, PS, VEX, VEX_LIG;
2444 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2445 "comisd">, PD, VEX, VEX_LIG;
2448 let isCodeGenOnly = 1 in {
2449 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2450 load, "ucomiss">, PS, VEX;
2451 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2452 load, "ucomisd">, PD, VEX;
2454 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
2455 load, "comiss">, PS, VEX;
2456 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
2457 load, "comisd">, PD, VEX;
2459 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
2461 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
2464 let Pattern = []<dag> in {
2465 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
2467 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
2471 let isCodeGenOnly = 1 in {
2472 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
2473 load, "ucomiss">, PS;
2474 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
2475 load, "ucomisd">, PD;
2477 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
2479 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
2482 } // Defs = [EFLAGS]
2484 // sse12_cmp_packed - sse 1 & 2 compare packed instructions
2485 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
2486 Operand CC, Intrinsic Int, string asm,
2487 string asm_alt, Domain d, ImmLeaf immLeaf,
2488 PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
2489 let isCommutable = 1 in
2490 def rri : PIi8<0xC2, MRMSrcReg,
2491 (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
2492 [(set RC:$dst, (Int RC:$src1, RC:$src2, immLeaf:$cc))],
2495 def rmi : PIi8<0xC2, MRMSrcMem,
2496 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
2497 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2), immLeaf:$cc))],
2499 Sched<[WriteFAddLd, ReadAfterLd]>;
2501 // Accept explicit immediate argument form instead of comparison code.
2502 let isAsmParserOnly = 1, hasSideEffects = 0 in {
2503 def rri_alt : PIi8<0xC2, MRMSrcReg,
2504 (outs RC:$dst), (ins RC:$src1, RC:$src2, u8imm:$cc),
2505 asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;
2507 def rmi_alt : PIi8<0xC2, MRMSrcMem,
2508 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, u8imm:$cc),
2509 asm_alt, [], itins.rm, d>,
2510 Sched<[WriteFAddLd, ReadAfterLd]>;
2514 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse_cmp_ps,
2515 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2516 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2517 SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V;
2518 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, int_x86_sse2_cmp_pd,
2519 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2520 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2521 SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V;
2522 defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_ps_256,
2523 "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2524 "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2525 SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L;
2526 defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, int_x86_avx_cmp_pd_256,
2527 "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2528 "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
2529 SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L;
2530 let Constraints = "$src1 = $dst" in {
2531 defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse_cmp_ps,
2532 "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
2533 "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2534 SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS;
2535 defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, int_x86_sse2_cmp_pd,
2536 "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
2537 "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
2538 SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD;
2541 let Predicates = [HasAVX] in {
2542 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2543 (VCMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2544 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (loadv4f32 addr:$src2), imm:$cc)),
2545 (VCMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2546 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2547 (VCMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2548 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (loadv2f64 addr:$src2), imm:$cc)),
2549 (VCMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2551 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), VR256:$src2, imm:$cc)),
2552 (VCMPPSYrri (v8f32 VR256:$src1), (v8f32 VR256:$src2), imm:$cc)>;
2553 def : Pat<(v8i32 (X86cmpp (v8f32 VR256:$src1), (loadv8f32 addr:$src2), imm:$cc)),
2554 (VCMPPSYrmi (v8f32 VR256:$src1), addr:$src2, imm:$cc)>;
2555 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), VR256:$src2, imm:$cc)),
2556 (VCMPPDYrri VR256:$src1, VR256:$src2, imm:$cc)>;
2557 def : Pat<(v4i64 (X86cmpp (v4f64 VR256:$src1), (loadv4f64 addr:$src2), imm:$cc)),
2558 (VCMPPDYrmi VR256:$src1, addr:$src2, imm:$cc)>;
2561 let Predicates = [UseSSE1] in {
2562 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
2563 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
2564 def : Pat<(v4i32 (X86cmpp (v4f32 VR128:$src1), (memopv4f32 addr:$src2), imm:$cc)),
2565 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
2568 let Predicates = [UseSSE2] in {
2569 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
2570 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
2571 def : Pat<(v2i64 (X86cmpp (v2f64 VR128:$src1), (memopv2f64 addr:$src2), imm:$cc)),
2572 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
2575 //===----------------------------------------------------------------------===//
2576 // SSE 1 & 2 - Shuffle Instructions
2577 //===----------------------------------------------------------------------===//
2579 /// sse12_shuffle - sse 1 & 2 fp shuffle instructions
2580 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
2581 ValueType vt, string asm, PatFrag mem_frag,
2583 def rmi : PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
2584 (ins RC:$src1, x86memop:$src2, u8imm:$src3), asm,
2585 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
2586 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2587 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2588 def rri : PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
2589 (ins RC:$src1, RC:$src2, u8imm:$src3), asm,
2590 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
2591 (i8 imm:$src3))))], IIC_SSE_SHUFP, d>,
2592 Sched<[WriteFShuffle]>;
2595 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2596 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2597 loadv4f32, SSEPackedSingle>, PS, VEX_4V;
2598 defm VSHUFPSY : sse12_shuffle<VR256, f256mem, v8f32,
2599 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2600 loadv8f32, SSEPackedSingle>, PS, VEX_4V, VEX_L;
2601 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2602 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2603 loadv2f64, SSEPackedDouble>, PD, VEX_4V;
2604 defm VSHUFPDY : sse12_shuffle<VR256, f256mem, v4f64,
2605 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
2606 loadv4f64, SSEPackedDouble>, PD, VEX_4V, VEX_L;
2608 let Constraints = "$src1 = $dst" in {
2609 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
2610 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2611 memopv4f32, SSEPackedSingle>, PS;
2612 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
2613 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2614 memopv2f64, SSEPackedDouble>, PD;
2617 let Predicates = [HasAVX] in {
2618 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2619 (bc_v4i32 (loadv2i64 addr:$src2)), (i8 imm:$imm))),
2620 (VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2621 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2622 (VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2624 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2625 (loadv2i64 addr:$src2), (i8 imm:$imm))),
2626 (VSHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2627 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2628 (VSHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2631 def : Pat<(v8i32 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2632 (VSHUFPSYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2633 def : Pat<(v8i32 (X86Shufp VR256:$src1,
2634 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
2635 (VSHUFPSYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2637 def : Pat<(v4i64 (X86Shufp VR256:$src1, VR256:$src2, (i8 imm:$imm))),
2638 (VSHUFPDYrri VR256:$src1, VR256:$src2, imm:$imm)>;
2639 def : Pat<(v4i64 (X86Shufp VR256:$src1,
2640 (loadv4i64 addr:$src2), (i8 imm:$imm))),
2641 (VSHUFPDYrmi VR256:$src1, addr:$src2, imm:$imm)>;
2644 let Predicates = [UseSSE1] in {
2645 def : Pat<(v4i32 (X86Shufp VR128:$src1,
2646 (bc_v4i32 (memopv2i64 addr:$src2)), (i8 imm:$imm))),
2647 (SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
2648 def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2649 (SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
2652 let Predicates = [UseSSE2] in {
2653 // Generic SHUFPD patterns
2654 def : Pat<(v2i64 (X86Shufp VR128:$src1,
2655 (memopv2i64 addr:$src2), (i8 imm:$imm))),
2656 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$imm)>;
2657 def : Pat<(v2i64 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
2658 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$imm)>;
2661 //===----------------------------------------------------------------------===//
2662 // SSE 1 & 2 - Unpack FP Instructions
2663 //===----------------------------------------------------------------------===//
2665 /// sse12_unpack_interleave - sse 1 & 2 fp unpack and interleave
2666 multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
2667 PatFrag mem_frag, RegisterClass RC,
2668 X86MemOperand x86memop, string asm,
2670 def rr : PI<opc, MRMSrcReg,
2671 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2673 (vt (OpNode RC:$src1, RC:$src2)))],
2674 IIC_SSE_UNPCK, d>, Sched<[WriteFShuffle]>;
2675 def rm : PI<opc, MRMSrcMem,
2676 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2678 (vt (OpNode RC:$src1,
2679 (mem_frag addr:$src2))))],
2681 Sched<[WriteFShuffleLd, ReadAfterLd]>;
2684 defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, loadv4f32,
2685 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2686 SSEPackedSingle>, PS, VEX_4V;
2687 defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, loadv2f64,
2688 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2689 SSEPackedDouble>, PD, VEX_4V;
2690 defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, loadv4f32,
2691 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2692 SSEPackedSingle>, PS, VEX_4V;
2693 defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, loadv2f64,
2694 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2695 SSEPackedDouble>, PD, VEX_4V;
2697 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, loadv8f32,
2698 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2699 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2700 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, loadv4f64,
2701 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2702 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2703 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, loadv8f32,
2704 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2705 SSEPackedSingle>, PS, VEX_4V, VEX_L;
2706 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, loadv4f64,
2707 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2708 SSEPackedDouble>, PD, VEX_4V, VEX_L;
2710 let Constraints = "$src1 = $dst" in {
2711 defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
2712 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
2713 SSEPackedSingle>, PS;
2714 defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
2715 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
2716 SSEPackedDouble>, PD;
2717 defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
2718 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
2719 SSEPackedSingle>, PS;
2720 defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
2721 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
2722 SSEPackedDouble>, PD;
2723 } // Constraints = "$src1 = $dst"
2725 let Predicates = [HasAVX1Only] in {
2726 def : Pat<(v8i32 (X86Unpckl VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2727 (VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
2728 def : Pat<(v8i32 (X86Unpckl VR256:$src1, VR256:$src2)),
2729 (VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
2730 def : Pat<(v8i32 (X86Unpckh VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
2731 (VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
2732 def : Pat<(v8i32 (X86Unpckh VR256:$src1, VR256:$src2)),
2733 (VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
2735 def : Pat<(v4i64 (X86Unpckl VR256:$src1, (loadv4i64 addr:$src2))),
2736 (VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
2737 def : Pat<(v4i64 (X86Unpckl VR256:$src1, VR256:$src2)),
2738 (VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
2739 def : Pat<(v4i64 (X86Unpckh VR256:$src1, (loadv4i64 addr:$src2))),
2740 (VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
2741 def : Pat<(v4i64 (X86Unpckh VR256:$src1, VR256:$src2)),
2742 (VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
2745 //===----------------------------------------------------------------------===//
2746 // SSE 1 & 2 - Extract Floating-Point Sign mask
2747 //===----------------------------------------------------------------------===//
2749 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
2750 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
2752 def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
2753 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
2754 [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,
2755 Sched<[WriteVecLogic]>;
2758 let Predicates = [HasAVX] in {
2759 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
2760 "movmskps", SSEPackedSingle>, PS, VEX;
2761 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
2762 "movmskpd", SSEPackedDouble>, PD, VEX;
2763 defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_ps_256,
2764 "movmskps", SSEPackedSingle>, PS,
2766 defm VMOVMSKPDY : sse12_extr_sign_mask<VR256, int_x86_avx_movmsk_pd_256,
2767 "movmskpd", SSEPackedDouble>, PD,
2770 def : Pat<(i32 (X86fgetsign FR32:$src)),
2771 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
2772 def : Pat<(i64 (X86fgetsign FR32:$src)),
2773 (SUBREG_TO_REG (i64 0),
2774 (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;
2775 def : Pat<(i32 (X86fgetsign FR64:$src)),
2776 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
2777 def : Pat<(i64 (X86fgetsign FR64:$src)),
2778 (SUBREG_TO_REG (i64 0),
2779 (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;
2782 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
2783 SSEPackedSingle>, PS;
2784 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
2785 SSEPackedDouble>, PD;
2787 def : Pat<(i32 (X86fgetsign FR32:$src)),
2788 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,
2789 Requires<[UseSSE1]>;
2790 def : Pat<(i64 (X86fgetsign FR32:$src)),
2791 (SUBREG_TO_REG (i64 0),
2792 (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,
2793 Requires<[UseSSE1]>;
2794 def : Pat<(i32 (X86fgetsign FR64:$src)),
2795 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,
2796 Requires<[UseSSE2]>;
2797 def : Pat<(i64 (X86fgetsign FR64:$src)),
2798 (SUBREG_TO_REG (i64 0),
2799 (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,
2800 Requires<[UseSSE2]>;
2802 //===---------------------------------------------------------------------===//
2803 // SSE2 - Packed Integer Logical Instructions
2804 //===---------------------------------------------------------------------===//
2806 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2808 /// PDI_binop_rm - Simple SSE2 binary operator.
2809 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2810 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2811 X86MemOperand x86memop, OpndItins itins,
2812 bit IsCommutable, bit Is2Addr> {
2813 let isCommutable = IsCommutable in
2814 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
2815 (ins RC:$src1, RC:$src2),
2817 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2819 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
2820 Sched<[itins.Sched]>;
2821 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
2822 (ins RC:$src1, x86memop:$src2),
2824 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2825 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2826 [(set RC:$dst, (OpVT (OpNode RC:$src1,
2827 (bitconvert (memop_frag addr:$src2)))))],
2829 Sched<[itins.Sched.Folded, ReadAfterLd]>;
2831 } // ExeDomain = SSEPackedInt
2833 multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
2834 ValueType OpVT128, ValueType OpVT256,
2835 OpndItins itins, bit IsCommutable = 0> {
2836 let Predicates = [HasAVX, NoVLX] in
2837 defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
2838 VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
2840 let Constraints = "$src1 = $dst" in
2841 defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
2842 memopv2i64, i128mem, itins, IsCommutable, 1>;
2844 let Predicates = [HasAVX2, NoVLX] in
2845 defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
2846 OpVT256, VR256, loadv4i64, i256mem, itins,
2847 IsCommutable, 0>, VEX_4V, VEX_L;
2850 // These are ordered here for pattern ordering requirements with the fp versions
2852 defm PAND : PDI_binop_all<0xDB, "pand", and, v2i64, v4i64,
2853 SSE_VEC_BIT_ITINS_P, 1>;
2854 defm POR : PDI_binop_all<0xEB, "por", or, v2i64, v4i64,
2855 SSE_VEC_BIT_ITINS_P, 1>;
2856 defm PXOR : PDI_binop_all<0xEF, "pxor", xor, v2i64, v4i64,
2857 SSE_VEC_BIT_ITINS_P, 1>;
2858 defm PANDN : PDI_binop_all<0xDF, "pandn", X86andnp, v2i64, v4i64,
2859 SSE_VEC_BIT_ITINS_P, 0>;
2861 //===----------------------------------------------------------------------===//
2862 // SSE 1 & 2 - Logical Instructions
2863 //===----------------------------------------------------------------------===//
2865 // Multiclass for scalars using the X86 logical operation aliases for FP.
2866 multiclass sse12_fp_packed_scalar_logical_alias<
2867 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2868 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2869 FR32, f32, f128mem, loadf32_128, SSEPackedSingle, itins, 0>,
2872 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2873 FR64, f64, f128mem, loadf64_128, SSEPackedDouble, itins, 0>,
2876 let Constraints = "$src1 = $dst" in {
2877 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
2878 f32, f128mem, memopfsf32_128, SSEPackedSingle, itins>, PS;
2880 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
2881 f64, f128mem, memopfsf64_128, SSEPackedDouble, itins>, PD;
2885 let isCodeGenOnly = 1 in {
2886 defm FsAND : sse12_fp_packed_scalar_logical_alias<0x54, "and", X86fand,
2888 defm FsOR : sse12_fp_packed_scalar_logical_alias<0x56, "or", X86for,
2890 defm FsXOR : sse12_fp_packed_scalar_logical_alias<0x57, "xor", X86fxor,
2893 let isCommutable = 0 in
2894 defm FsANDN : sse12_fp_packed_scalar_logical_alias<0x55, "andn", X86fandn,
2898 // Multiclass for vectors using the X86 logical operation aliases for FP.
2899 multiclass sse12_fp_packed_vector_logical_alias<
2900 bits<8> opc, string OpcodeStr, SDNode OpNode, OpndItins itins> {
2901 let Predicates = [HasAVX, NoVLX] in {
2902 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
2903 VR128, v4f32, f128mem, loadv4f32, SSEPackedSingle, itins, 0>,
2906 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
2907 VR128, v2f64, f128mem, loadv2f64, SSEPackedDouble, itins, 0>,
2911 let Constraints = "$src1 = $dst" in {
2912 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
2913 v4f32, f128mem, memopv4f32, SSEPackedSingle, itins>,
2916 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
2917 v2f64, f128mem, memopv2f64, SSEPackedDouble, itins>,
2922 let isCodeGenOnly = 1 in {
2923 defm FvAND : sse12_fp_packed_vector_logical_alias<0x54, "and", X86fand,
2925 defm FvOR : sse12_fp_packed_vector_logical_alias<0x56, "or", X86for,
2927 defm FvXOR : sse12_fp_packed_vector_logical_alias<0x57, "xor", X86fxor,
2930 let isCommutable = 0 in
2931 defm FvANDN : sse12_fp_packed_vector_logical_alias<0x55, "andn", X86fandn,
2935 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
2937 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
2939 let Predicates = [HasAVX, NoVLX] in {
2940 defm V#NAME#PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
2941 !strconcat(OpcodeStr, "ps"), f256mem,
2942 [(set VR256:$dst, (v4i64 (OpNode VR256:$src1, VR256:$src2)))],
2943 [(set VR256:$dst, (OpNode (bc_v4i64 (v8f32 VR256:$src1)),
2944 (loadv4i64 addr:$src2)))], 0>, PS, VEX_4V, VEX_L;
2946 defm V#NAME#PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
2947 !strconcat(OpcodeStr, "pd"), f256mem,
2948 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2949 (bc_v4i64 (v4f64 VR256:$src2))))],
2950 [(set VR256:$dst, (OpNode (bc_v4i64 (v4f64 VR256:$src1)),
2951 (loadv4i64 addr:$src2)))], 0>,
2954 // In AVX no need to add a pattern for 128-bit logical rr ps, because they
2955 // are all promoted to v2i64, and the patterns are covered by the int
2956 // version. This is needed in SSE only, because v2i64 isn't supported on
2957 // SSE1, but only on SSE2.
2958 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2959 !strconcat(OpcodeStr, "ps"), f128mem, [],
2960 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2961 (loadv2i64 addr:$src2)))], 0>, PS, VEX_4V;
2963 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2964 !strconcat(OpcodeStr, "pd"), f128mem,
2965 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2966 (bc_v2i64 (v2f64 VR128:$src2))))],
2967 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2968 (loadv2i64 addr:$src2)))], 0>,
2972 let Constraints = "$src1 = $dst" in {
2973 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
2974 !strconcat(OpcodeStr, "ps"), f128mem,
2975 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))],
2976 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
2977 (memopv2i64 addr:$src2)))]>, PS;
2979 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
2980 !strconcat(OpcodeStr, "pd"), f128mem,
2981 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2982 (bc_v2i64 (v2f64 VR128:$src2))))],
2983 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
2984 (memopv2i64 addr:$src2)))]>, PD;
2988 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
2989 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
2990 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
2991 let isCommutable = 0 in
2992 defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp>;
2994 // AVX1 requires type coercions in order to fold loads directly into logical
2996 let Predicates = [HasAVX1Only] in {
2997 def : Pat<(bc_v8f32 (and VR256:$src1, (loadv4i64 addr:$src2))),
2998 (VANDPSYrm VR256:$src1, addr:$src2)>;
2999 def : Pat<(bc_v8f32 (or VR256:$src1, (loadv4i64 addr:$src2))),
3000 (VORPSYrm VR256:$src1, addr:$src2)>;
3001 def : Pat<(bc_v8f32 (xor VR256:$src1, (loadv4i64 addr:$src2))),
3002 (VXORPSYrm VR256:$src1, addr:$src2)>;
3003 def : Pat<(bc_v8f32 (X86andnp VR256:$src1, (loadv4i64 addr:$src2))),
3004 (VANDNPSYrm VR256:$src1, addr:$src2)>;
3007 //===----------------------------------------------------------------------===//
3008 // SSE 1 & 2 - Arithmetic Instructions
3009 //===----------------------------------------------------------------------===//
3011 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
3014 /// In addition, we also have a special variant of the scalar form here to
3015 /// represent the associated intrinsic operation. This form is unlike the
3016 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
3017 /// and leaves the top elements unmodified (therefore these cannot be commuted).
3019 /// These three forms can each be reg+reg or reg+mem.
3022 /// FIXME: once all 256-bit intrinsics are matched, cleanup and refactor those
3024 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr,
3025 SDNode OpNode, SizeItins itins> {
3026 let Predicates = [HasAVX, NoVLX] in {
3027 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
3028 VR128, v4f32, f128mem, loadv4f32,
3029 SSEPackedSingle, itins.s, 0>, PS, VEX_4V;
3030 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
3031 VR128, v2f64, f128mem, loadv2f64,
3032 SSEPackedDouble, itins.d, 0>, PD, VEX_4V;
3034 defm V#NAME#PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"),
3035 OpNode, VR256, v8f32, f256mem, loadv8f32,
3036 SSEPackedSingle, itins.s, 0>, PS, VEX_4V, VEX_L;
3037 defm V#NAME#PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"),
3038 OpNode, VR256, v4f64, f256mem, loadv4f64,
3039 SSEPackedDouble, itins.d, 0>, PD, VEX_4V, VEX_L;
3042 let Constraints = "$src1 = $dst" in {
3043 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
3044 v4f32, f128mem, memopv4f32, SSEPackedSingle,
3046 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
3047 v2f64, f128mem, memopv2f64, SSEPackedDouble,
3052 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3054 defm V#NAME#SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3055 OpNode, FR32, f32mem, SSEPackedSingle, itins.s, 0>,
3056 XS, VEX_4V, VEX_LIG;
3057 defm V#NAME#SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3058 OpNode, FR64, f64mem, SSEPackedDouble, itins.d, 0>,
3059 XD, VEX_4V, VEX_LIG;
3061 let Constraints = "$src1 = $dst" in {
3062 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
3063 OpNode, FR32, f32mem, SSEPackedSingle,
3065 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
3066 OpNode, FR64, f64mem, SSEPackedDouble,
3071 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
3073 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3074 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3075 SSEPackedSingle, itins.s, 0>, XS, VEX_4V, VEX_LIG;
3076 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3077 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3078 SSEPackedDouble, itins.d, 0>, XD, VEX_4V, VEX_LIG;
3080 let Constraints = "$src1 = $dst" in {
3081 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3082 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32,
3083 SSEPackedSingle, itins.s>, XS;
3084 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
3085 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64,
3086 SSEPackedDouble, itins.d>, XD;
3090 // Binary Arithmetic instructions
3091 defm ADD : basic_sse12_fp_binop_p<0x58, "add", fadd, SSE_ALU_ITINS_P>,
3092 basic_sse12_fp_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>,
3093 basic_sse12_fp_binop_s_int<0x58, "add", SSE_ALU_ITINS_S>;
3094 defm MUL : basic_sse12_fp_binop_p<0x59, "mul", fmul, SSE_MUL_ITINS_P>,
3095 basic_sse12_fp_binop_s<0x59, "mul", fmul, SSE_MUL_ITINS_S>,
3096 basic_sse12_fp_binop_s_int<0x59, "mul", SSE_MUL_ITINS_S>;
3097 let isCommutable = 0 in {
3098 defm SUB : basic_sse12_fp_binop_p<0x5C, "sub", fsub, SSE_ALU_ITINS_P>,
3099 basic_sse12_fp_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>,
3100 basic_sse12_fp_binop_s_int<0x5C, "sub", SSE_ALU_ITINS_S>;
3101 defm DIV : basic_sse12_fp_binop_p<0x5E, "div", fdiv, SSE_DIV_ITINS_P>,
3102 basic_sse12_fp_binop_s<0x5E, "div", fdiv, SSE_DIV_ITINS_S>,
3103 basic_sse12_fp_binop_s_int<0x5E, "div", SSE_DIV_ITINS_S>;
3104 defm MAX : basic_sse12_fp_binop_p<0x5F, "max", X86fmax, SSE_ALU_ITINS_P>,
3105 basic_sse12_fp_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>,
3106 basic_sse12_fp_binop_s_int<0x5F, "max", SSE_ALU_ITINS_S>;
3107 defm MIN : basic_sse12_fp_binop_p<0x5D, "min", X86fmin, SSE_ALU_ITINS_P>,
3108 basic_sse12_fp_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>,
3109 basic_sse12_fp_binop_s_int<0x5D, "min", SSE_ALU_ITINS_S>;
3112 let isCodeGenOnly = 1 in {
3113 defm MAXC: basic_sse12_fp_binop_p<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_P>,
3114 basic_sse12_fp_binop_s<0x5F, "max", X86fmaxc, SSE_ALU_ITINS_S>;
3115 defm MINC: basic_sse12_fp_binop_p<0x5D, "min", X86fminc, SSE_ALU_ITINS_P>,
3116 basic_sse12_fp_binop_s<0x5D, "min", X86fminc, SSE_ALU_ITINS_S>;
3119 // Patterns used to select SSE scalar fp arithmetic instructions from
3122 // (1) a scalar fp operation followed by a blend
3124 // The effect is that the backend no longer emits unnecessary vector
3125 // insert instructions immediately after SSE scalar fp instructions
3126 // like addss or mulss.
3128 // For example, given the following code:
3129 // __m128 foo(__m128 A, __m128 B) {
3134 // Previously we generated:
3135 // addss %xmm0, %xmm1
3136 // movss %xmm1, %xmm0
3139 // addss %xmm1, %xmm0
3141 // (2) a vector packed single/double fp operation followed by a vector insert
3143 // The effect is that the backend converts the packed fp instruction
3144 // followed by a vector insert into a single SSE scalar fp instruction.
3146 // For example, given the following code:
3147 // __m128 foo(__m128 A, __m128 B) {
3148 // __m128 C = A + B;
3149 // return (__m128) {c[0], a[1], a[2], a[3]};
3152 // Previously we generated:
3153 // addps %xmm0, %xmm1
3154 // movss %xmm1, %xmm0
3157 // addss %xmm1, %xmm0
3159 // TODO: Some canonicalization in lowering would simplify the number of
3160 // patterns we have to try to match.
3161 multiclass scalar_math_f32_patterns<SDNode Op, string OpcPrefix> {
3162 let Predicates = [UseSSE1] in {
3163 // extracted scalar math op with insert via movss
3164 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3165 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3167 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3168 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3170 // vector math op with insert via movss
3171 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3172 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3173 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3176 // With SSE 4.1, blendi is preferred to movsd, so match that too.
3177 let Predicates = [UseSSE41] in {
3178 // extracted scalar math op with insert via blend
3179 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3180 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3181 FR32:$src))), (i8 1))),
3182 (!cast<I>(OpcPrefix#SSrr_Int) v4f32:$dst,
3183 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3185 // vector math op with insert via blend
3186 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3187 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3188 (!cast<I>(OpcPrefix#SSrr_Int)v4f32:$dst, v4f32:$src)>;
3192 // Repeat everything for AVX, except for the movss + scalar combo...
3193 // because that one shouldn't occur with AVX codegen?
3194 let Predicates = [HasAVX] in {
3195 // extracted scalar math op with insert via blend
3196 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst), (v4f32 (scalar_to_vector
3197 (Op (f32 (vector_extract (v4f32 VR128:$dst), (iPTR 0))),
3198 FR32:$src))), (i8 1))),
3199 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst,
3200 (COPY_TO_REGCLASS FR32:$src, VR128))>;
3202 // vector math op with insert via movss
3203 def : Pat<(v4f32 (X86Movss (v4f32 VR128:$dst),
3204 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)))),
3205 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3207 // vector math op with insert via blend
3208 def : Pat<(v4f32 (X86Blendi (v4f32 VR128:$dst),
3209 (Op (v4f32 VR128:$dst), (v4f32 VR128:$src)), (i8 1))),
3210 (!cast<I>("V"#OpcPrefix#SSrr_Int) v4f32:$dst, v4f32:$src)>;
3214 defm : scalar_math_f32_patterns<fadd, "ADD">;
3215 defm : scalar_math_f32_patterns<fsub, "SUB">;
3216 defm : scalar_math_f32_patterns<fmul, "MUL">;
3217 defm : scalar_math_f32_patterns<fdiv, "DIV">;
3219 multiclass scalar_math_f64_patterns<SDNode Op, string OpcPrefix> {
3220 let Predicates = [UseSSE2] in {
3221 // extracted scalar math op with insert via movsd
3222 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3223 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3225 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3226 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3228 // vector math op with insert via movsd
3229 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3230 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3231 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3234 // With SSE 4.1, blendi is preferred to movsd, so match those too.
3235 let Predicates = [UseSSE41] in {
3236 // extracted scalar math op with insert via blend
3237 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3238 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3239 FR64:$src))), (i8 1))),
3240 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst,
3241 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3243 // vector math op with insert via blend
3244 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3245 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3246 (!cast<I>(OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3249 // Repeat everything for AVX.
3250 let Predicates = [HasAVX] in {
3251 // extracted scalar math op with insert via movsd
3252 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3253 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3255 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3256 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3258 // extracted scalar math op with insert via blend
3259 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst), (v2f64 (scalar_to_vector
3260 (Op (f64 (vector_extract (v2f64 VR128:$dst), (iPTR 0))),
3261 FR64:$src))), (i8 1))),
3262 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst,
3263 (COPY_TO_REGCLASS FR64:$src, VR128))>;
3265 // vector math op with insert via movsd
3266 def : Pat<(v2f64 (X86Movsd (v2f64 VR128:$dst),
3267 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)))),
3268 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3270 // vector math op with insert via blend
3271 def : Pat<(v2f64 (X86Blendi (v2f64 VR128:$dst),
3272 (Op (v2f64 VR128:$dst), (v2f64 VR128:$src)), (i8 1))),
3273 (!cast<I>("V"#OpcPrefix#SDrr_Int) v2f64:$dst, v2f64:$src)>;
3277 defm : scalar_math_f64_patterns<fadd, "ADD">;
3278 defm : scalar_math_f64_patterns<fsub, "SUB">;
3279 defm : scalar_math_f64_patterns<fmul, "MUL">;
3280 defm : scalar_math_f64_patterns<fdiv, "DIV">;
3284 /// In addition, we also have a special variant of the scalar form here to
3285 /// represent the associated intrinsic operation. This form is unlike the
3286 /// plain scalar form, in that it takes an entire vector (instead of a
3287 /// scalar) and leaves the top elements undefined.
3289 /// And, we have a special variant form for a full-vector intrinsic form.
3291 let Sched = WriteFSqrt in {
3292 def SSE_SQRTPS : OpndItins<
3293 IIC_SSE_SQRTPS_RR, IIC_SSE_SQRTPS_RM
3296 def SSE_SQRTSS : OpndItins<
3297 IIC_SSE_SQRTSS_RR, IIC_SSE_SQRTSS_RM
3300 def SSE_SQRTPD : OpndItins<
3301 IIC_SSE_SQRTPD_RR, IIC_SSE_SQRTPD_RM
3304 def SSE_SQRTSD : OpndItins<
3305 IIC_SSE_SQRTSD_RR, IIC_SSE_SQRTSD_RM
3309 let Sched = WriteFRsqrt in {
3310 def SSE_RSQRTPS : OpndItins<
3311 IIC_SSE_RSQRTPS_RR, IIC_SSE_RSQRTPS_RM
3314 def SSE_RSQRTSS : OpndItins<
3315 IIC_SSE_RSQRTSS_RR, IIC_SSE_RSQRTSS_RM
3319 let Sched = WriteFRcp in {
3320 def SSE_RCPP : OpndItins<
3321 IIC_SSE_RCPP_RR, IIC_SSE_RCPP_RM
3324 def SSE_RCPS : OpndItins<
3325 IIC_SSE_RCPS_RR, IIC_SSE_RCPS_RM
3329 /// sse_fp_unop_s - SSE1 unops in scalar form
3330 /// For the non-AVX defs, we need $src1 to be tied to $dst because
3331 /// the HW instructions are 2 operand / destructive.
3332 multiclass sse_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3333 ValueType vt, ValueType ScalarVT,
3334 X86MemOperand x86memop, Operand vec_memop,
3335 ComplexPattern mem_cpat, Intrinsic Intr,
3336 SDNode OpNode, Domain d, OpndItins itins,
3337 Predicate target, string Suffix> {
3338 let hasSideEffects = 0 in {
3339 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1),
3340 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3341 [(set RC:$dst, (OpNode RC:$src1))], itins.rr, d>, Sched<[itins.Sched]>,
3344 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1),
3345 !strconcat(OpcodeStr, "\t{$src1, $dst|$dst, $src1}"),
3346 [(set RC:$dst, (OpNode (load addr:$src1)))], itins.rm, d>,
3347 Sched<[itins.Sched.Folded, ReadAfterLd]>,
3348 Requires<[target, OptForSize]>;
3350 let isCodeGenOnly = 1, Constraints = "$src1 = $dst" in {
3351 def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3352 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3353 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3355 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, vec_memop:$src2),
3356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3357 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3361 let Predicates = [target] in {
3362 def : Pat<(vt (OpNode mem_cpat:$src)),
3363 (vt (COPY_TO_REGCLASS (vt (!cast<Instruction>(NAME#Suffix##m_Int)
3364 (vt (IMPLICIT_DEF)), mem_cpat:$src)), RC))>;
3365 // These are unary operations, but they are modeled as having 2 source operands
3366 // because the high elements of the destination are unchanged in SSE.
3367 def : Pat<(Intr VR128:$src),
3368 (!cast<Instruction>(NAME#Suffix##r_Int) VR128:$src, VR128:$src)>;
3369 def : Pat<(Intr (load addr:$src)),
3370 (vt (COPY_TO_REGCLASS(!cast<Instruction>(NAME#Suffix##m)
3371 addr:$src), VR128))>;
3372 def : Pat<(Intr mem_cpat:$src),
3373 (!cast<Instruction>(NAME#Suffix##m_Int)
3374 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3378 multiclass avx_fp_unop_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3379 ValueType vt, ValueType ScalarVT,
3380 X86MemOperand x86memop, Operand vec_memop,
3381 ComplexPattern mem_cpat,
3382 Intrinsic Intr, SDNode OpNode, Domain d,
3383 OpndItins itins, Predicate target, string Suffix> {
3384 let hasSideEffects = 0 in {
3385 def r : I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
3386 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3387 [], itins.rr, d>, Sched<[itins.Sched]>;
3389 def m : I<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
3390 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3391 [], itins.rm, d>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3392 let isCodeGenOnly = 1 in {
3393 // todo: uncomment when all r_Int forms will be added to X86InstrInfo.cpp
3394 //def r_Int : I<opc, MRMSrcReg, (outs VR128:$dst),
3395 // (ins VR128:$src1, VR128:$src2),
3396 // !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3397 // []>, Sched<[itins.Sched.Folded]>;
3399 def m_Int : I<opc, MRMSrcMem, (outs VR128:$dst),
3400 (ins VR128:$src1, vec_memop:$src2),
3401 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3402 []>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3406 let Predicates = [target] in {
3407 def : Pat<(OpNode RC:$src), (!cast<Instruction>("V"#NAME#Suffix##r)
3408 (ScalarVT (IMPLICIT_DEF)), RC:$src)>;
3410 def : Pat<(vt (OpNode mem_cpat:$src)),
3411 (!cast<Instruction>("V"#NAME#Suffix##m_Int) (vt (IMPLICIT_DEF)),
3414 // todo: use r_Int form when it will be ready
3415 //def : Pat<(Intr VR128:$src), (!cast<Instruction>("V"#NAME#Suffix##r_Int)
3416 // (VT (IMPLICIT_DEF)), VR128:$src)>;
3417 def : Pat<(Intr VR128:$src),
3418 (vt (COPY_TO_REGCLASS(
3419 !cast<Instruction>("V"#NAME#Suffix##r) (ScalarVT (IMPLICIT_DEF)),
3420 (ScalarVT (COPY_TO_REGCLASS VR128:$src, RC))), VR128))>;
3421 def : Pat<(Intr mem_cpat:$src),
3422 (!cast<Instruction>("V"#NAME#Suffix##m_Int)
3423 (vt (IMPLICIT_DEF)), mem_cpat:$src)>;
3425 let Predicates = [target, OptForSize] in
3426 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3427 (!cast<Instruction>("V"#NAME#Suffix##m) (ScalarVT (IMPLICIT_DEF)),
3431 /// sse1_fp_unop_p - SSE1 unops in packed form.
3432 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3434 let Predicates = [HasAVX] in {
3435 def V#NAME#PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3436 !strconcat("v", OpcodeStr,
3437 "ps\t{$src, $dst|$dst, $src}"),
3438 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))],
3439 itins.rr>, VEX, Sched<[itins.Sched]>;
3440 def V#NAME#PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3441 !strconcat("v", OpcodeStr,
3442 "ps\t{$src, $dst|$dst, $src}"),
3443 [(set VR128:$dst, (OpNode (loadv4f32 addr:$src)))],
3444 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3445 def V#NAME#PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3446 !strconcat("v", OpcodeStr,
3447 "ps\t{$src, $dst|$dst, $src}"),
3448 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))],
3449 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3450 def V#NAME#PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3451 !strconcat("v", OpcodeStr,
3452 "ps\t{$src, $dst|$dst, $src}"),
3453 [(set VR256:$dst, (OpNode (loadv8f32 addr:$src)))],
3454 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3457 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3458 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3459 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))], itins.rr>,
3460 Sched<[itins.Sched]>;
3461 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3462 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3463 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))], itins.rm>,
3464 Sched<[itins.Sched.Folded]>;
3467 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
3468 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
3469 Intrinsic V4F32Int, Intrinsic V8F32Int,
3471 let isCodeGenOnly = 1 in {
3472 let Predicates = [HasAVX] in {
3473 def V#NAME#PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3474 !strconcat("v", OpcodeStr,
3475 "ps\t{$src, $dst|$dst, $src}"),
3476 [(set VR128:$dst, (V4F32Int VR128:$src))],
3477 itins.rr>, VEX, Sched<[itins.Sched]>;
3478 def V#NAME#PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3479 !strconcat("v", OpcodeStr,
3480 "ps\t{$src, $dst|$dst, $src}"),
3481 [(set VR128:$dst, (V4F32Int (loadv4f32 addr:$src)))],
3482 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3483 def V#NAME#PSYr_Int : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3484 !strconcat("v", OpcodeStr,
3485 "ps\t{$src, $dst|$dst, $src}"),
3486 [(set VR256:$dst, (V8F32Int VR256:$src))],
3487 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3488 def V#NAME#PSYm_Int : PSI<opc, MRMSrcMem, (outs VR256:$dst),
3490 !strconcat("v", OpcodeStr,
3491 "ps\t{$src, $dst|$dst, $src}"),
3492 [(set VR256:$dst, (V8F32Int (loadv8f32 addr:$src)))],
3493 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3496 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3497 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3498 [(set VR128:$dst, (V4F32Int VR128:$src))],
3499 itins.rr>, Sched<[itins.Sched]>;
3500 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3501 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
3502 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))],
3503 itins.rm>, Sched<[itins.Sched.Folded]>;
3504 } // isCodeGenOnly = 1
3507 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3508 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
3509 SDNode OpNode, OpndItins itins> {
3510 let Predicates = [HasAVX] in {
3511 def V#NAME#PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3512 !strconcat("v", OpcodeStr,
3513 "pd\t{$src, $dst|$dst, $src}"),
3514 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))],
3515 itins.rr>, VEX, Sched<[itins.Sched]>;
3516 def V#NAME#PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3517 !strconcat("v", OpcodeStr,
3518 "pd\t{$src, $dst|$dst, $src}"),
3519 [(set VR128:$dst, (OpNode (loadv2f64 addr:$src)))],
3520 itins.rm>, VEX, Sched<[itins.Sched.Folded]>;
3521 def V#NAME#PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3522 !strconcat("v", OpcodeStr,
3523 "pd\t{$src, $dst|$dst, $src}"),
3524 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))],
3525 itins.rr>, VEX, VEX_L, Sched<[itins.Sched]>;
3526 def V#NAME#PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
3527 !strconcat("v", OpcodeStr,
3528 "pd\t{$src, $dst|$dst, $src}"),
3529 [(set VR256:$dst, (OpNode (loadv4f64 addr:$src)))],
3530 itins.rm>, VEX, VEX_L, Sched<[itins.Sched.Folded]>;
3533 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3534 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3535 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))], itins.rr>,
3536 Sched<[itins.Sched]>;
3537 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
3538 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
3539 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))], itins.rm>,
3540 Sched<[itins.Sched.Folded]>;
3543 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3545 defm SS : sse_fp_unop_s<opc, OpcodeStr##ss, FR32, v4f32, f32, f32mem,
3546 ssmem, sse_load_f32,
3547 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3548 SSEPackedSingle, itins, UseSSE1, "SS">, XS;
3549 defm V#NAME#SS : avx_fp_unop_s<opc, "v"#OpcodeStr##ss, FR32, v4f32, f32,
3550 f32mem, ssmem, sse_load_f32,
3551 !cast<Intrinsic>("int_x86_sse_"##OpcodeStr##_ss), OpNode,
3552 SSEPackedSingle, itins, UseAVX, "SS">, XS, VEX_4V, VEX_LIG;
3555 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
3557 defm SD : sse_fp_unop_s<opc, OpcodeStr##sd, FR64, v2f64, f64, f64mem,
3558 sdmem, sse_load_f64,
3559 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3560 OpNode, SSEPackedDouble, itins, UseSSE2, "SD">, XD;
3561 defm V#NAME#SD : avx_fp_unop_s<opc, "v"#OpcodeStr##sd, FR64, v2f64, f64,
3562 f64mem, sdmem, sse_load_f64,
3563 !cast<Intrinsic>("int_x86_sse2_"##OpcodeStr##_sd),
3564 OpNode, SSEPackedDouble, itins, UseAVX, "SD">,
3565 XD, VEX_4V, VEX_LIG;
3569 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSS>,
3570 sse1_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPS>,
3571 sse2_fp_unop_s<0x51, "sqrt", fsqrt, SSE_SQRTSD>,
3572 sse2_fp_unop_p<0x51, "sqrt", fsqrt, SSE_SQRTPD>;
3574 // Reciprocal approximations. Note that these typically require refinement
3575 // in order to obtain suitable precision.
3576 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, SSE_RSQRTSS>,
3577 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt, SSE_RSQRTPS>,
3578 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps,
3579 int_x86_avx_rsqrt_ps_256, SSE_RSQRTPS>;
3580 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, SSE_RCPS>,
3581 sse1_fp_unop_p<0x53, "rcp", X86frcp, SSE_RCPP>,
3582 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps,
3583 int_x86_avx_rcp_ps_256, SSE_RCPP>;
3585 // There is no f64 version of the reciprocal approximation instructions.
3587 //===----------------------------------------------------------------------===//
3588 // SSE 1 & 2 - Non-temporal stores
3589 //===----------------------------------------------------------------------===//
3591 let AddedComplexity = 400 in { // Prefer non-temporal versions
3592 let SchedRW = [WriteStore] in {
3593 let Predicates = [HasAVX, NoVLX] in {
3594 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
3595 (ins f128mem:$dst, VR128:$src),
3596 "movntps\t{$src, $dst|$dst, $src}",
3597 [(alignednontemporalstore (v4f32 VR128:$src),
3599 IIC_SSE_MOVNT>, VEX;
3600 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
3601 (ins f128mem:$dst, VR128:$src),
3602 "movntpd\t{$src, $dst|$dst, $src}",
3603 [(alignednontemporalstore (v2f64 VR128:$src),
3605 IIC_SSE_MOVNT>, VEX;
3607 let ExeDomain = SSEPackedInt in
3608 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
3609 (ins f128mem:$dst, VR128:$src),
3610 "movntdq\t{$src, $dst|$dst, $src}",
3611 [(alignednontemporalstore (v2i64 VR128:$src),
3613 IIC_SSE_MOVNT>, VEX;
3615 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
3616 (ins f256mem:$dst, VR256:$src),
3617 "movntps\t{$src, $dst|$dst, $src}",
3618 [(alignednontemporalstore (v8f32 VR256:$src),
3620 IIC_SSE_MOVNT>, VEX, VEX_L;
3621 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
3622 (ins f256mem:$dst, VR256:$src),
3623 "movntpd\t{$src, $dst|$dst, $src}",
3624 [(alignednontemporalstore (v4f64 VR256:$src),
3626 IIC_SSE_MOVNT>, VEX, VEX_L;
3627 let ExeDomain = SSEPackedInt in
3628 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
3629 (ins f256mem:$dst, VR256:$src),
3630 "movntdq\t{$src, $dst|$dst, $src}",
3631 [(alignednontemporalstore (v4i64 VR256:$src),
3633 IIC_SSE_MOVNT>, VEX, VEX_L;
3636 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3637 "movntps\t{$src, $dst|$dst, $src}",
3638 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)],
3640 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3641 "movntpd\t{$src, $dst|$dst, $src}",
3642 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)],
3645 let ExeDomain = SSEPackedInt in
3646 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
3647 "movntdq\t{$src, $dst|$dst, $src}",
3648 [(alignednontemporalstore (v2i64 VR128:$src), addr:$dst)],
3651 // There is no AVX form for instructions below this point
3652 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
3653 "movnti{l}\t{$src, $dst|$dst, $src}",
3654 [(nontemporalstore (i32 GR32:$src), addr:$dst)],
3656 PS, Requires<[HasSSE2]>;
3657 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
3658 "movnti{q}\t{$src, $dst|$dst, $src}",
3659 [(nontemporalstore (i64 GR64:$src), addr:$dst)],
3661 PS, Requires<[HasSSE2]>;
3662 } // SchedRW = [WriteStore]
3664 let Predicates = [HasAVX2, NoVLX] in {
3665 def : Pat<(alignednontemporalstore (v8i32 VR256:$src), addr:$dst),
3666 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3667 def : Pat<(alignednontemporalstore (v16i16 VR256:$src), addr:$dst),
3668 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3669 def : Pat<(alignednontemporalstore (v32i8 VR256:$src), addr:$dst),
3670 (VMOVNTDQYmr addr:$dst, VR256:$src)>;
3673 let Predicates = [HasAVX, NoVLX] in {
3674 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3675 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3676 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3677 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3678 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3679 (VMOVNTDQmr addr:$dst, VR128:$src)>;
3682 def : Pat<(alignednontemporalstore (v4i32 VR128:$src), addr:$dst),
3683 (MOVNTDQmr addr:$dst, VR128:$src)>;
3684 def : Pat<(alignednontemporalstore (v8i16 VR128:$src), addr:$dst),
3685 (MOVNTDQmr addr:$dst, VR128:$src)>;
3686 def : Pat<(alignednontemporalstore (v16i8 VR128:$src), addr:$dst),
3687 (MOVNTDQmr addr:$dst, VR128:$src)>;
3689 } // AddedComplexity
3691 //===----------------------------------------------------------------------===//
3692 // SSE 1 & 2 - Prefetch and memory fence
3693 //===----------------------------------------------------------------------===//
3695 // Prefetch intrinsic.
3696 let Predicates = [HasSSE1], SchedRW = [WriteLoad] in {
3697 def PREFETCHT0 : I<0x18, MRM1m, (outs), (ins i8mem:$src),
3698 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))],
3699 IIC_SSE_PREFETCH>, TB;
3700 def PREFETCHT1 : I<0x18, MRM2m, (outs), (ins i8mem:$src),
3701 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))],
3702 IIC_SSE_PREFETCH>, TB;
3703 def PREFETCHT2 : I<0x18, MRM3m, (outs), (ins i8mem:$src),
3704 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))],
3705 IIC_SSE_PREFETCH>, TB;
3706 def PREFETCHNTA : I<0x18, MRM0m, (outs), (ins i8mem:$src),
3707 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))],
3708 IIC_SSE_PREFETCH>, TB;
3711 // FIXME: How should flush instruction be modeled?
3712 let SchedRW = [WriteLoad] in {
3714 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
3715 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)],
3716 IIC_SSE_PREFETCH>, PS, Requires<[HasSSE2]>;
3719 let SchedRW = [WriteNop] in {
3720 // Pause. This "instruction" is encoded as "rep; nop", so even though it
3721 // was introduced with SSE2, it's backward compatible.
3722 def PAUSE : I<0x90, RawFrm, (outs), (ins),
3723 "pause", [(int_x86_sse2_pause)], IIC_SSE_PAUSE>,
3724 OBXS, Requires<[HasSSE2]>;
3727 let SchedRW = [WriteFence] in {
3728 // Load, store, and memory fence
3729 def SFENCE : I<0xAE, MRM_F8, (outs), (ins),
3730 "sfence", [(int_x86_sse_sfence)], IIC_SSE_SFENCE>,
3731 PS, Requires<[HasSSE1]>;
3732 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
3733 "lfence", [(int_x86_sse2_lfence)], IIC_SSE_LFENCE>,
3734 TB, Requires<[HasSSE2]>;
3735 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
3736 "mfence", [(int_x86_sse2_mfence)], IIC_SSE_MFENCE>,
3737 TB, Requires<[HasSSE2]>;
3740 def : Pat<(X86SFence), (SFENCE)>;
3741 def : Pat<(X86LFence), (LFENCE)>;
3742 def : Pat<(X86MFence), (MFENCE)>;
3744 //===----------------------------------------------------------------------===//
3745 // SSE 1 & 2 - Load/Store XCSR register
3746 //===----------------------------------------------------------------------===//
3748 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
3749 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3750 IIC_SSE_LDMXCSR>, VEX, Sched<[WriteLoad]>;
3751 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3752 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3753 IIC_SSE_STMXCSR>, VEX, Sched<[WriteStore]>;
3755 let Predicates = [UseSSE1] in {
3756 def LDMXCSR : I<0xAE, MRM2m, (outs), (ins i32mem:$src),
3757 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)],
3758 IIC_SSE_LDMXCSR>, TB, Sched<[WriteLoad]>;
3759 def STMXCSR : I<0xAE, MRM3m, (outs), (ins i32mem:$dst),
3760 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)],
3761 IIC_SSE_STMXCSR>, TB, Sched<[WriteStore]>;
3764 //===---------------------------------------------------------------------===//
3765 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
3766 //===---------------------------------------------------------------------===//
3768 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3770 let hasSideEffects = 0, SchedRW = [WriteMove] in {
3771 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3772 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3774 def VMOVDQAYrr : VPDI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3775 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>,
3777 def VMOVDQUrr : VSSI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3778 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3780 def VMOVDQUYrr : VSSI<0x6F, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
3781 "movdqu\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVU_P_RR>,
3786 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
3787 SchedRW = [WriteMove] in {
3788 def VMOVDQArr_REV : VPDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3789 "movdqa\t{$src, $dst|$dst, $src}", [],
3792 def VMOVDQAYrr_REV : VPDI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3793 "movdqa\t{$src, $dst|$dst, $src}", [],
3794 IIC_SSE_MOVA_P_RR>, VEX, VEX_L;
3795 def VMOVDQUrr_REV : VSSI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3796 "movdqu\t{$src, $dst|$dst, $src}", [],
3799 def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
3800 "movdqu\t{$src, $dst|$dst, $src}", [],
3801 IIC_SSE_MOVU_P_RR>, VEX, VEX_L;
3804 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3805 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3806 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3807 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3809 def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3810 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
3812 let Predicates = [HasAVX] in {
3813 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3814 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3816 def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
3817 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
3822 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3823 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
3824 (ins i128mem:$dst, VR128:$src),
3825 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3827 def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
3828 (ins i256mem:$dst, VR256:$src),
3829 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
3831 let Predicates = [HasAVX] in {
3832 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3833 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3835 def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
3836 "vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
3841 let SchedRW = [WriteMove] in {
3842 let hasSideEffects = 0 in
3843 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3844 "movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>;
3846 def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3847 "movdqu\t{$src, $dst|$dst, $src}",
3848 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3851 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
3852 def MOVDQArr_REV : PDI<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3853 "movdqa\t{$src, $dst|$dst, $src}", [],
3856 def MOVDQUrr_REV : I<0x7F, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
3857 "movdqu\t{$src, $dst|$dst, $src}",
3858 [], IIC_SSE_MOVU_P_RR>, XS, Requires<[UseSSE2]>;
3862 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
3863 hasSideEffects = 0, SchedRW = [WriteLoad] in {
3864 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3865 "movdqa\t{$src, $dst|$dst, $src}",
3866 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/],
3868 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3869 "movdqu\t{$src, $dst|$dst, $src}",
3870 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/],
3872 XS, Requires<[UseSSE2]>;
3875 let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
3876 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3877 "movdqa\t{$src, $dst|$dst, $src}",
3878 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/],
3880 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
3881 "movdqu\t{$src, $dst|$dst, $src}",
3882 [/*(store (v2i64 VR128:$src), addr:$dst)*/],
3884 XS, Requires<[UseSSE2]>;
3887 } // ExeDomain = SSEPackedInt
3889 let Predicates = [HasAVX] in {
3890 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3891 (VMOVDQUmr addr:$dst, VR128:$src)>;
3892 def : Pat<(int_x86_avx_storeu_dq_256 addr:$dst, VR256:$src),
3893 (VMOVDQUYmr addr:$dst, VR256:$src)>;
3895 let Predicates = [UseSSE2] in
3896 def : Pat<(int_x86_sse2_storeu_dq addr:$dst, VR128:$src),
3897 (MOVDQUmr addr:$dst, VR128:$src)>;
3899 //===---------------------------------------------------------------------===//
3900 // SSE2 - Packed Integer Arithmetic Instructions
3901 //===---------------------------------------------------------------------===//
3903 let Sched = WriteVecIMul in
3904 def SSE_PMADD : OpndItins<
3905 IIC_SSE_PMADD, IIC_SSE_PMADD
3908 let ExeDomain = SSEPackedInt in { // SSE integer instructions
3910 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
3911 RegisterClass RC, PatFrag memop_frag,
3912 X86MemOperand x86memop,
3914 bit IsCommutable = 0,
3916 let isCommutable = IsCommutable in
3917 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3918 (ins RC:$src1, RC:$src2),
3920 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3921 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3922 [(set RC:$dst, (IntId RC:$src1, RC:$src2))], itins.rr>,
3923 Sched<[itins.Sched]>;
3924 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3925 (ins RC:$src1, x86memop:$src2),
3927 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3928 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3929 [(set RC:$dst, (IntId RC:$src1, (bitconvert (memop_frag addr:$src2))))],
3930 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
3933 multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
3934 Intrinsic IntId256, OpndItins itins,
3935 bit IsCommutable = 0> {
3936 let Predicates = [HasAVX] in
3937 defm V#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
3938 VR128, loadv2i64, i128mem, itins,
3939 IsCommutable, 0>, VEX_4V;
3941 let Constraints = "$src1 = $dst" in
3942 defm NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
3943 i128mem, itins, IsCommutable, 1>;
3945 let Predicates = [HasAVX2] in
3946 defm V#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
3947 VR256, loadv4i64, i256mem, itins,
3948 IsCommutable, 0>, VEX_4V, VEX_L;
3951 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3952 string OpcodeStr, SDNode OpNode,
3953 SDNode OpNode2, RegisterClass RC,
3954 ValueType DstVT, ValueType SrcVT, PatFrag bc_frag,
3955 PatFrag ld_frag, ShiftOpndItins itins,
3957 // src2 is always 128-bit
3958 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3959 (ins RC:$src1, VR128:$src2),
3961 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3962 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3963 [(set RC:$dst, (DstVT (OpNode RC:$src1, (SrcVT VR128:$src2))))],
3964 itins.rr>, Sched<[WriteVecShift]>;
3965 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3966 (ins RC:$src1, i128mem:$src2),
3968 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3969 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3970 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3971 (bc_frag (ld_frag addr:$src2)))))], itins.rm>,
3972 Sched<[WriteVecShiftLd, ReadAfterLd]>;
3973 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3974 (ins RC:$src1, u8imm:$src2),
3976 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3977 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3978 [(set RC:$dst, (DstVT (OpNode2 RC:$src1, (i8 imm:$src2))))], itins.ri>,
3979 Sched<[WriteVecShift]>;
3982 /// PDI_binop_rm2 - Simple SSE2 binary operator with different src and dst types
3983 multiclass PDI_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
3984 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
3985 PatFrag memop_frag, X86MemOperand x86memop,
3987 bit IsCommutable = 0, bit Is2Addr = 1> {
3988 let isCommutable = IsCommutable in
3989 def rr : PDI<opc, MRMSrcReg, (outs RC:$dst),
3990 (ins RC:$src1, RC:$src2),
3992 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3993 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3994 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
3995 Sched<[itins.Sched]>;
3996 def rm : PDI<opc, MRMSrcMem, (outs RC:$dst),
3997 (ins RC:$src1, x86memop:$src2),
3999 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4000 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4001 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
4002 (bitconvert (memop_frag addr:$src2)))))]>,
4003 Sched<[itins.Sched.Folded, ReadAfterLd]>;
4005 } // ExeDomain = SSEPackedInt
4007 defm PADDB : PDI_binop_all<0xFC, "paddb", add, v16i8, v32i8,
4008 SSE_INTALU_ITINS_P, 1>;
4009 defm PADDW : PDI_binop_all<0xFD, "paddw", add, v8i16, v16i16,
4010 SSE_INTALU_ITINS_P, 1>;
4011 defm PADDD : PDI_binop_all<0xFE, "paddd", add, v4i32, v8i32,
4012 SSE_INTALU_ITINS_P, 1>;
4013 defm PADDQ : PDI_binop_all<0xD4, "paddq", add, v2i64, v4i64,
4014 SSE_INTALUQ_ITINS_P, 1>;
4015 defm PMULLW : PDI_binop_all<0xD5, "pmullw", mul, v8i16, v16i16,
4016 SSE_INTMUL_ITINS_P, 1>;
4017 defm PMULHUW : PDI_binop_all<0xE4, "pmulhuw", mulhu, v8i16, v16i16,
4018 SSE_INTMUL_ITINS_P, 1>;
4019 defm PMULHW : PDI_binop_all<0xE5, "pmulhw", mulhs, v8i16, v16i16,
4020 SSE_INTMUL_ITINS_P, 1>;
4021 defm PSUBB : PDI_binop_all<0xF8, "psubb", sub, v16i8, v32i8,
4022 SSE_INTALU_ITINS_P, 0>;
4023 defm PSUBW : PDI_binop_all<0xF9, "psubw", sub, v8i16, v16i16,
4024 SSE_INTALU_ITINS_P, 0>;
4025 defm PSUBD : PDI_binop_all<0xFA, "psubd", sub, v4i32, v8i32,
4026 SSE_INTALU_ITINS_P, 0>;
4027 defm PSUBQ : PDI_binop_all<0xFB, "psubq", sub, v2i64, v4i64,
4028 SSE_INTALUQ_ITINS_P, 0>;
4029 defm PSUBUSB : PDI_binop_all<0xD8, "psubusb", X86subus, v16i8, v32i8,
4030 SSE_INTALU_ITINS_P, 0>;
4031 defm PSUBUSW : PDI_binop_all<0xD9, "psubusw", X86subus, v8i16, v16i16,
4032 SSE_INTALU_ITINS_P, 0>;
4033 defm PMINUB : PDI_binop_all<0xDA, "pminub", X86umin, v16i8, v32i8,
4034 SSE_INTALU_ITINS_P, 1>;
4035 defm PMINSW : PDI_binop_all<0xEA, "pminsw", X86smin, v8i16, v16i16,
4036 SSE_INTALU_ITINS_P, 1>;
4037 defm PMAXUB : PDI_binop_all<0xDE, "pmaxub", X86umax, v16i8, v32i8,
4038 SSE_INTALU_ITINS_P, 1>;
4039 defm PMAXSW : PDI_binop_all<0xEE, "pmaxsw", X86smax, v8i16, v16i16,
4040 SSE_INTALU_ITINS_P, 1>;
4043 defm PSUBSB : PDI_binop_all_int<0xE8, "psubsb", int_x86_sse2_psubs_b,
4044 int_x86_avx2_psubs_b, SSE_INTALU_ITINS_P, 0>;
4045 defm PSUBSW : PDI_binop_all_int<0xE9, "psubsw" , int_x86_sse2_psubs_w,
4046 int_x86_avx2_psubs_w, SSE_INTALU_ITINS_P, 0>;
4047 defm PADDSB : PDI_binop_all_int<0xEC, "paddsb" , int_x86_sse2_padds_b,
4048 int_x86_avx2_padds_b, SSE_INTALU_ITINS_P, 1>;
4049 defm PADDSW : PDI_binop_all_int<0xED, "paddsw" , int_x86_sse2_padds_w,
4050 int_x86_avx2_padds_w, SSE_INTALU_ITINS_P, 1>;
4051 defm PADDUSB : PDI_binop_all_int<0xDC, "paddusb", int_x86_sse2_paddus_b,
4052 int_x86_avx2_paddus_b, SSE_INTALU_ITINS_P, 1>;
4053 defm PADDUSW : PDI_binop_all_int<0xDD, "paddusw", int_x86_sse2_paddus_w,
4054 int_x86_avx2_paddus_w, SSE_INTALU_ITINS_P, 1>;
4055 defm PMADDWD : PDI_binop_all_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd,
4056 int_x86_avx2_pmadd_wd, SSE_PMADD, 1>;
4057 defm PAVGB : PDI_binop_all_int<0xE0, "pavgb", int_x86_sse2_pavg_b,
4058 int_x86_avx2_pavg_b, SSE_INTALU_ITINS_P, 1>;
4059 defm PAVGW : PDI_binop_all_int<0xE3, "pavgw", int_x86_sse2_pavg_w,
4060 int_x86_avx2_pavg_w, SSE_INTALU_ITINS_P, 1>;
4061 defm PSADBW : PDI_binop_all_int<0xF6, "psadbw", int_x86_sse2_psad_bw,
4062 int_x86_avx2_psad_bw, SSE_PMADD, 1>;
4064 let Predicates = [HasAVX] in
4065 defm VPMULUDQ : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v2i64, v4i32, VR128,
4066 loadv2i64, i128mem, SSE_INTMUL_ITINS_P, 1, 0>,
4068 let Predicates = [HasAVX2] in
4069 defm VPMULUDQY : PDI_binop_rm2<0xF4, "vpmuludq", X86pmuludq, v4i64, v8i32,
4070 VR256, loadv4i64, i256mem,
4071 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
4072 let Constraints = "$src1 = $dst" in
4073 defm PMULUDQ : PDI_binop_rm2<0xF4, "pmuludq", X86pmuludq, v2i64, v4i32, VR128,
4074 memopv2i64, i128mem, SSE_INTMUL_ITINS_P, 1>;
4076 //===---------------------------------------------------------------------===//
4077 // SSE2 - Packed Integer Logical Instructions
4078 //===---------------------------------------------------------------------===//
4080 let Predicates = [HasAVX, NoVLX] in {
4081 defm VPSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4082 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4083 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4084 defm VPSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4085 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4086 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4087 defm VPSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4088 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4089 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4091 defm VPSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4092 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4093 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4094 defm VPSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4095 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4096 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4097 defm VPSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4098 VR128, v2i64, v2i64, bc_v2i64, loadv2i64,
4099 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4101 defm VPSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4102 VR128, v8i16, v8i16, bc_v8i16, loadv2i64,
4103 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4104 defm VPSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4105 VR128, v4i32, v4i32, bc_v4i32, loadv2i64,
4106 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V;
4108 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift] in {
4109 // 128-bit logical shifts.
4110 def VPSLLDQri : PDIi8<0x73, MRM7r,
4111 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4112 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4114 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))]>,
4116 def VPSRLDQri : PDIi8<0x73, MRM3r,
4117 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4118 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4120 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))]>,
4122 // PSRADQri doesn't exist in SSE[1-3].
4124 } // Predicates = [HasAVX]
4126 let Predicates = [HasAVX2, NoVLX] in {
4127 defm VPSLLWY : PDI_binop_rmi<0xF1, 0x71, MRM6r, "vpsllw", X86vshl, X86vshli,
4128 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4129 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4130 defm VPSLLDY : PDI_binop_rmi<0xF2, 0x72, MRM6r, "vpslld", X86vshl, X86vshli,
4131 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4132 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4133 defm VPSLLQY : PDI_binop_rmi<0xF3, 0x73, MRM6r, "vpsllq", X86vshl, X86vshli,
4134 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4135 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4137 defm VPSRLWY : PDI_binop_rmi<0xD1, 0x71, MRM2r, "vpsrlw", X86vsrl, X86vsrli,
4138 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4139 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4140 defm VPSRLDY : PDI_binop_rmi<0xD2, 0x72, MRM2r, "vpsrld", X86vsrl, X86vsrli,
4141 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4142 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4143 defm VPSRLQY : PDI_binop_rmi<0xD3, 0x73, MRM2r, "vpsrlq", X86vsrl, X86vsrli,
4144 VR256, v4i64, v2i64, bc_v2i64, loadv2i64,
4145 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4147 defm VPSRAWY : PDI_binop_rmi<0xE1, 0x71, MRM4r, "vpsraw", X86vsra, X86vsrai,
4148 VR256, v16i16, v8i16, bc_v8i16, loadv2i64,
4149 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4150 defm VPSRADY : PDI_binop_rmi<0xE2, 0x72, MRM4r, "vpsrad", X86vsra, X86vsrai,
4151 VR256, v8i32, v4i32, bc_v4i32, loadv2i64,
4152 SSE_INTSHIFT_ITINS_P, 0>, VEX_4V, VEX_L;
4154 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4155 // 256-bit logical shifts.
4156 def VPSLLDQYri : PDIi8<0x73, MRM7r,
4157 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4158 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4160 (v4i64 (X86vshldq VR256:$src1, (i8 imm:$src2))))]>,
4162 def VPSRLDQYri : PDIi8<0x73, MRM3r,
4163 (outs VR256:$dst), (ins VR256:$src1, u8imm:$src2),
4164 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4166 (v4i64 (X86vshrdq VR256:$src1, (i8 imm:$src2))))]>,
4168 // PSRADQYri doesn't exist in SSE[1-3].
4170 } // Predicates = [HasAVX2]
4172 let Constraints = "$src1 = $dst" in {
4173 defm PSLLW : PDI_binop_rmi<0xF1, 0x71, MRM6r, "psllw", X86vshl, X86vshli,
4174 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4175 SSE_INTSHIFT_ITINS_P>;
4176 defm PSLLD : PDI_binop_rmi<0xF2, 0x72, MRM6r, "pslld", X86vshl, X86vshli,
4177 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4178 SSE_INTSHIFT_ITINS_P>;
4179 defm PSLLQ : PDI_binop_rmi<0xF3, 0x73, MRM6r, "psllq", X86vshl, X86vshli,
4180 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4181 SSE_INTSHIFT_ITINS_P>;
4183 defm PSRLW : PDI_binop_rmi<0xD1, 0x71, MRM2r, "psrlw", X86vsrl, X86vsrli,
4184 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4185 SSE_INTSHIFT_ITINS_P>;
4186 defm PSRLD : PDI_binop_rmi<0xD2, 0x72, MRM2r, "psrld", X86vsrl, X86vsrli,
4187 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4188 SSE_INTSHIFT_ITINS_P>;
4189 defm PSRLQ : PDI_binop_rmi<0xD3, 0x73, MRM2r, "psrlq", X86vsrl, X86vsrli,
4190 VR128, v2i64, v2i64, bc_v2i64, memopv2i64,
4191 SSE_INTSHIFT_ITINS_P>;
4193 defm PSRAW : PDI_binop_rmi<0xE1, 0x71, MRM4r, "psraw", X86vsra, X86vsrai,
4194 VR128, v8i16, v8i16, bc_v8i16, memopv2i64,
4195 SSE_INTSHIFT_ITINS_P>;
4196 defm PSRAD : PDI_binop_rmi<0xE2, 0x72, MRM4r, "psrad", X86vsra, X86vsrai,
4197 VR128, v4i32, v4i32, bc_v4i32, memopv2i64,
4198 SSE_INTSHIFT_ITINS_P>;
4200 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecShift], hasSideEffects = 0 in {
4201 // 128-bit logical shifts.
4202 def PSLLDQri : PDIi8<0x73, MRM7r,
4203 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4204 "pslldq\t{$src2, $dst|$dst, $src2}",
4206 (v2i64 (X86vshldq VR128:$src1, (i8 imm:$src2))))],
4207 IIC_SSE_INTSHDQ_P_RI>;
4208 def PSRLDQri : PDIi8<0x73, MRM3r,
4209 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4210 "psrldq\t{$src2, $dst|$dst, $src2}",
4212 (v2i64 (X86vshrdq VR128:$src1, (i8 imm:$src2))))],
4213 IIC_SSE_INTSHDQ_P_RI>;
4214 // PSRADQri doesn't exist in SSE[1-3].
4216 } // Constraints = "$src1 = $dst"
4218 let Predicates = [HasAVX] in {
4219 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4220 (VPSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4223 let Predicates = [UseSSE2] in {
4224 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
4225 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2))>;
4228 //===---------------------------------------------------------------------===//
4229 // SSE2 - Packed Integer Comparison Instructions
4230 //===---------------------------------------------------------------------===//
4232 defm PCMPEQB : PDI_binop_all<0x74, "pcmpeqb", X86pcmpeq, v16i8, v32i8,
4233 SSE_INTALU_ITINS_P, 1>;
4234 defm PCMPEQW : PDI_binop_all<0x75, "pcmpeqw", X86pcmpeq, v8i16, v16i16,
4235 SSE_INTALU_ITINS_P, 1>;
4236 defm PCMPEQD : PDI_binop_all<0x76, "pcmpeqd", X86pcmpeq, v4i32, v8i32,
4237 SSE_INTALU_ITINS_P, 1>;
4238 defm PCMPGTB : PDI_binop_all<0x64, "pcmpgtb", X86pcmpgt, v16i8, v32i8,
4239 SSE_INTALU_ITINS_P, 0>;
4240 defm PCMPGTW : PDI_binop_all<0x65, "pcmpgtw", X86pcmpgt, v8i16, v16i16,
4241 SSE_INTALU_ITINS_P, 0>;
4242 defm PCMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
4243 SSE_INTALU_ITINS_P, 0>;
4245 //===---------------------------------------------------------------------===//
4246 // SSE2 - Packed Integer Shuffle Instructions
4247 //===---------------------------------------------------------------------===//
4249 let ExeDomain = SSEPackedInt in {
4250 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt128, ValueType vt256,
4252 let Predicates = [HasAVX] in {
4253 def V#NAME#ri : Ii8<0x70, MRMSrcReg, (outs VR128:$dst),
4254 (ins VR128:$src1, u8imm:$src2),
4255 !strconcat("v", OpcodeStr,
4256 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4258 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4259 IIC_SSE_PSHUF_RI>, VEX, Sched<[WriteShuffle]>;
4260 def V#NAME#mi : Ii8<0x70, MRMSrcMem, (outs VR128:$dst),
4261 (ins i128mem:$src1, u8imm:$src2),
4262 !strconcat("v", OpcodeStr,
4263 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4265 (vt128 (OpNode (bitconvert (loadv2i64 addr:$src1)),
4266 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX,
4267 Sched<[WriteShuffleLd]>;
4270 let Predicates = [HasAVX2] in {
4271 def V#NAME#Yri : Ii8<0x70, MRMSrcReg, (outs VR256:$dst),
4272 (ins VR256:$src1, u8imm:$src2),
4273 !strconcat("v", OpcodeStr,
4274 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4276 (vt256 (OpNode VR256:$src1, (i8 imm:$src2))))],
4277 IIC_SSE_PSHUF_RI>, VEX, VEX_L, Sched<[WriteShuffle]>;
4278 def V#NAME#Ymi : Ii8<0x70, MRMSrcMem, (outs VR256:$dst),
4279 (ins i256mem:$src1, u8imm:$src2),
4280 !strconcat("v", OpcodeStr,
4281 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4283 (vt256 (OpNode (bitconvert (loadv4i64 addr:$src1)),
4284 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>, VEX, VEX_L,
4285 Sched<[WriteShuffleLd]>;
4288 let Predicates = [UseSSE2] in {
4289 def ri : Ii8<0x70, MRMSrcReg,
4290 (outs VR128:$dst), (ins VR128:$src1, u8imm:$src2),
4291 !strconcat(OpcodeStr,
4292 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4294 (vt128 (OpNode VR128:$src1, (i8 imm:$src2))))],
4295 IIC_SSE_PSHUF_RI>, Sched<[WriteShuffle]>;
4296 def mi : Ii8<0x70, MRMSrcMem,
4297 (outs VR128:$dst), (ins i128mem:$src1, u8imm:$src2),
4298 !strconcat(OpcodeStr,
4299 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4301 (vt128 (OpNode (bitconvert (memopv2i64 addr:$src1)),
4302 (i8 imm:$src2))))], IIC_SSE_PSHUF_MI>,
4303 Sched<[WriteShuffleLd, ReadAfterLd]>;
4306 } // ExeDomain = SSEPackedInt
4308 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, v8i32, X86PShufd>, PD;
4309 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, v16i16, X86PShufhw>, XS;
4310 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, v16i16, X86PShuflw>, XD;
4312 let Predicates = [HasAVX] in {
4313 def : Pat<(v4f32 (X86PShufd (loadv4f32 addr:$src1), (i8 imm:$imm))),
4314 (VPSHUFDmi addr:$src1, imm:$imm)>;
4315 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4316 (VPSHUFDri VR128:$src1, imm:$imm)>;
4319 let Predicates = [UseSSE2] in {
4320 def : Pat<(v4f32 (X86PShufd (memopv4f32 addr:$src1), (i8 imm:$imm))),
4321 (PSHUFDmi addr:$src1, imm:$imm)>;
4322 def : Pat<(v4f32 (X86PShufd VR128:$src1, (i8 imm:$imm))),
4323 (PSHUFDri VR128:$src1, imm:$imm)>;
4326 //===---------------------------------------------------------------------===//
4327 // Packed Integer Pack Instructions (SSE & AVX)
4328 //===---------------------------------------------------------------------===//
4330 let ExeDomain = SSEPackedInt in {
4331 multiclass sse2_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4332 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4333 PatFrag ld_frag, bit Is2Addr = 1> {
4334 def rr : PDI<opc, MRMSrcReg,
4335 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4338 !strconcat(OpcodeStr,
4339 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4341 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4342 Sched<[WriteShuffle]>;
4343 def rm : PDI<opc, MRMSrcMem,
4344 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4346 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4347 !strconcat(OpcodeStr,
4348 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4350 (OutVT (OpNode VR128:$src1,
4351 (bc_frag (ld_frag addr:$src2)))))]>,
4352 Sched<[WriteShuffleLd, ReadAfterLd]>;
4355 multiclass sse2_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4356 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4357 def Yrr : PDI<opc, MRMSrcReg,
4358 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4359 !strconcat(OpcodeStr,
4360 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4362 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4363 Sched<[WriteShuffle]>;
4364 def Yrm : PDI<opc, MRMSrcMem,
4365 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4366 !strconcat(OpcodeStr,
4367 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4369 (OutVT (OpNode VR256:$src1,
4370 (bc_frag (loadv4i64 addr:$src2)))))]>,
4371 Sched<[WriteShuffleLd, ReadAfterLd]>;
4374 multiclass sse4_pack<bits<8> opc, string OpcodeStr, ValueType OutVT,
4375 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag,
4376 PatFrag ld_frag, bit Is2Addr = 1> {
4377 def rr : SS48I<opc, MRMSrcReg,
4378 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4380 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4381 !strconcat(OpcodeStr,
4382 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4384 (OutVT (OpNode (ArgVT VR128:$src1), VR128:$src2)))]>,
4385 Sched<[WriteShuffle]>;
4386 def rm : SS48I<opc, MRMSrcMem,
4387 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4389 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4390 !strconcat(OpcodeStr,
4391 "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4393 (OutVT (OpNode VR128:$src1,
4394 (bc_frag (ld_frag addr:$src2)))))]>,
4395 Sched<[WriteShuffleLd, ReadAfterLd]>;
4398 multiclass sse4_pack_y<bits<8> opc, string OpcodeStr, ValueType OutVT,
4399 ValueType ArgVT, SDNode OpNode, PatFrag bc_frag> {
4400 def Yrr : SS48I<opc, MRMSrcReg,
4401 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4402 !strconcat(OpcodeStr,
4403 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4405 (OutVT (OpNode (ArgVT VR256:$src1), VR256:$src2)))]>,
4406 Sched<[WriteShuffle]>;
4407 def Yrm : SS48I<opc, MRMSrcMem,
4408 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4409 !strconcat(OpcodeStr,
4410 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4412 (OutVT (OpNode VR256:$src1,
4413 (bc_frag (loadv4i64 addr:$src2)))))]>,
4414 Sched<[WriteShuffleLd, ReadAfterLd]>;
4417 let Predicates = [HasAVX] in {
4418 defm VPACKSSWB : sse2_pack<0x63, "vpacksswb", v16i8, v8i16, X86Packss,
4419 bc_v8i16, loadv2i64, 0>, VEX_4V;
4420 defm VPACKSSDW : sse2_pack<0x6B, "vpackssdw", v8i16, v4i32, X86Packss,
4421 bc_v4i32, loadv2i64, 0>, VEX_4V;
4423 defm VPACKUSWB : sse2_pack<0x67, "vpackuswb", v16i8, v8i16, X86Packus,
4424 bc_v8i16, loadv2i64, 0>, VEX_4V;
4425 defm VPACKUSDW : sse4_pack<0x2B, "vpackusdw", v8i16, v4i32, X86Packus,
4426 bc_v4i32, loadv2i64, 0>, VEX_4V;
4429 let Predicates = [HasAVX2] in {
4430 defm VPACKSSWB : sse2_pack_y<0x63, "vpacksswb", v32i8, v16i16, X86Packss,
4431 bc_v16i16>, VEX_4V, VEX_L;
4432 defm VPACKSSDW : sse2_pack_y<0x6B, "vpackssdw", v16i16, v8i32, X86Packss,
4433 bc_v8i32>, VEX_4V, VEX_L;
4435 defm VPACKUSWB : sse2_pack_y<0x67, "vpackuswb", v32i8, v16i16, X86Packus,
4436 bc_v16i16>, VEX_4V, VEX_L;
4437 defm VPACKUSDW : sse4_pack_y<0x2B, "vpackusdw", v16i16, v8i32, X86Packus,
4438 bc_v8i32>, VEX_4V, VEX_L;
4441 let Constraints = "$src1 = $dst" in {
4442 defm PACKSSWB : sse2_pack<0x63, "packsswb", v16i8, v8i16, X86Packss,
4443 bc_v8i16, memopv2i64>;
4444 defm PACKSSDW : sse2_pack<0x6B, "packssdw", v8i16, v4i32, X86Packss,
4445 bc_v4i32, memopv2i64>;
4447 defm PACKUSWB : sse2_pack<0x67, "packuswb", v16i8, v8i16, X86Packus,
4448 bc_v8i16, memopv2i64>;
4450 let Predicates = [HasSSE41] in
4451 defm PACKUSDW : sse4_pack<0x2B, "packusdw", v8i16, v4i32, X86Packus,
4452 bc_v4i32, memopv2i64>;
4454 } // ExeDomain = SSEPackedInt
4456 //===---------------------------------------------------------------------===//
4457 // SSE2 - Packed Integer Unpack Instructions
4458 //===---------------------------------------------------------------------===//
4460 let ExeDomain = SSEPackedInt in {
4461 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
4462 SDNode OpNode, PatFrag bc_frag, PatFrag ld_frag,
4464 def rr : PDI<opc, MRMSrcReg,
4465 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
4467 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4468 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4469 [(set VR128:$dst, (vt (OpNode VR128:$src1, VR128:$src2)))],
4470 IIC_SSE_UNPCK>, Sched<[WriteShuffle]>;
4471 def rm : PDI<opc, MRMSrcMem,
4472 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
4474 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
4475 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4476 [(set VR128:$dst, (OpNode VR128:$src1,
4477 (bc_frag (ld_frag addr:$src2))))],
4479 Sched<[WriteShuffleLd, ReadAfterLd]>;
4482 multiclass sse2_unpack_y<bits<8> opc, string OpcodeStr, ValueType vt,
4483 SDNode OpNode, PatFrag bc_frag> {
4484 def Yrr : PDI<opc, MRMSrcReg,
4485 (outs VR256:$dst), (ins VR256:$src1, VR256:$src2),
4486 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4487 [(set VR256:$dst, (vt (OpNode VR256:$src1, VR256:$src2)))]>,
4488 Sched<[WriteShuffle]>;
4489 def Yrm : PDI<opc, MRMSrcMem,
4490 (outs VR256:$dst), (ins VR256:$src1, i256mem:$src2),
4491 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4492 [(set VR256:$dst, (OpNode VR256:$src1,
4493 (bc_frag (loadv4i64 addr:$src2))))]>,
4494 Sched<[WriteShuffleLd, ReadAfterLd]>;
4497 let Predicates = [HasAVX] in {
4498 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, X86Unpckl,
4499 bc_v16i8, loadv2i64, 0>, VEX_4V;
4500 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, X86Unpckl,
4501 bc_v8i16, loadv2i64, 0>, VEX_4V;
4502 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, X86Unpckl,
4503 bc_v4i32, loadv2i64, 0>, VEX_4V;
4504 defm VPUNPCKLQDQ : sse2_unpack<0x6C, "vpunpcklqdq", v2i64, X86Unpckl,
4505 bc_v2i64, loadv2i64, 0>, VEX_4V;
4507 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, X86Unpckh,
4508 bc_v16i8, loadv2i64, 0>, VEX_4V;
4509 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, X86Unpckh,
4510 bc_v8i16, loadv2i64, 0>, VEX_4V;
4511 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, X86Unpckh,
4512 bc_v4i32, loadv2i64, 0>, VEX_4V;
4513 defm VPUNPCKHQDQ : sse2_unpack<0x6D, "vpunpckhqdq", v2i64, X86Unpckh,
4514 bc_v2i64, loadv2i64, 0>, VEX_4V;
4517 let Predicates = [HasAVX2] in {
4518 defm VPUNPCKLBW : sse2_unpack_y<0x60, "vpunpcklbw", v32i8, X86Unpckl,
4519 bc_v32i8>, VEX_4V, VEX_L;
4520 defm VPUNPCKLWD : sse2_unpack_y<0x61, "vpunpcklwd", v16i16, X86Unpckl,
4521 bc_v16i16>, VEX_4V, VEX_L;
4522 defm VPUNPCKLDQ : sse2_unpack_y<0x62, "vpunpckldq", v8i32, X86Unpckl,
4523 bc_v8i32>, VEX_4V, VEX_L;
4524 defm VPUNPCKLQDQ : sse2_unpack_y<0x6C, "vpunpcklqdq", v4i64, X86Unpckl,
4525 bc_v4i64>, VEX_4V, VEX_L;
4527 defm VPUNPCKHBW : sse2_unpack_y<0x68, "vpunpckhbw", v32i8, X86Unpckh,
4528 bc_v32i8>, VEX_4V, VEX_L;
4529 defm VPUNPCKHWD : sse2_unpack_y<0x69, "vpunpckhwd", v16i16, X86Unpckh,
4530 bc_v16i16>, VEX_4V, VEX_L;
4531 defm VPUNPCKHDQ : sse2_unpack_y<0x6A, "vpunpckhdq", v8i32, X86Unpckh,
4532 bc_v8i32>, VEX_4V, VEX_L;
4533 defm VPUNPCKHQDQ : sse2_unpack_y<0x6D, "vpunpckhqdq", v4i64, X86Unpckh,
4534 bc_v4i64>, VEX_4V, VEX_L;
4537 let Constraints = "$src1 = $dst" in {
4538 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, X86Unpckl,
4539 bc_v16i8, memopv2i64>;
4540 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, X86Unpckl,
4541 bc_v8i16, memopv2i64>;
4542 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, X86Unpckl,
4543 bc_v4i32, memopv2i64>;
4544 defm PUNPCKLQDQ : sse2_unpack<0x6C, "punpcklqdq", v2i64, X86Unpckl,
4545 bc_v2i64, memopv2i64>;
4547 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, X86Unpckh,
4548 bc_v16i8, memopv2i64>;
4549 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, X86Unpckh,
4550 bc_v8i16, memopv2i64>;
4551 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, X86Unpckh,
4552 bc_v4i32, memopv2i64>;
4553 defm PUNPCKHQDQ : sse2_unpack<0x6D, "punpckhqdq", v2i64, X86Unpckh,
4554 bc_v2i64, memopv2i64>;
4556 } // ExeDomain = SSEPackedInt
4558 //===---------------------------------------------------------------------===//
4559 // SSE2 - Packed Integer Extract and Insert
4560 //===---------------------------------------------------------------------===//
4562 let ExeDomain = SSEPackedInt in {
4563 multiclass sse2_pinsrw<bit Is2Addr = 1> {
4564 def rri : Ii8<0xC4, MRMSrcReg,
4565 (outs VR128:$dst), (ins VR128:$src1,
4566 GR32orGR64:$src2, u8imm:$src3),
4568 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4569 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4571 (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],
4572 IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;
4573 def rmi : Ii8<0xC4, MRMSrcMem,
4574 (outs VR128:$dst), (ins VR128:$src1,
4575 i16mem:$src2, u8imm:$src3),
4577 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
4578 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4580 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
4581 imm:$src3))], IIC_SSE_PINSRW>,
4582 Sched<[WriteShuffleLd, ReadAfterLd]>;
4586 let Predicates = [HasAVX] in
4587 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
4588 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4589 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4590 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4591 imm:$src2))]>, PD, VEX,
4592 Sched<[WriteShuffle]>;
4593 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
4594 (outs GR32orGR64:$dst), (ins VR128:$src1, u8imm:$src2),
4595 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4596 [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),
4597 imm:$src2))], IIC_SSE_PEXTRW>,
4598 Sched<[WriteShuffleLd, ReadAfterLd]>;
4601 let Predicates = [HasAVX] in
4602 defm VPINSRW : sse2_pinsrw<0>, PD, VEX_4V;
4604 let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in
4605 defm PINSRW : sse2_pinsrw, PD;
4607 } // ExeDomain = SSEPackedInt
4609 //===---------------------------------------------------------------------===//
4610 // SSE2 - Packed Mask Creation
4611 //===---------------------------------------------------------------------===//
4613 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
4615 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4617 "pmovmskb\t{$src, $dst|$dst, $src}",
4618 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4619 IIC_SSE_MOVMSK>, VEX;
4621 let Predicates = [HasAVX2] in {
4622 def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
4624 "pmovmskb\t{$src, $dst|$dst, $src}",
4625 [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,
4629 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
4630 "pmovmskb\t{$src, $dst|$dst, $src}",
4631 [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],
4634 } // ExeDomain = SSEPackedInt
4636 //===---------------------------------------------------------------------===//
4637 // SSE2 - Conditional Store
4638 //===---------------------------------------------------------------------===//
4640 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4642 let Uses = [EDI], Predicates = [HasAVX,Not64BitMode] in
4643 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
4644 (ins VR128:$src, VR128:$mask),
4645 "maskmovdqu\t{$mask, $src|$src, $mask}",
4646 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4647 IIC_SSE_MASKMOV>, VEX;
4648 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4649 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
4650 (ins VR128:$src, VR128:$mask),
4651 "maskmovdqu\t{$mask, $src|$src, $mask}",
4652 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4653 IIC_SSE_MASKMOV>, VEX;
4655 let Uses = [EDI], Predicates = [UseSSE2,Not64BitMode] in
4656 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4657 "maskmovdqu\t{$mask, $src|$src, $mask}",
4658 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)],
4660 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4661 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
4662 "maskmovdqu\t{$mask, $src|$src, $mask}",
4663 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)],
4666 } // ExeDomain = SSEPackedInt
4668 //===---------------------------------------------------------------------===//
4669 // SSE2 - Move Doubleword
4670 //===---------------------------------------------------------------------===//
4672 //===---------------------------------------------------------------------===//
4673 // Move Int Doubleword to Packed Double Int
4675 def VMOVDI2PDIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4676 "movd\t{$src, $dst|$dst, $src}",
4678 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4679 VEX, Sched<[WriteMove]>;
4680 def VMOVDI2PDIrm : VS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4681 "movd\t{$src, $dst|$dst, $src}",
4683 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4685 VEX, Sched<[WriteLoad]>;
4686 def VMOV64toPQIrr : VRS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4687 "movq\t{$src, $dst|$dst, $src}",
4689 (v2i64 (scalar_to_vector GR64:$src)))],
4690 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4691 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4692 def VMOV64toPQIrm : VRS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4693 "movq\t{$src, $dst|$dst, $src}",
4694 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteLoad]>;
4695 let isCodeGenOnly = 1 in
4696 def VMOV64toSDrr : VRS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4697 "movq\t{$src, $dst|$dst, $src}",
4698 [(set FR64:$dst, (bitconvert GR64:$src))],
4699 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4701 def MOVDI2PDIrr : S2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
4702 "movd\t{$src, $dst|$dst, $src}",
4704 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
4706 def MOVDI2PDIrm : S2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
4707 "movd\t{$src, $dst|$dst, $src}",
4709 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
4710 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4711 def MOV64toPQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4712 "mov{d|q}\t{$src, $dst|$dst, $src}",
4714 (v2i64 (scalar_to_vector GR64:$src)))],
4715 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4716 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
4717 def MOV64toPQIrm : RS2I<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4718 "mov{d|q}\t{$src, $dst|$dst, $src}",
4719 [], IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4720 let isCodeGenOnly = 1 in
4721 def MOV64toSDrr : RS2I<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
4722 "mov{d|q}\t{$src, $dst|$dst, $src}",
4723 [(set FR64:$dst, (bitconvert GR64:$src))],
4724 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4726 //===---------------------------------------------------------------------===//
4727 // Move Int Doubleword to Single Scalar
4729 let isCodeGenOnly = 1 in {
4730 def VMOVDI2SSrr : VS2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4731 "movd\t{$src, $dst|$dst, $src}",
4732 [(set FR32:$dst, (bitconvert GR32:$src))],
4733 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4735 def VMOVDI2SSrm : VS2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4736 "movd\t{$src, $dst|$dst, $src}",
4737 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4739 VEX, Sched<[WriteLoad]>;
4740 def MOVDI2SSrr : S2I<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
4741 "movd\t{$src, $dst|$dst, $src}",
4742 [(set FR32:$dst, (bitconvert GR32:$src))],
4743 IIC_SSE_MOVDQ>, Sched<[WriteMove]>;
4745 def MOVDI2SSrm : S2I<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
4746 "movd\t{$src, $dst|$dst, $src}",
4747 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))],
4748 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4751 //===---------------------------------------------------------------------===//
4752 // Move Packed Doubleword Int to Packed Double Int
4754 def VMOVPDI2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4755 "movd\t{$src, $dst|$dst, $src}",
4756 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4757 (iPTR 0)))], IIC_SSE_MOVD_ToGP>, VEX,
4759 def VMOVPDI2DImr : VS2I<0x7E, MRMDestMem, (outs),
4760 (ins i32mem:$dst, VR128:$src),
4761 "movd\t{$src, $dst|$dst, $src}",
4762 [(store (i32 (vector_extract (v4i32 VR128:$src),
4763 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
4764 VEX, Sched<[WriteStore]>;
4765 def MOVPDI2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
4766 "movd\t{$src, $dst|$dst, $src}",
4767 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
4768 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
4770 def MOVPDI2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
4771 "movd\t{$src, $dst|$dst, $src}",
4772 [(store (i32 (vector_extract (v4i32 VR128:$src),
4773 (iPTR 0))), addr:$dst)],
4774 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4776 def : Pat<(v8i32 (X86Vinsert (v8i32 immAllZerosV), GR32:$src2, (iPTR 0))),
4777 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4779 def : Pat<(v4i64 (X86Vinsert (bc_v4i64 (v8i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
4780 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4782 def : Pat<(v8i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
4783 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src2), sub_xmm)>;
4785 def : Pat<(v4i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
4786 (SUBREG_TO_REG (i32 0), (VMOV64toPQIrr GR64:$src2), sub_xmm)>;
4788 //===---------------------------------------------------------------------===//
4789 // Move Packed Doubleword Int first element to Doubleword Int
4791 let SchedRW = [WriteMove] in {
4792 def VMOVPQIto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4793 "movq\t{$src, $dst|$dst, $src}",
4794 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4799 def MOVPQIto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4800 "mov{d|q}\t{$src, $dst|$dst, $src}",
4801 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
4806 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4807 def VMOVPQIto64rm : VRS2I<0x7E, MRMDestMem, (outs i64mem:$dst),
4808 (ins VR128:$src), "movq\t{$src, $dst|$dst, $src}",
4809 [], IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4810 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
4811 def MOVPQIto64rm : RS2I<0x7E, MRMDestMem, (outs i64mem:$dst), (ins VR128:$src),
4812 "mov{d|q}\t{$src, $dst|$dst, $src}",
4813 [], IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4815 //===---------------------------------------------------------------------===//
4816 // Bitcast FR64 <-> GR64
4818 let isCodeGenOnly = 1 in {
4819 let Predicates = [UseAVX] in
4820 def VMOV64toSDrm : VS2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4821 "movq\t{$src, $dst|$dst, $src}",
4822 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>,
4823 VEX, Sched<[WriteLoad]>;
4824 def VMOVSDto64rr : VRS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4825 "movq\t{$src, $dst|$dst, $src}",
4826 [(set GR64:$dst, (bitconvert FR64:$src))],
4827 IIC_SSE_MOVDQ>, VEX, Sched<[WriteMove]>;
4828 def VMOVSDto64mr : VRS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4829 "movq\t{$src, $dst|$dst, $src}",
4830 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4831 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4833 def MOV64toSDrm : S2SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
4834 "movq\t{$src, $dst|$dst, $src}",
4835 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))],
4836 IIC_SSE_MOVDQ>, Sched<[WriteLoad]>;
4837 def MOVSDto64rr : RS2I<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
4838 "mov{d|q}\t{$src, $dst|$dst, $src}",
4839 [(set GR64:$dst, (bitconvert FR64:$src))],
4840 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4841 def MOVSDto64mr : RS2I<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
4842 "movq\t{$src, $dst|$dst, $src}",
4843 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
4844 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4847 //===---------------------------------------------------------------------===//
4848 // Move Scalar Single to Double Int
4850 let isCodeGenOnly = 1 in {
4851 def VMOVSS2DIrr : VS2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4852 "movd\t{$src, $dst|$dst, $src}",
4853 [(set GR32:$dst, (bitconvert FR32:$src))],
4854 IIC_SSE_MOVD_ToGP>, VEX, Sched<[WriteMove]>;
4855 def VMOVSS2DImr : VS2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4856 "movd\t{$src, $dst|$dst, $src}",
4857 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4858 IIC_SSE_MOVDQ>, VEX, Sched<[WriteStore]>;
4859 def MOVSS2DIrr : S2I<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
4860 "movd\t{$src, $dst|$dst, $src}",
4861 [(set GR32:$dst, (bitconvert FR32:$src))],
4862 IIC_SSE_MOVD_ToGP>, Sched<[WriteMove]>;
4863 def MOVSS2DImr : S2I<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
4864 "movd\t{$src, $dst|$dst, $src}",
4865 [(store (i32 (bitconvert FR32:$src)), addr:$dst)],
4866 IIC_SSE_MOVDQ>, Sched<[WriteStore]>;
4869 //===---------------------------------------------------------------------===//
4870 // Patterns and instructions to describe movd/movq to XMM register zero-extends
4872 let isCodeGenOnly = 1, SchedRW = [WriteMove] in {
4873 let AddedComplexity = 15 in {
4874 def VMOVZQI2PQIrr : VS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4875 "movq\t{$src, $dst|$dst, $src}", // X86-64 only
4876 [(set VR128:$dst, (v2i64 (X86vzmovl
4877 (v2i64 (scalar_to_vector GR64:$src)))))],
4880 def MOVZQI2PQIrr : RS2I<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
4881 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
4882 [(set VR128:$dst, (v2i64 (X86vzmovl
4883 (v2i64 (scalar_to_vector GR64:$src)))))],
4886 } // isCodeGenOnly, SchedRW
4888 let Predicates = [UseAVX] in {
4889 let AddedComplexity = 15 in
4890 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4891 (VMOVDI2PDIrr GR32:$src)>;
4893 // AVX 128-bit movd/movq instructions write zeros in the high 128-bit part.
4894 // These instructions also write zeros in the high part of a 256-bit register.
4895 let AddedComplexity = 20 in {
4896 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4897 (VMOVDI2PDIrm addr:$src)>;
4898 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4899 (VMOVDI2PDIrm addr:$src)>;
4900 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4901 (VMOVDI2PDIrm addr:$src)>;
4902 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4903 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
4904 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrm addr:$src), sub_xmm)>;
4906 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
4907 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
4908 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
4909 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIrr GR32:$src), sub_xmm)>;
4910 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
4911 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
4912 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrr GR64:$src), sub_xmm)>;
4915 let Predicates = [UseSSE2] in {
4916 let AddedComplexity = 15 in
4917 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
4918 (MOVDI2PDIrr GR32:$src)>;
4920 let AddedComplexity = 20 in {
4921 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
4922 (MOVDI2PDIrm addr:$src)>;
4923 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
4924 (MOVDI2PDIrm addr:$src)>;
4925 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
4926 (MOVDI2PDIrm addr:$src)>;
4930 // These are the correct encodings of the instructions so that we know how to
4931 // read correct assembly, even though we continue to emit the wrong ones for
4932 // compatibility with Darwin's buggy assembler.
4933 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4934 (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4935 def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
4936 (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4937 // Allow "vmovd" but print "vmovq" since we don't need compatibility for AVX.
4938 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4939 (VMOV64toPQIrr VR128:$dst, GR64:$src), 0>;
4940 def : InstAlias<"vmovd\t{$src, $dst|$dst, $src}",
4941 (VMOVPQIto64rr GR64:$dst, VR128:$src), 0>;
4943 //===---------------------------------------------------------------------===//
4944 // SSE2 - Move Quadword
4945 //===---------------------------------------------------------------------===//
4947 //===---------------------------------------------------------------------===//
4948 // Move Quadword Int to Packed Quadword Int
4951 let ExeDomain = SSEPackedInt, SchedRW = [WriteLoad] in {
4952 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4953 "vmovq\t{$src, $dst|$dst, $src}",
4955 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
4956 VEX, Requires<[UseAVX]>;
4957 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
4958 "movq\t{$src, $dst|$dst, $src}",
4960 (v2i64 (scalar_to_vector (loadi64 addr:$src))))],
4962 Requires<[UseSSE2]>; // SSE2 instruction with XS Prefix
4963 } // ExeDomain, SchedRW
4965 //===---------------------------------------------------------------------===//
4966 // Move Packed Quadword Int to Quadword Int
4968 let ExeDomain = SSEPackedInt, SchedRW = [WriteStore] in {
4969 def VMOVPQI2QImr : VS2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4970 "movq\t{$src, $dst|$dst, $src}",
4971 [(store (i64 (vector_extract (v2i64 VR128:$src),
4972 (iPTR 0))), addr:$dst)],
4973 IIC_SSE_MOVDQ>, VEX;
4974 def MOVPQI2QImr : S2I<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
4975 "movq\t{$src, $dst|$dst, $src}",
4976 [(store (i64 (vector_extract (v2i64 VR128:$src),
4977 (iPTR 0))), addr:$dst)],
4979 } // ExeDomain, SchedRW
4981 // For disassembler only
4982 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
4983 SchedRW = [WriteVecLogic] in {
4984 def VMOVPQI2QIrr : VS2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4985 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>, VEX;
4986 def MOVPQI2QIrr : S2I<0xD6, MRMDestReg, (outs VR128:$dst), (ins VR128:$src),
4987 "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>;
4990 //===---------------------------------------------------------------------===//
4991 // Store / copy lower 64-bits of a XMM register.
4993 let Predicates = [UseAVX] in
4994 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4995 (VMOVPQI2QImr addr:$dst, VR128:$src)>;
4996 let Predicates = [UseSSE2] in
4997 def : Pat<(int_x86_sse2_storel_dq addr:$dst, VR128:$src),
4998 (MOVPQI2QImr addr:$dst, VR128:$src)>;
5000 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, AddedComplexity = 20 in {
5001 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5002 "vmovq\t{$src, $dst|$dst, $src}",
5004 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5005 (loadi64 addr:$src))))))],
5007 XS, VEX, Requires<[UseAVX]>, Sched<[WriteLoad]>;
5009 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
5010 "movq\t{$src, $dst|$dst, $src}",
5012 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
5013 (loadi64 addr:$src))))))],
5015 XS, Requires<[UseSSE2]>, Sched<[WriteLoad]>;
5016 } // ExeDomain, isCodeGenOnly, AddedComplexity
5018 let Predicates = [UseAVX], AddedComplexity = 20 in {
5019 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5020 (VMOVZQI2PQIrm addr:$src)>;
5021 def : Pat<(v2i64 (X86vzload addr:$src)),
5022 (VMOVZQI2PQIrm addr:$src)>;
5023 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
5024 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
5025 (SUBREG_TO_REG (i64 0), (VMOVZQI2PQIrm addr:$src), sub_xmm)>;
5028 let Predicates = [UseSSE2], AddedComplexity = 20 in {
5029 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
5030 (MOVZQI2PQIrm addr:$src)>;
5031 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
5034 let Predicates = [HasAVX] in {
5035 def : Pat<(v4i64 (alignedX86vzload addr:$src)),
5036 (SUBREG_TO_REG (i32 0), (VMOVAPSrm addr:$src), sub_xmm)>;
5037 def : Pat<(v4i64 (X86vzload addr:$src)),
5038 (SUBREG_TO_REG (i32 0), (VMOVUPSrm addr:$src), sub_xmm)>;
5041 //===---------------------------------------------------------------------===//
5042 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
5043 // IA32 document. movq xmm1, xmm2 does clear the high bits.
5045 let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
5046 let AddedComplexity = 15 in
5047 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5048 "vmovq\t{$src, $dst|$dst, $src}",
5049 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5051 XS, VEX, Requires<[UseAVX]>;
5052 let AddedComplexity = 15 in
5053 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5054 "movq\t{$src, $dst|$dst, $src}",
5055 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))],
5057 XS, Requires<[UseSSE2]>;
5058 } // ExeDomain, SchedRW
5060 let ExeDomain = SSEPackedInt, isCodeGenOnly = 1, SchedRW = [WriteVecLogicLd] in {
5061 let AddedComplexity = 20 in
5062 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5063 "vmovq\t{$src, $dst|$dst, $src}",
5064 [(set VR128:$dst, (v2i64 (X86vzmovl
5065 (loadv2i64 addr:$src))))],
5067 XS, VEX, Requires<[UseAVX]>;
5068 let AddedComplexity = 20 in {
5069 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5070 "movq\t{$src, $dst|$dst, $src}",
5071 [(set VR128:$dst, (v2i64 (X86vzmovl
5072 (loadv2i64 addr:$src))))],
5074 XS, Requires<[UseSSE2]>;
5076 } // ExeDomain, isCodeGenOnly, SchedRW
5078 let AddedComplexity = 20 in {
5079 let Predicates = [UseAVX] in {
5080 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5081 (VMOVZPQILo2PQIrr VR128:$src)>;
5083 let Predicates = [UseSSE2] in {
5084 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
5085 (MOVZPQILo2PQIrr VR128:$src)>;
5089 //===---------------------------------------------------------------------===//
5090 // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
5091 //===---------------------------------------------------------------------===//
5092 multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
5093 ValueType vt, RegisterClass RC, PatFrag mem_frag,
5094 X86MemOperand x86memop> {
5095 def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
5096 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5097 [(set RC:$dst, (vt (OpNode RC:$src)))],
5098 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5099 def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
5100 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5101 [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
5102 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5105 let Predicates = [HasAVX] in {
5106 defm VMOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5107 v4f32, VR128, loadv4f32, f128mem>, VEX;
5108 defm VMOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5109 v4f32, VR128, loadv4f32, f128mem>, VEX;
5110 defm VMOVSHDUPY : sse3_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
5111 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5112 defm VMOVSLDUPY : sse3_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
5113 v8f32, VR256, loadv8f32, f256mem>, VEX, VEX_L;
5115 defm MOVSHDUP : sse3_replicate_sfp<0x16, X86Movshdup, "movshdup", v4f32, VR128,
5116 memopv4f32, f128mem>;
5117 defm MOVSLDUP : sse3_replicate_sfp<0x12, X86Movsldup, "movsldup", v4f32, VR128,
5118 memopv4f32, f128mem>;
5120 let Predicates = [HasAVX] in {
5121 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5122 (VMOVSHDUPrr VR128:$src)>;
5123 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (loadv2i64 addr:$src)))),
5124 (VMOVSHDUPrm addr:$src)>;
5125 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5126 (VMOVSLDUPrr VR128:$src)>;
5127 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (loadv2i64 addr:$src)))),
5128 (VMOVSLDUPrm addr:$src)>;
5129 def : Pat<(v8i32 (X86Movshdup VR256:$src)),
5130 (VMOVSHDUPYrr VR256:$src)>;
5131 def : Pat<(v8i32 (X86Movshdup (bc_v8i32 (loadv4i64 addr:$src)))),
5132 (VMOVSHDUPYrm addr:$src)>;
5133 def : Pat<(v8i32 (X86Movsldup VR256:$src)),
5134 (VMOVSLDUPYrr VR256:$src)>;
5135 def : Pat<(v8i32 (X86Movsldup (bc_v8i32 (loadv4i64 addr:$src)))),
5136 (VMOVSLDUPYrm addr:$src)>;
5139 let Predicates = [UseSSE3] in {
5140 def : Pat<(v4i32 (X86Movshdup VR128:$src)),
5141 (MOVSHDUPrr VR128:$src)>;
5142 def : Pat<(v4i32 (X86Movshdup (bc_v4i32 (memopv2i64 addr:$src)))),
5143 (MOVSHDUPrm addr:$src)>;
5144 def : Pat<(v4i32 (X86Movsldup VR128:$src)),
5145 (MOVSLDUPrr VR128:$src)>;
5146 def : Pat<(v4i32 (X86Movsldup (bc_v4i32 (memopv2i64 addr:$src)))),
5147 (MOVSLDUPrm addr:$src)>;
5150 //===---------------------------------------------------------------------===//
5151 // SSE3 - Replicate Double FP - MOVDDUP
5152 //===---------------------------------------------------------------------===//
5154 multiclass sse3_replicate_dfp<string OpcodeStr> {
5155 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
5156 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5157 [(set VR128:$dst, (v2f64 (X86Movddup VR128:$src)))],
5158 IIC_SSE_MOV_LH>, Sched<[WriteFShuffle]>;
5159 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
5160 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5163 (scalar_to_vector (loadf64 addr:$src)))))],
5164 IIC_SSE_MOV_LH>, Sched<[WriteLoad]>;
5167 // FIXME: Merge with above classe when there're patterns for the ymm version
5168 multiclass sse3_replicate_dfp_y<string OpcodeStr> {
5169 def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
5170 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5171 [(set VR256:$dst, (v4f64 (X86Movddup VR256:$src)))]>,
5172 Sched<[WriteFShuffle]>;
5173 def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
5174 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5177 (scalar_to_vector (loadf64 addr:$src)))))]>,
5181 let Predicates = [HasAVX] in {
5182 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
5183 defm VMOVDDUPY : sse3_replicate_dfp_y<"vmovddup">, VEX, VEX_L;
5186 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
5188 let Predicates = [HasAVX] in {
5189 def : Pat<(X86Movddup (loadv2f64 addr:$src)),
5190 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5191 def : Pat<(X86Movddup (bc_v2f64 (loadv4f32 addr:$src))),
5192 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5193 def : Pat<(X86Movddup (bc_v2f64 (loadv2i64 addr:$src))),
5194 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5195 def : Pat<(X86Movddup (bc_v2f64
5196 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5197 (VMOVDDUPrm addr:$src)>, Requires<[HasAVX]>;
5200 def : Pat<(X86Movddup (loadv4f64 addr:$src)),
5201 (VMOVDDUPYrm addr:$src)>;
5202 def : Pat<(X86Movddup (loadv4i64 addr:$src)),
5203 (VMOVDDUPYrm addr:$src)>;
5204 def : Pat<(X86Movddup (v4i64 (scalar_to_vector (loadi64 addr:$src)))),
5205 (VMOVDDUPYrm addr:$src)>;
5206 def : Pat<(X86Movddup (v4i64 VR256:$src)),
5207 (VMOVDDUPYrr VR256:$src)>;
5210 let Predicates = [UseAVX, OptForSize] in {
5211 def : Pat<(v2f64 (X86VBroadcast (loadf64 addr:$src))),
5212 (VMOVDDUPrm addr:$src)>;
5213 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
5214 (VMOVDDUPrm addr:$src)>;
5217 let Predicates = [UseSSE3] in {
5218 def : Pat<(X86Movddup (memopv2f64 addr:$src)),
5219 (MOVDDUPrm addr:$src)>;
5220 def : Pat<(X86Movddup (bc_v2f64 (memopv4f32 addr:$src))),
5221 (MOVDDUPrm addr:$src)>;
5222 def : Pat<(X86Movddup (bc_v2f64 (memopv2i64 addr:$src))),
5223 (MOVDDUPrm addr:$src)>;
5224 def : Pat<(X86Movddup (bc_v2f64
5225 (v2i64 (scalar_to_vector (loadi64 addr:$src))))),
5226 (MOVDDUPrm addr:$src)>;
5229 //===---------------------------------------------------------------------===//
5230 // SSE3 - Move Unaligned Integer
5231 //===---------------------------------------------------------------------===//
5233 let SchedRW = [WriteLoad] in {
5234 let Predicates = [HasAVX] in {
5235 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5236 "vlddqu\t{$src, $dst|$dst, $src}",
5237 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
5238 def VLDDQUYrm : S3DI<0xF0, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
5239 "vlddqu\t{$src, $dst|$dst, $src}",
5240 [(set VR256:$dst, (int_x86_avx_ldu_dq_256 addr:$src))]>,
5243 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
5244 "lddqu\t{$src, $dst|$dst, $src}",
5245 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))],
5249 //===---------------------------------------------------------------------===//
5250 // SSE3 - Arithmetic
5251 //===---------------------------------------------------------------------===//
5253 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, RegisterClass RC,
5254 X86MemOperand x86memop, OpndItins itins,
5255 PatFrag ld_frag, bit Is2Addr = 1> {
5256 def rr : I<0xD0, MRMSrcReg,
5257 (outs RC:$dst), (ins RC:$src1, RC:$src2),
5259 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5261 [(set RC:$dst, (Int RC:$src1, RC:$src2))], itins.rr>,
5262 Sched<[itins.Sched]>;
5263 def rm : I<0xD0, MRMSrcMem,
5264 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5266 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5267 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5268 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))], itins.rr>,
5269 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5272 let Predicates = [HasAVX] in {
5273 let ExeDomain = SSEPackedSingle in {
5274 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", VR128,
5275 f128mem, SSE_ALU_F32P, loadv4f32, 0>, XD, VEX_4V;
5276 defm VADDSUBPSY : sse3_addsub<int_x86_avx_addsub_ps_256, "vaddsubps", VR256,
5277 f256mem, SSE_ALU_F32P, loadv8f32, 0>, XD, VEX_4V, VEX_L;
5279 let ExeDomain = SSEPackedDouble in {
5280 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", VR128,
5281 f128mem, SSE_ALU_F64P, loadv2f64, 0>, PD, VEX_4V;
5282 defm VADDSUBPDY : sse3_addsub<int_x86_avx_addsub_pd_256, "vaddsubpd", VR256,
5283 f256mem, SSE_ALU_F64P, loadv4f64, 0>, PD, VEX_4V, VEX_L;
5286 let Constraints = "$src1 = $dst", Predicates = [UseSSE3] in {
5287 let ExeDomain = SSEPackedSingle in
5288 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps", VR128,
5289 f128mem, SSE_ALU_F32P, memopv4f32>, XD;
5290 let ExeDomain = SSEPackedDouble in
5291 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd", VR128,
5292 f128mem, SSE_ALU_F64P, memopv2f64>, PD;
5295 // Patterns used to select 'addsub' instructions.
5296 let Predicates = [HasAVX] in {
5297 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5298 (VADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5299 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (loadv4f32 addr:$rhs))),
5300 (VADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5301 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5302 (VADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5303 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (loadv2f64 addr:$rhs))),
5304 (VADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5306 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (v8f32 VR256:$rhs))),
5307 (VADDSUBPSYrr VR256:$lhs, VR256:$rhs)>;
5308 def : Pat<(v8f32 (X86Addsub (v8f32 VR256:$lhs), (loadv8f32 addr:$rhs))),
5309 (VADDSUBPSYrm VR256:$lhs, f256mem:$rhs)>;
5310 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (v4f64 VR256:$rhs))),
5311 (VADDSUBPDYrr VR256:$lhs, VR256:$rhs)>;
5312 def : Pat<(v4f64 (X86Addsub (v4f64 VR256:$lhs), (loadv4f64 addr:$rhs))),
5313 (VADDSUBPDYrm VR256:$lhs, f256mem:$rhs)>;
5316 let Predicates = [UseSSE3] in {
5317 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (v4f32 VR128:$rhs))),
5318 (ADDSUBPSrr VR128:$lhs, VR128:$rhs)>;
5319 def : Pat<(v4f32 (X86Addsub (v4f32 VR128:$lhs), (memopv4f32 addr:$rhs))),
5320 (ADDSUBPSrm VR128:$lhs, f128mem:$rhs)>;
5321 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (v2f64 VR128:$rhs))),
5322 (ADDSUBPDrr VR128:$lhs, VR128:$rhs)>;
5323 def : Pat<(v2f64 (X86Addsub (v2f64 VR128:$lhs), (memopv2f64 addr:$rhs))),
5324 (ADDSUBPDrm VR128:$lhs, f128mem:$rhs)>;
5327 //===---------------------------------------------------------------------===//
5328 // SSE3 Instructions
5329 //===---------------------------------------------------------------------===//
5332 multiclass S3D_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5333 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5335 def rr : S3DI<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5338 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5339 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5342 def rm : S3DI<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5344 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5345 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5346 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5347 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5349 multiclass S3_Int<bits<8> o, string OpcodeStr, ValueType vt, RegisterClass RC,
5350 X86MemOperand x86memop, SDNode OpNode, PatFrag ld_frag,
5352 def rr : S3I<o, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
5354 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5355 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5356 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], IIC_SSE_HADDSUB_RR>,
5359 def rm : S3I<o, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
5361 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5362 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5363 [(set RC:$dst, (vt (OpNode RC:$src1, (ld_frag addr:$src2))))],
5364 IIC_SSE_HADDSUB_RM>, Sched<[WriteFAddLd, ReadAfterLd]>;
5367 let Predicates = [HasAVX] in {
5368 let ExeDomain = SSEPackedSingle in {
5369 defm VHADDPS : S3D_Int<0x7C, "vhaddps", v4f32, VR128, f128mem,
5370 X86fhadd, loadv4f32, 0>, VEX_4V;
5371 defm VHSUBPS : S3D_Int<0x7D, "vhsubps", v4f32, VR128, f128mem,
5372 X86fhsub, loadv4f32, 0>, VEX_4V;
5373 defm VHADDPSY : S3D_Int<0x7C, "vhaddps", v8f32, VR256, f256mem,
5374 X86fhadd, loadv8f32, 0>, VEX_4V, VEX_L;
5375 defm VHSUBPSY : S3D_Int<0x7D, "vhsubps", v8f32, VR256, f256mem,
5376 X86fhsub, loadv8f32, 0>, VEX_4V, VEX_L;
5378 let ExeDomain = SSEPackedDouble in {
5379 defm VHADDPD : S3_Int <0x7C, "vhaddpd", v2f64, VR128, f128mem,
5380 X86fhadd, loadv2f64, 0>, VEX_4V;
5381 defm VHSUBPD : S3_Int <0x7D, "vhsubpd", v2f64, VR128, f128mem,
5382 X86fhsub, loadv2f64, 0>, VEX_4V;
5383 defm VHADDPDY : S3_Int <0x7C, "vhaddpd", v4f64, VR256, f256mem,
5384 X86fhadd, loadv4f64, 0>, VEX_4V, VEX_L;
5385 defm VHSUBPDY : S3_Int <0x7D, "vhsubpd", v4f64, VR256, f256mem,
5386 X86fhsub, loadv4f64, 0>, VEX_4V, VEX_L;
5390 let Constraints = "$src1 = $dst" in {
5391 let ExeDomain = SSEPackedSingle in {
5392 defm HADDPS : S3D_Int<0x7C, "haddps", v4f32, VR128, f128mem, X86fhadd,
5394 defm HSUBPS : S3D_Int<0x7D, "hsubps", v4f32, VR128, f128mem, X86fhsub,
5397 let ExeDomain = SSEPackedDouble in {
5398 defm HADDPD : S3_Int<0x7C, "haddpd", v2f64, VR128, f128mem, X86fhadd,
5400 defm HSUBPD : S3_Int<0x7D, "hsubpd", v2f64, VR128, f128mem, X86fhsub,
5405 //===---------------------------------------------------------------------===//
5406 // SSSE3 - Packed Absolute Instructions
5407 //===---------------------------------------------------------------------===//
5410 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5411 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
5413 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5415 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5416 [(set VR128:$dst, (IntId128 VR128:$src))], IIC_SSE_PABS_RR>,
5417 Sched<[WriteVecALU]>;
5419 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5421 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5424 (bitconvert (ld_frag addr:$src))))], IIC_SSE_PABS_RM>,
5425 Sched<[WriteVecALULd]>;
5428 /// SS3I_unop_rm_int_y - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
5429 multiclass SS3I_unop_rm_int_y<bits<8> opc, string OpcodeStr,
5430 Intrinsic IntId256> {
5431 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5433 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5434 [(set VR256:$dst, (IntId256 VR256:$src))]>,
5435 Sched<[WriteVecALU]>;
5437 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5439 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5442 (bitconvert (loadv4i64 addr:$src))))]>,
5443 Sched<[WriteVecALULd]>;
5446 // Helper fragments to match sext vXi1 to vXiY.
5447 def v16i1sextv16i8 : PatLeaf<(v16i8 (X86pcmpgt (bc_v16i8 (v4i32 immAllZerosV)),
5449 def v8i1sextv8i16 : PatLeaf<(v8i16 (X86vsrai VR128:$src, (i8 15)))>;
5450 def v4i1sextv4i32 : PatLeaf<(v4i32 (X86vsrai VR128:$src, (i8 31)))>;
5451 def v32i1sextv32i8 : PatLeaf<(v32i8 (X86pcmpgt (bc_v32i8 (v8i32 immAllZerosV)),
5453 def v16i1sextv16i16: PatLeaf<(v16i16 (X86vsrai VR256:$src, (i8 15)))>;
5454 def v8i1sextv8i32 : PatLeaf<(v8i32 (X86vsrai VR256:$src, (i8 31)))>;
5456 let Predicates = [HasAVX] in {
5457 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", int_x86_ssse3_pabs_b_128,
5459 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", int_x86_ssse3_pabs_w_128,
5461 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", int_x86_ssse3_pabs_d_128,
5465 (bc_v2i64 (v16i1sextv16i8)),
5466 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5467 (VPABSBrr128 VR128:$src)>;
5469 (bc_v2i64 (v8i1sextv8i16)),
5470 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5471 (VPABSWrr128 VR128:$src)>;
5473 (bc_v2i64 (v4i1sextv4i32)),
5474 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5475 (VPABSDrr128 VR128:$src)>;
5478 let Predicates = [HasAVX2] in {
5479 defm VPABSB : SS3I_unop_rm_int_y<0x1C, "vpabsb",
5480 int_x86_avx2_pabs_b>, VEX, VEX_L;
5481 defm VPABSW : SS3I_unop_rm_int_y<0x1D, "vpabsw",
5482 int_x86_avx2_pabs_w>, VEX, VEX_L;
5483 defm VPABSD : SS3I_unop_rm_int_y<0x1E, "vpabsd",
5484 int_x86_avx2_pabs_d>, VEX, VEX_L;
5487 (bc_v4i64 (v32i1sextv32i8)),
5488 (bc_v4i64 (add (v32i8 VR256:$src), (v32i1sextv32i8)))),
5489 (VPABSBrr256 VR256:$src)>;
5491 (bc_v4i64 (v16i1sextv16i16)),
5492 (bc_v4i64 (add (v16i16 VR256:$src), (v16i1sextv16i16)))),
5493 (VPABSWrr256 VR256:$src)>;
5495 (bc_v4i64 (v8i1sextv8i32)),
5496 (bc_v4i64 (add (v8i32 VR256:$src), (v8i1sextv8i32)))),
5497 (VPABSDrr256 VR256:$src)>;
5500 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", int_x86_ssse3_pabs_b_128,
5502 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", int_x86_ssse3_pabs_w_128,
5504 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", int_x86_ssse3_pabs_d_128,
5507 let Predicates = [HasSSSE3] in {
5509 (bc_v2i64 (v16i1sextv16i8)),
5510 (bc_v2i64 (add (v16i8 VR128:$src), (v16i1sextv16i8)))),
5511 (PABSBrr128 VR128:$src)>;
5513 (bc_v2i64 (v8i1sextv8i16)),
5514 (bc_v2i64 (add (v8i16 VR128:$src), (v8i1sextv8i16)))),
5515 (PABSWrr128 VR128:$src)>;
5517 (bc_v2i64 (v4i1sextv4i32)),
5518 (bc_v2i64 (add (v4i32 VR128:$src), (v4i1sextv4i32)))),
5519 (PABSDrr128 VR128:$src)>;
5522 //===---------------------------------------------------------------------===//
5523 // SSSE3 - Packed Binary Operator Instructions
5524 //===---------------------------------------------------------------------===//
5526 let Sched = WriteVecALU in {
5527 def SSE_PHADDSUBD : OpndItins<
5528 IIC_SSE_PHADDSUBD_RR, IIC_SSE_PHADDSUBD_RM
5530 def SSE_PHADDSUBSW : OpndItins<
5531 IIC_SSE_PHADDSUBSW_RR, IIC_SSE_PHADDSUBSW_RM
5533 def SSE_PHADDSUBW : OpndItins<
5534 IIC_SSE_PHADDSUBW_RR, IIC_SSE_PHADDSUBW_RM
5537 let Sched = WriteShuffle in
5538 def SSE_PSHUFB : OpndItins<
5539 IIC_SSE_PSHUFB_RR, IIC_SSE_PSHUFB_RM
5541 let Sched = WriteVecALU in
5542 def SSE_PSIGN : OpndItins<
5543 IIC_SSE_PSIGN_RR, IIC_SSE_PSIGN_RM
5545 let Sched = WriteVecIMul in
5546 def SSE_PMULHRSW : OpndItins<
5547 IIC_SSE_PMULHRSW, IIC_SSE_PMULHRSW
5550 /// SS3I_binop_rm - Simple SSSE3 bin op
5551 multiclass SS3I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
5552 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
5553 X86MemOperand x86memop, OpndItins itins,
5555 let isCommutable = 1 in
5556 def rr : SS38I<opc, MRMSrcReg, (outs RC:$dst),
5557 (ins RC:$src1, RC:$src2),
5559 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5560 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5561 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))], itins.rr>,
5562 Sched<[itins.Sched]>;
5563 def rm : SS38I<opc, MRMSrcMem, (outs RC:$dst),
5564 (ins RC:$src1, x86memop:$src2),
5566 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5567 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5569 (OpVT (OpNode RC:$src1,
5570 (bitconvert (memop_frag addr:$src2)))))], itins.rm>,
5571 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5574 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
5575 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
5576 Intrinsic IntId128, OpndItins itins,
5577 PatFrag ld_frag, bit Is2Addr = 1> {
5578 let isCommutable = 1 in
5579 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
5580 (ins VR128:$src1, VR128:$src2),
5582 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5583 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5584 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
5585 Sched<[itins.Sched]>;
5586 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
5587 (ins VR128:$src1, i128mem:$src2),
5589 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
5590 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
5592 (IntId128 VR128:$src1,
5593 (bitconvert (ld_frag addr:$src2))))]>,
5594 Sched<[itins.Sched.Folded, ReadAfterLd]>;
5597 multiclass SS3I_binop_rm_int_y<bits<8> opc, string OpcodeStr,
5599 X86FoldableSchedWrite Sched> {
5600 let isCommutable = 1 in
5601 def rr256 : SS38I<opc, MRMSrcReg, (outs VR256:$dst),
5602 (ins VR256:$src1, VR256:$src2),
5603 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5604 [(set VR256:$dst, (IntId256 VR256:$src1, VR256:$src2))]>,
5606 def rm256 : SS38I<opc, MRMSrcMem, (outs VR256:$dst),
5607 (ins VR256:$src1, i256mem:$src2),
5608 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
5610 (IntId256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2))))]>,
5611 Sched<[Sched.Folded, ReadAfterLd]>;
5614 let ImmT = NoImm, Predicates = [HasAVX] in {
5615 let isCommutable = 0 in {
5616 defm VPHADDW : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v8i16, VR128,
5618 SSE_PHADDSUBW, 0>, VEX_4V;
5619 defm VPHADDD : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v4i32, VR128,
5621 SSE_PHADDSUBD, 0>, VEX_4V;
5622 defm VPHSUBW : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v8i16, VR128,
5624 SSE_PHADDSUBW, 0>, VEX_4V;
5625 defm VPHSUBD : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v4i32, VR128,
5627 SSE_PHADDSUBD, 0>, VEX_4V;
5628 defm VPSIGNB : SS3I_binop_rm<0x08, "vpsignb", X86psign, v16i8, VR128,
5630 SSE_PSIGN, 0>, VEX_4V;
5631 defm VPSIGNW : SS3I_binop_rm<0x09, "vpsignw", X86psign, v8i16, VR128,
5633 SSE_PSIGN, 0>, VEX_4V;
5634 defm VPSIGND : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v4i32, VR128,
5636 SSE_PSIGN, 0>, VEX_4V;
5637 defm VPSHUFB : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v16i8, VR128,
5639 SSE_PSHUFB, 0>, VEX_4V;
5640 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw",
5641 int_x86_ssse3_phadd_sw_128,
5642 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5643 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw",
5644 int_x86_ssse3_phsub_sw_128,
5645 SSE_PHADDSUBSW, loadv2i64, 0>, VEX_4V;
5646 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw",
5647 int_x86_ssse3_pmadd_ub_sw_128,
5648 SSE_PMADD, loadv2i64, 0>, VEX_4V;
5650 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw",
5651 int_x86_ssse3_pmul_hr_sw_128,
5652 SSE_PMULHRSW, loadv2i64, 0>, VEX_4V;
5655 let ImmT = NoImm, Predicates = [HasAVX2] in {
5656 let isCommutable = 0 in {
5657 defm VPHADDWY : SS3I_binop_rm<0x01, "vphaddw", X86hadd, v16i16, VR256,
5659 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5660 defm VPHADDDY : SS3I_binop_rm<0x02, "vphaddd", X86hadd, v8i32, VR256,
5662 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5663 defm VPHSUBWY : SS3I_binop_rm<0x05, "vphsubw", X86hsub, v16i16, VR256,
5665 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5666 defm VPHSUBDY : SS3I_binop_rm<0x06, "vphsubd", X86hsub, v8i32, VR256,
5668 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5669 defm VPSIGNBY : SS3I_binop_rm<0x08, "vpsignb", X86psign, v32i8, VR256,
5671 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5672 defm VPSIGNWY : SS3I_binop_rm<0x09, "vpsignw", X86psign, v16i16, VR256,
5674 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5675 defm VPSIGNDY : SS3I_binop_rm<0x0A, "vpsignd", X86psign, v8i32, VR256,
5677 SSE_PHADDSUBW, 0>, VEX_4V, VEX_L;
5678 defm VPSHUFBY : SS3I_binop_rm<0x00, "vpshufb", X86pshufb, v32i8, VR256,
5680 SSE_PSHUFB, 0>, VEX_4V, VEX_L;
5681 defm VPHADDSW : SS3I_binop_rm_int_y<0x03, "vphaddsw",
5682 int_x86_avx2_phadd_sw,
5683 WriteVecALU>, VEX_4V, VEX_L;
5684 defm VPHSUBSW : SS3I_binop_rm_int_y<0x07, "vphsubsw",
5685 int_x86_avx2_phsub_sw,
5686 WriteVecALU>, VEX_4V, VEX_L;
5687 defm VPMADDUBSW : SS3I_binop_rm_int_y<0x04, "vpmaddubsw",
5688 int_x86_avx2_pmadd_ub_sw,
5689 WriteVecIMul>, VEX_4V, VEX_L;
5691 defm VPMULHRSW : SS3I_binop_rm_int_y<0x0B, "vpmulhrsw",
5692 int_x86_avx2_pmul_hr_sw,
5693 WriteVecIMul>, VEX_4V, VEX_L;
5696 // None of these have i8 immediate fields.
5697 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
5698 let isCommutable = 0 in {
5699 defm PHADDW : SS3I_binop_rm<0x01, "phaddw", X86hadd, v8i16, VR128,
5700 memopv2i64, i128mem, SSE_PHADDSUBW>;
5701 defm PHADDD : SS3I_binop_rm<0x02, "phaddd", X86hadd, v4i32, VR128,
5702 memopv2i64, i128mem, SSE_PHADDSUBD>;
5703 defm PHSUBW : SS3I_binop_rm<0x05, "phsubw", X86hsub, v8i16, VR128,
5704 memopv2i64, i128mem, SSE_PHADDSUBW>;
5705 defm PHSUBD : SS3I_binop_rm<0x06, "phsubd", X86hsub, v4i32, VR128,
5706 memopv2i64, i128mem, SSE_PHADDSUBD>;
5707 defm PSIGNB : SS3I_binop_rm<0x08, "psignb", X86psign, v16i8, VR128,
5708 memopv2i64, i128mem, SSE_PSIGN>;
5709 defm PSIGNW : SS3I_binop_rm<0x09, "psignw", X86psign, v8i16, VR128,
5710 memopv2i64, i128mem, SSE_PSIGN>;
5711 defm PSIGND : SS3I_binop_rm<0x0A, "psignd", X86psign, v4i32, VR128,
5712 memopv2i64, i128mem, SSE_PSIGN>;
5713 defm PSHUFB : SS3I_binop_rm<0x00, "pshufb", X86pshufb, v16i8, VR128,
5714 memopv2i64, i128mem, SSE_PSHUFB>;
5715 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw",
5716 int_x86_ssse3_phadd_sw_128,
5717 SSE_PHADDSUBSW, memopv2i64>;
5718 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw",
5719 int_x86_ssse3_phsub_sw_128,
5720 SSE_PHADDSUBSW, memopv2i64>;
5721 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw",
5722 int_x86_ssse3_pmadd_ub_sw_128,
5723 SSE_PMADD, memopv2i64>;
5725 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw",
5726 int_x86_ssse3_pmul_hr_sw_128,
5727 SSE_PMULHRSW, memopv2i64>;
5730 //===---------------------------------------------------------------------===//
5731 // SSSE3 - Packed Align Instruction Patterns
5732 //===---------------------------------------------------------------------===//
5734 multiclass ssse3_palignr<string asm, bit Is2Addr = 1> {
5735 let hasSideEffects = 0 in {
5736 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
5737 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
5739 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5741 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5742 [], IIC_SSE_PALIGNRR>, Sched<[WriteShuffle]>;
5744 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
5745 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
5747 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
5749 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
5750 [], IIC_SSE_PALIGNRM>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5754 multiclass ssse3_palignr_y<string asm, bit Is2Addr = 1> {
5755 let hasSideEffects = 0 in {
5756 def R256rr : SS3AI<0x0F, MRMSrcReg, (outs VR256:$dst),
5757 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
5759 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5760 []>, Sched<[WriteShuffle]>;
5762 def R256rm : SS3AI<0x0F, MRMSrcMem, (outs VR256:$dst),
5763 (ins VR256:$src1, i256mem:$src2, u8imm:$src3),
5765 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
5766 []>, Sched<[WriteShuffleLd, ReadAfterLd]>;
5770 let Predicates = [HasAVX] in
5771 defm VPALIGN : ssse3_palignr<"vpalignr", 0>, VEX_4V;
5772 let Predicates = [HasAVX2] in
5773 defm VPALIGN : ssse3_palignr_y<"vpalignr", 0>, VEX_4V, VEX_L;
5774 let Constraints = "$src1 = $dst", Predicates = [UseSSSE3] in
5775 defm PALIGN : ssse3_palignr<"palignr">;
5777 let Predicates = [HasAVX2] in {
5778 def : Pat<(v8i32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5779 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5780 def : Pat<(v8f32 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5781 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5782 def : Pat<(v16i16 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5783 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5784 def : Pat<(v32i8 (X86PAlignr VR256:$src1, VR256:$src2, (i8 imm:$imm))),
5785 (VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
5788 let Predicates = [HasAVX] in {
5789 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5790 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5791 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5792 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5793 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5794 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5795 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5796 (VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5799 let Predicates = [UseSSSE3] in {
5800 def : Pat<(v4i32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5801 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5802 def : Pat<(v4f32 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5803 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5804 def : Pat<(v8i16 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5805 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5806 def : Pat<(v16i8 (X86PAlignr VR128:$src1, VR128:$src2, (i8 imm:$imm))),
5807 (PALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;
5810 //===---------------------------------------------------------------------===//
5811 // SSSE3 - Thread synchronization
5812 //===---------------------------------------------------------------------===//
5814 let SchedRW = [WriteSystem] in {
5815 let usesCustomInserter = 1 in {
5816 def MONITOR : PseudoI<(outs), (ins i32mem:$src1, GR32:$src2, GR32:$src3),
5817 [(int_x86_sse3_monitor addr:$src1, GR32:$src2, GR32:$src3)]>,
5818 Requires<[HasSSE3]>;
5821 let Uses = [EAX, ECX, EDX] in
5822 def MONITORrrr : I<0x01, MRM_C8, (outs), (ins), "monitor", [], IIC_SSE_MONITOR>,
5823 TB, Requires<[HasSSE3]>;
5824 let Uses = [ECX, EAX] in
5825 def MWAITrr : I<0x01, MRM_C9, (outs), (ins), "mwait",
5826 [(int_x86_sse3_mwait ECX, EAX)], IIC_SSE_MWAIT>,
5827 TB, Requires<[HasSSE3]>;
5830 def : InstAlias<"mwait\t{%eax, %ecx|ecx, eax}", (MWAITrr)>, Requires<[Not64BitMode]>;
5831 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
5833 def : InstAlias<"monitor\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORrrr)>,
5834 Requires<[Not64BitMode]>;
5835 def : InstAlias<"monitor\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORrrr)>,
5836 Requires<[In64BitMode]>;
5838 //===----------------------------------------------------------------------===//
5839 // SSE4.1 - Packed Move with Sign/Zero Extend
5840 //===----------------------------------------------------------------------===//
5842 multiclass SS41I_pmovx_rrrm<bits<8> opc, string OpcodeStr, X86MemOperand MemOp,
5843 RegisterClass OutRC, RegisterClass InRC,
5845 def rr : SS48I<opc, MRMSrcReg, (outs OutRC:$dst), (ins InRC:$src),
5846 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5848 Sched<[itins.Sched]>;
5850 def rm : SS48I<opc, MRMSrcMem, (outs OutRC:$dst), (ins MemOp:$src),
5851 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
5853 itins.rm>, Sched<[itins.Sched.Folded]>;
5856 multiclass SS41I_pmovx_rm_all<bits<8> opc, string OpcodeStr,
5857 X86MemOperand MemOp, X86MemOperand MemYOp,
5858 OpndItins SSEItins, OpndItins AVXItins,
5859 OpndItins AVX2Itins> {
5860 defm NAME : SS41I_pmovx_rrrm<opc, OpcodeStr, MemOp, VR128, VR128, SSEItins>;
5861 let Predicates = [HasAVX] in
5862 defm V#NAME : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemOp,
5863 VR128, VR128, AVXItins>, VEX;
5864 let Predicates = [HasAVX2] in
5865 defm V#NAME#Y : SS41I_pmovx_rrrm<opc, !strconcat("v", OpcodeStr), MemYOp,
5866 VR256, VR128, AVX2Itins>, VEX, VEX_L;
5869 multiclass SS41I_pmovx_rm<bits<8> opc, string OpcodeStr,
5870 X86MemOperand MemOp, X86MemOperand MemYOp> {
5871 defm PMOVSX#NAME : SS41I_pmovx_rm_all<opc, !strconcat("pmovsx", OpcodeStr),
5873 SSE_INTALU_ITINS_SHUFF_P,
5874 DEFAULT_ITINS_SHUFFLESCHED,
5875 DEFAULT_ITINS_SHUFFLESCHED>;
5876 defm PMOVZX#NAME : SS41I_pmovx_rm_all<!add(opc, 0x10),
5877 !strconcat("pmovzx", OpcodeStr),
5879 SSE_INTALU_ITINS_SHUFF_P,
5880 DEFAULT_ITINS_SHUFFLESCHED,
5881 DEFAULT_ITINS_SHUFFLESCHED>;
5884 defm BW : SS41I_pmovx_rm<0x20, "bw", i64mem, i128mem>;
5885 defm WD : SS41I_pmovx_rm<0x23, "wd", i64mem, i128mem>;
5886 defm DQ : SS41I_pmovx_rm<0x25, "dq", i64mem, i128mem>;
5888 defm BD : SS41I_pmovx_rm<0x21, "bd", i32mem, i64mem>;
5889 defm WQ : SS41I_pmovx_rm<0x24, "wq", i32mem, i64mem>;
5891 defm BQ : SS41I_pmovx_rm<0x22, "bq", i16mem, i32mem>;
5894 multiclass SS41I_pmovx_avx2_patterns<string OpcPrefix, string ExtTy, SDNode ExtOp> {
5895 // Register-Register patterns
5896 def : Pat<(v16i16 (ExtOp (v16i8 VR128:$src))),
5897 (!cast<I>(OpcPrefix#BWYrr) VR128:$src)>;
5898 def : Pat<(v8i32 (ExtOp (v16i8 VR128:$src))),
5899 (!cast<I>(OpcPrefix#BDYrr) VR128:$src)>;
5900 def : Pat<(v4i64 (ExtOp (v16i8 VR128:$src))),
5901 (!cast<I>(OpcPrefix#BQYrr) VR128:$src)>;
5903 def : Pat<(v8i32 (ExtOp (v8i16 VR128:$src))),
5904 (!cast<I>(OpcPrefix#WDYrr) VR128:$src)>;
5905 def : Pat<(v4i64 (ExtOp (v8i16 VR128:$src))),
5906 (!cast<I>(OpcPrefix#WQYrr) VR128:$src)>;
5908 def : Pat<(v4i64 (ExtOp (v4i32 VR128:$src))),
5909 (!cast<I>(OpcPrefix#DQYrr) VR128:$src)>;
5911 // On AVX2, we also support 256bit inputs.
5912 def : Pat<(v16i16 (ExtOp (v32i8 VR256:$src))),
5913 (!cast<I>(OpcPrefix#BWYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5914 def : Pat<(v8i32 (ExtOp (v32i8 VR256:$src))),
5915 (!cast<I>(OpcPrefix#BDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5916 def : Pat<(v4i64 (ExtOp (v32i8 VR256:$src))),
5917 (!cast<I>(OpcPrefix#BQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5919 def : Pat<(v8i32 (ExtOp (v16i16 VR256:$src))),
5920 (!cast<I>(OpcPrefix#WDYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5921 def : Pat<(v4i64 (ExtOp (v16i16 VR256:$src))),
5922 (!cast<I>(OpcPrefix#WQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5924 def : Pat<(v4i64 (ExtOp (v8i32 VR256:$src))),
5925 (!cast<I>(OpcPrefix#DQYrr) (EXTRACT_SUBREG VR256:$src, sub_xmm))>;
5927 // Simple Register-Memory patterns
5928 def : Pat<(v16i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5929 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5930 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5931 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5932 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
5933 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5935 def : Pat<(v8i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5936 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5937 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
5938 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5940 def : Pat<(v4i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
5941 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5943 // AVX2 Register-Memory patterns
5944 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5945 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5946 def : Pat<(v16i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5947 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5948 def : Pat<(v16i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5949 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5950 def : Pat<(v16i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5951 (!cast<I>(OpcPrefix#BWYrm) addr:$src)>;
5953 def : Pat<(v8i32 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5954 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5955 def : Pat<(v8i32 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
5956 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5957 def : Pat<(v8i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5958 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5959 def : Pat<(v8i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5960 (!cast<I>(OpcPrefix#BDYrm) addr:$src)>;
5962 def : Pat<(v4i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
5963 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5964 def : Pat<(v4i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
5965 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5966 def : Pat<(v4i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
5967 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5968 def : Pat<(v4i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
5969 (!cast<I>(OpcPrefix#BQYrm) addr:$src)>;
5971 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5972 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5973 def : Pat<(v8i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5974 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5975 def : Pat<(v8i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5976 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5977 def : Pat<(v8i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5978 (!cast<I>(OpcPrefix#WDYrm) addr:$src)>;
5980 def : Pat<(v4i64 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
5981 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5982 def : Pat<(v4i64 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
5983 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5984 def : Pat<(v4i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
5985 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5986 def : Pat<(v4i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
5987 (!cast<I>(OpcPrefix#WQYrm) addr:$src)>;
5989 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5990 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5991 def : Pat<(v4i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
5992 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5993 def : Pat<(v4i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
5994 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5995 def : Pat<(v4i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
5996 (!cast<I>(OpcPrefix#DQYrm) addr:$src)>;
5999 let Predicates = [HasAVX2] in {
6000 defm : SS41I_pmovx_avx2_patterns<"VPMOVSX", "s", X86vsext>;
6001 defm : SS41I_pmovx_avx2_patterns<"VPMOVZX", "z", X86vzext>;
6004 // SSE4.1/AVX patterns.
6005 multiclass SS41I_pmovx_patterns<string OpcPrefix, string ExtTy,
6006 SDNode ExtOp, PatFrag ExtLoad16> {
6007 def : Pat<(v8i16 (ExtOp (v16i8 VR128:$src))),
6008 (!cast<I>(OpcPrefix#BWrr) VR128:$src)>;
6009 def : Pat<(v4i32 (ExtOp (v16i8 VR128:$src))),
6010 (!cast<I>(OpcPrefix#BDrr) VR128:$src)>;
6011 def : Pat<(v2i64 (ExtOp (v16i8 VR128:$src))),
6012 (!cast<I>(OpcPrefix#BQrr) VR128:$src)>;
6014 def : Pat<(v4i32 (ExtOp (v8i16 VR128:$src))),
6015 (!cast<I>(OpcPrefix#WDrr) VR128:$src)>;
6016 def : Pat<(v2i64 (ExtOp (v8i16 VR128:$src))),
6017 (!cast<I>(OpcPrefix#WQrr) VR128:$src)>;
6019 def : Pat<(v2i64 (ExtOp (v4i32 VR128:$src))),
6020 (!cast<I>(OpcPrefix#DQrr) VR128:$src)>;
6022 def : Pat<(v8i16 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6023 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6024 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6025 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6026 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi8") addr:$src)),
6027 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6029 def : Pat<(v4i32 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6030 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6031 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi16") addr:$src)),
6032 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6034 def : Pat<(v2i64 (!cast<PatFrag>(ExtTy#"extloadvi32") addr:$src)),
6035 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6037 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6038 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6039 def : Pat<(v8i16 (ExtOp (bc_v16i8 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6040 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6041 def : Pat<(v8i16 (ExtOp (v16i8 (vzmovl_v2i64 addr:$src)))),
6042 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6043 def : Pat<(v8i16 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6044 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6045 def : Pat<(v8i16 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6046 (!cast<I>(OpcPrefix#BWrm) addr:$src)>;
6048 def : Pat<(v4i32 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6049 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6050 def : Pat<(v4i32 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6051 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6052 def : Pat<(v4i32 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6053 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6054 def : Pat<(v4i32 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6055 (!cast<I>(OpcPrefix#BDrm) addr:$src)>;
6057 def : Pat<(v2i64 (ExtOp (bc_v16i8 (v4i32 (scalar_to_vector (ExtLoad16 addr:$src)))))),
6058 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6059 def : Pat<(v2i64 (ExtOp (v16i8 (vzmovl_v4i32 addr:$src)))),
6060 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6061 def : Pat<(v2i64 (ExtOp (v16i8 (vzload_v2i64 addr:$src)))),
6062 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6063 def : Pat<(v2i64 (ExtOp (bc_v16i8 (loadv2i64 addr:$src)))),
6064 (!cast<I>(OpcPrefix#BQrm) addr:$src)>;
6066 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6067 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6068 def : Pat<(v4i32 (ExtOp (bc_v8i16 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6069 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6070 def : Pat<(v4i32 (ExtOp (v8i16 (vzmovl_v2i64 addr:$src)))),
6071 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6072 def : Pat<(v4i32 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6073 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6074 def : Pat<(v4i32 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6075 (!cast<I>(OpcPrefix#WDrm) addr:$src)>;
6077 def : Pat<(v2i64 (ExtOp (bc_v8i16 (v4i32 (scalar_to_vector (loadi32 addr:$src)))))),
6078 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6079 def : Pat<(v2i64 (ExtOp (v8i16 (vzmovl_v4i32 addr:$src)))),
6080 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6081 def : Pat<(v2i64 (ExtOp (v8i16 (vzload_v2i64 addr:$src)))),
6082 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6083 def : Pat<(v2i64 (ExtOp (bc_v8i16 (loadv2i64 addr:$src)))),
6084 (!cast<I>(OpcPrefix#WQrm) addr:$src)>;
6086 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2i64 (scalar_to_vector (loadi64 addr:$src)))))),
6087 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6088 def : Pat<(v2i64 (ExtOp (bc_v4i32 (v2f64 (scalar_to_vector (loadf64 addr:$src)))))),
6089 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6090 def : Pat<(v2i64 (ExtOp (v4i32 (vzmovl_v2i64 addr:$src)))),
6091 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6092 def : Pat<(v2i64 (ExtOp (v4i32 (vzload_v2i64 addr:$src)))),
6093 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6094 def : Pat<(v2i64 (ExtOp (bc_v4i32 (loadv2i64 addr:$src)))),
6095 (!cast<I>(OpcPrefix#DQrm) addr:$src)>;
6098 let Predicates = [HasAVX] in {
6099 defm : SS41I_pmovx_patterns<"VPMOVSX", "s", X86vsext, extloadi32i16>;
6100 defm : SS41I_pmovx_patterns<"VPMOVZX", "z", X86vzext, loadi16_anyext>;
6103 let Predicates = [UseSSE41] in {
6104 defm : SS41I_pmovx_patterns<"PMOVSX", "s", X86vsext, extloadi32i16>;
6105 defm : SS41I_pmovx_patterns<"PMOVZX", "z", X86vzext, loadi16_anyext>;
6108 //===----------------------------------------------------------------------===//
6109 // SSE4.1 - Extract Instructions
6110 //===----------------------------------------------------------------------===//
6112 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
6113 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
6114 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6115 (ins VR128:$src1, u8imm:$src2),
6116 !strconcat(OpcodeStr,
6117 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6118 [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),
6120 Sched<[WriteShuffle]>;
6121 let hasSideEffects = 0, mayStore = 1,
6122 SchedRW = [WriteShuffleLd, WriteRMW] in
6123 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6124 (ins i8mem:$dst, VR128:$src1, u8imm:$src2),
6125 !strconcat(OpcodeStr,
6126 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6127 [(store (i8 (trunc (assertzext (X86pextrb (v16i8 VR128:$src1),
6128 imm:$src2)))), addr:$dst)]>;
6131 let Predicates = [HasAVX] in
6132 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
6134 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
6137 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
6138 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
6139 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
6140 def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6141 (ins VR128:$src1, u8imm:$src2),
6142 !strconcat(OpcodeStr,
6143 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6144 []>, Sched<[WriteShuffle]>;
6146 let hasSideEffects = 0, mayStore = 1,
6147 SchedRW = [WriteShuffleLd, WriteRMW] in
6148 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6149 (ins i16mem:$dst, VR128:$src1, u8imm:$src2),
6150 !strconcat(OpcodeStr,
6151 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6152 [(store (i16 (trunc (assertzext (X86pextrw (v8i16 VR128:$src1),
6153 imm:$src2)))), addr:$dst)]>;
6156 let Predicates = [HasAVX] in
6157 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
6159 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
6162 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6163 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
6164 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
6165 (ins VR128:$src1, u8imm:$src2),
6166 !strconcat(OpcodeStr,
6167 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6169 (extractelt (v4i32 VR128:$src1), imm:$src2))]>,
6170 Sched<[WriteShuffle]>;
6171 let SchedRW = [WriteShuffleLd, WriteRMW] in
6172 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6173 (ins i32mem:$dst, VR128:$src1, u8imm:$src2),
6174 !strconcat(OpcodeStr,
6175 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6176 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
6180 let Predicates = [HasAVX] in
6181 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
6183 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
6185 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
6186 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
6187 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
6188 (ins VR128:$src1, u8imm:$src2),
6189 !strconcat(OpcodeStr,
6190 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6192 (extractelt (v2i64 VR128:$src1), imm:$src2))]>,
6193 Sched<[WriteShuffle]>, REX_W;
6194 let SchedRW = [WriteShuffleLd, WriteRMW] in
6195 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6196 (ins i64mem:$dst, VR128:$src1, u8imm:$src2),
6197 !strconcat(OpcodeStr,
6198 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6199 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
6200 addr:$dst)]>, REX_W;
6203 let Predicates = [HasAVX] in
6204 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
6206 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
6208 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
6210 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,
6211 OpndItins itins = DEFAULT_ITINS> {
6212 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),
6213 (ins VR128:$src1, u8imm:$src2),
6214 !strconcat(OpcodeStr,
6215 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6216 [(set GR32orGR64:$dst,
6217 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],
6218 itins.rr>, Sched<[WriteFBlend]>;
6219 let SchedRW = [WriteFBlendLd, WriteRMW] in
6220 def mr : SS4AIi8<opc, MRMDestMem, (outs),
6221 (ins f32mem:$dst, VR128:$src1, u8imm:$src2),
6222 !strconcat(OpcodeStr,
6223 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6224 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
6225 addr:$dst)], itins.rm>;
6228 let ExeDomain = SSEPackedSingle in {
6229 let Predicates = [UseAVX] in
6230 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
6231 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;
6234 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
6235 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6238 (VEXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6240 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
6243 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
6244 Requires<[UseSSE41]>;
6246 //===----------------------------------------------------------------------===//
6247 // SSE4.1 - Insert Instructions
6248 //===----------------------------------------------------------------------===//
6250 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
6251 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6252 (ins VR128:$src1, GR32orGR64:$src2, u8imm:$src3),
6254 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6256 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6258 (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>,
6259 Sched<[WriteShuffle]>;
6260 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6261 (ins VR128:$src1, i8mem:$src2, u8imm:$src3),
6263 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6265 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6267 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
6268 imm:$src3))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6271 let Predicates = [HasAVX] in
6272 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
6273 let Constraints = "$src1 = $dst" in
6274 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
6276 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
6277 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6278 (ins VR128:$src1, GR32:$src2, u8imm:$src3),
6280 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6282 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6284 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
6285 Sched<[WriteShuffle]>;
6286 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6287 (ins VR128:$src1, i32mem:$src2, u8imm:$src3),
6289 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6291 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6293 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
6294 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6297 let Predicates = [HasAVX] in
6298 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
6299 let Constraints = "$src1 = $dst" in
6300 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
6302 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
6303 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6304 (ins VR128:$src1, GR64:$src2, u8imm:$src3),
6306 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6308 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6310 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
6311 Sched<[WriteShuffle]>;
6312 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6313 (ins VR128:$src1, i64mem:$src2, u8imm:$src3),
6315 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6317 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6319 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
6320 imm:$src3)))]>, Sched<[WriteShuffleLd, ReadAfterLd]>;
6323 let Predicates = [HasAVX] in
6324 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
6325 let Constraints = "$src1 = $dst" in
6326 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
6328 // insertps has a few different modes, there's the first two here below which
6329 // are optimized inserts that won't zero arbitrary elements in the destination
6330 // vector. The next one matches the intrinsic and could zero arbitrary elements
6331 // in the target vector.
6332 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1,
6333 OpndItins itins = DEFAULT_ITINS> {
6334 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
6335 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
6337 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6339 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6341 (X86insertps VR128:$src1, VR128:$src2, imm:$src3))], itins.rr>,
6342 Sched<[WriteFShuffle]>;
6343 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
6344 (ins VR128:$src1, f32mem:$src2, u8imm:$src3),
6346 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6348 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6350 (X86insertps VR128:$src1,
6351 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
6352 imm:$src3))], itins.rm>,
6353 Sched<[WriteFShuffleLd, ReadAfterLd]>;
6356 let ExeDomain = SSEPackedSingle in {
6357 let Predicates = [UseAVX] in
6358 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
6359 let Constraints = "$src1 = $dst" in
6360 defm INSERTPS : SS41I_insertf32<0x21, "insertps", 1, SSE_INSERT_ITINS>;
6363 let Predicates = [UseSSE41] in {
6364 // If we're inserting an element from a load or a null pshuf of a load,
6365 // fold the load into the insertps instruction.
6366 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd (v4f32
6367 (scalar_to_vector (loadf32 addr:$src2))), (i8 0)),
6369 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6370 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1), (X86PShufd
6371 (loadv4f32 addr:$src2), (i8 0)), imm:$src3)),
6372 (INSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6375 let Predicates = [UseAVX] in {
6376 // If we're inserting an element from a vbroadcast of a load, fold the
6377 // load into the X86insertps instruction.
6378 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6379 (X86VBroadcast (loadf32 addr:$src2)), imm:$src3)),
6380 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6381 def : Pat<(v4f32 (X86insertps (v4f32 VR128:$src1),
6382 (X86VBroadcast (loadv4f32 addr:$src2)), imm:$src3)),
6383 (VINSERTPSrm VR128:$src1, addr:$src2, imm:$src3)>;
6386 //===----------------------------------------------------------------------===//
6387 // SSE4.1 - Round Instructions
6388 //===----------------------------------------------------------------------===//
6390 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
6391 X86MemOperand x86memop, RegisterClass RC,
6392 PatFrag mem_frag32, PatFrag mem_frag64,
6393 Intrinsic V4F32Int, Intrinsic V2F64Int> {
6394 let ExeDomain = SSEPackedSingle in {
6395 // Intrinsic operation, reg.
6396 // Vector intrinsic operation, reg
6397 def PSr : SS4AIi8<opcps, MRMSrcReg,
6398 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6399 !strconcat(OpcodeStr,
6400 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6401 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))],
6402 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6404 // Vector intrinsic operation, mem
6405 def PSm : SS4AIi8<opcps, MRMSrcMem,
6406 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6407 !strconcat(OpcodeStr,
6408 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6410 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))],
6411 IIC_SSE_ROUNDPS_MEM>, Sched<[WriteFAddLd]>;
6412 } // ExeDomain = SSEPackedSingle
6414 let ExeDomain = SSEPackedDouble in {
6415 // Vector intrinsic operation, reg
6416 def PDr : SS4AIi8<opcpd, MRMSrcReg,
6417 (outs RC:$dst), (ins RC:$src1, i32u8imm:$src2),
6418 !strconcat(OpcodeStr,
6419 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6420 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))],
6421 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAdd]>;
6423 // Vector intrinsic operation, mem
6424 def PDm : SS4AIi8<opcpd, MRMSrcMem,
6425 (outs RC:$dst), (ins x86memop:$src1, i32u8imm:$src2),
6426 !strconcat(OpcodeStr,
6427 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
6429 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))],
6430 IIC_SSE_ROUNDPS_REG>, Sched<[WriteFAddLd]>;
6431 } // ExeDomain = SSEPackedDouble
6434 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
6437 Intrinsic F64Int, bit Is2Addr = 1> {
6438 let ExeDomain = GenericDomain in {
6440 let hasSideEffects = 0 in
6441 def SSr : SS4AIi8<opcss, MRMSrcReg,
6442 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, i32u8imm:$src3),
6444 !strconcat(OpcodeStr,
6445 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6446 !strconcat(OpcodeStr,
6447 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6448 []>, Sched<[WriteFAdd]>;
6450 // Intrinsic operation, reg.
6451 let isCodeGenOnly = 1 in
6452 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
6453 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6455 !strconcat(OpcodeStr,
6456 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6457 !strconcat(OpcodeStr,
6458 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6459 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6462 // Intrinsic operation, mem.
6463 def SSm : SS4AIi8<opcss, MRMSrcMem,
6464 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32u8imm:$src3),
6466 !strconcat(OpcodeStr,
6467 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6468 !strconcat(OpcodeStr,
6469 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6471 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
6472 Sched<[WriteFAddLd, ReadAfterLd]>;
6475 let hasSideEffects = 0 in
6476 def SDr : SS4AIi8<opcsd, MRMSrcReg,
6477 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, i32u8imm:$src3),
6479 !strconcat(OpcodeStr,
6480 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6481 !strconcat(OpcodeStr,
6482 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6483 []>, Sched<[WriteFAdd]>;
6485 // Intrinsic operation, reg.
6486 let isCodeGenOnly = 1 in
6487 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
6488 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32u8imm:$src3),
6490 !strconcat(OpcodeStr,
6491 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6492 !strconcat(OpcodeStr,
6493 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6494 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
6497 // Intrinsic operation, mem.
6498 def SDm : SS4AIi8<opcsd, MRMSrcMem,
6499 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32u8imm:$src3),
6501 !strconcat(OpcodeStr,
6502 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6503 !strconcat(OpcodeStr,
6504 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6506 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
6507 Sched<[WriteFAddLd, ReadAfterLd]>;
6508 } // ExeDomain = GenericDomain
6511 // FP round - roundss, roundps, roundsd, roundpd
6512 let Predicates = [HasAVX] in {
6514 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround", f128mem, VR128,
6515 loadv4f32, loadv2f64,
6516 int_x86_sse41_round_ps,
6517 int_x86_sse41_round_pd>, VEX;
6518 defm VROUNDY : sse41_fp_unop_rm<0x08, 0x09, "vround", f256mem, VR256,
6519 loadv8f32, loadv4f64,
6520 int_x86_avx_round_ps_256,
6521 int_x86_avx_round_pd_256>, VEX, VEX_L;
6522 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
6523 int_x86_sse41_round_ss,
6524 int_x86_sse41_round_sd, 0>, VEX_4V, VEX_LIG;
6527 let Predicates = [UseAVX] in {
6528 def : Pat<(ffloor FR32:$src),
6529 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6530 def : Pat<(f64 (ffloor FR64:$src)),
6531 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6532 def : Pat<(f32 (fnearbyint FR32:$src)),
6533 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6534 def : Pat<(f64 (fnearbyint FR64:$src)),
6535 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6536 def : Pat<(f32 (fceil FR32:$src)),
6537 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6538 def : Pat<(f64 (fceil FR64:$src)),
6539 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6540 def : Pat<(f32 (frint FR32:$src)),
6541 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6542 def : Pat<(f64 (frint FR64:$src)),
6543 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6544 def : Pat<(f32 (ftrunc FR32:$src)),
6545 (VROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6546 def : Pat<(f64 (ftrunc FR64:$src)),
6547 (VROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6550 let Predicates = [HasAVX] in {
6551 def : Pat<(v4f32 (ffloor VR128:$src)),
6552 (VROUNDPSr VR128:$src, (i32 0x1))>;
6553 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6554 (VROUNDPSr VR128:$src, (i32 0xC))>;
6555 def : Pat<(v4f32 (fceil VR128:$src)),
6556 (VROUNDPSr VR128:$src, (i32 0x2))>;
6557 def : Pat<(v4f32 (frint VR128:$src)),
6558 (VROUNDPSr VR128:$src, (i32 0x4))>;
6559 def : Pat<(v4f32 (ftrunc VR128:$src)),
6560 (VROUNDPSr VR128:$src, (i32 0x3))>;
6562 def : Pat<(v2f64 (ffloor VR128:$src)),
6563 (VROUNDPDr VR128:$src, (i32 0x1))>;
6564 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6565 (VROUNDPDr VR128:$src, (i32 0xC))>;
6566 def : Pat<(v2f64 (fceil VR128:$src)),
6567 (VROUNDPDr VR128:$src, (i32 0x2))>;
6568 def : Pat<(v2f64 (frint VR128:$src)),
6569 (VROUNDPDr VR128:$src, (i32 0x4))>;
6570 def : Pat<(v2f64 (ftrunc VR128:$src)),
6571 (VROUNDPDr VR128:$src, (i32 0x3))>;
6573 def : Pat<(v8f32 (ffloor VR256:$src)),
6574 (VROUNDYPSr VR256:$src, (i32 0x1))>;
6575 def : Pat<(v8f32 (fnearbyint VR256:$src)),
6576 (VROUNDYPSr VR256:$src, (i32 0xC))>;
6577 def : Pat<(v8f32 (fceil VR256:$src)),
6578 (VROUNDYPSr VR256:$src, (i32 0x2))>;
6579 def : Pat<(v8f32 (frint VR256:$src)),
6580 (VROUNDYPSr VR256:$src, (i32 0x4))>;
6581 def : Pat<(v8f32 (ftrunc VR256:$src)),
6582 (VROUNDYPSr VR256:$src, (i32 0x3))>;
6584 def : Pat<(v4f64 (ffloor VR256:$src)),
6585 (VROUNDYPDr VR256:$src, (i32 0x1))>;
6586 def : Pat<(v4f64 (fnearbyint VR256:$src)),
6587 (VROUNDYPDr VR256:$src, (i32 0xC))>;
6588 def : Pat<(v4f64 (fceil VR256:$src)),
6589 (VROUNDYPDr VR256:$src, (i32 0x2))>;
6590 def : Pat<(v4f64 (frint VR256:$src)),
6591 (VROUNDYPDr VR256:$src, (i32 0x4))>;
6592 def : Pat<(v4f64 (ftrunc VR256:$src)),
6593 (VROUNDYPDr VR256:$src, (i32 0x3))>;
6596 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round", f128mem, VR128,
6597 memopv4f32, memopv2f64,
6598 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
6599 let Constraints = "$src1 = $dst" in
6600 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
6601 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
6603 let Predicates = [UseSSE41] in {
6604 def : Pat<(ffloor FR32:$src),
6605 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x1))>;
6606 def : Pat<(f64 (ffloor FR64:$src)),
6607 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x1))>;
6608 def : Pat<(f32 (fnearbyint FR32:$src)),
6609 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0xC))>;
6610 def : Pat<(f64 (fnearbyint FR64:$src)),
6611 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0xC))>;
6612 def : Pat<(f32 (fceil FR32:$src)),
6613 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x2))>;
6614 def : Pat<(f64 (fceil FR64:$src)),
6615 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x2))>;
6616 def : Pat<(f32 (frint FR32:$src)),
6617 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x4))>;
6618 def : Pat<(f64 (frint FR64:$src)),
6619 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x4))>;
6620 def : Pat<(f32 (ftrunc FR32:$src)),
6621 (ROUNDSSr (f32 (IMPLICIT_DEF)), FR32:$src, (i32 0x3))>;
6622 def : Pat<(f64 (ftrunc FR64:$src)),
6623 (ROUNDSDr (f64 (IMPLICIT_DEF)), FR64:$src, (i32 0x3))>;
6625 def : Pat<(v4f32 (ffloor VR128:$src)),
6626 (ROUNDPSr VR128:$src, (i32 0x1))>;
6627 def : Pat<(v4f32 (fnearbyint VR128:$src)),
6628 (ROUNDPSr VR128:$src, (i32 0xC))>;
6629 def : Pat<(v4f32 (fceil VR128:$src)),
6630 (ROUNDPSr VR128:$src, (i32 0x2))>;
6631 def : Pat<(v4f32 (frint VR128:$src)),
6632 (ROUNDPSr VR128:$src, (i32 0x4))>;
6633 def : Pat<(v4f32 (ftrunc VR128:$src)),
6634 (ROUNDPSr VR128:$src, (i32 0x3))>;
6636 def : Pat<(v2f64 (ffloor VR128:$src)),
6637 (ROUNDPDr VR128:$src, (i32 0x1))>;
6638 def : Pat<(v2f64 (fnearbyint VR128:$src)),
6639 (ROUNDPDr VR128:$src, (i32 0xC))>;
6640 def : Pat<(v2f64 (fceil VR128:$src)),
6641 (ROUNDPDr VR128:$src, (i32 0x2))>;
6642 def : Pat<(v2f64 (frint VR128:$src)),
6643 (ROUNDPDr VR128:$src, (i32 0x4))>;
6644 def : Pat<(v2f64 (ftrunc VR128:$src)),
6645 (ROUNDPDr VR128:$src, (i32 0x3))>;
6648 //===----------------------------------------------------------------------===//
6649 // SSE4.1 - Packed Bit Test
6650 //===----------------------------------------------------------------------===//
6652 // ptest instruction we'll lower to this in X86ISelLowering primarily from
6653 // the intel intrinsic that corresponds to this.
6654 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6655 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6656 "vptest\t{$src2, $src1|$src1, $src2}",
6657 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6658 Sched<[WriteVecLogic]>, VEX;
6659 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6660 "vptest\t{$src2, $src1|$src1, $src2}",
6661 [(set EFLAGS,(X86ptest VR128:$src1, (loadv2i64 addr:$src2)))]>,
6662 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6664 def VPTESTYrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR256:$src1, VR256:$src2),
6665 "vptest\t{$src2, $src1|$src1, $src2}",
6666 [(set EFLAGS, (X86ptest VR256:$src1, (v4i64 VR256:$src2)))]>,
6667 Sched<[WriteVecLogic]>, VEX, VEX_L;
6668 def VPTESTYrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR256:$src1, i256mem:$src2),
6669 "vptest\t{$src2, $src1|$src1, $src2}",
6670 [(set EFLAGS,(X86ptest VR256:$src1, (loadv4i64 addr:$src2)))]>,
6671 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX, VEX_L;
6674 let Defs = [EFLAGS] in {
6675 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
6676 "ptest\t{$src2, $src1|$src1, $src2}",
6677 [(set EFLAGS, (X86ptest VR128:$src1, (v2i64 VR128:$src2)))]>,
6678 Sched<[WriteVecLogic]>;
6679 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
6680 "ptest\t{$src2, $src1|$src1, $src2}",
6681 [(set EFLAGS, (X86ptest VR128:$src1, (memopv2i64 addr:$src2)))]>,
6682 Sched<[WriteVecLogicLd, ReadAfterLd]>;
6685 // The bit test instructions below are AVX only
6686 multiclass avx_bittest<bits<8> opc, string OpcodeStr, RegisterClass RC,
6687 X86MemOperand x86memop, PatFrag mem_frag, ValueType vt> {
6688 def rr : SS48I<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
6689 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6690 [(set EFLAGS, (X86testp RC:$src1, (vt RC:$src2)))]>,
6691 Sched<[WriteVecLogic]>, VEX;
6692 def rm : SS48I<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
6693 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
6694 [(set EFLAGS, (X86testp RC:$src1, (mem_frag addr:$src2)))]>,
6695 Sched<[WriteVecLogicLd, ReadAfterLd]>, VEX;
6698 let Defs = [EFLAGS], Predicates = [HasAVX] in {
6699 let ExeDomain = SSEPackedSingle in {
6700 defm VTESTPS : avx_bittest<0x0E, "vtestps", VR128, f128mem, loadv4f32, v4f32>;
6701 defm VTESTPSY : avx_bittest<0x0E, "vtestps", VR256, f256mem, loadv8f32, v8f32>,
6704 let ExeDomain = SSEPackedDouble in {
6705 defm VTESTPD : avx_bittest<0x0F, "vtestpd", VR128, f128mem, loadv2f64, v2f64>;
6706 defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64>,
6711 //===----------------------------------------------------------------------===//
6712 // SSE4.1 - Misc Instructions
6713 //===----------------------------------------------------------------------===//
6715 let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
6716 def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
6717 "popcnt{w}\t{$src, $dst|$dst, $src}",
6718 [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
6719 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6721 def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
6722 "popcnt{w}\t{$src, $dst|$dst, $src}",
6723 [(set GR16:$dst, (ctpop (loadi16 addr:$src))),
6724 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6725 Sched<[WriteFAddLd]>, OpSize16, XS;
6727 def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
6728 "popcnt{l}\t{$src, $dst|$dst, $src}",
6729 [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)],
6730 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>,
6733 def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
6734 "popcnt{l}\t{$src, $dst|$dst, $src}",
6735 [(set GR32:$dst, (ctpop (loadi32 addr:$src))),
6736 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6737 Sched<[WriteFAddLd]>, OpSize32, XS;
6739 def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
6740 "popcnt{q}\t{$src, $dst|$dst, $src}",
6741 [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)],
6742 IIC_SSE_POPCNT_RR>, Sched<[WriteFAdd]>, XS;
6743 def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
6744 "popcnt{q}\t{$src, $dst|$dst, $src}",
6745 [(set GR64:$dst, (ctpop (loadi64 addr:$src))),
6746 (implicit EFLAGS)], IIC_SSE_POPCNT_RM>,
6747 Sched<[WriteFAddLd]>, XS;
6752 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
6753 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
6754 Intrinsic IntId128, PatFrag ld_frag,
6755 X86FoldableSchedWrite Sched> {
6756 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
6758 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6759 [(set VR128:$dst, (IntId128 VR128:$src))]>,
6761 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
6763 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
6765 (IntId128 (bitconvert (ld_frag addr:$src))))]>,
6766 Sched<[Sched.Folded]>;
6769 // PHMIN has the same profile as PSAD, thus we use the same scheduling
6770 // model, although the naming is misleading.
6771 let Predicates = [HasAVX] in
6772 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
6773 int_x86_sse41_phminposuw, loadv2i64,
6775 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
6776 int_x86_sse41_phminposuw, memopv2i64,
6779 /// SS48I_binop_rm - Simple SSE41 binary operator.
6780 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
6781 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6782 X86MemOperand x86memop, bit Is2Addr = 1,
6783 OpndItins itins = SSE_INTALU_ITINS_P> {
6784 let isCommutable = 1 in
6785 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6786 (ins RC:$src1, RC:$src2),
6788 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6789 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6790 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>,
6791 Sched<[itins.Sched]>;
6792 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6793 (ins RC:$src1, x86memop:$src2),
6795 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6796 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6798 (OpVT (OpNode RC:$src1, (bitconvert (memop_frag addr:$src2)))))]>,
6799 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6802 /// SS48I_binop_rm2 - Simple SSE41 binary operator with different src and dst
6804 multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
6805 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
6806 PatFrag memop_frag, X86MemOperand x86memop,
6808 bit IsCommutable = 0, bit Is2Addr = 1> {
6809 let isCommutable = IsCommutable in
6810 def rr : SS48I<opc, MRMSrcReg, (outs RC:$dst),
6811 (ins RC:$src1, RC:$src2),
6813 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6814 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6815 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1), RC:$src2)))]>,
6816 Sched<[itins.Sched]>;
6817 def rm : SS48I<opc, MRMSrcMem, (outs RC:$dst),
6818 (ins RC:$src1, x86memop:$src2),
6820 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
6821 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
6822 [(set RC:$dst, (DstVT (OpNode (SrcVT RC:$src1),
6823 (bitconvert (memop_frag addr:$src2)))))]>,
6824 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6827 let Predicates = [HasAVX, NoVLX] in {
6828 let isCommutable = 0 in
6829 defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
6830 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6832 defm VPMINSD : SS48I_binop_rm<0x39, "vpminsd", X86smin, v4i32, VR128,
6833 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6835 defm VPMINUD : SS48I_binop_rm<0x3B, "vpminud", X86umin, v4i32, VR128,
6836 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6838 defm VPMINUW : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v8i16, VR128,
6839 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6841 defm VPMAXSB : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v16i8, VR128,
6842 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6844 defm VPMAXSD : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v4i32, VR128,
6845 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6847 defm VPMAXUD : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v4i32, VR128,
6848 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6850 defm VPMAXUW : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v8i16, VR128,
6851 loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6853 defm VPMULDQ : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v2i64, v4i32,
6854 VR128, loadv2i64, i128mem,
6855 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
6858 let Predicates = [HasAVX2, NoVLX] in {
6859 let isCommutable = 0 in
6860 defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
6861 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6863 defm VPMINSDY : SS48I_binop_rm<0x39, "vpminsd", X86smin, v8i32, VR256,
6864 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6866 defm VPMINUDY : SS48I_binop_rm<0x3B, "vpminud", X86umin, v8i32, VR256,
6867 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6869 defm VPMINUWY : SS48I_binop_rm<0x3A, "vpminuw", X86umin, v16i16, VR256,
6870 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6872 defm VPMAXSBY : SS48I_binop_rm<0x3C, "vpmaxsb", X86smax, v32i8, VR256,
6873 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6875 defm VPMAXSDY : SS48I_binop_rm<0x3D, "vpmaxsd", X86smax, v8i32, VR256,
6876 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6878 defm VPMAXUDY : SS48I_binop_rm<0x3F, "vpmaxud", X86umax, v8i32, VR256,
6879 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6881 defm VPMAXUWY : SS48I_binop_rm<0x3E, "vpmaxuw", X86umax, v16i16, VR256,
6882 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6884 defm VPMULDQY : SS48I_binop_rm2<0x28, "vpmuldq", X86pmuldq, v4i64, v8i32,
6885 VR256, loadv4i64, i256mem,
6886 SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V, VEX_L;
6889 let Constraints = "$src1 = $dst" in {
6890 let isCommutable = 0 in
6891 defm PMINSB : SS48I_binop_rm<0x38, "pminsb", X86smin, v16i8, VR128,
6892 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6893 defm PMINSD : SS48I_binop_rm<0x39, "pminsd", X86smin, v4i32, VR128,
6894 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6895 defm PMINUD : SS48I_binop_rm<0x3B, "pminud", X86umin, v4i32, VR128,
6896 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6897 defm PMINUW : SS48I_binop_rm<0x3A, "pminuw", X86umin, v8i16, VR128,
6898 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6899 defm PMAXSB : SS48I_binop_rm<0x3C, "pmaxsb", X86smax, v16i8, VR128,
6900 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6901 defm PMAXSD : SS48I_binop_rm<0x3D, "pmaxsd", X86smax, v4i32, VR128,
6902 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6903 defm PMAXUD : SS48I_binop_rm<0x3F, "pmaxud", X86umax, v4i32, VR128,
6904 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6905 defm PMAXUW : SS48I_binop_rm<0x3E, "pmaxuw", X86umax, v8i16, VR128,
6906 memopv2i64, i128mem, 1, SSE_INTALU_ITINS_P>;
6907 defm PMULDQ : SS48I_binop_rm2<0x28, "pmuldq", X86pmuldq, v2i64, v4i32,
6908 VR128, memopv2i64, i128mem,
6909 SSE_INTMUL_ITINS_P, 1>;
6912 let Predicates = [HasAVX, NoVLX] in {
6913 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, VR128,
6914 memopv2i64, i128mem, 0, SSE_PMULLD_ITINS>,
6916 defm VPCMPEQQ : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v2i64, VR128,
6917 memopv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
6920 let Predicates = [HasAVX2] in {
6921 defm VPMULLDY : SS48I_binop_rm<0x40, "vpmulld", mul, v8i32, VR256,
6922 loadv4i64, i256mem, 0, SSE_PMULLD_ITINS>,
6924 defm VPCMPEQQY : SS48I_binop_rm<0x29, "vpcmpeqq", X86pcmpeq, v4i64, VR256,
6925 loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,
6929 let Constraints = "$src1 = $dst" in {
6930 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, VR128,
6931 memopv2i64, i128mem, 1, SSE_PMULLD_ITINS>;
6932 defm PCMPEQQ : SS48I_binop_rm<0x29, "pcmpeqq", X86pcmpeq, v2i64, VR128,
6933 memopv2i64, i128mem, 1, SSE_INTALUQ_ITINS_P>;
6936 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
6937 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
6938 Intrinsic IntId, RegisterClass RC, PatFrag memop_frag,
6939 X86MemOperand x86memop, bit Is2Addr = 1,
6940 OpndItins itins = DEFAULT_ITINS> {
6941 let isCommutable = 1 in
6942 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6943 (ins RC:$src1, RC:$src2, u8imm:$src3),
6945 !strconcat(OpcodeStr,
6946 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6947 !strconcat(OpcodeStr,
6948 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6949 [(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))], itins.rr>,
6950 Sched<[itins.Sched]>;
6951 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6952 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6954 !strconcat(OpcodeStr,
6955 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6956 !strconcat(OpcodeStr,
6957 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6960 (bitconvert (memop_frag addr:$src2)), imm:$src3))], itins.rm>,
6961 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6964 /// SS41I_binop_rmi - SSE 4.1 binary operator with 8-bit immediate
6965 multiclass SS41I_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
6966 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
6967 X86MemOperand x86memop, bit Is2Addr = 1,
6968 OpndItins itins = DEFAULT_ITINS> {
6969 let isCommutable = 1 in
6970 def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),
6971 (ins RC:$src1, RC:$src2, u8imm:$src3),
6973 !strconcat(OpcodeStr,
6974 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6975 !strconcat(OpcodeStr,
6976 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6977 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))],
6978 itins.rr>, Sched<[itins.Sched]>;
6979 def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),
6980 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
6982 !strconcat(OpcodeStr,
6983 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
6984 !strconcat(OpcodeStr,
6985 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
6987 (OpVT (OpNode RC:$src1,
6988 (bitconvert (memop_frag addr:$src2)), imm:$src3)))], itins.rm>,
6989 Sched<[itins.Sched.Folded, ReadAfterLd]>;
6992 let Predicates = [HasAVX] in {
6993 let isCommutable = 0 in {
6994 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
6995 VR128, loadv2i64, i128mem, 0,
6996 DEFAULT_ITINS_MPSADSCHED>, VEX_4V;
6999 let ExeDomain = SSEPackedSingle in {
7000 defm VBLENDPS : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v4f32,
7001 VR128, loadv4f32, f128mem, 0,
7002 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7003 defm VBLENDPSY : SS41I_binop_rmi<0x0C, "vblendps", X86Blendi, v8f32,
7004 VR256, loadv8f32, f256mem, 0,
7005 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7007 let ExeDomain = SSEPackedDouble in {
7008 defm VBLENDPD : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v2f64,
7009 VR128, loadv2f64, f128mem, 0,
7010 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;
7011 defm VBLENDPDY : SS41I_binop_rmi<0x0D, "vblendpd", X86Blendi, v4f64,
7012 VR256, loadv4f64, f256mem, 0,
7013 DEFAULT_ITINS_FBLENDSCHED>, VEX_4V, VEX_L;
7015 defm VPBLENDW : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v8i16,
7016 VR128, loadv2i64, i128mem, 0,
7017 DEFAULT_ITINS_BLENDSCHED>, VEX_4V;
7019 let ExeDomain = SSEPackedSingle in
7020 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
7021 VR128, loadv4f32, f128mem, 0,
7022 SSE_DPPS_ITINS>, VEX_4V;
7023 let ExeDomain = SSEPackedDouble in
7024 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
7025 VR128, loadv2f64, f128mem, 0,
7026 SSE_DPPS_ITINS>, VEX_4V;
7027 let ExeDomain = SSEPackedSingle in
7028 defm VDPPSY : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_avx_dp_ps_256,
7029 VR256, loadv8f32, i256mem, 0,
7030 SSE_DPPS_ITINS>, VEX_4V, VEX_L;
7033 let Predicates = [HasAVX2] in {
7034 let isCommutable = 0 in {
7035 defm VMPSADBWY : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_avx2_mpsadbw,
7036 VR256, loadv4i64, i256mem, 0,
7037 DEFAULT_ITINS_MPSADSCHED>, VEX_4V, VEX_L;
7039 defm VPBLENDWY : SS41I_binop_rmi<0x0E, "vpblendw", X86Blendi, v16i16,
7040 VR256, loadv4i64, i256mem, 0,
7041 DEFAULT_ITINS_BLENDSCHED>, VEX_4V, VEX_L;
7044 let Constraints = "$src1 = $dst" in {
7045 let isCommutable = 0 in {
7046 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,
7047 VR128, memopv2i64, i128mem,
7048 1, SSE_MPSADBW_ITINS>;
7050 let ExeDomain = SSEPackedSingle in
7051 defm BLENDPS : SS41I_binop_rmi<0x0C, "blendps", X86Blendi, v4f32,
7052 VR128, memopv4f32, f128mem,
7053 1, SSE_INTALU_ITINS_FBLEND_P>;
7054 let ExeDomain = SSEPackedDouble in
7055 defm BLENDPD : SS41I_binop_rmi<0x0D, "blendpd", X86Blendi, v2f64,
7056 VR128, memopv2f64, f128mem,
7057 1, SSE_INTALU_ITINS_FBLEND_P>;
7058 defm PBLENDW : SS41I_binop_rmi<0x0E, "pblendw", X86Blendi, v8i16,
7059 VR128, memopv2i64, i128mem,
7060 1, SSE_INTALU_ITINS_BLEND_P>;
7061 let ExeDomain = SSEPackedSingle in
7062 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,
7063 VR128, memopv4f32, f128mem, 1,
7065 let ExeDomain = SSEPackedDouble in
7066 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd,
7067 VR128, memopv2f64, f128mem, 1,
7071 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
7072 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr,
7073 RegisterClass RC, X86MemOperand x86memop,
7074 PatFrag mem_frag, Intrinsic IntId,
7075 X86FoldableSchedWrite Sched> {
7076 def rr : Ii8<opc, MRMSrcReg, (outs RC:$dst),
7077 (ins RC:$src1, RC:$src2, RC:$src3),
7078 !strconcat(OpcodeStr,
7079 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7080 [(set RC:$dst, (IntId RC:$src1, RC:$src2, RC:$src3))],
7081 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7084 def rm : Ii8<opc, MRMSrcMem, (outs RC:$dst),
7085 (ins RC:$src1, x86memop:$src2, RC:$src3),
7086 !strconcat(OpcodeStr,
7087 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
7089 (IntId RC:$src1, (bitconvert (mem_frag addr:$src2)),
7091 NoItinerary, SSEPackedInt>, TAPD, VEX_4V, VEX_I8IMM,
7092 Sched<[Sched.Folded, ReadAfterLd]>;
7095 let Predicates = [HasAVX] in {
7096 let ExeDomain = SSEPackedDouble in {
7097 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR128, f128mem,
7098 loadv2f64, int_x86_sse41_blendvpd,
7100 defm VBLENDVPDY : SS41I_quaternary_int_avx<0x4B, "vblendvpd", VR256, f256mem,
7101 loadv4f64, int_x86_avx_blendv_pd_256,
7102 WriteFVarBlend>, VEX_L;
7103 } // ExeDomain = SSEPackedDouble
7104 let ExeDomain = SSEPackedSingle in {
7105 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR128, f128mem,
7106 loadv4f32, int_x86_sse41_blendvps,
7108 defm VBLENDVPSY : SS41I_quaternary_int_avx<0x4A, "vblendvps", VR256, f256mem,
7109 loadv8f32, int_x86_avx_blendv_ps_256,
7110 WriteFVarBlend>, VEX_L;
7111 } // ExeDomain = SSEPackedSingle
7112 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR128, i128mem,
7113 loadv2i64, int_x86_sse41_pblendvb,
7117 let Predicates = [HasAVX2] in {
7118 defm VPBLENDVBY : SS41I_quaternary_int_avx<0x4C, "vpblendvb", VR256, i256mem,
7119 loadv4i64, int_x86_avx2_pblendvb,
7120 WriteVarBlend>, VEX_L;
7123 let Predicates = [HasAVX] in {
7124 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
7125 (v16i8 VR128:$src2))),
7126 (VPBLENDVBrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7127 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
7128 (v4i32 VR128:$src2))),
7129 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7130 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
7131 (v4f32 VR128:$src2))),
7132 (VBLENDVPSrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7133 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
7134 (v2i64 VR128:$src2))),
7135 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7136 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
7137 (v2f64 VR128:$src2))),
7138 (VBLENDVPDrr VR128:$src2, VR128:$src1, VR128:$mask)>;
7139 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
7140 (v8i32 VR256:$src2))),
7141 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7142 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
7143 (v8f32 VR256:$src2))),
7144 (VBLENDVPSYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7145 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
7146 (v4i64 VR256:$src2))),
7147 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7148 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
7149 (v4f64 VR256:$src2))),
7150 (VBLENDVPDYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7153 let Predicates = [HasAVX2] in {
7154 def : Pat<(v32i8 (vselect (v32i8 VR256:$mask), (v32i8 VR256:$src1),
7155 (v32i8 VR256:$src2))),
7156 (VPBLENDVBYrr VR256:$src2, VR256:$src1, VR256:$mask)>;
7160 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7161 // on targets where they have equal performance. These were changed to use
7162 // blends because blends have better throughput on SandyBridge and Haswell, but
7163 // movs[s/d] are 1-2 byte shorter instructions.
7164 let Predicates = [UseAVX] in {
7165 let AddedComplexity = 15 in {
7166 // Move scalar to XMM zero-extended, zeroing a VR128 then do a
7167 // MOVS{S,D} to the lower bits.
7168 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
7169 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)>;
7170 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7171 (VBLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7172 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7173 (VPBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7174 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
7175 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)>;
7177 // Move low f32 and clear high bits.
7178 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256:$src))),
7179 (VBLENDPSYrri (v8f32 (AVX_SET0)), VR256:$src, (i8 1))>;
7181 // Move low f64 and clear high bits.
7182 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
7183 (VBLENDPDYrri (v4f64 (AVX_SET0)), VR256:$src, (i8 1))>;
7186 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
7187 (v4f32 (scalar_to_vector FR32:$src)), (iPTR 0)))),
7188 (SUBREG_TO_REG (i32 0),
7189 (v4f32 (VMOVSSrr (v4f32 (V_SET0)), FR32:$src)),
7191 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
7192 (v2f64 (scalar_to_vector FR64:$src)), (iPTR 0)))),
7193 (SUBREG_TO_REG (i64 0),
7194 (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
7197 // These will incur an FP/int domain crossing penalty, but it may be the only
7198 // way without AVX2. Do not add any complexity because we may be able to match
7199 // more optimal patterns defined earlier in this file.
7200 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256:$src))),
7201 (VBLENDPSYrri (v8i32 (AVX_SET0)), VR256:$src, (i8 1))>;
7202 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256:$src))),
7203 (VBLENDPDYrri (v4i64 (AVX_SET0)), VR256:$src, (i8 1))>;
7206 // FIXME: Prefer a movss or movsd over a blendps when optimizing for size or
7207 // on targets where they have equal performance. These were changed to use
7208 // blends because blends have better throughput on SandyBridge and Haswell, but
7209 // movs[s/d] are 1-2 byte shorter instructions.
7210 let Predicates = [UseSSE41] in {
7211 // With SSE41 we can use blends for these patterns.
7212 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
7213 (BLENDPSrri (v4f32 (V_SET0)), VR128:$src, (i8 1))>;
7214 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
7215 (PBLENDWrri (v4i32 (V_SET0)), VR128:$src, (i8 3))>;
7216 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
7217 (BLENDPDrri (v2f64 (V_SET0)), VR128:$src, (i8 1))>;
7221 /// SS41I_ternary_int - SSE 4.1 ternary operator
7222 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
7223 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
7224 X86MemOperand x86memop, Intrinsic IntId,
7225 OpndItins itins = DEFAULT_ITINS> {
7226 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
7227 (ins VR128:$src1, VR128:$src2),
7228 !strconcat(OpcodeStr,
7229 "\t{$src2, $dst|$dst, $src2}"),
7230 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))],
7231 itins.rr>, Sched<[itins.Sched]>;
7233 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
7234 (ins VR128:$src1, x86memop:$src2),
7235 !strconcat(OpcodeStr,
7236 "\t{$src2, $dst|$dst, $src2}"),
7239 (bitconvert (mem_frag addr:$src2)), XMM0))],
7240 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
7244 let ExeDomain = SSEPackedDouble in
7245 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", memopv2f64, f128mem,
7246 int_x86_sse41_blendvpd,
7247 DEFAULT_ITINS_FBLENDSCHED>;
7248 let ExeDomain = SSEPackedSingle in
7249 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", memopv4f32, f128mem,
7250 int_x86_sse41_blendvps,
7251 DEFAULT_ITINS_FBLENDSCHED>;
7252 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", memopv2i64, i128mem,
7253 int_x86_sse41_pblendvb,
7254 DEFAULT_ITINS_VARBLENDSCHED>;
7256 // Aliases with the implicit xmm0 argument
7257 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7258 (BLENDVPDrr0 VR128:$dst, VR128:$src2)>;
7259 def : InstAlias<"blendvpd\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7260 (BLENDVPDrm0 VR128:$dst, f128mem:$src2)>;
7261 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7262 (BLENDVPSrr0 VR128:$dst, VR128:$src2)>;
7263 def : InstAlias<"blendvps\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7264 (BLENDVPSrm0 VR128:$dst, f128mem:$src2)>;
7265 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7266 (PBLENDVBrr0 VR128:$dst, VR128:$src2)>;
7267 def : InstAlias<"pblendvb\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7268 (PBLENDVBrm0 VR128:$dst, i128mem:$src2)>;
7270 let Predicates = [UseSSE41] in {
7271 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
7272 (v16i8 VR128:$src2))),
7273 (PBLENDVBrr0 VR128:$src2, VR128:$src1)>;
7274 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
7275 (v4i32 VR128:$src2))),
7276 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7277 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
7278 (v4f32 VR128:$src2))),
7279 (BLENDVPSrr0 VR128:$src2, VR128:$src1)>;
7280 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
7281 (v2i64 VR128:$src2))),
7282 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7283 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
7284 (v2f64 VR128:$src2))),
7285 (BLENDVPDrr0 VR128:$src2, VR128:$src1)>;
7288 let SchedRW = [WriteLoad] in {
7289 let Predicates = [HasAVX] in
7290 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7291 "vmovntdqa\t{$src, $dst|$dst, $src}",
7292 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
7294 let Predicates = [HasAVX2] in
7295 def VMOVNTDQAYrm : SS48I<0x2A, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
7296 "vmovntdqa\t{$src, $dst|$dst, $src}",
7297 [(set VR256:$dst, (int_x86_avx2_movntdqa addr:$src))]>,
7299 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
7300 "movntdqa\t{$src, $dst|$dst, $src}",
7301 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
7304 //===----------------------------------------------------------------------===//
7305 // SSE4.2 - Compare Instructions
7306 //===----------------------------------------------------------------------===//
7308 /// SS42I_binop_rm - Simple SSE 4.2 binary operator
7309 multiclass SS42I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
7310 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
7311 X86MemOperand x86memop, bit Is2Addr = 1> {
7312 def rr : SS428I<opc, MRMSrcReg, (outs RC:$dst),
7313 (ins RC:$src1, RC:$src2),
7315 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7316 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7317 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2)))]>;
7318 def rm : SS428I<opc, MRMSrcMem, (outs RC:$dst),
7319 (ins RC:$src1, x86memop:$src2),
7321 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7322 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7324 (OpVT (OpNode RC:$src1, (memop_frag addr:$src2))))]>;
7327 let Predicates = [HasAVX] in
7328 defm VPCMPGTQ : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v2i64, VR128,
7329 loadv2i64, i128mem, 0>, VEX_4V;
7331 let Predicates = [HasAVX2] in
7332 defm VPCMPGTQY : SS42I_binop_rm<0x37, "vpcmpgtq", X86pcmpgt, v4i64, VR256,
7333 loadv4i64, i256mem, 0>, VEX_4V, VEX_L;
7335 let Constraints = "$src1 = $dst" in
7336 defm PCMPGTQ : SS42I_binop_rm<0x37, "pcmpgtq", X86pcmpgt, v2i64, VR128,
7337 memopv2i64, i128mem>;
7339 //===----------------------------------------------------------------------===//
7340 // SSE4.2 - String/text Processing Instructions
7341 //===----------------------------------------------------------------------===//
7343 // Packed Compare Implicit Length Strings, Return Mask
7344 multiclass pseudo_pcmpistrm<string asm, PatFrag ld_frag> {
7345 def REG : PseudoI<(outs VR128:$dst),
7346 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7347 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
7349 def MEM : PseudoI<(outs VR128:$dst),
7350 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7351 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1,
7352 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7355 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7356 defm VPCMPISTRM128 : pseudo_pcmpistrm<"#VPCMPISTRM128", loadv2i64>,
7358 defm PCMPISTRM128 : pseudo_pcmpistrm<"#PCMPISTRM128", memopv2i64>,
7359 Requires<[UseSSE42]>;
7362 multiclass pcmpistrm_SS42AI<string asm> {
7363 def rr : SS42AI<0x62, MRMSrcReg, (outs),
7364 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7365 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7366 []>, Sched<[WritePCmpIStrM]>;
7368 def rm :SS42AI<0x62, MRMSrcMem, (outs),
7369 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7370 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7371 []>, Sched<[WritePCmpIStrMLd, ReadAfterLd]>;
7374 let Defs = [XMM0, EFLAGS], hasSideEffects = 0 in {
7375 let Predicates = [HasAVX] in
7376 defm VPCMPISTRM128 : pcmpistrm_SS42AI<"vpcmpistrm">, VEX;
7377 defm PCMPISTRM128 : pcmpistrm_SS42AI<"pcmpistrm"> ;
7380 // Packed Compare Explicit Length Strings, Return Mask
7381 multiclass pseudo_pcmpestrm<string asm, PatFrag ld_frag> {
7382 def REG : PseudoI<(outs VR128:$dst),
7383 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7384 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
7385 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7386 def MEM : PseudoI<(outs VR128:$dst),
7387 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7388 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128 VR128:$src1, EAX,
7389 (bc_v16i8 (ld_frag addr:$src3)), EDX, imm:$src5))]>;
7392 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7393 defm VPCMPESTRM128 : pseudo_pcmpestrm<"#VPCMPESTRM128", loadv2i64>,
7395 defm PCMPESTRM128 : pseudo_pcmpestrm<"#PCMPESTRM128", memopv2i64>,
7396 Requires<[UseSSE42]>;
7399 multiclass SS42AI_pcmpestrm<string asm> {
7400 def rr : SS42AI<0x60, MRMSrcReg, (outs),
7401 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7402 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7403 []>, Sched<[WritePCmpEStrM]>;
7405 def rm : SS42AI<0x60, MRMSrcMem, (outs),
7406 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7407 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7408 []>, Sched<[WritePCmpEStrMLd, ReadAfterLd]>;
7411 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7412 let Predicates = [HasAVX] in
7413 defm VPCMPESTRM128 : SS42AI_pcmpestrm<"vpcmpestrm">, VEX;
7414 defm PCMPESTRM128 : SS42AI_pcmpestrm<"pcmpestrm">;
7417 // Packed Compare Implicit Length Strings, Return Index
7418 multiclass pseudo_pcmpistri<string asm, PatFrag ld_frag> {
7419 def REG : PseudoI<(outs GR32:$dst),
7420 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7421 [(set GR32:$dst, EFLAGS,
7422 (X86pcmpistri VR128:$src1, VR128:$src2, imm:$src3))]>;
7423 def MEM : PseudoI<(outs GR32:$dst),
7424 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7425 [(set GR32:$dst, EFLAGS, (X86pcmpistri VR128:$src1,
7426 (bc_v16i8 (ld_frag addr:$src2)), imm:$src3))]>;
7429 let Defs = [EFLAGS], usesCustomInserter = 1 in {
7430 defm VPCMPISTRI : pseudo_pcmpistri<"#VPCMPISTRI", loadv2i64>,
7432 defm PCMPISTRI : pseudo_pcmpistri<"#PCMPISTRI", memopv2i64>,
7433 Requires<[UseSSE42]>;
7436 multiclass SS42AI_pcmpistri<string asm> {
7437 def rr : SS42AI<0x63, MRMSrcReg, (outs),
7438 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7439 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7440 []>, Sched<[WritePCmpIStrI]>;
7442 def rm : SS42AI<0x63, MRMSrcMem, (outs),
7443 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7444 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
7445 []>, Sched<[WritePCmpIStrILd, ReadAfterLd]>;
7448 let Defs = [ECX, EFLAGS], hasSideEffects = 0 in {
7449 let Predicates = [HasAVX] in
7450 defm VPCMPISTRI : SS42AI_pcmpistri<"vpcmpistri">, VEX;
7451 defm PCMPISTRI : SS42AI_pcmpistri<"pcmpistri">;
7454 // Packed Compare Explicit Length Strings, Return Index
7455 multiclass pseudo_pcmpestri<string asm, PatFrag ld_frag> {
7456 def REG : PseudoI<(outs GR32:$dst),
7457 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7458 [(set GR32:$dst, EFLAGS,
7459 (X86pcmpestri VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>;
7460 def MEM : PseudoI<(outs GR32:$dst),
7461 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7462 [(set GR32:$dst, EFLAGS,
7463 (X86pcmpestri VR128:$src1, EAX, (bc_v16i8 (ld_frag addr:$src3)), EDX,
7467 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
7468 defm VPCMPESTRI : pseudo_pcmpestri<"#VPCMPESTRI", loadv2i64>,
7470 defm PCMPESTRI : pseudo_pcmpestri<"#PCMPESTRI", memopv2i64>,
7471 Requires<[UseSSE42]>;
7474 multiclass SS42AI_pcmpestri<string asm> {
7475 def rr : SS42AI<0x61, MRMSrcReg, (outs),
7476 (ins VR128:$src1, VR128:$src3, u8imm:$src5),
7477 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7478 []>, Sched<[WritePCmpEStrI]>;
7480 def rm : SS42AI<0x61, MRMSrcMem, (outs),
7481 (ins VR128:$src1, i128mem:$src3, u8imm:$src5),
7482 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
7483 []>, Sched<[WritePCmpEStrILd, ReadAfterLd]>;
7486 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX], hasSideEffects = 0 in {
7487 let Predicates = [HasAVX] in
7488 defm VPCMPESTRI : SS42AI_pcmpestri<"vpcmpestri">, VEX;
7489 defm PCMPESTRI : SS42AI_pcmpestri<"pcmpestri">;
7492 //===----------------------------------------------------------------------===//
7493 // SSE4.2 - CRC Instructions
7494 //===----------------------------------------------------------------------===//
7496 // No CRC instructions have AVX equivalents
7498 // crc intrinsic instruction
7499 // This set of instructions are only rm, the only difference is the size
7501 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
7502 RegisterClass RCIn, SDPatternOperator Int> :
7503 SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
7504 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7505 [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
7508 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
7509 X86MemOperand x86memop, SDPatternOperator Int> :
7510 SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
7511 !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
7512 [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
7513 IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
7515 let Constraints = "$src1 = $dst" in {
7516 def CRC32r32m8 : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
7517 int_x86_sse42_crc32_32_8>;
7518 def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
7519 int_x86_sse42_crc32_32_8>;
7520 def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
7521 int_x86_sse42_crc32_32_16>, OpSize16;
7522 def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
7523 int_x86_sse42_crc32_32_16>, OpSize16;
7524 def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
7525 int_x86_sse42_crc32_32_32>, OpSize32;
7526 def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
7527 int_x86_sse42_crc32_32_32>, OpSize32;
7528 def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
7529 int_x86_sse42_crc32_64_64>, REX_W;
7530 def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
7531 int_x86_sse42_crc32_64_64>, REX_W;
7532 let hasSideEffects = 0 in {
7534 def CRC32r64m8 : SS42I_crc32m<0xF0, "crc32{b}", GR64, i8mem,
7536 def CRC32r64r8 : SS42I_crc32r<0xF0, "crc32{b}", GR64, GR8,
7541 //===----------------------------------------------------------------------===//
7542 // SHA-NI Instructions
7543 //===----------------------------------------------------------------------===//
7545 multiclass SHAI_binop<bits<8> Opc, string OpcodeStr, Intrinsic IntId,
7547 def rr : I<Opc, MRMSrcReg, (outs VR128:$dst),
7548 (ins VR128:$src1, VR128:$src2),
7549 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7551 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0)),
7552 (set VR128:$dst, (IntId VR128:$src1, VR128:$src2)))]>, T8;
7554 def rm : I<Opc, MRMSrcMem, (outs VR128:$dst),
7555 (ins VR128:$src1, i128mem:$src2),
7556 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7558 (set VR128:$dst, (IntId VR128:$src1,
7559 (bc_v4i32 (memopv2i64 addr:$src2)), XMM0)),
7560 (set VR128:$dst, (IntId VR128:$src1,
7561 (bc_v4i32 (memopv2i64 addr:$src2)))))]>, T8;
7564 let Constraints = "$src1 = $dst", Predicates = [HasSHA] in {
7565 def SHA1RNDS4rri : Ii8<0xCC, MRMSrcReg, (outs VR128:$dst),
7566 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7567 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7569 (int_x86_sha1rnds4 VR128:$src1, VR128:$src2,
7570 (i8 imm:$src3)))]>, TA;
7571 def SHA1RNDS4rmi : Ii8<0xCC, MRMSrcMem, (outs VR128:$dst),
7572 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7573 "sha1rnds4\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7575 (int_x86_sha1rnds4 VR128:$src1,
7576 (bc_v4i32 (memopv2i64 addr:$src2)),
7577 (i8 imm:$src3)))]>, TA;
7579 defm SHA1NEXTE : SHAI_binop<0xC8, "sha1nexte", int_x86_sha1nexte>;
7580 defm SHA1MSG1 : SHAI_binop<0xC9, "sha1msg1", int_x86_sha1msg1>;
7581 defm SHA1MSG2 : SHAI_binop<0xCA, "sha1msg2", int_x86_sha1msg2>;
7584 defm SHA256RNDS2 : SHAI_binop<0xCB, "sha256rnds2", int_x86_sha256rnds2, 1>;
7586 defm SHA256MSG1 : SHAI_binop<0xCC, "sha256msg1", int_x86_sha256msg1>;
7587 defm SHA256MSG2 : SHAI_binop<0xCD, "sha256msg2", int_x86_sha256msg2>;
7590 // Aliases with explicit %xmm0
7591 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7592 (SHA256RNDS2rr VR128:$dst, VR128:$src2)>;
7593 def : InstAlias<"sha256rnds2\t{%xmm0, $src2, $dst|$dst, $src2, xmm0}",
7594 (SHA256RNDS2rm VR128:$dst, i128mem:$src2)>;
7596 //===----------------------------------------------------------------------===//
7597 // AES-NI Instructions
7598 //===----------------------------------------------------------------------===//
7600 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
7601 PatFrag ld_frag, bit Is2Addr = 1> {
7602 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
7603 (ins VR128:$src1, VR128:$src2),
7605 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7606 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7607 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
7608 Sched<[WriteAESDecEnc]>;
7609 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
7610 (ins VR128:$src1, i128mem:$src2),
7612 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
7613 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
7615 (IntId128 VR128:$src1, (ld_frag addr:$src2)))]>,
7616 Sched<[WriteAESDecEncLd, ReadAfterLd]>;
7619 // Perform One Round of an AES Encryption/Decryption Flow
7620 let Predicates = [HasAVX, HasAES] in {
7621 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
7622 int_x86_aesni_aesenc, loadv2i64, 0>, VEX_4V;
7623 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
7624 int_x86_aesni_aesenclast, loadv2i64, 0>, VEX_4V;
7625 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
7626 int_x86_aesni_aesdec, loadv2i64, 0>, VEX_4V;
7627 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
7628 int_x86_aesni_aesdeclast, loadv2i64, 0>, VEX_4V;
7631 let Constraints = "$src1 = $dst" in {
7632 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
7633 int_x86_aesni_aesenc, memopv2i64>;
7634 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
7635 int_x86_aesni_aesenclast, memopv2i64>;
7636 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
7637 int_x86_aesni_aesdec, memopv2i64>;
7638 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
7639 int_x86_aesni_aesdeclast, memopv2i64>;
7642 // Perform the AES InvMixColumn Transformation
7643 let Predicates = [HasAVX, HasAES] in {
7644 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7646 "vaesimc\t{$src1, $dst|$dst, $src1}",
7648 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>,
7650 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7651 (ins i128mem:$src1),
7652 "vaesimc\t{$src1, $dst|$dst, $src1}",
7653 [(set VR128:$dst, (int_x86_aesni_aesimc (loadv2i64 addr:$src1)))]>,
7654 Sched<[WriteAESIMCLd]>, VEX;
7656 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
7658 "aesimc\t{$src1, $dst|$dst, $src1}",
7660 (int_x86_aesni_aesimc VR128:$src1))]>, Sched<[WriteAESIMC]>;
7661 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
7662 (ins i128mem:$src1),
7663 "aesimc\t{$src1, $dst|$dst, $src1}",
7664 [(set VR128:$dst, (int_x86_aesni_aesimc (memopv2i64 addr:$src1)))]>,
7665 Sched<[WriteAESIMCLd]>;
7667 // AES Round Key Generation Assist
7668 let Predicates = [HasAVX, HasAES] in {
7669 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7670 (ins VR128:$src1, u8imm:$src2),
7671 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7673 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7674 Sched<[WriteAESKeyGen]>, VEX;
7675 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7676 (ins i128mem:$src1, u8imm:$src2),
7677 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7679 (int_x86_aesni_aeskeygenassist (loadv2i64 addr:$src1), imm:$src2))]>,
7680 Sched<[WriteAESKeyGenLd]>, VEX;
7682 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
7683 (ins VR128:$src1, u8imm:$src2),
7684 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7686 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
7687 Sched<[WriteAESKeyGen]>;
7688 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
7689 (ins i128mem:$src1, u8imm:$src2),
7690 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7692 (int_x86_aesni_aeskeygenassist (memopv2i64 addr:$src1), imm:$src2))]>,
7693 Sched<[WriteAESKeyGenLd]>;
7695 //===----------------------------------------------------------------------===//
7696 // PCLMUL Instructions
7697 //===----------------------------------------------------------------------===//
7699 // AVX carry-less Multiplication instructions
7700 let isCommutable = 1 in
7701 def VPCLMULQDQrr : AVXPCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7702 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7703 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7705 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))]>,
7706 Sched<[WriteCLMul]>;
7708 def VPCLMULQDQrm : AVXPCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7709 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7710 "vpclmulqdq\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7711 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7712 (loadv2i64 addr:$src2), imm:$src3))]>,
7713 Sched<[WriteCLMulLd, ReadAfterLd]>;
7715 // Carry-less Multiplication instructions
7716 let Constraints = "$src1 = $dst" in {
7717 let isCommutable = 1 in
7718 def PCLMULQDQrr : PCLMULIi8<0x44, MRMSrcReg, (outs VR128:$dst),
7719 (ins VR128:$src1, VR128:$src2, u8imm:$src3),
7720 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7722 (int_x86_pclmulqdq VR128:$src1, VR128:$src2, imm:$src3))],
7723 IIC_SSE_PCLMULQDQ_RR>, Sched<[WriteCLMul]>;
7725 def PCLMULQDQrm : PCLMULIi8<0x44, MRMSrcMem, (outs VR128:$dst),
7726 (ins VR128:$src1, i128mem:$src2, u8imm:$src3),
7727 "pclmulqdq\t{$src3, $src2, $dst|$dst, $src2, $src3}",
7728 [(set VR128:$dst, (int_x86_pclmulqdq VR128:$src1,
7729 (memopv2i64 addr:$src2), imm:$src3))],
7730 IIC_SSE_PCLMULQDQ_RM>,
7731 Sched<[WriteCLMulLd, ReadAfterLd]>;
7732 } // Constraints = "$src1 = $dst"
7735 multiclass pclmul_alias<string asm, int immop> {
7736 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7737 (PCLMULQDQrr VR128:$dst, VR128:$src, immop), 0>;
7739 def : InstAlias<!strconcat("pclmul", asm, "dq {$src, $dst|$dst, $src}"),
7740 (PCLMULQDQrm VR128:$dst, i128mem:$src, immop), 0>;
7742 def : InstAlias<!strconcat("vpclmul", asm,
7743 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7744 (VPCLMULQDQrr VR128:$dst, VR128:$src1, VR128:$src2, immop),
7747 def : InstAlias<!strconcat("vpclmul", asm,
7748 "dq {$src2, $src1, $dst|$dst, $src1, $src2}"),
7749 (VPCLMULQDQrm VR128:$dst, VR128:$src1, i128mem:$src2, immop),
7752 defm : pclmul_alias<"hqhq", 0x11>;
7753 defm : pclmul_alias<"hqlq", 0x01>;
7754 defm : pclmul_alias<"lqhq", 0x10>;
7755 defm : pclmul_alias<"lqlq", 0x00>;
7757 //===----------------------------------------------------------------------===//
7758 // SSE4A Instructions
7759 //===----------------------------------------------------------------------===//
7761 let Predicates = [HasSSE4A] in {
7763 let Constraints = "$src = $dst" in {
7764 def EXTRQI : Ii8<0x78, MRMXr, (outs VR128:$dst),
7765 (ins VR128:$src, u8imm:$len, u8imm:$idx),
7766 "extrq\t{$idx, $len, $src|$src, $len, $idx}",
7767 [(set VR128:$dst, (int_x86_sse4a_extrqi VR128:$src, imm:$len,
7769 def EXTRQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7770 (ins VR128:$src, VR128:$mask),
7771 "extrq\t{$mask, $src|$src, $mask}",
7772 [(set VR128:$dst, (int_x86_sse4a_extrq VR128:$src,
7773 VR128:$mask))]>, PD;
7775 def INSERTQI : Ii8<0x78, MRMSrcReg, (outs VR128:$dst),
7776 (ins VR128:$src, VR128:$src2, u8imm:$len, u8imm:$idx),
7777 "insertq\t{$idx, $len, $src2, $src|$src, $src2, $len, $idx}",
7778 [(set VR128:$dst, (int_x86_sse4a_insertqi VR128:$src,
7779 VR128:$src2, imm:$len, imm:$idx))]>, XD;
7780 def INSERTQ : I<0x79, MRMSrcReg, (outs VR128:$dst),
7781 (ins VR128:$src, VR128:$mask),
7782 "insertq\t{$mask, $src|$src, $mask}",
7783 [(set VR128:$dst, (int_x86_sse4a_insertq VR128:$src,
7784 VR128:$mask))]>, XD;
7787 def MOVNTSS : I<0x2B, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
7788 "movntss\t{$src, $dst|$dst, $src}",
7789 [(int_x86_sse4a_movnt_ss addr:$dst, VR128:$src)]>, XS;
7791 def MOVNTSD : I<0x2B, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
7792 "movntsd\t{$src, $dst|$dst, $src}",
7793 [(int_x86_sse4a_movnt_sd addr:$dst, VR128:$src)]>, XD;
7796 //===----------------------------------------------------------------------===//
7798 //===----------------------------------------------------------------------===//
7800 //===----------------------------------------------------------------------===//
7801 // VBROADCAST - Load from memory and broadcast to all elements of the
7802 // destination operand
7804 class avx_broadcast<bits<8> opc, string OpcodeStr, RegisterClass RC,
7805 X86MemOperand x86memop, Intrinsic Int, SchedWrite Sched> :
7806 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7807 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7808 [(set RC:$dst, (Int addr:$src))]>, Sched<[Sched]>, VEX;
7810 class avx_broadcast_no_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
7811 X86MemOperand x86memop, ValueType VT,
7812 PatFrag ld_frag, SchedWrite Sched> :
7813 AVX8I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
7814 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7815 [(set RC:$dst, (VT (X86VBroadcast (ld_frag addr:$src))))]>,
7816 Sched<[Sched]>, VEX {
7820 // AVX2 adds register forms
7821 class avx2_broadcast_reg<bits<8> opc, string OpcodeStr, RegisterClass RC,
7822 Intrinsic Int, SchedWrite Sched> :
7823 AVX28I<opc, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
7824 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
7825 [(set RC:$dst, (Int VR128:$src))]>, Sched<[Sched]>, VEX;
7827 let ExeDomain = SSEPackedSingle in {
7828 def VBROADCASTSSrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR128,
7829 f32mem, v4f32, loadf32, WriteLoad>;
7830 def VBROADCASTSSYrm : avx_broadcast_no_int<0x18, "vbroadcastss", VR256,
7831 f32mem, v8f32, loadf32,
7832 WriteFShuffleLd>, VEX_L;
7834 let ExeDomain = SSEPackedDouble in
7835 def VBROADCASTSDYrm : avx_broadcast_no_int<0x19, "vbroadcastsd", VR256, f64mem,
7836 v4f64, loadf64, WriteFShuffleLd>, VEX_L;
7837 def VBROADCASTF128 : avx_broadcast<0x1A, "vbroadcastf128", VR256, f128mem,
7838 int_x86_avx_vbroadcastf128_pd_256,
7839 WriteFShuffleLd>, VEX_L;
7841 let ExeDomain = SSEPackedSingle in {
7842 def VBROADCASTSSrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR128,
7843 int_x86_avx2_vbroadcast_ss_ps,
7845 def VBROADCASTSSYrr : avx2_broadcast_reg<0x18, "vbroadcastss", VR256,
7846 int_x86_avx2_vbroadcast_ss_ps_256,
7847 WriteFShuffle256>, VEX_L;
7849 let ExeDomain = SSEPackedDouble in
7850 def VBROADCASTSDYrr : avx2_broadcast_reg<0x19, "vbroadcastsd", VR256,
7851 int_x86_avx2_vbroadcast_sd_pd_256,
7852 WriteFShuffle256>, VEX_L;
7854 let Predicates = [HasAVX2] in
7855 def VBROADCASTI128 : avx_broadcast_no_int<0x5A, "vbroadcasti128", VR256,
7856 i128mem, v4i64, loadv2i64,
7859 let Predicates = [HasAVX] in
7860 def : Pat<(int_x86_avx_vbroadcastf128_ps_256 addr:$src),
7861 (VBROADCASTF128 addr:$src)>;
7864 //===----------------------------------------------------------------------===//
7865 // VINSERTF128 - Insert packed floating-point values
7867 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7868 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
7869 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
7870 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7871 []>, Sched<[WriteFShuffle]>, VEX_4V, VEX_L;
7873 def VINSERTF128rm : AVXAIi8<0x18, MRMSrcMem, (outs VR256:$dst),
7874 (ins VR256:$src1, f128mem:$src2, u8imm:$src3),
7875 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
7876 []>, Sched<[WriteFShuffleLd, ReadAfterLd]>, VEX_4V, VEX_L;
7879 let Predicates = [HasAVX] in {
7880 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (v4f32 VR128:$src2),
7882 (VINSERTF128rr VR256:$src1, VR128:$src2,
7883 (INSERT_get_vinsert128_imm VR256:$ins))>;
7884 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (v2f64 VR128:$src2),
7886 (VINSERTF128rr VR256:$src1, VR128:$src2,
7887 (INSERT_get_vinsert128_imm VR256:$ins))>;
7889 def : Pat<(vinsert128_insert:$ins (v8f32 VR256:$src1), (loadv4f32 addr:$src2),
7891 (VINSERTF128rm VR256:$src1, addr:$src2,
7892 (INSERT_get_vinsert128_imm VR256:$ins))>;
7893 def : Pat<(vinsert128_insert:$ins (v4f64 VR256:$src1), (loadv2f64 addr:$src2),
7895 (VINSERTF128rm VR256:$src1, addr:$src2,
7896 (INSERT_get_vinsert128_imm VR256:$ins))>;
7899 let Predicates = [HasAVX1Only] in {
7900 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
7902 (VINSERTF128rr VR256:$src1, VR128:$src2,
7903 (INSERT_get_vinsert128_imm VR256:$ins))>;
7904 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
7906 (VINSERTF128rr VR256:$src1, VR128:$src2,
7907 (INSERT_get_vinsert128_imm VR256:$ins))>;
7908 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
7910 (VINSERTF128rr VR256:$src1, VR128:$src2,
7911 (INSERT_get_vinsert128_imm VR256:$ins))>;
7912 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
7914 (VINSERTF128rr VR256:$src1, VR128:$src2,
7915 (INSERT_get_vinsert128_imm VR256:$ins))>;
7917 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
7919 (VINSERTF128rm VR256:$src1, addr:$src2,
7920 (INSERT_get_vinsert128_imm VR256:$ins))>;
7921 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
7922 (bc_v4i32 (loadv2i64 addr:$src2)),
7924 (VINSERTF128rm VR256:$src1, addr:$src2,
7925 (INSERT_get_vinsert128_imm VR256:$ins))>;
7926 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
7927 (bc_v16i8 (loadv2i64 addr:$src2)),
7929 (VINSERTF128rm VR256:$src1, addr:$src2,
7930 (INSERT_get_vinsert128_imm VR256:$ins))>;
7931 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
7932 (bc_v8i16 (loadv2i64 addr:$src2)),
7934 (VINSERTF128rm VR256:$src1, addr:$src2,
7935 (INSERT_get_vinsert128_imm VR256:$ins))>;
7938 //===----------------------------------------------------------------------===//
7939 // VEXTRACTF128 - Extract packed floating-point values
7941 let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
7942 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
7943 (ins VR256:$src1, u8imm:$src2),
7944 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7945 []>, Sched<[WriteFShuffle]>, VEX, VEX_L;
7947 def VEXTRACTF128mr : AVXAIi8<0x19, MRMDestMem, (outs),
7948 (ins f128mem:$dst, VR256:$src1, u8imm:$src2),
7949 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
7950 []>, Sched<[WriteStore]>, VEX, VEX_L;
7954 let Predicates = [HasAVX] in {
7955 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7956 (v4f32 (VEXTRACTF128rr
7957 (v8f32 VR256:$src1),
7958 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7959 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7960 (v2f64 (VEXTRACTF128rr
7961 (v4f64 VR256:$src1),
7962 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7964 def : Pat<(store (v4f32 (vextract128_extract:$ext (v8f32 VR256:$src1),
7965 (iPTR imm))), addr:$dst),
7966 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7967 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7968 def : Pat<(store (v2f64 (vextract128_extract:$ext (v4f64 VR256:$src1),
7969 (iPTR imm))), addr:$dst),
7970 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7971 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7974 let Predicates = [HasAVX1Only] in {
7975 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7976 (v2i64 (VEXTRACTF128rr
7977 (v4i64 VR256:$src1),
7978 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7979 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7980 (v4i32 (VEXTRACTF128rr
7981 (v8i32 VR256:$src1),
7982 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7983 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7984 (v8i16 (VEXTRACTF128rr
7985 (v16i16 VR256:$src1),
7986 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7987 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
7988 (v16i8 (VEXTRACTF128rr
7989 (v32i8 VR256:$src1),
7990 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
7992 def : Pat<(alignedstore (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
7993 (iPTR imm))), addr:$dst),
7994 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7995 (EXTRACT_get_vextract128_imm VR128:$ext))>;
7996 def : Pat<(alignedstore (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
7997 (iPTR imm))), addr:$dst),
7998 (VEXTRACTF128mr addr:$dst, VR256:$src1,
7999 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8000 def : Pat<(alignedstore (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8001 (iPTR imm))), addr:$dst),
8002 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8003 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8004 def : Pat<(alignedstore (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8005 (iPTR imm))), addr:$dst),
8006 (VEXTRACTF128mr addr:$dst, VR256:$src1,
8007 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8010 //===----------------------------------------------------------------------===//
8011 // VMASKMOV - Conditional SIMD Packed Loads and Stores
8013 multiclass avx_movmask_rm<bits<8> opc_rm, bits<8> opc_mr, string OpcodeStr,
8014 Intrinsic IntLd, Intrinsic IntLd256,
8015 Intrinsic IntSt, Intrinsic IntSt256> {
8016 def rm : AVX8I<opc_rm, MRMSrcMem, (outs VR128:$dst),
8017 (ins VR128:$src1, f128mem:$src2),
8018 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8019 [(set VR128:$dst, (IntLd addr:$src2, VR128:$src1))]>,
8021 def Yrm : AVX8I<opc_rm, MRMSrcMem, (outs VR256:$dst),
8022 (ins VR256:$src1, f256mem:$src2),
8023 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8024 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8026 def mr : AVX8I<opc_mr, MRMDestMem, (outs),
8027 (ins f128mem:$dst, VR128:$src1, VR128:$src2),
8028 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8029 [(IntSt addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8030 def Ymr : AVX8I<opc_mr, MRMDestMem, (outs),
8031 (ins f256mem:$dst, VR256:$src1, VR256:$src2),
8032 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8033 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8036 let ExeDomain = SSEPackedSingle in
8037 defm VMASKMOVPS : avx_movmask_rm<0x2C, 0x2E, "vmaskmovps",
8038 int_x86_avx_maskload_ps,
8039 int_x86_avx_maskload_ps_256,
8040 int_x86_avx_maskstore_ps,
8041 int_x86_avx_maskstore_ps_256>;
8042 let ExeDomain = SSEPackedDouble in
8043 defm VMASKMOVPD : avx_movmask_rm<0x2D, 0x2F, "vmaskmovpd",
8044 int_x86_avx_maskload_pd,
8045 int_x86_avx_maskload_pd_256,
8046 int_x86_avx_maskstore_pd,
8047 int_x86_avx_maskstore_pd_256>;
8049 //===----------------------------------------------------------------------===//
8050 // VPERMIL - Permute Single and Double Floating-Point Values
8052 multiclass avx_permil<bits<8> opc_rm, bits<8> opc_rmi, string OpcodeStr,
8053 RegisterClass RC, X86MemOperand x86memop_f,
8054 X86MemOperand x86memop_i, PatFrag i_frag,
8055 Intrinsic IntVar, ValueType vt> {
8056 def rr : AVX8I<opc_rm, MRMSrcReg, (outs RC:$dst),
8057 (ins RC:$src1, RC:$src2),
8058 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8059 [(set RC:$dst, (IntVar RC:$src1, RC:$src2))]>, VEX_4V,
8060 Sched<[WriteFShuffle]>;
8061 def rm : AVX8I<opc_rm, MRMSrcMem, (outs RC:$dst),
8062 (ins RC:$src1, x86memop_i:$src2),
8063 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8064 [(set RC:$dst, (IntVar RC:$src1,
8065 (bitconvert (i_frag addr:$src2))))]>, VEX_4V,
8066 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8068 def ri : AVXAIi8<opc_rmi, MRMSrcReg, (outs RC:$dst),
8069 (ins RC:$src1, u8imm:$src2),
8070 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8071 [(set RC:$dst, (vt (X86VPermilpi RC:$src1, (i8 imm:$src2))))]>, VEX,
8072 Sched<[WriteFShuffle]>;
8073 def mi : AVXAIi8<opc_rmi, MRMSrcMem, (outs RC:$dst),
8074 (ins x86memop_f:$src1, u8imm:$src2),
8075 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8077 (vt (X86VPermilpi (load addr:$src1), (i8 imm:$src2))))]>, VEX,
8078 Sched<[WriteFShuffleLd]>;
8081 let ExeDomain = SSEPackedSingle in {
8082 defm VPERMILPS : avx_permil<0x0C, 0x04, "vpermilps", VR128, f128mem, i128mem,
8083 loadv2i64, int_x86_avx_vpermilvar_ps, v4f32>;
8084 defm VPERMILPSY : avx_permil<0x0C, 0x04, "vpermilps", VR256, f256mem, i256mem,
8085 loadv4i64, int_x86_avx_vpermilvar_ps_256, v8f32>, VEX_L;
8087 let ExeDomain = SSEPackedDouble in {
8088 defm VPERMILPD : avx_permil<0x0D, 0x05, "vpermilpd", VR128, f128mem, i128mem,
8089 loadv2i64, int_x86_avx_vpermilvar_pd, v2f64>;
8090 defm VPERMILPDY : avx_permil<0x0D, 0x05, "vpermilpd", VR256, f256mem, i256mem,
8091 loadv4i64, int_x86_avx_vpermilvar_pd_256, v4f64>, VEX_L;
8094 let Predicates = [HasAVX] in {
8095 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (v8i32 VR256:$src2))),
8096 (VPERMILPSYrr VR256:$src1, VR256:$src2)>;
8097 def : Pat<(v8f32 (X86VPermilpv VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)))),
8098 (VPERMILPSYrm VR256:$src1, addr:$src2)>;
8099 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (v4i64 VR256:$src2))),
8100 (VPERMILPDYrr VR256:$src1, VR256:$src2)>;
8101 def : Pat<(v4f64 (X86VPermilpv VR256:$src1, (loadv4i64 addr:$src2))),
8102 (VPERMILPDYrm VR256:$src1, addr:$src2)>;
8104 def : Pat<(v8i32 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8105 (VPERMILPSYri VR256:$src1, imm:$imm)>;
8106 def : Pat<(v4i64 (X86VPermilpi VR256:$src1, (i8 imm:$imm))),
8107 (VPERMILPDYri VR256:$src1, imm:$imm)>;
8108 def : Pat<(v8i32 (X86VPermilpi (bc_v8i32 (loadv4i64 addr:$src1)),
8110 (VPERMILPSYmi addr:$src1, imm:$imm)>;
8111 def : Pat<(v4i64 (X86VPermilpi (loadv4i64 addr:$src1), (i8 imm:$imm))),
8112 (VPERMILPDYmi addr:$src1, imm:$imm)>;
8114 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (v4i32 VR128:$src2))),
8115 (VPERMILPSrr VR128:$src1, VR128:$src2)>;
8116 def : Pat<(v4f32 (X86VPermilpv VR128:$src1, (bc_v4i32 (loadv2i64 addr:$src2)))),
8117 (VPERMILPSrm VR128:$src1, addr:$src2)>;
8118 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (v2i64 VR128:$src2))),
8119 (VPERMILPDrr VR128:$src1, VR128:$src2)>;
8120 def : Pat<(v2f64 (X86VPermilpv VR128:$src1, (loadv2i64 addr:$src2))),
8121 (VPERMILPDrm VR128:$src1, addr:$src2)>;
8123 def : Pat<(v2i64 (X86VPermilpi VR128:$src1, (i8 imm:$imm))),
8124 (VPERMILPDri VR128:$src1, imm:$imm)>;
8125 def : Pat<(v2i64 (X86VPermilpi (loadv2i64 addr:$src1), (i8 imm:$imm))),
8126 (VPERMILPDmi addr:$src1, imm:$imm)>;
8129 //===----------------------------------------------------------------------===//
8130 // VPERM2F128 - Permute Floating-Point Values in 128-bit chunks
8132 let ExeDomain = SSEPackedSingle in {
8133 def VPERM2F128rr : AVXAIi8<0x06, MRMSrcReg, (outs VR256:$dst),
8134 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8135 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8136 [(set VR256:$dst, (v8f32 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8137 (i8 imm:$src3))))]>, VEX_4V, VEX_L,
8138 Sched<[WriteFShuffle]>;
8139 def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst),
8140 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8141 "vperm2f128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8142 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv8f32 addr:$src2),
8143 (i8 imm:$src3)))]>, VEX_4V, VEX_L,
8144 Sched<[WriteFShuffleLd, ReadAfterLd]>;
8147 let Predicates = [HasAVX] in {
8148 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8149 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8150 def : Pat<(v4f64 (X86VPerm2x128 VR256:$src1,
8151 (loadv4f64 addr:$src2), (i8 imm:$imm))),
8152 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8155 let Predicates = [HasAVX1Only] in {
8156 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8157 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8158 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8159 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8160 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8161 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8162 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8163 (VPERM2F128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8165 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1,
8166 (bc_v8i32 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8167 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8168 def : Pat<(v4i64 (X86VPerm2x128 VR256:$src1,
8169 (loadv4i64 addr:$src2), (i8 imm:$imm))),
8170 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8171 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1,
8172 (bc_v32i8 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8173 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8174 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8175 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8176 (VPERM2F128rm VR256:$src1, addr:$src2, imm:$imm)>;
8179 //===----------------------------------------------------------------------===//
8180 // VZERO - Zero YMM registers
8182 let Defs = [YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7,
8183 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
8184 // Zero All YMM registers
8185 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
8186 [(int_x86_avx_vzeroall)]>, PS, VEX, VEX_L, Requires<[HasAVX]>;
8188 // Zero Upper bits of YMM registers
8189 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
8190 [(int_x86_avx_vzeroupper)]>, PS, VEX, Requires<[HasAVX]>;
8193 //===----------------------------------------------------------------------===//
8194 // Half precision conversion instructions
8195 //===----------------------------------------------------------------------===//
8196 multiclass f16c_ph2ps<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8197 def rr : I<0x13, MRMSrcReg, (outs RC:$dst), (ins VR128:$src),
8198 "vcvtph2ps\t{$src, $dst|$dst, $src}",
8199 [(set RC:$dst, (Int VR128:$src))]>,
8200 T8PD, VEX, Sched<[WriteCvtF2F]>;
8201 let hasSideEffects = 0, mayLoad = 1 in
8202 def rm : I<0x13, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
8203 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8PD, VEX,
8204 Sched<[WriteCvtF2FLd]>;
8207 multiclass f16c_ps2ph<RegisterClass RC, X86MemOperand x86memop, Intrinsic Int> {
8208 def rr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
8209 (ins RC:$src1, i32u8imm:$src2),
8210 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}",
8211 [(set VR128:$dst, (Int RC:$src1, imm:$src2))]>,
8212 TAPD, VEX, Sched<[WriteCvtF2F]>;
8213 let hasSideEffects = 0, mayStore = 1,
8214 SchedRW = [WriteCvtF2FLd, WriteRMW] in
8215 def mr : Ii8<0x1D, MRMDestMem, (outs),
8216 (ins x86memop:$dst, RC:$src1, i32u8imm:$src2),
8217 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8221 let Predicates = [HasF16C] in {
8222 defm VCVTPH2PS : f16c_ph2ps<VR128, f64mem, int_x86_vcvtph2ps_128>;
8223 defm VCVTPH2PSY : f16c_ph2ps<VR256, f128mem, int_x86_vcvtph2ps_256>, VEX_L;
8224 defm VCVTPS2PH : f16c_ps2ph<VR128, f64mem, int_x86_vcvtps2ph_128>;
8225 defm VCVTPS2PHY : f16c_ps2ph<VR256, f128mem, int_x86_vcvtps2ph_256>, VEX_L;
8227 // Pattern match vcvtph2ps of a scalar i64 load.
8228 def : Pat<(int_x86_vcvtph2ps_128 (vzmovl_v2i64 addr:$src)),
8229 (VCVTPH2PSrm addr:$src)>;
8230 def : Pat<(int_x86_vcvtph2ps_128 (vzload_v2i64 addr:$src)),
8231 (VCVTPH2PSrm addr:$src)>;
8233 def : Pat<(store (f64 (vector_extract (bc_v2f64 (v8i16
8234 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8236 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8237 def : Pat<(store (i64 (vector_extract (bc_v2i64 (v8i16
8238 (int_x86_vcvtps2ph_128 VR128:$src1, i32:$src2))), (iPTR 0))),
8240 (VCVTPS2PHmr addr:$dst, VR128:$src1, imm:$src2)>;
8241 def : Pat<(store (v8i16 (int_x86_vcvtps2ph_256 VR256:$src1, i32:$src2)),
8243 (VCVTPS2PHYmr addr:$dst, VR256:$src1, imm:$src2)>;
8246 // Patterns for matching conversions from float to half-float and vice versa.
8247 let Predicates = [HasF16C] in {
8248 def : Pat<(fp_to_f16 FR32:$src),
8249 (i16 (EXTRACT_SUBREG (VMOVPDI2DIrr (VCVTPS2PHrr
8250 (COPY_TO_REGCLASS FR32:$src, VR128), 0)), sub_16bit))>;
8252 def : Pat<(f16_to_fp GR16:$src),
8253 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8254 (COPY_TO_REGCLASS (MOVSX32rr16 GR16:$src), VR128)), FR32)) >;
8256 def : Pat<(f16_to_fp (i16 (fp_to_f16 FR32:$src))),
8257 (f32 (COPY_TO_REGCLASS (VCVTPH2PSrr
8258 (VCVTPS2PHrr (COPY_TO_REGCLASS FR32:$src, VR128), 0)), FR32)) >;
8261 //===----------------------------------------------------------------------===//
8262 // AVX2 Instructions
8263 //===----------------------------------------------------------------------===//
8265 /// AVX2_binop_rmi - AVX2 binary operator with 8-bit immediate
8266 multiclass AVX2_binop_rmi<bits<8> opc, string OpcodeStr, SDNode OpNode,
8267 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
8268 X86MemOperand x86memop> {
8269 let isCommutable = 1 in
8270 def rri : AVX2AIi8<opc, MRMSrcReg, (outs RC:$dst),
8271 (ins RC:$src1, RC:$src2, u8imm:$src3),
8272 !strconcat(OpcodeStr,
8273 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8274 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2, imm:$src3)))]>,
8275 Sched<[WriteBlend]>, VEX_4V;
8276 def rmi : AVX2AIi8<opc, MRMSrcMem, (outs RC:$dst),
8277 (ins RC:$src1, x86memop:$src2, u8imm:$src3),
8278 !strconcat(OpcodeStr,
8279 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
8281 (OpVT (OpNode RC:$src1,
8282 (bitconvert (memop_frag addr:$src2)), imm:$src3)))]>,
8283 Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;
8286 defm VPBLENDD : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v4i32,
8287 VR128, loadv2i64, i128mem>;
8288 defm VPBLENDDY : AVX2_binop_rmi<0x02, "vpblendd", X86Blendi, v8i32,
8289 VR256, loadv4i64, i256mem>, VEX_L;
8291 //===----------------------------------------------------------------------===//
8292 // VPBROADCAST - Load from memory and broadcast to all elements of the
8293 // destination operand
8295 multiclass avx2_broadcast<bits<8> opc, string OpcodeStr,
8296 X86MemOperand x86memop, PatFrag ld_frag,
8297 Intrinsic Int128, Intrinsic Int256> {
8298 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
8299 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8300 [(set VR128:$dst, (Int128 VR128:$src))]>,
8301 Sched<[WriteShuffle]>, VEX;
8302 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst), (ins x86memop:$src),
8303 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8305 (Int128 (scalar_to_vector (ld_frag addr:$src))))]>,
8306 Sched<[WriteLoad]>, VEX;
8307 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
8308 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8309 [(set VR256:$dst, (Int256 VR128:$src))]>,
8310 Sched<[WriteShuffle256]>, VEX, VEX_L;
8311 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst), (ins x86memop:$src),
8312 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
8314 (Int256 (scalar_to_vector (ld_frag addr:$src))))]>,
8315 Sched<[WriteLoad]>, VEX, VEX_L;
8318 defm VPBROADCASTB : avx2_broadcast<0x78, "vpbroadcastb", i8mem, loadi8,
8319 int_x86_avx2_pbroadcastb_128,
8320 int_x86_avx2_pbroadcastb_256>;
8321 defm VPBROADCASTW : avx2_broadcast<0x79, "vpbroadcastw", i16mem, loadi16,
8322 int_x86_avx2_pbroadcastw_128,
8323 int_x86_avx2_pbroadcastw_256>;
8324 defm VPBROADCASTD : avx2_broadcast<0x58, "vpbroadcastd", i32mem, loadi32,
8325 int_x86_avx2_pbroadcastd_128,
8326 int_x86_avx2_pbroadcastd_256>;
8327 defm VPBROADCASTQ : avx2_broadcast<0x59, "vpbroadcastq", i64mem, loadi64,
8328 int_x86_avx2_pbroadcastq_128,
8329 int_x86_avx2_pbroadcastq_256>;
8331 let Predicates = [HasAVX2] in {
8332 def : Pat<(v16i8 (X86VBroadcast (loadi8 addr:$src))),
8333 (VPBROADCASTBrm addr:$src)>;
8334 def : Pat<(v32i8 (X86VBroadcast (loadi8 addr:$src))),
8335 (VPBROADCASTBYrm addr:$src)>;
8336 def : Pat<(v8i16 (X86VBroadcast (loadi16 addr:$src))),
8337 (VPBROADCASTWrm addr:$src)>;
8338 def : Pat<(v16i16 (X86VBroadcast (loadi16 addr:$src))),
8339 (VPBROADCASTWYrm addr:$src)>;
8340 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8341 (VPBROADCASTDrm addr:$src)>;
8342 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8343 (VPBROADCASTDYrm addr:$src)>;
8344 def : Pat<(v2i64 (X86VBroadcast (loadi64 addr:$src))),
8345 (VPBROADCASTQrm addr:$src)>;
8346 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8347 (VPBROADCASTQYrm addr:$src)>;
8349 def : Pat<(v16i8 (X86VBroadcast (v16i8 VR128:$src))),
8350 (VPBROADCASTBrr VR128:$src)>;
8351 def : Pat<(v32i8 (X86VBroadcast (v16i8 VR128:$src))),
8352 (VPBROADCASTBYrr VR128:$src)>;
8353 def : Pat<(v8i16 (X86VBroadcast (v8i16 VR128:$src))),
8354 (VPBROADCASTWrr VR128:$src)>;
8355 def : Pat<(v16i16 (X86VBroadcast (v8i16 VR128:$src))),
8356 (VPBROADCASTWYrr VR128:$src)>;
8357 def : Pat<(v4i32 (X86VBroadcast (v4i32 VR128:$src))),
8358 (VPBROADCASTDrr VR128:$src)>;
8359 def : Pat<(v8i32 (X86VBroadcast (v4i32 VR128:$src))),
8360 (VPBROADCASTDYrr VR128:$src)>;
8361 def : Pat<(v2i64 (X86VBroadcast (v2i64 VR128:$src))),
8362 (VPBROADCASTQrr VR128:$src)>;
8363 def : Pat<(v4i64 (X86VBroadcast (v2i64 VR128:$src))),
8364 (VPBROADCASTQYrr VR128:$src)>;
8365 def : Pat<(v4f32 (X86VBroadcast (v4f32 VR128:$src))),
8366 (VBROADCASTSSrr VR128:$src)>;
8367 def : Pat<(v8f32 (X86VBroadcast (v4f32 VR128:$src))),
8368 (VBROADCASTSSYrr VR128:$src)>;
8369 def : Pat<(v2f64 (X86VBroadcast (v2f64 VR128:$src))),
8370 (VPBROADCASTQrr VR128:$src)>;
8371 def : Pat<(v4f64 (X86VBroadcast (v2f64 VR128:$src))),
8372 (VBROADCASTSDYrr VR128:$src)>;
8374 // Provide aliases for broadcast from the same register class that
8375 // automatically does the extract.
8376 def : Pat<(v32i8 (X86VBroadcast (v32i8 VR256:$src))),
8377 (VPBROADCASTBYrr (v16i8 (EXTRACT_SUBREG (v32i8 VR256:$src),
8379 def : Pat<(v16i16 (X86VBroadcast (v16i16 VR256:$src))),
8380 (VPBROADCASTWYrr (v8i16 (EXTRACT_SUBREG (v16i16 VR256:$src),
8382 def : Pat<(v8i32 (X86VBroadcast (v8i32 VR256:$src))),
8383 (VPBROADCASTDYrr (v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src),
8385 def : Pat<(v4i64 (X86VBroadcast (v4i64 VR256:$src))),
8386 (VPBROADCASTQYrr (v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src),
8388 def : Pat<(v8f32 (X86VBroadcast (v8f32 VR256:$src))),
8389 (VBROADCASTSSYrr (v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src),
8391 def : Pat<(v4f64 (X86VBroadcast (v4f64 VR256:$src))),
8392 (VBROADCASTSDYrr (v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src),
8395 // Provide fallback in case the load node that is used in the patterns above
8396 // is used by additional users, which prevents the pattern selection.
8397 let AddedComplexity = 20 in {
8398 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8399 (VBROADCASTSSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8400 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8401 (VBROADCASTSSYrr (COPY_TO_REGCLASS FR32:$src, VR128))>;
8402 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8403 (VBROADCASTSDYrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8405 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8406 (VBROADCASTSSrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8407 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8408 (VBROADCASTSSYrr (COPY_TO_REGCLASS GR32:$src, VR128))>;
8409 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8410 (VBROADCASTSDYrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8412 def : Pat<(v16i8 (X86VBroadcast GR8:$src)),
8413 (VPBROADCASTBrr (COPY_TO_REGCLASS
8414 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8416 def : Pat<(v32i8 (X86VBroadcast GR8:$src)),
8417 (VPBROADCASTBYrr (COPY_TO_REGCLASS
8418 (i32 (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
8421 def : Pat<(v8i16 (X86VBroadcast GR16:$src)),
8422 (VPBROADCASTWrr (COPY_TO_REGCLASS
8423 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8425 def : Pat<(v16i16 (X86VBroadcast GR16:$src)),
8426 (VPBROADCASTWYrr (COPY_TO_REGCLASS
8427 (i32 (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit)),
8430 // The patterns for VPBROADCASTD are not needed because they would match
8431 // the exact same thing as VBROADCASTSS patterns.
8433 def : Pat<(v2i64 (X86VBroadcast GR64:$src)),
8434 (VPBROADCASTQrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8435 // The v4i64 pattern is not needed because VBROADCASTSDYrr already match.
8439 // AVX1 broadcast patterns
8440 let Predicates = [HasAVX1Only] in {
8441 def : Pat<(v8i32 (X86VBroadcast (loadi32 addr:$src))),
8442 (VBROADCASTSSYrm addr:$src)>;
8443 def : Pat<(v4i64 (X86VBroadcast (loadi64 addr:$src))),
8444 (VBROADCASTSDYrm addr:$src)>;
8445 def : Pat<(v4i32 (X86VBroadcast (loadi32 addr:$src))),
8446 (VBROADCASTSSrm addr:$src)>;
8449 let Predicates = [HasAVX] in {
8450 // Provide fallback in case the load node that is used in the patterns above
8451 // is used by additional users, which prevents the pattern selection.
8452 let AddedComplexity = 20 in {
8453 // 128bit broadcasts:
8454 def : Pat<(v4f32 (X86VBroadcast FR32:$src)),
8455 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0)>;
8456 def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
8457 (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
8458 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), sub_xmm),
8459 (VPSHUFDri (COPY_TO_REGCLASS FR32:$src, VR128), 0), 1)>;
8460 def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
8461 (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
8462 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), sub_xmm),
8463 (VPSHUFDri (COPY_TO_REGCLASS FR64:$src, VR128), 0x44), 1)>;
8465 def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
8466 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0)>;
8467 def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
8468 (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
8469 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), sub_xmm),
8470 (VPSHUFDri (COPY_TO_REGCLASS GR32:$src, VR128), 0), 1)>;
8471 def : Pat<(v4i64 (X86VBroadcast GR64:$src)),
8472 (VINSERTF128rr (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)),
8473 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), sub_xmm),
8474 (VPSHUFDri (COPY_TO_REGCLASS GR64:$src, VR128), 0x44), 1)>;
8477 def : Pat<(v2f64 (X86VBroadcast f64:$src)),
8478 (VMOVDDUPrr (COPY_TO_REGCLASS FR64:$src, VR128))>;
8479 def : Pat<(v2i64 (X86VBroadcast i64:$src)),
8480 (VMOVDDUPrr (COPY_TO_REGCLASS GR64:$src, VR128))>;
8483 //===----------------------------------------------------------------------===//
8484 // VPERM - Permute instructions
8487 multiclass avx2_perm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8488 ValueType OpVT, X86FoldableSchedWrite Sched> {
8489 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8490 (ins VR256:$src1, VR256:$src2),
8491 !strconcat(OpcodeStr,
8492 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8494 (OpVT (X86VPermv VR256:$src1, VR256:$src2)))]>,
8495 Sched<[Sched]>, VEX_4V, VEX_L;
8496 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8497 (ins VR256:$src1, i256mem:$src2),
8498 !strconcat(OpcodeStr,
8499 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8501 (OpVT (X86VPermv VR256:$src1,
8502 (bitconvert (mem_frag addr:$src2)))))]>,
8503 Sched<[Sched.Folded, ReadAfterLd]>, VEX_4V, VEX_L;
8506 defm VPERMD : avx2_perm<0x36, "vpermd", loadv4i64, v8i32, WriteShuffle256>;
8507 let ExeDomain = SSEPackedSingle in
8508 defm VPERMPS : avx2_perm<0x16, "vpermps", loadv8f32, v8f32, WriteFShuffle256>;
8510 multiclass avx2_perm_imm<bits<8> opc, string OpcodeStr, PatFrag mem_frag,
8511 ValueType OpVT, X86FoldableSchedWrite Sched> {
8512 def Yri : AVX2AIi8<opc, MRMSrcReg, (outs VR256:$dst),
8513 (ins VR256:$src1, u8imm:$src2),
8514 !strconcat(OpcodeStr,
8515 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8517 (OpVT (X86VPermi VR256:$src1, (i8 imm:$src2))))]>,
8518 Sched<[Sched]>, VEX, VEX_L;
8519 def Ymi : AVX2AIi8<opc, MRMSrcMem, (outs VR256:$dst),
8520 (ins i256mem:$src1, u8imm:$src2),
8521 !strconcat(OpcodeStr,
8522 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8524 (OpVT (X86VPermi (mem_frag addr:$src1),
8525 (i8 imm:$src2))))]>,
8526 Sched<[Sched.Folded, ReadAfterLd]>, VEX, VEX_L;
8529 defm VPERMQ : avx2_perm_imm<0x00, "vpermq", loadv4i64, v4i64,
8530 WriteShuffle256>, VEX_W;
8531 let ExeDomain = SSEPackedDouble in
8532 defm VPERMPD : avx2_perm_imm<0x01, "vpermpd", loadv4f64, v4f64,
8533 WriteFShuffle256>, VEX_W;
8535 //===----------------------------------------------------------------------===//
8536 // VPERM2I128 - Permute Floating-Point Values in 128-bit chunks
8538 def VPERM2I128rr : AVX2AIi8<0x46, MRMSrcReg, (outs VR256:$dst),
8539 (ins VR256:$src1, VR256:$src2, u8imm:$src3),
8540 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8541 [(set VR256:$dst, (v4i64 (X86VPerm2x128 VR256:$src1, VR256:$src2,
8542 (i8 imm:$src3))))]>, Sched<[WriteShuffle256]>,
8544 def VPERM2I128rm : AVX2AIi8<0x46, MRMSrcMem, (outs VR256:$dst),
8545 (ins VR256:$src1, f256mem:$src2, u8imm:$src3),
8546 "vperm2i128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8547 [(set VR256:$dst, (X86VPerm2x128 VR256:$src1, (loadv4i64 addr:$src2),
8549 Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8551 let Predicates = [HasAVX2] in {
8552 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8553 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8554 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8555 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8556 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1, VR256:$src2, (i8 imm:$imm))),
8557 (VPERM2I128rr VR256:$src1, VR256:$src2, imm:$imm)>;
8559 def : Pat<(v32i8 (X86VPerm2x128 VR256:$src1, (bc_v32i8 (loadv4i64 addr:$src2)),
8561 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8562 def : Pat<(v16i16 (X86VPerm2x128 VR256:$src1,
8563 (bc_v16i16 (loadv4i64 addr:$src2)), (i8 imm:$imm))),
8564 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8565 def : Pat<(v8i32 (X86VPerm2x128 VR256:$src1, (bc_v8i32 (loadv4i64 addr:$src2)),
8567 (VPERM2I128rm VR256:$src1, addr:$src2, imm:$imm)>;
8571 //===----------------------------------------------------------------------===//
8572 // VINSERTI128 - Insert packed integer values
8574 let hasSideEffects = 0 in {
8575 def VINSERTI128rr : AVX2AIi8<0x38, MRMSrcReg, (outs VR256:$dst),
8576 (ins VR256:$src1, VR128:$src2, u8imm:$src3),
8577 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8578 []>, Sched<[WriteShuffle256]>, VEX_4V, VEX_L;
8580 def VINSERTI128rm : AVX2AIi8<0x38, MRMSrcMem, (outs VR256:$dst),
8581 (ins VR256:$src1, i128mem:$src2, u8imm:$src3),
8582 "vinserti128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
8583 []>, Sched<[WriteShuffle256Ld, ReadAfterLd]>, VEX_4V, VEX_L;
8586 let Predicates = [HasAVX2] in {
8587 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (v2i64 VR128:$src2),
8589 (VINSERTI128rr VR256:$src1, VR128:$src2,
8590 (INSERT_get_vinsert128_imm VR256:$ins))>;
8591 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1), (v4i32 VR128:$src2),
8593 (VINSERTI128rr VR256:$src1, VR128:$src2,
8594 (INSERT_get_vinsert128_imm VR256:$ins))>;
8595 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1), (v16i8 VR128:$src2),
8597 (VINSERTI128rr VR256:$src1, VR128:$src2,
8598 (INSERT_get_vinsert128_imm VR256:$ins))>;
8599 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
8601 (VINSERTI128rr VR256:$src1, VR128:$src2,
8602 (INSERT_get_vinsert128_imm VR256:$ins))>;
8604 def : Pat<(vinsert128_insert:$ins (v4i64 VR256:$src1), (loadv2i64 addr:$src2),
8606 (VINSERTI128rm VR256:$src1, addr:$src2,
8607 (INSERT_get_vinsert128_imm VR256:$ins))>;
8608 def : Pat<(vinsert128_insert:$ins (v8i32 VR256:$src1),
8609 (bc_v4i32 (loadv2i64 addr:$src2)),
8611 (VINSERTI128rm VR256:$src1, addr:$src2,
8612 (INSERT_get_vinsert128_imm VR256:$ins))>;
8613 def : Pat<(vinsert128_insert:$ins (v32i8 VR256:$src1),
8614 (bc_v16i8 (loadv2i64 addr:$src2)),
8616 (VINSERTI128rm VR256:$src1, addr:$src2,
8617 (INSERT_get_vinsert128_imm VR256:$ins))>;
8618 def : Pat<(vinsert128_insert:$ins (v16i16 VR256:$src1),
8619 (bc_v8i16 (loadv2i64 addr:$src2)),
8621 (VINSERTI128rm VR256:$src1, addr:$src2,
8622 (INSERT_get_vinsert128_imm VR256:$ins))>;
8625 //===----------------------------------------------------------------------===//
8626 // VEXTRACTI128 - Extract packed integer values
8628 def VEXTRACTI128rr : AVX2AIi8<0x39, MRMDestReg, (outs VR128:$dst),
8629 (ins VR256:$src1, u8imm:$src2),
8630 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8631 Sched<[WriteShuffle256]>, VEX, VEX_L;
8632 let hasSideEffects = 0, mayStore = 1 in
8633 def VEXTRACTI128mr : AVX2AIi8<0x39, MRMDestMem, (outs),
8634 (ins i128mem:$dst, VR256:$src1, u8imm:$src2),
8635 "vextracti128\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
8636 Sched<[WriteStore]>, VEX, VEX_L;
8638 let Predicates = [HasAVX2] in {
8639 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8640 (v2i64 (VEXTRACTI128rr
8641 (v4i64 VR256:$src1),
8642 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8643 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8644 (v4i32 (VEXTRACTI128rr
8645 (v8i32 VR256:$src1),
8646 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8647 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8648 (v8i16 (VEXTRACTI128rr
8649 (v16i16 VR256:$src1),
8650 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8651 def : Pat<(vextract128_extract:$ext VR256:$src1, (iPTR imm)),
8652 (v16i8 (VEXTRACTI128rr
8653 (v32i8 VR256:$src1),
8654 (EXTRACT_get_vextract128_imm VR128:$ext)))>;
8656 def : Pat<(store (v2i64 (vextract128_extract:$ext (v4i64 VR256:$src1),
8657 (iPTR imm))), addr:$dst),
8658 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8659 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8660 def : Pat<(store (v4i32 (vextract128_extract:$ext (v8i32 VR256:$src1),
8661 (iPTR imm))), addr:$dst),
8662 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8663 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8664 def : Pat<(store (v8i16 (vextract128_extract:$ext (v16i16 VR256:$src1),
8665 (iPTR imm))), addr:$dst),
8666 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8667 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8668 def : Pat<(store (v16i8 (vextract128_extract:$ext (v32i8 VR256:$src1),
8669 (iPTR imm))), addr:$dst),
8670 (VEXTRACTI128mr addr:$dst, VR256:$src1,
8671 (EXTRACT_get_vextract128_imm VR128:$ext))>;
8674 //===----------------------------------------------------------------------===//
8675 // VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
8677 multiclass avx2_pmovmask<string OpcodeStr,
8678 Intrinsic IntLd128, Intrinsic IntLd256,
8679 Intrinsic IntSt128, Intrinsic IntSt256> {
8680 def rm : AVX28I<0x8c, MRMSrcMem, (outs VR128:$dst),
8681 (ins VR128:$src1, i128mem:$src2),
8682 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8683 [(set VR128:$dst, (IntLd128 addr:$src2, VR128:$src1))]>, VEX_4V;
8684 def Yrm : AVX28I<0x8c, MRMSrcMem, (outs VR256:$dst),
8685 (ins VR256:$src1, i256mem:$src2),
8686 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8687 [(set VR256:$dst, (IntLd256 addr:$src2, VR256:$src1))]>,
8689 def mr : AVX28I<0x8e, MRMDestMem, (outs),
8690 (ins i128mem:$dst, VR128:$src1, VR128:$src2),
8691 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8692 [(IntSt128 addr:$dst, VR128:$src1, VR128:$src2)]>, VEX_4V;
8693 def Ymr : AVX28I<0x8e, MRMDestMem, (outs),
8694 (ins i256mem:$dst, VR256:$src1, VR256:$src2),
8695 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8696 [(IntSt256 addr:$dst, VR256:$src1, VR256:$src2)]>, VEX_4V, VEX_L;
8699 defm VPMASKMOVD : avx2_pmovmask<"vpmaskmovd",
8700 int_x86_avx2_maskload_d,
8701 int_x86_avx2_maskload_d_256,
8702 int_x86_avx2_maskstore_d,
8703 int_x86_avx2_maskstore_d_256>;
8704 defm VPMASKMOVQ : avx2_pmovmask<"vpmaskmovq",
8705 int_x86_avx2_maskload_q,
8706 int_x86_avx2_maskload_q_256,
8707 int_x86_avx2_maskstore_q,
8708 int_x86_avx2_maskstore_q_256>, VEX_W;
8710 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src)),
8711 (VMASKMOVPSYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8713 def: Pat<(masked_store addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src)),
8714 (VPMASKMOVDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8716 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src)),
8717 (VMASKMOVPSmr addr:$ptr, VR128:$mask, VR128:$src)>;
8719 def: Pat<(masked_store addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src)),
8720 (VPMASKMOVDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8722 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8723 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8725 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask),
8726 (bc_v8f32 (v8i32 immAllZerosV)))),
8727 (VMASKMOVPSYrm VR256:$mask, addr:$ptr)>;
8729 def: Pat<(v8f32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8f32 VR256:$src0))),
8730 (VBLENDVPSYrr VR256:$src0, (VMASKMOVPSYrm VR256:$mask, addr:$ptr),
8733 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), undef)),
8734 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8736 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 immAllZerosV))),
8737 (VPMASKMOVDYrm VR256:$mask, addr:$ptr)>;
8739 def: Pat<(v8i32 (masked_load addr:$ptr, (v8i32 VR256:$mask), (v8i32 VR256:$src0))),
8740 (VBLENDVPSYrr VR256:$src0, (VPMASKMOVDYrm VR256:$mask, addr:$ptr),
8743 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8744 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8746 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask),
8747 (bc_v4f32 (v4i32 immAllZerosV)))),
8748 (VMASKMOVPSrm VR128:$mask, addr:$ptr)>;
8750 def: Pat<(v4f32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4f32 VR128:$src0))),
8751 (VBLENDVPSrr VR128:$src0, (VMASKMOVPSrm VR128:$mask, addr:$ptr),
8754 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), undef)),
8755 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8757 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 immAllZerosV))),
8758 (VPMASKMOVDrm VR128:$mask, addr:$ptr)>;
8760 def: Pat<(v4i32 (masked_load addr:$ptr, (v4i32 VR128:$mask), (v4i32 VR128:$src0))),
8761 (VBLENDVPSrr VR128:$src0, (VPMASKMOVDrm VR128:$mask, addr:$ptr),
8764 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src)),
8765 (VMASKMOVPDYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8767 def: Pat<(masked_store addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src)),
8768 (VPMASKMOVQYmr addr:$ptr, VR256:$mask, VR256:$src)>;
8770 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8771 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8773 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8774 (v4f64 immAllZerosV))),
8775 (VMASKMOVPDYrm VR256:$mask, addr:$ptr)>;
8777 def: Pat<(v4f64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4f64 VR256:$src0))),
8778 (VBLENDVPDYrr VR256:$src0, (VMASKMOVPDYrm VR256:$mask, addr:$ptr),
8781 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), undef)),
8782 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8784 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask),
8785 (bc_v4i64 (v8i32 immAllZerosV)))),
8786 (VPMASKMOVQYrm VR256:$mask, addr:$ptr)>;
8788 def: Pat<(v4i64 (masked_load addr:$ptr, (v4i64 VR256:$mask), (v4i64 VR256:$src0))),
8789 (VBLENDVPDYrr VR256:$src0, (VPMASKMOVQYrm VR256:$mask, addr:$ptr),
8792 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src)),
8793 (VMASKMOVPDmr addr:$ptr, VR128:$mask, VR128:$src)>;
8795 def: Pat<(masked_store addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src)),
8796 (VPMASKMOVQmr addr:$ptr, VR128:$mask, VR128:$src)>;
8798 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8799 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8801 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8802 (v2f64 immAllZerosV))),
8803 (VMASKMOVPDrm VR128:$mask, addr:$ptr)>;
8805 def: Pat<(v2f64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2f64 VR128:$src0))),
8806 (VBLENDVPDrr VR128:$src0, (VMASKMOVPDrm VR128:$mask, addr:$ptr),
8809 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), undef)),
8810 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8812 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask),
8813 (bc_v2i64 (v4i32 immAllZerosV)))),
8814 (VPMASKMOVQrm VR128:$mask, addr:$ptr)>;
8816 def: Pat<(v2i64 (masked_load addr:$ptr, (v2i64 VR128:$mask), (v2i64 VR128:$src0))),
8817 (VBLENDVPDrr VR128:$src0, (VPMASKMOVQrm VR128:$mask, addr:$ptr),
8820 //===----------------------------------------------------------------------===//
8821 // Variable Bit Shifts
8823 multiclass avx2_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
8824 ValueType vt128, ValueType vt256> {
8825 def rr : AVX28I<opc, MRMSrcReg, (outs VR128:$dst),
8826 (ins VR128:$src1, VR128:$src2),
8827 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8829 (vt128 (OpNode VR128:$src1, (vt128 VR128:$src2))))]>,
8830 VEX_4V, Sched<[WriteVarVecShift]>;
8831 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst),
8832 (ins VR128:$src1, i128mem:$src2),
8833 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8835 (vt128 (OpNode VR128:$src1,
8836 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
8837 VEX_4V, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8838 def Yrr : AVX28I<opc, MRMSrcReg, (outs VR256:$dst),
8839 (ins VR256:$src1, VR256:$src2),
8840 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8842 (vt256 (OpNode VR256:$src1, (vt256 VR256:$src2))))]>,
8843 VEX_4V, VEX_L, Sched<[WriteVarVecShift]>;
8844 def Yrm : AVX28I<opc, MRMSrcMem, (outs VR256:$dst),
8845 (ins VR256:$src1, i256mem:$src2),
8846 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
8848 (vt256 (OpNode VR256:$src1,
8849 (vt256 (bitconvert (loadv4i64 addr:$src2))))))]>,
8850 VEX_4V, VEX_L, Sched<[WriteVarVecShiftLd, ReadAfterLd]>;
8853 defm VPSLLVD : avx2_var_shift<0x47, "vpsllvd", shl, v4i32, v8i32>;
8854 defm VPSLLVQ : avx2_var_shift<0x47, "vpsllvq", shl, v2i64, v4i64>, VEX_W;
8855 defm VPSRLVD : avx2_var_shift<0x45, "vpsrlvd", srl, v4i32, v8i32>;
8856 defm VPSRLVQ : avx2_var_shift<0x45, "vpsrlvq", srl, v2i64, v4i64>, VEX_W;
8857 defm VPSRAVD : avx2_var_shift<0x46, "vpsravd", sra, v4i32, v8i32>;
8859 //===----------------------------------------------------------------------===//
8860 // VGATHER - GATHER Operations
8861 multiclass avx2_gather<bits<8> opc, string OpcodeStr, RegisterClass RC256,
8862 X86MemOperand memop128, X86MemOperand memop256> {
8863 def rm : AVX28I<opc, MRMSrcMem, (outs VR128:$dst, VR128:$mask_wb),
8864 (ins VR128:$src1, memop128:$src2, VR128:$mask),
8865 !strconcat(OpcodeStr,
8866 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8868 def Yrm : AVX28I<opc, MRMSrcMem, (outs RC256:$dst, RC256:$mask_wb),
8869 (ins RC256:$src1, memop256:$src2, RC256:$mask),
8870 !strconcat(OpcodeStr,
8871 "\t{$mask, $src2, $dst|$dst, $src2, $mask}"),
8872 []>, VEX_4VOp3, VEX_L;
8875 let mayLoad = 1, Constraints
8876 = "@earlyclobber $dst,@earlyclobber $mask_wb, $src1 = $dst, $mask = $mask_wb"
8878 defm VPGATHERDQ : avx2_gather<0x90, "vpgatherdq", VR256, vx64mem, vx64mem>, VEX_W;
8879 defm VPGATHERQQ : avx2_gather<0x91, "vpgatherqq", VR256, vx64mem, vy64mem>, VEX_W;
8880 defm VPGATHERDD : avx2_gather<0x90, "vpgatherdd", VR256, vx32mem, vy32mem>;
8881 defm VPGATHERQD : avx2_gather<0x91, "vpgatherqd", VR128, vx32mem, vy32mem>;
8883 let ExeDomain = SSEPackedDouble in {
8884 defm VGATHERDPD : avx2_gather<0x92, "vgatherdpd", VR256, vx64mem, vx64mem>, VEX_W;
8885 defm VGATHERQPD : avx2_gather<0x93, "vgatherqpd", VR256, vx64mem, vy64mem>, VEX_W;
8888 let ExeDomain = SSEPackedSingle in {
8889 defm VGATHERDPS : avx2_gather<0x92, "vgatherdps", VR256, vx32mem, vy32mem>;
8890 defm VGATHERQPS : avx2_gather<0x93, "vgatherqps", VR128, vx32mem, vy32mem>;