1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE scalar FP Instructions
19 //===----------------------------------------------------------------------===//
21 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
22 // instruction selection into a branch sequence.
23 let Uses = [EFLAGS], usesCustomInserter = 1 in {
24 def CMOV_FR32 : I<0, Pseudo,
25 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
27 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
29 def CMOV_FR64 : I<0, Pseudo,
30 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
32 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
34 def CMOV_V4F32 : I<0, Pseudo,
35 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
36 "#CMOV_V4F32 PSEUDO!",
38 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
40 def CMOV_V2F64 : I<0, Pseudo,
41 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
42 "#CMOV_V2F64 PSEUDO!",
44 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
46 def CMOV_V2I64 : I<0, Pseudo,
47 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
48 "#CMOV_V2I64 PSEUDO!",
50 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
54 //===----------------------------------------------------------------------===//
55 // SSE 1 & 2 Instructions Classes
56 //===----------------------------------------------------------------------===//
58 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
59 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
60 RegisterClass RC, X86MemOperand x86memop,
62 let isCommutable = 1 in {
63 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
65 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
66 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
67 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
69 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
71 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
72 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
73 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
76 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
77 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
78 string asm, string SSEVer, string FPSizeStr,
79 Operand memopr, ComplexPattern mem_cpat,
81 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
83 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
84 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
85 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
86 !strconcat(SSEVer, !strconcat("_",
87 !strconcat(OpcodeStr, FPSizeStr))))
88 RC:$src1, RC:$src2))]>;
89 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memopr:$src2),
91 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
92 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
93 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
94 !strconcat(SSEVer, !strconcat("_",
95 !strconcat(OpcodeStr, FPSizeStr))))
96 RC:$src1, mem_cpat:$src2))]>;
99 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
100 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
101 RegisterClass RC, ValueType vt,
102 X86MemOperand x86memop, PatFrag mem_frag,
103 Domain d, bit Is2Addr = 1> {
104 let isCommutable = 1 in
105 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
107 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
108 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
109 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], d>;
111 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
113 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
114 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
115 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))], d>;
118 /// sse12_fp_packed_logical_rm - SSE 1 & 2 packed instructions class
119 multiclass sse12_fp_packed_logical_rm<bits<8> opc, RegisterClass RC, Domain d,
120 string OpcodeStr, X86MemOperand x86memop,
121 list<dag> pat_rr, list<dag> pat_rm,
123 let isCommutable = 1 in
124 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
126 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
127 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
129 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
131 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
132 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
136 /// sse12_fp_packed_int - SSE 1 & 2 packed instructions intrinsics class
137 multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
138 string asm, string SSEVer, string FPSizeStr,
139 X86MemOperand x86memop, PatFrag mem_frag,
140 Domain d, bit Is2Addr = 1> {
141 def rr_Int : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
143 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
144 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
145 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
146 !strconcat(SSEVer, !strconcat("_",
147 !strconcat(OpcodeStr, FPSizeStr))))
148 RC:$src1, RC:$src2))], d>;
149 def rm_Int : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1,x86memop:$src2),
151 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
152 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
153 [(set RC:$dst, (!nameconcat<Intrinsic>("int_x86_sse",
154 !strconcat(SSEVer, !strconcat("_",
155 !strconcat(OpcodeStr, FPSizeStr))))
156 RC:$src1, (mem_frag addr:$src2)))], d>;
159 //===----------------------------------------------------------------------===//
160 // SSE 1 & 2 - Move Instructions
161 //===----------------------------------------------------------------------===//
163 class sse12_move_rr<RegisterClass RC, ValueType vt, string asm> :
164 SI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, RC:$src2), asm,
165 [(set (vt VR128:$dst), (movl VR128:$src1, (scalar_to_vector RC:$src2)))]>;
167 // Loading from memory automatically zeroing upper bits.
168 class sse12_move_rm<RegisterClass RC, X86MemOperand x86memop,
169 PatFrag mem_pat, string OpcodeStr> :
170 SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
171 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
172 [(set RC:$dst, (mem_pat addr:$src))]>;
174 // Move Instructions. Register-to-register movss/movsd is not used for FR32/64
175 // register copies because it's a partial register update; FsMOVAPSrr/FsMOVAPDrr
176 // is used instead. Register-to-register movss/movsd is not modeled as an
177 // INSERT_SUBREG because INSERT_SUBREG requires that the insert be implementable
178 // in terms of a copy, and just mentioned, we don't use movss/movsd for copies.
179 let isAsmParserOnly = 1 in {
180 def VMOVSSrr : sse12_move_rr<FR32, v4f32,
181 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V;
182 def VMOVSDrr : sse12_move_rr<FR64, v2f64,
183 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V;
185 let canFoldAsLoad = 1, isReMaterializable = 1 in {
186 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX;
188 let AddedComplexity = 20 in
189 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX;
193 let Constraints = "$src1 = $dst" in {
194 def MOVSSrr : sse12_move_rr<FR32, v4f32,
195 "movss\t{$src2, $dst|$dst, $src2}">, XS;
196 def MOVSDrr : sse12_move_rr<FR64, v2f64,
197 "movsd\t{$src2, $dst|$dst, $src2}">, XD;
200 let canFoldAsLoad = 1, isReMaterializable = 1 in {
201 def MOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS;
203 let AddedComplexity = 20 in
204 def MOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD;
207 let AddedComplexity = 15 in {
208 // Extract the low 32-bit value from one vector and insert it into another.
209 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
210 (MOVSSrr (v4f32 VR128:$src1),
211 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
212 // Extract the low 64-bit value from one vector and insert it into another.
213 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
214 (MOVSDrr (v2f64 VR128:$src1),
215 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
218 // Implicitly promote a 32-bit scalar to a vector.
219 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
220 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
221 // Implicitly promote a 64-bit scalar to a vector.
222 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
223 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
225 let AddedComplexity = 20 in {
226 // MOVSSrm zeros the high parts of the register; represent this
227 // with SUBREG_TO_REG.
228 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
229 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
230 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
231 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
232 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
233 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
234 // MOVSDrm zeros the high parts of the register; represent this
235 // with SUBREG_TO_REG.
236 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
237 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
238 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
239 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
240 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
241 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
242 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
243 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
244 def : Pat<(v2f64 (X86vzload addr:$src)),
245 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
248 // Store scalar value to memory.
249 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
250 "movss\t{$src, $dst|$dst, $src}",
251 [(store FR32:$src, addr:$dst)]>;
252 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
253 "movsd\t{$src, $dst|$dst, $src}",
254 [(store FR64:$src, addr:$dst)]>;
256 let isAsmParserOnly = 1 in {
257 def VMOVSSmr : SI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
258 "movss\t{$src, $dst|$dst, $src}",
259 [(store FR32:$src, addr:$dst)]>, XS, VEX_4V;
260 def VMOVSDmr : SI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
261 "movsd\t{$src, $dst|$dst, $src}",
262 [(store FR64:$src, addr:$dst)]>, XD, VEX_4V;
265 // Extract and store.
266 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
269 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
270 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
273 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
275 // Move Aligned/Unaligned floating point values
276 multiclass sse12_mov_packed<bits<8> opc, RegisterClass RC,
277 X86MemOperand x86memop, PatFrag ld_frag,
278 string asm, Domain d,
279 bit IsReMaterializable = 1> {
280 let neverHasSideEffects = 1 in
281 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
282 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>;
283 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable in
284 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
285 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
286 [(set RC:$dst, (ld_frag addr:$src))], d>;
289 let isAsmParserOnly = 1 in {
290 defm VMOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
291 "movaps", SSEPackedSingle>, VEX;
292 defm VMOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
293 "movapd", SSEPackedDouble>, OpSize, VEX;
294 defm VMOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
295 "movups", SSEPackedSingle>, VEX;
296 defm VMOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
297 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
299 defm VMOVAPSY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv8f32,
300 "movaps", SSEPackedSingle>, VEX;
301 defm VMOVAPDY : sse12_mov_packed<0x28, VR256, f256mem, alignedloadv4f64,
302 "movapd", SSEPackedDouble>, OpSize, VEX;
303 defm VMOVUPSY : sse12_mov_packed<0x10, VR256, f256mem, loadv8f32,
304 "movups", SSEPackedSingle>, VEX;
305 defm VMOVUPDY : sse12_mov_packed<0x10, VR256, f256mem, loadv4f64,
306 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
308 defm MOVAPS : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv4f32,
309 "movaps", SSEPackedSingle>, TB;
310 defm MOVAPD : sse12_mov_packed<0x28, VR128, f128mem, alignedloadv2f64,
311 "movapd", SSEPackedDouble>, TB, OpSize;
312 defm MOVUPS : sse12_mov_packed<0x10, VR128, f128mem, loadv4f32,
313 "movups", SSEPackedSingle>, TB;
314 defm MOVUPD : sse12_mov_packed<0x10, VR128, f128mem, loadv2f64,
315 "movupd", SSEPackedDouble, 0>, TB, OpSize;
317 let isAsmParserOnly = 1 in {
318 def VMOVAPSmr : VPSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
319 "movaps\t{$src, $dst|$dst, $src}",
320 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>, VEX;
321 def VMOVAPDmr : VPDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
322 "movapd\t{$src, $dst|$dst, $src}",
323 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>, VEX;
324 def VMOVUPSmr : VPSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
325 "movups\t{$src, $dst|$dst, $src}",
326 [(store (v4f32 VR128:$src), addr:$dst)]>, VEX;
327 def VMOVUPDmr : VPDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
328 "movupd\t{$src, $dst|$dst, $src}",
329 [(store (v2f64 VR128:$src), addr:$dst)]>, VEX;
330 def VMOVAPSYmr : VPSI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
331 "movaps\t{$src, $dst|$dst, $src}",
332 [(alignedstore (v8f32 VR256:$src), addr:$dst)]>, VEX;
333 def VMOVAPDYmr : VPDI<0x29, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
334 "movapd\t{$src, $dst|$dst, $src}",
335 [(alignedstore (v4f64 VR256:$src), addr:$dst)]>, VEX;
336 def VMOVUPSYmr : VPSI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
337 "movups\t{$src, $dst|$dst, $src}",
338 [(store (v8f32 VR256:$src), addr:$dst)]>, VEX;
339 def VMOVUPDYmr : VPDI<0x11, MRMDestMem, (outs), (ins f256mem:$dst, VR256:$src),
340 "movupd\t{$src, $dst|$dst, $src}",
341 [(store (v4f64 VR256:$src), addr:$dst)]>, VEX;
343 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
344 "movaps\t{$src, $dst|$dst, $src}",
345 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
346 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
347 "movapd\t{$src, $dst|$dst, $src}",
348 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
349 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
350 "movups\t{$src, $dst|$dst, $src}",
351 [(store (v4f32 VR128:$src), addr:$dst)]>;
352 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
353 "movupd\t{$src, $dst|$dst, $src}",
354 [(store (v2f64 VR128:$src), addr:$dst)]>;
356 // Intrinsic forms of MOVUPS/D load and store
357 let isAsmParserOnly = 1 in {
358 let canFoldAsLoad = 1, isReMaterializable = 1 in
359 def VMOVUPSrm_Int : VPSI<0x10, MRMSrcMem, (outs VR128:$dst),
361 "movups\t{$src, $dst|$dst, $src}",
362 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>, VEX;
363 def VMOVUPDrm_Int : VPDI<0x10, MRMSrcMem, (outs VR128:$dst),
365 "movupd\t{$src, $dst|$dst, $src}",
366 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>, VEX;
367 def VMOVUPSmr_Int : VPSI<0x11, MRMDestMem, (outs),
368 (ins f128mem:$dst, VR128:$src),
369 "movups\t{$src, $dst|$dst, $src}",
370 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>, VEX;
371 def VMOVUPDmr_Int : VPDI<0x11, MRMDestMem, (outs),
372 (ins f128mem:$dst, VR128:$src),
373 "movupd\t{$src, $dst|$dst, $src}",
374 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>, VEX;
376 let canFoldAsLoad = 1, isReMaterializable = 1 in
377 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
378 "movups\t{$src, $dst|$dst, $src}",
379 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
380 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
381 "movupd\t{$src, $dst|$dst, $src}",
382 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
384 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
385 "movups\t{$src, $dst|$dst, $src}",
386 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
387 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
388 "movupd\t{$src, $dst|$dst, $src}",
389 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
391 // Move Low/High packed floating point values
392 multiclass sse12_mov_hilo_packed<bits<8>opc, RegisterClass RC,
393 PatFrag mov_frag, string base_opc,
395 def PSrm : PI<opc, MRMSrcMem,
396 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
397 !strconcat(!strconcat(base_opc,"s"), asm_opr),
400 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))],
401 SSEPackedSingle>, TB;
403 def PDrm : PI<opc, MRMSrcMem,
404 (outs RC:$dst), (ins RC:$src1, f64mem:$src2),
405 !strconcat(!strconcat(base_opc,"d"), asm_opr),
406 [(set RC:$dst, (v2f64 (mov_frag RC:$src1,
407 (scalar_to_vector (loadf64 addr:$src2)))))],
408 SSEPackedDouble>, TB, OpSize;
411 let isAsmParserOnly = 1, AddedComplexity = 20 in {
412 defm VMOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
413 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
414 defm VMOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
415 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
417 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
418 defm MOVL : sse12_mov_hilo_packed<0x12, VR128, movlp, "movlp",
419 "\t{$src2, $dst|$dst, $src2}">;
420 defm MOVH : sse12_mov_hilo_packed<0x16, VR128, movlhps, "movhp",
421 "\t{$src2, $dst|$dst, $src2}">;
424 let isAsmParserOnly = 1 in {
425 def VMOVLPSmr : VPSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
426 "movlps\t{$src, $dst|$dst, $src}",
427 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
428 (iPTR 0))), addr:$dst)]>, VEX;
429 def VMOVLPDmr : VPDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
430 "movlpd\t{$src, $dst|$dst, $src}",
431 [(store (f64 (vector_extract (v2f64 VR128:$src),
432 (iPTR 0))), addr:$dst)]>, VEX;
434 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
435 "movlps\t{$src, $dst|$dst, $src}",
436 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
437 (iPTR 0))), addr:$dst)]>;
438 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
439 "movlpd\t{$src, $dst|$dst, $src}",
440 [(store (f64 (vector_extract (v2f64 VR128:$src),
441 (iPTR 0))), addr:$dst)]>;
443 // v2f64 extract element 1 is always custom lowered to unpack high to low
444 // and extract element 0 so the non-store version isn't too horrible.
445 let isAsmParserOnly = 1 in {
446 def VMOVHPSmr : VPSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
447 "movhps\t{$src, $dst|$dst, $src}",
448 [(store (f64 (vector_extract
449 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
450 (undef)), (iPTR 0))), addr:$dst)]>,
452 def VMOVHPDmr : VPDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
453 "movhpd\t{$src, $dst|$dst, $src}",
454 [(store (f64 (vector_extract
455 (v2f64 (unpckh VR128:$src, (undef))),
456 (iPTR 0))), addr:$dst)]>,
459 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
460 "movhps\t{$src, $dst|$dst, $src}",
461 [(store (f64 (vector_extract
462 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
463 (undef)), (iPTR 0))), addr:$dst)]>;
464 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
465 "movhpd\t{$src, $dst|$dst, $src}",
466 [(store (f64 (vector_extract
467 (v2f64 (unpckh VR128:$src, (undef))),
468 (iPTR 0))), addr:$dst)]>;
470 let isAsmParserOnly = 1, AddedComplexity = 20 in {
471 def VMOVLHPSrr : VPSI<0x16, MRMSrcReg, (outs VR128:$dst),
472 (ins VR128:$src1, VR128:$src2),
473 "movlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
475 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>,
477 def VMOVHLPSrr : VPSI<0x12, MRMSrcReg, (outs VR128:$dst),
478 (ins VR128:$src1, VR128:$src2),
479 "movhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
481 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>,
484 let Constraints = "$src1 = $dst", AddedComplexity = 20 in {
485 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
486 (ins VR128:$src1, VR128:$src2),
487 "movlhps\t{$src2, $dst|$dst, $src2}",
489 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
490 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
491 (ins VR128:$src1, VR128:$src2),
492 "movhlps\t{$src2, $dst|$dst, $src2}",
494 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
497 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
498 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
499 let AddedComplexity = 20 in {
500 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
501 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
502 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
503 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
506 //===----------------------------------------------------------------------===//
507 // SSE 1 & 2 - Conversion Instructions
508 //===----------------------------------------------------------------------===//
510 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
511 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
513 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
514 [(set DstRC:$dst, (OpNode SrcRC:$src))]>;
515 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
516 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
519 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
520 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
521 string asm, Domain d> {
522 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
523 [(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
524 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
525 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
528 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
529 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
531 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
533 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
534 (ins DstRC:$src1, x86memop:$src), asm, []>;
537 let isAsmParserOnly = 1 in {
538 defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
539 "cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
540 defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
541 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
542 defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
543 "cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
545 defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
546 "cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
550 defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
551 "cvttss2si\t{$src, $dst|$dst, $src}">, XS;
552 defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
553 "cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
554 defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
555 "cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
556 defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
557 "cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
559 // Conversion Instructions Intrinsics - Match intrinsics which expect MM
560 // and/or XMM operand(s).
561 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
562 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
563 string asm, Domain d> {
564 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
565 [(set DstRC:$dst, (Int SrcRC:$src))], d>;
566 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
567 [(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
570 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
571 Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
573 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
574 [(set DstRC:$dst, (Int SrcRC:$src))]>;
575 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
576 [(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
579 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
580 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
581 PatFrag ld_frag, string asm, Domain d> {
582 def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
583 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))], d>;
584 def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst),
585 (ins DstRC:$src1, x86memop:$src2), asm,
586 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
589 multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
590 RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
591 PatFrag ld_frag, string asm> {
592 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
593 asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
594 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
595 (ins DstRC:$src1, x86memop:$src2), asm,
596 [(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
599 let isAsmParserOnly = 1 in {
600 defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
601 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
603 defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
604 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
607 defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
608 f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
609 defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
610 f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
613 let Constraints = "$src1 = $dst" in {
614 defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
615 int_x86_sse_cvtsi2ss, i32mem, loadi32,
616 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
617 defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
618 int_x86_sse2_cvtsi2sd, i32mem, loadi32,
619 "cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
622 // Instructions below don't have an AVX form.
623 defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
624 f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
625 SSEPackedSingle>, TB;
626 defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
627 f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
628 SSEPackedDouble>, TB, OpSize;
629 defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
630 f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
631 SSEPackedSingle>, TB;
632 defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
633 f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
634 SSEPackedDouble>, TB, OpSize;
635 defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
636 i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
637 SSEPackedDouble>, TB, OpSize;
638 let Constraints = "$src1 = $dst" in {
639 defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
640 int_x86_sse_cvtpi2ps,
641 i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
642 SSEPackedSingle>, TB;
647 // Aliases for intrinsics
648 let isAsmParserOnly = 1, Pattern = []<dag> in {
649 defm Int_VCVTTSS2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
650 int_x86_sse_cvttss2si, f32mem, load,
651 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS;
652 defm Int_VCVTTSD2SI : sse12_cvt_sint_3addr<0x2C, VR128, GR32,
653 int_x86_sse2_cvttsd2si, f128mem, load,
654 "cvttss2si\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD;
656 defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
657 f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
659 defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
660 f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
663 let isAsmParserOnly = 1, Pattern = []<dag> in {
664 defm VCVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load,
665 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS, VEX;
666 defm VCVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load,
667 "cvtdq2ps\t{$src, $dst|$dst, $src}",
668 SSEPackedSingle>, TB, VEX;
670 let Pattern = []<dag> in {
671 defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
672 "cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
673 defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
674 "cvtdq2ps\t{$src, $dst|$dst, $src}",
675 SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
680 // Convert scalar double to scalar single
681 let isAsmParserOnly = 1 in {
682 def VCVTSD2SSrr : VSDI<0x5A, MRMSrcReg, (outs FR32:$dst),
683 (ins FR64:$src1, FR64:$src2),
684 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
686 def VCVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst),
687 (ins FR64:$src1, f64mem:$src2),
688 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
689 []>, XD, Requires<[HasAVX, OptForSize]>, VEX_4V;
691 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
692 "cvtsd2ss\t{$src, $dst|$dst, $src}",
693 [(set FR32:$dst, (fround FR64:$src))]>;
694 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
695 "cvtsd2ss\t{$src, $dst|$dst, $src}",
696 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
697 Requires<[HasSSE2, OptForSize]>;
699 let isAsmParserOnly = 1 in
700 defm Int_VCVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
701 int_x86_sse2_cvtsd2ss, f64mem, load,
702 "cvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}">,
704 let Constraints = "$src1 = $dst" in
705 defm Int_CVTSD2SS: sse12_cvt_sint_3addr<0x5A, VR128, VR128,
706 int_x86_sse2_cvtsd2ss, f64mem, load,
707 "cvtsd2ss\t{$src2, $dst|$dst, $src2}">, XS;
709 // Convert scalar single to scalar double
710 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
711 def VCVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst),
712 (ins FR32:$src1, FR32:$src2),
713 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
714 []>, XS, Requires<[HasAVX]>, VEX_4V;
715 def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst),
716 (ins FR32:$src1, f32mem:$src2),
717 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
718 []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>;
720 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
721 "cvtss2sd\t{$src, $dst|$dst, $src}",
722 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
724 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
725 "cvtss2sd\t{$src, $dst|$dst, $src}",
726 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
727 Requires<[HasSSE2, OptForSize]>;
729 let isAsmParserOnly = 1 in {
730 def Int_VCVTSS2SDrr: I<0x5A, MRMSrcReg,
731 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
732 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
733 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
734 VR128:$src2))]>, XS, VEX_4V,
736 def Int_VCVTSS2SDrm: I<0x5A, MRMSrcMem,
737 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
738 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
739 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
740 (load addr:$src2)))]>, XS, VEX_4V,
743 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
744 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
745 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
746 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
747 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
750 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
751 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
752 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
753 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
754 (load addr:$src2)))]>, XS,
758 def : Pat<(extloadf32 addr:$src),
759 (CVTSS2SDrr (MOVSSrm addr:$src))>,
760 Requires<[HasSSE2, OptForSpeed]>;
762 // Convert doubleword to packed single/double fp
763 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
764 def Int_VCVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
765 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
766 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
767 TB, VEX, Requires<[HasAVX]>;
768 def Int_VCVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
769 "vcvtdq2ps\t{$src, $dst|$dst, $src}",
770 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
771 (bitconvert (memopv2i64 addr:$src))))]>,
772 TB, VEX, Requires<[HasAVX]>;
774 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
775 "cvtdq2ps\t{$src, $dst|$dst, $src}",
776 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
777 TB, Requires<[HasSSE2]>;
778 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
779 "cvtdq2ps\t{$src, $dst|$dst, $src}",
780 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
781 (bitconvert (memopv2i64 addr:$src))))]>,
782 TB, Requires<[HasSSE2]>;
784 // FIXME: why the non-intrinsic version is described as SSE3?
785 let isAsmParserOnly = 1 in { // SSE2 instructions with XS prefix
786 def Int_VCVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
787 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
788 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
789 XS, VEX, Requires<[HasAVX]>;
790 def Int_VCVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
791 "vcvtdq2pd\t{$src, $dst|$dst, $src}",
792 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
793 (bitconvert (memopv2i64 addr:$src))))]>,
794 XS, VEX, Requires<[HasAVX]>;
796 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
797 "cvtdq2pd\t{$src, $dst|$dst, $src}",
798 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
799 XS, Requires<[HasSSE2]>;
800 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
801 "cvtdq2pd\t{$src, $dst|$dst, $src}",
802 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
803 (bitconvert (memopv2i64 addr:$src))))]>,
804 XS, Requires<[HasSSE2]>;
806 // Convert packed single/double fp to doubleword
807 let isAsmParserOnly = 1 in {
808 def VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
809 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
810 def VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
811 "cvtps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
813 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
814 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
815 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
816 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
818 let isAsmParserOnly = 1 in {
819 def Int_VCVTPS2DQrr : VPDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
820 "cvtps2dq\t{$src, $dst|$dst, $src}",
821 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>,
823 def Int_VCVTPS2DQrm : VPDI<0x5B, MRMSrcMem, (outs VR128:$dst),
825 "cvtps2dq\t{$src, $dst|$dst, $src}",
826 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
827 (memop addr:$src)))]>, VEX;
829 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
830 "cvtps2dq\t{$src, $dst|$dst, $src}",
831 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
832 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
833 "cvtps2dq\t{$src, $dst|$dst, $src}",
834 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
835 (memop addr:$src)))]>;
837 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XD prefix
838 def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
839 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
840 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
841 XD, VEX, Requires<[HasAVX]>;
842 def Int_VCVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
843 "vcvtpd2dq\t{$src, $dst|$dst, $src}",
844 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
845 (memop addr:$src)))]>,
846 XD, VEX, Requires<[HasAVX]>;
848 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
849 "cvtpd2dq\t{$src, $dst|$dst, $src}",
850 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
851 XD, Requires<[HasSSE2]>;
852 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
853 "cvtpd2dq\t{$src, $dst|$dst, $src}",
854 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
855 (memop addr:$src)))]>,
856 XD, Requires<[HasSSE2]>;
859 // Convert with truncation packed single/double fp to doubleword
860 let isAsmParserOnly = 1 in { // SSE2 packed instructions with XS prefix
861 def VCVTTPS2DQrr : VSSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
862 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
863 def VCVTTPS2DQrm : VSSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
864 "cvttps2dq\t{$src, $dst|$dst, $src}", []>, VEX;
866 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
867 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
868 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
869 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
872 let isAsmParserOnly = 1 in {
873 def Int_VCVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
874 "vcvttps2dq\t{$src, $dst|$dst, $src}",
876 (int_x86_sse2_cvttps2dq VR128:$src))]>,
877 XS, VEX, Requires<[HasAVX]>;
878 def Int_VCVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
879 "vcvttps2dq\t{$src, $dst|$dst, $src}",
880 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
881 (memop addr:$src)))]>,
882 XS, VEX, Requires<[HasAVX]>;
884 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
885 "cvttps2dq\t{$src, $dst|$dst, $src}",
887 (int_x86_sse2_cvttps2dq VR128:$src))]>,
888 XS, Requires<[HasSSE2]>;
889 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
890 "cvttps2dq\t{$src, $dst|$dst, $src}",
891 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
892 (memop addr:$src)))]>,
893 XS, Requires<[HasSSE2]>;
895 let isAsmParserOnly = 1 in {
896 def Int_VCVTTPD2DQrr : VPDI<0xE6, MRMSrcReg, (outs VR128:$dst),
898 "cvttpd2dq\t{$src, $dst|$dst, $src}",
899 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>,
901 def Int_VCVTTPD2DQrm : VPDI<0xE6, MRMSrcMem, (outs VR128:$dst),
903 "cvttpd2dq\t{$src, $dst|$dst, $src}",
904 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
905 (memop addr:$src)))]>, VEX;
907 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
908 "cvttpd2dq\t{$src, $dst|$dst, $src}",
909 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
910 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
911 "cvttpd2dq\t{$src, $dst|$dst, $src}",
912 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
913 (memop addr:$src)))]>;
915 // Convert packed single to packed double
916 let isAsmParserOnly = 1 in { // SSE2 instructions without OpSize prefix
917 def VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
918 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
920 def VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
921 "vcvtps2pd\t{$src, $dst|$dst, $src}", []>, VEX,
924 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
925 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
926 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
927 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
929 let isAsmParserOnly = 1 in {
930 def Int_VCVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
931 "cvtps2pd\t{$src, $dst|$dst, $src}",
932 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
933 VEX, Requires<[HasAVX]>;
934 def Int_VCVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
935 "cvtps2pd\t{$src, $dst|$dst, $src}",
936 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
937 (load addr:$src)))]>,
938 VEX, Requires<[HasAVX]>;
940 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
941 "cvtps2pd\t{$src, $dst|$dst, $src}",
942 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
943 TB, Requires<[HasSSE2]>;
944 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
945 "cvtps2pd\t{$src, $dst|$dst, $src}",
946 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
947 (load addr:$src)))]>,
948 TB, Requires<[HasSSE2]>;
950 // Convert packed double to packed single
951 let isAsmParserOnly = 1 in {
952 def VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
953 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>, VEX;
954 // FIXME: the memory form of this instruction should described using
955 // use extra asm syntax
957 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
958 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
959 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
960 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
963 let isAsmParserOnly = 1 in {
964 def Int_VCVTPD2PSrr : VPDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
965 "cvtpd2ps\t{$src, $dst|$dst, $src}",
966 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
967 def Int_VCVTPD2PSrm : VPDI<0x5A, MRMSrcMem, (outs VR128:$dst),
969 "cvtpd2ps\t{$src, $dst|$dst, $src}",
970 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
971 (memop addr:$src)))]>;
973 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
974 "cvtpd2ps\t{$src, $dst|$dst, $src}",
975 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
976 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
977 "cvtpd2ps\t{$src, $dst|$dst, $src}",
978 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
979 (memop addr:$src)))]>;
981 //===----------------------------------------------------------------------===//
982 // SSE 1 & 2 - Compare Instructions
983 //===----------------------------------------------------------------------===//
985 // sse12_cmp_scalar - sse 1 & 2 compare scalar instructions
986 multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
987 string asm, string asm_alt> {
988 def rr : SIi8<0xC2, MRMSrcReg,
989 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc),
992 def rm : SIi8<0xC2, MRMSrcMem,
993 (outs RC:$dst), (ins RC:$src1, x86memop:$src, SSECC:$cc),
995 // Accept explicit immediate argument form instead of comparison code.
996 let isAsmParserOnly = 1 in {
997 def rr_alt : SIi8<0xC2, MRMSrcReg,
998 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1001 def rm_alt : SIi8<0xC2, MRMSrcMem,
1002 (outs RC:$dst), (ins RC:$src1, x86memop:$src, i8imm:$src2),
1007 let neverHasSideEffects = 1, isAsmParserOnly = 1 in {
1008 defm VCMPSS : sse12_cmp_scalar<FR32, f32mem,
1009 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
1010 "cmpss\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1012 defm VCMPSD : sse12_cmp_scalar<FR64, f64mem,
1013 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
1014 "cmpsd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}">,
1018 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1019 defm CMPSS : sse12_cmp_scalar<FR32, f32mem,
1020 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
1021 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}">, XS;
1022 defm CMPSD : sse12_cmp_scalar<FR64, f64mem,
1023 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1024 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}">, XD;
1027 multiclass sse12_cmp_scalar_int<RegisterClass RC, X86MemOperand x86memop,
1028 Intrinsic Int, string asm> {
1029 def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
1030 (ins VR128:$src1, VR128:$src, SSECC:$cc), asm,
1031 [(set VR128:$dst, (Int VR128:$src1,
1032 VR128:$src, imm:$cc))]>;
1033 def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
1034 (ins VR128:$src1, f32mem:$src, SSECC:$cc), asm,
1035 [(set VR128:$dst, (Int VR128:$src1,
1036 (load addr:$src), imm:$cc))]>;
1039 // Aliases to match intrinsics which expect XMM operand(s).
1040 let isAsmParserOnly = 1 in {
1041 defm Int_VCMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1042 "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}">,
1044 defm Int_VCMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1045 "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}">,
1048 let Constraints = "$src1 = $dst" in {
1049 defm Int_CMPSS : sse12_cmp_scalar_int<VR128, f32mem, int_x86_sse_cmp_ss,
1050 "cmp${cc}ss\t{$src, $dst|$dst, $src}">, XS;
1051 defm Int_CMPSD : sse12_cmp_scalar_int<VR128, f64mem, int_x86_sse2_cmp_sd,
1052 "cmp${cc}sd\t{$src, $dst|$dst, $src}">, XD;
1056 // sse12_ord_cmp - Unordered/Ordered scalar fp compare and set EFLAGS
1057 multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
1058 ValueType vt, X86MemOperand x86memop,
1059 PatFrag ld_frag, string OpcodeStr, Domain d> {
1060 def rr: PI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
1061 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1062 [(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))], d>;
1063 def rm: PI<opc, MRMSrcMem, (outs), (ins RC:$src1, x86memop:$src2),
1064 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
1065 [(set EFLAGS, (OpNode (vt RC:$src1),
1066 (ld_frag addr:$src2)))], d>;
1069 let Defs = [EFLAGS] in {
1070 let isAsmParserOnly = 1 in {
1071 defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1072 "ucomiss", SSEPackedSingle>, VEX;
1073 defm VUCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1074 "ucomisd", SSEPackedDouble>, OpSize, VEX;
1075 let Pattern = []<dag> in {
1076 defm VCOMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1077 "comiss", SSEPackedSingle>, VEX;
1078 defm VCOMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1079 "comisd", SSEPackedDouble>, OpSize, VEX;
1082 defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1083 load, "ucomiss", SSEPackedSingle>, VEX;
1084 defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1085 load, "ucomisd", SSEPackedDouble>, OpSize, VEX;
1087 defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
1088 load, "comiss", SSEPackedSingle>, VEX;
1089 defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
1090 load, "comisd", SSEPackedDouble>, OpSize, VEX;
1092 defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
1093 "ucomiss", SSEPackedSingle>, TB;
1094 defm UCOMISD : sse12_ord_cmp<0x2E, FR64, X86cmp, f64, f64mem, loadf64,
1095 "ucomisd", SSEPackedDouble>, TB, OpSize;
1097 let Pattern = []<dag> in {
1098 defm COMISS : sse12_ord_cmp<0x2F, VR128, undef, v4f32, f128mem, load,
1099 "comiss", SSEPackedSingle>, TB;
1100 defm COMISD : sse12_ord_cmp<0x2F, VR128, undef, v2f64, f128mem, load,
1101 "comisd", SSEPackedDouble>, TB, OpSize;
1104 defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
1105 load, "ucomiss", SSEPackedSingle>, TB;
1106 defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
1107 load, "ucomisd", SSEPackedDouble>, TB, OpSize;
1109 defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
1110 "comiss", SSEPackedSingle>, TB;
1111 defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
1112 "comisd", SSEPackedDouble>, TB, OpSize;
1113 } // Defs = [EFLAGS]
1115 // sse12_cmp_packed - sse 1 & 2 compared packed instructions
1116 multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
1117 Intrinsic Int, string asm, string asm_alt,
1119 def rri : PIi8<0xC2, MRMSrcReg,
1120 (outs RC:$dst), (ins RC:$src1, RC:$src, SSECC:$cc), asm,
1121 [(set RC:$dst, (Int RC:$src1, RC:$src, imm:$cc))], d>;
1122 def rmi : PIi8<0xC2, MRMSrcMem,
1123 (outs RC:$dst), (ins RC:$src1, f128mem:$src, SSECC:$cc), asm,
1124 [(set RC:$dst, (Int RC:$src1, (memop addr:$src), imm:$cc))], d>;
1125 // Accept explicit immediate argument form instead of comparison code.
1126 let isAsmParserOnly = 1 in {
1127 def rri_alt : PIi8<0xC2, MRMSrcReg,
1128 (outs RC:$dst), (ins RC:$src1, RC:$src, i8imm:$src2),
1130 def rmi_alt : PIi8<0xC2, MRMSrcMem,
1131 (outs RC:$dst), (ins RC:$src1, f128mem:$src, i8imm:$src2),
1136 let isAsmParserOnly = 1 in {
1137 defm VCMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1138 "cmp${cc}ps\t{$src, $src1, $dst|$dst, $src1, $src}",
1139 "cmpps\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1140 SSEPackedSingle>, VEX_4V;
1141 defm VCMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1142 "cmp${cc}pd\t{$src, $src1, $dst|$dst, $src1, $src}",
1143 "cmppd\t{$src2, $src, $src1, $dst|$dst, $src1, $src, $src2}",
1144 SSEPackedDouble>, OpSize, VEX_4V;
1146 let Constraints = "$src1 = $dst" in {
1147 defm CMPPS : sse12_cmp_packed<VR128, f128mem, int_x86_sse_cmp_ps,
1148 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1149 "cmpps\t{$src2, $src, $dst|$dst, $src, $src2}",
1150 SSEPackedSingle>, TB;
1151 defm CMPPD : sse12_cmp_packed<VR128, f128mem, int_x86_sse2_cmp_pd,
1152 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1153 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}",
1154 SSEPackedDouble>, TB, OpSize;
1157 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1158 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1159 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1160 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1161 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1162 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1163 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1164 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1166 //===----------------------------------------------------------------------===//
1167 // SSE 1 & 2 - Shuffle Instructions
1168 //===----------------------------------------------------------------------===//
1170 /// sse12_shuffle - sse 1 & 2 shuffle instructions
1171 multiclass sse12_shuffle<RegisterClass RC, X86MemOperand x86memop,
1172 ValueType vt, string asm, PatFrag mem_frag,
1173 Domain d, bit IsConvertibleToThreeAddress = 0> {
1174 def rmi : PIi8<0xC6, MRMSrcMem, (outs VR128:$dst),
1175 (ins VR128:$src1, f128mem:$src2, i8imm:$src3), asm,
1176 [(set VR128:$dst, (vt (shufp:$src3
1177 VR128:$src1, (mem_frag addr:$src2))))], d>;
1178 let isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
1179 def rri : PIi8<0xC6, MRMSrcReg, (outs VR128:$dst),
1180 (ins VR128:$src1, VR128:$src2, i8imm:$src3), asm,
1182 (vt (shufp:$src3 VR128:$src1, VR128:$src2)))], d>;
1185 let isAsmParserOnly = 1 in {
1186 defm VSHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1187 "shufps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
1188 memopv4f32, SSEPackedSingle>, VEX_4V;
1189 defm VSHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1190 "shufpd\t{$src3, $src2, $src1, $dst|$dst, $src2, $src2, $src3}",
1191 memopv2f64, SSEPackedDouble>, OpSize, VEX_4V;
1194 let Constraints = "$src1 = $dst" in {
1195 defm SHUFPS : sse12_shuffle<VR128, f128mem, v4f32,
1196 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1197 memopv4f32, SSEPackedSingle, 1 /* cvt to pshufd */>,
1199 defm SHUFPD : sse12_shuffle<VR128, f128mem, v2f64,
1200 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1201 memopv2f64, SSEPackedDouble>, TB, OpSize;
1204 //===----------------------------------------------------------------------===//
1205 // SSE 1 & 2 - Unpack Instructions
1206 //===----------------------------------------------------------------------===//
1208 /// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
1209 multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
1210 PatFrag mem_frag, RegisterClass RC,
1211 X86MemOperand x86memop, string asm,
1213 def rr : PI<opc, MRMSrcReg,
1214 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1216 (vt (OpNode RC:$src1, RC:$src2)))], d>;
1217 def rm : PI<opc, MRMSrcMem,
1218 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1220 (vt (OpNode RC:$src1,
1221 (mem_frag addr:$src2))))], d>;
1224 let AddedComplexity = 10 in {
1225 let isAsmParserOnly = 1 in {
1226 defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1227 VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1228 SSEPackedSingle>, VEX_4V;
1229 defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1230 VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1231 SSEPackedDouble>, OpSize, VEX_4V;
1232 defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1233 VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1234 SSEPackedSingle>, VEX_4V;
1235 defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1236 VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1237 SSEPackedDouble>, OpSize, VEX_4V;
1239 defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
1240 VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1241 SSEPackedSingle>, VEX_4V;
1242 defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
1243 VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1244 SSEPackedDouble>, OpSize, VEX_4V;
1245 defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
1246 VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1247 SSEPackedSingle>, VEX_4V;
1248 defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
1249 VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1250 SSEPackedDouble>, OpSize, VEX_4V;
1253 let Constraints = "$src1 = $dst" in {
1254 defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
1255 VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
1256 SSEPackedSingle>, TB;
1257 defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
1258 VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
1259 SSEPackedDouble>, TB, OpSize;
1260 defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
1261 VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
1262 SSEPackedSingle>, TB;
1263 defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
1264 VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
1265 SSEPackedDouble>, TB, OpSize;
1266 } // Constraints = "$src1 = $dst"
1267 } // AddedComplexity
1269 //===----------------------------------------------------------------------===//
1270 // SSE 1 & 2 - Extract Floating-Point Sign mask
1271 //===----------------------------------------------------------------------===//
1273 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
1274 multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
1276 def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
1277 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1278 [(set GR32:$dst, (Int RC:$src))], d>;
1282 defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
1283 SSEPackedSingle>, TB;
1284 defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
1285 SSEPackedDouble>, TB, OpSize;
1287 let isAsmParserOnly = 1 in {
1288 defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
1289 "movmskps", SSEPackedSingle>, VEX;
1290 defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
1291 "movmskpd", SSEPackedDouble>, OpSize,
1293 // FIXME: merge with multiclass above when the intrinsics come.
1294 def VMOVMSKPSYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1295 "movmskps\t{$src, $dst|$dst, $src}", [], SSEPackedSingle>, VEX;
1296 def VMOVMSKPDYrr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),
1297 "movmskpd\t{$src, $dst|$dst, $src}", [], SSEPackedDouble>, OpSize,
1301 //===----------------------------------------------------------------------===//
1302 // SSE 1 & 2 - Misc aliasing of packed SSE 1 & 2 instructions
1303 //===----------------------------------------------------------------------===//
1305 // Aliases of packed SSE1 & SSE2 instructions for scalar use. These all have
1306 // names that start with 'Fs'.
1308 // Alias instructions that map fld0 to pxor for sse.
1309 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1310 canFoldAsLoad = 1 in {
1311 // FIXME: Set encoding to pseudo!
1312 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
1313 [(set FR32:$dst, fp32imm0)]>,
1314 Requires<[HasSSE1]>, TB, OpSize;
1315 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1316 [(set FR64:$dst, fpimm0)]>,
1317 Requires<[HasSSE2]>, TB, OpSize;
1320 // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper
1321 // bits are disregarded.
1322 let neverHasSideEffects = 1 in {
1323 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1324 "movaps\t{$src, $dst|$dst, $src}", []>;
1325 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1326 "movapd\t{$src, $dst|$dst, $src}", []>;
1329 // Alias instruction to load FR32 or FR64 from f128mem using movaps. Upper
1330 // bits are disregarded.
1331 let canFoldAsLoad = 1, isReMaterializable = 1 in {
1332 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
1333 "movaps\t{$src, $dst|$dst, $src}",
1334 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
1335 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1336 "movapd\t{$src, $dst|$dst, $src}",
1337 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1340 //===----------------------------------------------------------------------===//
1341 // SSE 1 & 2 - Logical Instructions
1342 //===----------------------------------------------------------------------===//
1344 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
1346 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
1348 let isAsmParserOnly = 1 in {
1349 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode,
1350 FR32, f32, f128mem, memopfsf32, SSEPackedSingle, 0>, VEX_4V;
1352 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode,
1353 FR64, f64, f128mem, memopfsf64, SSEPackedDouble, 0>, OpSize, VEX_4V;
1356 let Constraints = "$src1 = $dst" in {
1357 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, FR32,
1358 f32, f128mem, memopfsf32, SSEPackedSingle>, TB;
1360 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, FR64,
1361 f64, f128mem, memopfsf64, SSEPackedDouble>, TB, OpSize;
1365 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1366 let mayLoad = 0 in {
1367 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
1368 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
1369 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
1372 let neverHasSideEffects = 1, Pattern = []<dag>, isCommutable = 0 in
1373 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef>;
1375 /// sse12_fp_packed_logical - SSE 1 & 2 packed FP logical ops
1377 multiclass sse12_fp_packed_logical<bits<8> opc, string OpcodeStr,
1378 SDNode OpNode, int HasPat = 0,
1379 list<list<dag>> Pattern = []> {
1380 let isAsmParserOnly = 1, Pattern = []<dag> in {
1381 defm V#NAME#PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1382 !strconcat(OpcodeStr, "ps"), f128mem,
1383 !if(HasPat, Pattern[0], // rr
1384 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1386 !if(HasPat, Pattern[2], // rm
1387 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1388 (memopv2i64 addr:$src2)))]), 0>,
1391 defm V#NAME#PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1392 !strconcat(OpcodeStr, "pd"), f128mem,
1393 !if(HasPat, Pattern[1], // rr
1394 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1397 !if(HasPat, Pattern[3], // rm
1398 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1399 (memopv2i64 addr:$src2)))]), 0>,
1402 let Constraints = "$src1 = $dst" in {
1403 defm PS : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedSingle,
1404 !strconcat(OpcodeStr, "ps"), f128mem,
1405 !if(HasPat, Pattern[0], // rr
1406 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1408 !if(HasPat, Pattern[2], // rm
1409 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1410 (memopv2i64 addr:$src2)))])>, TB;
1412 defm PD : sse12_fp_packed_logical_rm<opc, VR128, SSEPackedDouble,
1413 !strconcat(OpcodeStr, "pd"), f128mem,
1414 !if(HasPat, Pattern[1], // rr
1415 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1418 !if(HasPat, Pattern[3], // rm
1419 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1420 (memopv2i64 addr:$src2)))])>,
1425 /// sse12_fp_packed_logical_y - AVX 256-bit SSE 1 & 2 logical ops forms
1427 let isAsmParserOnly = 1 in {
1428 multiclass sse12_fp_packed_logical_y<bits<8> opc, string OpcodeStr> {
1429 defm PSY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedSingle,
1430 !strconcat(OpcodeStr, "ps"), f256mem, [], [], 0>, VEX_4V;
1432 defm PDY : sse12_fp_packed_logical_rm<opc, VR256, SSEPackedDouble,
1433 !strconcat(OpcodeStr, "pd"), f256mem, [], [], 0>, OpSize, VEX_4V;
1437 // AVX 256-bit packed logical ops forms
1438 defm VAND : sse12_fp_packed_logical_y<0x54, "and">;
1439 defm VOR : sse12_fp_packed_logical_y<0x56, "or">;
1440 defm VXOR : sse12_fp_packed_logical_y<0x57, "xor">;
1441 let isCommutable = 0 in
1442 defm VANDN : sse12_fp_packed_logical_y<0x55, "andn">;
1444 defm AND : sse12_fp_packed_logical<0x54, "and", and>;
1445 defm OR : sse12_fp_packed_logical<0x56, "or", or>;
1446 defm XOR : sse12_fp_packed_logical<0x57, "xor", xor>;
1447 let isCommutable = 0 in
1448 defm ANDN : sse12_fp_packed_logical<0x55, "andn", undef /* dummy */, 1, [
1450 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1451 (bc_v2i64 (v4i32 immAllOnesV))),
1454 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1455 (bc_v2i64 (v2f64 VR128:$src2))))],
1457 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1458 (bc_v2i64 (v4i32 immAllOnesV))),
1459 (memopv2i64 addr:$src2))))],
1461 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1462 (memopv2i64 addr:$src2)))]]>;
1464 //===----------------------------------------------------------------------===//
1465 // SSE 1 & 2 - Arithmetic Instructions
1466 //===----------------------------------------------------------------------===//
1468 /// basic_sse12_fp_binop_xxx - SSE 1 & 2 binops come in both scalar and
1471 /// In addition, we also have a special variant of the scalar form here to
1472 /// represent the associated intrinsic operation. This form is unlike the
1473 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1474 /// and leaves the top elements unmodified (therefore these cannot be commuted).
1476 /// These three forms can each be reg+reg or reg+mem.
1478 multiclass basic_sse12_fp_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1480 defm SS : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"),
1481 OpNode, FR32, f32mem, Is2Addr>, XS;
1482 defm SD : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"),
1483 OpNode, FR64, f64mem, Is2Addr>, XD;
1486 multiclass basic_sse12_fp_binop_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
1488 let mayLoad = 0 in {
1489 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR128,
1490 v4f32, f128mem, memopv4f32, SSEPackedSingle, Is2Addr>, TB;
1491 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR128,
1492 v2f64, f128mem, memopv2f64, SSEPackedDouble, Is2Addr>, TB, OpSize;
1496 multiclass basic_sse12_fp_binop_p_y<bits<8> opc, string OpcodeStr,
1498 let mayLoad = 0 in {
1499 defm PSY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "ps"), OpNode, VR256,
1500 v8f32, f256mem, memopv8f32, SSEPackedSingle, 0>, TB;
1501 defm PDY : sse12_fp_packed<opc, !strconcat(OpcodeStr, "pd"), OpNode, VR256,
1502 v4f64, f256mem, memopv4f64, SSEPackedDouble, 0>, TB, OpSize;
1506 multiclass basic_sse12_fp_binop_s_int<bits<8> opc, string OpcodeStr,
1508 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1509 !strconcat(OpcodeStr, "ss"), "", "_ss", ssmem, sse_load_f32, Is2Addr>, XS;
1510 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
1511 !strconcat(OpcodeStr, "sd"), "2", "_sd", sdmem, sse_load_f64, Is2Addr>, XD;
1514 multiclass basic_sse12_fp_binop_p_int<bits<8> opc, string OpcodeStr,
1516 defm PS : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1517 !strconcat(OpcodeStr, "ps"), "", "_ps", f128mem, memopv4f32,
1518 SSEPackedSingle, Is2Addr>, TB;
1520 defm PD : sse12_fp_packed_int<opc, OpcodeStr, VR128,
1521 !strconcat(OpcodeStr, "pd"), "2", "_pd", f128mem, memopv2f64,
1522 SSEPackedDouble, Is2Addr>, TB, OpSize;
1525 // Binary Arithmetic instructions
1526 let isAsmParserOnly = 1 in {
1527 defm VADD : basic_sse12_fp_binop_s<0x58, "add", fadd, 0>,
1528 basic_sse12_fp_binop_p<0x58, "add", fadd, 0>,
1529 basic_sse12_fp_binop_p_y<0x58, "add", fadd>, VEX_4V;
1530 defm VMUL : basic_sse12_fp_binop_s<0x59, "mul", fmul, 0>,
1531 basic_sse12_fp_binop_p<0x59, "mul", fmul, 0>,
1532 basic_sse12_fp_binop_p_y<0x59, "mul", fmul>, VEX_4V;
1534 let isCommutable = 0 in {
1535 defm VSUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub, 0>,
1536 basic_sse12_fp_binop_p<0x5C, "sub", fsub, 0>,
1537 basic_sse12_fp_binop_p_y<0x5C, "sub", fsub>, VEX_4V;
1538 defm VDIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv, 0>,
1539 basic_sse12_fp_binop_p<0x5E, "div", fdiv, 0>,
1540 basic_sse12_fp_binop_p_y<0x5E, "div", fdiv>, VEX_4V;
1541 defm VMAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax, 0>,
1542 basic_sse12_fp_binop_p<0x5F, "max", X86fmax, 0>,
1543 basic_sse12_fp_binop_p_y<0x5F, "max", X86fmax>, VEX_4V;
1544 defm VMIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin, 0>,
1545 basic_sse12_fp_binop_p<0x5D, "min", X86fmin, 0>,
1546 basic_sse12_fp_binop_p_y<0x5D, "min", X86fmin>, VEX_4V;
1550 let Constraints = "$src1 = $dst" in {
1551 defm ADD : basic_sse12_fp_binop_s<0x58, "add", fadd>,
1552 basic_sse12_fp_binop_p<0x58, "add", fadd>,
1553 basic_sse12_fp_binop_s_int<0x58, "add">;
1554 defm MUL : basic_sse12_fp_binop_s<0x59, "mul", fmul>,
1555 basic_sse12_fp_binop_p<0x59, "mul", fmul>,
1556 basic_sse12_fp_binop_s_int<0x59, "mul">;
1558 let isCommutable = 0 in {
1559 defm SUB : basic_sse12_fp_binop_s<0x5C, "sub", fsub>,
1560 basic_sse12_fp_binop_p<0x5C, "sub", fsub>,
1561 basic_sse12_fp_binop_s_int<0x5C, "sub">;
1562 defm DIV : basic_sse12_fp_binop_s<0x5E, "div", fdiv>,
1563 basic_sse12_fp_binop_p<0x5E, "div", fdiv>,
1564 basic_sse12_fp_binop_s_int<0x5E, "div">;
1565 defm MAX : basic_sse12_fp_binop_s<0x5F, "max", X86fmax>,
1566 basic_sse12_fp_binop_p<0x5F, "max", X86fmax>,
1567 basic_sse12_fp_binop_s_int<0x5F, "max">,
1568 basic_sse12_fp_binop_p_int<0x5F, "max">;
1569 defm MIN : basic_sse12_fp_binop_s<0x5D, "min", X86fmin>,
1570 basic_sse12_fp_binop_p<0x5D, "min", X86fmin>,
1571 basic_sse12_fp_binop_s_int<0x5D, "min">,
1572 basic_sse12_fp_binop_p_int<0x5D, "min">;
1577 /// In addition, we also have a special variant of the scalar form here to
1578 /// represent the associated intrinsic operation. This form is unlike the
1579 /// plain scalar form, in that it takes an entire vector (instead of a
1580 /// scalar) and leaves the top elements undefined.
1582 /// And, we have a special variant form for a full-vector intrinsic form.
1584 /// sse1_fp_unop_s - SSE1 unops in scalar form.
1585 multiclass sse1_fp_unop_s<bits<8> opc, string OpcodeStr,
1586 SDNode OpNode, Intrinsic F32Int> {
1587 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1588 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1589 [(set FR32:$dst, (OpNode FR32:$src))]>;
1590 // For scalar unary operations, fold a load into the operation
1591 // only in OptForSize mode. It eliminates an instruction, but it also
1592 // eliminates a whole-register clobber (the load), so it introduces a
1593 // partial register update condition.
1594 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1595 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1596 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1597 Requires<[HasSSE1, OptForSize]>;
1598 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1599 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1600 [(set VR128:$dst, (F32Int VR128:$src))]>;
1601 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1602 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1603 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1606 /// sse1_fp_unop_s_avx - AVX SSE1 unops in scalar form.
1607 multiclass sse1_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1608 SDNode OpNode, Intrinsic F32Int> {
1609 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
1610 !strconcat(!strconcat("v", OpcodeStr),
1611 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1612 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
1613 !strconcat(!strconcat("v", OpcodeStr),
1614 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1615 []>, XS, Requires<[HasAVX, OptForSize]>;
1616 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
1617 (ins VR128:$src1, VR128:$src2),
1618 !strconcat(!strconcat("v", OpcodeStr),
1619 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1620 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
1621 (ins VR128:$src1, ssmem:$src2),
1622 !strconcat(!strconcat("v", OpcodeStr),
1623 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1626 /// sse1_fp_unop_p - SSE1 unops in packed form.
1627 multiclass sse1_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1628 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1629 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1630 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]>;
1631 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1632 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1633 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1636 /// sse1_fp_unop_p_y - AVX 256-bit SSE1 unops in packed form.
1637 multiclass sse1_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1638 def PSYr : PSI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1639 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1640 [(set VR256:$dst, (v8f32 (OpNode VR256:$src)))]>;
1641 def PSYm : PSI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1642 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1643 [(set VR256:$dst, (OpNode (memopv8f32 addr:$src)))]>;
1646 /// sse1_fp_unop_p_int - SSE1 intrinsics unops in packed forms.
1647 multiclass sse1_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1648 Intrinsic V4F32Int> {
1649 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1650 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1651 [(set VR128:$dst, (V4F32Int VR128:$src))]>;
1652 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1653 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1654 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1658 /// sse2_fp_unop_s - SSE2 unops in scalar form.
1659 multiclass sse2_fp_unop_s<bits<8> opc, string OpcodeStr,
1660 SDNode OpNode, Intrinsic F64Int> {
1661 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1662 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1663 [(set FR64:$dst, (OpNode FR64:$src))]>;
1664 // See the comments in sse1_fp_unop_s for why this is OptForSize.
1665 def SDm : I<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1666 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1667 [(set FR64:$dst, (OpNode (load addr:$src)))]>, XD,
1668 Requires<[HasSSE2, OptForSize]>;
1669 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1670 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1671 [(set VR128:$dst, (F64Int VR128:$src))]>;
1672 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1673 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1674 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1677 /// sse2_fp_unop_s_avx - AVX SSE2 unops in scalar form.
1678 multiclass sse2_fp_unop_s_avx<bits<8> opc, string OpcodeStr,
1679 SDNode OpNode, Intrinsic F64Int> {
1680 def SDr : VSDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1681 !strconcat(OpcodeStr,
1682 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1683 def SDm : VSDI<opc, MRMSrcMem, (outs FR64:$dst),
1684 (ins FR64:$src1, f64mem:$src2),
1685 !strconcat(OpcodeStr,
1686 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
1687 def SDr_Int : VSDI<opc, MRMSrcReg, (outs VR128:$dst),
1688 (ins VR128:$src1, VR128:$src2),
1689 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1691 def SDm_Int : VSDI<opc, MRMSrcMem, (outs VR128:$dst),
1692 (ins VR128:$src1, sdmem:$src2),
1693 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1697 /// sse2_fp_unop_p - SSE2 unops in vector forms.
1698 multiclass sse2_fp_unop_p<bits<8> opc, string OpcodeStr,
1700 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1701 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1702 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]>;
1703 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1704 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1705 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1708 /// sse2_fp_unop_p_y - AVX SSE2 256-bit unops in vector forms.
1709 multiclass sse2_fp_unop_p_y<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1710 def PDYr : PDI<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
1711 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1712 [(set VR256:$dst, (v4f64 (OpNode VR256:$src)))]>;
1713 def PDYm : PDI<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
1714 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1715 [(set VR256:$dst, (OpNode (memopv4f64 addr:$src)))]>;
1718 /// sse2_fp_unop_p_int - SSE2 intrinsic unops in vector forms.
1719 multiclass sse2_fp_unop_p_int<bits<8> opc, string OpcodeStr,
1720 Intrinsic V2F64Int> {
1721 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1722 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1723 [(set VR128:$dst, (V2F64Int VR128:$src))]>;
1724 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1725 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1726 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1729 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
1731 defm VSQRT : sse1_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1732 sse2_fp_unop_s_avx<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1735 defm VSQRT : sse1_fp_unop_p<0x51, "vsqrt", fsqrt>,
1736 sse2_fp_unop_p<0x51, "vsqrt", fsqrt>,
1737 sse1_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1738 sse2_fp_unop_p_y<0x51, "vsqrt", fsqrt>,
1741 // Reciprocal approximations. Note that these typically require refinement
1742 // in order to obtain suitable precision.
1743 defm VRSQRT : sse1_fp_unop_s_avx<0x52, "rsqrt", X86frsqrt,
1744 int_x86_sse_rsqrt_ss>, VEX_4V;
1745 defm VRSQRT : sse1_fp_unop_p<0x52, "vrsqrt", X86frsqrt>,
1746 sse1_fp_unop_p_y<0x52, "vrsqrt", X86frsqrt>, VEX;
1748 defm VRCP : sse1_fp_unop_s_avx<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1750 defm VRCP : sse1_fp_unop_p<0x53, "vrcp", X86frcp>,
1751 sse1_fp_unop_p_y<0x53, "vrcp", X86frcp>, VEX;
1755 defm SQRT : sse1_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse_sqrt_ss>,
1756 sse1_fp_unop_p<0x51, "sqrt", fsqrt>,
1757 sse1_fp_unop_p_int<0x51, "sqrt", int_x86_sse_sqrt_ps>,
1758 sse2_fp_unop_s<0x51, "sqrt", fsqrt, int_x86_sse2_sqrt_sd>,
1759 sse2_fp_unop_p<0x51, "sqrt", fsqrt>,
1760 sse2_fp_unop_p_int<0x51, "sqrt", int_x86_sse2_sqrt_pd>;
1762 // Reciprocal approximations. Note that these typically require refinement
1763 // in order to obtain suitable precision.
1764 defm RSQRT : sse1_fp_unop_s<0x52, "rsqrt", X86frsqrt, int_x86_sse_rsqrt_ss>,
1765 sse1_fp_unop_p<0x52, "rsqrt", X86frsqrt>,
1766 sse1_fp_unop_p_int<0x52, "rsqrt", int_x86_sse_rsqrt_ps>;
1767 defm RCP : sse1_fp_unop_s<0x53, "rcp", X86frcp, int_x86_sse_rcp_ss>,
1768 sse1_fp_unop_p<0x53, "rcp", X86frcp>,
1769 sse1_fp_unop_p_int<0x53, "rcp", int_x86_sse_rcp_ps>;
1771 // There is no f64 version of the reciprocal approximation instructions.
1773 //===----------------------------------------------------------------------===//
1774 // SSE 1 & 2 - Non-temporal stores
1775 //===----------------------------------------------------------------------===//
1777 let isAsmParserOnly = 1 in {
1778 def VMOVNTPSmr_Int : VPSI<0x2B, MRMDestMem, (outs),
1779 (ins i128mem:$dst, VR128:$src),
1780 "movntps\t{$src, $dst|$dst, $src}",
1781 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>, VEX;
1782 def VMOVNTPDmr_Int : VPDI<0x2B, MRMDestMem, (outs),
1783 (ins i128mem:$dst, VR128:$src),
1784 "movntpd\t{$src, $dst|$dst, $src}",
1785 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>, VEX;
1787 let ExeDomain = SSEPackedInt in
1788 def VMOVNTDQmr_Int : VPDI<0xE7, MRMDestMem, (outs),
1789 (ins f128mem:$dst, VR128:$src),
1790 "movntdq\t{$src, $dst|$dst, $src}",
1791 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>, VEX;
1793 let AddedComplexity = 400 in { // Prefer non-temporal versions
1794 def VMOVNTPSmr : VPSI<0x2B, MRMDestMem, (outs),
1795 (ins f128mem:$dst, VR128:$src),
1796 "movntps\t{$src, $dst|$dst, $src}",
1797 [(alignednontemporalstore (v4f32 VR128:$src),
1799 def VMOVNTPDmr : VPDI<0x2B, MRMDestMem, (outs),
1800 (ins f128mem:$dst, VR128:$src),
1801 "movntpd\t{$src, $dst|$dst, $src}",
1802 [(alignednontemporalstore (v2f64 VR128:$src),
1804 def VMOVNTDQ_64mr : VPDI<0xE7, MRMDestMem, (outs),
1805 (ins f128mem:$dst, VR128:$src),
1806 "movntdq\t{$src, $dst|$dst, $src}",
1807 [(alignednontemporalstore (v2f64 VR128:$src),
1809 let ExeDomain = SSEPackedInt in
1810 def VMOVNTDQmr : VPDI<0xE7, MRMDestMem, (outs),
1811 (ins f128mem:$dst, VR128:$src),
1812 "movntdq\t{$src, $dst|$dst, $src}",
1813 [(alignednontemporalstore (v4f32 VR128:$src),
1816 def VMOVNTPSYmr : VPSI<0x2B, MRMDestMem, (outs),
1817 (ins f256mem:$dst, VR256:$src),
1818 "movntps\t{$src, $dst|$dst, $src}",
1819 [(alignednontemporalstore (v8f32 VR256:$src),
1821 def VMOVNTPDYmr : VPDI<0x2B, MRMDestMem, (outs),
1822 (ins f256mem:$dst, VR256:$src),
1823 "movntpd\t{$src, $dst|$dst, $src}",
1824 [(alignednontemporalstore (v4f64 VR256:$src),
1826 def VMOVNTDQY_64mr : VPDI<0xE7, MRMDestMem, (outs),
1827 (ins f256mem:$dst, VR256:$src),
1828 "movntdq\t{$src, $dst|$dst, $src}",
1829 [(alignednontemporalstore (v4f64 VR256:$src),
1831 let ExeDomain = SSEPackedInt in
1832 def VMOVNTDQYmr : VPDI<0xE7, MRMDestMem, (outs),
1833 (ins f256mem:$dst, VR256:$src),
1834 "movntdq\t{$src, $dst|$dst, $src}",
1835 [(alignednontemporalstore (v8f32 VR256:$src),
1840 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1841 "movntps\t{$src, $dst|$dst, $src}",
1842 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1843 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1844 "movntpd\t{$src, $dst|$dst, $src}",
1845 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
1847 let ExeDomain = SSEPackedInt in
1848 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1849 "movntdq\t{$src, $dst|$dst, $src}",
1850 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
1852 let AddedComplexity = 400 in { // Prefer non-temporal versions
1853 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1854 "movntps\t{$src, $dst|$dst, $src}",
1855 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1856 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1857 "movntpd\t{$src, $dst|$dst, $src}",
1858 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
1860 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1861 "movntdq\t{$src, $dst|$dst, $src}",
1862 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1864 let ExeDomain = SSEPackedInt in
1865 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1866 "movntdq\t{$src, $dst|$dst, $src}",
1867 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1869 // There is no AVX form for instructions below this point
1870 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1871 "movnti\t{$src, $dst|$dst, $src}",
1872 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1873 TB, Requires<[HasSSE2]>;
1875 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1876 "movnti\t{$src, $dst|$dst, $src}",
1877 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1878 TB, Requires<[HasSSE2]>;
1881 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1882 "movnti\t{$src, $dst|$dst, $src}",
1883 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
1884 TB, Requires<[HasSSE2]>;
1886 //===----------------------------------------------------------------------===//
1887 // SSE 1 & 2 - Misc Instructions (No AVX form)
1888 //===----------------------------------------------------------------------===//
1890 // Prefetch intrinsic.
1891 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1892 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1893 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1894 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1895 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1896 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1897 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1898 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1900 // Load, store, and memory fence
1901 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1902 TB, Requires<[HasSSE1]>;
1904 // Alias instructions that map zero vector to pxor / xorp* for sse.
1905 // We set canFoldAsLoad because this can be converted to a constant-pool
1906 // load of an all-zeros value if folding it would be beneficial.
1907 // FIXME: Change encoding to pseudo!
1908 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1909 isCodeGenOnly = 1 in {
1910 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1911 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1912 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1913 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1914 let ExeDomain = SSEPackedInt in
1915 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1916 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1919 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1920 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1921 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1923 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1924 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1926 //===----------------------------------------------------------------------===//
1927 // SSE 1 & 2 - Load/Store XCSR register
1928 //===----------------------------------------------------------------------===//
1930 let isAsmParserOnly = 1 in {
1931 def VLDMXCSR : VPSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1932 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>, VEX;
1933 def VSTMXCSR : VPSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1934 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>, VEX;
1937 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1938 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1939 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1940 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1942 //===---------------------------------------------------------------------===//
1943 // SSE2 - Move Aligned/Unaligned Packed Integer Instructions
1944 //===---------------------------------------------------------------------===//
1945 let ExeDomain = SSEPackedInt in { // SSE integer instructions
1947 let isAsmParserOnly = 1 in {
1948 let neverHasSideEffects = 1 in
1949 def VMOVDQArr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1950 "movdqa\t{$src, $dst|$dst, $src}", []>, VEX;
1951 def VMOVDQUrr : VPDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1952 "movdqu\t{$src, $dst|$dst, $src}", []>, XS, VEX;
1954 let canFoldAsLoad = 1, mayLoad = 1 in {
1955 def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1956 "movdqa\t{$src, $dst|$dst, $src}",
1957 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>,
1959 def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1960 "vmovdqu\t{$src, $dst|$dst, $src}",
1961 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1962 XS, VEX, Requires<[HasAVX]>;
1965 let mayStore = 1 in {
1966 def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
1967 (ins i128mem:$dst, VR128:$src),
1968 "movdqa\t{$src, $dst|$dst, $src}",
1969 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>, VEX;
1970 def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1971 "vmovdqu\t{$src, $dst|$dst, $src}",
1972 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1973 XS, VEX, Requires<[HasAVX]>;
1977 let neverHasSideEffects = 1 in
1978 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1979 "movdqa\t{$src, $dst|$dst, $src}", []>;
1981 let canFoldAsLoad = 1, mayLoad = 1 in {
1982 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1983 "movdqa\t{$src, $dst|$dst, $src}",
1984 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1985 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1986 "movdqu\t{$src, $dst|$dst, $src}",
1987 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1988 XS, Requires<[HasSSE2]>;
1991 let mayStore = 1 in {
1992 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1993 "movdqa\t{$src, $dst|$dst, $src}",
1994 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1995 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1996 "movdqu\t{$src, $dst|$dst, $src}",
1997 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1998 XS, Requires<[HasSSE2]>;
2001 // Intrinsic forms of MOVDQU load and store
2002 let isAsmParserOnly = 1 in {
2003 let canFoldAsLoad = 1 in
2004 def VMOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2005 "vmovdqu\t{$src, $dst|$dst, $src}",
2006 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2007 XS, VEX, Requires<[HasAVX]>;
2008 def VMOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2009 "vmovdqu\t{$src, $dst|$dst, $src}",
2010 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2011 XS, VEX, Requires<[HasAVX]>;
2014 let canFoldAsLoad = 1 in
2015 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2016 "movdqu\t{$src, $dst|$dst, $src}",
2017 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
2018 XS, Requires<[HasSSE2]>;
2019 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2020 "movdqu\t{$src, $dst|$dst, $src}",
2021 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
2022 XS, Requires<[HasSSE2]>;
2024 } // ExeDomain = SSEPackedInt
2026 //===---------------------------------------------------------------------===//
2027 // SSE2 - Packed Integer Arithmetic Instructions
2028 //===---------------------------------------------------------------------===//
2030 let ExeDomain = SSEPackedInt in { // SSE integer instructions
2032 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
2033 bit IsCommutable = 0, bit Is2Addr = 1> {
2034 let isCommutable = IsCommutable in
2035 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2036 (ins VR128:$src1, VR128:$src2),
2038 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2039 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2040 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2041 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2042 (ins VR128:$src1, i128mem:$src2),
2044 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2046 [(set VR128:$dst, (IntId VR128:$src1,
2047 (bitconvert (memopv2i64 addr:$src2))))]>;
2050 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
2051 string OpcodeStr, Intrinsic IntId,
2052 Intrinsic IntId2, bit Is2Addr = 1> {
2053 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2054 (ins VR128:$src1, VR128:$src2),
2056 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2057 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2058 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
2059 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2060 (ins VR128:$src1, i128mem:$src2),
2062 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2063 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2064 [(set VR128:$dst, (IntId VR128:$src1,
2065 (bitconvert (memopv2i64 addr:$src2))))]>;
2066 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
2067 (ins VR128:$src1, i32i8imm:$src2),
2069 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2070 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2071 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
2074 /// PDI_binop_rm - Simple SSE2 binary operator.
2075 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2076 ValueType OpVT, bit IsCommutable = 0, bit Is2Addr = 1> {
2077 let isCommutable = IsCommutable in
2078 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2079 (ins VR128:$src1, VR128:$src2),
2081 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2082 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2083 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>;
2084 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2085 (ins VR128:$src1, i128mem:$src2),
2087 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2088 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2089 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
2090 (bitconvert (memopv2i64 addr:$src2)))))]>;
2093 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
2095 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
2096 /// to collapse (bitconvert VT to VT) into its operand.
2098 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
2099 bit IsCommutable = 0, bit Is2Addr = 1> {
2100 let isCommutable = IsCommutable in
2101 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
2102 (ins VR128:$src1, VR128:$src2),
2104 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2105 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2106 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]>;
2107 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
2108 (ins VR128:$src1, i128mem:$src2),
2110 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2111 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2112 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2i64 addr:$src2)))]>;
2115 } // ExeDomain = SSEPackedInt
2117 // 128-bit Integer Arithmetic
2119 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2120 defm VPADDB : PDI_binop_rm<0xFC, "vpaddb", add, v16i8, 1, 0 /*3addr*/>, VEX_4V;
2121 defm VPADDW : PDI_binop_rm<0xFD, "vpaddw", add, v8i16, 1, 0>, VEX_4V;
2122 defm VPADDD : PDI_binop_rm<0xFE, "vpaddd", add, v4i32, 1, 0>, VEX_4V;
2123 defm VPADDQ : PDI_binop_rm_v2i64<0xD4, "vpaddq", add, 1, 0>, VEX_4V;
2124 defm VPMULLW : PDI_binop_rm<0xD5, "vpmullw", mul, v8i16, 1, 0>, VEX_4V;
2125 defm VPSUBB : PDI_binop_rm<0xF8, "vpsubb", sub, v16i8, 0, 0>, VEX_4V;
2126 defm VPSUBW : PDI_binop_rm<0xF9, "vpsubw", sub, v8i16, 0, 0>, VEX_4V;
2127 defm VPSUBD : PDI_binop_rm<0xFA, "vpsubd", sub, v4i32, 0, 0>, VEX_4V;
2128 defm VPSUBQ : PDI_binop_rm_v2i64<0xFB, "vpsubq", sub, 0, 0>, VEX_4V;
2131 defm VPSUBSB : PDI_binop_rm_int<0xE8, "vpsubsb" , int_x86_sse2_psubs_b, 0, 0>,
2133 defm VPSUBSW : PDI_binop_rm_int<0xE9, "vpsubsw" , int_x86_sse2_psubs_w, 0, 0>,
2135 defm VPSUBUSB : PDI_binop_rm_int<0xD8, "vpsubusb", int_x86_sse2_psubus_b, 0, 0>,
2137 defm VPSUBUSW : PDI_binop_rm_int<0xD9, "vpsubusw", int_x86_sse2_psubus_w, 0, 0>,
2139 defm VPADDSB : PDI_binop_rm_int<0xEC, "vpaddsb" , int_x86_sse2_padds_b, 1, 0>,
2141 defm VPADDSW : PDI_binop_rm_int<0xED, "vpaddsw" , int_x86_sse2_padds_w, 1, 0>,
2143 defm VPADDUSB : PDI_binop_rm_int<0xDC, "vpaddusb", int_x86_sse2_paddus_b, 1, 0>,
2145 defm VPADDUSW : PDI_binop_rm_int<0xDD, "vpaddusw", int_x86_sse2_paddus_w, 1, 0>,
2147 defm VPMULHUW : PDI_binop_rm_int<0xE4, "vpmulhuw", int_x86_sse2_pmulhu_w, 1, 0>,
2149 defm VPMULHW : PDI_binop_rm_int<0xE5, "vpmulhw" , int_x86_sse2_pmulh_w, 1, 0>,
2151 defm VPMULUDQ : PDI_binop_rm_int<0xF4, "vpmuludq", int_x86_sse2_pmulu_dq, 1, 0>,
2153 defm VPMADDWD : PDI_binop_rm_int<0xF5, "vpmaddwd", int_x86_sse2_pmadd_wd, 1, 0>,
2155 defm VPAVGB : PDI_binop_rm_int<0xE0, "vpavgb", int_x86_sse2_pavg_b, 1, 0>,
2157 defm VPAVGW : PDI_binop_rm_int<0xE3, "vpavgw", int_x86_sse2_pavg_w, 1, 0>,
2159 defm VPMINUB : PDI_binop_rm_int<0xDA, "vpminub", int_x86_sse2_pminu_b, 1, 0>,
2161 defm VPMINSW : PDI_binop_rm_int<0xEA, "vpminsw", int_x86_sse2_pmins_w, 1, 0>,
2163 defm VPMAXUB : PDI_binop_rm_int<0xDE, "vpmaxub", int_x86_sse2_pmaxu_b, 1, 0>,
2165 defm VPMAXSW : PDI_binop_rm_int<0xEE, "vpmaxsw", int_x86_sse2_pmaxs_w, 1, 0>,
2167 defm VPSADBW : PDI_binop_rm_int<0xF6, "vpsadbw", int_x86_sse2_psad_bw, 1, 0>,
2171 let Constraints = "$src1 = $dst" in {
2172 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
2173 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
2174 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
2175 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
2176 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2177 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2178 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2179 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2180 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2183 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2184 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2185 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2186 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2187 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
2188 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
2189 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2190 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2191 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2192 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w, 1>;
2193 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2194 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2195 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2196 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2197 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2198 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2199 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2200 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2201 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2203 } // Constraints = "$src1 = $dst"
2205 //===---------------------------------------------------------------------===//
2206 // SSE2 - Packed Integer Logical Instructions
2207 //===---------------------------------------------------------------------===//
2209 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2210 defm VPSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "vpsllw",
2211 int_x86_sse2_psll_w, int_x86_sse2_pslli_w, 0>,
2213 defm VPSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "vpslld",
2214 int_x86_sse2_psll_d, int_x86_sse2_pslli_d, 0>,
2216 defm VPSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "vpsllq",
2217 int_x86_sse2_psll_q, int_x86_sse2_pslli_q, 0>,
2220 defm VPSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "vpsrlw",
2221 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w, 0>,
2223 defm VPSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "vpsrld",
2224 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d, 0>,
2226 defm VPSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "vpsrlq",
2227 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q, 0>,
2230 defm VPSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "vpsraw",
2231 int_x86_sse2_psra_w, int_x86_sse2_psrai_w, 0>,
2233 defm VPSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "vpsrad",
2234 int_x86_sse2_psra_d, int_x86_sse2_psrai_d, 0>,
2237 defm VPAND : PDI_binop_rm_v2i64<0xDB, "vpand", and, 1, 0>, VEX_4V;
2238 defm VPOR : PDI_binop_rm_v2i64<0xEB, "vpor" , or, 1, 0>, VEX_4V;
2239 defm VPXOR : PDI_binop_rm_v2i64<0xEF, "vpxor", xor, 1, 0>, VEX_4V;
2241 let ExeDomain = SSEPackedInt in {
2242 let neverHasSideEffects = 1 in {
2243 // 128-bit logical shifts.
2244 def VPSLLDQri : PDIi8<0x73, MRM7r,
2245 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2246 "vpslldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2248 def VPSRLDQri : PDIi8<0x73, MRM3r,
2249 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2250 "vpsrldq\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
2252 // PSRADQri doesn't exist in SSE[1-3].
2254 def VPANDNrr : PDI<0xDF, MRMSrcReg,
2255 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2256 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2257 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2258 VR128:$src2)))]>, VEX_4V;
2260 def VPANDNrm : PDI<0xDF, MRMSrcMem,
2261 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2262 "vpandn\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2263 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2264 (memopv2i64 addr:$src2))))]>,
2269 let Constraints = "$src1 = $dst" in {
2270 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2271 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2272 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2273 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2274 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2275 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2277 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2278 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2279 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2280 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2281 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2282 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2284 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2285 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2286 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2287 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2289 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2290 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or, 1>;
2291 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2293 let ExeDomain = SSEPackedInt in {
2294 let neverHasSideEffects = 1 in {
2295 // 128-bit logical shifts.
2296 def PSLLDQri : PDIi8<0x73, MRM7r,
2297 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2298 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2299 def PSRLDQri : PDIi8<0x73, MRM3r,
2300 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2301 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2302 // PSRADQri doesn't exist in SSE[1-3].
2304 def PANDNrr : PDI<0xDF, MRMSrcReg,
2305 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2306 "pandn\t{$src2, $dst|$dst, $src2}",
2307 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2310 def PANDNrm : PDI<0xDF, MRMSrcMem,
2311 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2312 "pandn\t{$src2, $dst|$dst, $src2}",
2313 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2314 (memopv2i64 addr:$src2))))]>;
2316 } // Constraints = "$src1 = $dst"
2318 let Predicates = [HasSSE2] in {
2319 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2320 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2321 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2322 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2323 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2324 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2325 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2326 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2327 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2328 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2330 // Shift up / down and insert zero's.
2331 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2332 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2333 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2334 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2337 //===---------------------------------------------------------------------===//
2338 // SSE2 - Packed Integer Comparison Instructions
2339 //===---------------------------------------------------------------------===//
2341 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2342 defm VPCMPEQB : PDI_binop_rm_int<0x74, "vpcmpeqb", int_x86_sse2_pcmpeq_b, 1,
2344 defm VPCMPEQW : PDI_binop_rm_int<0x75, "vpcmpeqw", int_x86_sse2_pcmpeq_w, 1,
2346 defm VPCMPEQD : PDI_binop_rm_int<0x76, "vpcmpeqd", int_x86_sse2_pcmpeq_d, 1,
2348 defm VPCMPGTB : PDI_binop_rm_int<0x64, "vpcmpgtb", int_x86_sse2_pcmpgt_b, 0,
2350 defm VPCMPGTW : PDI_binop_rm_int<0x65, "vpcmpgtw", int_x86_sse2_pcmpgt_w, 0,
2352 defm VPCMPGTD : PDI_binop_rm_int<0x66, "vpcmpgtd", int_x86_sse2_pcmpgt_d, 0,
2356 let Constraints = "$src1 = $dst" in {
2357 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b, 1>;
2358 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w, 1>;
2359 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d, 1>;
2360 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2361 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2362 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2363 } // Constraints = "$src1 = $dst"
2365 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2366 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2367 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2368 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2369 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2370 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2371 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2372 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2373 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2374 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2375 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2376 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2378 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2379 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2380 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2381 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2382 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2383 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2384 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2385 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2386 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2387 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2388 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2389 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2391 //===---------------------------------------------------------------------===//
2392 // SSE2 - Packed Integer Pack Instructions
2393 //===---------------------------------------------------------------------===//
2395 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2396 defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
2398 defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
2400 defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
2404 let Constraints = "$src1 = $dst" in {
2405 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2406 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2407 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2408 } // Constraints = "$src1 = $dst"
2410 //===---------------------------------------------------------------------===//
2411 // SSE2 - Packed Integer Shuffle Instructions
2412 //===---------------------------------------------------------------------===//
2414 let ExeDomain = SSEPackedInt in {
2415 multiclass sse2_pshuffle<string OpcodeStr, ValueType vt, PatFrag pshuf_frag,
2417 def ri : Ii8<0x70, MRMSrcReg,
2418 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2419 !strconcat(OpcodeStr,
2420 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2421 [(set VR128:$dst, (vt (pshuf_frag:$src2 VR128:$src1,
2423 def mi : Ii8<0x70, MRMSrcMem,
2424 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2425 !strconcat(OpcodeStr,
2426 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2427 [(set VR128:$dst, (vt (pshuf_frag:$src2
2428 (bc_frag (memopv2i64 addr:$src1)),
2431 } // ExeDomain = SSEPackedInt
2433 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2434 let AddedComplexity = 5 in
2435 defm VPSHUFD : sse2_pshuffle<"vpshufd", v4i32, pshufd, bc_v4i32>, OpSize,
2438 // SSE2 with ImmT == Imm8 and XS prefix.
2439 defm VPSHUFHW : sse2_pshuffle<"vpshufhw", v8i16, pshufhw, bc_v8i16>, XS,
2442 // SSE2 with ImmT == Imm8 and XD prefix.
2443 defm VPSHUFLW : sse2_pshuffle<"vpshuflw", v8i16, pshuflw, bc_v8i16>, XD,
2447 let Predicates = [HasSSE2] in {
2448 let AddedComplexity = 5 in
2449 defm PSHUFD : sse2_pshuffle<"pshufd", v4i32, pshufd, bc_v4i32>, TB, OpSize;
2451 // SSE2 with ImmT == Imm8 and XS prefix.
2452 defm PSHUFHW : sse2_pshuffle<"pshufhw", v8i16, pshufhw, bc_v8i16>, XS;
2454 // SSE2 with ImmT == Imm8 and XD prefix.
2455 defm PSHUFLW : sse2_pshuffle<"pshuflw", v8i16, pshuflw, bc_v8i16>, XD;
2458 //===---------------------------------------------------------------------===//
2459 // SSE2 - Packed Integer Unpack Instructions
2460 //===---------------------------------------------------------------------===//
2462 let ExeDomain = SSEPackedInt in {
2463 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2464 PatFrag unp_frag, PatFrag bc_frag, bit Is2Addr = 1> {
2465 def rr : PDI<opc, MRMSrcReg,
2466 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2468 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2469 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2470 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2471 def rm : PDI<opc, MRMSrcMem,
2472 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2474 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2475 !strconcat(OpcodeStr,"\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
2476 [(set VR128:$dst, (unp_frag VR128:$src1,
2477 (bc_frag (memopv2i64
2481 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2482 defm VPUNPCKLBW : sse2_unpack<0x60, "vpunpcklbw", v16i8, unpckl, bc_v16i8,
2484 defm VPUNPCKLWD : sse2_unpack<0x61, "vpunpcklwd", v8i16, unpckl, bc_v8i16,
2486 defm VPUNPCKLDQ : sse2_unpack<0x62, "vpunpckldq", v4i32, unpckl, bc_v4i32,
2489 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2490 /// knew to collapse (bitconvert VT to VT) into its operand.
2491 def VPUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2492 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2493 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2495 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>, VEX_4V;
2496 def VPUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2497 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2498 "vpunpcklqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2500 (v2i64 (unpckl VR128:$src1,
2501 (memopv2i64 addr:$src2))))]>, VEX_4V;
2503 defm VPUNPCKHBW : sse2_unpack<0x68, "vpunpckhbw", v16i8, unpckh, bc_v16i8,
2505 defm VPUNPCKHWD : sse2_unpack<0x69, "vpunpckhwd", v8i16, unpckh, bc_v8i16,
2507 defm VPUNPCKHDQ : sse2_unpack<0x6A, "vpunpckhdq", v4i32, unpckh, bc_v4i32,
2510 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2511 /// knew to collapse (bitconvert VT to VT) into its operand.
2512 def VPUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2513 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2514 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2516 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>, VEX_4V;
2517 def VPUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2518 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2519 "vpunpckhqdq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2521 (v2i64 (unpckh VR128:$src1,
2522 (memopv2i64 addr:$src2))))]>, VEX_4V;
2525 let Constraints = "$src1 = $dst" in {
2526 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2527 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2528 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2530 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2531 /// knew to collapse (bitconvert VT to VT) into its operand.
2532 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2533 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2534 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2536 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2537 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2538 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2539 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2541 (v2i64 (unpckl VR128:$src1,
2542 (memopv2i64 addr:$src2))))]>;
2544 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2545 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2546 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2548 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2549 /// knew to collapse (bitconvert VT to VT) into its operand.
2550 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2551 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2552 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2554 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2555 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2556 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2557 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2559 (v2i64 (unpckh VR128:$src1,
2560 (memopv2i64 addr:$src2))))]>;
2563 } // ExeDomain = SSEPackedInt
2565 //===---------------------------------------------------------------------===//
2566 // SSE2 - Packed Integer Extract and Insert
2567 //===---------------------------------------------------------------------===//
2569 let ExeDomain = SSEPackedInt in {
2570 multiclass sse2_pinsrw<bit Is2Addr = 1> {
2571 def rri : Ii8<0xC4, MRMSrcReg,
2572 (outs VR128:$dst), (ins VR128:$src1,
2573 GR32:$src2, i32i8imm:$src3),
2575 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2576 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2578 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2579 def rmi : Ii8<0xC4, MRMSrcMem,
2580 (outs VR128:$dst), (ins VR128:$src1,
2581 i16mem:$src2, i32i8imm:$src3),
2583 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2584 "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2586 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2591 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2592 def VPEXTRWri : Ii8<0xC5, MRMSrcReg,
2593 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2594 "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2595 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2596 imm:$src2))]>, OpSize, VEX;
2597 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2598 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2599 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2600 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2604 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2605 defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V;
2607 let Constraints = "$src1 = $dst" in
2608 defm VPINSRW : sse2_pinsrw, TB, OpSize;
2610 } // ExeDomain = SSEPackedInt
2612 //===---------------------------------------------------------------------===//
2613 // SSE2 - Packed Mask Creation
2614 //===---------------------------------------------------------------------===//
2616 let ExeDomain = SSEPackedInt in {
2618 let isAsmParserOnly = 1 in
2619 def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2620 "pmovmskb\t{$src, $dst|$dst, $src}",
2621 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>, VEX;
2622 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2623 "pmovmskb\t{$src, $dst|$dst, $src}",
2624 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2626 } // ExeDomain = SSEPackedInt
2628 //===---------------------------------------------------------------------===//
2629 // SSE2 - Conditional Store
2630 //===---------------------------------------------------------------------===//
2632 let ExeDomain = SSEPackedInt in {
2634 let isAsmParserOnly = 1 in {
2636 def VMASKMOVDQU : VPDI<0xF7, MRMSrcReg, (outs),
2637 (ins VR128:$src, VR128:$mask),
2638 "maskmovdqu\t{$mask, $src|$src, $mask}",
2639 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>, VEX;
2641 def VMASKMOVDQU64 : VPDI<0xF7, MRMSrcReg, (outs),
2642 (ins VR128:$src, VR128:$mask),
2643 "maskmovdqu\t{$mask, $src|$src, $mask}",
2644 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>, VEX;
2648 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2649 "maskmovdqu\t{$mask, $src|$src, $mask}",
2650 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2652 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2653 "maskmovdqu\t{$mask, $src|$src, $mask}",
2654 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2656 } // ExeDomain = SSEPackedInt
2658 //===---------------------------------------------------------------------===//
2659 // SSE2 - Move Doubleword
2660 //===---------------------------------------------------------------------===//
2662 // Move Int Doubleword to Packed Double Int
2663 let isAsmParserOnly = 1 in {
2664 def VMOVDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2665 "movd\t{$src, $dst|$dst, $src}",
2667 (v4i32 (scalar_to_vector GR32:$src)))]>, VEX;
2668 def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2669 "movd\t{$src, $dst|$dst, $src}",
2671 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
2674 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2675 "movd\t{$src, $dst|$dst, $src}",
2677 (v4i32 (scalar_to_vector GR32:$src)))]>;
2678 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2679 "movd\t{$src, $dst|$dst, $src}",
2681 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2684 // Move Int Doubleword to Single Scalar
2685 let isAsmParserOnly = 1 in {
2686 def VMOVDI2SSrr : VPDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2687 "movd\t{$src, $dst|$dst, $src}",
2688 [(set FR32:$dst, (bitconvert GR32:$src))]>, VEX;
2690 def VMOVDI2SSrm : VPDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2691 "movd\t{$src, $dst|$dst, $src}",
2692 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>,
2695 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2696 "movd\t{$src, $dst|$dst, $src}",
2697 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2699 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2700 "movd\t{$src, $dst|$dst, $src}",
2701 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2703 // Move Packed Doubleword Int to Packed Double Int
2704 let isAsmParserOnly = 1 in {
2705 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2706 "movd\t{$src, $dst|$dst, $src}",
2707 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2709 def VMOVPDI2DImr : VPDI<0x7E, MRMDestMem, (outs),
2710 (ins i32mem:$dst, VR128:$src),
2711 "movd\t{$src, $dst|$dst, $src}",
2712 [(store (i32 (vector_extract (v4i32 VR128:$src),
2713 (iPTR 0))), addr:$dst)]>, VEX;
2715 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2716 "movd\t{$src, $dst|$dst, $src}",
2717 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2719 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2720 "movd\t{$src, $dst|$dst, $src}",
2721 [(store (i32 (vector_extract (v4i32 VR128:$src),
2722 (iPTR 0))), addr:$dst)]>;
2724 // Move Scalar Single to Double Int
2725 let isAsmParserOnly = 1 in {
2726 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2727 "movd\t{$src, $dst|$dst, $src}",
2728 [(set GR32:$dst, (bitconvert FR32:$src))]>, VEX;
2729 def VMOVSS2DImr : VPDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2730 "movd\t{$src, $dst|$dst, $src}",
2731 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>, VEX;
2733 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2734 "movd\t{$src, $dst|$dst, $src}",
2735 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2736 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2737 "movd\t{$src, $dst|$dst, $src}",
2738 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2740 // movd / movq to XMM register zero-extends
2741 let AddedComplexity = 15, isAsmParserOnly = 1 in {
2742 def VMOVZDI2PDIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2743 "movd\t{$src, $dst|$dst, $src}",
2744 [(set VR128:$dst, (v4i32 (X86vzmovl
2745 (v4i32 (scalar_to_vector GR32:$src)))))]>,
2747 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2748 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2749 [(set VR128:$dst, (v2i64 (X86vzmovl
2750 (v2i64 (scalar_to_vector GR64:$src)))))]>,
2753 let AddedComplexity = 15 in {
2754 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2755 "movd\t{$src, $dst|$dst, $src}",
2756 [(set VR128:$dst, (v4i32 (X86vzmovl
2757 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2758 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2759 "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
2760 [(set VR128:$dst, (v2i64 (X86vzmovl
2761 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2764 let AddedComplexity = 20 in {
2765 let isAsmParserOnly = 1 in
2766 def VMOVZDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2767 "movd\t{$src, $dst|$dst, $src}",
2769 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2770 (loadi32 addr:$src))))))]>,
2772 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2773 "movd\t{$src, $dst|$dst, $src}",
2775 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2776 (loadi32 addr:$src))))))]>;
2778 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2779 (MOVZDI2PDIrm addr:$src)>;
2780 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2781 (MOVZDI2PDIrm addr:$src)>;
2782 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2783 (MOVZDI2PDIrm addr:$src)>;
2786 //===---------------------------------------------------------------------===//
2787 // SSE2 - Move Quadword
2788 //===---------------------------------------------------------------------===//
2790 // Move Quadword Int to Packed Quadword Int
2791 let isAsmParserOnly = 1 in
2792 def VMOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2793 "vmovq\t{$src, $dst|$dst, $src}",
2795 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2796 VEX, Requires<[HasAVX]>;
2797 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2798 "movq\t{$src, $dst|$dst, $src}",
2800 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2801 Requires<[HasSSE2]>; // SSE2 instruction with XS Prefix
2803 // Move Packed Quadword Int to Quadword Int
2804 let isAsmParserOnly = 1 in
2805 def VMOVPQI2QImr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2806 "movq\t{$src, $dst|$dst, $src}",
2807 [(store (i64 (vector_extract (v2i64 VR128:$src),
2808 (iPTR 0))), addr:$dst)]>, VEX;
2809 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2810 "movq\t{$src, $dst|$dst, $src}",
2811 [(store (i64 (vector_extract (v2i64 VR128:$src),
2812 (iPTR 0))), addr:$dst)]>;
2814 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2815 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2817 // Store / copy lower 64-bits of a XMM register.
2818 let isAsmParserOnly = 1 in
2819 def VMOVLQ128mr : VPDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2820 "movq\t{$src, $dst|$dst, $src}",
2821 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>, VEX;
2822 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2823 "movq\t{$src, $dst|$dst, $src}",
2824 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2826 let AddedComplexity = 20, isAsmParserOnly = 1 in
2827 def VMOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2828 "vmovq\t{$src, $dst|$dst, $src}",
2830 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2831 (loadi64 addr:$src))))))]>,
2832 XS, VEX, Requires<[HasAVX]>;
2834 let AddedComplexity = 20 in {
2835 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2836 "movq\t{$src, $dst|$dst, $src}",
2838 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2839 (loadi64 addr:$src))))))]>,
2840 XS, Requires<[HasSSE2]>;
2842 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2843 (MOVZQI2PQIrm addr:$src)>;
2844 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2845 (MOVZQI2PQIrm addr:$src)>;
2846 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2849 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2850 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2851 let isAsmParserOnly = 1, AddedComplexity = 15 in
2852 def VMOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2853 "vmovq\t{$src, $dst|$dst, $src}",
2854 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2855 XS, VEX, Requires<[HasAVX]>;
2856 let AddedComplexity = 15 in
2857 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2858 "movq\t{$src, $dst|$dst, $src}",
2859 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2860 XS, Requires<[HasSSE2]>;
2862 let AddedComplexity = 20, isAsmParserOnly = 1 in
2863 def VMOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2864 "vmovq\t{$src, $dst|$dst, $src}",
2865 [(set VR128:$dst, (v2i64 (X86vzmovl
2866 (loadv2i64 addr:$src))))]>,
2867 XS, VEX, Requires<[HasAVX]>;
2868 let AddedComplexity = 20 in {
2869 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2870 "movq\t{$src, $dst|$dst, $src}",
2871 [(set VR128:$dst, (v2i64 (X86vzmovl
2872 (loadv2i64 addr:$src))))]>,
2873 XS, Requires<[HasSSE2]>;
2875 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2876 (MOVZPQILo2PQIrm addr:$src)>;
2879 // Instructions to match in the assembler
2880 let isAsmParserOnly = 1 in {
2881 // This instructions is in fact an alias to movd with 64 bit dst
2882 def VMOVQs64rr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2883 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
2884 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2885 "movq\t{$src, $dst|$dst, $src}", []>, VEX, VEX_W;
2888 // Instructions for the disassembler
2889 // xr = XMM register
2892 let isAsmParserOnly = 1 in
2893 def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2894 "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS;
2895 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2896 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2898 //===---------------------------------------------------------------------===//
2899 // SSE2 - Misc Instructions
2900 //===---------------------------------------------------------------------===//
2903 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2904 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2905 TB, Requires<[HasSSE2]>;
2907 // Load, store, and memory fence
2908 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2909 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2910 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2911 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2913 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2914 // was introduced with SSE2, it's backward compatible.
2915 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2917 //TODO: custom lower this so as to never even generate the noop
2918 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2920 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2921 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2922 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2925 // Alias instructions that map zero vector to pxor / xorp* for sse.
2926 // We set canFoldAsLoad because this can be converted to a constant-pool
2927 // load of an all-ones value if folding it would be beneficial.
2928 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2929 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2930 // FIXME: Change encoding to pseudo.
2931 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2932 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2934 //===---------------------------------------------------------------------===//
2935 // SSE3 - Conversion Instructions
2936 //===---------------------------------------------------------------------===//
2938 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2939 def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2940 "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
2941 def VCVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2942 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2943 def VCVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2944 "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
2947 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2948 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2949 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2950 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
2951 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2952 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2953 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2954 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
2956 //===---------------------------------------------------------------------===//
2957 // SSE3 - Move Instructions
2958 //===---------------------------------------------------------------------===//
2960 // Replicate Single FP
2961 multiclass sse3_replicate_sfp<bits<8> op, PatFrag rep_frag, string OpcodeStr> {
2962 def rr : S3SI<op, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2963 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2964 [(set VR128:$dst, (v4f32 (rep_frag
2965 VR128:$src, (undef))))]>;
2966 def rm : S3SI<op, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2967 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2968 [(set VR128:$dst, (rep_frag
2969 (memopv4f32 addr:$src), (undef)))]>;
2972 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
2973 defm VMOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "vmovshdup">, VEX;
2974 defm VMOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "vmovsldup">, VEX;
2976 defm MOVSHDUP : sse3_replicate_sfp<0x16, movshdup, "movshdup">;
2977 defm MOVSLDUP : sse3_replicate_sfp<0x12, movsldup, "movsldup">;
2979 // Replicate Double FP
2980 multiclass sse3_replicate_dfp<string OpcodeStr> {
2981 def rr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2982 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2983 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2984 def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2985 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2987 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2991 let isAsmParserOnly = 1, Predicates = [HasAVX] in
2992 defm VMOVDDUP : sse3_replicate_dfp<"vmovddup">, VEX;
2993 defm MOVDDUP : sse3_replicate_dfp<"movddup">;
2995 // Move Unaligned Integer
2996 let isAsmParserOnly = 1 in
2997 def VLDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2998 "vlddqu\t{$src, $dst|$dst, $src}",
2999 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>, VEX;
3000 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3001 "lddqu\t{$src, $dst|$dst, $src}",
3002 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
3004 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
3006 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3008 // Several Move patterns
3009 let AddedComplexity = 5 in {
3010 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
3011 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3012 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
3013 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3014 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
3015 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3016 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
3017 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
3020 // vector_shuffle v1, <undef> <1, 1, 3, 3>
3021 let AddedComplexity = 15 in
3022 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
3023 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3024 let AddedComplexity = 20 in
3025 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3026 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
3028 // vector_shuffle v1, <undef> <0, 0, 2, 2>
3029 let AddedComplexity = 15 in
3030 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
3031 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
3032 let AddedComplexity = 20 in
3033 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
3034 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
3036 //===---------------------------------------------------------------------===//
3037 // SSE3 - Arithmetic
3038 //===---------------------------------------------------------------------===//
3040 multiclass sse3_addsub<Intrinsic Int, string OpcodeStr, bit Is2Addr = 1> {
3041 def rr : I<0xD0, MRMSrcReg,
3042 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3044 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3045 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3046 [(set VR128:$dst, (Int VR128:$src1,
3048 def rm : I<0xD0, MRMSrcMem,
3049 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3051 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3052 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3053 [(set VR128:$dst, (Int VR128:$src1,
3054 (memop addr:$src2)))]>;
3058 let isAsmParserOnly = 1, Predicates = [HasAVX],
3059 ExeDomain = SSEPackedDouble in {
3060 defm VADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "vaddsubps", 0>, XD,
3062 defm VADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "vaddsubpd", 0>, OpSize,
3065 let Constraints = "$src1 = $dst", Predicates = [HasSSE3],
3066 ExeDomain = SSEPackedDouble in {
3067 defm ADDSUBPS : sse3_addsub<int_x86_sse3_addsub_ps, "addsubps">, XD;
3068 defm ADDSUBPD : sse3_addsub<int_x86_sse3_addsub_pd, "addsubpd">, TB, OpSize;
3071 //===---------------------------------------------------------------------===//
3072 // SSE3 Instructions
3073 //===---------------------------------------------------------------------===//
3076 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3077 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3079 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3080 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3081 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
3082 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3083 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3085 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3086 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3087 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
3088 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3089 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
3091 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3092 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3093 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
3094 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId, bit Is2Addr = 1>
3095 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
3097 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3098 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3099 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
3101 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3102 def VHADDPSrr : S3D_Intrr<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
3103 def VHADDPSrm : S3D_Intrm<0x7C, "vhaddps", int_x86_sse3_hadd_ps, 0>, VEX_4V;
3104 def VHADDPDrr : S3_Intrr <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
3105 def VHADDPDrm : S3_Intrm <0x7C, "vhaddpd", int_x86_sse3_hadd_pd, 0>, VEX_4V;
3106 def VHSUBPSrr : S3D_Intrr<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
3107 def VHSUBPSrm : S3D_Intrm<0x7D, "vhsubps", int_x86_sse3_hsub_ps, 0>, VEX_4V;
3108 def VHSUBPDrr : S3_Intrr <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
3109 def VHSUBPDrm : S3_Intrm <0x7D, "vhsubpd", int_x86_sse3_hsub_pd, 0>, VEX_4V;
3112 let Constraints = "$src1 = $dst" in {
3113 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
3114 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
3115 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
3116 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
3117 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
3118 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
3119 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
3120 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
3123 //===---------------------------------------------------------------------===//
3124 // SSSE3 - Packed Absolute Instructions
3125 //===---------------------------------------------------------------------===//
3127 /// SS3I_unop_rm_int - Simple SSSE3 unary op whose type can be v*{i8,i16,i32}.
3128 multiclass SS3I_unop_rm_int<bits<8> opc, string OpcodeStr,
3129 PatFrag mem_frag64, PatFrag mem_frag128,
3130 Intrinsic IntId64, Intrinsic IntId128> {
3131 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
3132 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3133 [(set VR64:$dst, (IntId64 VR64:$src))]>;
3135 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
3136 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3138 (IntId64 (bitconvert (mem_frag64 addr:$src))))]>;
3140 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3142 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3143 [(set VR128:$dst, (IntId128 VR128:$src))]>,
3146 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3148 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3151 (bitconvert (mem_frag128 addr:$src))))]>, OpSize;
3154 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3155 defm VPABSB : SS3I_unop_rm_int<0x1C, "vpabsb", memopv8i8, memopv16i8,
3156 int_x86_ssse3_pabs_b,
3157 int_x86_ssse3_pabs_b_128>, VEX;
3158 defm VPABSW : SS3I_unop_rm_int<0x1D, "vpabsw", memopv4i16, memopv8i16,
3159 int_x86_ssse3_pabs_w,
3160 int_x86_ssse3_pabs_w_128>, VEX;
3161 defm VPABSD : SS3I_unop_rm_int<0x1E, "vpabsd", memopv2i32, memopv4i32,
3162 int_x86_ssse3_pabs_d,
3163 int_x86_ssse3_pabs_d_128>, VEX;
3166 defm PABSB : SS3I_unop_rm_int<0x1C, "pabsb", memopv8i8, memopv16i8,
3167 int_x86_ssse3_pabs_b,
3168 int_x86_ssse3_pabs_b_128>;
3169 defm PABSW : SS3I_unop_rm_int<0x1D, "pabsw", memopv4i16, memopv8i16,
3170 int_x86_ssse3_pabs_w,
3171 int_x86_ssse3_pabs_w_128>;
3172 defm PABSD : SS3I_unop_rm_int<0x1E, "pabsd", memopv2i32, memopv4i32,
3173 int_x86_ssse3_pabs_d,
3174 int_x86_ssse3_pabs_d_128>;
3176 //===---------------------------------------------------------------------===//
3177 // SSSE3 - Packed Binary Operator Instructions
3178 //===---------------------------------------------------------------------===//
3180 /// SS3I_binop_rm_int - Simple SSSE3 bin op whose type can be v*{i8,i16,i32}.
3181 multiclass SS3I_binop_rm_int<bits<8> opc, string OpcodeStr,
3182 PatFrag mem_frag64, PatFrag mem_frag128,
3183 Intrinsic IntId64, Intrinsic IntId128,
3185 let isCommutable = 1 in
3186 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
3187 (ins VR64:$src1, VR64:$src2),
3189 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3190 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3191 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]>;
3192 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
3193 (ins VR64:$src1, i64mem:$src2),
3195 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3196 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3198 (IntId64 VR64:$src1,
3199 (bitconvert (memopv8i8 addr:$src2))))]>;
3201 let isCommutable = 1 in
3202 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
3203 (ins VR128:$src1, VR128:$src2),
3205 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3206 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3207 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3209 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
3210 (ins VR128:$src1, i128mem:$src2),
3212 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3213 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
3215 (IntId128 VR128:$src1,
3216 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3219 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3220 let isCommutable = 0 in {
3221 defm VPHADDW : SS3I_binop_rm_int<0x01, "vphaddw", memopv4i16, memopv8i16,
3222 int_x86_ssse3_phadd_w,
3223 int_x86_ssse3_phadd_w_128, 0>, VEX_4V;
3224 defm VPHADDD : SS3I_binop_rm_int<0x02, "vphaddd", memopv2i32, memopv4i32,
3225 int_x86_ssse3_phadd_d,
3226 int_x86_ssse3_phadd_d_128, 0>, VEX_4V;
3227 defm VPHADDSW : SS3I_binop_rm_int<0x03, "vphaddsw", memopv4i16, memopv8i16,
3228 int_x86_ssse3_phadd_sw,
3229 int_x86_ssse3_phadd_sw_128, 0>, VEX_4V;
3230 defm VPHSUBW : SS3I_binop_rm_int<0x05, "vphsubw", memopv4i16, memopv8i16,
3231 int_x86_ssse3_phsub_w,
3232 int_x86_ssse3_phsub_w_128, 0>, VEX_4V;
3233 defm VPHSUBD : SS3I_binop_rm_int<0x06, "vphsubd", memopv2i32, memopv4i32,
3234 int_x86_ssse3_phsub_d,
3235 int_x86_ssse3_phsub_d_128, 0>, VEX_4V;
3236 defm VPHSUBSW : SS3I_binop_rm_int<0x07, "vphsubsw", memopv4i16, memopv8i16,
3237 int_x86_ssse3_phsub_sw,
3238 int_x86_ssse3_phsub_sw_128, 0>, VEX_4V;
3239 defm VPMADDUBSW : SS3I_binop_rm_int<0x04, "vpmaddubsw", memopv8i8, memopv16i8,
3240 int_x86_ssse3_pmadd_ub_sw,
3241 int_x86_ssse3_pmadd_ub_sw_128, 0>, VEX_4V;
3242 defm VPSHUFB : SS3I_binop_rm_int<0x00, "vpshufb", memopv8i8, memopv16i8,
3243 int_x86_ssse3_pshuf_b,
3244 int_x86_ssse3_pshuf_b_128, 0>, VEX_4V;
3245 defm VPSIGNB : SS3I_binop_rm_int<0x08, "vpsignb", memopv8i8, memopv16i8,
3246 int_x86_ssse3_psign_b,
3247 int_x86_ssse3_psign_b_128, 0>, VEX_4V;
3248 defm VPSIGNW : SS3I_binop_rm_int<0x09, "vpsignw", memopv4i16, memopv8i16,
3249 int_x86_ssse3_psign_w,
3250 int_x86_ssse3_psign_w_128, 0>, VEX_4V;
3251 defm VPSIGND : SS3I_binop_rm_int<0x0A, "vpsignd", memopv2i32, memopv4i32,
3252 int_x86_ssse3_psign_d,
3253 int_x86_ssse3_psign_d_128, 0>, VEX_4V;
3255 defm VPMULHRSW : SS3I_binop_rm_int<0x0B, "vpmulhrsw", memopv4i16, memopv8i16,
3256 int_x86_ssse3_pmul_hr_sw,
3257 int_x86_ssse3_pmul_hr_sw_128, 0>, VEX_4V;
3260 // None of these have i8 immediate fields.
3261 let ImmT = NoImm, Constraints = "$src1 = $dst" in {
3262 let isCommutable = 0 in {
3263 defm PHADDW : SS3I_binop_rm_int<0x01, "phaddw", memopv4i16, memopv8i16,
3264 int_x86_ssse3_phadd_w,
3265 int_x86_ssse3_phadd_w_128>;
3266 defm PHADDD : SS3I_binop_rm_int<0x02, "phaddd", memopv2i32, memopv4i32,
3267 int_x86_ssse3_phadd_d,
3268 int_x86_ssse3_phadd_d_128>;
3269 defm PHADDSW : SS3I_binop_rm_int<0x03, "phaddsw", memopv4i16, memopv8i16,
3270 int_x86_ssse3_phadd_sw,
3271 int_x86_ssse3_phadd_sw_128>;
3272 defm PHSUBW : SS3I_binop_rm_int<0x05, "phsubw", memopv4i16, memopv8i16,
3273 int_x86_ssse3_phsub_w,
3274 int_x86_ssse3_phsub_w_128>;
3275 defm PHSUBD : SS3I_binop_rm_int<0x06, "phsubd", memopv2i32, memopv4i32,
3276 int_x86_ssse3_phsub_d,
3277 int_x86_ssse3_phsub_d_128>;
3278 defm PHSUBSW : SS3I_binop_rm_int<0x07, "phsubsw", memopv4i16, memopv8i16,
3279 int_x86_ssse3_phsub_sw,
3280 int_x86_ssse3_phsub_sw_128>;
3281 defm PMADDUBSW : SS3I_binop_rm_int<0x04, "pmaddubsw", memopv8i8, memopv16i8,
3282 int_x86_ssse3_pmadd_ub_sw,
3283 int_x86_ssse3_pmadd_ub_sw_128>;
3284 defm PSHUFB : SS3I_binop_rm_int<0x00, "pshufb", memopv8i8, memopv16i8,
3285 int_x86_ssse3_pshuf_b,
3286 int_x86_ssse3_pshuf_b_128>;
3287 defm PSIGNB : SS3I_binop_rm_int<0x08, "psignb", memopv8i8, memopv16i8,
3288 int_x86_ssse3_psign_b,
3289 int_x86_ssse3_psign_b_128>;
3290 defm PSIGNW : SS3I_binop_rm_int<0x09, "psignw", memopv4i16, memopv8i16,
3291 int_x86_ssse3_psign_w,
3292 int_x86_ssse3_psign_w_128>;
3293 defm PSIGND : SS3I_binop_rm_int<0x0A, "psignd", memopv2i32, memopv4i32,
3294 int_x86_ssse3_psign_d,
3295 int_x86_ssse3_psign_d_128>;
3297 defm PMULHRSW : SS3I_binop_rm_int<0x0B, "pmulhrsw", memopv4i16, memopv8i16,
3298 int_x86_ssse3_pmul_hr_sw,
3299 int_x86_ssse3_pmul_hr_sw_128>;
3302 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
3303 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
3304 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
3305 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
3307 //===---------------------------------------------------------------------===//
3308 // SSSE3 - Packed Align Instruction Patterns
3309 //===---------------------------------------------------------------------===//
3311 multiclass sse3_palign<string asm, bit Is2Addr = 1> {
3312 def R64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
3313 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
3315 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3317 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3319 def R64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
3320 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
3322 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3324 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3327 def R128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
3328 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3330 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3332 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3334 def R128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
3335 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3337 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3339 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3343 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3344 defm VPALIGN : sse3_palign<"vpalignr", 0>, VEX_4V;
3345 let Constraints = "$src1 = $dst" in
3346 defm PALIGN : sse3_palign<"palignr">;
3348 let AddedComplexity = 5 in {
3350 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
3351 (PALIGNR64rr VR64:$src2, VR64:$src1,
3352 (SHUFFLE_get_palign_imm VR64:$src3))>,
3353 Requires<[HasSSSE3]>;
3354 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
3355 (PALIGNR64rr VR64:$src2, VR64:$src1,
3356 (SHUFFLE_get_palign_imm VR64:$src3))>,
3357 Requires<[HasSSSE3]>;
3358 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
3359 (PALIGNR64rr VR64:$src2, VR64:$src1,
3360 (SHUFFLE_get_palign_imm VR64:$src3))>,
3361 Requires<[HasSSSE3]>;
3362 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
3363 (PALIGNR64rr VR64:$src2, VR64:$src1,
3364 (SHUFFLE_get_palign_imm VR64:$src3))>,
3365 Requires<[HasSSSE3]>;
3367 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
3368 (PALIGNR128rr VR128:$src2, VR128:$src1,
3369 (SHUFFLE_get_palign_imm VR128:$src3))>,
3370 Requires<[HasSSSE3]>;
3371 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
3372 (PALIGNR128rr VR128:$src2, VR128:$src1,
3373 (SHUFFLE_get_palign_imm VR128:$src3))>,
3374 Requires<[HasSSSE3]>;
3375 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
3376 (PALIGNR128rr VR128:$src2, VR128:$src1,
3377 (SHUFFLE_get_palign_imm VR128:$src3))>,
3378 Requires<[HasSSSE3]>;
3379 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
3380 (PALIGNR128rr VR128:$src2, VR128:$src1,
3381 (SHUFFLE_get_palign_imm VR128:$src3))>,
3382 Requires<[HasSSSE3]>;
3385 //===---------------------------------------------------------------------===//
3386 // SSSE3 Misc Instructions
3387 //===---------------------------------------------------------------------===//
3389 // Thread synchronization
3390 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
3391 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
3392 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
3393 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
3395 //===---------------------------------------------------------------------===//
3396 // Non-Instruction Patterns
3397 //===---------------------------------------------------------------------===//
3399 // extload f32 -> f64. This matches load+fextend because we have a hack in
3400 // the isel (PreprocessForFPConvert) that can introduce loads after dag
3402 // Since these loads aren't folded into the fextend, we have to match it
3404 let Predicates = [HasSSE2] in
3405 def : Pat<(fextend (loadf32 addr:$src)),
3406 (CVTSS2SDrm addr:$src)>;
3409 let Predicates = [HasSSE2] in {
3410 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
3411 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
3412 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
3413 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
3414 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
3415 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
3416 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
3417 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
3418 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
3419 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
3420 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
3421 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
3422 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
3423 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
3424 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
3425 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
3426 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
3427 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
3428 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
3429 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
3430 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
3431 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
3432 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
3433 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
3434 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
3435 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
3436 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
3437 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
3438 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
3439 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
3442 // Move scalar to XMM zero-extended
3443 // movd to XMM register zero-extends
3444 let AddedComplexity = 15 in {
3445 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
3446 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
3447 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
3448 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
3449 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
3450 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
3451 (MOVSSrr (v4f32 (V_SET0PS)),
3452 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
3453 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
3454 (MOVSSrr (v4i32 (V_SET0PI)),
3455 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
3458 // Splat v2f64 / v2i64
3459 let AddedComplexity = 10 in {
3460 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
3461 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3462 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
3463 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3464 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
3465 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3466 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
3467 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
3470 // Special unary SHUFPSrri case.
3471 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
3472 (SHUFPSrri VR128:$src1, VR128:$src1,
3473 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3474 let AddedComplexity = 5 in
3475 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
3476 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3477 Requires<[HasSSE2]>;
3478 // Special unary SHUFPDrri case.
3479 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
3480 (SHUFPDrri VR128:$src1, VR128:$src1,
3481 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3482 Requires<[HasSSE2]>;
3483 // Special unary SHUFPDrri case.
3484 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
3485 (SHUFPDrri VR128:$src1, VR128:$src1,
3486 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3487 Requires<[HasSSE2]>;
3488 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
3489 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
3490 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3491 Requires<[HasSSE2]>;
3493 // Special binary v4i32 shuffle cases with SHUFPS.
3494 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
3495 (SHUFPSrri VR128:$src1, VR128:$src2,
3496 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3497 Requires<[HasSSE2]>;
3498 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
3499 (SHUFPSrmi VR128:$src1, addr:$src2,
3500 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3501 Requires<[HasSSE2]>;
3502 // Special binary v2i64 shuffle cases using SHUFPDrri.
3503 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
3504 (SHUFPDrri VR128:$src1, VR128:$src2,
3505 (SHUFFLE_get_shuf_imm VR128:$src3))>,
3506 Requires<[HasSSE2]>;
3508 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3509 let AddedComplexity = 15 in {
3510 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3511 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3512 Requires<[OptForSpeed, HasSSE2]>;
3513 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3514 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3515 Requires<[OptForSpeed, HasSSE2]>;
3517 let AddedComplexity = 10 in {
3518 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3519 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3520 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3521 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3522 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3523 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3524 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3525 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3528 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3529 let AddedComplexity = 15 in {
3530 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3531 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3532 Requires<[OptForSpeed, HasSSE2]>;
3533 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3534 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3535 Requires<[OptForSpeed, HasSSE2]>;
3537 let AddedComplexity = 10 in {
3538 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3539 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3540 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3541 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3542 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3543 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3544 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3545 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3548 let AddedComplexity = 20 in {
3549 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3550 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3551 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3553 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3554 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3555 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3557 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3558 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3559 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3560 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3561 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3564 let AddedComplexity = 20 in {
3565 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3566 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3567 (MOVLPSrm VR128:$src1, addr:$src2)>;
3568 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3569 (MOVLPDrm VR128:$src1, addr:$src2)>;
3570 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3571 (MOVLPSrm VR128:$src1, addr:$src2)>;
3572 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3573 (MOVLPDrm VR128:$src1, addr:$src2)>;
3576 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3577 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3578 (MOVLPSmr addr:$src1, VR128:$src2)>;
3579 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3580 (MOVLPDmr addr:$src1, VR128:$src2)>;
3581 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3583 (MOVLPSmr addr:$src1, VR128:$src2)>;
3584 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3585 (MOVLPDmr addr:$src1, VR128:$src2)>;
3587 let AddedComplexity = 15 in {
3588 // Setting the lowest element in the vector.
3589 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3590 (MOVSSrr (v4i32 VR128:$src1),
3591 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3592 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3593 (MOVSDrr (v2i64 VR128:$src1),
3594 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3596 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3597 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3598 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3599 Requires<[HasSSE2]>;
3600 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3601 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3602 Requires<[HasSSE2]>;
3605 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3606 // fall back to this for SSE1)
3607 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3608 (SHUFPSrri VR128:$src2, VR128:$src1,
3609 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3611 // Set lowest element and zero upper elements.
3612 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3613 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3615 // Some special case pandn patterns.
3616 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3618 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3619 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3621 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3622 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3624 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3626 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3627 (memop addr:$src2))),
3628 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3629 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3630 (memop addr:$src2))),
3631 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3632 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3633 (memop addr:$src2))),
3634 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3636 // vector -> vector casts
3637 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3638 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3639 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3640 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3641 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3642 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3643 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3644 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3646 // Use movaps / movups for SSE integer load / store (one byte shorter).
3647 def : Pat<(alignedloadv4i32 addr:$src),
3648 (MOVAPSrm addr:$src)>;
3649 def : Pat<(loadv4i32 addr:$src),
3650 (MOVUPSrm addr:$src)>;
3651 def : Pat<(alignedloadv2i64 addr:$src),
3652 (MOVAPSrm addr:$src)>;
3653 def : Pat<(loadv2i64 addr:$src),
3654 (MOVUPSrm addr:$src)>;
3656 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3657 (MOVAPSmr addr:$dst, VR128:$src)>;
3658 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3659 (MOVAPSmr addr:$dst, VR128:$src)>;
3660 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3661 (MOVAPSmr addr:$dst, VR128:$src)>;
3662 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3663 (MOVAPSmr addr:$dst, VR128:$src)>;
3664 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3665 (MOVUPSmr addr:$dst, VR128:$src)>;
3666 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3667 (MOVUPSmr addr:$dst, VR128:$src)>;
3668 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3669 (MOVUPSmr addr:$dst, VR128:$src)>;
3670 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3671 (MOVUPSmr addr:$dst, VR128:$src)>;
3673 //===----------------------------------------------------------------------===//
3674 // SSE4.1 - Packed Move with Sign/Zero Extend
3675 //===----------------------------------------------------------------------===//
3677 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3678 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3679 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3680 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3682 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3683 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3685 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3689 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3690 defm VPMOVSXBW : SS41I_binop_rm_int8<0x20, "vpmovsxbw", int_x86_sse41_pmovsxbw>,
3692 defm VPMOVSXWD : SS41I_binop_rm_int8<0x23, "vpmovsxwd", int_x86_sse41_pmovsxwd>,
3694 defm VPMOVSXDQ : SS41I_binop_rm_int8<0x25, "vpmovsxdq", int_x86_sse41_pmovsxdq>,
3696 defm VPMOVZXBW : SS41I_binop_rm_int8<0x30, "vpmovzxbw", int_x86_sse41_pmovzxbw>,
3698 defm VPMOVZXWD : SS41I_binop_rm_int8<0x33, "vpmovzxwd", int_x86_sse41_pmovzxwd>,
3700 defm VPMOVZXDQ : SS41I_binop_rm_int8<0x35, "vpmovzxdq", int_x86_sse41_pmovzxdq>,
3704 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3705 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3706 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3707 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3708 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3709 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3711 // Common patterns involving scalar load.
3712 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3713 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3714 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3715 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3717 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3718 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3719 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3720 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3722 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3723 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3724 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3725 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3727 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3728 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3729 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3730 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3732 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3733 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3734 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3735 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3737 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3738 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3739 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3740 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3743 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3744 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3745 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3746 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3748 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3749 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3751 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3755 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3756 defm VPMOVSXBD : SS41I_binop_rm_int4<0x21, "vpmovsxbd", int_x86_sse41_pmovsxbd>,
3758 defm VPMOVSXWQ : SS41I_binop_rm_int4<0x24, "vpmovsxwq", int_x86_sse41_pmovsxwq>,
3760 defm VPMOVZXBD : SS41I_binop_rm_int4<0x31, "vpmovzxbd", int_x86_sse41_pmovzxbd>,
3762 defm VPMOVZXWQ : SS41I_binop_rm_int4<0x34, "vpmovzxwq", int_x86_sse41_pmovzxwq>,
3766 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3767 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3768 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3769 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3771 // Common patterns involving scalar load
3772 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3773 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3774 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3775 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3777 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3778 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3779 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3780 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3783 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3784 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3785 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3786 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3788 // Expecting a i16 load any extended to i32 value.
3789 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3790 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3791 [(set VR128:$dst, (IntId (bitconvert
3792 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3796 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
3797 defm VPMOVSXBQ : SS41I_binop_rm_int2<0x22, "vpmovsxbq", int_x86_sse41_pmovsxbq>,
3799 defm VPMOVZXBQ : SS41I_binop_rm_int2<0x32, "vpmovzxbq", int_x86_sse41_pmovzxbq>,
3802 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3803 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3805 // Common patterns involving scalar load
3806 def : Pat<(int_x86_sse41_pmovsxbq
3807 (bitconvert (v4i32 (X86vzmovl
3808 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3809 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3811 def : Pat<(int_x86_sse41_pmovzxbq
3812 (bitconvert (v4i32 (X86vzmovl
3813 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3814 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3816 //===----------------------------------------------------------------------===//
3817 // SSE4.1 - Extract Instructions
3818 //===----------------------------------------------------------------------===//
3820 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3821 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3822 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3823 (ins VR128:$src1, i32i8imm:$src2),
3824 !strconcat(OpcodeStr,
3825 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3826 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3828 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3829 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3830 !strconcat(OpcodeStr,
3831 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3834 // There's an AssertZext in the way of writing the store pattern
3835 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3838 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3839 defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;
3841 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3844 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3845 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3846 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3847 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3848 !strconcat(OpcodeStr,
3849 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3852 // There's an AssertZext in the way of writing the store pattern
3853 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3856 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3857 defm VPEXTRW : SS41I_extract16<0x15, "vpextrw">, VEX;
3859 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3862 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3863 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3864 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3865 (ins VR128:$src1, i32i8imm:$src2),
3866 !strconcat(OpcodeStr,
3867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3869 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3870 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3871 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3872 !strconcat(OpcodeStr,
3873 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3874 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3875 addr:$dst)]>, OpSize;
3878 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3879 defm VPEXTRD : SS41I_extract32<0x16, "vpextrd">, VEX;
3881 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3883 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3884 multiclass SS41I_extract64<bits<8> opc, string OpcodeStr> {
3885 def rr : SS4AIi8<opc, MRMDestReg, (outs GR64:$dst),
3886 (ins VR128:$src1, i32i8imm:$src2),
3887 !strconcat(OpcodeStr,
3888 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3890 (extractelt (v2i64 VR128:$src1), imm:$src2))]>, OpSize, REX_W;
3891 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3892 (ins i64mem:$dst, VR128:$src1, i32i8imm:$src2),
3893 !strconcat(OpcodeStr,
3894 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3895 [(store (extractelt (v2i64 VR128:$src1), imm:$src2),
3896 addr:$dst)]>, OpSize, REX_W;
3899 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3900 defm VPEXTRQ : SS41I_extract64<0x16, "vpextrq">, VEX, VEX_W;
3902 defm PEXTRQ : SS41I_extract64<0x16, "pextrq">;
3904 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3906 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3907 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3908 (ins VR128:$src1, i32i8imm:$src2),
3909 !strconcat(OpcodeStr,
3910 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3912 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3914 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3915 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3916 !strconcat(OpcodeStr,
3917 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3918 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3919 addr:$dst)]>, OpSize;
3922 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3923 defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;
3924 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3926 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3927 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3930 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3931 Requires<[HasSSE41]>;
3933 //===----------------------------------------------------------------------===//
3934 // SSE4.1 - Insert Instructions
3935 //===----------------------------------------------------------------------===//
3937 multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {
3938 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3939 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3941 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3943 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3945 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3946 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3947 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3949 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3951 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3953 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3954 imm:$src3))]>, OpSize;
3957 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3958 defm VPINSRB : SS41I_insert8<0x20, "vpinsrb", 0>, VEX_4V;
3959 let Constraints = "$src1 = $dst" in
3960 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3962 multiclass SS41I_insert32<bits<8> opc, string asm, bit Is2Addr = 1> {
3963 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3964 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3966 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3968 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3970 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3972 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3973 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3975 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3977 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3979 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3980 imm:$src3)))]>, OpSize;
3983 let isAsmParserOnly = 1, Predicates = [HasAVX] in
3984 defm VPINSRD : SS41I_insert32<0x22, "vpinsrd", 0>, VEX_4V;
3985 let Constraints = "$src1 = $dst" in
3986 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3988 multiclass SS41I_insert64<bits<8> opc, string asm, bit Is2Addr = 1> {
3989 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3990 (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),
3992 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3994 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
3996 (v2i64 (insertelt VR128:$src1, GR64:$src2, imm:$src3)))]>,
3998 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3999 (ins VR128:$src1, i64mem:$src2, i32i8imm:$src3),
4001 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4003 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4005 (v2i64 (insertelt VR128:$src1, (loadi64 addr:$src2),
4006 imm:$src3)))]>, OpSize;
4009 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4010 defm VPINSRQ : SS41I_insert64<0x22, "vpinsrq", 0>, VEX_4V, VEX_W;
4011 let Constraints = "$src1 = $dst" in
4012 defm PINSRQ : SS41I_insert64<0x22, "pinsrq">, REX_W;
4014 // insertps has a few different modes, there's the first two here below which
4015 // are optimized inserts that won't zero arbitrary elements in the destination
4016 // vector. The next one matches the intrinsic and could zero arbitrary elements
4017 // in the target vector.
4018 multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
4019 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4020 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4022 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4024 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4026 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
4028 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4029 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
4031 !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4033 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4035 (X86insrtps VR128:$src1,
4036 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
4037 imm:$src3))]>, OpSize;
4040 let Constraints = "$src1 = $dst" in
4041 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
4042 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4043 defm VINSERTPS : SS41I_insertf32<0x21, "vinsertps", 0>, VEX_4V;
4045 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
4046 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
4048 //===----------------------------------------------------------------------===//
4049 // SSE4.1 - Round Instructions
4050 //===----------------------------------------------------------------------===//
4052 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
4055 Intrinsic V2F64Int> {
4056 // Intrinsic operation, reg.
4057 // Vector intrinsic operation, reg
4058 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
4059 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4060 !strconcat(OpcodeStr,
4061 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4062 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
4065 // Vector intrinsic operation, mem
4066 def PSm_Int : Ii8<opcps, MRMSrcMem,
4067 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4068 !strconcat(OpcodeStr,
4069 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4071 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
4073 Requires<[HasSSE41]>;
4075 // Vector intrinsic operation, reg
4076 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
4077 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4078 !strconcat(OpcodeStr,
4079 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4080 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
4083 // Vector intrinsic operation, mem
4084 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
4085 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4086 !strconcat(OpcodeStr,
4087 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4089 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
4093 multiclass sse41_fp_unop_rm_avx<bits<8> opcps, bits<8> opcpd,
4095 // Intrinsic operation, reg.
4096 // Vector intrinsic operation, reg
4097 def PSr : SS4AIi8<opcps, MRMSrcReg,
4098 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4099 !strconcat(OpcodeStr,
4100 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4103 // Vector intrinsic operation, mem
4104 def PSm : Ii8<opcps, MRMSrcMem,
4105 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4106 !strconcat(OpcodeStr,
4107 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4108 []>, TA, OpSize, Requires<[HasSSE41]>;
4110 // Vector intrinsic operation, reg
4111 def PDr : SS4AIi8<opcpd, MRMSrcReg,
4112 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
4113 !strconcat(OpcodeStr,
4114 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4117 // Vector intrinsic operation, mem
4118 def PDm : SS4AIi8<opcpd, MRMSrcMem,
4119 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
4120 !strconcat(OpcodeStr,
4121 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4125 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4128 Intrinsic F64Int, bit Is2Addr = 1> {
4129 // Intrinsic operation, reg.
4130 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
4131 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4133 !strconcat(OpcodeStr,
4134 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4135 !strconcat(OpcodeStr,
4136 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4137 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4140 // Intrinsic operation, mem.
4141 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
4142 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4144 !strconcat(OpcodeStr,
4145 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4146 !strconcat(OpcodeStr,
4147 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4149 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
4152 // Intrinsic operation, reg.
4153 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
4154 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4156 !strconcat(OpcodeStr,
4157 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4158 !strconcat(OpcodeStr,
4159 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4160 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
4163 // Intrinsic operation, mem.
4164 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
4165 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4167 !strconcat(OpcodeStr,
4168 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4169 !strconcat(OpcodeStr,
4170 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4172 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
4176 multiclass sse41_fp_binop_rm_avx<bits<8> opcss, bits<8> opcsd,
4178 // Intrinsic operation, reg.
4179 def SSr : SS4AIi8<opcss, MRMSrcReg,
4180 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4181 !strconcat(OpcodeStr,
4182 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4185 // Intrinsic operation, mem.
4186 def SSm : SS4AIi8<opcss, MRMSrcMem,
4187 (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
4188 !strconcat(OpcodeStr,
4189 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4192 // Intrinsic operation, reg.
4193 def SDr : SS4AIi8<opcsd, MRMSrcReg,
4194 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4195 !strconcat(OpcodeStr,
4196 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4199 // Intrinsic operation, mem.
4200 def SDm : SS4AIi8<opcsd, MRMSrcMem,
4201 (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
4202 !strconcat(OpcodeStr,
4203 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4207 // FP round - roundss, roundps, roundsd, roundpd
4208 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4210 defm VROUND : sse41_fp_unop_rm<0x08, 0x09, "vround",
4211 int_x86_sse41_round_ps, int_x86_sse41_round_pd>,
4213 defm VROUND : sse41_fp_binop_rm<0x0A, 0x0B, "vround",
4214 int_x86_sse41_round_ss, int_x86_sse41_round_sd,
4216 // Instructions for the assembler
4217 defm VROUND : sse41_fp_unop_rm_avx<0x08, 0x09, "vround">, VEX;
4218 defm VROUND : sse41_fp_binop_rm_avx<0x0A, 0x0B, "vround">, VEX_4V;
4221 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
4222 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
4223 let Constraints = "$src1 = $dst" in
4224 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
4225 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
4227 //===----------------------------------------------------------------------===//
4228 // SSE4.1 - Misc Instructions
4229 //===----------------------------------------------------------------------===//
4231 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
4232 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
4233 Intrinsic IntId128> {
4234 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4236 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4237 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
4238 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4240 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
4243 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
4246 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4247 defm VPHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "vphminposuw",
4248 int_x86_sse41_phminposuw>, VEX;
4249 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
4250 int_x86_sse41_phminposuw>;
4252 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
4253 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
4254 Intrinsic IntId128, bit Is2Addr = 1> {
4255 let isCommutable = 1 in
4256 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4257 (ins VR128:$src1, VR128:$src2),
4259 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4260 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4261 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
4262 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4263 (ins VR128:$src1, i128mem:$src2),
4265 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4266 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4268 (IntId128 VR128:$src1,
4269 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4272 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4273 let isCommutable = 0 in
4274 defm VPACKUSDW : SS41I_binop_rm_int<0x2B, "vpackusdw", int_x86_sse41_packusdw,
4276 defm VPCMPEQQ : SS41I_binop_rm_int<0x29, "vpcmpeqq", int_x86_sse41_pcmpeqq,
4278 defm VPMINSB : SS41I_binop_rm_int<0x38, "vpminsb", int_x86_sse41_pminsb,
4280 defm VPMINSD : SS41I_binop_rm_int<0x39, "vpminsd", int_x86_sse41_pminsd,
4282 defm VPMINUD : SS41I_binop_rm_int<0x3B, "vpminud", int_x86_sse41_pminud,
4284 defm VPMINUW : SS41I_binop_rm_int<0x3A, "vpminuw", int_x86_sse41_pminuw,
4286 defm VPMAXSB : SS41I_binop_rm_int<0x3C, "vpmaxsb", int_x86_sse41_pmaxsb,
4288 defm VPMAXSD : SS41I_binop_rm_int<0x3D, "vpmaxsd", int_x86_sse41_pmaxsd,
4290 defm VPMAXUD : SS41I_binop_rm_int<0x3F, "vpmaxud", int_x86_sse41_pmaxud,
4292 defm VPMAXUW : SS41I_binop_rm_int<0x3E, "vpmaxuw", int_x86_sse41_pmaxuw,
4294 defm VPMULDQ : SS41I_binop_rm_int<0x28, "vpmuldq", int_x86_sse41_pmuldq,
4298 let Constraints = "$src1 = $dst" in {
4299 let isCommutable = 0 in
4300 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
4301 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
4302 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
4303 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
4304 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
4305 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
4306 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
4307 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
4308 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
4309 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
4310 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
4313 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
4314 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
4315 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
4316 (PCMPEQQrm VR128:$src1, addr:$src2)>;
4318 /// SS48I_binop_rm - Simple SSE41 binary operator.
4319 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
4320 ValueType OpVT, bit Is2Addr = 1> {
4321 let isCommutable = 1 in
4322 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4323 (ins VR128:$src1, VR128:$src2),
4325 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4326 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4327 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
4329 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4330 (ins VR128:$src1, i128mem:$src2),
4332 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4333 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4334 [(set VR128:$dst, (OpNode VR128:$src1,
4335 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
4339 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4340 defm VPMULLD : SS48I_binop_rm<0x40, "vpmulld", mul, v4i32, 0>, VEX_4V;
4341 let Constraints = "$src1 = $dst" in
4342 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
4344 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
4345 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
4346 Intrinsic IntId128, bit Is2Addr = 1> {
4347 let isCommutable = 1 in
4348 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
4349 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
4351 !strconcat(OpcodeStr,
4352 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4353 !strconcat(OpcodeStr,
4354 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4356 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
4358 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
4359 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
4361 !strconcat(OpcodeStr,
4362 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
4363 !strconcat(OpcodeStr,
4364 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
4366 (IntId128 VR128:$src1,
4367 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
4371 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4372 let isCommutable = 0 in {
4373 defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,
4375 defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,
4377 defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,
4379 defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,
4382 defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,
4384 defm VDPPD : SS41I_binop_rmi_int<0x41, "vdppd", int_x86_sse41_dppd,
4388 let Constraints = "$src1 = $dst" in {
4389 let isCommutable = 0 in {
4390 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;
4391 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd>;
4392 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw>;
4393 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw>;
4395 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps>;
4396 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
4399 /// SS41I_quaternary_int_avx - AVX SSE 4.1 with 4 operators
4400 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4401 multiclass SS41I_quaternary_int_avx<bits<8> opc, string OpcodeStr> {
4402 def rr : I<opc, MRMSrcReg, (outs VR128:$dst),
4403 (ins VR128:$src1, VR128:$src2, VR128:$src3),
4404 !strconcat(OpcodeStr,
4405 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4406 [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4408 def rm : I<opc, MRMSrcMem, (outs VR128:$dst),
4409 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
4410 !strconcat(OpcodeStr,
4411 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4412 [], SSEPackedInt>, OpSize, TA, VEX_4V, VEX_I8IMM;
4416 defm VBLENDVPD : SS41I_quaternary_int_avx<0x4B, "vblendvpd">;
4417 defm VBLENDVPS : SS41I_quaternary_int_avx<0x4A, "vblendvps">;
4418 defm VPBLENDVB : SS41I_quaternary_int_avx<0x4C, "vpblendvb">;
4420 /// SS41I_ternary_int - SSE 4.1 ternary operator
4421 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
4422 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
4423 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
4424 (ins VR128:$src1, VR128:$src2),
4425 !strconcat(OpcodeStr,
4426 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4427 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
4430 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
4431 (ins VR128:$src1, i128mem:$src2),
4432 !strconcat(OpcodeStr,
4433 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
4436 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
4440 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
4441 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
4442 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
4444 // ptest instruction we'll lower to this in X86ISelLowering primarily from
4445 // the intel intrinsic that corresponds to this.
4446 let Defs = [EFLAGS], isAsmParserOnly = 1, Predicates = [HasAVX] in {
4447 def VPTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4448 "vptest\t{$src2, $src1|$src1, $src2}",
4449 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4451 def VPTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4452 "vptest\t{$src2, $src1|$src1, $src2}",
4453 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4457 let Defs = [EFLAGS] in {
4458 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
4459 "ptest \t{$src2, $src1|$src1, $src2}",
4460 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
4462 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
4463 "ptest \t{$src2, $src1|$src1, $src2}",
4464 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
4468 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4469 def VMOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4470 "vmovntdqa\t{$src, $dst|$dst, $src}",
4471 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4473 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
4474 "movntdqa\t{$src, $dst|$dst, $src}",
4475 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
4478 //===----------------------------------------------------------------------===//
4479 // SSE4.2 - Compare Instructions
4480 //===----------------------------------------------------------------------===//
4482 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
4483 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
4484 Intrinsic IntId128, bit Is2Addr = 1> {
4485 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
4486 (ins VR128:$src1, VR128:$src2),
4488 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4489 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4490 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4492 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
4493 (ins VR128:$src1, i128mem:$src2),
4495 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4496 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4498 (IntId128 VR128:$src1,
4499 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4502 let isAsmParserOnly = 1, Predicates = [HasAVX] in
4503 defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
4505 let Constraints = "$src1 = $dst" in
4506 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
4508 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
4509 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
4510 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
4511 (PCMPGTQrm VR128:$src1, addr:$src2)>;
4513 //===----------------------------------------------------------------------===//
4514 // SSE4.2 - String/text Processing Instructions
4515 //===----------------------------------------------------------------------===//
4517 // Packed Compare Implicit Length Strings, Return Mask
4518 let Defs = [EFLAGS], usesCustomInserter = 1 in {
4519 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4520 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4521 "#PCMPISTRM128rr PSEUDO!",
4522 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
4523 imm:$src3))]>, OpSize;
4524 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4525 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4526 "#PCMPISTRM128rm PSEUDO!",
4527 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128
4528 VR128:$src1, (load addr:$src2), imm:$src3))]>, OpSize;
4531 let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
4532 Predicates = [HasAVX] in {
4533 def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4534 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4535 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4536 def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4537 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4538 "vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
4541 let Defs = [XMM0, EFLAGS] in {
4542 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
4543 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4544 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4545 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
4546 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4547 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
4550 // Packed Compare Explicit Length Strings, Return Mask
4551 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
4552 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
4553 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4554 "#PCMPESTRM128rr PSEUDO!",
4556 (int_x86_sse42_pcmpestrm128
4557 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
4559 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
4560 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4561 "#PCMPESTRM128rm PSEUDO!",
4562 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
4563 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
4567 let isAsmParserOnly = 1, Predicates = [HasAVX],
4568 Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4569 def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4570 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4571 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4572 def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4573 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4574 "vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
4577 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
4578 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
4579 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4580 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4581 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
4582 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4583 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
4586 // Packed Compare Implicit Length Strings, Return Index
4587 let Defs = [ECX, EFLAGS] in {
4588 multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
4589 def rr : SS42AI<0x63, MRMSrcReg, (outs),
4590 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
4591 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4592 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
4593 (implicit EFLAGS)]>, OpSize;
4594 def rm : SS42AI<0x63, MRMSrcMem, (outs),
4595 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
4596 !strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
4597 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
4598 (implicit EFLAGS)]>, OpSize;
4602 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4603 defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
4605 defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
4607 defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
4609 defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
4611 defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
4613 defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
4617 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
4618 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
4619 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
4620 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
4621 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
4622 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
4624 // Packed Compare Explicit Length Strings, Return Index
4625 let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
4626 multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
4627 def rr : SS42AI<0x61, MRMSrcReg, (outs),
4628 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
4629 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4630 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
4631 (implicit EFLAGS)]>, OpSize;
4632 def rm : SS42AI<0x61, MRMSrcMem, (outs),
4633 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
4634 !strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
4636 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
4637 (implicit EFLAGS)]>, OpSize;
4641 let isAsmParserOnly = 1, Predicates = [HasAVX] in {
4642 defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
4644 defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
4646 defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
4648 defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
4650 defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
4652 defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
4656 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
4657 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
4658 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
4659 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
4660 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
4661 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
4663 //===----------------------------------------------------------------------===//
4664 // SSE4.2 - CRC Instructions
4665 //===----------------------------------------------------------------------===//
4667 // No CRC instructions have AVX equivalents
4669 // crc intrinsic instruction
4670 // This set of instructions are only rm, the only difference is the size
4672 let Constraints = "$src1 = $dst" in {
4673 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
4674 (ins GR32:$src1, i8mem:$src2),
4675 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4677 (int_x86_sse42_crc32_8 GR32:$src1,
4678 (load addr:$src2)))]>;
4679 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
4680 (ins GR32:$src1, GR8:$src2),
4681 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4683 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
4684 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4685 (ins GR32:$src1, i16mem:$src2),
4686 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4688 (int_x86_sse42_crc32_16 GR32:$src1,
4689 (load addr:$src2)))]>,
4691 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4692 (ins GR32:$src1, GR16:$src2),
4693 "crc32{w} \t{$src2, $src1|$src1, $src2}",
4695 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
4697 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
4698 (ins GR32:$src1, i32mem:$src2),
4699 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4701 (int_x86_sse42_crc32_32 GR32:$src1,
4702 (load addr:$src2)))]>;
4703 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
4704 (ins GR32:$src1, GR32:$src2),
4705 "crc32{l} \t{$src2, $src1|$src1, $src2}",
4707 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
4708 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
4709 (ins GR64:$src1, i8mem:$src2),
4710 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4712 (int_x86_sse42_crc64_8 GR64:$src1,
4713 (load addr:$src2)))]>,
4715 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
4716 (ins GR64:$src1, GR8:$src2),
4717 "crc32{b} \t{$src2, $src1|$src1, $src2}",
4719 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
4721 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
4722 (ins GR64:$src1, i64mem:$src2),
4723 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4725 (int_x86_sse42_crc64_64 GR64:$src1,
4726 (load addr:$src2)))]>,
4728 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
4729 (ins GR64:$src1, GR64:$src2),
4730 "crc32{q} \t{$src2, $src1|$src1, $src2}",
4732 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
4736 //===----------------------------------------------------------------------===//
4737 // AES-NI Instructions
4738 //===----------------------------------------------------------------------===//
4740 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
4741 Intrinsic IntId128, bit Is2Addr = 1> {
4742 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
4743 (ins VR128:$src1, VR128:$src2),
4745 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4746 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4747 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
4749 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
4750 (ins VR128:$src1, i128mem:$src2),
4752 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
4753 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
4755 (IntId128 VR128:$src1,
4756 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
4759 // Perform One Round of an AES Encryption/Decryption Flow
4760 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
4761 defm VAESENC : AESI_binop_rm_int<0xDC, "vaesenc",
4762 int_x86_aesni_aesenc, 0>, VEX_4V;
4763 defm VAESENCLAST : AESI_binop_rm_int<0xDD, "vaesenclast",
4764 int_x86_aesni_aesenclast, 0>, VEX_4V;
4765 defm VAESDEC : AESI_binop_rm_int<0xDE, "vaesdec",
4766 int_x86_aesni_aesdec, 0>, VEX_4V;
4767 defm VAESDECLAST : AESI_binop_rm_int<0xDF, "vaesdeclast",
4768 int_x86_aesni_aesdeclast, 0>, VEX_4V;
4771 let Constraints = "$src1 = $dst" in {
4772 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
4773 int_x86_aesni_aesenc>;
4774 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
4775 int_x86_aesni_aesenclast>;
4776 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
4777 int_x86_aesni_aesdec>;
4778 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
4779 int_x86_aesni_aesdeclast>;
4782 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
4783 (AESENCrr VR128:$src1, VR128:$src2)>;
4784 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
4785 (AESENCrm VR128:$src1, addr:$src2)>;
4786 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
4787 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
4788 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
4789 (AESENCLASTrm VR128:$src1, addr:$src2)>;
4790 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
4791 (AESDECrr VR128:$src1, VR128:$src2)>;
4792 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
4793 (AESDECrm VR128:$src1, addr:$src2)>;
4794 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
4795 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
4796 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
4797 (AESDECLASTrm VR128:$src1, addr:$src2)>;
4799 // Perform the AES InvMixColumn Transformation
4800 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
4801 def VAESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4803 "vaesimc\t{$src1, $dst|$dst, $src1}",
4805 (int_x86_aesni_aesimc VR128:$src1))]>,
4807 def VAESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4808 (ins i128mem:$src1),
4809 "vaesimc\t{$src1, $dst|$dst, $src1}",
4811 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4814 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
4816 "aesimc\t{$src1, $dst|$dst, $src1}",
4818 (int_x86_aesni_aesimc VR128:$src1))]>,
4820 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
4821 (ins i128mem:$src1),
4822 "aesimc\t{$src1, $dst|$dst, $src1}",
4824 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
4827 // AES Round Key Generation Assist
4828 let isAsmParserOnly = 1, Predicates = [HasAVX, HasAES] in {
4829 def VAESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4830 (ins VR128:$src1, i8imm:$src2),
4831 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4833 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4835 def VAESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4836 (ins i128mem:$src1, i8imm:$src2),
4837 "vaeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4839 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),
4843 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
4844 (ins VR128:$src1, i8imm:$src2),
4845 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4847 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
4849 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
4850 (ins i128mem:$src1, i8imm:$src2),
4851 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
4853 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),