1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
23 def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
24 SDTCisFP<1>, SDTCisVT<3, i8>]>;
26 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
27 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
28 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
33 [SDNPCommutative, SDNPAssociative]>;
34 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
35 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
36 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
37 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
38 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
39 def X86pshufb : SDNode<"X86ISD::PSHUFB",
40 SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
42 def X86pextrb : SDNode<"X86ISD::PEXTRB",
43 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
44 def X86pextrw : SDNode<"X86ISD::PEXTRW",
45 SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<2>]>>;
46 def X86pinsrb : SDNode<"X86ISD::PINSRB",
47 SDTypeProfile<1, 3, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>,
48 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
49 def X86pinsrw : SDNode<"X86ISD::PINSRW",
50 SDTypeProfile<1, 3, [SDTCisVT<0, v8i16>, SDTCisSameAs<0,1>,
51 SDTCisVT<2, i32>, SDTCisPtrTy<3>]>>;
52 def X86insrtps : SDNode<"X86ISD::INSERTPS",
53 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisSameAs<0,1>,
54 SDTCisVT<2, v4f32>, SDTCisPtrTy<3>]>>;
55 def X86vzmovl : SDNode<"X86ISD::VZEXT_MOVL",
56 SDTypeProfile<1, 1, [SDTCisSameAs<0,1>]>>;
57 def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
58 [SDNPHasChain, SDNPMayLoad]>;
59 def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
60 def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
61 def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
62 def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
63 def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
64 def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
65 def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
66 def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
67 def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
68 def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
69 def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
70 def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
72 def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>,
75 def X86ptest : SDNode<"X86ISD::PTEST", SDTX86CmpPTest>;
77 //===----------------------------------------------------------------------===//
78 // SSE Complex Patterns
79 //===----------------------------------------------------------------------===//
81 // These are 'extloads' from a scalar to the low element of a vector, zeroing
82 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
84 def sse_load_f32 : ComplexPattern<v4f32, 5, "SelectScalarSSELoad", [],
85 [SDNPHasChain, SDNPMayLoad]>;
86 def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [],
87 [SDNPHasChain, SDNPMayLoad]>;
89 def ssmem : Operand<v4f32> {
90 let PrintMethod = "printf32mem";
91 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
92 let ParserMatchClass = X86MemAsmOperand;
94 def sdmem : Operand<v2f64> {
95 let PrintMethod = "printf64mem";
96 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm);
97 let ParserMatchClass = X86MemAsmOperand;
100 //===----------------------------------------------------------------------===//
101 // SSE pattern fragments
102 //===----------------------------------------------------------------------===//
104 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
105 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
106 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
107 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
109 // Like 'store', but always requires vector alignment.
110 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
111 (store node:$val, node:$ptr), [{
112 return cast<StoreSDNode>(N)->getAlignment() >= 16;
115 // Like 'load', but always requires vector alignment.
116 def alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
117 return cast<LoadSDNode>(N)->getAlignment() >= 16;
120 def alignedloadfsf32 : PatFrag<(ops node:$ptr),
121 (f32 (alignedload node:$ptr))>;
122 def alignedloadfsf64 : PatFrag<(ops node:$ptr),
123 (f64 (alignedload node:$ptr))>;
124 def alignedloadv4f32 : PatFrag<(ops node:$ptr),
125 (v4f32 (alignedload node:$ptr))>;
126 def alignedloadv2f64 : PatFrag<(ops node:$ptr),
127 (v2f64 (alignedload node:$ptr))>;
128 def alignedloadv4i32 : PatFrag<(ops node:$ptr),
129 (v4i32 (alignedload node:$ptr))>;
130 def alignedloadv2i64 : PatFrag<(ops node:$ptr),
131 (v2i64 (alignedload node:$ptr))>;
133 // Like 'load', but uses special alignment checks suitable for use in
134 // memory operands in most SSE instructions, which are required to
135 // be naturally aligned on some targets but not on others. If the subtarget
136 // allows unaligned accesses, match any load, though this may require
137 // setting a feature bit in the processor (on startup, for example).
138 // Opteron 10h and later implement such a feature.
139 def memop : PatFrag<(ops node:$ptr), (load node:$ptr), [{
140 return Subtarget->hasVectorUAMem()
141 || cast<LoadSDNode>(N)->getAlignment() >= 16;
144 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
145 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
146 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
147 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
148 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
149 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
150 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
152 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
154 // FIXME: 8 byte alignment for mmx reads is not required
155 def memop64 : PatFrag<(ops node:$ptr), (load node:$ptr), [{
156 return cast<LoadSDNode>(N)->getAlignment() >= 8;
159 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
160 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
161 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
162 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
165 // Like 'store', but requires the non-temporal bit to be set
166 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
167 (st node:$val, node:$ptr), [{
168 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
169 return ST->isNonTemporal();
173 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
174 (st node:$val, node:$ptr), [{
175 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
176 return ST->isNonTemporal() && !ST->isTruncatingStore() &&
177 ST->getAddressingMode() == ISD::UNINDEXED &&
178 ST->getAlignment() >= 16;
182 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
183 (st node:$val, node:$ptr), [{
184 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
185 return ST->isNonTemporal() &&
186 ST->getAlignment() < 16;
190 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
191 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
192 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
193 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
194 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
195 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
197 def vzmovl_v2i64 : PatFrag<(ops node:$src),
198 (bitconvert (v2i64 (X86vzmovl
199 (v2i64 (scalar_to_vector (loadi64 node:$src))))))>;
200 def vzmovl_v4i32 : PatFrag<(ops node:$src),
201 (bitconvert (v4i32 (X86vzmovl
202 (v4i32 (scalar_to_vector (loadi32 node:$src))))))>;
204 def vzload_v2i64 : PatFrag<(ops node:$src),
205 (bitconvert (v2i64 (X86vzload node:$src)))>;
208 def fp32imm0 : PatLeaf<(f32 fpimm), [{
209 return N->isExactlyValue(+0.0);
212 // BYTE_imm - Transform bit immediates into byte immediates.
213 def BYTE_imm : SDNodeXForm<imm, [{
214 // Transformation function: imm >> 3
215 return getI32Imm(N->getZExtValue() >> 3);
218 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
220 def SHUFFLE_get_shuf_imm : SDNodeXForm<vector_shuffle, [{
221 return getI8Imm(X86::getShuffleSHUFImmediate(N));
224 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
226 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<vector_shuffle, [{
227 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
230 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
232 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<vector_shuffle, [{
233 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
236 // SHUFFLE_get_palign_imm xform function: convert vector_shuffle mask to
238 def SHUFFLE_get_palign_imm : SDNodeXForm<vector_shuffle, [{
239 return getI8Imm(X86::getShufflePALIGNRImmediate(N));
242 def splat_lo : PatFrag<(ops node:$lhs, node:$rhs),
243 (vector_shuffle node:$lhs, node:$rhs), [{
244 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
245 return SVOp->isSplat() && SVOp->getSplatIndex() == 0;
248 def movddup : PatFrag<(ops node:$lhs, node:$rhs),
249 (vector_shuffle node:$lhs, node:$rhs), [{
250 return X86::isMOVDDUPMask(cast<ShuffleVectorSDNode>(N));
253 def movhlps : PatFrag<(ops node:$lhs, node:$rhs),
254 (vector_shuffle node:$lhs, node:$rhs), [{
255 return X86::isMOVHLPSMask(cast<ShuffleVectorSDNode>(N));
258 def movhlps_undef : PatFrag<(ops node:$lhs, node:$rhs),
259 (vector_shuffle node:$lhs, node:$rhs), [{
260 return X86::isMOVHLPS_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
263 def movlhps : PatFrag<(ops node:$lhs, node:$rhs),
264 (vector_shuffle node:$lhs, node:$rhs), [{
265 return X86::isMOVLHPSMask(cast<ShuffleVectorSDNode>(N));
268 def movlp : PatFrag<(ops node:$lhs, node:$rhs),
269 (vector_shuffle node:$lhs, node:$rhs), [{
270 return X86::isMOVLPMask(cast<ShuffleVectorSDNode>(N));
273 def movl : PatFrag<(ops node:$lhs, node:$rhs),
274 (vector_shuffle node:$lhs, node:$rhs), [{
275 return X86::isMOVLMask(cast<ShuffleVectorSDNode>(N));
278 def movshdup : PatFrag<(ops node:$lhs, node:$rhs),
279 (vector_shuffle node:$lhs, node:$rhs), [{
280 return X86::isMOVSHDUPMask(cast<ShuffleVectorSDNode>(N));
283 def movsldup : PatFrag<(ops node:$lhs, node:$rhs),
284 (vector_shuffle node:$lhs, node:$rhs), [{
285 return X86::isMOVSLDUPMask(cast<ShuffleVectorSDNode>(N));
288 def unpckl : PatFrag<(ops node:$lhs, node:$rhs),
289 (vector_shuffle node:$lhs, node:$rhs), [{
290 return X86::isUNPCKLMask(cast<ShuffleVectorSDNode>(N));
293 def unpckh : PatFrag<(ops node:$lhs, node:$rhs),
294 (vector_shuffle node:$lhs, node:$rhs), [{
295 return X86::isUNPCKHMask(cast<ShuffleVectorSDNode>(N));
298 def unpckl_undef : PatFrag<(ops node:$lhs, node:$rhs),
299 (vector_shuffle node:$lhs, node:$rhs), [{
300 return X86::isUNPCKL_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
303 def unpckh_undef : PatFrag<(ops node:$lhs, node:$rhs),
304 (vector_shuffle node:$lhs, node:$rhs), [{
305 return X86::isUNPCKH_v_undef_Mask(cast<ShuffleVectorSDNode>(N));
308 def pshufd : PatFrag<(ops node:$lhs, node:$rhs),
309 (vector_shuffle node:$lhs, node:$rhs), [{
310 return X86::isPSHUFDMask(cast<ShuffleVectorSDNode>(N));
311 }], SHUFFLE_get_shuf_imm>;
313 def shufp : PatFrag<(ops node:$lhs, node:$rhs),
314 (vector_shuffle node:$lhs, node:$rhs), [{
315 return X86::isSHUFPMask(cast<ShuffleVectorSDNode>(N));
316 }], SHUFFLE_get_shuf_imm>;
318 def pshufhw : PatFrag<(ops node:$lhs, node:$rhs),
319 (vector_shuffle node:$lhs, node:$rhs), [{
320 return X86::isPSHUFHWMask(cast<ShuffleVectorSDNode>(N));
321 }], SHUFFLE_get_pshufhw_imm>;
323 def pshuflw : PatFrag<(ops node:$lhs, node:$rhs),
324 (vector_shuffle node:$lhs, node:$rhs), [{
325 return X86::isPSHUFLWMask(cast<ShuffleVectorSDNode>(N));
326 }], SHUFFLE_get_pshuflw_imm>;
328 def palign : PatFrag<(ops node:$lhs, node:$rhs),
329 (vector_shuffle node:$lhs, node:$rhs), [{
330 return X86::isPALIGNRMask(cast<ShuffleVectorSDNode>(N));
331 }], SHUFFLE_get_palign_imm>;
333 //===----------------------------------------------------------------------===//
334 // SSE scalar FP Instructions
335 //===----------------------------------------------------------------------===//
337 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
338 // instruction selection into a branch sequence.
339 let Uses = [EFLAGS], usesCustomInserter = 1 in {
340 def CMOV_FR32 : I<0, Pseudo,
341 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
342 "#CMOV_FR32 PSEUDO!",
343 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
345 def CMOV_FR64 : I<0, Pseudo,
346 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
347 "#CMOV_FR64 PSEUDO!",
348 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
350 def CMOV_V4F32 : I<0, Pseudo,
351 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
352 "#CMOV_V4F32 PSEUDO!",
354 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
356 def CMOV_V2F64 : I<0, Pseudo,
357 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
358 "#CMOV_V2F64 PSEUDO!",
360 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
362 def CMOV_V2I64 : I<0, Pseudo,
363 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
364 "#CMOV_V2I64 PSEUDO!",
366 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Move Instructions. Register-to-register movss is not used for FR32
375 // register copies because it's a partial register update; FsMOVAPSrr is
376 // used instead. Register-to-register movss is not modeled as an INSERT_SUBREG
377 // because INSERT_SUBREG requires that the insert be implementable in terms of
378 // a copy, and just mentioned, we don't use movss for copies.
379 let Constraints = "$src1 = $dst" in
380 def MOVSSrr : SSI<0x10, MRMSrcReg,
381 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
382 "movss\t{$src2, $dst|$dst, $src2}",
383 [(set (v4f32 VR128:$dst),
384 (movl VR128:$src1, (scalar_to_vector FR32:$src2)))]>;
386 // Extract the low 32-bit value from one vector and insert it into another.
387 let AddedComplexity = 15 in
388 def : Pat<(v4f32 (movl VR128:$src1, VR128:$src2)),
389 (MOVSSrr (v4f32 VR128:$src1),
390 (EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
392 // Implicitly promote a 32-bit scalar to a vector.
393 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
394 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FR32:$src, sub_ss)>;
396 // Loading from memory automatically zeroing upper bits.
397 let canFoldAsLoad = 1, isReMaterializable = 1 in
398 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
399 "movss\t{$src, $dst|$dst, $src}",
400 [(set FR32:$dst, (loadf32 addr:$src))]>;
402 // MOVSSrm zeros the high parts of the register; represent this
403 // with SUBREG_TO_REG.
404 let AddedComplexity = 20 in {
405 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
406 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
407 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
408 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
409 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
410 (SUBREG_TO_REG (i32 0), (MOVSSrm addr:$src), sub_ss)>;
413 // Store scalar value to memory.
414 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
415 "movss\t{$src, $dst|$dst, $src}",
416 [(store FR32:$src, addr:$dst)]>;
418 // Extract and store.
419 def : Pat<(store (f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
422 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
424 // Conversion instructions
425 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
426 "cvttss2si\t{$src, $dst|$dst, $src}",
427 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
428 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
429 "cvttss2si\t{$src, $dst|$dst, $src}",
430 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
431 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
432 "cvtsi2ss\t{$src, $dst|$dst, $src}",
433 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
434 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
435 "cvtsi2ss\t{$src, $dst|$dst, $src}",
436 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
438 // Match intrinsics which expect XMM operand(s).
439 def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
440 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
441 def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
442 "cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
444 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
445 "cvtss2si\t{$src, $dst|$dst, $src}",
446 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
447 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
448 "cvtss2si\t{$src, $dst|$dst, $src}",
449 [(set GR32:$dst, (int_x86_sse_cvtss2si
450 (load addr:$src)))]>;
452 // Match intrinsics which expect MM and XMM operand(s).
453 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
454 "cvtps2pi\t{$src, $dst|$dst, $src}",
455 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
456 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
457 "cvtps2pi\t{$src, $dst|$dst, $src}",
458 [(set VR64:$dst, (int_x86_sse_cvtps2pi
459 (load addr:$src)))]>;
460 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
461 "cvttps2pi\t{$src, $dst|$dst, $src}",
462 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
463 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
464 "cvttps2pi\t{$src, $dst|$dst, $src}",
465 [(set VR64:$dst, (int_x86_sse_cvttps2pi
466 (load addr:$src)))]>;
467 let Constraints = "$src1 = $dst" in {
468 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
469 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
470 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
471 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
473 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
474 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
475 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
476 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
477 (load addr:$src2)))]>;
480 // Aliases for intrinsics
481 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
482 "cvttss2si\t{$src, $dst|$dst, $src}",
484 (int_x86_sse_cvttss2si VR128:$src))]>;
485 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
486 "cvttss2si\t{$src, $dst|$dst, $src}",
488 (int_x86_sse_cvttss2si(load addr:$src)))]>;
490 let Constraints = "$src1 = $dst" in {
491 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
492 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
493 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
494 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
496 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
497 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
498 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
499 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
500 (loadi32 addr:$src2)))]>;
503 // Comparison instructions
504 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
505 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
506 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
507 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
509 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
510 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
511 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
513 // Accept explicit immediate argument form instead of comparison code.
514 let isAsmParserOnly = 1 in {
515 def CMPSSrr_alt : SSIi8<0xC2, MRMSrcReg,
516 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2),
517 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
519 def CMPSSrm_alt : SSIi8<0xC2, MRMSrcMem,
520 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2),
521 "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
525 let Defs = [EFLAGS] in {
526 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
527 "ucomiss\t{$src2, $src1|$src1, $src2}",
528 [(set EFLAGS, (X86cmp FR32:$src1, FR32:$src2))]>;
529 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
530 "ucomiss\t{$src2, $src1|$src1, $src2}",
531 [(set EFLAGS, (X86cmp FR32:$src1, (loadf32 addr:$src2)))]>;
533 def COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
534 "comiss\t{$src2, $src1|$src1, $src2}", []>;
535 def COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
536 "comiss\t{$src2, $src1|$src1, $src2}", []>;
540 // Aliases to match intrinsics which expect XMM operand(s).
541 let Constraints = "$src1 = $dst" in {
542 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
544 (ins VR128:$src1, VR128:$src, SSECC:$cc),
545 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
546 [(set VR128:$dst, (int_x86_sse_cmp_ss
548 VR128:$src, imm:$cc))]>;
549 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
551 (ins VR128:$src1, f32mem:$src, SSECC:$cc),
552 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
553 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
554 (load addr:$src), imm:$cc))]>;
557 let Defs = [EFLAGS] in {
558 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
559 "ucomiss\t{$src2, $src1|$src1, $src2}",
560 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
562 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
563 "ucomiss\t{$src2, $src1|$src1, $src2}",
564 [(set EFLAGS, (X86ucomi (v4f32 VR128:$src1),
565 (load addr:$src2)))]>;
567 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
568 "comiss\t{$src2, $src1|$src1, $src2}",
569 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
571 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
572 "comiss\t{$src2, $src1|$src1, $src2}",
573 [(set EFLAGS, (X86comi (v4f32 VR128:$src1),
574 (load addr:$src2)))]>;
577 // Aliases of packed SSE1 instructions for scalar use. These all have names
578 // that start with 'Fs'.
580 // Alias instructions that map fld0 to pxor for sse.
581 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
583 // FIXME: Set encoding to pseudo!
584 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins), "",
585 [(set FR32:$dst, fp32imm0)]>,
586 Requires<[HasSSE1]>, TB, OpSize;
588 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
590 let neverHasSideEffects = 1 in
591 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
592 "movaps\t{$src, $dst|$dst, $src}", []>;
594 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
596 let canFoldAsLoad = 1, isReMaterializable = 1 in
597 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
598 "movaps\t{$src, $dst|$dst, $src}",
599 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
601 /// sse12_fp_alias_pack_logical - SSE 1 & 2 aliased packed FP logical ops
603 multiclass sse12_fp_alias_pack_logical<bits<8> opc, string OpcodeStr,
604 SDNode OpNode, int NoPat = 0,
605 bit MayLoad = 0, bit Commutable = 1> {
606 def PSrr : PSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
607 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
609 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))])> {
610 let isCommutable = Commutable;
613 def PDrr : PDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
614 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
616 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))])> {
617 let isCommutable = Commutable;
620 def PSrm : PSI<opc, MRMSrcMem, (outs FR32:$dst),
621 (ins FR32:$src1, f128mem:$src2),
622 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
624 [(set FR32:$dst, (OpNode FR32:$src1,
625 (memopfsf32 addr:$src2)))])> {
626 let mayLoad = MayLoad;
629 def PDrm : PDI<opc, MRMSrcMem, (outs FR64:$dst),
630 (ins FR64:$src1, f128mem:$src2),
631 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
633 [(set FR64:$dst, (OpNode FR64:$src1,
634 (memopfsf64 addr:$src2)))])> {
635 let mayLoad = MayLoad;
639 // Alias bitwise logical operations using SSE logical ops on packed FP values.
640 let Constraints = "$src1 = $dst" in {
641 defm FsAND : sse12_fp_alias_pack_logical<0x54, "and", X86fand>;
642 defm FsOR : sse12_fp_alias_pack_logical<0x56, "or", X86for>;
643 defm FsXOR : sse12_fp_alias_pack_logical<0x57, "xor", X86fxor>;
645 let neverHasSideEffects = 1 in
646 defm FsANDN : sse12_fp_alias_pack_logical<0x55, "andn", undef, 1, 1, 0>;
649 /// sse12_fp_scalar - SSE 1 & 2 scalar instructions class
650 multiclass sse12_fp_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
651 RegisterClass RC, X86MemOperand memop> {
652 let isCommutable = 1 in {
653 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
654 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>;
656 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memop:$src2),
657 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))]>;
660 /// sse12_fp_scalar_int - SSE 1 & 2 scalar instructions intrinsics class
661 multiclass sse12_fp_scalar_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
662 string asm, string SSEVer, string FPSizeStr,
663 Operand memop, ComplexPattern mem_cpat> {
664 def rr_Int : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
665 asm, [(set RC:$dst, (
666 !nameconcat<Intrinsic>("int_x86_sse",
667 !strconcat(SSEVer, !strconcat("_",
668 !strconcat(OpcodeStr, FPSizeStr))))
669 RC:$src1, RC:$src2))]>;
670 def rm_Int : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, memop:$src2),
671 asm, [(set RC:$dst, (
672 !nameconcat<Intrinsic>("int_x86_sse",
673 !strconcat(SSEVer, !strconcat("_",
674 !strconcat(OpcodeStr, FPSizeStr))))
675 RC:$src1, mem_cpat:$src2))]>;
678 /// sse12_fp_packed - SSE 1 & 2 packed instructions class
679 multiclass sse12_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
680 RegisterClass RC, ValueType vt,
681 X86MemOperand x86memop, PatFrag mem_frag,
683 let isCommutable = 1 in
684 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
685 OpcodeStr, [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))],d>;
686 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
687 OpcodeStr, [(set RC:$dst, (OpNode RC:$src1,
688 (mem_frag addr:$src2)))],d>;
691 /// basic_sse12_fp_binop_rm - SSE 1 & 2 binops come in both scalar and
694 /// In addition, we also have a special variant of the scalar form here to
695 /// represent the associated intrinsic operation. This form is unlike the
696 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
697 /// and leaves the top elements unmodified (therefore these cannot be commuted).
699 /// These three forms can each be reg+reg or reg+mem, so there are a total of
700 /// six "instructions".
702 multiclass basic_sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
703 SDNode OpNode, bit Commutable = 0> {
705 let isAsmParserOnly = 1 in {
706 defm V#NAME#SS : sse12_fp_scalar<opc,
707 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
708 OpNode, FR32, f32mem>, XS, VEX_4V;
710 defm V#NAME#SD : sse12_fp_scalar<opc,
711 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
712 OpNode, FR64, f64mem>, XD, VEX_4V;
714 defm V#NAME#PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
715 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
716 VR128, v4f32, f128mem, memopv4f32, SSEPackedSingle>,
719 defm V#NAME#PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
720 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), OpNode,
721 VR128, v2f64, f128mem, memopv2f64, SSEPackedDouble>,
724 defm V#NAME#SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
725 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
726 "", "_ss", ssmem, sse_load_f32>, XS, VEX_4V;
728 defm V#NAME#SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
729 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
730 "2", "_sd", sdmem, sse_load_f64>, XD, VEX_4V;
733 let Constraints = "$src1 = $dst" in {
734 defm SS : sse12_fp_scalar<opc,
735 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
736 OpNode, FR32, f32mem>, XS;
738 defm SD : sse12_fp_scalar<opc,
739 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
740 OpNode, FR64, f64mem>, XD;
742 defm PS : sse12_fp_packed<opc, !strconcat(OpcodeStr,
743 "ps\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v4f32,
744 f128mem, memopv4f32, SSEPackedSingle>, TB;
746 defm PD : sse12_fp_packed<opc, !strconcat(OpcodeStr,
747 "pd\t{$src2, $dst|$dst, $src2}"), OpNode, VR128, v2f64,
748 f128mem, memopv2f64, SSEPackedDouble>, TB, OpSize;
750 defm SS : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
751 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
752 "", "_ss", ssmem, sse_load_f32>, XS;
754 defm SD : sse12_fp_scalar_int<opc, OpcodeStr, VR128,
755 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
756 "2", "_sd", sdmem, sse_load_f64>, XD;
760 // Arithmetic instructions
761 defm ADD : basic_sse12_fp_binop_rm<0x58, "add", fadd, 1>;
762 defm MUL : basic_sse12_fp_binop_rm<0x59, "mul", fmul, 1>;
764 let isCommutable = 0 in {
765 defm SUB : basic_sse12_fp_binop_rm<0x5C, "sub", fsub>;
766 defm DIV : basic_sse12_fp_binop_rm<0x5E, "div", fdiv>;
769 /// sse12_fp_binop_rm - Other SSE 1 & 2 binops
771 /// This multiclass is like basic_sse12_fp_binop_rm, with the addition of
772 /// instructions for a full-vector intrinsic form. Operations that map
773 /// onto C operators don't use this form since they just use the plain
774 /// vector form instead of having a separate vector intrinsic form.
776 /// This provides a total of eight "instructions".
778 let Constraints = "$src1 = $dst" in {
779 multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
780 SDNode OpNode, bit Commutable = 0> {
782 let Constraints = "", isAsmParserOnly = 1 in {
783 // Scalar operation, reg+reg.
784 defm V#NAME#SS : sse12_fp_scalar<opc,
785 !strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
786 OpNode, FR32, f32mem>, XS, VEX_4V;
788 defm V#NAME#SD : sse12_fp_scalar<opc,
789 !strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
790 OpNode, FR64, f64mem>, XD, VEX_4V;
793 let Constraints = "$src1 = $dst" in {
794 // Scalar operation, reg+reg.
795 defm SS : sse12_fp_scalar<opc,
796 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
797 OpNode, FR32, f32mem>, XS;
798 defm SD : sse12_fp_scalar<opc,
799 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
800 OpNode, FR64, f64mem>, XD;
803 // Vector operation, reg+reg.
804 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
805 (ins VR128:$src1, VR128:$src2),
806 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
807 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
808 let isCommutable = Commutable;
811 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
812 (ins VR128:$src1, VR128:$src2),
813 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
814 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
815 let isCommutable = Commutable;
818 // Vector operation, reg+mem.
819 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
820 (ins VR128:$src1, f128mem:$src2),
821 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
822 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
824 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
825 (ins VR128:$src1, f128mem:$src2),
826 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
827 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
829 // Intrinsic operation, reg+reg.
830 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst),
831 (ins VR128:$src1, VR128:$src2),
832 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
833 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
834 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
836 // int_x86_sse_xxx_ss
837 let isCommutable = Commutable;
840 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst),
841 (ins VR128:$src1, VR128:$src2),
842 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
843 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
844 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
846 // int_x86_sse2_xxx_sd
847 let isCommutable = Commutable;
850 // Intrinsic operation, reg+mem.
851 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst),
852 (ins VR128:$src1, ssmem:$src2),
853 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
854 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
855 !strconcat(OpcodeStr, "_ss")) VR128:$src1,
856 sse_load_f32:$src2))]>;
857 // int_x86_sse_xxx_ss
859 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst),
860 (ins VR128:$src1, sdmem:$src2),
861 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
862 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
863 !strconcat(OpcodeStr, "_sd")) VR128:$src1,
864 sse_load_f64:$src2))]>;
865 // int_x86_sse2_xxx_sd
867 // Vector intrinsic operation, reg+reg.
868 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst),
869 (ins VR128:$src1, VR128:$src2),
870 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
871 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
872 !strconcat(OpcodeStr, "_ps")) VR128:$src1,
874 // int_x86_sse_xxx_ps
875 let isCommutable = Commutable;
878 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst),
879 (ins VR128:$src1, VR128:$src2),
880 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
881 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
882 !strconcat(OpcodeStr, "_pd")) VR128:$src1,
884 // int_x86_sse2_xxx_pd
885 let isCommutable = Commutable;
888 // Vector intrinsic operation, reg+mem.
889 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst),
890 (ins VR128:$src1, f128mem:$src2),
891 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
892 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse_",
893 !strconcat(OpcodeStr, "_ps")) VR128:$src1,
894 (memopv4f32 addr:$src2)))]>;
895 // int_x86_sse_xxx_ps
897 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst),
898 (ins VR128:$src1, f128mem:$src2),
899 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
900 [(set VR128:$dst, (!nameconcat<Intrinsic>("int_x86_sse2_",
901 !strconcat(OpcodeStr, "_pd")) VR128:$src1,
902 (memopv2f64 addr:$src2)))]>;
903 // int_x86_sse2_xxx_pd
907 let isCommutable = 0 in {
908 defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
909 defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
912 //===----------------------------------------------------------------------===//
913 // SSE packed FP Instructions
916 let neverHasSideEffects = 1 in
917 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
918 "movaps\t{$src, $dst|$dst, $src}", []>;
919 let canFoldAsLoad = 1, isReMaterializable = 1 in
920 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
921 "movaps\t{$src, $dst|$dst, $src}",
922 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
924 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
925 "movaps\t{$src, $dst|$dst, $src}",
926 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
928 let neverHasSideEffects = 1 in
929 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
930 "movups\t{$src, $dst|$dst, $src}", []>;
931 let canFoldAsLoad = 1, isReMaterializable = 1 in
932 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
933 "movups\t{$src, $dst|$dst, $src}",
934 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
935 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
936 "movups\t{$src, $dst|$dst, $src}",
937 [(store (v4f32 VR128:$src), addr:$dst)]>;
939 // Intrinsic forms of MOVUPS load and store
940 let canFoldAsLoad = 1, isReMaterializable = 1 in
941 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
942 "movups\t{$src, $dst|$dst, $src}",
943 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
944 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
945 "movups\t{$src, $dst|$dst, $src}",
946 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
948 let Constraints = "$src1 = $dst" in {
949 let AddedComplexity = 20 in {
950 def MOVLPSrm : PSI<0x12, MRMSrcMem,
951 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
952 "movlps\t{$src2, $dst|$dst, $src2}",
955 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
956 def MOVHPSrm : PSI<0x16, MRMSrcMem,
957 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
958 "movhps\t{$src2, $dst|$dst, $src2}",
960 (movlhps VR128:$src1,
961 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))))]>;
963 } // Constraints = "$src1 = $dst"
966 def : Pat<(movlhps VR128:$src1, (bc_v4i32 (v2i64 (X86vzload addr:$src2)))),
967 (MOVHPSrm (v4i32 VR128:$src1), addr:$src2)>;
969 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
970 "movlps\t{$src, $dst|$dst, $src}",
971 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
972 (iPTR 0))), addr:$dst)]>;
974 // v2f64 extract element 1 is always custom lowered to unpack high to low
975 // and extract element 0 so the non-store version isn't too horrible.
976 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
977 "movhps\t{$src, $dst|$dst, $src}",
978 [(store (f64 (vector_extract
979 (unpckh (bc_v2f64 (v4f32 VR128:$src)),
980 (undef)), (iPTR 0))), addr:$dst)]>;
982 let Constraints = "$src1 = $dst" in {
983 let AddedComplexity = 20 in {
984 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst),
985 (ins VR128:$src1, VR128:$src2),
986 "movlhps\t{$src2, $dst|$dst, $src2}",
988 (v4f32 (movlhps VR128:$src1, VR128:$src2)))]>;
990 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst),
991 (ins VR128:$src1, VR128:$src2),
992 "movhlps\t{$src2, $dst|$dst, $src2}",
994 (v4f32 (movhlps VR128:$src1, VR128:$src2)))]>;
996 } // Constraints = "$src1 = $dst"
998 let AddedComplexity = 20 in {
999 def : Pat<(v4f32 (movddup VR128:$src, (undef))),
1000 (MOVLHPSrr (v4f32 VR128:$src), (v4f32 VR128:$src))>;
1001 def : Pat<(v2i64 (movddup VR128:$src, (undef))),
1002 (MOVLHPSrr (v2i64 VR128:$src), (v2i64 VR128:$src))>;
1009 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
1011 /// In addition, we also have a special variant of the scalar form here to
1012 /// represent the associated intrinsic operation. This form is unlike the
1013 /// plain scalar form, in that it takes an entire vector (instead of a
1014 /// scalar) and leaves the top elements undefined.
1016 /// And, we have a special variant form for a full-vector intrinsic form.
1018 /// These four forms can each have a reg or a mem operand, so there are a
1019 /// total of eight "instructions".
1021 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
1025 bit Commutable = 0> {
1026 // Scalar operation, reg.
1027 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
1028 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1029 [(set FR32:$dst, (OpNode FR32:$src))]> {
1030 let isCommutable = Commutable;
1033 // Scalar operation, mem.
1034 def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
1035 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1036 [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS,
1037 Requires<[HasSSE1, OptForSize]>;
1039 // Vector operation, reg.
1040 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1041 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1042 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
1043 let isCommutable = Commutable;
1046 // Vector operation, mem.
1047 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1048 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1049 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
1051 // Intrinsic operation, reg.
1052 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1053 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1054 [(set VR128:$dst, (F32Int VR128:$src))]> {
1055 let isCommutable = Commutable;
1058 // Intrinsic operation, mem.
1059 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
1060 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
1061 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
1063 // Vector intrinsic operation, reg
1064 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1065 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1066 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
1067 let isCommutable = Commutable;
1070 // Vector intrinsic operation, mem
1071 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1072 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
1073 [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src)))]>;
1077 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
1078 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
1080 // Reciprocal approximations. Note that these typically require refinement
1081 // in order to obtain suitable precision.
1082 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
1083 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
1084 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
1085 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
1087 /// sse12_fp_pack_logical - SSE 1 & 2 packed FP logical ops
1089 multiclass sse12_fp_pack_logical<bits<8> opc, string OpcodeStr,
1090 SDNode OpNode, int HasPat = 0,
1092 list<list<dag>> Pattern = []> {
1093 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
1094 (ins VR128:$src1, VR128:$src2),
1095 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1096 !if(HasPat, Pattern[0],
1097 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1,
1099 { let isCommutable = Commutable; }
1101 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1102 (ins VR128:$src1, VR128:$src2),
1103 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1104 !if(HasPat, Pattern[1],
1105 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1106 (bc_v2i64 (v2f64 VR128:$src2))))])>
1107 { let isCommutable = Commutable; }
1109 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst),
1110 (ins VR128:$src1, f128mem:$src2),
1111 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
1112 !if(HasPat, Pattern[2],
1113 [(set VR128:$dst, (OpNode (bc_v2i64 (v4f32 VR128:$src1)),
1114 (memopv2i64 addr:$src2)))])>;
1116 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1117 (ins VR128:$src1, f128mem:$src2),
1118 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1119 !if(HasPat, Pattern[3],
1120 [(set VR128:$dst, (OpNode (bc_v2i64 (v2f64 VR128:$src1)),
1121 (memopv2i64 addr:$src2)))])>;
1125 let Constraints = "$src1 = $dst" in {
1126 defm AND : sse12_fp_pack_logical<0x54, "and", and>;
1127 defm OR : sse12_fp_pack_logical<0x56, "or", or>;
1128 defm XOR : sse12_fp_pack_logical<0x57, "xor", xor>;
1129 defm ANDN : sse12_fp_pack_logical<0x55, "andn", undef /* dummy */, 1, 0, [
1131 [(set VR128:$dst, (v2i64 (and (xor VR128:$src1,
1132 (bc_v2i64 (v4i32 immAllOnesV))),
1135 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1136 (bc_v2i64 (v2f64 VR128:$src2))))],
1138 [(set VR128:$dst, (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
1139 (bc_v2i64 (v4i32 immAllOnesV))),
1140 (memopv2i64 addr:$src2))))],
1142 [(set VR128:$dst, (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1143 (memopv2i64 addr:$src2)))]]>;
1146 let Constraints = "$src1 = $dst" in {
1147 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
1148 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1149 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1150 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1151 VR128:$src, imm:$cc))]>;
1152 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
1153 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1154 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
1155 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
1156 (memop addr:$src), imm:$cc))]>;
1158 // Accept explicit immediate argument form instead of comparison code.
1159 let isAsmParserOnly = 1 in {
1160 def CMPPSrri_alt : PSIi8<0xC2, MRMSrcReg,
1161 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1162 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1163 def CMPPSrmi_alt : PSIi8<0xC2, MRMSrcMem,
1164 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1165 "cmpps\t{$src2, $src, $dst|$dst, $src, $src}", []>;
1168 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
1169 (CMPPSrri (v4f32 VR128:$src1), (v4f32 VR128:$src2), imm:$cc)>;
1170 def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
1171 (CMPPSrmi (v4f32 VR128:$src1), addr:$src2, imm:$cc)>;
1173 // Shuffle and unpack instructions
1174 let Constraints = "$src1 = $dst" in {
1175 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
1176 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
1177 (outs VR128:$dst), (ins VR128:$src1,
1178 VR128:$src2, i8imm:$src3),
1179 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1181 (v4f32 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1182 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
1183 (outs VR128:$dst), (ins VR128:$src1,
1184 f128mem:$src2, i8imm:$src3),
1185 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1188 VR128:$src1, (memopv4f32 addr:$src2))))]>;
1190 let AddedComplexity = 10 in {
1191 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
1192 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1193 "unpckhps\t{$src2, $dst|$dst, $src2}",
1195 (v4f32 (unpckh VR128:$src1, VR128:$src2)))]>;
1196 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
1197 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1198 "unpckhps\t{$src2, $dst|$dst, $src2}",
1200 (v4f32 (unpckh VR128:$src1,
1201 (memopv4f32 addr:$src2))))]>;
1203 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
1204 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1205 "unpcklps\t{$src2, $dst|$dst, $src2}",
1207 (v4f32 (unpckl VR128:$src1, VR128:$src2)))]>;
1208 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
1209 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1210 "unpcklps\t{$src2, $dst|$dst, $src2}",
1212 (unpckl VR128:$src1, (memopv4f32 addr:$src2)))]>;
1213 } // AddedComplexity
1214 } // Constraints = "$src1 = $dst"
1217 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1218 "movmskps\t{$src, $dst|$dst, $src}",
1219 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
1220 def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1221 "movmskpd\t{$src, $dst|$dst, $src}",
1222 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
1224 // Prefetch intrinsic.
1225 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
1226 "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
1227 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
1228 "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
1229 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
1230 "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
1231 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
1232 "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
1234 // Non-temporal stores
1235 def MOVNTPSmr_Int : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1236 "movntps\t{$src, $dst|$dst, $src}",
1237 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
1239 let AddedComplexity = 400 in { // Prefer non-temporal versions
1240 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1241 "movntps\t{$src, $dst|$dst, $src}",
1242 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
1244 def MOVNTDQ_64mr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1245 "movntdq\t{$src, $dst|$dst, $src}",
1246 [(alignednontemporalstore (v2f64 VR128:$src), addr:$dst)]>;
1248 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
1249 "movnti\t{$src, $dst|$dst, $src}",
1250 [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
1251 TB, Requires<[HasSSE2]>;
1253 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
1254 "movnti\t{$src, $dst|$dst, $src}",
1255 [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
1256 TB, Requires<[HasSSE2]>;
1259 // Load, store, and memory fence
1260 def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
1261 TB, Requires<[HasSSE1]>;
1264 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
1265 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
1266 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
1267 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
1269 // Alias instructions that map zero vector to pxor / xorp* for sse.
1270 // We set canFoldAsLoad because this can be converted to a constant-pool
1271 // load of an all-zeros value if folding it would be beneficial.
1272 // FIXME: Change encoding to pseudo!
1273 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
1274 isCodeGenOnly = 1 in {
1275 def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1276 [(set VR128:$dst, (v4f32 immAllZerosV))]>;
1277 def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "",
1278 [(set VR128:$dst, (v2f64 immAllZerosV))]>;
1279 let ExeDomain = SSEPackedInt in
1280 def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "",
1281 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
1284 def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>;
1285 def : Pat<(v8i16 immAllZerosV), (V_SET0PI)>;
1286 def : Pat<(v16i8 immAllZerosV), (V_SET0PI)>;
1288 def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
1289 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss))>;
1291 //===---------------------------------------------------------------------===//
1292 // SSE2 Instructions
1293 //===---------------------------------------------------------------------===//
1295 // Move Instructions. Register-to-register movsd is not used for FR64
1296 // register copies because it's a partial register update; FsMOVAPDrr is
1297 // used instead. Register-to-register movsd is not modeled as an INSERT_SUBREG
1298 // because INSERT_SUBREG requires that the insert be implementable in terms of
1299 // a copy, and just mentioned, we don't use movsd for copies.
1300 let Constraints = "$src1 = $dst" in
1301 def MOVSDrr : SDI<0x10, MRMSrcReg,
1302 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
1303 "movsd\t{$src2, $dst|$dst, $src2}",
1304 [(set (v2f64 VR128:$dst),
1305 (movl VR128:$src1, (scalar_to_vector FR64:$src2)))]>;
1307 // Extract the low 64-bit value from one vector and insert it into another.
1308 let AddedComplexity = 15 in
1309 def : Pat<(v2f64 (movl VR128:$src1, VR128:$src2)),
1310 (MOVSDrr (v2f64 VR128:$src1),
1311 (EXTRACT_SUBREG (v2f64 VR128:$src2), sub_sd))>;
1313 // Implicitly promote a 64-bit scalar to a vector.
1314 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
1315 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FR64:$src, sub_sd)>;
1317 // Loading from memory automatically zeroing upper bits.
1318 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 20 in
1319 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1320 "movsd\t{$src, $dst|$dst, $src}",
1321 [(set FR64:$dst, (loadf64 addr:$src))]>;
1323 // MOVSDrm zeros the high parts of the register; represent this
1324 // with SUBREG_TO_REG.
1325 let AddedComplexity = 20 in {
1326 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1327 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1328 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1329 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1330 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1331 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1332 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1333 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1334 def : Pat<(v2f64 (X86vzload addr:$src)),
1335 (SUBREG_TO_REG (i64 0), (MOVSDrm addr:$src), sub_sd)>;
1338 // Store scalar value to memory.
1339 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1340 "movsd\t{$src, $dst|$dst, $src}",
1341 [(store FR64:$src, addr:$dst)]>;
1343 // Extract and store.
1344 def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
1347 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
1349 // Conversion instructions
1350 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1351 "cvttsd2si\t{$src, $dst|$dst, $src}",
1352 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1353 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1354 "cvttsd2si\t{$src, $dst|$dst, $src}",
1355 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1356 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1357 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1358 [(set FR32:$dst, (fround FR64:$src))]>;
1359 def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1360 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1361 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD,
1362 Requires<[HasSSE2, OptForSize]>;
1363 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1364 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1365 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1366 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1367 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1368 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1370 def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1371 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1372 def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1373 "cvtpd2dq\t{$src, $dst|$dst, $src}", []>;
1374 def CVTDQ2PDrm : S3SI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1375 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1376 def CVTDQ2PDrr : S3SI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1377 "cvtdq2pd\t{$src, $dst|$dst, $src}", []>;
1378 def CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1379 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1380 def CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1381 "cvtps2dq\t{$src, $dst|$dst, $src}", []>;
1382 def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1383 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1384 def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1385 "cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
1386 def COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1387 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1388 def COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1389 "comisd\t{$src2, $src1|$src1, $src2}", []>;
1391 // SSE2 instructions with XS prefix
1392 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1393 "cvtss2sd\t{$src, $dst|$dst, $src}",
1394 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1395 Requires<[HasSSE2]>;
1396 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1397 "cvtss2sd\t{$src, $dst|$dst, $src}",
1398 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1399 Requires<[HasSSE2, OptForSize]>;
1401 def : Pat<(extloadf32 addr:$src),
1402 (CVTSS2SDrr (MOVSSrm addr:$src))>,
1403 Requires<[HasSSE2, OptForSpeed]>;
1405 // Match intrinsics which expect XMM operand(s).
1406 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1407 "cvtsd2si\t{$src, $dst|$dst, $src}",
1408 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1409 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1410 "cvtsd2si\t{$src, $dst|$dst, $src}",
1411 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1412 (load addr:$src)))]>;
1414 // Match intrinsics which expect MM and XMM operand(s).
1415 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1416 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1417 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1418 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1419 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1420 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1421 (memop addr:$src)))]>;
1422 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1423 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1424 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1425 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1426 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1427 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1428 (memop addr:$src)))]>;
1429 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1430 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1431 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1432 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1433 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1434 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1435 (load addr:$src)))]>;
1437 // Aliases for intrinsics
1438 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1439 "cvttsd2si\t{$src, $dst|$dst, $src}",
1441 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1442 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1443 "cvttsd2si\t{$src, $dst|$dst, $src}",
1444 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1445 (load addr:$src)))]>;
1447 // Comparison instructions
1448 let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in {
1449 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1450 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1451 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1453 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1454 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1455 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1457 // Accept explicit immediate argument form instead of comparison code.
1458 let isAsmParserOnly = 1 in {
1459 def CMPSDrr_alt : SDIi8<0xC2, MRMSrcReg,
1460 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2),
1461 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1463 def CMPSDrm_alt : SDIi8<0xC2, MRMSrcMem,
1464 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2),
1465 "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1469 let Defs = [EFLAGS] in {
1470 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1471 "ucomisd\t{$src2, $src1|$src1, $src2}",
1472 [(set EFLAGS, (X86cmp FR64:$src1, FR64:$src2))]>;
1473 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1474 "ucomisd\t{$src2, $src1|$src1, $src2}",
1475 [(set EFLAGS, (X86cmp FR64:$src1, (loadf64 addr:$src2)))]>;
1476 } // Defs = [EFLAGS]
1478 // Aliases to match intrinsics which expect XMM operand(s).
1479 let Constraints = "$src1 = $dst" in {
1480 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1482 (ins VR128:$src1, VR128:$src, SSECC:$cc),
1483 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1484 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1485 VR128:$src, imm:$cc))]>;
1486 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1488 (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1489 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1490 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1491 (load addr:$src), imm:$cc))]>;
1494 let Defs = [EFLAGS] in {
1495 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1496 "ucomisd\t{$src2, $src1|$src1, $src2}",
1497 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1499 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1500 "ucomisd\t{$src2, $src1|$src1, $src2}",
1501 [(set EFLAGS, (X86ucomi (v2f64 VR128:$src1),
1502 (load addr:$src2)))]>;
1504 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1505 "comisd\t{$src2, $src1|$src1, $src2}",
1506 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1508 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1509 "comisd\t{$src2, $src1|$src1, $src2}",
1510 [(set EFLAGS, (X86comi (v2f64 VR128:$src1),
1511 (load addr:$src2)))]>;
1512 } // Defs = [EFLAGS]
1514 // Aliases of packed SSE2 instructions for scalar use. These all have names
1515 // that start with 'Fs'.
1517 // Alias instructions that map fld0 to pxor for sse.
1518 let isReMaterializable = 1, isAsCheapAsAMove = 1, isCodeGenOnly = 1,
1519 canFoldAsLoad = 1 in
1520 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins), "",
1521 [(set FR64:$dst, fpimm0)]>,
1522 Requires<[HasSSE2]>, TB, OpSize;
1524 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1526 let neverHasSideEffects = 1 in
1527 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1528 "movapd\t{$src, $dst|$dst, $src}", []>;
1530 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1532 let canFoldAsLoad = 1, isReMaterializable = 1 in
1533 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1534 "movapd\t{$src, $dst|$dst, $src}",
1535 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1537 //===---------------------------------------------------------------------===//
1538 // SSE packed FP Instructions
1540 // Move Instructions
1541 let neverHasSideEffects = 1 in
1542 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1543 "movapd\t{$src, $dst|$dst, $src}", []>;
1544 let canFoldAsLoad = 1, isReMaterializable = 1 in
1545 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1546 "movapd\t{$src, $dst|$dst, $src}",
1547 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1549 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1550 "movapd\t{$src, $dst|$dst, $src}",
1551 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1553 let neverHasSideEffects = 1 in
1554 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1555 "movupd\t{$src, $dst|$dst, $src}", []>;
1556 let canFoldAsLoad = 1 in
1557 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1558 "movupd\t{$src, $dst|$dst, $src}",
1559 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1560 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1561 "movupd\t{$src, $dst|$dst, $src}",
1562 [(store (v2f64 VR128:$src), addr:$dst)]>;
1564 // Intrinsic forms of MOVUPD load and store
1565 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1566 "movupd\t{$src, $dst|$dst, $src}",
1567 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1568 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1569 "movupd\t{$src, $dst|$dst, $src}",
1570 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1572 let Constraints = "$src1 = $dst" in {
1573 let AddedComplexity = 20 in {
1574 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1575 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1576 "movlpd\t{$src2, $dst|$dst, $src2}",
1578 (v2f64 (movlp VR128:$src1,
1579 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1580 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1581 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1582 "movhpd\t{$src2, $dst|$dst, $src2}",
1584 (v2f64 (movlhps VR128:$src1,
1585 (scalar_to_vector (loadf64 addr:$src2)))))]>;
1586 } // AddedComplexity
1587 } // Constraints = "$src1 = $dst"
1589 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1590 "movlpd\t{$src, $dst|$dst, $src}",
1591 [(store (f64 (vector_extract (v2f64 VR128:$src),
1592 (iPTR 0))), addr:$dst)]>;
1594 // v2f64 extract element 1 is always custom lowered to unpack high to low
1595 // and extract element 0 so the non-store version isn't too horrible.
1596 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1597 "movhpd\t{$src, $dst|$dst, $src}",
1598 [(store (f64 (vector_extract
1599 (v2f64 (unpckh VR128:$src, (undef))),
1600 (iPTR 0))), addr:$dst)]>;
1602 // SSE2 instructions without OpSize prefix
1603 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1604 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1605 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1606 TB, Requires<[HasSSE2]>;
1607 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1608 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1609 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1610 (bitconvert (memopv2i64 addr:$src))))]>,
1611 TB, Requires<[HasSSE2]>;
1613 // SSE2 instructions with XS prefix
1614 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1615 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1616 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1617 XS, Requires<[HasSSE2]>;
1618 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1619 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1620 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1621 (bitconvert (memopv2i64 addr:$src))))]>,
1622 XS, Requires<[HasSSE2]>;
1624 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1625 "cvtps2dq\t{$src, $dst|$dst, $src}",
1626 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1627 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1628 "cvtps2dq\t{$src, $dst|$dst, $src}",
1629 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1630 (memop addr:$src)))]>;
1631 // SSE2 packed instructions with XS prefix
1632 def CVTTPS2DQrr : SSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1633 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1634 def CVTTPS2DQrm : SSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1635 "cvttps2dq\t{$src, $dst|$dst, $src}", []>;
1637 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1638 "cvttps2dq\t{$src, $dst|$dst, $src}",
1640 (int_x86_sse2_cvttps2dq VR128:$src))]>,
1641 XS, Requires<[HasSSE2]>;
1642 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1643 "cvttps2dq\t{$src, $dst|$dst, $src}",
1644 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1645 (memop addr:$src)))]>,
1646 XS, Requires<[HasSSE2]>;
1648 // SSE2 packed instructions with XD prefix
1649 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1650 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1651 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1652 XD, Requires<[HasSSE2]>;
1653 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1654 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1655 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1656 (memop addr:$src)))]>,
1657 XD, Requires<[HasSSE2]>;
1659 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1660 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1661 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1662 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst),(ins f128mem:$src),
1663 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1664 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1665 (memop addr:$src)))]>;
1667 // SSE2 instructions without OpSize prefix
1668 def CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1669 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1670 def CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1671 "cvtps2pd\t{$src, $dst|$dst, $src}", []>, TB;
1673 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1674 "cvtps2pd\t{$src, $dst|$dst, $src}",
1675 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1676 TB, Requires<[HasSSE2]>;
1677 def Int_CVTPS2PDrm : I<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
1678 "cvtps2pd\t{$src, $dst|$dst, $src}",
1679 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1680 (load addr:$src)))]>,
1681 TB, Requires<[HasSSE2]>;
1683 def CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1684 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1685 def CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1686 "cvtpd2ps\t{$src, $dst|$dst, $src}", []>;
1689 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1690 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1691 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1692 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1693 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1694 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1695 (memop addr:$src)))]>;
1697 // Match intrinsics which expect XMM operand(s).
1698 // Aliases for intrinsics
1699 let Constraints = "$src1 = $dst" in {
1700 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1701 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1702 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1703 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1705 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1706 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1707 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1708 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1709 (loadi32 addr:$src2)))]>;
1710 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1711 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1712 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1713 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1715 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1716 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1717 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1718 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1719 (load addr:$src2)))]>;
1720 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1721 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1722 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1723 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1724 VR128:$src2))]>, XS,
1725 Requires<[HasSSE2]>;
1726 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1727 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1728 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1729 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1730 (load addr:$src2)))]>, XS,
1731 Requires<[HasSSE2]>;
1736 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1738 /// In addition, we also have a special variant of the scalar form here to
1739 /// represent the associated intrinsic operation. This form is unlike the
1740 /// plain scalar form, in that it takes an entire vector (instead of a
1741 /// scalar) and leaves the top elements undefined.
1743 /// And, we have a special variant form for a full-vector intrinsic form.
1745 /// These four forms can each have a reg or a mem operand, so there are a
1746 /// total of eight "instructions".
1748 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1752 bit Commutable = 0> {
1753 // Scalar operation, reg.
1754 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1755 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1756 [(set FR64:$dst, (OpNode FR64:$src))]> {
1757 let isCommutable = Commutable;
1760 // Scalar operation, mem.
1761 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1762 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1763 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1765 // Vector operation, reg.
1766 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1767 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1768 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1769 let isCommutable = Commutable;
1772 // Vector operation, mem.
1773 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1774 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1775 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1777 // Intrinsic operation, reg.
1778 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1779 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1780 [(set VR128:$dst, (F64Int VR128:$src))]> {
1781 let isCommutable = Commutable;
1784 // Intrinsic operation, mem.
1785 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1786 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1787 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1789 // Vector intrinsic operation, reg
1790 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1791 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1792 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1793 let isCommutable = Commutable;
1796 // Vector intrinsic operation, mem
1797 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1798 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1799 [(set VR128:$dst, (V2F64Int (memopv2f64 addr:$src)))]>;
1803 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1804 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1806 // There is no f64 version of the reciprocal approximation instructions.
1808 let Constraints = "$src1 = $dst" in {
1809 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1810 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1811 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1812 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1813 VR128:$src, imm:$cc))]>;
1814 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1815 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1816 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1817 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1818 (memop addr:$src), imm:$cc))]>;
1820 // Accept explicit immediate argument form instead of comparison code.
1821 let isAsmParserOnly = 1 in {
1822 def CMPPDrri_alt : PDIi8<0xC2, MRMSrcReg,
1823 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, i8imm:$src2),
1824 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1825 def CMPPDrmi_alt : PDIi8<0xC2, MRMSrcMem,
1826 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, i8imm:$src2),
1827 "cmppd\t{$src2, $src, $dst|$dst, $src, $src2}", []>;
1830 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), VR128:$src2, imm:$cc)),
1831 (CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
1832 def : Pat<(v2i64 (X86cmppd (v2f64 VR128:$src1), (memop addr:$src2), imm:$cc)),
1833 (CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
1835 // Shuffle and unpack instructions
1836 let Constraints = "$src1 = $dst" in {
1837 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1838 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1839 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1841 (v2f64 (shufp:$src3 VR128:$src1, VR128:$src2)))]>;
1842 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1843 (outs VR128:$dst), (ins VR128:$src1,
1844 f128mem:$src2, i8imm:$src3),
1845 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1848 VR128:$src1, (memopv2f64 addr:$src2))))]>;
1850 let AddedComplexity = 10 in {
1851 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1852 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1853 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1855 (v2f64 (unpckh VR128:$src1, VR128:$src2)))]>;
1856 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1857 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1858 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1860 (v2f64 (unpckh VR128:$src1,
1861 (memopv2f64 addr:$src2))))]>;
1863 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1864 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1865 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1867 (v2f64 (unpckl VR128:$src1, VR128:$src2)))]>;
1868 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1869 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1870 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1872 (unpckl VR128:$src1, (memopv2f64 addr:$src2)))]>;
1873 } // AddedComplexity
1874 } // Constraints = "$src1 = $dst"
1877 //===---------------------------------------------------------------------===//
1878 // SSE integer instructions
1879 let ExeDomain = SSEPackedInt in {
1881 // Move Instructions
1882 let neverHasSideEffects = 1 in
1883 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1884 "movdqa\t{$src, $dst|$dst, $src}", []>;
1885 let canFoldAsLoad = 1, mayLoad = 1 in
1886 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1887 "movdqa\t{$src, $dst|$dst, $src}",
1888 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1890 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1891 "movdqa\t{$src, $dst|$dst, $src}",
1892 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1893 let canFoldAsLoad = 1, mayLoad = 1 in
1894 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1895 "movdqu\t{$src, $dst|$dst, $src}",
1896 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1897 XS, Requires<[HasSSE2]>;
1899 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1900 "movdqu\t{$src, $dst|$dst, $src}",
1901 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1902 XS, Requires<[HasSSE2]>;
1904 // Intrinsic forms of MOVDQU load and store
1905 let canFoldAsLoad = 1 in
1906 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1907 "movdqu\t{$src, $dst|$dst, $src}",
1908 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1909 XS, Requires<[HasSSE2]>;
1910 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1911 "movdqu\t{$src, $dst|$dst, $src}",
1912 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1913 XS, Requires<[HasSSE2]>;
1915 let Constraints = "$src1 = $dst" in {
1917 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1918 bit Commutable = 0> {
1919 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1920 (ins VR128:$src1, VR128:$src2),
1921 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1922 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1923 let isCommutable = Commutable;
1925 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1926 (ins VR128:$src1, i128mem:$src2),
1927 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1928 [(set VR128:$dst, (IntId VR128:$src1,
1929 (bitconvert (memopv2i64
1933 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1935 Intrinsic IntId, Intrinsic IntId2> {
1936 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1937 (ins VR128:$src1, VR128:$src2),
1938 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1939 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1940 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1941 (ins VR128:$src1, i128mem:$src2),
1942 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1943 [(set VR128:$dst, (IntId VR128:$src1,
1944 (bitconvert (memopv2i64 addr:$src2))))]>;
1945 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst),
1946 (ins VR128:$src1, i32i8imm:$src2),
1947 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1948 [(set VR128:$dst, (IntId2 VR128:$src1, (i32 imm:$src2)))]>;
1951 /// PDI_binop_rm - Simple SSE2 binary operator.
1952 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1953 ValueType OpVT, bit Commutable = 0> {
1954 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1955 (ins VR128:$src1, VR128:$src2),
1956 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1957 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1958 let isCommutable = Commutable;
1960 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1961 (ins VR128:$src1, i128mem:$src2),
1962 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1963 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1964 (bitconvert (memopv2i64 addr:$src2)))))]>;
1967 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1969 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1970 /// to collapse (bitconvert VT to VT) into its operand.
1972 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1973 bit Commutable = 0> {
1974 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst),
1975 (ins VR128:$src1, VR128:$src2),
1976 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1977 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1978 let isCommutable = Commutable;
1980 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst),
1981 (ins VR128:$src1, i128mem:$src2),
1982 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1983 [(set VR128:$dst, (OpNode VR128:$src1,
1984 (memopv2i64 addr:$src2)))]>;
1987 } // Constraints = "$src1 = $dst"
1988 } // ExeDomain = SSEPackedInt
1990 // 128-bit Integer Arithmetic
1992 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1993 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1994 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1995 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1997 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1998 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1999 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
2000 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
2002 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
2003 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
2004 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
2005 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
2007 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
2008 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
2009 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
2010 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
2012 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
2014 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
2015 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
2016 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
2018 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
2020 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
2021 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
2024 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
2025 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
2026 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
2027 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
2028 defm PSADBW : PDI_binop_rm_int<0xF6, "psadbw", int_x86_sse2_psad_bw, 1>;
2031 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw",
2032 int_x86_sse2_psll_w, int_x86_sse2_pslli_w>;
2033 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld",
2034 int_x86_sse2_psll_d, int_x86_sse2_pslli_d>;
2035 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq",
2036 int_x86_sse2_psll_q, int_x86_sse2_pslli_q>;
2038 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw",
2039 int_x86_sse2_psrl_w, int_x86_sse2_psrli_w>;
2040 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld",
2041 int_x86_sse2_psrl_d, int_x86_sse2_psrli_d>;
2042 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq",
2043 int_x86_sse2_psrl_q, int_x86_sse2_psrli_q>;
2045 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw",
2046 int_x86_sse2_psra_w, int_x86_sse2_psrai_w>;
2047 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad",
2048 int_x86_sse2_psra_d, int_x86_sse2_psrai_d>;
2050 // 128-bit logical shifts.
2051 let Constraints = "$src1 = $dst", neverHasSideEffects = 1,
2052 ExeDomain = SSEPackedInt in {
2053 def PSLLDQri : PDIi8<0x73, MRM7r,
2054 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2055 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
2056 def PSRLDQri : PDIi8<0x73, MRM3r,
2057 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
2058 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
2059 // PSRADQri doesn't exist in SSE[1-3].
2062 let Predicates = [HasSSE2] in {
2063 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
2064 (v2i64 (PSLLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2065 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
2066 (v2i64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2067 def : Pat<(int_x86_sse2_psll_dq_bs VR128:$src1, imm:$src2),
2068 (v2i64 (PSLLDQri VR128:$src1, imm:$src2))>;
2069 def : Pat<(int_x86_sse2_psrl_dq_bs VR128:$src1, imm:$src2),
2070 (v2i64 (PSRLDQri VR128:$src1, imm:$src2))>;
2071 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
2072 (v2f64 (PSRLDQri VR128:$src1, (BYTE_imm imm:$src2)))>;
2074 // Shift up / down and insert zero's.
2075 def : Pat<(v2i64 (X86vshl VR128:$src, (i8 imm:$amt))),
2076 (v2i64 (PSLLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2077 def : Pat<(v2i64 (X86vshr VR128:$src, (i8 imm:$amt))),
2078 (v2i64 (PSRLDQri VR128:$src, (BYTE_imm imm:$amt)))>;
2082 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
2083 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
2084 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
2086 let Constraints = "$src1 = $dst", ExeDomain = SSEPackedInt in {
2087 def PANDNrr : PDI<0xDF, MRMSrcReg,
2088 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2089 "pandn\t{$src2, $dst|$dst, $src2}",
2090 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2093 def PANDNrm : PDI<0xDF, MRMSrcMem,
2094 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2095 "pandn\t{$src2, $dst|$dst, $src2}",
2096 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
2097 (memopv2i64 addr:$src2))))]>;
2100 // SSE2 Integer comparison
2101 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
2102 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
2103 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
2104 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
2105 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
2106 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
2108 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
2109 (PCMPEQBrr VR128:$src1, VR128:$src2)>;
2110 def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
2111 (PCMPEQBrm VR128:$src1, addr:$src2)>;
2112 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
2113 (PCMPEQWrr VR128:$src1, VR128:$src2)>;
2114 def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
2115 (PCMPEQWrm VR128:$src1, addr:$src2)>;
2116 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
2117 (PCMPEQDrr VR128:$src1, VR128:$src2)>;
2118 def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
2119 (PCMPEQDrm VR128:$src1, addr:$src2)>;
2121 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
2122 (PCMPGTBrr VR128:$src1, VR128:$src2)>;
2123 def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
2124 (PCMPGTBrm VR128:$src1, addr:$src2)>;
2125 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
2126 (PCMPGTWrr VR128:$src1, VR128:$src2)>;
2127 def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
2128 (PCMPGTWrm VR128:$src1, addr:$src2)>;
2129 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
2130 (PCMPGTDrr VR128:$src1, VR128:$src2)>;
2131 def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
2132 (PCMPGTDrm VR128:$src1, addr:$src2)>;
2135 // Pack instructions
2136 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
2137 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
2138 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
2140 let ExeDomain = SSEPackedInt in {
2142 // Shuffle and unpack instructions
2143 let AddedComplexity = 5 in {
2144 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
2145 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2146 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2147 [(set VR128:$dst, (v4i32 (pshufd:$src2
2148 VR128:$src1, (undef))))]>;
2149 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
2150 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2151 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2152 [(set VR128:$dst, (v4i32 (pshufd:$src2
2153 (bc_v4i32 (memopv2i64 addr:$src1)),
2157 // SSE2 with ImmT == Imm8 and XS prefix.
2158 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
2159 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2160 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2161 [(set VR128:$dst, (v8i16 (pshufhw:$src2 VR128:$src1,
2163 XS, Requires<[HasSSE2]>;
2164 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
2165 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2166 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2167 [(set VR128:$dst, (v8i16 (pshufhw:$src2
2168 (bc_v8i16 (memopv2i64 addr:$src1)),
2170 XS, Requires<[HasSSE2]>;
2172 // SSE2 with ImmT == Imm8 and XD prefix.
2173 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
2174 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
2175 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2176 [(set VR128:$dst, (v8i16 (pshuflw:$src2 VR128:$src1,
2178 XD, Requires<[HasSSE2]>;
2179 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
2180 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
2181 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2182 [(set VR128:$dst, (v8i16 (pshuflw:$src2
2183 (bc_v8i16 (memopv2i64 addr:$src1)),
2185 XD, Requires<[HasSSE2]>;
2187 // Unpack instructions
2188 multiclass sse2_unpack<bits<8> opc, string OpcodeStr, ValueType vt,
2189 PatFrag unp_frag, PatFrag bc_frag> {
2190 def rr : PDI<opc, MRMSrcReg,
2191 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2192 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2193 [(set VR128:$dst, (vt (unp_frag VR128:$src1, VR128:$src2)))]>;
2194 def rm : PDI<opc, MRMSrcMem,
2195 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2196 !strconcat(OpcodeStr,"\t{$src2, $dst|$dst, $src2}"),
2197 [(set VR128:$dst, (unp_frag VR128:$src1,
2198 (bc_frag (memopv2i64
2202 let Constraints = "$src1 = $dst" in {
2203 defm PUNPCKLBW : sse2_unpack<0x60, "punpcklbw", v16i8, unpckl, bc_v16i8>;
2204 defm PUNPCKLWD : sse2_unpack<0x61, "punpcklwd", v8i16, unpckl, bc_v8i16>;
2205 defm PUNPCKLDQ : sse2_unpack<0x62, "punpckldq", v4i32, unpckl, bc_v4i32>;
2207 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2208 /// knew to collapse (bitconvert VT to VT) into its operand.
2209 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2210 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2211 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2213 (v2i64 (unpckl VR128:$src1, VR128:$src2)))]>;
2214 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2215 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2216 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2218 (v2i64 (unpckl VR128:$src1,
2219 (memopv2i64 addr:$src2))))]>;
2221 defm PUNPCKHBW : sse2_unpack<0x68, "punpckhbw", v16i8, unpckh, bc_v16i8>;
2222 defm PUNPCKHWD : sse2_unpack<0x69, "punpckhwd", v8i16, unpckh, bc_v8i16>;
2223 defm PUNPCKHDQ : sse2_unpack<0x6A, "punpckhdq", v4i32, unpckh, bc_v4i32>;
2225 /// FIXME: we could eliminate this and use sse2_unpack instead if tblgen
2226 /// knew to collapse (bitconvert VT to VT) into its operand.
2227 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2228 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2229 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2231 (v2i64 (unpckh VR128:$src1, VR128:$src2)))]>;
2232 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2233 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2234 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2236 (v2i64 (unpckh VR128:$src1,
2237 (memopv2i64 addr:$src2))))]>;
2241 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2242 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2243 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2244 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2246 let Constraints = "$src1 = $dst" in {
2247 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2248 (outs VR128:$dst), (ins VR128:$src1,
2249 GR32:$src2, i32i8imm:$src3),
2250 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2252 (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))]>;
2253 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2254 (outs VR128:$dst), (ins VR128:$src1,
2255 i16mem:$src2, i32i8imm:$src3),
2256 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2258 (X86pinsrw VR128:$src1, (extloadi16 addr:$src2),
2263 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2264 "pmovmskb\t{$src, $dst|$dst, $src}",
2265 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2267 // Conditional store
2269 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2270 "maskmovdqu\t{$mask, $src|$src, $mask}",
2271 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2274 def MASKMOVDQU64 : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2275 "maskmovdqu\t{$mask, $src|$src, $mask}",
2276 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, RDI)]>;
2278 } // ExeDomain = SSEPackedInt
2280 // Non-temporal stores
2281 def MOVNTPDmr_Int : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2282 "movntpd\t{$src, $dst|$dst, $src}",
2283 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2284 let ExeDomain = SSEPackedInt in
2285 def MOVNTDQmr_Int : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2286 "movntdq\t{$src, $dst|$dst, $src}",
2287 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2288 def MOVNTImr_Int : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2289 "movnti\t{$src, $dst|$dst, $src}",
2290 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2291 TB, Requires<[HasSSE2]>;
2293 let AddedComplexity = 400 in { // Prefer non-temporal versions
2294 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2295 "movntpd\t{$src, $dst|$dst, $src}",
2296 [(alignednontemporalstore(v2f64 VR128:$src), addr:$dst)]>;
2298 let ExeDomain = SSEPackedInt in
2299 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2300 "movntdq\t{$src, $dst|$dst, $src}",
2301 [(alignednontemporalstore (v4f32 VR128:$src), addr:$dst)]>;
2305 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2306 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2307 TB, Requires<[HasSSE2]>;
2309 // Load, store, and memory fence
2310 def LFENCE : I<0xAE, MRM_E8, (outs), (ins),
2311 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2312 def MFENCE : I<0xAE, MRM_F0, (outs), (ins),
2313 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2315 // Pause. This "instruction" is encoded as "rep; nop", so even though it
2316 // was introduced with SSE2, it's backward compatible.
2317 def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP;
2319 //TODO: custom lower this so as to never even generate the noop
2320 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2322 def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
2323 def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
2324 def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm),
2327 // Alias instructions that map zero vector to pxor / xorp* for sse.
2328 // We set canFoldAsLoad because this can be converted to a constant-pool
2329 // load of an all-ones value if folding it would be beneficial.
2330 let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
2331 isCodeGenOnly = 1, ExeDomain = SSEPackedInt in
2332 // FIXME: Change encoding to pseudo.
2333 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "",
2334 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2336 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2337 "movd\t{$src, $dst|$dst, $src}",
2339 (v4i32 (scalar_to_vector GR32:$src)))]>;
2340 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2341 "movd\t{$src, $dst|$dst, $src}",
2343 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2345 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2346 "movd\t{$src, $dst|$dst, $src}",
2347 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2349 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2350 "movd\t{$src, $dst|$dst, $src}",
2351 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2353 // SSE2 instructions with XS prefix
2354 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2355 "movq\t{$src, $dst|$dst, $src}",
2357 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2358 Requires<[HasSSE2]>;
2359 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2360 "movq\t{$src, $dst|$dst, $src}",
2361 [(store (i64 (vector_extract (v2i64 VR128:$src),
2362 (iPTR 0))), addr:$dst)]>;
2364 def : Pat<(f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
2365 (f64 (EXTRACT_SUBREG (v2f64 VR128:$src), sub_sd))>;
2367 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2368 "movd\t{$src, $dst|$dst, $src}",
2369 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2371 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2372 "movd\t{$src, $dst|$dst, $src}",
2373 [(store (i32 (vector_extract (v4i32 VR128:$src),
2374 (iPTR 0))), addr:$dst)]>;
2376 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2377 "movd\t{$src, $dst|$dst, $src}",
2378 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2379 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2380 "movd\t{$src, $dst|$dst, $src}",
2381 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2383 // Store / copy lower 64-bits of a XMM register.
2384 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2385 "movq\t{$src, $dst|$dst, $src}",
2386 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2388 // movd / movq to XMM register zero-extends
2389 let AddedComplexity = 15 in {
2390 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2391 "movd\t{$src, $dst|$dst, $src}",
2392 [(set VR128:$dst, (v4i32 (X86vzmovl
2393 (v4i32 (scalar_to_vector GR32:$src)))))]>;
2394 // This is X86-64 only.
2395 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2396 "mov{d|q}\t{$src, $dst|$dst, $src}",
2397 [(set VR128:$dst, (v2i64 (X86vzmovl
2398 (v2i64 (scalar_to_vector GR64:$src)))))]>;
2401 let AddedComplexity = 20 in {
2402 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2403 "movd\t{$src, $dst|$dst, $src}",
2405 (v4i32 (X86vzmovl (v4i32 (scalar_to_vector
2406 (loadi32 addr:$src))))))]>;
2408 def : Pat<(v4i32 (X86vzmovl (loadv4i32 addr:$src))),
2409 (MOVZDI2PDIrm addr:$src)>;
2410 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2411 (MOVZDI2PDIrm addr:$src)>;
2412 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2413 (MOVZDI2PDIrm addr:$src)>;
2415 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2416 "movq\t{$src, $dst|$dst, $src}",
2418 (v2i64 (X86vzmovl (v2i64 (scalar_to_vector
2419 (loadi64 addr:$src))))))]>, XS,
2420 Requires<[HasSSE2]>;
2422 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2423 (MOVZQI2PQIrm addr:$src)>;
2424 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4f32 addr:$src)))),
2425 (MOVZQI2PQIrm addr:$src)>;
2426 def : Pat<(v2i64 (X86vzload addr:$src)), (MOVZQI2PQIrm addr:$src)>;
2429 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2430 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2431 let AddedComplexity = 15 in
2432 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2433 "movq\t{$src, $dst|$dst, $src}",
2434 [(set VR128:$dst, (v2i64 (X86vzmovl (v2i64 VR128:$src))))]>,
2435 XS, Requires<[HasSSE2]>;
2437 let AddedComplexity = 20 in {
2438 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2439 "movq\t{$src, $dst|$dst, $src}",
2440 [(set VR128:$dst, (v2i64 (X86vzmovl
2441 (loadv2i64 addr:$src))))]>,
2442 XS, Requires<[HasSSE2]>;
2444 def : Pat<(v2i64 (X86vzmovl (bc_v2i64 (loadv4i32 addr:$src)))),
2445 (MOVZPQILo2PQIrm addr:$src)>;
2448 // Instructions for the disassembler
2449 // xr = XMM register
2452 def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2453 "movq\t{$src, $dst|$dst, $src}", []>, XS;
2455 //===---------------------------------------------------------------------===//
2456 // SSE3 Instructions
2457 //===---------------------------------------------------------------------===//
2459 // Move Instructions
2460 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2461 "movshdup\t{$src, $dst|$dst, $src}",
2462 [(set VR128:$dst, (v4f32 (movshdup
2463 VR128:$src, (undef))))]>;
2464 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2465 "movshdup\t{$src, $dst|$dst, $src}",
2466 [(set VR128:$dst, (movshdup
2467 (memopv4f32 addr:$src), (undef)))]>;
2469 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2470 "movsldup\t{$src, $dst|$dst, $src}",
2471 [(set VR128:$dst, (v4f32 (movsldup
2472 VR128:$src, (undef))))]>;
2473 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2474 "movsldup\t{$src, $dst|$dst, $src}",
2475 [(set VR128:$dst, (movsldup
2476 (memopv4f32 addr:$src), (undef)))]>;
2478 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2479 "movddup\t{$src, $dst|$dst, $src}",
2480 [(set VR128:$dst,(v2f64 (movddup VR128:$src, (undef))))]>;
2481 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2482 "movddup\t{$src, $dst|$dst, $src}",
2484 (v2f64 (movddup (scalar_to_vector (loadf64 addr:$src)),
2487 def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
2489 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2491 let AddedComplexity = 5 in {
2492 def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
2493 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2494 def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
2495 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2496 def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
2497 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2498 def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
2499 (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
2503 let Constraints = "$src1 = $dst" in {
2504 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2505 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2506 "addsubps\t{$src2, $dst|$dst, $src2}",
2507 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2509 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2510 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2511 "addsubps\t{$src2, $dst|$dst, $src2}",
2512 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2513 (memop addr:$src2)))]>;
2514 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2515 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2516 "addsubpd\t{$src2, $dst|$dst, $src2}",
2517 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2519 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2520 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2521 "addsubpd\t{$src2, $dst|$dst, $src2}",
2522 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2523 (memop addr:$src2)))]>;
2526 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2527 "lddqu\t{$src, $dst|$dst, $src}",
2528 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2531 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2532 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2533 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2534 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2535 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2536 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2537 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2538 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (memop addr:$src2))))]>;
2539 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2540 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2541 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2542 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2543 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2544 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2545 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2546 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (memopv2f64 addr:$src2))))]>;
2548 let Constraints = "$src1 = $dst" in {
2549 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2550 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2551 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2552 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2553 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2554 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2555 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2556 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2559 // Thread synchronization
2560 def MONITOR : I<0x01, MRM_C8, (outs), (ins), "monitor",
2561 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2562 def MWAIT : I<0x01, MRM_C9, (outs), (ins), "mwait",
2563 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2565 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2566 let AddedComplexity = 15 in
2567 def : Pat<(v4i32 (movshdup VR128:$src, (undef))),
2568 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2569 let AddedComplexity = 20 in
2570 def : Pat<(v4i32 (movshdup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2571 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2573 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2574 let AddedComplexity = 15 in
2575 def : Pat<(v4i32 (movsldup VR128:$src, (undef))),
2576 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2577 let AddedComplexity = 20 in
2578 def : Pat<(v4i32 (movsldup (bc_v4i32 (memopv2i64 addr:$src)), (undef))),
2579 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2581 //===---------------------------------------------------------------------===//
2582 // SSSE3 Instructions
2583 //===---------------------------------------------------------------------===//
2585 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2586 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2587 Intrinsic IntId64, Intrinsic IntId128> {
2588 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2589 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2590 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2592 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2593 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2595 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2597 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2599 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2600 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2603 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2605 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2608 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2611 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2612 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2613 Intrinsic IntId64, Intrinsic IntId128> {
2614 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2616 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2617 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2619 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2621 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2624 (bitconvert (memopv4i16 addr:$src))))]>;
2626 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2628 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2629 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2632 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2634 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2637 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2640 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2641 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2642 Intrinsic IntId64, Intrinsic IntId128> {
2643 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2645 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2646 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2648 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2650 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2653 (bitconvert (memopv2i32 addr:$src))))]>;
2655 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2657 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2658 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2661 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2663 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2666 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2669 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2670 int_x86_ssse3_pabs_b,
2671 int_x86_ssse3_pabs_b_128>;
2672 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2673 int_x86_ssse3_pabs_w,
2674 int_x86_ssse3_pabs_w_128>;
2675 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2676 int_x86_ssse3_pabs_d,
2677 int_x86_ssse3_pabs_d_128>;
2679 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2680 let Constraints = "$src1 = $dst" in {
2681 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2682 Intrinsic IntId64, Intrinsic IntId128,
2683 bit Commutable = 0> {
2684 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2685 (ins VR64:$src1, VR64:$src2),
2686 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2687 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2688 let isCommutable = Commutable;
2690 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2691 (ins VR64:$src1, i64mem:$src2),
2692 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2694 (IntId64 VR64:$src1,
2695 (bitconvert (memopv8i8 addr:$src2))))]>;
2697 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2698 (ins VR128:$src1, VR128:$src2),
2699 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2700 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2702 let isCommutable = Commutable;
2704 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2705 (ins VR128:$src1, i128mem:$src2),
2706 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2708 (IntId128 VR128:$src1,
2709 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2713 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2714 let Constraints = "$src1 = $dst" in {
2715 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2716 Intrinsic IntId64, Intrinsic IntId128,
2717 bit Commutable = 0> {
2718 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2719 (ins VR64:$src1, VR64:$src2),
2720 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2721 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2722 let isCommutable = Commutable;
2724 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2725 (ins VR64:$src1, i64mem:$src2),
2726 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2728 (IntId64 VR64:$src1,
2729 (bitconvert (memopv4i16 addr:$src2))))]>;
2731 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2732 (ins VR128:$src1, VR128:$src2),
2733 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2734 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2736 let isCommutable = Commutable;
2738 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2739 (ins VR128:$src1, i128mem:$src2),
2740 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2742 (IntId128 VR128:$src1,
2743 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2747 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2748 let Constraints = "$src1 = $dst" in {
2749 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2750 Intrinsic IntId64, Intrinsic IntId128,
2751 bit Commutable = 0> {
2752 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2753 (ins VR64:$src1, VR64:$src2),
2754 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2755 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2756 let isCommutable = Commutable;
2758 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2759 (ins VR64:$src1, i64mem:$src2),
2760 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2762 (IntId64 VR64:$src1,
2763 (bitconvert (memopv2i32 addr:$src2))))]>;
2765 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2766 (ins VR128:$src1, VR128:$src2),
2767 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2768 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2770 let isCommutable = Commutable;
2772 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2773 (ins VR128:$src1, i128mem:$src2),
2774 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2776 (IntId128 VR128:$src1,
2777 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2781 let ImmT = NoImm in { // None of these have i8 immediate fields.
2782 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2783 int_x86_ssse3_phadd_w,
2784 int_x86_ssse3_phadd_w_128>;
2785 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2786 int_x86_ssse3_phadd_d,
2787 int_x86_ssse3_phadd_d_128>;
2788 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2789 int_x86_ssse3_phadd_sw,
2790 int_x86_ssse3_phadd_sw_128>;
2791 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2792 int_x86_ssse3_phsub_w,
2793 int_x86_ssse3_phsub_w_128>;
2794 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2795 int_x86_ssse3_phsub_d,
2796 int_x86_ssse3_phsub_d_128>;
2797 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2798 int_x86_ssse3_phsub_sw,
2799 int_x86_ssse3_phsub_sw_128>;
2800 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2801 int_x86_ssse3_pmadd_ub_sw,
2802 int_x86_ssse3_pmadd_ub_sw_128>;
2803 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2804 int_x86_ssse3_pmul_hr_sw,
2805 int_x86_ssse3_pmul_hr_sw_128, 1>;
2807 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2808 int_x86_ssse3_pshuf_b,
2809 int_x86_ssse3_pshuf_b_128>;
2810 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2811 int_x86_ssse3_psign_b,
2812 int_x86_ssse3_psign_b_128>;
2813 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2814 int_x86_ssse3_psign_w,
2815 int_x86_ssse3_psign_w_128>;
2816 defm PSIGND : SS3I_binop_rm_int_32<0x0A, "psignd",
2817 int_x86_ssse3_psign_d,
2818 int_x86_ssse3_psign_d_128>;
2821 // palignr patterns.
2822 let Constraints = "$src1 = $dst" in {
2823 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2824 (ins VR64:$src1, VR64:$src2, i8imm:$src3),
2825 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2827 def PALIGNR64rm : SS3AI<0x0F, MRMSrcMem, (outs VR64:$dst),
2828 (ins VR64:$src1, i64mem:$src2, i8imm:$src3),
2829 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2832 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2833 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
2834 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2836 def PALIGNR128rm : SS3AI<0x0F, MRMSrcMem, (outs VR128:$dst),
2837 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
2838 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2842 let AddedComplexity = 5 in {
2844 def : Pat<(v1i64 (palign:$src3 VR64:$src1, VR64:$src2)),
2845 (PALIGNR64rr VR64:$src2, VR64:$src1,
2846 (SHUFFLE_get_palign_imm VR64:$src3))>,
2847 Requires<[HasSSSE3]>;
2848 def : Pat<(v2i32 (palign:$src3 VR64:$src1, VR64:$src2)),
2849 (PALIGNR64rr VR64:$src2, VR64:$src1,
2850 (SHUFFLE_get_palign_imm VR64:$src3))>,
2851 Requires<[HasSSSE3]>;
2852 def : Pat<(v2f32 (palign:$src3 VR64:$src1, VR64:$src2)),
2853 (PALIGNR64rr VR64:$src2, VR64:$src1,
2854 (SHUFFLE_get_palign_imm VR64:$src3))>,
2855 Requires<[HasSSSE3]>;
2856 def : Pat<(v4i16 (palign:$src3 VR64:$src1, VR64:$src2)),
2857 (PALIGNR64rr VR64:$src2, VR64:$src1,
2858 (SHUFFLE_get_palign_imm VR64:$src3))>,
2859 Requires<[HasSSSE3]>;
2860 def : Pat<(v8i8 (palign:$src3 VR64:$src1, VR64:$src2)),
2861 (PALIGNR64rr VR64:$src2, VR64:$src1,
2862 (SHUFFLE_get_palign_imm VR64:$src3))>,
2863 Requires<[HasSSSE3]>;
2865 def : Pat<(v4i32 (palign:$src3 VR128:$src1, VR128:$src2)),
2866 (PALIGNR128rr VR128:$src2, VR128:$src1,
2867 (SHUFFLE_get_palign_imm VR128:$src3))>,
2868 Requires<[HasSSSE3]>;
2869 def : Pat<(v4f32 (palign:$src3 VR128:$src1, VR128:$src2)),
2870 (PALIGNR128rr VR128:$src2, VR128:$src1,
2871 (SHUFFLE_get_palign_imm VR128:$src3))>,
2872 Requires<[HasSSSE3]>;
2873 def : Pat<(v8i16 (palign:$src3 VR128:$src1, VR128:$src2)),
2874 (PALIGNR128rr VR128:$src2, VR128:$src1,
2875 (SHUFFLE_get_palign_imm VR128:$src3))>,
2876 Requires<[HasSSSE3]>;
2877 def : Pat<(v16i8 (palign:$src3 VR128:$src1, VR128:$src2)),
2878 (PALIGNR128rr VR128:$src2, VR128:$src1,
2879 (SHUFFLE_get_palign_imm VR128:$src3))>,
2880 Requires<[HasSSSE3]>;
2883 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
2884 (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
2885 def : Pat<(X86pshufb VR128:$src, (bc_v16i8 (memopv2i64 addr:$mask))),
2886 (PSHUFBrm128 VR128:$src, addr:$mask)>, Requires<[HasSSSE3]>;
2888 //===---------------------------------------------------------------------===//
2889 // Non-Instruction Patterns
2890 //===---------------------------------------------------------------------===//
2892 // extload f32 -> f64. This matches load+fextend because we have a hack in
2893 // the isel (PreprocessForFPConvert) that can introduce loads after dag
2895 // Since these loads aren't folded into the fextend, we have to match it
2897 let Predicates = [HasSSE2] in
2898 def : Pat<(fextend (loadf32 addr:$src)),
2899 (CVTSS2SDrm addr:$src)>;
2902 let Predicates = [HasSSE2] in {
2903 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2904 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2905 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2906 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2907 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2908 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2909 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2910 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2911 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2912 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2913 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2914 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2915 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2916 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2917 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2918 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2919 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2920 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2921 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2922 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2923 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2924 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2925 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2926 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2927 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2928 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2929 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2930 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2931 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2932 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2935 // Move scalar to XMM zero-extended
2936 // movd to XMM register zero-extends
2937 let AddedComplexity = 15 in {
2938 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2939 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64:$src)))),
2940 (MOVSDrr (v2f64 (V_SET0PS)), FR64:$src)>;
2941 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32:$src)))),
2942 (MOVSSrr (v4f32 (V_SET0PS)), FR32:$src)>;
2943 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128:$src))),
2944 (MOVSSrr (v4f32 (V_SET0PS)),
2945 (f32 (EXTRACT_SUBREG (v4f32 VR128:$src), sub_ss)))>;
2946 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128:$src))),
2947 (MOVSSrr (v4i32 (V_SET0PI)),
2948 (EXTRACT_SUBREG (v4i32 VR128:$src), sub_ss))>;
2951 // Splat v2f64 / v2i64
2952 let AddedComplexity = 10 in {
2953 def : Pat<(splat_lo (v2f64 VR128:$src), (undef)),
2954 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2955 def : Pat<(unpckh (v2f64 VR128:$src), (undef)),
2956 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2957 def : Pat<(splat_lo (v2i64 VR128:$src), (undef)),
2958 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2959 def : Pat<(unpckh (v2i64 VR128:$src), (undef)),
2960 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2963 // Special unary SHUFPSrri case.
2964 def : Pat<(v4f32 (pshufd:$src3 VR128:$src1, (undef))),
2965 (SHUFPSrri VR128:$src1, VR128:$src1,
2966 (SHUFFLE_get_shuf_imm VR128:$src3))>;
2967 let AddedComplexity = 5 in
2968 def : Pat<(v4f32 (pshufd:$src2 VR128:$src1, (undef))),
2969 (PSHUFDri VR128:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2970 Requires<[HasSSE2]>;
2971 // Special unary SHUFPDrri case.
2972 def : Pat<(v2i64 (pshufd:$src3 VR128:$src1, (undef))),
2973 (SHUFPDrri VR128:$src1, VR128:$src1,
2974 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2975 Requires<[HasSSE2]>;
2976 // Special unary SHUFPDrri case.
2977 def : Pat<(v2f64 (pshufd:$src3 VR128:$src1, (undef))),
2978 (SHUFPDrri VR128:$src1, VR128:$src1,
2979 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2980 Requires<[HasSSE2]>;
2981 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2982 def : Pat<(pshufd:$src2 (bc_v4i32 (memopv4f32 addr:$src1)), (undef)),
2983 (PSHUFDmi addr:$src1, (SHUFFLE_get_shuf_imm VR128:$src2))>,
2984 Requires<[HasSSE2]>;
2986 // Special binary v4i32 shuffle cases with SHUFPS.
2987 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (v4i32 VR128:$src2))),
2988 (SHUFPSrri VR128:$src1, VR128:$src2,
2989 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2990 Requires<[HasSSE2]>;
2991 def : Pat<(v4i32 (shufp:$src3 VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)))),
2992 (SHUFPSrmi VR128:$src1, addr:$src2,
2993 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2994 Requires<[HasSSE2]>;
2995 // Special binary v2i64 shuffle cases using SHUFPDrri.
2996 def : Pat<(v2i64 (shufp:$src3 VR128:$src1, VR128:$src2)),
2997 (SHUFPDrri VR128:$src1, VR128:$src2,
2998 (SHUFFLE_get_shuf_imm VR128:$src3))>,
2999 Requires<[HasSSE2]>;
3001 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
3002 let AddedComplexity = 15 in {
3003 def : Pat<(v4i32 (unpckl_undef:$src2 VR128:$src, (undef))),
3004 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3005 Requires<[OptForSpeed, HasSSE2]>;
3006 def : Pat<(v4f32 (unpckl_undef:$src2 VR128:$src, (undef))),
3007 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3008 Requires<[OptForSpeed, HasSSE2]>;
3010 let AddedComplexity = 10 in {
3011 def : Pat<(v4f32 (unpckl_undef VR128:$src, (undef))),
3012 (UNPCKLPSrr VR128:$src, VR128:$src)>;
3013 def : Pat<(v16i8 (unpckl_undef VR128:$src, (undef))),
3014 (PUNPCKLBWrr VR128:$src, VR128:$src)>;
3015 def : Pat<(v8i16 (unpckl_undef VR128:$src, (undef))),
3016 (PUNPCKLWDrr VR128:$src, VR128:$src)>;
3017 def : Pat<(v4i32 (unpckl_undef VR128:$src, (undef))),
3018 (PUNPCKLDQrr VR128:$src, VR128:$src)>;
3021 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
3022 let AddedComplexity = 15 in {
3023 def : Pat<(v4i32 (unpckh_undef:$src2 VR128:$src, (undef))),
3024 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3025 Requires<[OptForSpeed, HasSSE2]>;
3026 def : Pat<(v4f32 (unpckh_undef:$src2 VR128:$src, (undef))),
3027 (PSHUFDri VR128:$src, (SHUFFLE_get_shuf_imm VR128:$src2))>,
3028 Requires<[OptForSpeed, HasSSE2]>;
3030 let AddedComplexity = 10 in {
3031 def : Pat<(v4f32 (unpckh_undef VR128:$src, (undef))),
3032 (UNPCKHPSrr VR128:$src, VR128:$src)>;
3033 def : Pat<(v16i8 (unpckh_undef VR128:$src, (undef))),
3034 (PUNPCKHBWrr VR128:$src, VR128:$src)>;
3035 def : Pat<(v8i16 (unpckh_undef VR128:$src, (undef))),
3036 (PUNPCKHWDrr VR128:$src, VR128:$src)>;
3037 def : Pat<(v4i32 (unpckh_undef VR128:$src, (undef))),
3038 (PUNPCKHDQrr VR128:$src, VR128:$src)>;
3041 let AddedComplexity = 20 in {
3042 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
3043 def : Pat<(v4i32 (movlhps VR128:$src1, VR128:$src2)),
3044 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
3046 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
3047 def : Pat<(v4i32 (movhlps VR128:$src1, VR128:$src2)),
3048 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
3050 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
3051 def : Pat<(v4f32 (movhlps_undef VR128:$src1, (undef))),
3052 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3053 def : Pat<(v4i32 (movhlps_undef VR128:$src1, (undef))),
3054 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
3057 let AddedComplexity = 20 in {
3058 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
3059 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
3060 (MOVLPSrm VR128:$src1, addr:$src2)>;
3061 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
3062 (MOVLPDrm VR128:$src1, addr:$src2)>;
3063 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
3064 (MOVLPSrm VR128:$src1, addr:$src2)>;
3065 def : Pat<(v2i64 (movlp VR128:$src1, (load addr:$src2))),
3066 (MOVLPDrm VR128:$src1, addr:$src2)>;
3069 // (store (vector_shuffle (load addr), v2, <4, 5, 2, 3>), addr) using MOVLPS
3070 def : Pat<(store (v4f32 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3071 (MOVLPSmr addr:$src1, VR128:$src2)>;
3072 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3073 (MOVLPDmr addr:$src1, VR128:$src2)>;
3074 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),
3076 (MOVLPSmr addr:$src1, VR128:$src2)>;
3077 def : Pat<(store (v2i64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
3078 (MOVLPDmr addr:$src1, VR128:$src2)>;
3080 let AddedComplexity = 15 in {
3081 // Setting the lowest element in the vector.
3082 def : Pat<(v4i32 (movl VR128:$src1, VR128:$src2)),
3083 (MOVSSrr (v4i32 VR128:$src1),
3084 (EXTRACT_SUBREG (v4i32 VR128:$src2), sub_ss))>;
3085 def : Pat<(v2i64 (movl VR128:$src1, VR128:$src2)),
3086 (MOVSDrr (v2i64 VR128:$src1),
3087 (EXTRACT_SUBREG (v2i64 VR128:$src2), sub_sd))>;
3089 // vector_shuffle v1, v2 <4, 5, 2, 3> using movsd
3090 def : Pat<(v4f32 (movlp VR128:$src1, VR128:$src2)),
3091 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3092 Requires<[HasSSE2]>;
3093 def : Pat<(v4i32 (movlp VR128:$src1, VR128:$src2)),
3094 (MOVSDrr VR128:$src1, (EXTRACT_SUBREG VR128:$src2, sub_sd))>,
3095 Requires<[HasSSE2]>;
3098 // vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
3099 // fall back to this for SSE1)
3100 def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
3101 (SHUFPSrri VR128:$src2, VR128:$src1,
3102 (SHUFFLE_get_shuf_imm VR128:$src3))>;
3104 // Set lowest element and zero upper elements.
3105 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128:$src))),
3106 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
3108 // Some special case pandn patterns.
3109 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3111 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3112 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3114 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3115 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3117 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
3119 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
3120 (memop addr:$src2))),
3121 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3122 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
3123 (memop addr:$src2))),
3124 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3125 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
3126 (memop addr:$src2))),
3127 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
3129 // vector -> vector casts
3130 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
3131 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
3132 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
3133 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3134 def : Pat<(v2f64 (sint_to_fp (v2i32 VR64:$src))),
3135 (Int_CVTPI2PDrr VR64:$src)>, Requires<[HasSSE2]>;
3136 def : Pat<(v2i32 (fp_to_sint (v2f64 VR128:$src))),
3137 (Int_CVTTPD2PIrr VR128:$src)>, Requires<[HasSSE2]>;
3139 // Use movaps / movups for SSE integer load / store (one byte shorter).
3140 def : Pat<(alignedloadv4i32 addr:$src),
3141 (MOVAPSrm addr:$src)>;
3142 def : Pat<(loadv4i32 addr:$src),
3143 (MOVUPSrm addr:$src)>;
3144 def : Pat<(alignedloadv2i64 addr:$src),
3145 (MOVAPSrm addr:$src)>;
3146 def : Pat<(loadv2i64 addr:$src),
3147 (MOVUPSrm addr:$src)>;
3149 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3150 (MOVAPSmr addr:$dst, VR128:$src)>;
3151 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3152 (MOVAPSmr addr:$dst, VR128:$src)>;
3153 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3154 (MOVAPSmr addr:$dst, VR128:$src)>;
3155 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3156 (MOVAPSmr addr:$dst, VR128:$src)>;
3157 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3158 (MOVUPSmr addr:$dst, VR128:$src)>;
3159 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3160 (MOVUPSmr addr:$dst, VR128:$src)>;
3161 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3162 (MOVUPSmr addr:$dst, VR128:$src)>;
3163 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3164 (MOVUPSmr addr:$dst, VR128:$src)>;
3166 //===----------------------------------------------------------------------===//
3167 // SSE4.1 Instructions
3168 //===----------------------------------------------------------------------===//
3170 multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
3173 Intrinsic V2F64Int> {
3174 // Intrinsic operation, reg.
3175 // Vector intrinsic operation, reg
3176 def PSr_Int : SS4AIi8<opcps, MRMSrcReg,
3177 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3178 !strconcat(OpcodeStr,
3179 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3180 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3183 // Vector intrinsic operation, mem
3184 def PSm_Int : Ii8<opcps, MRMSrcMem,
3185 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3186 !strconcat(OpcodeStr,
3187 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3189 (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>,
3191 Requires<[HasSSE41]>;
3193 // Vector intrinsic operation, reg
3194 def PDr_Int : SS4AIi8<opcpd, MRMSrcReg,
3195 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3196 !strconcat(OpcodeStr,
3197 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3198 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3201 // Vector intrinsic operation, mem
3202 def PDm_Int : SS4AIi8<opcpd, MRMSrcMem,
3203 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3204 !strconcat(OpcodeStr,
3205 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3207 (V2F64Int (memopv2f64 addr:$src1),imm:$src2))]>,
3211 let Constraints = "$src1 = $dst" in {
3212 multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
3216 // Intrinsic operation, reg.
3217 def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
3219 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3220 !strconcat(OpcodeStr,
3221 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3223 (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3226 // Intrinsic operation, mem.
3227 def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
3229 (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
3230 !strconcat(OpcodeStr,
3231 "ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3233 (F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
3236 // Intrinsic operation, reg.
3237 def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
3239 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3240 !strconcat(OpcodeStr,
3241 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3243 (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
3246 // Intrinsic operation, mem.
3247 def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
3249 (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
3250 !strconcat(OpcodeStr,
3251 "sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3253 (F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
3258 // FP round - roundss, roundps, roundsd, roundpd
3259 defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
3260 int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
3261 defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
3262 int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
3264 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3265 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3266 Intrinsic IntId128> {
3267 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3269 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3270 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3271 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3273 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3276 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3279 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3280 int_x86_sse41_phminposuw>;
3282 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3283 let Constraints = "$src1 = $dst" in {
3284 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3285 Intrinsic IntId128, bit Commutable = 0> {
3286 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3287 (ins VR128:$src1, VR128:$src2),
3288 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3289 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3291 let isCommutable = Commutable;
3293 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3294 (ins VR128:$src1, i128mem:$src2),
3295 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3297 (IntId128 VR128:$src1,
3298 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3302 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3303 int_x86_sse41_pcmpeqq, 1>;
3304 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3305 int_x86_sse41_packusdw, 0>;
3306 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3307 int_x86_sse41_pminsb, 1>;
3308 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3309 int_x86_sse41_pminsd, 1>;
3310 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3311 int_x86_sse41_pminud, 1>;
3312 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3313 int_x86_sse41_pminuw, 1>;
3314 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3315 int_x86_sse41_pmaxsb, 1>;
3316 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3317 int_x86_sse41_pmaxsd, 1>;
3318 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3319 int_x86_sse41_pmaxud, 1>;
3320 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3321 int_x86_sse41_pmaxuw, 1>;
3323 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
3325 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
3326 (PCMPEQQrr VR128:$src1, VR128:$src2)>;
3327 def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
3328 (PCMPEQQrm VR128:$src1, addr:$src2)>;
3330 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3331 let Constraints = "$src1 = $dst" in {
3332 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
3333 SDNode OpNode, Intrinsic IntId128,
3334 bit Commutable = 0> {
3335 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3336 (ins VR128:$src1, VR128:$src2),
3337 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3338 [(set VR128:$dst, (OpNode (OpVT VR128:$src1),
3339 VR128:$src2))]>, OpSize {
3340 let isCommutable = Commutable;
3342 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3343 (ins VR128:$src1, VR128:$src2),
3344 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3345 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3347 let isCommutable = Commutable;
3349 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3350 (ins VR128:$src1, i128mem:$src2),
3351 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3353 (OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
3354 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3355 (ins VR128:$src1, i128mem:$src2),
3356 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3358 (IntId128 VR128:$src1, (memop addr:$src2)))]>,
3363 /// SS48I_binop_rm - Simple SSE41 binary operator.
3364 let Constraints = "$src1 = $dst" in {
3365 multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3366 ValueType OpVT, bit Commutable = 0> {
3367 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3368 (ins VR128:$src1, VR128:$src2),
3369 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3370 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
3372 let isCommutable = Commutable;
3374 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3375 (ins VR128:$src1, i128mem:$src2),
3376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3377 [(set VR128:$dst, (OpNode VR128:$src1,
3378 (bc_v4i32 (memopv2i64 addr:$src2))))]>,
3383 defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
3385 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
3386 let Constraints = "$src1 = $dst" in {
3387 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3388 Intrinsic IntId128, bit Commutable = 0> {
3389 def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3390 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3391 !strconcat(OpcodeStr,
3392 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3394 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3396 let isCommutable = Commutable;
3398 def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3399 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3400 !strconcat(OpcodeStr,
3401 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3403 (IntId128 VR128:$src1,
3404 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3409 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3410 int_x86_sse41_blendps, 0>;
3411 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3412 int_x86_sse41_blendpd, 0>;
3413 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3414 int_x86_sse41_pblendw, 0>;
3415 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3416 int_x86_sse41_dpps, 1>;
3417 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3418 int_x86_sse41_dppd, 1>;
3419 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3420 int_x86_sse41_mpsadbw, 0>;
3423 /// SS41I_ternary_int - SSE 4.1 ternary operator
3424 let Uses = [XMM0], Constraints = "$src1 = $dst" in {
3425 multiclass SS41I_ternary_int<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3426 def rr0 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3427 (ins VR128:$src1, VR128:$src2),
3428 !strconcat(OpcodeStr,
3429 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3430 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2, XMM0))]>,
3433 def rm0 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3434 (ins VR128:$src1, i128mem:$src2),
3435 !strconcat(OpcodeStr,
3436 "\t{%xmm0, $src2, $dst|$dst, $src2, %xmm0}"),
3439 (bitconvert (memopv16i8 addr:$src2)), XMM0))]>, OpSize;
3443 defm BLENDVPD : SS41I_ternary_int<0x15, "blendvpd", int_x86_sse41_blendvpd>;
3444 defm BLENDVPS : SS41I_ternary_int<0x14, "blendvps", int_x86_sse41_blendvps>;
3445 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
3448 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3449 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3450 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3451 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3453 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3454 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3456 (IntId (bitconvert (v2i64 (scalar_to_vector (loadi64 addr:$src))))))]>,
3460 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3461 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3462 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3463 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3464 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3465 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3467 // Common patterns involving scalar load.
3468 def : Pat<(int_x86_sse41_pmovsxbw (vzmovl_v2i64 addr:$src)),
3469 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3470 def : Pat<(int_x86_sse41_pmovsxbw (vzload_v2i64 addr:$src)),
3471 (PMOVSXBWrm addr:$src)>, Requires<[HasSSE41]>;
3473 def : Pat<(int_x86_sse41_pmovsxwd (vzmovl_v2i64 addr:$src)),
3474 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3475 def : Pat<(int_x86_sse41_pmovsxwd (vzload_v2i64 addr:$src)),
3476 (PMOVSXWDrm addr:$src)>, Requires<[HasSSE41]>;
3478 def : Pat<(int_x86_sse41_pmovsxdq (vzmovl_v2i64 addr:$src)),
3479 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3480 def : Pat<(int_x86_sse41_pmovsxdq (vzload_v2i64 addr:$src)),
3481 (PMOVSXDQrm addr:$src)>, Requires<[HasSSE41]>;
3483 def : Pat<(int_x86_sse41_pmovzxbw (vzmovl_v2i64 addr:$src)),
3484 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3485 def : Pat<(int_x86_sse41_pmovzxbw (vzload_v2i64 addr:$src)),
3486 (PMOVZXBWrm addr:$src)>, Requires<[HasSSE41]>;
3488 def : Pat<(int_x86_sse41_pmovzxwd (vzmovl_v2i64 addr:$src)),
3489 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3490 def : Pat<(int_x86_sse41_pmovzxwd (vzload_v2i64 addr:$src)),
3491 (PMOVZXWDrm addr:$src)>, Requires<[HasSSE41]>;
3493 def : Pat<(int_x86_sse41_pmovzxdq (vzmovl_v2i64 addr:$src)),
3494 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3495 def : Pat<(int_x86_sse41_pmovzxdq (vzload_v2i64 addr:$src)),
3496 (PMOVZXDQrm addr:$src)>, Requires<[HasSSE41]>;
3499 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3500 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3501 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3502 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3504 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3505 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3507 (IntId (bitconvert (v4i32 (scalar_to_vector (loadi32 addr:$src))))))]>,
3511 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3512 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3513 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3514 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3516 // Common patterns involving scalar load
3517 def : Pat<(int_x86_sse41_pmovsxbd (vzmovl_v4i32 addr:$src)),
3518 (PMOVSXBDrm addr:$src)>, Requires<[HasSSE41]>;
3519 def : Pat<(int_x86_sse41_pmovsxwq (vzmovl_v4i32 addr:$src)),
3520 (PMOVSXWQrm addr:$src)>, Requires<[HasSSE41]>;
3522 def : Pat<(int_x86_sse41_pmovzxbd (vzmovl_v4i32 addr:$src)),
3523 (PMOVZXBDrm addr:$src)>, Requires<[HasSSE41]>;
3524 def : Pat<(int_x86_sse41_pmovzxwq (vzmovl_v4i32 addr:$src)),
3525 (PMOVZXWQrm addr:$src)>, Requires<[HasSSE41]>;
3528 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3529 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3530 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3531 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3533 // Expecting a i16 load any extended to i32 value.
3534 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3535 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3536 [(set VR128:$dst, (IntId (bitconvert
3537 (v4i32 (scalar_to_vector (loadi16_anyext addr:$src))))))]>,
3541 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3542 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovzxbq", int_x86_sse41_pmovzxbq>;
3544 // Common patterns involving scalar load
3545 def : Pat<(int_x86_sse41_pmovsxbq
3546 (bitconvert (v4i32 (X86vzmovl
3547 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3548 (PMOVSXBQrm addr:$src)>, Requires<[HasSSE41]>;
3550 def : Pat<(int_x86_sse41_pmovzxbq
3551 (bitconvert (v4i32 (X86vzmovl
3552 (v4i32 (scalar_to_vector (loadi32 addr:$src))))))),
3553 (PMOVZXBQrm addr:$src)>, Requires<[HasSSE41]>;
3556 /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem
3557 multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {
3558 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3559 (ins VR128:$src1, i32i8imm:$src2),
3560 !strconcat(OpcodeStr,
3561 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3562 [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,
3564 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3565 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3566 !strconcat(OpcodeStr,
3567 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3570 // There's an AssertZext in the way of writing the store pattern
3571 // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3574 defm PEXTRB : SS41I_extract8<0x14, "pextrb">;
3577 /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination
3578 multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {
3579 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3580 (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2),
3581 !strconcat(OpcodeStr,
3582 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3585 // There's an AssertZext in the way of writing the store pattern
3586 // (store (i16 (trunc (X86pextrw (v16i8 VR128:$src1), imm:$src2))), addr:$dst)
3589 defm PEXTRW : SS41I_extract16<0x15, "pextrw">;
3592 /// SS41I_extract32 - SSE 4.1 extract 32 bits to int reg or memory destination
3593 multiclass SS41I_extract32<bits<8> opc, string OpcodeStr> {
3594 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3595 (ins VR128:$src1, i32i8imm:$src2),
3596 !strconcat(OpcodeStr,
3597 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3599 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3600 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3601 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3602 !strconcat(OpcodeStr,
3603 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3604 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3605 addr:$dst)]>, OpSize;
3608 defm PEXTRD : SS41I_extract32<0x16, "pextrd">;
3611 /// SS41I_extractf32 - SSE 4.1 extract 32 bits fp value to int reg or memory
3613 multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr> {
3614 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
3615 (ins VR128:$src1, i32i8imm:$src2),
3616 !strconcat(OpcodeStr,
3617 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3619 (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))]>,
3621 def mr : SS4AIi8<opc, MRMDestMem, (outs),
3622 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3623 !strconcat(OpcodeStr,
3624 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3625 [(store (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2),
3626 addr:$dst)]>, OpSize;
3629 defm EXTRACTPS : SS41I_extractf32<0x17, "extractps">;
3631 // Also match an EXTRACTPS store when the store is done as f32 instead of i32.
3632 def : Pat<(store (f32 (bitconvert (extractelt (bc_v4i32 (v4f32 VR128:$src1)),
3635 (EXTRACTPSmr addr:$dst, VR128:$src1, imm:$src2)>,
3636 Requires<[HasSSE41]>;
3638 let Constraints = "$src1 = $dst" in {
3639 multiclass SS41I_insert8<bits<8> opc, string OpcodeStr> {
3640 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3641 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3642 !strconcat(OpcodeStr,
3643 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3645 (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;
3646 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3647 (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),
3648 !strconcat(OpcodeStr,
3649 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3651 (X86pinsrb VR128:$src1, (extloadi8 addr:$src2),
3652 imm:$src3))]>, OpSize;
3656 defm PINSRB : SS41I_insert8<0x20, "pinsrb">;
3658 let Constraints = "$src1 = $dst" in {
3659 multiclass SS41I_insert32<bits<8> opc, string OpcodeStr> {
3660 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3661 (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),
3662 !strconcat(OpcodeStr,
3663 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3665 (v4i32 (insertelt VR128:$src1, GR32:$src2, imm:$src3)))]>,
3667 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3668 (ins VR128:$src1, i32mem:$src2, i32i8imm:$src3),
3669 !strconcat(OpcodeStr,
3670 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3672 (v4i32 (insertelt VR128:$src1, (loadi32 addr:$src2),
3673 imm:$src3)))]>, OpSize;
3677 defm PINSRD : SS41I_insert32<0x22, "pinsrd">;
3679 // insertps has a few different modes, there's the first two here below which
3680 // are optimized inserts that won't zero arbitrary elements in the destination
3681 // vector. The next one matches the intrinsic and could zero arbitrary elements
3682 // in the target vector.
3683 let Constraints = "$src1 = $dst" in {
3684 multiclass SS41I_insertf32<bits<8> opc, string OpcodeStr> {
3685 def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
3686 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3687 !strconcat(OpcodeStr,
3688 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3690 (X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,
3692 def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
3693 (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),
3694 !strconcat(OpcodeStr,
3695 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
3697 (X86insrtps VR128:$src1,
3698 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
3699 imm:$src3))]>, OpSize;
3703 defm INSERTPS : SS41I_insertf32<0x21, "insertps">;
3705 def : Pat<(int_x86_sse41_insertps VR128:$src1, VR128:$src2, imm:$src3),
3706 (INSERTPSrr VR128:$src1, VR128:$src2, imm:$src3)>;
3708 // ptest instruction we'll lower to this in X86ISelLowering primarily from
3709 // the intel intrinsic that corresponds to this.
3710 let Defs = [EFLAGS] in {
3711 def PTESTrr : SS48I<0x17, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
3712 "ptest \t{$src2, $src1|$src1, $src2}",
3713 [(set EFLAGS, (X86ptest VR128:$src1, VR128:$src2))]>,
3715 def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
3716 "ptest \t{$src2, $src1|$src1, $src2}",
3717 [(set EFLAGS, (X86ptest VR128:$src1, (load addr:$src2)))]>,
3721 def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
3722 "movntdqa\t{$src, $dst|$dst, $src}",
3723 [(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>,
3727 //===----------------------------------------------------------------------===//
3728 // SSE4.2 Instructions
3729 //===----------------------------------------------------------------------===//
3731 /// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
3732 let Constraints = "$src1 = $dst" in {
3733 multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
3734 Intrinsic IntId128, bit Commutable = 0> {
3735 def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
3736 (ins VR128:$src1, VR128:$src2),
3737 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3738 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3740 let isCommutable = Commutable;
3742 def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
3743 (ins VR128:$src1, i128mem:$src2),
3744 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3746 (IntId128 VR128:$src1,
3747 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3751 defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
3753 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
3754 (PCMPGTQrr VR128:$src1, VR128:$src2)>;
3755 def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
3756 (PCMPGTQrm VR128:$src1, addr:$src2)>;
3758 // crc intrinsic instruction
3759 // This set of instructions are only rm, the only difference is the size
3761 let Constraints = "$src1 = $dst" in {
3762 def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst),
3763 (ins GR32:$src1, i8mem:$src2),
3764 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3766 (int_x86_sse42_crc32_8 GR32:$src1,
3767 (load addr:$src2)))]>;
3768 def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst),
3769 (ins GR32:$src1, GR8:$src2),
3770 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3772 (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>;
3773 def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3774 (ins GR32:$src1, i16mem:$src2),
3775 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3777 (int_x86_sse42_crc32_16 GR32:$src1,
3778 (load addr:$src2)))]>,
3780 def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3781 (ins GR32:$src1, GR16:$src2),
3782 "crc32{w} \t{$src2, $src1|$src1, $src2}",
3784 (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>,
3786 def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst),
3787 (ins GR32:$src1, i32mem:$src2),
3788 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3790 (int_x86_sse42_crc32_32 GR32:$src1,
3791 (load addr:$src2)))]>;
3792 def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst),
3793 (ins GR32:$src1, GR32:$src2),
3794 "crc32{l} \t{$src2, $src1|$src1, $src2}",
3796 (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>;
3797 def CRC64m8 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst),
3798 (ins GR64:$src1, i8mem:$src2),
3799 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3801 (int_x86_sse42_crc64_8 GR64:$src1,
3802 (load addr:$src2)))]>,
3804 def CRC64r8 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst),
3805 (ins GR64:$src1, GR8:$src2),
3806 "crc32{b} \t{$src2, $src1|$src1, $src2}",
3808 (int_x86_sse42_crc64_8 GR64:$src1, GR8:$src2))]>,
3810 def CRC64m64 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst),
3811 (ins GR64:$src1, i64mem:$src2),
3812 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3814 (int_x86_sse42_crc64_64 GR64:$src1,
3815 (load addr:$src2)))]>,
3817 def CRC64r64 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst),
3818 (ins GR64:$src1, GR64:$src2),
3819 "crc32{q} \t{$src2, $src1|$src1, $src2}",
3821 (int_x86_sse42_crc64_64 GR64:$src1, GR64:$src2))]>,
3825 // String/text processing instructions.
3826 let Defs = [EFLAGS], usesCustomInserter = 1 in {
3827 def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3828 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3829 "#PCMPISTRM128rr PSEUDO!",
3830 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
3831 imm:$src3))]>, OpSize;
3832 def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3833 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3834 "#PCMPISTRM128rm PSEUDO!",
3835 [(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
3836 imm:$src3))]>, OpSize;
3839 let Defs = [XMM0, EFLAGS] in {
3840 def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
3841 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3842 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3843 def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
3844 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3845 "pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
3848 let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
3849 def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
3850 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3851 "#PCMPESTRM128rr PSEUDO!",
3853 (int_x86_sse42_pcmpestrm128
3854 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
3856 def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
3857 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3858 "#PCMPESTRM128rm PSEUDO!",
3859 [(set VR128:$dst, (int_x86_sse42_pcmpestrm128
3860 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
3864 let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
3865 def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
3866 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3867 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3868 def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
3869 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3870 "pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
3873 let Defs = [ECX, EFLAGS] in {
3874 multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
3875 def rr : SS42AI<0x63, MRMSrcReg, (outs),
3876 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
3877 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3878 [(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
3879 (implicit EFLAGS)]>, OpSize;
3880 def rm : SS42AI<0x63, MRMSrcMem, (outs),
3881 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
3882 "pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
3883 [(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
3884 (implicit EFLAGS)]>, OpSize;
3888 defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
3889 defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
3890 defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
3891 defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
3892 defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
3893 defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
3895 let Defs = [ECX, EFLAGS] in {
3896 let Uses = [EAX, EDX] in {
3897 multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
3898 def rr : SS42AI<0x61, MRMSrcReg, (outs),
3899 (ins VR128:$src1, VR128:$src3, i8imm:$src5),
3900 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3901 [(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
3902 (implicit EFLAGS)]>, OpSize;
3903 def rm : SS42AI<0x61, MRMSrcMem, (outs),
3904 (ins VR128:$src1, i128mem:$src3, i8imm:$src5),
3905 "pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
3907 (IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
3908 (implicit EFLAGS)]>, OpSize;
3913 defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
3914 defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
3915 defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
3916 defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
3917 defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
3918 defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
3920 //===----------------------------------------------------------------------===//
3921 // AES-NI Instructions
3922 //===----------------------------------------------------------------------===//
3924 let Constraints = "$src1 = $dst" in {
3925 multiclass AESI_binop_rm_int<bits<8> opc, string OpcodeStr,
3926 Intrinsic IntId128, bit Commutable = 0> {
3927 def rr : AES8I<opc, MRMSrcReg, (outs VR128:$dst),
3928 (ins VR128:$src1, VR128:$src2),
3929 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3930 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3932 let isCommutable = Commutable;
3934 def rm : AES8I<opc, MRMSrcMem, (outs VR128:$dst),
3935 (ins VR128:$src1, i128mem:$src2),
3936 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3938 (IntId128 VR128:$src1,
3939 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3943 defm AESENC : AESI_binop_rm_int<0xDC, "aesenc",
3944 int_x86_aesni_aesenc>;
3945 defm AESENCLAST : AESI_binop_rm_int<0xDD, "aesenclast",
3946 int_x86_aesni_aesenclast>;
3947 defm AESDEC : AESI_binop_rm_int<0xDE, "aesdec",
3948 int_x86_aesni_aesdec>;
3949 defm AESDECLAST : AESI_binop_rm_int<0xDF, "aesdeclast",
3950 int_x86_aesni_aesdeclast>;
3952 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, VR128:$src2)),
3953 (AESENCrr VR128:$src1, VR128:$src2)>;
3954 def : Pat<(v2i64 (int_x86_aesni_aesenc VR128:$src1, (memop addr:$src2))),
3955 (AESENCrm VR128:$src1, addr:$src2)>;
3956 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, VR128:$src2)),
3957 (AESENCLASTrr VR128:$src1, VR128:$src2)>;
3958 def : Pat<(v2i64 (int_x86_aesni_aesenclast VR128:$src1, (memop addr:$src2))),
3959 (AESENCLASTrm VR128:$src1, addr:$src2)>;
3960 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, VR128:$src2)),
3961 (AESDECrr VR128:$src1, VR128:$src2)>;
3962 def : Pat<(v2i64 (int_x86_aesni_aesdec VR128:$src1, (memop addr:$src2))),
3963 (AESDECrm VR128:$src1, addr:$src2)>;
3964 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, VR128:$src2)),
3965 (AESDECLASTrr VR128:$src1, VR128:$src2)>;
3966 def : Pat<(v2i64 (int_x86_aesni_aesdeclast VR128:$src1, (memop addr:$src2))),
3967 (AESDECLASTrm VR128:$src1, addr:$src2)>;
3969 def AESIMCrr : AES8I<0xDB, MRMSrcReg, (outs VR128:$dst),
3971 "aesimc\t{$src1, $dst|$dst, $src1}",
3973 (int_x86_aesni_aesimc VR128:$src1))]>,
3976 def AESIMCrm : AES8I<0xDB, MRMSrcMem, (outs VR128:$dst),
3977 (ins i128mem:$src1),
3978 "aesimc\t{$src1, $dst|$dst, $src1}",
3980 (int_x86_aesni_aesimc (bitconvert (memopv2i64 addr:$src1))))]>,
3983 def AESKEYGENASSIST128rr : AESAI<0xDF, MRMSrcReg, (outs VR128:$dst),
3984 (ins VR128:$src1, i8imm:$src2),
3985 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3987 (int_x86_aesni_aeskeygenassist VR128:$src1, imm:$src2))]>,
3989 def AESKEYGENASSIST128rm : AESAI<0xDF, MRMSrcMem, (outs VR128:$dst),
3990 (ins i128mem:$src1, i8imm:$src2),
3991 "aeskeygenassist\t{$src2, $src1, $dst|$dst, $src1, $src2}",
3993 (int_x86_aesni_aeskeygenassist (bitconvert (memopv2i64 addr:$src1)),