1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 SSE instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
17 //===----------------------------------------------------------------------===//
18 // SSE specific DAG Nodes.
19 //===----------------------------------------------------------------------===//
21 def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
22 SDTCisFP<0>, SDTCisInt<2> ]>;
24 def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
25 def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
26 def X86fand : SDNode<"X86ISD::FAND", SDTFPBinOp,
27 [SDNPCommutative, SDNPAssociative]>;
28 def X86for : SDNode<"X86ISD::FOR", SDTFPBinOp,
29 [SDNPCommutative, SDNPAssociative]>;
30 def X86fxor : SDNode<"X86ISD::FXOR", SDTFPBinOp,
31 [SDNPCommutative, SDNPAssociative]>;
32 def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>;
33 def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>;
34 def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>;
35 def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>;
36 def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>;
37 def X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
38 def X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
39 def X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
41 //===----------------------------------------------------------------------===//
42 // SSE 'Special' Instructions
43 //===----------------------------------------------------------------------===//
45 let isImplicitDef = 1 in {
46 def IMPLICIT_DEF_VR128 : I<0, Pseudo, (outs VR128:$dst), (ins),
48 [(set VR128:$dst, (v4f32 (undef)))]>,
50 def IMPLICIT_DEF_FR32 : I<0, Pseudo, (outs FR32:$dst), (ins),
52 [(set FR32:$dst, (undef))]>, Requires<[HasSSE1]>;
53 def IMPLICIT_DEF_FR64 : I<0, Pseudo, (outs FR64:$dst), (ins),
55 [(set FR64:$dst, (undef))]>, Requires<[HasSSE2]>;
58 //===----------------------------------------------------------------------===//
59 // SSE Complex Patterns
60 //===----------------------------------------------------------------------===//
62 // These are 'extloads' from a scalar to the low element of a vector, zeroing
63 // the top elements. These are used for the SSE 'ss' and 'sd' instruction
65 def sse_load_f32 : ComplexPattern<v4f32, 4, "SelectScalarSSELoad", [],
66 [SDNPHasChain, SDNPMayLoad]>;
67 def sse_load_f64 : ComplexPattern<v2f64, 4, "SelectScalarSSELoad", [],
68 [SDNPHasChain, SDNPMayLoad]>;
70 def ssmem : Operand<v4f32> {
71 let PrintMethod = "printf32mem";
72 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
74 def sdmem : Operand<v2f64> {
75 let PrintMethod = "printf64mem";
76 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm);
79 //===----------------------------------------------------------------------===//
80 // SSE pattern fragments
81 //===----------------------------------------------------------------------===//
83 def loadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (load node:$ptr))>;
84 def loadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (load node:$ptr))>;
85 def loadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (load node:$ptr))>;
86 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
88 // Like 'store', but always requires vector alignment.
89 def alignedstore : PatFrag<(ops node:$val, node:$ptr),
90 (st node:$val, node:$ptr), [{
91 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N))
92 return !ST->isTruncatingStore() &&
93 ST->getAddressingMode() == ISD::UNINDEXED &&
94 ST->getAlignment() >= 16;
98 // Like 'load', but always requires vector alignment.
99 def alignedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
100 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
101 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
102 LD->getAddressingMode() == ISD::UNINDEXED &&
103 LD->getAlignment() >= 16;
107 def alignedloadfsf32 : PatFrag<(ops node:$ptr), (f32 (alignedload node:$ptr))>;
108 def alignedloadfsf64 : PatFrag<(ops node:$ptr), (f64 (alignedload node:$ptr))>;
109 def alignedloadv4f32 : PatFrag<(ops node:$ptr), (v4f32 (alignedload node:$ptr))>;
110 def alignedloadv2f64 : PatFrag<(ops node:$ptr), (v2f64 (alignedload node:$ptr))>;
111 def alignedloadv4i32 : PatFrag<(ops node:$ptr), (v4i32 (alignedload node:$ptr))>;
112 def alignedloadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (alignedload node:$ptr))>;
114 // Like 'load', but uses special alignment checks suitable for use in
115 // memory operands in most SSE instructions, which are required to
116 // be naturally aligned on some targets but not on others.
117 // FIXME: Actually implement support for targets that don't require the
118 // alignment. This probably wants a subtarget predicate.
119 def memop : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
120 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
121 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
122 LD->getAddressingMode() == ISD::UNINDEXED &&
123 LD->getAlignment() >= 16;
127 def memopfsf32 : PatFrag<(ops node:$ptr), (f32 (memop node:$ptr))>;
128 def memopfsf64 : PatFrag<(ops node:$ptr), (f64 (memop node:$ptr))>;
129 def memopv4f32 : PatFrag<(ops node:$ptr), (v4f32 (memop node:$ptr))>;
130 def memopv2f64 : PatFrag<(ops node:$ptr), (v2f64 (memop node:$ptr))>;
131 def memopv4i32 : PatFrag<(ops node:$ptr), (v4i32 (memop node:$ptr))>;
132 def memopv2i64 : PatFrag<(ops node:$ptr), (v2i64 (memop node:$ptr))>;
133 def memopv16i8 : PatFrag<(ops node:$ptr), (v16i8 (memop node:$ptr))>;
135 // SSSE3 uses MMX registers for some instructions. They aren't aligned on a
137 // FIXME: 8 byte alignment for mmx reads is not required
138 def memop64 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
139 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
140 return LD->getExtensionType() == ISD::NON_EXTLOAD &&
141 LD->getAddressingMode() == ISD::UNINDEXED &&
142 LD->getAlignment() >= 8;
146 def memopv8i8 : PatFrag<(ops node:$ptr), (v8i8 (memop64 node:$ptr))>;
147 def memopv4i16 : PatFrag<(ops node:$ptr), (v4i16 (memop64 node:$ptr))>;
148 def memopv8i16 : PatFrag<(ops node:$ptr), (v8i16 (memop64 node:$ptr))>;
149 def memopv2i32 : PatFrag<(ops node:$ptr), (v2i32 (memop64 node:$ptr))>;
151 def bc_v4f32 : PatFrag<(ops node:$in), (v4f32 (bitconvert node:$in))>;
152 def bc_v2f64 : PatFrag<(ops node:$in), (v2f64 (bitconvert node:$in))>;
153 def bc_v16i8 : PatFrag<(ops node:$in), (v16i8 (bitconvert node:$in))>;
154 def bc_v8i16 : PatFrag<(ops node:$in), (v8i16 (bitconvert node:$in))>;
155 def bc_v4i32 : PatFrag<(ops node:$in), (v4i32 (bitconvert node:$in))>;
156 def bc_v2i64 : PatFrag<(ops node:$in), (v2i64 (bitconvert node:$in))>;
158 def fp32imm0 : PatLeaf<(f32 fpimm), [{
159 return N->isExactlyValue(+0.0);
162 def PSxLDQ_imm : SDNodeXForm<imm, [{
163 // Transformation function: imm >> 3
164 return getI32Imm(N->getValue() >> 3);
167 // SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
169 def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
170 return getI8Imm(X86::getShuffleSHUFImmediate(N));
173 // SHUFFLE_get_pshufhw_imm xform function: convert vector_shuffle mask to
175 def SHUFFLE_get_pshufhw_imm : SDNodeXForm<build_vector, [{
176 return getI8Imm(X86::getShufflePSHUFHWImmediate(N));
179 // SHUFFLE_get_pshuflw_imm xform function: convert vector_shuffle mask to
181 def SHUFFLE_get_pshuflw_imm : SDNodeXForm<build_vector, [{
182 return getI8Imm(X86::getShufflePSHUFLWImmediate(N));
185 def SSE_splat_mask : PatLeaf<(build_vector), [{
186 return X86::isSplatMask(N);
187 }], SHUFFLE_get_shuf_imm>;
189 def SSE_splat_lo_mask : PatLeaf<(build_vector), [{
190 return X86::isSplatLoMask(N);
193 def MOVHLPS_shuffle_mask : PatLeaf<(build_vector), [{
194 return X86::isMOVHLPSMask(N);
197 def MOVHLPS_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
198 return X86::isMOVHLPS_v_undef_Mask(N);
201 def MOVHP_shuffle_mask : PatLeaf<(build_vector), [{
202 return X86::isMOVHPMask(N);
205 def MOVLP_shuffle_mask : PatLeaf<(build_vector), [{
206 return X86::isMOVLPMask(N);
209 def MOVL_shuffle_mask : PatLeaf<(build_vector), [{
210 return X86::isMOVLMask(N);
213 def MOVSHDUP_shuffle_mask : PatLeaf<(build_vector), [{
214 return X86::isMOVSHDUPMask(N);
217 def MOVSLDUP_shuffle_mask : PatLeaf<(build_vector), [{
218 return X86::isMOVSLDUPMask(N);
221 def UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
222 return X86::isUNPCKLMask(N);
225 def UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
226 return X86::isUNPCKHMask(N);
229 def UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
230 return X86::isUNPCKL_v_undef_Mask(N);
233 def UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
234 return X86::isUNPCKH_v_undef_Mask(N);
237 def PSHUFD_shuffle_mask : PatLeaf<(build_vector), [{
238 return X86::isPSHUFDMask(N);
239 }], SHUFFLE_get_shuf_imm>;
241 def PSHUFHW_shuffle_mask : PatLeaf<(build_vector), [{
242 return X86::isPSHUFHWMask(N);
243 }], SHUFFLE_get_pshufhw_imm>;
245 def PSHUFLW_shuffle_mask : PatLeaf<(build_vector), [{
246 return X86::isPSHUFLWMask(N);
247 }], SHUFFLE_get_pshuflw_imm>;
249 def SHUFP_unary_shuffle_mask : PatLeaf<(build_vector), [{
250 return X86::isPSHUFDMask(N);
251 }], SHUFFLE_get_shuf_imm>;
253 def SHUFP_shuffle_mask : PatLeaf<(build_vector), [{
254 return X86::isSHUFPMask(N);
255 }], SHUFFLE_get_shuf_imm>;
257 def PSHUFD_binary_shuffle_mask : PatLeaf<(build_vector), [{
258 return X86::isSHUFPMask(N);
259 }], SHUFFLE_get_shuf_imm>;
261 //===----------------------------------------------------------------------===//
262 // SSE scalar FP Instructions
263 //===----------------------------------------------------------------------===//
265 // CMOV* - Used to implement the SSE SELECT DAG operation. Expanded by the
266 // scheduler into a branch sequence.
267 // These are expanded by the scheduler.
268 let Uses = [EFLAGS], usesCustomDAGSchedInserter = 1 in {
269 def CMOV_FR32 : I<0, Pseudo,
270 (outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
271 "#CMOV_FR32 PSEUDO!",
272 [(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
274 def CMOV_FR64 : I<0, Pseudo,
275 (outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
276 "#CMOV_FR64 PSEUDO!",
277 [(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
279 def CMOV_V4F32 : I<0, Pseudo,
280 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
281 "#CMOV_V4F32 PSEUDO!",
283 (v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
285 def CMOV_V2F64 : I<0, Pseudo,
286 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
287 "#CMOV_V2F64 PSEUDO!",
289 (v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
291 def CMOV_V2I64 : I<0, Pseudo,
292 (outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
293 "#CMOV_V2I64 PSEUDO!",
295 (v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
299 //===----------------------------------------------------------------------===//
301 //===----------------------------------------------------------------------===//
304 let neverHasSideEffects = 1 in
305 def MOVSSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
306 "movss\t{$src, $dst|$dst, $src}", []>;
307 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
308 def MOVSSrm : SSI<0x10, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
309 "movss\t{$src, $dst|$dst, $src}",
310 [(set FR32:$dst, (loadf32 addr:$src))]>;
311 def MOVSSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, FR32:$src),
312 "movss\t{$src, $dst|$dst, $src}",
313 [(store FR32:$src, addr:$dst)]>;
315 // Conversion instructions
316 def CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
317 "cvttss2si\t{$src, $dst|$dst, $src}",
318 [(set GR32:$dst, (fp_to_sint FR32:$src))]>;
319 def CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
320 "cvttss2si\t{$src, $dst|$dst, $src}",
321 [(set GR32:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
322 def CVTSI2SSrr : SSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
323 "cvtsi2ss\t{$src, $dst|$dst, $src}",
324 [(set FR32:$dst, (sint_to_fp GR32:$src))]>;
325 def CVTSI2SSrm : SSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
326 "cvtsi2ss\t{$src, $dst|$dst, $src}",
327 [(set FR32:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
329 // Match intrinsics which expect XMM operand(s).
330 def Int_CVTSS2SIrr : SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
331 "cvtss2si\t{$src, $dst|$dst, $src}",
332 [(set GR32:$dst, (int_x86_sse_cvtss2si VR128:$src))]>;
333 def Int_CVTSS2SIrm : SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
334 "cvtss2si\t{$src, $dst|$dst, $src}",
335 [(set GR32:$dst, (int_x86_sse_cvtss2si
336 (load addr:$src)))]>;
338 // Match intrinisics which expect MM and XMM operand(s).
339 def Int_CVTPS2PIrr : PSI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
340 "cvtps2pi\t{$src, $dst|$dst, $src}",
341 [(set VR64:$dst, (int_x86_sse_cvtps2pi VR128:$src))]>;
342 def Int_CVTPS2PIrm : PSI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
343 "cvtps2pi\t{$src, $dst|$dst, $src}",
344 [(set VR64:$dst, (int_x86_sse_cvtps2pi
345 (load addr:$src)))]>;
346 def Int_CVTTPS2PIrr: PSI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
347 "cvttps2pi\t{$src, $dst|$dst, $src}",
348 [(set VR64:$dst, (int_x86_sse_cvttps2pi VR128:$src))]>;
349 def Int_CVTTPS2PIrm: PSI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f64mem:$src),
350 "cvttps2pi\t{$src, $dst|$dst, $src}",
351 [(set VR64:$dst, (int_x86_sse_cvttps2pi
352 (load addr:$src)))]>;
353 let isTwoAddress = 1 in {
354 def Int_CVTPI2PSrr : PSI<0x2A, MRMSrcReg,
355 (outs VR128:$dst), (ins VR128:$src1, VR64:$src2),
356 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
357 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
359 def Int_CVTPI2PSrm : PSI<0x2A, MRMSrcMem,
360 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
361 "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
362 [(set VR128:$dst, (int_x86_sse_cvtpi2ps VR128:$src1,
363 (load addr:$src2)))]>;
366 // Aliases for intrinsics
367 def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
368 "cvttss2si\t{$src, $dst|$dst, $src}",
370 (int_x86_sse_cvttss2si VR128:$src))]>;
371 def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
372 "cvttss2si\t{$src, $dst|$dst, $src}",
374 (int_x86_sse_cvttss2si(load addr:$src)))]>;
376 let isTwoAddress = 1 in {
377 def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
378 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
379 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
380 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
382 def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
383 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
384 "cvtsi2ss\t{$src2, $dst|$dst, $src2}",
385 [(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
386 (loadi32 addr:$src2)))]>;
389 // Comparison instructions
390 let isTwoAddress = 1 in {
391 let neverHasSideEffects = 1 in
392 def CMPSSrr : SSIi8<0xC2, MRMSrcReg,
393 (outs FR32:$dst), (ins FR32:$src1, FR32:$src, SSECC:$cc),
394 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
395 let neverHasSideEffects = 1, mayLoad = 1 in
396 def CMPSSrm : SSIi8<0xC2, MRMSrcMem,
397 (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, SSECC:$cc),
398 "cmp${cc}ss\t{$src, $dst|$dst, $src}", []>;
401 let Defs = [EFLAGS] in {
402 def UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs), (ins FR32:$src1, FR32:$src2),
403 "ucomiss\t{$src2, $src1|$src1, $src2}",
404 [(X86cmp FR32:$src1, FR32:$src2), (implicit EFLAGS)]>;
405 def UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs), (ins FR32:$src1, f32mem:$src2),
406 "ucomiss\t{$src2, $src1|$src1, $src2}",
407 [(X86cmp FR32:$src1, (loadf32 addr:$src2)),
411 // Aliases to match intrinsics which expect XMM operand(s).
412 let isTwoAddress = 1 in {
413 def Int_CMPSSrr : SSIi8<0xC2, MRMSrcReg,
414 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
415 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
416 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
417 VR128:$src, imm:$cc))]>;
418 def Int_CMPSSrm : SSIi8<0xC2, MRMSrcMem,
419 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src, SSECC:$cc),
420 "cmp${cc}ss\t{$src, $dst|$dst, $src}",
421 [(set VR128:$dst, (int_x86_sse_cmp_ss VR128:$src1,
422 (load addr:$src), imm:$cc))]>;
425 let Defs = [EFLAGS] in {
426 def Int_UCOMISSrr: PSI<0x2E, MRMSrcReg, (outs),
427 (ins VR128:$src1, VR128:$src2),
428 "ucomiss\t{$src2, $src1|$src1, $src2}",
429 [(X86ucomi (v4f32 VR128:$src1), VR128:$src2),
431 def Int_UCOMISSrm: PSI<0x2E, MRMSrcMem, (outs),
432 (ins VR128:$src1, f128mem:$src2),
433 "ucomiss\t{$src2, $src1|$src1, $src2}",
434 [(X86ucomi (v4f32 VR128:$src1), (load addr:$src2)),
437 def Int_COMISSrr: PSI<0x2F, MRMSrcReg, (outs),
438 (ins VR128:$src1, VR128:$src2),
439 "comiss\t{$src2, $src1|$src1, $src2}",
440 [(X86comi (v4f32 VR128:$src1), VR128:$src2),
442 def Int_COMISSrm: PSI<0x2F, MRMSrcMem, (outs),
443 (ins VR128:$src1, f128mem:$src2),
444 "comiss\t{$src2, $src1|$src1, $src2}",
445 [(X86comi (v4f32 VR128:$src1), (load addr:$src2)),
449 // Aliases of packed SSE1 instructions for scalar use. These all have names that
452 // Alias instructions that map fld0 to pxor for sse.
453 let isReMaterializable = 1 in
454 def FsFLD0SS : I<0xEF, MRMInitReg, (outs FR32:$dst), (ins),
455 "pxor\t$dst, $dst", [(set FR32:$dst, fp32imm0)]>,
456 Requires<[HasSSE1]>, TB, OpSize;
458 // Alias instruction to do FR32 reg-to-reg copy using movaps. Upper bits are
460 let neverHasSideEffects = 1 in
461 def FsMOVAPSrr : PSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
462 "movaps\t{$src, $dst|$dst, $src}", []>;
464 // Alias instruction to load FR32 from f128mem using movaps. Upper bits are
466 let isSimpleLoad = 1 in
467 def FsMOVAPSrm : PSI<0x28, MRMSrcMem, (outs FR32:$dst), (ins f128mem:$src),
468 "movaps\t{$src, $dst|$dst, $src}",
469 [(set FR32:$dst, (alignedloadfsf32 addr:$src))]>;
471 // Alias bitwise logical operations using SSE logical ops on packed FP values.
472 let isTwoAddress = 1 in {
473 let isCommutable = 1 in {
474 def FsANDPSrr : PSI<0x54, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
475 "andps\t{$src2, $dst|$dst, $src2}",
476 [(set FR32:$dst, (X86fand FR32:$src1, FR32:$src2))]>;
477 def FsORPSrr : PSI<0x56, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
478 "orps\t{$src2, $dst|$dst, $src2}",
479 [(set FR32:$dst, (X86for FR32:$src1, FR32:$src2))]>;
480 def FsXORPSrr : PSI<0x57, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
481 "xorps\t{$src2, $dst|$dst, $src2}",
482 [(set FR32:$dst, (X86fxor FR32:$src1, FR32:$src2))]>;
485 def FsANDPSrm : PSI<0x54, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
486 "andps\t{$src2, $dst|$dst, $src2}",
487 [(set FR32:$dst, (X86fand FR32:$src1,
488 (memopfsf32 addr:$src2)))]>;
489 def FsORPSrm : PSI<0x56, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
490 "orps\t{$src2, $dst|$dst, $src2}",
491 [(set FR32:$dst, (X86for FR32:$src1,
492 (memopfsf32 addr:$src2)))]>;
493 def FsXORPSrm : PSI<0x57, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
494 "xorps\t{$src2, $dst|$dst, $src2}",
495 [(set FR32:$dst, (X86fxor FR32:$src1,
496 (memopfsf32 addr:$src2)))]>;
497 let neverHasSideEffects = 1 in {
498 def FsANDNPSrr : PSI<0x55, MRMSrcReg,
499 (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
500 "andnps\t{$src2, $dst|$dst, $src2}", []>;
503 def FsANDNPSrm : PSI<0x55, MRMSrcMem,
504 (outs FR32:$dst), (ins FR32:$src1, f128mem:$src2),
505 "andnps\t{$src2, $dst|$dst, $src2}", []>;
509 /// basic_sse1_fp_binop_rm - SSE1 binops come in both scalar and vector forms.
511 /// In addition, we also have a special variant of the scalar form here to
512 /// represent the associated intrinsic operation. This form is unlike the
513 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
514 /// and leaves the top elements undefined.
516 /// These three forms can each be reg+reg or reg+mem, so there are a total of
517 /// six "instructions".
519 let isTwoAddress = 1 in {
520 multiclass basic_sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
521 SDNode OpNode, Intrinsic F32Int,
522 bit Commutable = 0> {
523 // Scalar operation, reg+reg.
524 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
525 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
526 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
527 let isCommutable = Commutable;
530 // Scalar operation, reg+mem.
531 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
532 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
533 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
535 // Vector operation, reg+reg.
536 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
537 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
538 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
539 let isCommutable = Commutable;
542 // Vector operation, reg+mem.
543 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
544 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
545 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
547 // Intrinsic operation, reg+reg.
548 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
549 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
550 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
551 let isCommutable = Commutable;
554 // Intrinsic operation, reg+mem.
555 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
556 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
557 [(set VR128:$dst, (F32Int VR128:$src1,
558 sse_load_f32:$src2))]>;
562 // Arithmetic instructions
563 defm ADD : basic_sse1_fp_binop_rm<0x58, "add", fadd, int_x86_sse_add_ss, 1>;
564 defm MUL : basic_sse1_fp_binop_rm<0x59, "mul", fmul, int_x86_sse_mul_ss, 1>;
565 defm SUB : basic_sse1_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse_sub_ss>;
566 defm DIV : basic_sse1_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse_div_ss>;
568 /// sse1_fp_binop_rm - Other SSE1 binops
570 /// This multiclass is like basic_sse1_fp_binop_rm, with the addition of
571 /// instructions for a full-vector intrinsic form. Operations that map
572 /// onto C operators don't use this form since they just use the plain
573 /// vector form instead of having a separate vector intrinsic form.
575 /// This provides a total of eight "instructions".
577 let isTwoAddress = 1 in {
578 multiclass sse1_fp_binop_rm<bits<8> opc, string OpcodeStr,
582 bit Commutable = 0> {
584 // Scalar operation, reg+reg.
585 def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
586 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
587 [(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
588 let isCommutable = Commutable;
591 // Scalar operation, reg+mem.
592 def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2),
593 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
594 [(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
596 // Vector operation, reg+reg.
597 def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
598 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
599 [(set VR128:$dst, (v4f32 (OpNode VR128:$src1, VR128:$src2)))]> {
600 let isCommutable = Commutable;
603 // Vector operation, reg+mem.
604 def PSrm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
605 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
606 [(set VR128:$dst, (OpNode VR128:$src1, (memopv4f32 addr:$src2)))]>;
608 // Intrinsic operation, reg+reg.
609 def SSrr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
610 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
611 [(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2))]> {
612 let isCommutable = Commutable;
615 // Intrinsic operation, reg+mem.
616 def SSrm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, ssmem:$src2),
617 !strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
618 [(set VR128:$dst, (F32Int VR128:$src1,
619 sse_load_f32:$src2))]>;
621 // Vector intrinsic operation, reg+reg.
622 def PSrr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
623 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
624 [(set VR128:$dst, (V4F32Int VR128:$src1, VR128:$src2))]> {
625 let isCommutable = Commutable;
628 // Vector intrinsic operation, reg+mem.
629 def PSrm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
630 !strconcat(OpcodeStr, "ps\t{$src2, $dst|$dst, $src2}"),
631 [(set VR128:$dst, (V4F32Int VR128:$src1, (load addr:$src2)))]>;
635 defm MAX : sse1_fp_binop_rm<0x5F, "max", X86fmax,
636 int_x86_sse_max_ss, int_x86_sse_max_ps>;
637 defm MIN : sse1_fp_binop_rm<0x5D, "min", X86fmin,
638 int_x86_sse_min_ss, int_x86_sse_min_ps>;
640 //===----------------------------------------------------------------------===//
641 // SSE packed FP Instructions
644 let neverHasSideEffects = 1 in
645 def MOVAPSrr : PSI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
646 "movaps\t{$src, $dst|$dst, $src}", []>;
647 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
648 def MOVAPSrm : PSI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
649 "movaps\t{$src, $dst|$dst, $src}",
650 [(set VR128:$dst, (alignedloadv4f32 addr:$src))]>;
652 def MOVAPSmr : PSI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
653 "movaps\t{$src, $dst|$dst, $src}",
654 [(alignedstore (v4f32 VR128:$src), addr:$dst)]>;
656 let neverHasSideEffects = 1 in
657 def MOVUPSrr : PSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
658 "movups\t{$src, $dst|$dst, $src}", []>;
659 let isSimpleLoad = 1 in
660 def MOVUPSrm : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
661 "movups\t{$src, $dst|$dst, $src}",
662 [(set VR128:$dst, (loadv4f32 addr:$src))]>;
663 def MOVUPSmr : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
664 "movups\t{$src, $dst|$dst, $src}",
665 [(store (v4f32 VR128:$src), addr:$dst)]>;
667 // Intrinsic forms of MOVUPS load and store
668 let isSimpleLoad = 1 in
669 def MOVUPSrm_Int : PSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
670 "movups\t{$src, $dst|$dst, $src}",
671 [(set VR128:$dst, (int_x86_sse_loadu_ps addr:$src))]>;
672 def MOVUPSmr_Int : PSI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
673 "movups\t{$src, $dst|$dst, $src}",
674 [(int_x86_sse_storeu_ps addr:$dst, VR128:$src)]>;
676 let isTwoAddress = 1 in {
677 let AddedComplexity = 20 in {
678 def MOVLPSrm : PSI<0x12, MRMSrcMem,
679 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
680 "movlps\t{$src2, $dst|$dst, $src2}",
682 (v4f32 (vector_shuffle VR128:$src1,
683 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
684 MOVLP_shuffle_mask)))]>;
685 def MOVHPSrm : PSI<0x16, MRMSrcMem,
686 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
687 "movhps\t{$src2, $dst|$dst, $src2}",
689 (v4f32 (vector_shuffle VR128:$src1,
690 (bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2)))),
691 MOVHP_shuffle_mask)))]>;
695 def MOVLPSmr : PSI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
696 "movlps\t{$src, $dst|$dst, $src}",
697 [(store (f64 (vector_extract (bc_v2f64 (v4f32 VR128:$src)),
698 (iPTR 0))), addr:$dst)]>;
700 // v2f64 extract element 1 is always custom lowered to unpack high to low
701 // and extract element 0 so the non-store version isn't too horrible.
702 def MOVHPSmr : PSI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
703 "movhps\t{$src, $dst|$dst, $src}",
704 [(store (f64 (vector_extract
705 (v2f64 (vector_shuffle
706 (bc_v2f64 (v4f32 VR128:$src)), (undef),
707 UNPCKH_shuffle_mask)), (iPTR 0))),
710 let isTwoAddress = 1 in {
711 let AddedComplexity = 15 in {
712 def MOVLHPSrr : PSI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
713 "movlhps\t{$src2, $dst|$dst, $src2}",
715 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
716 MOVHP_shuffle_mask)))]>;
718 def MOVHLPSrr : PSI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
719 "movhlps\t{$src2, $dst|$dst, $src2}",
721 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
722 MOVHLPS_shuffle_mask)))]>;
730 /// sse1_fp_unop_rm - SSE1 unops come in both scalar and vector forms.
732 /// In addition, we also have a special variant of the scalar form here to
733 /// represent the associated intrinsic operation. This form is unlike the
734 /// plain scalar form, in that it takes an entire vector (instead of a
735 /// scalar) and leaves the top elements undefined.
737 /// And, we have a special variant form for a full-vector intrinsic form.
739 /// These four forms can each have a reg or a mem operand, so there are a
740 /// total of eight "instructions".
742 multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr,
746 bit Commutable = 0> {
747 // Scalar operation, reg.
748 def SSr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src),
749 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
750 [(set FR32:$dst, (OpNode FR32:$src))]> {
751 let isCommutable = Commutable;
754 // Scalar operation, mem.
755 def SSm : SSI<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src),
756 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
757 [(set FR32:$dst, (OpNode (load addr:$src)))]>;
759 // Vector operation, reg.
760 def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
761 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
762 [(set VR128:$dst, (v4f32 (OpNode VR128:$src)))]> {
763 let isCommutable = Commutable;
766 // Vector operation, mem.
767 def PSm : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
768 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
769 [(set VR128:$dst, (OpNode (memopv4f32 addr:$src)))]>;
771 // Intrinsic operation, reg.
772 def SSr_Int : SSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
773 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
774 [(set VR128:$dst, (F32Int VR128:$src))]> {
775 let isCommutable = Commutable;
778 // Intrinsic operation, mem.
779 def SSm_Int : SSI<opc, MRMSrcMem, (outs VR128:$dst), (ins ssmem:$src),
780 !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"),
781 [(set VR128:$dst, (F32Int sse_load_f32:$src))]>;
783 // Vector intrinsic operation, reg
784 def PSr_Int : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
785 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
786 [(set VR128:$dst, (V4F32Int VR128:$src))]> {
787 let isCommutable = Commutable;
790 // Vector intrinsic operation, mem
791 def PSm_Int : PSI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
792 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
793 [(set VR128:$dst, (V4F32Int (load addr:$src)))]>;
797 defm SQRT : sse1_fp_unop_rm<0x51, "sqrt", fsqrt,
798 int_x86_sse_sqrt_ss, int_x86_sse_sqrt_ps>;
800 // Reciprocal approximations. Note that these typically require refinement
801 // in order to obtain suitable precision.
802 defm RSQRT : sse1_fp_unop_rm<0x52, "rsqrt", X86frsqrt,
803 int_x86_sse_rsqrt_ss, int_x86_sse_rsqrt_ps>;
804 defm RCP : sse1_fp_unop_rm<0x53, "rcp", X86frcp,
805 int_x86_sse_rcp_ss, int_x86_sse_rcp_ps>;
808 let isTwoAddress = 1 in {
809 let isCommutable = 1 in {
810 def ANDPSrr : PSI<0x54, MRMSrcReg,
811 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
812 "andps\t{$src2, $dst|$dst, $src2}",
813 [(set VR128:$dst, (v2i64
814 (and VR128:$src1, VR128:$src2)))]>;
815 def ORPSrr : PSI<0x56, MRMSrcReg,
816 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
817 "orps\t{$src2, $dst|$dst, $src2}",
818 [(set VR128:$dst, (v2i64
819 (or VR128:$src1, VR128:$src2)))]>;
820 def XORPSrr : PSI<0x57, MRMSrcReg,
821 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
822 "xorps\t{$src2, $dst|$dst, $src2}",
823 [(set VR128:$dst, (v2i64
824 (xor VR128:$src1, VR128:$src2)))]>;
827 def ANDPSrm : PSI<0x54, MRMSrcMem,
828 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
829 "andps\t{$src2, $dst|$dst, $src2}",
830 [(set VR128:$dst, (and (bc_v2i64 (v4f32 VR128:$src1)),
831 (memopv2i64 addr:$src2)))]>;
832 def ORPSrm : PSI<0x56, MRMSrcMem,
833 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
834 "orps\t{$src2, $dst|$dst, $src2}",
835 [(set VR128:$dst, (or (bc_v2i64 (v4f32 VR128:$src1)),
836 (memopv2i64 addr:$src2)))]>;
837 def XORPSrm : PSI<0x57, MRMSrcMem,
838 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
839 "xorps\t{$src2, $dst|$dst, $src2}",
840 [(set VR128:$dst, (xor (bc_v2i64 (v4f32 VR128:$src1)),
841 (memopv2i64 addr:$src2)))]>;
842 def ANDNPSrr : PSI<0x55, MRMSrcReg,
843 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
844 "andnps\t{$src2, $dst|$dst, $src2}",
846 (v2i64 (and (xor VR128:$src1,
847 (bc_v2i64 (v4i32 immAllOnesV))),
849 def ANDNPSrm : PSI<0x55, MRMSrcMem,
850 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
851 "andnps\t{$src2, $dst|$dst, $src2}",
853 (v2i64 (and (xor (bc_v2i64 (v4f32 VR128:$src1)),
854 (bc_v2i64 (v4i32 immAllOnesV))),
855 (memopv2i64 addr:$src2))))]>;
858 let isTwoAddress = 1 in {
859 def CMPPSrri : PSIi8<0xC2, MRMSrcReg,
860 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
861 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
862 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
863 VR128:$src, imm:$cc))]>;
864 def CMPPSrmi : PSIi8<0xC2, MRMSrcMem,
865 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
866 "cmp${cc}ps\t{$src, $dst|$dst, $src}",
867 [(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
868 (load addr:$src), imm:$cc))]>;
871 // Shuffle and unpack instructions
872 let isTwoAddress = 1 in {
873 let isConvertibleToThreeAddress = 1 in // Convert to pshufd
874 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg,
875 (outs VR128:$dst), (ins VR128:$src1,
876 VR128:$src2, i32i8imm:$src3),
877 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
879 (v4f32 (vector_shuffle
880 VR128:$src1, VR128:$src2,
881 SHUFP_shuffle_mask:$src3)))]>;
882 def SHUFPSrmi : PSIi8<0xC6, MRMSrcMem,
883 (outs VR128:$dst), (ins VR128:$src1,
884 f128mem:$src2, i32i8imm:$src3),
885 "shufps\t{$src3, $src2, $dst|$dst, $src2, $src3}",
887 (v4f32 (vector_shuffle
888 VR128:$src1, (memopv4f32 addr:$src2),
889 SHUFP_shuffle_mask:$src3)))]>;
891 let AddedComplexity = 10 in {
892 def UNPCKHPSrr : PSI<0x15, MRMSrcReg,
893 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
894 "unpckhps\t{$src2, $dst|$dst, $src2}",
896 (v4f32 (vector_shuffle
897 VR128:$src1, VR128:$src2,
898 UNPCKH_shuffle_mask)))]>;
899 def UNPCKHPSrm : PSI<0x15, MRMSrcMem,
900 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
901 "unpckhps\t{$src2, $dst|$dst, $src2}",
903 (v4f32 (vector_shuffle
904 VR128:$src1, (memopv4f32 addr:$src2),
905 UNPCKH_shuffle_mask)))]>;
907 def UNPCKLPSrr : PSI<0x14, MRMSrcReg,
908 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
909 "unpcklps\t{$src2, $dst|$dst, $src2}",
911 (v4f32 (vector_shuffle
912 VR128:$src1, VR128:$src2,
913 UNPCKL_shuffle_mask)))]>;
914 def UNPCKLPSrm : PSI<0x14, MRMSrcMem,
915 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
916 "unpcklps\t{$src2, $dst|$dst, $src2}",
918 (v4f32 (vector_shuffle
919 VR128:$src1, (memopv4f32 addr:$src2),
920 UNPCKL_shuffle_mask)))]>;
925 def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
926 "movmskps\t{$src, $dst|$dst, $src}",
927 [(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
928 def MOVMSKPDrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
929 "movmskpd\t{$src, $dst|$dst, $src}",
930 [(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
932 // Prefetching loads.
933 // TODO: no intrinsics for these?
934 def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src), "prefetcht0\t$src", []>;
935 def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src), "prefetcht1\t$src", []>;
936 def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src), "prefetcht2\t$src", []>;
937 def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src), "prefetchnta\t$src", []>;
939 // Non-temporal stores
940 def MOVNTPSmr : PSI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
941 "movntps\t{$src, $dst|$dst, $src}",
942 [(int_x86_sse_movnt_ps addr:$dst, VR128:$src)]>;
944 // Load, store, and memory fence
945 def SFENCE : PSI<0xAE, MRM7m, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>;
948 def LDMXCSR : PSI<0xAE, MRM2m, (outs), (ins i32mem:$src),
949 "ldmxcsr\t$src", [(int_x86_sse_ldmxcsr addr:$src)]>;
950 def STMXCSR : PSI<0xAE, MRM3m, (outs), (ins i32mem:$dst),
951 "stmxcsr\t$dst", [(int_x86_sse_stmxcsr addr:$dst)]>;
953 // Alias instructions that map zero vector to pxor / xorp* for sse.
954 let isReMaterializable = 1 in
955 def V_SET0 : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins),
957 [(set VR128:$dst, (v4i32 immAllZerosV))]>;
959 // FR32 to 128-bit vector conversion.
960 def MOVSS2PSrr : SSI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR32:$src),
961 "movss\t{$src, $dst|$dst, $src}",
963 (v4f32 (scalar_to_vector FR32:$src)))]>;
964 def MOVSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
965 "movss\t{$src, $dst|$dst, $src}",
967 (v4f32 (scalar_to_vector (loadf32 addr:$src))))]>;
969 // FIXME: may not be able to eliminate this movss with coalescing the src and
970 // dest register classes are different. We really want to write this pattern
972 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
974 def MOVPS2SSrr : SSI<0x10, MRMSrcReg, (outs FR32:$dst), (ins VR128:$src),
975 "movss\t{$src, $dst|$dst, $src}",
976 [(set FR32:$dst, (vector_extract (v4f32 VR128:$src),
978 def MOVPS2SSmr : SSI<0x11, MRMDestMem, (outs), (ins f32mem:$dst, VR128:$src),
979 "movss\t{$src, $dst|$dst, $src}",
980 [(store (f32 (vector_extract (v4f32 VR128:$src),
981 (iPTR 0))), addr:$dst)]>;
984 // Move to lower bits of a VR128, leaving upper bits alone.
985 // Three operand (but two address) aliases.
986 let isTwoAddress = 1 in {
987 let neverHasSideEffects = 1 in
988 def MOVLSS2PSrr : SSI<0x10, MRMSrcReg,
989 (outs VR128:$dst), (ins VR128:$src1, FR32:$src2),
990 "movss\t{$src2, $dst|$dst, $src2}", []>;
992 let AddedComplexity = 15 in
993 def MOVLPSrr : SSI<0x10, MRMSrcReg,
994 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
995 "movss\t{$src2, $dst|$dst, $src2}",
997 (v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
998 MOVL_shuffle_mask)))]>;
1001 // Move to lower bits of a VR128 and zeroing upper bits.
1002 // Loading from memory automatically zeroing upper bits.
1003 let AddedComplexity = 20 in
1004 def MOVZSS2PSrm : SSI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f32mem:$src),
1005 "movss\t{$src, $dst|$dst, $src}",
1006 [(set VR128:$dst, (v4f32 (vector_shuffle immAllZerosV_bc,
1007 (v4f32 (scalar_to_vector (loadf32 addr:$src))),
1008 MOVL_shuffle_mask)))]>;
1011 //===----------------------------------------------------------------------===//
1012 // SSE2 Instructions
1013 //===----------------------------------------------------------------------===//
1015 // Move Instructions
1016 let neverHasSideEffects = 1 in
1017 def MOVSDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1018 "movsd\t{$src, $dst|$dst, $src}", []>;
1019 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1020 def MOVSDrm : SDI<0x10, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1021 "movsd\t{$src, $dst|$dst, $src}",
1022 [(set FR64:$dst, (loadf64 addr:$src))]>;
1023 def MOVSDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, FR64:$src),
1024 "movsd\t{$src, $dst|$dst, $src}",
1025 [(store FR64:$src, addr:$dst)]>;
1027 // Conversion instructions
1028 def CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src),
1029 "cvttsd2si\t{$src, $dst|$dst, $src}",
1030 [(set GR32:$dst, (fp_to_sint FR64:$src))]>;
1031 def CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f64mem:$src),
1032 "cvttsd2si\t{$src, $dst|$dst, $src}",
1033 [(set GR32:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
1034 def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src),
1035 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1036 [(set FR32:$dst, (fround FR64:$src))]>;
1037 def CVTSD2SSrm : SDI<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src),
1038 "cvtsd2ss\t{$src, $dst|$dst, $src}",
1039 [(set FR32:$dst, (fround (loadf64 addr:$src)))]>;
1040 def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src),
1041 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1042 [(set FR64:$dst, (sint_to_fp GR32:$src))]>;
1043 def CVTSI2SDrm : SDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i32mem:$src),
1044 "cvtsi2sd\t{$src, $dst|$dst, $src}",
1045 [(set FR64:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
1047 // SSE2 instructions with XS prefix
1048 def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src),
1049 "cvtss2sd\t{$src, $dst|$dst, $src}",
1050 [(set FR64:$dst, (fextend FR32:$src))]>, XS,
1051 Requires<[HasSSE2]>;
1052 def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src),
1053 "cvtss2sd\t{$src, $dst|$dst, $src}",
1054 [(set FR64:$dst, (extloadf32 addr:$src))]>, XS,
1055 Requires<[HasSSE2]>;
1057 // Match intrinsics which expect XMM operand(s).
1058 def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1059 "cvtsd2si\t{$src, $dst|$dst, $src}",
1060 [(set GR32:$dst, (int_x86_sse2_cvtsd2si VR128:$src))]>;
1061 def Int_CVTSD2SIrm : SDI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1062 "cvtsd2si\t{$src, $dst|$dst, $src}",
1063 [(set GR32:$dst, (int_x86_sse2_cvtsd2si
1064 (load addr:$src)))]>;
1066 // Match intrinisics which expect MM and XMM operand(s).
1067 def Int_CVTPD2PIrr : PDI<0x2D, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1068 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1069 [(set VR64:$dst, (int_x86_sse_cvtpd2pi VR128:$src))]>;
1070 def Int_CVTPD2PIrm : PDI<0x2D, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1071 "cvtpd2pi\t{$src, $dst|$dst, $src}",
1072 [(set VR64:$dst, (int_x86_sse_cvtpd2pi
1073 (load addr:$src)))]>;
1074 def Int_CVTTPD2PIrr: PDI<0x2C, MRMSrcReg, (outs VR64:$dst), (ins VR128:$src),
1075 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1076 [(set VR64:$dst, (int_x86_sse_cvttpd2pi VR128:$src))]>;
1077 def Int_CVTTPD2PIrm: PDI<0x2C, MRMSrcMem, (outs VR64:$dst), (ins f128mem:$src),
1078 "cvttpd2pi\t{$src, $dst|$dst, $src}",
1079 [(set VR64:$dst, (int_x86_sse_cvttpd2pi
1080 (load addr:$src)))]>;
1081 def Int_CVTPI2PDrr : PDI<0x2A, MRMSrcReg, (outs VR128:$dst), (ins VR64:$src),
1082 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1083 [(set VR128:$dst, (int_x86_sse_cvtpi2pd VR64:$src))]>;
1084 def Int_CVTPI2PDrm : PDI<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1085 "cvtpi2pd\t{$src, $dst|$dst, $src}",
1086 [(set VR128:$dst, (int_x86_sse_cvtpi2pd
1087 (load addr:$src)))]>;
1089 // Aliases for intrinsics
1090 def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
1091 "cvttsd2si\t{$src, $dst|$dst, $src}",
1093 (int_x86_sse2_cvttsd2si VR128:$src))]>;
1094 def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
1095 "cvttsd2si\t{$src, $dst|$dst, $src}",
1096 [(set GR32:$dst, (int_x86_sse2_cvttsd2si
1097 (load addr:$src)))]>;
1099 // Comparison instructions
1100 let isTwoAddress = 1, neverHasSideEffects = 1 in {
1101 def CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1102 (outs FR64:$dst), (ins FR64:$src1, FR64:$src, SSECC:$cc),
1103 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1105 def CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1106 (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, SSECC:$cc),
1107 "cmp${cc}sd\t{$src, $dst|$dst, $src}", []>;
1110 let Defs = [EFLAGS] in {
1111 def UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins FR64:$src1, FR64:$src2),
1112 "ucomisd\t{$src2, $src1|$src1, $src2}",
1113 [(X86cmp FR64:$src1, FR64:$src2), (implicit EFLAGS)]>;
1114 def UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs), (ins FR64:$src1, f64mem:$src2),
1115 "ucomisd\t{$src2, $src1|$src1, $src2}",
1116 [(X86cmp FR64:$src1, (loadf64 addr:$src2)),
1117 (implicit EFLAGS)]>;
1120 // Aliases to match intrinsics which expect XMM operand(s).
1121 let isTwoAddress = 1 in {
1122 def Int_CMPSDrr : SDIi8<0xC2, MRMSrcReg,
1123 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1124 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1125 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1126 VR128:$src, imm:$cc))]>;
1127 def Int_CMPSDrm : SDIi8<0xC2, MRMSrcMem,
1128 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src, SSECC:$cc),
1129 "cmp${cc}sd\t{$src, $dst|$dst, $src}",
1130 [(set VR128:$dst, (int_x86_sse2_cmp_sd VR128:$src1,
1131 (load addr:$src), imm:$cc))]>;
1134 let Defs = [EFLAGS] in {
1135 def Int_UCOMISDrr: PDI<0x2E, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1136 "ucomisd\t{$src2, $src1|$src1, $src2}",
1137 [(X86ucomi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1138 (implicit EFLAGS)]>;
1139 def Int_UCOMISDrm: PDI<0x2E, MRMSrcMem, (outs),(ins VR128:$src1, f128mem:$src2),
1140 "ucomisd\t{$src2, $src1|$src1, $src2}",
1141 [(X86ucomi (v2f64 VR128:$src1), (load addr:$src2)),
1142 (implicit EFLAGS)]>;
1144 def Int_COMISDrr: PDI<0x2F, MRMSrcReg, (outs), (ins VR128:$src1, VR128:$src2),
1145 "comisd\t{$src2, $src1|$src1, $src2}",
1146 [(X86comi (v2f64 VR128:$src1), (v2f64 VR128:$src2)),
1147 (implicit EFLAGS)]>;
1148 def Int_COMISDrm: PDI<0x2F, MRMSrcMem, (outs), (ins VR128:$src1, f128mem:$src2),
1149 "comisd\t{$src2, $src1|$src1, $src2}",
1150 [(X86comi (v2f64 VR128:$src1), (load addr:$src2)),
1151 (implicit EFLAGS)]>;
1154 // Aliases of packed SSE2 instructions for scalar use. These all have names that
1157 // Alias instructions that map fld0 to pxor for sse.
1158 let isReMaterializable = 1 in
1159 def FsFLD0SD : I<0xEF, MRMInitReg, (outs FR64:$dst), (ins),
1160 "pxor\t$dst, $dst", [(set FR64:$dst, fpimm0)]>,
1161 Requires<[HasSSE2]>, TB, OpSize;
1163 // Alias instruction to do FR64 reg-to-reg copy using movapd. Upper bits are
1165 let neverHasSideEffects = 1 in
1166 def FsMOVAPDrr : PDI<0x28, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1167 "movapd\t{$src, $dst|$dst, $src}", []>;
1169 // Alias instruction to load FR64 from f128mem using movapd. Upper bits are
1171 let isSimpleLoad = 1 in
1172 def FsMOVAPDrm : PDI<0x28, MRMSrcMem, (outs FR64:$dst), (ins f128mem:$src),
1173 "movapd\t{$src, $dst|$dst, $src}",
1174 [(set FR64:$dst, (alignedloadfsf64 addr:$src))]>;
1176 // Alias bitwise logical operations using SSE logical ops on packed FP values.
1177 let isTwoAddress = 1 in {
1178 let isCommutable = 1 in {
1179 def FsANDPDrr : PDI<0x54, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1180 "andpd\t{$src2, $dst|$dst, $src2}",
1181 [(set FR64:$dst, (X86fand FR64:$src1, FR64:$src2))]>;
1182 def FsORPDrr : PDI<0x56, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1183 "orpd\t{$src2, $dst|$dst, $src2}",
1184 [(set FR64:$dst, (X86for FR64:$src1, FR64:$src2))]>;
1185 def FsXORPDrr : PDI<0x57, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1186 "xorpd\t{$src2, $dst|$dst, $src2}",
1187 [(set FR64:$dst, (X86fxor FR64:$src1, FR64:$src2))]>;
1190 def FsANDPDrm : PDI<0x54, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1191 "andpd\t{$src2, $dst|$dst, $src2}",
1192 [(set FR64:$dst, (X86fand FR64:$src1,
1193 (memopfsf64 addr:$src2)))]>;
1194 def FsORPDrm : PDI<0x56, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1195 "orpd\t{$src2, $dst|$dst, $src2}",
1196 [(set FR64:$dst, (X86for FR64:$src1,
1197 (memopfsf64 addr:$src2)))]>;
1198 def FsXORPDrm : PDI<0x57, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1199 "xorpd\t{$src2, $dst|$dst, $src2}",
1200 [(set FR64:$dst, (X86fxor FR64:$src1,
1201 (memopfsf64 addr:$src2)))]>;
1203 let neverHasSideEffects = 1 in {
1204 def FsANDNPDrr : PDI<0x55, MRMSrcReg,
1205 (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1206 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1208 def FsANDNPDrm : PDI<0x55, MRMSrcMem,
1209 (outs FR64:$dst), (ins FR64:$src1, f128mem:$src2),
1210 "andnpd\t{$src2, $dst|$dst, $src2}", []>;
1214 /// basic_sse2_fp_binop_rm - SSE2 binops come in both scalar and vector forms.
1216 /// In addition, we also have a special variant of the scalar form here to
1217 /// represent the associated intrinsic operation. This form is unlike the
1218 /// plain scalar form, in that it takes an entire vector (instead of a scalar)
1219 /// and leaves the top elements undefined.
1221 /// These three forms can each be reg+reg or reg+mem, so there are a total of
1222 /// six "instructions".
1224 let isTwoAddress = 1 in {
1225 multiclass basic_sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1226 SDNode OpNode, Intrinsic F64Int,
1227 bit Commutable = 0> {
1228 // Scalar operation, reg+reg.
1229 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1230 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1231 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1232 let isCommutable = Commutable;
1235 // Scalar operation, reg+mem.
1236 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1237 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1238 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1240 // Vector operation, reg+reg.
1241 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1242 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1243 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1244 let isCommutable = Commutable;
1247 // Vector operation, reg+mem.
1248 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1249 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1250 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1252 // Intrinsic operation, reg+reg.
1253 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1254 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1255 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1256 let isCommutable = Commutable;
1259 // Intrinsic operation, reg+mem.
1260 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1261 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1262 [(set VR128:$dst, (F64Int VR128:$src1,
1263 sse_load_f64:$src2))]>;
1267 // Arithmetic instructions
1268 defm ADD : basic_sse2_fp_binop_rm<0x58, "add", fadd, int_x86_sse2_add_sd, 1>;
1269 defm MUL : basic_sse2_fp_binop_rm<0x59, "mul", fmul, int_x86_sse2_mul_sd, 1>;
1270 defm SUB : basic_sse2_fp_binop_rm<0x5C, "sub", fsub, int_x86_sse2_sub_sd>;
1271 defm DIV : basic_sse2_fp_binop_rm<0x5E, "div", fdiv, int_x86_sse2_div_sd>;
1273 /// sse2_fp_binop_rm - Other SSE2 binops
1275 /// This multiclass is like basic_sse2_fp_binop_rm, with the addition of
1276 /// instructions for a full-vector intrinsic form. Operations that map
1277 /// onto C operators don't use this form since they just use the plain
1278 /// vector form instead of having a separate vector intrinsic form.
1280 /// This provides a total of eight "instructions".
1282 let isTwoAddress = 1 in {
1283 multiclass sse2_fp_binop_rm<bits<8> opc, string OpcodeStr,
1287 bit Commutable = 0> {
1289 // Scalar operation, reg+reg.
1290 def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
1291 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1292 [(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
1293 let isCommutable = Commutable;
1296 // Scalar operation, reg+mem.
1297 def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2),
1298 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1299 [(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
1301 // Vector operation, reg+reg.
1302 def PDrr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1303 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1304 [(set VR128:$dst, (v2f64 (OpNode VR128:$src1, VR128:$src2)))]> {
1305 let isCommutable = Commutable;
1308 // Vector operation, reg+mem.
1309 def PDrm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1310 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1311 [(set VR128:$dst, (OpNode VR128:$src1, (memopv2f64 addr:$src2)))]>;
1313 // Intrinsic operation, reg+reg.
1314 def SDrr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1315 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1316 [(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2))]> {
1317 let isCommutable = Commutable;
1320 // Intrinsic operation, reg+mem.
1321 def SDrm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, sdmem:$src2),
1322 !strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
1323 [(set VR128:$dst, (F64Int VR128:$src1,
1324 sse_load_f64:$src2))]>;
1326 // Vector intrinsic operation, reg+reg.
1327 def PDrr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1328 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1329 [(set VR128:$dst, (V2F64Int VR128:$src1, VR128:$src2))]> {
1330 let isCommutable = Commutable;
1333 // Vector intrinsic operation, reg+mem.
1334 def PDrm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1335 !strconcat(OpcodeStr, "pd\t{$src2, $dst|$dst, $src2}"),
1336 [(set VR128:$dst, (V2F64Int VR128:$src1, (load addr:$src2)))]>;
1340 defm MAX : sse2_fp_binop_rm<0x5F, "max", X86fmax,
1341 int_x86_sse2_max_sd, int_x86_sse2_max_pd>;
1342 defm MIN : sse2_fp_binop_rm<0x5D, "min", X86fmin,
1343 int_x86_sse2_min_sd, int_x86_sse2_min_pd>;
1345 //===----------------------------------------------------------------------===//
1346 // SSE packed FP Instructions
1348 // Move Instructions
1349 let neverHasSideEffects = 1 in
1350 def MOVAPDrr : PDI<0x28, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1351 "movapd\t{$src, $dst|$dst, $src}", []>;
1352 let isSimpleLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
1353 def MOVAPDrm : PDI<0x28, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1354 "movapd\t{$src, $dst|$dst, $src}",
1355 [(set VR128:$dst, (alignedloadv2f64 addr:$src))]>;
1357 def MOVAPDmr : PDI<0x29, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1358 "movapd\t{$src, $dst|$dst, $src}",
1359 [(alignedstore (v2f64 VR128:$src), addr:$dst)]>;
1361 let neverHasSideEffects = 1 in
1362 def MOVUPDrr : PDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1363 "movupd\t{$src, $dst|$dst, $src}", []>;
1364 let isSimpleLoad = 1 in
1365 def MOVUPDrm : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1366 "movupd\t{$src, $dst|$dst, $src}",
1367 [(set VR128:$dst, (loadv2f64 addr:$src))]>;
1368 def MOVUPDmr : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1369 "movupd\t{$src, $dst|$dst, $src}",
1370 [(store (v2f64 VR128:$src), addr:$dst)]>;
1372 // Intrinsic forms of MOVUPD load and store
1373 def MOVUPDrm_Int : PDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1374 "movupd\t{$src, $dst|$dst, $src}",
1375 [(set VR128:$dst, (int_x86_sse2_loadu_pd addr:$src))]>;
1376 def MOVUPDmr_Int : PDI<0x11, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
1377 "movupd\t{$src, $dst|$dst, $src}",
1378 [(int_x86_sse2_storeu_pd addr:$dst, VR128:$src)]>;
1380 let isTwoAddress = 1 in {
1381 let AddedComplexity = 20 in {
1382 def MOVLPDrm : PDI<0x12, MRMSrcMem,
1383 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1384 "movlpd\t{$src2, $dst|$dst, $src2}",
1386 (v2f64 (vector_shuffle VR128:$src1,
1387 (scalar_to_vector (loadf64 addr:$src2)),
1388 MOVLP_shuffle_mask)))]>;
1389 def MOVHPDrm : PDI<0x16, MRMSrcMem,
1390 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1391 "movhpd\t{$src2, $dst|$dst, $src2}",
1393 (v2f64 (vector_shuffle VR128:$src1,
1394 (scalar_to_vector (loadf64 addr:$src2)),
1395 MOVHP_shuffle_mask)))]>;
1396 } // AddedComplexity
1399 def MOVLPDmr : PDI<0x13, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1400 "movlpd\t{$src, $dst|$dst, $src}",
1401 [(store (f64 (vector_extract (v2f64 VR128:$src),
1402 (iPTR 0))), addr:$dst)]>;
1404 // v2f64 extract element 1 is always custom lowered to unpack high to low
1405 // and extract element 0 so the non-store version isn't too horrible.
1406 def MOVHPDmr : PDI<0x17, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
1407 "movhpd\t{$src, $dst|$dst, $src}",
1408 [(store (f64 (vector_extract
1409 (v2f64 (vector_shuffle VR128:$src, (undef),
1410 UNPCKH_shuffle_mask)), (iPTR 0))),
1413 // SSE2 instructions without OpSize prefix
1414 def Int_CVTDQ2PSrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1415 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1416 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps VR128:$src))]>,
1417 TB, Requires<[HasSSE2]>;
1418 def Int_CVTDQ2PSrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1419 "cvtdq2ps\t{$src, $dst|$dst, $src}",
1420 [(set VR128:$dst, (int_x86_sse2_cvtdq2ps
1421 (bitconvert (memopv2i64 addr:$src))))]>,
1422 TB, Requires<[HasSSE2]>;
1424 // SSE2 instructions with XS prefix
1425 def Int_CVTDQ2PDrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1426 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1427 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd VR128:$src))]>,
1428 XS, Requires<[HasSSE2]>;
1429 def Int_CVTDQ2PDrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
1430 "cvtdq2pd\t{$src, $dst|$dst, $src}",
1431 [(set VR128:$dst, (int_x86_sse2_cvtdq2pd
1432 (bitconvert (memopv2i64 addr:$src))))]>,
1433 XS, Requires<[HasSSE2]>;
1435 def Int_CVTPS2DQrr : PDI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1436 "cvtps2dq\t{$src, $dst|$dst, $src}",
1437 [(set VR128:$dst, (int_x86_sse2_cvtps2dq VR128:$src))]>;
1438 def Int_CVTPS2DQrm : PDI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1439 "cvtps2dq\t{$src, $dst|$dst, $src}",
1440 [(set VR128:$dst, (int_x86_sse2_cvtps2dq
1441 (load addr:$src)))]>;
1442 // SSE2 packed instructions with XS prefix
1443 def Int_CVTTPS2DQrr : I<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1444 "cvttps2dq\t{$src, $dst|$dst, $src}",
1445 [(set VR128:$dst, (int_x86_sse2_cvttps2dq VR128:$src))]>,
1446 XS, Requires<[HasSSE2]>;
1447 def Int_CVTTPS2DQrm : I<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1448 "cvttps2dq\t{$src, $dst|$dst, $src}",
1449 [(set VR128:$dst, (int_x86_sse2_cvttps2dq
1450 (load addr:$src)))]>,
1451 XS, Requires<[HasSSE2]>;
1453 // SSE2 packed instructions with XD prefix
1454 def Int_CVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1455 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1456 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq VR128:$src))]>,
1457 XD, Requires<[HasSSE2]>;
1458 def Int_CVTPD2DQrm : I<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1459 "cvtpd2dq\t{$src, $dst|$dst, $src}",
1460 [(set VR128:$dst, (int_x86_sse2_cvtpd2dq
1461 (load addr:$src)))]>,
1462 XD, Requires<[HasSSE2]>;
1464 def Int_CVTTPD2DQrr : PDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1465 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1466 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq VR128:$src))]>;
1467 def Int_CVTTPD2DQrm : PDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1468 "cvttpd2dq\t{$src, $dst|$dst, $src}",
1469 [(set VR128:$dst, (int_x86_sse2_cvttpd2dq
1470 (load addr:$src)))]>;
1472 // SSE2 instructions without OpSize prefix
1473 def Int_CVTPS2PDrr : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1474 "cvtps2pd\t{$src, $dst|$dst, $src}",
1475 [(set VR128:$dst, (int_x86_sse2_cvtps2pd VR128:$src))]>,
1476 TB, Requires<[HasSSE2]>;
1477 def Int_CVTPS2PDrm : I<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f64mem:$src),
1478 "cvtps2pd\t{$src, $dst|$dst, $src}",
1479 [(set VR128:$dst, (int_x86_sse2_cvtps2pd
1480 (load addr:$src)))]>,
1481 TB, Requires<[HasSSE2]>;
1483 def Int_CVTPD2PSrr : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1484 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1485 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps VR128:$src))]>;
1486 def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcReg, (outs VR128:$dst), (ins f128mem:$src),
1487 "cvtpd2ps\t{$src, $dst|$dst, $src}",
1488 [(set VR128:$dst, (int_x86_sse2_cvtpd2ps
1489 (load addr:$src)))]>;
1491 // Match intrinsics which expect XMM operand(s).
1492 // Aliases for intrinsics
1493 let isTwoAddress = 1 in {
1494 def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
1495 (outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
1496 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1497 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1499 def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
1500 (outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
1501 "cvtsi2sd\t{$src2, $dst|$dst, $src2}",
1502 [(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
1503 (loadi32 addr:$src2)))]>;
1504 def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
1505 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1506 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1507 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1509 def Int_CVTSD2SSrm: SDI<0x5A, MRMSrcMem,
1510 (outs VR128:$dst), (ins VR128:$src1, f64mem:$src2),
1511 "cvtsd2ss\t{$src2, $dst|$dst, $src2}",
1512 [(set VR128:$dst, (int_x86_sse2_cvtsd2ss VR128:$src1,
1513 (load addr:$src2)))]>;
1514 def Int_CVTSS2SDrr: I<0x5A, MRMSrcReg,
1515 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1516 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1517 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1518 VR128:$src2))]>, XS,
1519 Requires<[HasSSE2]>;
1520 def Int_CVTSS2SDrm: I<0x5A, MRMSrcMem,
1521 (outs VR128:$dst), (ins VR128:$src1, f32mem:$src2),
1522 "cvtss2sd\t{$src2, $dst|$dst, $src2}",
1523 [(set VR128:$dst, (int_x86_sse2_cvtss2sd VR128:$src1,
1524 (load addr:$src2)))]>, XS,
1525 Requires<[HasSSE2]>;
1530 /// sse2_fp_unop_rm - SSE2 unops come in both scalar and vector forms.
1532 /// In addition, we also have a special variant of the scalar form here to
1533 /// represent the associated intrinsic operation. This form is unlike the
1534 /// plain scalar form, in that it takes an entire vector (instead of a
1535 /// scalar) and leaves the top elements undefined.
1537 /// And, we have a special variant form for a full-vector intrinsic form.
1539 /// These four forms can each have a reg or a mem operand, so there are a
1540 /// total of eight "instructions".
1542 multiclass sse2_fp_unop_rm<bits<8> opc, string OpcodeStr,
1546 bit Commutable = 0> {
1547 // Scalar operation, reg.
1548 def SDr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src),
1549 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1550 [(set FR64:$dst, (OpNode FR64:$src))]> {
1551 let isCommutable = Commutable;
1554 // Scalar operation, mem.
1555 def SDm : SDI<opc, MRMSrcMem, (outs FR64:$dst), (ins f64mem:$src),
1556 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1557 [(set FR64:$dst, (OpNode (load addr:$src)))]>;
1559 // Vector operation, reg.
1560 def PDr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1561 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1562 [(set VR128:$dst, (v2f64 (OpNode VR128:$src)))]> {
1563 let isCommutable = Commutable;
1566 // Vector operation, mem.
1567 def PDm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1568 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1569 [(set VR128:$dst, (OpNode (memopv2f64 addr:$src)))]>;
1571 // Intrinsic operation, reg.
1572 def SDr_Int : SDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1573 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1574 [(set VR128:$dst, (F64Int VR128:$src))]> {
1575 let isCommutable = Commutable;
1578 // Intrinsic operation, mem.
1579 def SDm_Int : SDI<opc, MRMSrcMem, (outs VR128:$dst), (ins sdmem:$src),
1580 !strconcat(OpcodeStr, "sd\t{$src, $dst|$dst, $src}"),
1581 [(set VR128:$dst, (F64Int sse_load_f64:$src))]>;
1583 // Vector intrinsic operation, reg
1584 def PDr_Int : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1585 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1586 [(set VR128:$dst, (V2F64Int VR128:$src))]> {
1587 let isCommutable = Commutable;
1590 // Vector intrinsic operation, mem
1591 def PDm_Int : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
1592 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
1593 [(set VR128:$dst, (V2F64Int (load addr:$src)))]>;
1597 defm SQRT : sse2_fp_unop_rm<0x51, "sqrt", fsqrt,
1598 int_x86_sse2_sqrt_sd, int_x86_sse2_sqrt_pd>;
1600 // There is no f64 version of the reciprocal approximation instructions.
1603 let isTwoAddress = 1 in {
1604 let isCommutable = 1 in {
1605 def ANDPDrr : PDI<0x54, MRMSrcReg,
1606 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1607 "andpd\t{$src2, $dst|$dst, $src2}",
1609 (and (bc_v2i64 (v2f64 VR128:$src1)),
1610 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1611 def ORPDrr : PDI<0x56, MRMSrcReg,
1612 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1613 "orpd\t{$src2, $dst|$dst, $src2}",
1615 (or (bc_v2i64 (v2f64 VR128:$src1)),
1616 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1617 def XORPDrr : PDI<0x57, MRMSrcReg,
1618 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1619 "xorpd\t{$src2, $dst|$dst, $src2}",
1621 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1622 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1625 def ANDPDrm : PDI<0x54, MRMSrcMem,
1626 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1627 "andpd\t{$src2, $dst|$dst, $src2}",
1629 (and (bc_v2i64 (v2f64 VR128:$src1)),
1630 (memopv2i64 addr:$src2)))]>;
1631 def ORPDrm : PDI<0x56, MRMSrcMem,
1632 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1633 "orpd\t{$src2, $dst|$dst, $src2}",
1635 (or (bc_v2i64 (v2f64 VR128:$src1)),
1636 (memopv2i64 addr:$src2)))]>;
1637 def XORPDrm : PDI<0x57, MRMSrcMem,
1638 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1639 "xorpd\t{$src2, $dst|$dst, $src2}",
1641 (xor (bc_v2i64 (v2f64 VR128:$src1)),
1642 (memopv2i64 addr:$src2)))]>;
1643 def ANDNPDrr : PDI<0x55, MRMSrcReg,
1644 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1645 "andnpd\t{$src2, $dst|$dst, $src2}",
1647 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1648 (bc_v2i64 (v2f64 VR128:$src2))))]>;
1649 def ANDNPDrm : PDI<0x55, MRMSrcMem,
1650 (outs VR128:$dst), (ins VR128:$src1,f128mem:$src2),
1651 "andnpd\t{$src2, $dst|$dst, $src2}",
1653 (and (vnot (bc_v2i64 (v2f64 VR128:$src1))),
1654 (memopv2i64 addr:$src2)))]>;
1657 let isTwoAddress = 1 in {
1658 def CMPPDrri : PDIi8<0xC2, MRMSrcReg,
1659 (outs VR128:$dst), (ins VR128:$src1, VR128:$src, SSECC:$cc),
1660 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1661 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1662 VR128:$src, imm:$cc))]>;
1663 def CMPPDrmi : PDIi8<0xC2, MRMSrcMem,
1664 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src, SSECC:$cc),
1665 "cmp${cc}pd\t{$src, $dst|$dst, $src}",
1666 [(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
1667 (load addr:$src), imm:$cc))]>;
1670 // Shuffle and unpack instructions
1671 let isTwoAddress = 1 in {
1672 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg,
1673 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i8imm:$src3),
1674 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1675 [(set VR128:$dst, (v2f64 (vector_shuffle
1676 VR128:$src1, VR128:$src2,
1677 SHUFP_shuffle_mask:$src3)))]>;
1678 def SHUFPDrmi : PDIi8<0xC6, MRMSrcMem,
1679 (outs VR128:$dst), (ins VR128:$src1,
1680 f128mem:$src2, i8imm:$src3),
1681 "shufpd\t{$src3, $src2, $dst|$dst, $src2, $src3}",
1683 (v2f64 (vector_shuffle
1684 VR128:$src1, (memopv2f64 addr:$src2),
1685 SHUFP_shuffle_mask:$src3)))]>;
1687 let AddedComplexity = 10 in {
1688 def UNPCKHPDrr : PDI<0x15, MRMSrcReg,
1689 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1690 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1692 (v2f64 (vector_shuffle
1693 VR128:$src1, VR128:$src2,
1694 UNPCKH_shuffle_mask)))]>;
1695 def UNPCKHPDrm : PDI<0x15, MRMSrcMem,
1696 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1697 "unpckhpd\t{$src2, $dst|$dst, $src2}",
1699 (v2f64 (vector_shuffle
1700 VR128:$src1, (memopv2f64 addr:$src2),
1701 UNPCKH_shuffle_mask)))]>;
1703 def UNPCKLPDrr : PDI<0x14, MRMSrcReg,
1704 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1705 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1707 (v2f64 (vector_shuffle
1708 VR128:$src1, VR128:$src2,
1709 UNPCKL_shuffle_mask)))]>;
1710 def UNPCKLPDrm : PDI<0x14, MRMSrcMem,
1711 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
1712 "unpcklpd\t{$src2, $dst|$dst, $src2}",
1714 (v2f64 (vector_shuffle
1715 VR128:$src1, (memopv2f64 addr:$src2),
1716 UNPCKL_shuffle_mask)))]>;
1717 } // AddedComplexity
1721 //===----------------------------------------------------------------------===//
1722 // SSE integer instructions
1724 // Move Instructions
1725 let neverHasSideEffects = 1 in
1726 def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
1727 "movdqa\t{$src, $dst|$dst, $src}", []>;
1728 let isSimpleLoad = 1, mayLoad = 1 in
1729 def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1730 "movdqa\t{$src, $dst|$dst, $src}",
1731 [/*(set VR128:$dst, (alignedloadv2i64 addr:$src))*/]>;
1733 def MOVDQAmr : PDI<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1734 "movdqa\t{$src, $dst|$dst, $src}",
1735 [/*(alignedstore (v2i64 VR128:$src), addr:$dst)*/]>;
1736 let isSimpleLoad = 1, mayLoad = 1 in
1737 def MOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1738 "movdqu\t{$src, $dst|$dst, $src}",
1739 [/*(set VR128:$dst, (loadv2i64 addr:$src))*/]>,
1740 XS, Requires<[HasSSE2]>;
1742 def MOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1743 "movdqu\t{$src, $dst|$dst, $src}",
1744 [/*(store (v2i64 VR128:$src), addr:$dst)*/]>,
1745 XS, Requires<[HasSSE2]>;
1747 // Intrinsic forms of MOVDQU load and store
1748 let isSimpleLoad = 1 in
1749 def MOVDQUrm_Int : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
1750 "movdqu\t{$src, $dst|$dst, $src}",
1751 [(set VR128:$dst, (int_x86_sse2_loadu_dq addr:$src))]>,
1752 XS, Requires<[HasSSE2]>;
1753 def MOVDQUmr_Int : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
1754 "movdqu\t{$src, $dst|$dst, $src}",
1755 [(int_x86_sse2_storeu_dq addr:$dst, VR128:$src)]>,
1756 XS, Requires<[HasSSE2]>;
1758 let isTwoAddress = 1 in {
1760 multiclass PDI_binop_rm_int<bits<8> opc, string OpcodeStr, Intrinsic IntId,
1761 bit Commutable = 0> {
1762 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1763 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1764 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]> {
1765 let isCommutable = Commutable;
1767 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1768 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1769 [(set VR128:$dst, (IntId VR128:$src1,
1770 (bitconvert (memopv2i64 addr:$src2))))]>;
1773 multiclass PDI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
1774 string OpcodeStr, Intrinsic IntId> {
1775 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1776 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1777 [(set VR128:$dst, (IntId VR128:$src1, VR128:$src2))]>;
1778 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1779 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1780 [(set VR128:$dst, (IntId VR128:$src1,
1781 (bitconvert (memopv2i64 addr:$src2))))]>;
1782 def ri : PDIi8<opc2, ImmForm, (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1783 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1784 [(set VR128:$dst, (IntId VR128:$src1,
1785 (scalar_to_vector (i32 imm:$src2))))]>;
1789 /// PDI_binop_rm - Simple SSE2 binary operator.
1790 multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1791 ValueType OpVT, bit Commutable = 0> {
1792 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1793 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1794 [(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]> {
1795 let isCommutable = Commutable;
1797 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1798 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1799 [(set VR128:$dst, (OpVT (OpNode VR128:$src1,
1800 (bitconvert (memopv2i64 addr:$src2)))))]>;
1803 /// PDI_binop_rm_v2i64 - Simple SSE2 binary operator whose type is v2i64.
1805 /// FIXME: we could eliminate this and use PDI_binop_rm instead if tblgen knew
1806 /// to collapse (bitconvert VT to VT) into its operand.
1808 multiclass PDI_binop_rm_v2i64<bits<8> opc, string OpcodeStr, SDNode OpNode,
1809 bit Commutable = 0> {
1810 def rr : PDI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1811 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1812 [(set VR128:$dst, (v2i64 (OpNode VR128:$src1, VR128:$src2)))]> {
1813 let isCommutable = Commutable;
1815 def rm : PDI<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1816 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
1817 [(set VR128:$dst, (OpNode VR128:$src1,(memopv2i64 addr:$src2)))]>;
1822 // 128-bit Integer Arithmetic
1824 defm PADDB : PDI_binop_rm<0xFC, "paddb", add, v16i8, 1>;
1825 defm PADDW : PDI_binop_rm<0xFD, "paddw", add, v8i16, 1>;
1826 defm PADDD : PDI_binop_rm<0xFE, "paddd", add, v4i32, 1>;
1827 defm PADDQ : PDI_binop_rm_v2i64<0xD4, "paddq", add, 1>;
1829 defm PADDSB : PDI_binop_rm_int<0xEC, "paddsb" , int_x86_sse2_padds_b, 1>;
1830 defm PADDSW : PDI_binop_rm_int<0xED, "paddsw" , int_x86_sse2_padds_w, 1>;
1831 defm PADDUSB : PDI_binop_rm_int<0xDC, "paddusb", int_x86_sse2_paddus_b, 1>;
1832 defm PADDUSW : PDI_binop_rm_int<0xDD, "paddusw", int_x86_sse2_paddus_w, 1>;
1834 defm PSUBB : PDI_binop_rm<0xF8, "psubb", sub, v16i8>;
1835 defm PSUBW : PDI_binop_rm<0xF9, "psubw", sub, v8i16>;
1836 defm PSUBD : PDI_binop_rm<0xFA, "psubd", sub, v4i32>;
1837 defm PSUBQ : PDI_binop_rm_v2i64<0xFB, "psubq", sub>;
1839 defm PSUBSB : PDI_binop_rm_int<0xE8, "psubsb" , int_x86_sse2_psubs_b>;
1840 defm PSUBSW : PDI_binop_rm_int<0xE9, "psubsw" , int_x86_sse2_psubs_w>;
1841 defm PSUBUSB : PDI_binop_rm_int<0xD8, "psubusb", int_x86_sse2_psubus_b>;
1842 defm PSUBUSW : PDI_binop_rm_int<0xD9, "psubusw", int_x86_sse2_psubus_w>;
1844 defm PMULLW : PDI_binop_rm<0xD5, "pmullw", mul, v8i16, 1>;
1846 defm PMULHUW : PDI_binop_rm_int<0xE4, "pmulhuw", int_x86_sse2_pmulhu_w, 1>;
1847 defm PMULHW : PDI_binop_rm_int<0xE5, "pmulhw" , int_x86_sse2_pmulh_w , 1>;
1848 defm PMULUDQ : PDI_binop_rm_int<0xF4, "pmuludq", int_x86_sse2_pmulu_dq, 1>;
1850 defm PMADDWD : PDI_binop_rm_int<0xF5, "pmaddwd", int_x86_sse2_pmadd_wd, 1>;
1852 defm PAVGB : PDI_binop_rm_int<0xE0, "pavgb", int_x86_sse2_pavg_b, 1>;
1853 defm PAVGW : PDI_binop_rm_int<0xE3, "pavgw", int_x86_sse2_pavg_w, 1>;
1856 defm PMINUB : PDI_binop_rm_int<0xDA, "pminub", int_x86_sse2_pminu_b, 1>;
1857 defm PMINSW : PDI_binop_rm_int<0xEA, "pminsw", int_x86_sse2_pmins_w, 1>;
1858 defm PMAXUB : PDI_binop_rm_int<0xDE, "pmaxub", int_x86_sse2_pmaxu_b, 1>;
1859 defm PMAXSW : PDI_binop_rm_int<0xEE, "pmaxsw", int_x86_sse2_pmaxs_w, 1>;
1860 defm PSADBW : PDI_binop_rm_int<0xE0, "psadbw", int_x86_sse2_psad_bw, 1>;
1863 defm PSLLW : PDI_binop_rmi_int<0xF1, 0x71, MRM6r, "psllw", int_x86_sse2_psll_w>;
1864 defm PSLLD : PDI_binop_rmi_int<0xF2, 0x72, MRM6r, "pslld", int_x86_sse2_psll_d>;
1865 defm PSLLQ : PDI_binop_rmi_int<0xF3, 0x73, MRM6r, "psllq", int_x86_sse2_psll_q>;
1867 defm PSRLW : PDI_binop_rmi_int<0xD1, 0x71, MRM2r, "psrlw", int_x86_sse2_psrl_w>;
1868 defm PSRLD : PDI_binop_rmi_int<0xD2, 0x72, MRM2r, "psrld", int_x86_sse2_psrl_d>;
1869 defm PSRLQ : PDI_binop_rmi_int<0xD3, 0x73, MRM2r, "psrlq", int_x86_sse2_psrl_q>;
1871 defm PSRAW : PDI_binop_rmi_int<0xE1, 0x71, MRM4r, "psraw", int_x86_sse2_psra_w>;
1872 defm PSRAD : PDI_binop_rmi_int<0xE2, 0x72, MRM4r, "psrad", int_x86_sse2_psra_d>;
1873 // PSRAQ doesn't exist in SSE[1-3].
1875 // 128-bit logical shifts.
1876 let isTwoAddress = 1, neverHasSideEffects = 1 in {
1877 def PSLLDQri : PDIi8<0x73, MRM7r,
1878 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1879 "pslldq\t{$src2, $dst|$dst, $src2}", []>;
1880 def PSRLDQri : PDIi8<0x73, MRM3r,
1881 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1882 "psrldq\t{$src2, $dst|$dst, $src2}", []>;
1883 // PSRADQri doesn't exist in SSE[1-3].
1886 let Predicates = [HasSSE2] in {
1887 def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
1888 (v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1889 def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
1890 (v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1891 def : Pat<(v2f64 (X86fsrl VR128:$src1, i32immSExt8:$src2)),
1892 (v2f64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
1896 defm PAND : PDI_binop_rm_v2i64<0xDB, "pand", and, 1>;
1897 defm POR : PDI_binop_rm_v2i64<0xEB, "por" , or , 1>;
1898 defm PXOR : PDI_binop_rm_v2i64<0xEF, "pxor", xor, 1>;
1900 let isTwoAddress = 1 in {
1901 def PANDNrr : PDI<0xDF, MRMSrcReg,
1902 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1903 "pandn\t{$src2, $dst|$dst, $src2}",
1904 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1907 def PANDNrm : PDI<0xDF, MRMSrcMem,
1908 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1909 "pandn\t{$src2, $dst|$dst, $src2}",
1910 [(set VR128:$dst, (v2i64 (and (vnot VR128:$src1),
1911 (memopv2i64 addr:$src2))))]>;
1914 // SSE2 Integer comparison
1915 defm PCMPEQB : PDI_binop_rm_int<0x74, "pcmpeqb", int_x86_sse2_pcmpeq_b>;
1916 defm PCMPEQW : PDI_binop_rm_int<0x75, "pcmpeqw", int_x86_sse2_pcmpeq_w>;
1917 defm PCMPEQD : PDI_binop_rm_int<0x76, "pcmpeqd", int_x86_sse2_pcmpeq_d>;
1918 defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
1919 defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
1920 defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
1922 // Pack instructions
1923 defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128>;
1924 defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128>;
1925 defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128>;
1927 // Shuffle and unpack instructions
1928 def PSHUFDri : PDIi8<0x70, MRMSrcReg,
1929 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1930 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1931 [(set VR128:$dst, (v4i32 (vector_shuffle
1932 VR128:$src1, (undef),
1933 PSHUFD_shuffle_mask:$src2)))]>;
1934 def PSHUFDmi : PDIi8<0x70, MRMSrcMem,
1935 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1936 "pshufd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1937 [(set VR128:$dst, (v4i32 (vector_shuffle
1938 (bc_v4i32(memopv2i64 addr:$src1)),
1940 PSHUFD_shuffle_mask:$src2)))]>;
1942 // SSE2 with ImmT == Imm8 and XS prefix.
1943 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
1944 (outs VR128:$dst), (ins VR128:$src1, i8imm:$src2),
1945 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1946 [(set VR128:$dst, (v8i16 (vector_shuffle
1947 VR128:$src1, (undef),
1948 PSHUFHW_shuffle_mask:$src2)))]>,
1949 XS, Requires<[HasSSE2]>;
1950 def PSHUFHWmi : Ii8<0x70, MRMSrcMem,
1951 (outs VR128:$dst), (ins i128mem:$src1, i8imm:$src2),
1952 "pshufhw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1953 [(set VR128:$dst, (v8i16 (vector_shuffle
1954 (bc_v8i16 (memopv2i64 addr:$src1)),
1956 PSHUFHW_shuffle_mask:$src2)))]>,
1957 XS, Requires<[HasSSE2]>;
1959 // SSE2 with ImmT == Imm8 and XD prefix.
1960 def PSHUFLWri : Ii8<0x70, MRMSrcReg,
1961 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
1962 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1963 [(set VR128:$dst, (v8i16 (vector_shuffle
1964 VR128:$src1, (undef),
1965 PSHUFLW_shuffle_mask:$src2)))]>,
1966 XD, Requires<[HasSSE2]>;
1967 def PSHUFLWmi : Ii8<0x70, MRMSrcMem,
1968 (outs VR128:$dst), (ins i128mem:$src1, i32i8imm:$src2),
1969 "pshuflw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1970 [(set VR128:$dst, (v8i16 (vector_shuffle
1971 (bc_v8i16 (memopv2i64 addr:$src1)),
1973 PSHUFLW_shuffle_mask:$src2)))]>,
1974 XD, Requires<[HasSSE2]>;
1977 let isTwoAddress = 1 in {
1978 def PUNPCKLBWrr : PDI<0x60, MRMSrcReg,
1979 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1980 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1982 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
1983 UNPCKL_shuffle_mask)))]>;
1984 def PUNPCKLBWrm : PDI<0x60, MRMSrcMem,
1985 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1986 "punpcklbw\t{$src2, $dst|$dst, $src2}",
1988 (v16i8 (vector_shuffle VR128:$src1,
1989 (bc_v16i8 (memopv2i64 addr:$src2)),
1990 UNPCKL_shuffle_mask)))]>;
1991 def PUNPCKLWDrr : PDI<0x61, MRMSrcReg,
1992 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
1993 "punpcklwd\t{$src2, $dst|$dst, $src2}",
1995 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
1996 UNPCKL_shuffle_mask)))]>;
1997 def PUNPCKLWDrm : PDI<0x61, MRMSrcMem,
1998 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
1999 "punpcklwd\t{$src2, $dst|$dst, $src2}",
2001 (v8i16 (vector_shuffle VR128:$src1,
2002 (bc_v8i16 (memopv2i64 addr:$src2)),
2003 UNPCKL_shuffle_mask)))]>;
2004 def PUNPCKLDQrr : PDI<0x62, MRMSrcReg,
2005 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2006 "punpckldq\t{$src2, $dst|$dst, $src2}",
2008 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2009 UNPCKL_shuffle_mask)))]>;
2010 def PUNPCKLDQrm : PDI<0x62, MRMSrcMem,
2011 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2012 "punpckldq\t{$src2, $dst|$dst, $src2}",
2014 (v4i32 (vector_shuffle VR128:$src1,
2015 (bc_v4i32 (memopv2i64 addr:$src2)),
2016 UNPCKL_shuffle_mask)))]>;
2017 def PUNPCKLQDQrr : PDI<0x6C, MRMSrcReg,
2018 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2019 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2021 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2022 UNPCKL_shuffle_mask)))]>;
2023 def PUNPCKLQDQrm : PDI<0x6C, MRMSrcMem,
2024 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2025 "punpcklqdq\t{$src2, $dst|$dst, $src2}",
2027 (v2i64 (vector_shuffle VR128:$src1,
2028 (memopv2i64 addr:$src2),
2029 UNPCKL_shuffle_mask)))]>;
2031 def PUNPCKHBWrr : PDI<0x68, MRMSrcReg,
2032 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2033 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2035 (v16i8 (vector_shuffle VR128:$src1, VR128:$src2,
2036 UNPCKH_shuffle_mask)))]>;
2037 def PUNPCKHBWrm : PDI<0x68, MRMSrcMem,
2038 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2039 "punpckhbw\t{$src2, $dst|$dst, $src2}",
2041 (v16i8 (vector_shuffle VR128:$src1,
2042 (bc_v16i8 (memopv2i64 addr:$src2)),
2043 UNPCKH_shuffle_mask)))]>;
2044 def PUNPCKHWDrr : PDI<0x69, MRMSrcReg,
2045 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2046 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2048 (v8i16 (vector_shuffle VR128:$src1, VR128:$src2,
2049 UNPCKH_shuffle_mask)))]>;
2050 def PUNPCKHWDrm : PDI<0x69, MRMSrcMem,
2051 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2052 "punpckhwd\t{$src2, $dst|$dst, $src2}",
2054 (v8i16 (vector_shuffle VR128:$src1,
2055 (bc_v8i16 (memopv2i64 addr:$src2)),
2056 UNPCKH_shuffle_mask)))]>;
2057 def PUNPCKHDQrr : PDI<0x6A, MRMSrcReg,
2058 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2059 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2061 (v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2062 UNPCKH_shuffle_mask)))]>;
2063 def PUNPCKHDQrm : PDI<0x6A, MRMSrcMem,
2064 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2065 "punpckhdq\t{$src2, $dst|$dst, $src2}",
2067 (v4i32 (vector_shuffle VR128:$src1,
2068 (bc_v4i32 (memopv2i64 addr:$src2)),
2069 UNPCKH_shuffle_mask)))]>;
2070 def PUNPCKHQDQrr : PDI<0x6D, MRMSrcReg,
2071 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2072 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2074 (v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2075 UNPCKH_shuffle_mask)))]>;
2076 def PUNPCKHQDQrm : PDI<0x6D, MRMSrcMem,
2077 (outs VR128:$dst), (ins VR128:$src1, i128mem:$src2),
2078 "punpckhqdq\t{$src2, $dst|$dst, $src2}",
2080 (v2i64 (vector_shuffle VR128:$src1,
2081 (memopv2i64 addr:$src2),
2082 UNPCKH_shuffle_mask)))]>;
2086 def PEXTRWri : PDIi8<0xC5, MRMSrcReg,
2087 (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),
2088 "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2089 [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),
2090 (iPTR imm:$src2)))]>;
2091 let isTwoAddress = 1 in {
2092 def PINSRWrri : PDIi8<0xC4, MRMSrcReg,
2093 (outs VR128:$dst), (ins VR128:$src1,
2094 GR32:$src2, i32i8imm:$src3),
2095 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2097 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2098 GR32:$src2, (iPTR imm:$src3))))]>;
2099 def PINSRWrmi : PDIi8<0xC4, MRMSrcMem,
2100 (outs VR128:$dst), (ins VR128:$src1,
2101 i16mem:$src2, i32i8imm:$src3),
2102 "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2104 (v8i16 (X86pinsrw (v8i16 VR128:$src1),
2105 (i32 (anyext (loadi16 addr:$src2))),
2106 (iPTR imm:$src3))))]>;
2110 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
2111 "pmovmskb\t{$src, $dst|$dst, $src}",
2112 [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))]>;
2114 // Conditional store
2116 def MASKMOVDQU : PDI<0xF7, MRMSrcReg, (outs), (ins VR128:$src, VR128:$mask),
2117 "maskmovdqu\t{$mask, $src|$src, $mask}",
2118 [(int_x86_sse2_maskmov_dqu VR128:$src, VR128:$mask, EDI)]>;
2120 // Non-temporal stores
2121 def MOVNTPDmr : PDI<0x2B, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
2122 "movntpd\t{$src, $dst|$dst, $src}",
2123 [(int_x86_sse2_movnt_pd addr:$dst, VR128:$src)]>;
2124 def MOVNTDQmr : PDI<0xE7, MRMDestMem, (outs), (ins f128mem:$dst, VR128:$src),
2125 "movntdq\t{$src, $dst|$dst, $src}",
2126 [(int_x86_sse2_movnt_dq addr:$dst, VR128:$src)]>;
2127 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
2128 "movnti\t{$src, $dst|$dst, $src}",
2129 [(int_x86_sse2_movnt_i addr:$dst, GR32:$src)]>,
2130 TB, Requires<[HasSSE2]>;
2133 def CLFLUSH : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
2134 "clflush\t$src", [(int_x86_sse2_clflush addr:$src)]>,
2135 TB, Requires<[HasSSE2]>;
2137 // Load, store, and memory fence
2138 def LFENCE : I<0xAE, MRM5m, (outs), (ins),
2139 "lfence", [(int_x86_sse2_lfence)]>, TB, Requires<[HasSSE2]>;
2140 def MFENCE : I<0xAE, MRM6m, (outs), (ins),
2141 "mfence", [(int_x86_sse2_mfence)]>, TB, Requires<[HasSSE2]>;
2143 // Alias instructions that map zero vector to pxor / xorp* for sse.
2144 let isReMaterializable = 1 in
2145 def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins),
2146 "pcmpeqd\t$dst, $dst",
2147 [(set VR128:$dst, (v4i32 immAllOnesV))]>;
2149 // FR64 to 128-bit vector conversion.
2150 def MOVSD2PDrr : SDI<0x10, MRMSrcReg, (outs VR128:$dst), (ins FR64:$src),
2151 "movsd\t{$src, $dst|$dst, $src}",
2153 (v2f64 (scalar_to_vector FR64:$src)))]>;
2154 def MOVSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2155 "movsd\t{$src, $dst|$dst, $src}",
2157 (v2f64 (scalar_to_vector (loadf64 addr:$src))))]>;
2159 def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2160 "movd\t{$src, $dst|$dst, $src}",
2162 (v4i32 (scalar_to_vector GR32:$src)))]>;
2163 def MOVDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2164 "movd\t{$src, $dst|$dst, $src}",
2166 (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
2168 def MOVDI2SSrr : PDI<0x6E, MRMSrcReg, (outs FR32:$dst), (ins GR32:$src),
2169 "movd\t{$src, $dst|$dst, $src}",
2170 [(set FR32:$dst, (bitconvert GR32:$src))]>;
2172 def MOVDI2SSrm : PDI<0x6E, MRMSrcMem, (outs FR32:$dst), (ins i32mem:$src),
2173 "movd\t{$src, $dst|$dst, $src}",
2174 [(set FR32:$dst, (bitconvert (loadi32 addr:$src)))]>;
2176 // SSE2 instructions with XS prefix
2177 def MOVQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2178 "movq\t{$src, $dst|$dst, $src}",
2180 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>, XS,
2181 Requires<[HasSSE2]>;
2182 def MOVPQI2QImr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2183 "movq\t{$src, $dst|$dst, $src}",
2184 [(store (i64 (vector_extract (v2i64 VR128:$src),
2185 (iPTR 0))), addr:$dst)]>;
2187 // FIXME: may not be able to eliminate this movss with coalescing the src and
2188 // dest register classes are different. We really want to write this pattern
2190 // def : Pat<(f32 (vector_extract (v4f32 VR128:$src), (iPTR 0))),
2191 // (f32 FR32:$src)>;
2192 def MOVPD2SDrr : SDI<0x10, MRMSrcReg, (outs FR64:$dst), (ins VR128:$src),
2193 "movsd\t{$src, $dst|$dst, $src}",
2194 [(set FR64:$dst, (vector_extract (v2f64 VR128:$src),
2196 def MOVPD2SDmr : SDI<0x11, MRMDestMem, (outs), (ins f64mem:$dst, VR128:$src),
2197 "movsd\t{$src, $dst|$dst, $src}",
2198 [(store (f64 (vector_extract (v2f64 VR128:$src),
2199 (iPTR 0))), addr:$dst)]>;
2200 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2201 "movd\t{$src, $dst|$dst, $src}",
2202 [(set GR32:$dst, (vector_extract (v4i32 VR128:$src),
2204 def MOVPDI2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, VR128:$src),
2205 "movd\t{$src, $dst|$dst, $src}",
2206 [(store (i32 (vector_extract (v4i32 VR128:$src),
2207 (iPTR 0))), addr:$dst)]>;
2209 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2210 "movd\t{$src, $dst|$dst, $src}",
2211 [(set GR32:$dst, (bitconvert FR32:$src))]>;
2212 def MOVSS2DImr : PDI<0x7E, MRMDestMem, (outs), (ins i32mem:$dst, FR32:$src),
2213 "movd\t{$src, $dst|$dst, $src}",
2214 [(store (i32 (bitconvert FR32:$src)), addr:$dst)]>;
2217 // Move to lower bits of a VR128, leaving upper bits alone.
2218 // Three operand (but two address) aliases.
2219 let isTwoAddress = 1 in {
2220 let neverHasSideEffects = 1 in
2221 def MOVLSD2PDrr : SDI<0x10, MRMSrcReg,
2222 (outs VR128:$dst), (ins VR128:$src1, FR64:$src2),
2223 "movsd\t{$src2, $dst|$dst, $src2}", []>;
2225 let AddedComplexity = 15 in
2226 def MOVLPDrr : SDI<0x10, MRMSrcReg,
2227 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2228 "movsd\t{$src2, $dst|$dst, $src2}",
2230 (v2f64 (vector_shuffle VR128:$src1, VR128:$src2,
2231 MOVL_shuffle_mask)))]>;
2234 // Store / copy lower 64-bits of a XMM register.
2235 def MOVLQ128mr : PDI<0xD6, MRMDestMem, (outs), (ins i64mem:$dst, VR128:$src),
2236 "movq\t{$src, $dst|$dst, $src}",
2237 [(int_x86_sse2_storel_dq addr:$dst, VR128:$src)]>;
2239 // Move to lower bits of a VR128 and zeroing upper bits.
2240 // Loading from memory automatically zeroing upper bits.
2241 let AddedComplexity = 20 in
2242 def MOVZSD2PDrm : SDI<0x10, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2243 "movsd\t{$src, $dst|$dst, $src}",
2245 (v2f64 (vector_shuffle immAllZerosV_bc,
2246 (v2f64 (scalar_to_vector
2247 (loadf64 addr:$src))),
2248 MOVL_shuffle_mask)))]>;
2250 // movd / movq to XMM register zero-extends
2251 let AddedComplexity = 15 in {
2252 def MOVZDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
2253 "movd\t{$src, $dst|$dst, $src}",
2255 (v4i32 (vector_shuffle immAllZerosV,
2256 (v4i32 (scalar_to_vector GR32:$src)),
2257 MOVL_shuffle_mask)))]>;
2258 // This is X86-64 only.
2259 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
2260 "mov{d|q}\t{$src, $dst|$dst, $src}",
2262 (v2i64 (vector_shuffle immAllZerosV_bc,
2263 (v2i64 (scalar_to_vector GR64:$src)),
2264 MOVL_shuffle_mask)))]>;
2267 let AddedComplexity = 20 in {
2268 def MOVZDI2PDIrm : PDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
2269 "movd\t{$src, $dst|$dst, $src}",
2271 (v4i32 (vector_shuffle immAllZerosV,
2272 (v4i32 (scalar_to_vector (loadi32 addr:$src))),
2273 MOVL_shuffle_mask)))]>;
2274 def MOVZQI2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
2275 "movq\t{$src, $dst|$dst, $src}",
2277 (v2i64 (vector_shuffle immAllZerosV_bc,
2278 (v2i64 (scalar_to_vector (loadi64 addr:$src))),
2279 MOVL_shuffle_mask)))]>, XS,
2280 Requires<[HasSSE2]>;
2283 // Moving from XMM to XMM and clear upper 64 bits. Note, there is a bug in
2284 // IA32 document. movq xmm1, xmm2 does clear the high bits.
2285 let AddedComplexity = 15 in
2286 def MOVZPQILo2PQIrr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2287 "movq\t{$src, $dst|$dst, $src}",
2288 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2290 MOVL_shuffle_mask)))]>,
2291 XS, Requires<[HasSSE2]>;
2293 let AddedComplexity = 20 in
2294 def MOVZPQILo2PQIrm : I<0x7E, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2295 "movq\t{$src, $dst|$dst, $src}",
2296 [(set VR128:$dst, (v2i64 (vector_shuffle immAllZerosV_bc,
2297 (memopv2i64 addr:$src),
2298 MOVL_shuffle_mask)))]>,
2299 XS, Requires<[HasSSE2]>;
2301 //===----------------------------------------------------------------------===//
2302 // SSE3 Instructions
2303 //===----------------------------------------------------------------------===//
2305 // Move Instructions
2306 def MOVSHDUPrr : S3SI<0x16, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2307 "movshdup\t{$src, $dst|$dst, $src}",
2308 [(set VR128:$dst, (v4f32 (vector_shuffle
2309 VR128:$src, (undef),
2310 MOVSHDUP_shuffle_mask)))]>;
2311 def MOVSHDUPrm : S3SI<0x16, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2312 "movshdup\t{$src, $dst|$dst, $src}",
2313 [(set VR128:$dst, (v4f32 (vector_shuffle
2314 (memopv4f32 addr:$src), (undef),
2315 MOVSHDUP_shuffle_mask)))]>;
2317 def MOVSLDUPrr : S3SI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2318 "movsldup\t{$src, $dst|$dst, $src}",
2319 [(set VR128:$dst, (v4f32 (vector_shuffle
2320 VR128:$src, (undef),
2321 MOVSLDUP_shuffle_mask)))]>;
2322 def MOVSLDUPrm : S3SI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
2323 "movsldup\t{$src, $dst|$dst, $src}",
2324 [(set VR128:$dst, (v4f32 (vector_shuffle
2325 (memopv4f32 addr:$src), (undef),
2326 MOVSLDUP_shuffle_mask)))]>;
2328 def MOVDDUPrr : S3DI<0x12, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
2329 "movddup\t{$src, $dst|$dst, $src}",
2330 [(set VR128:$dst, (v2f64 (vector_shuffle
2331 VR128:$src, (undef),
2332 SSE_splat_lo_mask)))]>;
2333 def MOVDDUPrm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
2334 "movddup\t{$src, $dst|$dst, $src}",
2336 (v2f64 (vector_shuffle
2337 (scalar_to_vector (loadf64 addr:$src)),
2339 SSE_splat_lo_mask)))]>;
2342 let isTwoAddress = 1 in {
2343 def ADDSUBPSrr : S3DI<0xD0, MRMSrcReg,
2344 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2345 "addsubps\t{$src2, $dst|$dst, $src2}",
2346 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2348 def ADDSUBPSrm : S3DI<0xD0, MRMSrcMem,
2349 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2350 "addsubps\t{$src2, $dst|$dst, $src2}",
2351 [(set VR128:$dst, (int_x86_sse3_addsub_ps VR128:$src1,
2352 (load addr:$src2)))]>;
2353 def ADDSUBPDrr : S3I<0xD0, MRMSrcReg,
2354 (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2355 "addsubpd\t{$src2, $dst|$dst, $src2}",
2356 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2358 def ADDSUBPDrm : S3I<0xD0, MRMSrcMem,
2359 (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2360 "addsubpd\t{$src2, $dst|$dst, $src2}",
2361 [(set VR128:$dst, (int_x86_sse3_addsub_pd VR128:$src1,
2362 (load addr:$src2)))]>;
2365 def LDDQUrm : S3DI<0xF0, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
2366 "lddqu\t{$src, $dst|$dst, $src}",
2367 [(set VR128:$dst, (int_x86_sse3_ldu_dq addr:$src))]>;
2370 class S3D_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2371 : S3DI<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2372 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2373 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, VR128:$src2)))]>;
2374 class S3D_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2375 : S3DI<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2376 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2377 [(set VR128:$dst, (v4f32 (IntId VR128:$src1, (load addr:$src2))))]>;
2378 class S3_Intrr<bits<8> o, string OpcodeStr, Intrinsic IntId>
2379 : S3I<o, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
2380 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2381 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, VR128:$src2)))]>;
2382 class S3_Intrm<bits<8> o, string OpcodeStr, Intrinsic IntId>
2383 : S3I<o, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2),
2384 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2385 [(set VR128:$dst, (v2f64 (IntId VR128:$src1, (load addr:$src2))))]>;
2387 let isTwoAddress = 1 in {
2388 def HADDPSrr : S3D_Intrr<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2389 def HADDPSrm : S3D_Intrm<0x7C, "haddps", int_x86_sse3_hadd_ps>;
2390 def HADDPDrr : S3_Intrr <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2391 def HADDPDrm : S3_Intrm <0x7C, "haddpd", int_x86_sse3_hadd_pd>;
2392 def HSUBPSrr : S3D_Intrr<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2393 def HSUBPSrm : S3D_Intrm<0x7D, "hsubps", int_x86_sse3_hsub_ps>;
2394 def HSUBPDrr : S3_Intrr <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2395 def HSUBPDrm : S3_Intrm <0x7D, "hsubpd", int_x86_sse3_hsub_pd>;
2398 // Thread synchronization
2399 def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
2400 [(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
2401 def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
2402 [(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
2404 // vector_shuffle v1, <undef> <1, 1, 3, 3>
2405 let AddedComplexity = 15 in
2406 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2407 MOVSHDUP_shuffle_mask)),
2408 (MOVSHDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2409 let AddedComplexity = 20 in
2410 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2411 MOVSHDUP_shuffle_mask)),
2412 (MOVSHDUPrm addr:$src)>, Requires<[HasSSE3]>;
2414 // vector_shuffle v1, <undef> <0, 0, 2, 2>
2415 let AddedComplexity = 15 in
2416 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2417 MOVSLDUP_shuffle_mask)),
2418 (MOVSLDUPrr VR128:$src)>, Requires<[HasSSE3]>;
2419 let AddedComplexity = 20 in
2420 def : Pat<(v4i32 (vector_shuffle (bc_v4i32 (memopv2i64 addr:$src)), (undef),
2421 MOVSLDUP_shuffle_mask)),
2422 (MOVSLDUPrm addr:$src)>, Requires<[HasSSE3]>;
2424 //===----------------------------------------------------------------------===//
2425 // SSSE3 Instructions
2426 //===----------------------------------------------------------------------===//
2428 // SSSE3 Instruction Templates:
2430 // SS38I - SSSE3 instructions with T8 prefix.
2431 // SS3AI - SSSE3 instructions with TA prefix.
2433 // Note: SSSE3 instructions have 64-bit and 128-bit versions. The 64-bit version
2434 // uses the MMX registers. We put those instructions here because they better
2435 // fit into the SSSE3 instruction category rather than the MMX category.
2437 class SS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
2439 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSSE3]>;
2440 class SS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
2442 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSSE3]>;
2444 /// SS3I_unop_rm_int_8 - Simple SSSE3 unary operator whose type is v*i8.
2445 multiclass SS3I_unop_rm_int_8<bits<8> opc, string OpcodeStr,
2446 Intrinsic IntId64, Intrinsic IntId128> {
2447 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst), (ins VR64:$src),
2448 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2449 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2451 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst), (ins i64mem:$src),
2452 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2454 (IntId64 (bitconvert (memopv8i8 addr:$src))))]>;
2456 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2458 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2459 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2462 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2464 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2467 (bitconvert (memopv16i8 addr:$src))))]>, OpSize;
2470 /// SS3I_unop_rm_int_16 - Simple SSSE3 unary operator whose type is v*i16.
2471 multiclass SS3I_unop_rm_int_16<bits<8> opc, string OpcodeStr,
2472 Intrinsic IntId64, Intrinsic IntId128> {
2473 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2475 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2476 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2478 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2480 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2483 (bitconvert (memopv4i16 addr:$src))))]>;
2485 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2487 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2488 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2491 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2493 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2496 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
2499 /// SS3I_unop_rm_int_32 - Simple SSSE3 unary operator whose type is v*i32.
2500 multiclass SS3I_unop_rm_int_32<bits<8> opc, string OpcodeStr,
2501 Intrinsic IntId64, Intrinsic IntId128> {
2502 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2504 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2505 [(set VR64:$dst, (IntId64 VR64:$src))]>;
2507 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2509 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2512 (bitconvert (memopv2i32 addr:$src))))]>;
2514 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2516 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2517 [(set VR128:$dst, (IntId128 VR128:$src))]>,
2520 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2522 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2525 (bitconvert (memopv4i32 addr:$src))))]>, OpSize;
2528 defm PABSB : SS3I_unop_rm_int_8 <0x1C, "pabsb",
2529 int_x86_ssse3_pabs_b,
2530 int_x86_ssse3_pabs_b_128>;
2531 defm PABSW : SS3I_unop_rm_int_16<0x1D, "pabsw",
2532 int_x86_ssse3_pabs_w,
2533 int_x86_ssse3_pabs_w_128>;
2534 defm PABSD : SS3I_unop_rm_int_32<0x1E, "pabsd",
2535 int_x86_ssse3_pabs_d,
2536 int_x86_ssse3_pabs_d_128>;
2538 /// SS3I_binop_rm_int_8 - Simple SSSE3 binary operator whose type is v*i8.
2539 let isTwoAddress = 1 in {
2540 multiclass SS3I_binop_rm_int_8<bits<8> opc, string OpcodeStr,
2541 Intrinsic IntId64, Intrinsic IntId128,
2542 bit Commutable = 0> {
2543 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2544 (ins VR64:$src1, VR64:$src2),
2545 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2546 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2547 let isCommutable = Commutable;
2549 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2550 (ins VR64:$src1, i64mem:$src2),
2551 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2553 (IntId64 VR64:$src1,
2554 (bitconvert (memopv8i8 addr:$src2))))]>;
2556 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2557 (ins VR128:$src1, VR128:$src2),
2558 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2559 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2561 let isCommutable = Commutable;
2563 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2564 (ins VR128:$src1, i128mem:$src2),
2565 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2567 (IntId128 VR128:$src1,
2568 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
2572 /// SS3I_binop_rm_int_16 - Simple SSSE3 binary operator whose type is v*i16.
2573 let isTwoAddress = 1 in {
2574 multiclass SS3I_binop_rm_int_16<bits<8> opc, string OpcodeStr,
2575 Intrinsic IntId64, Intrinsic IntId128,
2576 bit Commutable = 0> {
2577 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2578 (ins VR64:$src1, VR64:$src2),
2579 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2580 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2581 let isCommutable = Commutable;
2583 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2584 (ins VR64:$src1, i64mem:$src2),
2585 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2587 (IntId64 VR64:$src1,
2588 (bitconvert (memopv4i16 addr:$src2))))]>;
2590 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2591 (ins VR128:$src1, VR128:$src2),
2592 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2593 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2595 let isCommutable = Commutable;
2597 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2598 (ins VR128:$src1, i128mem:$src2),
2599 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2601 (IntId128 VR128:$src1,
2602 (bitconvert (memopv8i16 addr:$src2))))]>, OpSize;
2606 /// SS3I_binop_rm_int_32 - Simple SSSE3 binary operator whose type is v*i32.
2607 let isTwoAddress = 1 in {
2608 multiclass SS3I_binop_rm_int_32<bits<8> opc, string OpcodeStr,
2609 Intrinsic IntId64, Intrinsic IntId128,
2610 bit Commutable = 0> {
2611 def rr64 : SS38I<opc, MRMSrcReg, (outs VR64:$dst),
2612 (ins VR64:$src1, VR64:$src2),
2613 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2614 [(set VR64:$dst, (IntId64 VR64:$src1, VR64:$src2))]> {
2615 let isCommutable = Commutable;
2617 def rm64 : SS38I<opc, MRMSrcMem, (outs VR64:$dst),
2618 (ins VR64:$src1, i64mem:$src2),
2619 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2621 (IntId64 VR64:$src1,
2622 (bitconvert (memopv2i32 addr:$src2))))]>;
2624 def rr128 : SS38I<opc, MRMSrcReg, (outs VR128:$dst),
2625 (ins VR128:$src1, VR128:$src2),
2626 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2627 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
2629 let isCommutable = Commutable;
2631 def rm128 : SS38I<opc, MRMSrcMem, (outs VR128:$dst),
2632 (ins VR128:$src1, i128mem:$src2),
2633 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
2635 (IntId128 VR128:$src1,
2636 (bitconvert (memopv4i32 addr:$src2))))]>, OpSize;
2640 defm PHADDW : SS3I_binop_rm_int_16<0x01, "phaddw",
2641 int_x86_ssse3_phadd_w,
2642 int_x86_ssse3_phadd_w_128, 1>;
2643 defm PHADDD : SS3I_binop_rm_int_32<0x02, "phaddd",
2644 int_x86_ssse3_phadd_d,
2645 int_x86_ssse3_phadd_d_128, 1>;
2646 defm PHADDSW : SS3I_binop_rm_int_16<0x03, "phaddsw",
2647 int_x86_ssse3_phadd_sw,
2648 int_x86_ssse3_phadd_sw_128, 1>;
2649 defm PHSUBW : SS3I_binop_rm_int_16<0x05, "phsubw",
2650 int_x86_ssse3_phsub_w,
2651 int_x86_ssse3_phsub_w_128>;
2652 defm PHSUBD : SS3I_binop_rm_int_32<0x06, "phsubd",
2653 int_x86_ssse3_phsub_d,
2654 int_x86_ssse3_phsub_d_128>;
2655 defm PHSUBSW : SS3I_binop_rm_int_16<0x07, "phsubsw",
2656 int_x86_ssse3_phsub_sw,
2657 int_x86_ssse3_phsub_sw_128>;
2658 defm PMADDUBSW : SS3I_binop_rm_int_8 <0x04, "pmaddubsw",
2659 int_x86_ssse3_pmadd_ub_sw,
2660 int_x86_ssse3_pmadd_ub_sw_128, 1>;
2661 defm PMULHRSW : SS3I_binop_rm_int_16<0x0B, "pmulhrsw",
2662 int_x86_ssse3_pmul_hr_sw,
2663 int_x86_ssse3_pmul_hr_sw_128, 1>;
2664 defm PSHUFB : SS3I_binop_rm_int_8 <0x00, "pshufb",
2665 int_x86_ssse3_pshuf_b,
2666 int_x86_ssse3_pshuf_b_128>;
2667 defm PSIGNB : SS3I_binop_rm_int_8 <0x08, "psignb",
2668 int_x86_ssse3_psign_b,
2669 int_x86_ssse3_psign_b_128>;
2670 defm PSIGNW : SS3I_binop_rm_int_16<0x09, "psignw",
2671 int_x86_ssse3_psign_w,
2672 int_x86_ssse3_psign_w_128>;
2673 defm PSIGND : SS3I_binop_rm_int_32<0x09, "psignd",
2674 int_x86_ssse3_psign_d,
2675 int_x86_ssse3_psign_d_128>;
2677 let isTwoAddress = 1 in {
2678 def PALIGNR64rr : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2679 (ins VR64:$src1, VR64:$src2, i16imm:$src3),
2680 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2682 (int_x86_ssse3_palign_r
2683 VR64:$src1, VR64:$src2,
2685 def PALIGNR64rm : SS3AI<0x0F, MRMSrcReg, (outs VR64:$dst),
2686 (ins VR64:$src1, i64mem:$src2, i16imm:$src3),
2687 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2689 (int_x86_ssse3_palign_r
2691 (bitconvert (memopv2i32 addr:$src2)),
2694 def PALIGNR128rr : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2695 (ins VR128:$src1, VR128:$src2, i32imm:$src3),
2696 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2698 (int_x86_ssse3_palign_r_128
2699 VR128:$src1, VR128:$src2,
2700 imm:$src3))]>, OpSize;
2701 def PALIGNR128rm : SS3AI<0x0F, MRMSrcReg, (outs VR128:$dst),
2702 (ins VR128:$src1, i128mem:$src2, i32imm:$src3),
2703 "palignr\t{$src3, $src2, $dst|$dst, $src2, $src3}",
2705 (int_x86_ssse3_palign_r_128
2707 (bitconvert (memopv4i32 addr:$src2)),
2708 imm:$src3))]>, OpSize;
2711 //===----------------------------------------------------------------------===//
2712 // Non-Instruction Patterns
2713 //===----------------------------------------------------------------------===//
2715 // 128-bit vector undef's.
2716 def : Pat<(v4f32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2717 def : Pat<(v2f64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2718 def : Pat<(v16i8 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2719 def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2720 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2721 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
2723 // extload f32 -> f64. This matches load+fextend because we have a hack in
2724 // the isel (PreprocessForFPConvert) that can introduce loads after dag combine.
2725 // Since these loads aren't folded into the fextend, we have to match it
2727 let Predicates = [HasSSE2] in
2728 def : Pat<(fextend (loadf32 addr:$src)),
2729 (CVTSS2SDrm addr:$src)>;
2731 // Scalar to v8i16 / v16i8. The source may be a GR32, but only the lower 8 or
2733 def : Pat<(v8i16 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2734 Requires<[HasSSE2]>;
2735 def : Pat<(v16i8 (X86s2vec GR32:$src)), (MOVDI2PDIrr GR32:$src)>,
2736 Requires<[HasSSE2]>;
2739 let Predicates = [HasSSE2] in {
2740 def : Pat<(v2i64 (bitconvert (v4i32 VR128:$src))), (v2i64 VR128:$src)>;
2741 def : Pat<(v2i64 (bitconvert (v8i16 VR128:$src))), (v2i64 VR128:$src)>;
2742 def : Pat<(v2i64 (bitconvert (v16i8 VR128:$src))), (v2i64 VR128:$src)>;
2743 def : Pat<(v2i64 (bitconvert (v2f64 VR128:$src))), (v2i64 VR128:$src)>;
2744 def : Pat<(v2i64 (bitconvert (v4f32 VR128:$src))), (v2i64 VR128:$src)>;
2745 def : Pat<(v4i32 (bitconvert (v2i64 VR128:$src))), (v4i32 VR128:$src)>;
2746 def : Pat<(v4i32 (bitconvert (v8i16 VR128:$src))), (v4i32 VR128:$src)>;
2747 def : Pat<(v4i32 (bitconvert (v16i8 VR128:$src))), (v4i32 VR128:$src)>;
2748 def : Pat<(v4i32 (bitconvert (v2f64 VR128:$src))), (v4i32 VR128:$src)>;
2749 def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;
2750 def : Pat<(v8i16 (bitconvert (v2i64 VR128:$src))), (v8i16 VR128:$src)>;
2751 def : Pat<(v8i16 (bitconvert (v4i32 VR128:$src))), (v8i16 VR128:$src)>;
2752 def : Pat<(v8i16 (bitconvert (v16i8 VR128:$src))), (v8i16 VR128:$src)>;
2753 def : Pat<(v8i16 (bitconvert (v2f64 VR128:$src))), (v8i16 VR128:$src)>;
2754 def : Pat<(v8i16 (bitconvert (v4f32 VR128:$src))), (v8i16 VR128:$src)>;
2755 def : Pat<(v16i8 (bitconvert (v2i64 VR128:$src))), (v16i8 VR128:$src)>;
2756 def : Pat<(v16i8 (bitconvert (v4i32 VR128:$src))), (v16i8 VR128:$src)>;
2757 def : Pat<(v16i8 (bitconvert (v8i16 VR128:$src))), (v16i8 VR128:$src)>;
2758 def : Pat<(v16i8 (bitconvert (v2f64 VR128:$src))), (v16i8 VR128:$src)>;
2759 def : Pat<(v16i8 (bitconvert (v4f32 VR128:$src))), (v16i8 VR128:$src)>;
2760 def : Pat<(v4f32 (bitconvert (v2i64 VR128:$src))), (v4f32 VR128:$src)>;
2761 def : Pat<(v4f32 (bitconvert (v4i32 VR128:$src))), (v4f32 VR128:$src)>;
2762 def : Pat<(v4f32 (bitconvert (v8i16 VR128:$src))), (v4f32 VR128:$src)>;
2763 def : Pat<(v4f32 (bitconvert (v16i8 VR128:$src))), (v4f32 VR128:$src)>;
2764 def : Pat<(v4f32 (bitconvert (v2f64 VR128:$src))), (v4f32 VR128:$src)>;
2765 def : Pat<(v2f64 (bitconvert (v2i64 VR128:$src))), (v2f64 VR128:$src)>;
2766 def : Pat<(v2f64 (bitconvert (v4i32 VR128:$src))), (v2f64 VR128:$src)>;
2767 def : Pat<(v2f64 (bitconvert (v8i16 VR128:$src))), (v2f64 VR128:$src)>;
2768 def : Pat<(v2f64 (bitconvert (v16i8 VR128:$src))), (v2f64 VR128:$src)>;
2769 def : Pat<(v2f64 (bitconvert (v4f32 VR128:$src))), (v2f64 VR128:$src)>;
2772 // Move scalar to XMM zero-extended
2773 // movd to XMM register zero-extends
2774 let AddedComplexity = 15 in {
2775 // Zeroing a VR128 then do a MOVS{S|D} to the lower bits.
2776 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
2777 (v2f64 (scalar_to_vector FR64:$src)), MOVL_shuffle_mask)),
2778 (MOVLSD2PDrr (V_SET0), FR64:$src)>, Requires<[HasSSE2]>;
2779 def : Pat<(v4f32 (vector_shuffle immAllZerosV_bc,
2780 (v4f32 (scalar_to_vector FR32:$src)), MOVL_shuffle_mask)),
2781 (MOVLSS2PSrr (V_SET0), FR32:$src)>, Requires<[HasSSE2]>;
2784 // Splat v2f64 / v2i64
2785 let AddedComplexity = 10 in {
2786 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2787 (UNPCKLPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2788 def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2789 (UNPCKHPDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2790 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), SSE_splat_lo_mask:$sm),
2791 (PUNPCKLQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2792 def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKH_shuffle_mask:$sm),
2793 (PUNPCKHQDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2797 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SSE_splat_mask:$sm),
2798 (SHUFPSrri VR128:$src, VR128:$src, SSE_splat_mask:$sm)>,
2799 Requires<[HasSSE1]>;
2801 // Special unary SHUFPSrri case.
2802 // FIXME: when we want non two-address code, then we should use PSHUFD?
2803 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2804 SHUFP_unary_shuffle_mask:$sm)),
2805 (SHUFPSrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2806 Requires<[HasSSE1]>;
2807 // Special unary SHUFPDrri case.
2808 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (undef),
2809 SHUFP_unary_shuffle_mask:$sm)),
2810 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2811 Requires<[HasSSE2]>;
2812 // Unary v4f32 shuffle with PSHUF* in order to fold a load.
2813 def : Pat<(vector_shuffle (memopv4f32 addr:$src1), (undef),
2814 SHUFP_unary_shuffle_mask:$sm),
2815 (PSHUFDmi addr:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2816 Requires<[HasSSE2]>;
2817 // Special binary v4i32 shuffle cases with SHUFPS.
2818 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (v4i32 VR128:$src2),
2819 PSHUFD_binary_shuffle_mask:$sm)),
2820 (SHUFPSrri VR128:$src1, VR128:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2821 Requires<[HasSSE2]>;
2822 def : Pat<(v4i32 (vector_shuffle VR128:$src1,
2823 (bc_v4i32 (memopv2i64 addr:$src2)), PSHUFD_binary_shuffle_mask:$sm)),
2824 (SHUFPSrmi VR128:$src1, addr:$src2, PSHUFD_binary_shuffle_mask:$sm)>,
2825 Requires<[HasSSE2]>;
2826 // Special binary v2i64 shuffle cases using SHUFPDrri.
2827 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2828 SHUFP_shuffle_mask:$sm)),
2829 (SHUFPDrri VR128:$src1, VR128:$src2, SHUFP_shuffle_mask:$sm)>,
2830 Requires<[HasSSE2]>;
2831 // Special unary SHUFPDrri case.
2832 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (undef),
2833 SHUFP_unary_shuffle_mask:$sm)),
2834 (SHUFPDrri VR128:$src1, VR128:$src1, SHUFP_unary_shuffle_mask:$sm)>,
2835 Requires<[HasSSE2]>;
2837 // vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
2838 let AddedComplexity = 10 in {
2839 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2840 UNPCKL_v_undef_shuffle_mask)),
2841 (UNPCKLPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2842 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2843 UNPCKL_v_undef_shuffle_mask)),
2844 (PUNPCKLBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2845 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2846 UNPCKL_v_undef_shuffle_mask)),
2847 (PUNPCKLWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2848 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2849 UNPCKL_v_undef_shuffle_mask)),
2850 (PUNPCKLDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2853 // vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
2854 let AddedComplexity = 10 in {
2855 def : Pat<(v4f32 (vector_shuffle VR128:$src, (undef),
2856 UNPCKH_v_undef_shuffle_mask)),
2857 (UNPCKHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2858 def : Pat<(v16i8 (vector_shuffle VR128:$src, (undef),
2859 UNPCKH_v_undef_shuffle_mask)),
2860 (PUNPCKHBWrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2861 def : Pat<(v8i16 (vector_shuffle VR128:$src, (undef),
2862 UNPCKH_v_undef_shuffle_mask)),
2863 (PUNPCKHWDrr VR128:$src, VR128:$src)>, Requires<[HasSSE2]>;
2864 def : Pat<(v4i32 (vector_shuffle VR128:$src, (undef),
2865 UNPCKH_v_undef_shuffle_mask)),
2866 (PUNPCKHDQrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
2869 let AddedComplexity = 15 in {
2870 // vector_shuffle v1, v2 <0, 1, 4, 5> using MOVLHPS
2871 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2872 MOVHP_shuffle_mask)),
2873 (MOVLHPSrr VR128:$src1, VR128:$src2)>;
2875 // vector_shuffle v1, v2 <6, 7, 2, 3> using MOVHLPS
2876 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2877 MOVHLPS_shuffle_mask)),
2878 (MOVHLPSrr VR128:$src1, VR128:$src2)>;
2880 // vector_shuffle v1, undef <2, ?, ?, ?> using MOVHLPS
2881 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (undef),
2882 MOVHLPS_v_undef_shuffle_mask)),
2883 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2884 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (undef),
2885 MOVHLPS_v_undef_shuffle_mask)),
2886 (MOVHLPSrr VR128:$src1, VR128:$src1)>;
2889 let AddedComplexity = 20 in {
2890 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
2891 // vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
2892 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2893 MOVLP_shuffle_mask)),
2894 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2895 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2896 MOVLP_shuffle_mask)),
2897 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2898 def : Pat<(v4f32 (vector_shuffle VR128:$src1, (memopv4f32 addr:$src2),
2899 MOVHP_shuffle_mask)),
2900 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2901 def : Pat<(v2f64 (vector_shuffle VR128:$src1, (memopv2f64 addr:$src2),
2902 MOVHP_shuffle_mask)),
2903 (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2905 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2906 MOVLP_shuffle_mask)),
2907 (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2908 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2909 MOVLP_shuffle_mask)),
2910 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2911 def : Pat<(v4i32 (vector_shuffle VR128:$src1, (bc_v4i32 (memopv2i64 addr:$src2)),
2912 MOVHP_shuffle_mask)),
2913 (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
2914 def : Pat<(v2i64 (vector_shuffle VR128:$src1, (memopv2i64 addr:$src2),
2915 MOVLP_shuffle_mask)),
2916 (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2919 let AddedComplexity = 15 in {
2920 // Setting the lowest element in the vector.
2921 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2922 MOVL_shuffle_mask)),
2923 (MOVLPSrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2924 def : Pat<(v2i64 (vector_shuffle VR128:$src1, VR128:$src2,
2925 MOVL_shuffle_mask)),
2926 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2928 // vector_shuffle v1, v2 <4, 5, 2, 3> using MOVLPDrr (movsd)
2929 def : Pat<(v4f32 (vector_shuffle VR128:$src1, VR128:$src2,
2930 MOVLP_shuffle_mask)),
2931 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2932 def : Pat<(v4i32 (vector_shuffle VR128:$src1, VR128:$src2,
2933 MOVLP_shuffle_mask)),
2934 (MOVLPDrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2937 // Set lowest element and zero upper elements.
2938 let AddedComplexity = 15 in
2939 def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc, VR128:$src,
2940 MOVL_shuffle_mask)),
2941 (MOVZPQILo2PQIrr VR128:$src)>, Requires<[HasSSE2]>;
2944 // FIXME: Temporary workaround since 2-wide shuffle is broken.
2945 def : Pat<(int_x86_sse2_movs_d VR128:$src1, VR128:$src2),
2946 (v2f64 (MOVLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2947 def : Pat<(int_x86_sse2_loadh_pd VR128:$src1, addr:$src2),
2948 (v2f64 (MOVHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2949 def : Pat<(int_x86_sse2_loadl_pd VR128:$src1, addr:$src2),
2950 (v2f64 (MOVLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2951 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, VR128:$src2, imm:$src3),
2952 (v2f64 (SHUFPDrri VR128:$src1, VR128:$src2, imm:$src3))>,
2953 Requires<[HasSSE2]>;
2954 def : Pat<(int_x86_sse2_shuf_pd VR128:$src1, (load addr:$src2), imm:$src3),
2955 (v2f64 (SHUFPDrmi VR128:$src1, addr:$src2, imm:$src3))>,
2956 Requires<[HasSSE2]>;
2957 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, VR128:$src2),
2958 (v2f64 (UNPCKHPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2959 def : Pat<(int_x86_sse2_unpckh_pd VR128:$src1, (load addr:$src2)),
2960 (v2f64 (UNPCKHPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2961 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, VR128:$src2),
2962 (v2f64 (UNPCKLPDrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2963 def : Pat<(int_x86_sse2_unpckl_pd VR128:$src1, (load addr:$src2)),
2964 (v2f64 (UNPCKLPDrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2965 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, VR128:$src2),
2966 (v2i64 (PUNPCKHQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2967 def : Pat<(int_x86_sse2_punpckh_qdq VR128:$src1, (load addr:$src2)),
2968 (v2i64 (PUNPCKHQDQrm VR128:$src1, addr:$src2))>, Requires<[HasSSE2]>;
2969 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, VR128:$src2),
2970 (v2i64 (PUNPCKLQDQrr VR128:$src1, VR128:$src2))>, Requires<[HasSSE2]>;
2971 def : Pat<(int_x86_sse2_punpckl_qdq VR128:$src1, (load addr:$src2)),
2972 (PUNPCKLQDQrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2974 // Some special case pandn patterns.
2975 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2977 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2978 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2980 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2981 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2983 (PANDNrr VR128:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
2985 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v4i32 immAllOnesV))),
2986 (memopv2i64 addr:$src2))),
2987 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2988 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v8i16 immAllOnesV))),
2989 (memopv2i64 addr:$src2))),
2990 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2991 def : Pat<(v2i64 (and (xor VR128:$src1, (bc_v2i64 (v16i8 immAllOnesV))),
2992 (memopv2i64 addr:$src2))),
2993 (PANDNrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
2995 // vector -> vector casts
2996 def : Pat<(v4f32 (sint_to_fp (v4i32 VR128:$src))),
2997 (Int_CVTDQ2PSrr VR128:$src)>, Requires<[HasSSE2]>;
2998 def : Pat<(v4i32 (fp_to_sint (v4f32 VR128:$src))),
2999 (Int_CVTTPS2DQrr VR128:$src)>, Requires<[HasSSE2]>;
3001 // Use movaps / movups for SSE integer load / store (one byte shorter).
3002 def : Pat<(alignedloadv4i32 addr:$src),
3003 (MOVAPSrm addr:$src)>, Requires<[HasSSE1]>;
3004 def : Pat<(loadv4i32 addr:$src),
3005 (MOVUPSrm addr:$src)>, Requires<[HasSSE1]>;
3006 def : Pat<(alignedloadv2i64 addr:$src),
3007 (MOVAPSrm addr:$src)>, Requires<[HasSSE2]>;
3008 def : Pat<(loadv2i64 addr:$src),
3009 (MOVUPSrm addr:$src)>, Requires<[HasSSE2]>;
3011 def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
3012 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3013 def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
3014 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3015 def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
3016 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3017 def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
3018 (MOVAPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3019 def : Pat<(store (v2i64 VR128:$src), addr:$dst),
3020 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3021 def : Pat<(store (v4i32 VR128:$src), addr:$dst),
3022 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3023 def : Pat<(store (v8i16 VR128:$src), addr:$dst),
3024 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3025 def : Pat<(store (v16i8 VR128:$src), addr:$dst),
3026 (MOVUPSmr addr:$dst, VR128:$src)>, Requires<[HasSSE2]>;
3028 //===----------------------------------------------------------------------===//
3029 // SSE4.1 Instructions
3030 //===----------------------------------------------------------------------===//
3032 // SSE4.1 Instruction Templates:
3034 // SS48I - SSE 4.1 instructions with T8 prefix.
3035 // SS41AI - SSE 4.1 instructions with TA prefix.
3037 class SS48I<bits<8> o, Format F, dag outs, dag ins, string asm,
3039 : I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE41]>;
3040 class SS4AI<bits<8> o, Format F, dag outs, dag ins, string asm,
3042 : I<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
3045 multiclass sse41_fp_unop_rm<bits<8> opcss, bits<8> opcps,
3046 bits<8> opcsd, bits<8> opcpd,
3051 Intrinsic V2F64Int> {
3052 // Intrinsic operation, reg.
3053 def SSr_Int : SS4AI<opcss, MRMSrcReg,
3054 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3055 !strconcat(OpcodeStr,
3056 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3057 [(set VR128:$dst, (F32Int VR128:$src1, imm:$src2))]>,
3060 // Intrinsic operation, mem.
3061 def SSm_Int : SS4AI<opcss, MRMSrcMem,
3062 (outs VR128:$dst), (ins ssmem:$src1, i32i8imm:$src2),
3063 !strconcat(OpcodeStr,
3064 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3065 [(set VR128:$dst, (F32Int sse_load_f32:$src1, imm:$src2))]>,
3068 // Vector intrinsic operation, reg
3069 def PSr_Int : SS4AI<opcps, MRMSrcReg,
3070 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3071 !strconcat(OpcodeStr,
3072 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3073 [(set VR128:$dst, (V4F32Int VR128:$src1, imm:$src2))]>,
3076 // Vector intrinsic operation, mem
3077 def PSm_Int : SS4AI<opcps, MRMSrcMem,
3078 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3079 !strconcat(OpcodeStr,
3080 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3081 [(set VR128:$dst, (V4F32Int (load addr:$src1),imm:$src2))]>,
3084 // Intrinsic operation, reg.
3085 def SDr_Int : SS4AI<opcsd, MRMSrcReg,
3086 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3087 !strconcat(OpcodeStr,
3088 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3089 [(set VR128:$dst, (F64Int VR128:$src1, imm:$src2))]>,
3092 // Intrinsic operation, mem.
3093 def SDm_Int : SS4AI<opcsd, MRMSrcMem,
3094 (outs VR128:$dst), (ins sdmem:$src1, i32i8imm:$src2),
3095 !strconcat(OpcodeStr,
3096 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3097 [(set VR128:$dst, (F64Int sse_load_f64:$src1, imm:$src2))]>,
3100 // Vector intrinsic operation, reg
3101 def PDr_Int : SS4AI<opcpd, MRMSrcReg,
3102 (outs VR128:$dst), (ins VR128:$src1, i32i8imm:$src2),
3103 !strconcat(OpcodeStr,
3104 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3105 [(set VR128:$dst, (V2F64Int VR128:$src1, imm:$src2))]>,
3108 // Vector intrinsic operation, mem
3109 def PDm_Int : SS4AI<opcpd, MRMSrcMem,
3110 (outs VR128:$dst), (ins f128mem:$src1, i32i8imm:$src2),
3111 !strconcat(OpcodeStr,
3112 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3113 [(set VR128:$dst, (V2F64Int (load addr:$src1),imm:$src2))]>,
3117 // FP round - roundss, roundps, roundsd, roundpd
3118 defm ROUND : sse41_fp_unop_rm<0x0A, 0x08, 0x0B, 0x09, "round",
3119 int_x86_sse41_round_ss, int_x86_sse41_round_ps,
3120 int_x86_sse41_round_sd, int_x86_sse41_round_pd>;
3122 // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16.
3123 multiclass SS41I_unop_rm_int_v16<bits<8> opc, string OpcodeStr,
3124 Intrinsic IntId128> {
3125 def rr128 : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3127 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3128 [(set VR128:$dst, (IntId128 VR128:$src))]>, OpSize;
3129 def rm128 : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3131 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3134 (bitconvert (memopv8i16 addr:$src))))]>, OpSize;
3137 defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
3138 int_x86_sse41_phminposuw>;
3140 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3141 let isTwoAddress = 1 in {
3142 multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
3143 Intrinsic IntId128, bit Commutable = 0> {
3144 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3145 (ins VR128:$src1, VR128:$src2),
3146 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3147 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3149 let isCommutable = Commutable;
3151 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3152 (ins VR128:$src1, i128mem:$src2),
3153 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3155 (IntId128 VR128:$src1,
3156 (bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
3160 defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
3161 int_x86_sse41_pcmpeqq, 1>;
3162 defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
3163 int_x86_sse41_packusdw, 0>;
3164 defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
3165 int_x86_sse41_pminsb, 1>;
3166 defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
3167 int_x86_sse41_pminsd, 1>;
3168 defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
3169 int_x86_sse41_pminud, 1>;
3170 defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
3171 int_x86_sse41_pminuw, 1>;
3172 defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
3173 int_x86_sse41_pmaxsb, 1>;
3174 defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
3175 int_x86_sse41_pmaxsd, 1>;
3176 defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
3177 int_x86_sse41_pmaxud, 1>;
3178 defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
3179 int_x86_sse41_pmaxuw, 1>;
3180 defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
3181 int_x86_sse41_pmuldq, 1>;
3184 /// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
3185 let isTwoAddress = 1 in {
3186 multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, SDNode OpNode,
3187 Intrinsic IntId128, bit Commutable = 0> {
3188 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3189 (ins VR128:$src1, VR128:$src2),
3190 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3191 [(set VR128:$dst, (OpNode (v4i32 VR128:$src1),
3192 VR128:$src2))]>, OpSize {
3193 let isCommutable = Commutable;
3195 def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
3196 (ins VR128:$src1, VR128:$src2),
3197 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3198 [(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
3200 let isCommutable = Commutable;
3202 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3203 (ins VR128:$src1, i128mem:$src2),
3204 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3206 (OpNode VR128:$src1, (memopv4i32 addr:$src2)))]>, OpSize;
3207 def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
3208 (ins VR128:$src1, i128mem:$src2),
3209 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
3211 (IntId128 VR128:$src1, (memopv4i32 addr:$src2)))]>,
3215 defm PMULLD : SS41I_binop_patint<0x40, "pmulld", mul,
3216 int_x86_sse41_pmulld, 1>;
3219 /// SS41I_binop_rmi_int - SSE 4.1 binary operator with immediate
3220 let isTwoAddress = 1 in {
3221 multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
3222 Intrinsic IntId128, bit Commutable = 0> {
3223 def rri : SS4AI<opc, MRMSrcReg, (outs VR128:$dst),
3224 (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
3225 !strconcat(OpcodeStr,
3226 "\t{$$src3, src2, $dst|$dst, $src2, $src3}"),
3228 (IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
3230 let isCommutable = Commutable;
3232 def rmi : SS4AI<opc, MRMSrcMem, (outs VR128:$dst),
3233 (ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
3234 !strconcat(OpcodeStr,
3235 "\t{$$src3, src2, $dst|$dst, $src2, $src3}"),
3237 (IntId128 VR128:$src1,
3238 (bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
3243 defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
3244 int_x86_sse41_blendps, 0>;
3245 defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
3246 int_x86_sse41_blendpd, 0>;
3247 defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
3248 int_x86_sse41_pblendw, 0>;
3249 defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
3250 int_x86_sse41_dpps, 1>;
3251 defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
3252 int_x86_sse41_dppd, 1>;
3253 defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
3254 int_x86_sse41_mpsadbw, 0>;
3257 multiclass SS41I_binop_rm_int8<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3258 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3259 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3260 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3262 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i64mem:$src),
3263 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3265 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3268 defm PMOVSXBW : SS41I_binop_rm_int8<0x20, "pmovsxbw", int_x86_sse41_pmovsxbw>;
3269 defm PMOVSXWD : SS41I_binop_rm_int8<0x23, "pmovsxwd", int_x86_sse41_pmovsxwd>;
3270 defm PMOVSXDQ : SS41I_binop_rm_int8<0x25, "pmovsxdq", int_x86_sse41_pmovsxdq>;
3271 defm PMOVZXBW : SS41I_binop_rm_int8<0x30, "pmovzxbw", int_x86_sse41_pmovzxbw>;
3272 defm PMOVZXWD : SS41I_binop_rm_int8<0x33, "pmovzxwd", int_x86_sse41_pmovzxwd>;
3273 defm PMOVZXDQ : SS41I_binop_rm_int8<0x35, "pmovzxdq", int_x86_sse41_pmovzxdq>;
3275 multiclass SS41I_binop_rm_int4<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3276 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3277 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3278 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3280 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
3281 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3283 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3286 defm PMOVSXBD : SS41I_binop_rm_int4<0x21, "pmovsxbd", int_x86_sse41_pmovsxbd>;
3287 defm PMOVSXWQ : SS41I_binop_rm_int4<0x24, "pmovsxwq", int_x86_sse41_pmovsxwq>;
3288 defm PMOVZXBD : SS41I_binop_rm_int4<0x31, "pmovzxbd", int_x86_sse41_pmovzxbd>;
3289 defm PMOVZXWQ : SS41I_binop_rm_int4<0x34, "pmovzxwq", int_x86_sse41_pmovzxwq>;
3291 multiclass SS41I_binop_rm_int2<bits<8> opc, string OpcodeStr, Intrinsic IntId> {
3292 def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
3293 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3294 [(set VR128:$dst, (IntId VR128:$src))]>, OpSize;
3296 def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst), (ins i16mem:$src),
3297 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3299 (IntId (bitconvert (v4i32 (load addr:$src)))))]>, OpSize;
3302 defm PMOVSXBQ : SS41I_binop_rm_int2<0x22, "pmovsxbq", int_x86_sse41_pmovsxbq>;
3303 defm PMOVZXBQ : SS41I_binop_rm_int2<0x32, "pmovsxbq", int_x86_sse41_pmovzxbq>;
3306 /// SS41I_binop_ext8 - SSE 4.1 binary operator with immediate
3307 multiclass SS41I_binop_ext8<bits<8> opc, string OpcodeStr> {
3308 def rr : SS4AI<opc, MRMSrcReg, (outs GR32:$dst),
3309 (ins VR128:$src1, i32i8imm:$src2),
3310 !strconcat(OpcodeStr,
3311 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3312 [(set GR32:$dst, (zext
3313 (extractelt (v16i8 VR128:$src1), imm:$src2)))]>, OpSize;
3314 def mr : SS4AI<opc, MRMDestMem, (outs),
3315 (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),
3316 !strconcat(OpcodeStr,
3317 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3318 [(store (extractelt (v16i8 VR128:$src1), imm:$src2),
3319 addr:$dst)]>, OpSize;
3322 defm PEXTRB : SS41I_binop_ext8<0x14, "pextrb">;
3324 /// SS41I_binop_ext32 - SSE 4.1 binary operator with immediate
3325 multiclass SS41I_binop_ext32<bits<8> opc, string OpcodeStr> {
3326 def rr : SS4AI<opc, MRMSrcReg, (outs GR32:$dst),
3327 (ins VR128:$src1, i32i8imm:$src2),
3328 !strconcat(OpcodeStr,
3329 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3331 (extractelt (v4i32 VR128:$src1), imm:$src2))]>, OpSize;
3332 def mr : SS4AI<opc, MRMDestMem, (outs),
3333 (ins i32mem:$dst, VR128:$src1, i32i8imm:$src2),
3334 !strconcat(OpcodeStr,
3335 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3336 [(store (extractelt (v4i32 VR128:$src1), imm:$src2),
3337 addr:$dst)]>, OpSize;
3340 defm PEXTRD : SS41I_binop_ext32<0x16, "pextrd">;
3342 /// SS41I_binop_extf32 - SSE 4.1 binary operator with immediate
3343 multiclass SS41I_binop_extf32<bits<8> opc, string OpcodeStr> {
3344 def rr : SS4AI<opc, MRMSrcReg, (outs FR32:$dst),
3345 (ins VR128:$src1, i32i8imm:$src2),
3346 !strconcat(OpcodeStr,
3347 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3349 (extractelt (v4f32 VR128:$src1), imm:$src2))]>, OpSize;
3350 def mr : SS4AI<opc, MRMDestMem, (outs),
3351 (ins f32mem:$dst, VR128:$src1, i32i8imm:$src2),
3352 !strconcat(OpcodeStr,
3353 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
3354 [(store (extractelt (v4f32 VR128:$src1), imm:$src2),
3355 addr:$dst)]>, OpSize;
3358 defm EXTRACTPS : SS41I_binop_extf32<0x17, "extractps">;