1 //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the shift and rotate instructions.
12 //===----------------------------------------------------------------------===//
14 // FIXME: Someone needs to smear multipattern goodness all over this file.
16 let Defs = [EFLAGS] in {
18 let Constraints = "$src1 = $dst" in {
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, CL}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, CL}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, CL}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 "shl{q}\t{%cl, $dst|$dst, CL}",
31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
38 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>;
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
47 (ins GR64:$src1, i8imm:$src2),
48 "shl{q}\t{$src2, $dst|$dst, $src2}",
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
52 // NOTE: We don't include patterns for shifts of a register by one, because
53 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
54 let hasSideEffects = 0 in {
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
56 "shl{b}\t$dst", [], IIC_SR>;
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
58 "shl{w}\t$dst", [], IIC_SR>, OpSize;
59 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
60 "shl{l}\t$dst", [], IIC_SR>;
61 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
62 "shl{q}\t$dst", [], IIC_SR>;
63 } // hasSideEffects = 0
64 } // isConvertibleToThreeAddress = 1
65 } // Constraints = "$src = $dst"
68 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
71 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
72 "shl{b}\t{%cl, $dst|$dst, CL}",
73 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
74 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
75 "shl{w}\t{%cl, $dst|$dst, CL}",
76 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
78 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
79 "shl{l}\t{%cl, $dst|$dst, CL}",
80 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
81 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
82 "shl{q}\t{%cl, $dst|$dst, CL}",
83 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
85 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
86 "shl{b}\t{$src, $dst|$dst, $src}",
87 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
89 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
90 "shl{w}\t{$src, $dst|$dst, $src}",
91 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
94 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
95 "shl{l}\t{$src, $dst|$dst, $src}",
96 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
98 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
99 "shl{q}\t{$src, $dst|$dst, $src}",
100 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
104 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
106 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
108 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
110 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
113 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
115 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
117 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
119 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
122 let Constraints = "$src1 = $dst" in {
124 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
125 "shr{b}\t{%cl, $dst|$dst, CL}",
126 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
127 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
128 "shr{w}\t{%cl, $dst|$dst, CL}",
129 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
130 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
131 "shr{l}\t{%cl, $dst|$dst, CL}",
132 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
133 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
134 "shr{q}\t{%cl, $dst|$dst, CL}",
135 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
138 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
139 "shr{b}\t{$src2, $dst|$dst, $src2}",
140 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
141 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
142 "shr{w}\t{$src2, $dst|$dst, $src2}",
143 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
145 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
146 "shr{l}\t{$src2, $dst|$dst, $src2}",
147 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
149 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
150 "shr{q}\t{$src2, $dst|$dst, $src2}",
151 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
154 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
156 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
157 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
159 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
160 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
162 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>;
163 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
165 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
166 } // Constraints = "$src = $dst"
170 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
171 "shr{b}\t{%cl, $dst|$dst, CL}",
172 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
173 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
174 "shr{w}\t{%cl, $dst|$dst, CL}",
175 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
177 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
178 "shr{l}\t{%cl, $dst|$dst, CL}",
179 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
180 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
181 "shr{q}\t{%cl, $dst|$dst, CL}",
182 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
184 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
185 "shr{b}\t{$src, $dst|$dst, $src}",
186 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
188 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
189 "shr{w}\t{$src, $dst|$dst, $src}",
190 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
193 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
194 "shr{l}\t{$src, $dst|$dst, $src}",
195 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
197 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
198 "shr{q}\t{$src, $dst|$dst, $src}",
199 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
203 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
205 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
207 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
209 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
211 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
213 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
215 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
217 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
220 let Constraints = "$src1 = $dst" in {
222 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
223 "sar{b}\t{%cl, $dst|$dst, CL}",
224 [(set GR8:$dst, (sra GR8:$src1, CL))],
226 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
227 "sar{w}\t{%cl, $dst|$dst, CL}",
228 [(set GR16:$dst, (sra GR16:$src1, CL))],
230 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
231 "sar{l}\t{%cl, $dst|$dst, CL}",
232 [(set GR32:$dst, (sra GR32:$src1, CL))],
234 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
235 "sar{q}\t{%cl, $dst|$dst, CL}",
236 [(set GR64:$dst, (sra GR64:$src1, CL))],
240 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
241 "sar{b}\t{$src2, $dst|$dst, $src2}",
242 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
244 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
245 "sar{w}\t{$src2, $dst|$dst, $src2}",
246 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
249 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
250 "sar{l}\t{$src2, $dst|$dst, $src2}",
251 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
253 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
254 (ins GR64:$src1, i8imm:$src2),
255 "sar{q}\t{$src2, $dst|$dst, $src2}",
256 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
260 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
262 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
264 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
266 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
268 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
270 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
272 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
274 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
276 } // Constraints = "$src = $dst"
280 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
281 "sar{b}\t{%cl, $dst|$dst, CL}",
282 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
284 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
285 "sar{w}\t{%cl, $dst|$dst, CL}",
286 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
288 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
289 "sar{l}\t{%cl, $dst|$dst, CL}",
290 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
292 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
293 "sar{q}\t{%cl, $dst|$dst, CL}",
294 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
297 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
298 "sar{b}\t{$src, $dst|$dst, $src}",
299 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
301 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
302 "sar{w}\t{$src, $dst|$dst, $src}",
303 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
306 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
307 "sar{l}\t{$src, $dst|$dst, $src}",
308 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
310 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
311 "sar{q}\t{$src, $dst|$dst, $src}",
312 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
316 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
318 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
320 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
322 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
325 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
327 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
329 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
331 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
334 //===----------------------------------------------------------------------===//
335 // Rotate instructions
336 //===----------------------------------------------------------------------===//
338 let hasSideEffects = 0 in {
339 let Constraints = "$src1 = $dst" in {
340 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
341 "rcl{b}\t$dst", [], IIC_SR>;
342 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
343 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
345 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
346 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
348 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
349 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
350 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
351 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
353 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
354 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
356 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
357 "rcl{l}\t$dst", [], IIC_SR>;
358 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
359 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
361 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
362 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
365 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
366 "rcl{q}\t$dst", [], IIC_SR>;
367 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
368 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
370 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
371 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
374 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
375 "rcr{b}\t$dst", [], IIC_SR>;
376 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
377 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
379 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
380 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
382 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
383 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
384 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
385 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
387 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
388 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
390 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
391 "rcr{l}\t$dst", [], IIC_SR>;
392 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
393 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
395 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
396 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
398 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
399 "rcr{q}\t$dst", [], IIC_SR>;
400 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
401 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
403 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
404 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
406 } // Constraints = "$src = $dst"
408 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
409 "rcl{b}\t$dst", [], IIC_SR>;
410 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
411 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
412 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
413 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
414 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
415 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
416 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
417 "rcl{l}\t$dst", [], IIC_SR>;
418 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
419 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
420 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
421 "rcl{q}\t$dst", [], IIC_SR>;
422 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
423 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
425 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
426 "rcr{b}\t$dst", [], IIC_SR>;
427 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
428 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
429 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
430 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
431 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
432 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
433 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
434 "rcr{l}\t$dst", [], IIC_SR>;
435 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
436 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
437 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
438 "rcr{q}\t$dst", [], IIC_SR>;
439 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
440 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
443 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
444 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
445 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
446 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
447 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
448 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
449 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
450 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
452 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
453 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
454 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
455 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
456 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
457 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
458 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
459 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
461 } // hasSideEffects = 0
463 let Constraints = "$src1 = $dst" in {
464 // FIXME: provide shorter instructions when imm8 == 1
466 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
467 "rol{b}\t{%cl, $dst|$dst, CL}",
468 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
469 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
470 "rol{w}\t{%cl, $dst|$dst, CL}",
471 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
472 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
473 "rol{l}\t{%cl, $dst|$dst, CL}",
474 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
475 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
476 "rol{q}\t{%cl, $dst|$dst, CL}",
477 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
480 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
481 "rol{b}\t{$src2, $dst|$dst, $src2}",
482 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
483 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
484 "rol{w}\t{$src2, $dst|$dst, $src2}",
485 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
488 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
489 "rol{l}\t{$src2, $dst|$dst, $src2}",
490 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
492 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
493 (ins GR64:$src1, i8imm:$src2),
494 "rol{q}\t{$src2, $dst|$dst, $src2}",
495 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
499 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
501 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
503 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
505 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
507 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
509 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
511 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
513 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
515 } // Constraints = "$src = $dst"
518 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
519 "rol{b}\t{%cl, $dst|$dst, CL}",
520 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
522 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
523 "rol{w}\t{%cl, $dst|$dst, CL}",
524 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
526 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
527 "rol{l}\t{%cl, $dst|$dst, CL}",
528 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
530 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
531 "rol{q}\t{%cl, $dst|$dst, %cl}",
532 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
535 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
536 "rol{b}\t{$src1, $dst|$dst, $src1}",
537 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
539 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
540 "rol{w}\t{$src1, $dst|$dst, $src1}",
541 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
544 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
545 "rol{l}\t{$src1, $dst|$dst, $src1}",
546 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
548 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
549 "rol{q}\t{$src1, $dst|$dst, $src1}",
550 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
554 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
556 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
558 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
560 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
563 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
565 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
567 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
569 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
572 let Constraints = "$src1 = $dst" in {
574 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
575 "ror{b}\t{%cl, $dst|$dst, CL}",
576 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
577 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
578 "ror{w}\t{%cl, $dst|$dst, CL}",
579 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
580 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
581 "ror{l}\t{%cl, $dst|$dst, CL}",
582 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
583 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
584 "ror{q}\t{%cl, $dst|$dst, CL}",
585 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
588 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
589 "ror{b}\t{$src2, $dst|$dst, $src2}",
590 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
591 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
592 "ror{w}\t{$src2, $dst|$dst, $src2}",
593 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
596 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
597 "ror{l}\t{$src2, $dst|$dst, $src2}",
598 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
600 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
601 (ins GR64:$src1, i8imm:$src2),
602 "ror{q}\t{$src2, $dst|$dst, $src2}",
603 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
607 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
609 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
611 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
613 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
615 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
617 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
619 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
621 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
623 } // Constraints = "$src = $dst"
626 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
627 "ror{b}\t{%cl, $dst|$dst, CL}",
628 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
630 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
631 "ror{w}\t{%cl, $dst|$dst, CL}",
632 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
634 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
635 "ror{l}\t{%cl, $dst|$dst, CL}",
636 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
638 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
639 "ror{q}\t{%cl, $dst|$dst, CL}",
640 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
643 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
644 "ror{b}\t{$src, $dst|$dst, $src}",
645 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
647 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
648 "ror{w}\t{$src, $dst|$dst, $src}",
649 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
652 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
653 "ror{l}\t{$src, $dst|$dst, $src}",
654 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
656 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
657 "ror{q}\t{$src, $dst|$dst, $src}",
658 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
662 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
664 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
666 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
668 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
671 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
673 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
675 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
677 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
681 //===----------------------------------------------------------------------===//
682 // Double shift instructions (generalizations of rotate)
683 //===----------------------------------------------------------------------===//
685 let Constraints = "$src1 = $dst" in {
688 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
689 (ins GR16:$src1, GR16:$src2),
690 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
691 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
694 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
695 (ins GR16:$src1, GR16:$src2),
696 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
697 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
700 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
701 (ins GR32:$src1, GR32:$src2),
702 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
703 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
704 IIC_SHD32_REG_CL>, TB;
705 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
706 (ins GR32:$src1, GR32:$src2),
707 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
708 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
709 IIC_SHD32_REG_CL>, TB;
710 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
711 (ins GR64:$src1, GR64:$src2),
712 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
713 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
716 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
717 (ins GR64:$src1, GR64:$src2),
718 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
719 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
724 let isCommutable = 1 in { // These instructions commute to each other.
725 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
727 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
728 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
729 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
730 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
732 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
734 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
735 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
736 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
737 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
739 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
741 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
742 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
743 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
744 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
746 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
748 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
749 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
750 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
751 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
753 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
755 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
756 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
757 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
758 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
760 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
762 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
763 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
764 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
765 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
768 } // Constraints = "$src = $dst"
771 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
772 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
773 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
774 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
775 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
776 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
777 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
778 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
780 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
781 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
782 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
783 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
784 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
785 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
786 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
787 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
789 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
790 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
791 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
792 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
793 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
794 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
795 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
796 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
799 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
800 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
801 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
802 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
803 (i8 imm:$src3)), addr:$dst)],
806 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
807 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
808 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
809 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
810 (i8 imm:$src3)), addr:$dst)],
814 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
815 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
816 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
817 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
818 (i8 imm:$src3)), addr:$dst)],
821 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
822 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
823 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
824 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
825 (i8 imm:$src3)), addr:$dst)],
829 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
830 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
831 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
832 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
833 (i8 imm:$src3)), addr:$dst)],
836 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
837 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
838 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
839 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
840 (i8 imm:$src3)), addr:$dst)],
846 def ROT32L2R_imm8 : SDNodeXForm<imm, [{
847 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
848 return getI8Imm(32 - N->getZExtValue());
851 def ROT64L2R_imm8 : SDNodeXForm<imm, [{
852 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
853 return getI8Imm(64 - N->getZExtValue());
856 multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
857 let neverHasSideEffects = 1 in {
858 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
859 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
862 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
863 (ins x86memop:$src1, i8imm:$src2),
864 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
869 multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
870 let neverHasSideEffects = 1 in {
871 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
872 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
875 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
876 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
881 let Predicates = [HasBMI2] in {
882 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
883 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
884 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
885 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
886 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
887 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
888 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize;
889 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W;
891 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
892 let AddedComplexity = 10 in {
893 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
894 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
895 def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
896 (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
899 def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
900 (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
901 def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
902 (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
904 // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
905 // immedidate shift, i.e. the following code is considered better
914 // shlx %sil, %edi, %esi
917 let AddedComplexity = 1 in {
918 def : Pat<(sra GR32:$src1, GR8:$src2),
919 (SARX32rr GR32:$src1,
921 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
922 def : Pat<(sra GR64:$src1, GR8:$src2),
923 (SARX64rr GR64:$src1,
925 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
927 def : Pat<(srl GR32:$src1, GR8:$src2),
928 (SHRX32rr GR32:$src1,
930 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
931 def : Pat<(srl GR64:$src1, GR8:$src2),
932 (SHRX64rr GR64:$src1,
934 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
936 def : Pat<(shl GR32:$src1, GR8:$src2),
937 (SHLX32rr GR32:$src1,
939 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
940 def : Pat<(shl GR64:$src1, GR8:$src2),
941 (SHLX64rr GR64:$src1,
943 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
946 // Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor
954 // shlx %al, (%ecx), %esi
956 // As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
957 // optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.