1 //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the shift and rotate instructions.
12 //===----------------------------------------------------------------------===//
14 // FIXME: Someone needs to smear multipattern goodness all over this file.
16 let Defs = [EFLAGS] in {
18 let Constraints = "$src1 = $dst" in {
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, CL}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, CL}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, CL}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>;
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 "shl{q}\t{%cl, $dst|$dst, CL}",
31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
38 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>;
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
47 (ins GR64:$src1, i8imm:$src2),
48 "shl{q}\t{$src2, $dst|$dst, $src2}",
49 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
52 // NOTE: We don't include patterns for shifts of a register by one, because
53 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
54 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
55 "shl{b}\t$dst", [], IIC_SR>;
56 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
57 "shl{w}\t$dst", [], IIC_SR>, OpSize;
58 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
59 "shl{l}\t$dst", [], IIC_SR>;
60 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
61 "shl{q}\t$dst", [], IIC_SR>;
62 } // isConvertibleToThreeAddress = 1
63 } // Constraints = "$src = $dst"
66 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
69 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
70 "shl{b}\t{%cl, $dst|$dst, CL}",
71 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
72 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
73 "shl{w}\t{%cl, $dst|$dst, CL}",
74 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
76 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
77 "shl{l}\t{%cl, $dst|$dst, CL}",
78 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
79 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
80 "shl{q}\t{%cl, $dst|$dst, CL}",
81 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
83 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
84 "shl{b}\t{$src, $dst|$dst, $src}",
85 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
87 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
88 "shl{w}\t{$src, $dst|$dst, $src}",
89 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
92 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
93 "shl{l}\t{$src, $dst|$dst, $src}",
94 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
96 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
97 "shl{q}\t{$src, $dst|$dst, $src}",
98 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
102 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
104 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
106 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
108 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
111 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
113 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
115 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
117 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
120 let Constraints = "$src1 = $dst" in {
122 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
123 "shr{b}\t{%cl, $dst|$dst, CL}",
124 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
125 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
126 "shr{w}\t{%cl, $dst|$dst, CL}",
127 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
128 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
129 "shr{l}\t{%cl, $dst|$dst, CL}",
130 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>;
131 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
132 "shr{q}\t{%cl, $dst|$dst, CL}",
133 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
136 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
137 "shr{b}\t{$src2, $dst|$dst, $src2}",
138 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
139 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
140 "shr{w}\t{$src2, $dst|$dst, $src2}",
141 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
143 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
144 "shr{l}\t{$src2, $dst|$dst, $src2}",
145 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
147 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
148 "shr{q}\t{$src2, $dst|$dst, $src2}",
149 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
152 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
154 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
155 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
157 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
158 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
160 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>;
161 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
163 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
164 } // Constraints = "$src = $dst"
168 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
169 "shr{b}\t{%cl, $dst|$dst, CL}",
170 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
171 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
172 "shr{w}\t{%cl, $dst|$dst, CL}",
173 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
175 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
176 "shr{l}\t{%cl, $dst|$dst, CL}",
177 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>;
178 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
179 "shr{q}\t{%cl, $dst|$dst, CL}",
180 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
182 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
183 "shr{b}\t{$src, $dst|$dst, $src}",
184 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
186 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
187 "shr{w}\t{$src, $dst|$dst, $src}",
188 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
191 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
192 "shr{l}\t{$src, $dst|$dst, $src}",
193 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
195 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
196 "shr{q}\t{$src, $dst|$dst, $src}",
197 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
201 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
203 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
205 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
207 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
209 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
211 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
213 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
215 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
218 let Constraints = "$src1 = $dst" in {
220 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
221 "sar{b}\t{%cl, $dst|$dst, CL}",
222 [(set GR8:$dst, (sra GR8:$src1, CL))],
224 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
225 "sar{w}\t{%cl, $dst|$dst, CL}",
226 [(set GR16:$dst, (sra GR16:$src1, CL))],
228 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
229 "sar{l}\t{%cl, $dst|$dst, CL}",
230 [(set GR32:$dst, (sra GR32:$src1, CL))],
232 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
233 "sar{q}\t{%cl, $dst|$dst, CL}",
234 [(set GR64:$dst, (sra GR64:$src1, CL))],
238 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
239 "sar{b}\t{$src2, $dst|$dst, $src2}",
240 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
242 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
243 "sar{w}\t{$src2, $dst|$dst, $src2}",
244 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
247 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
248 "sar{l}\t{$src2, $dst|$dst, $src2}",
249 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
251 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
252 (ins GR64:$src1, i8imm:$src2),
253 "sar{q}\t{$src2, $dst|$dst, $src2}",
254 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
258 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
260 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
262 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
264 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
266 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
268 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
270 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
272 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
274 } // Constraints = "$src = $dst"
278 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
279 "sar{b}\t{%cl, $dst|$dst, CL}",
280 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
282 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
283 "sar{w}\t{%cl, $dst|$dst, CL}",
284 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
286 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
287 "sar{l}\t{%cl, $dst|$dst, CL}",
288 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
290 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
291 "sar{q}\t{%cl, $dst|$dst, CL}",
292 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
295 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
296 "sar{b}\t{$src, $dst|$dst, $src}",
297 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
299 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
300 "sar{w}\t{$src, $dst|$dst, $src}",
301 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
304 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
305 "sar{l}\t{$src, $dst|$dst, $src}",
306 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
308 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
309 "sar{q}\t{$src, $dst|$dst, $src}",
310 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
314 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
316 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
318 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
320 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
323 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
325 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
327 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
329 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
332 //===----------------------------------------------------------------------===//
333 // Rotate instructions
334 //===----------------------------------------------------------------------===//
336 let Constraints = "$src1 = $dst" in {
337 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
338 "rcl{b}\t$dst", [], IIC_SR>;
339 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
340 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
342 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
343 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
345 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
346 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
347 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
348 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
350 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
351 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
353 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
354 "rcl{l}\t$dst", [], IIC_SR>;
355 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
356 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
358 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
359 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
362 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
363 "rcl{q}\t$dst", [], IIC_SR>;
364 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
365 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
367 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
368 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
371 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
372 "rcr{b}\t$dst", [], IIC_SR>;
373 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
374 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
376 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
377 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
379 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
380 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
381 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
382 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
384 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
385 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
387 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
388 "rcr{l}\t$dst", [], IIC_SR>;
389 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
390 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
392 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
393 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
395 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
396 "rcr{q}\t$dst", [], IIC_SR>;
397 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
398 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
400 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
401 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
403 } // Constraints = "$src = $dst"
405 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
406 "rcl{b}\t$dst", [], IIC_SR>;
407 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
408 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
409 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
410 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
411 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
412 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
413 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
414 "rcl{l}\t$dst", [], IIC_SR>;
415 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
416 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
417 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
418 "rcl{q}\t$dst", [], IIC_SR>;
419 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
420 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
422 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
423 "rcr{b}\t$dst", [], IIC_SR>;
424 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
425 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
426 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
427 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
428 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
429 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
430 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
431 "rcr{l}\t$dst", [], IIC_SR>;
432 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
433 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
434 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
435 "rcr{q}\t$dst", [], IIC_SR>;
436 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
437 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
440 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
441 "rcl{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
442 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
443 "rcl{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
444 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
445 "rcl{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
446 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
447 "rcl{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
449 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
450 "rcr{b}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
451 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
452 "rcr{w}\t{%cl, $dst|$dst, CL}", [], IIC_SR>, OpSize;
453 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
454 "rcr{l}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
455 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
456 "rcr{q}\t{%cl, $dst|$dst, CL}", [], IIC_SR>;
459 let Constraints = "$src1 = $dst" in {
460 // FIXME: provide shorter instructions when imm8 == 1
462 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
463 "rol{b}\t{%cl, $dst|$dst, CL}",
464 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
465 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
466 "rol{w}\t{%cl, $dst|$dst, CL}",
467 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
468 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
469 "rol{l}\t{%cl, $dst|$dst, CL}",
470 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>;
471 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
472 "rol{q}\t{%cl, $dst|$dst, CL}",
473 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
476 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
477 "rol{b}\t{$src2, $dst|$dst, $src2}",
478 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
479 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
480 "rol{w}\t{$src2, $dst|$dst, $src2}",
481 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
484 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
485 "rol{l}\t{$src2, $dst|$dst, $src2}",
486 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
488 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
489 (ins GR64:$src1, i8imm:$src2),
490 "rol{q}\t{$src2, $dst|$dst, $src2}",
491 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
495 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
497 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
499 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
501 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
503 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
505 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
507 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
509 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
511 } // Constraints = "$src = $dst"
514 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
515 "rol{b}\t{%cl, $dst|$dst, CL}",
516 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
518 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
519 "rol{w}\t{%cl, $dst|$dst, CL}",
520 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
522 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
523 "rol{l}\t{%cl, $dst|$dst, CL}",
524 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
526 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
527 "rol{q}\t{%cl, $dst|$dst, %cl}",
528 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
531 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
532 "rol{b}\t{$src1, $dst|$dst, $src1}",
533 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
535 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
536 "rol{w}\t{$src1, $dst|$dst, $src1}",
537 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
540 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
541 "rol{l}\t{$src1, $dst|$dst, $src1}",
542 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
544 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
545 "rol{q}\t{$src1, $dst|$dst, $src1}",
546 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
550 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
552 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
554 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
556 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
559 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
561 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
563 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
565 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
568 let Constraints = "$src1 = $dst" in {
570 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
571 "ror{b}\t{%cl, $dst|$dst, CL}",
572 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
573 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
574 "ror{w}\t{%cl, $dst|$dst, CL}",
575 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
576 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
577 "ror{l}\t{%cl, $dst|$dst, CL}",
578 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>;
579 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
580 "ror{q}\t{%cl, $dst|$dst, CL}",
581 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
584 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
585 "ror{b}\t{$src2, $dst|$dst, $src2}",
586 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
587 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
588 "ror{w}\t{$src2, $dst|$dst, $src2}",
589 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
592 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
593 "ror{l}\t{$src2, $dst|$dst, $src2}",
594 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
596 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
597 (ins GR64:$src1, i8imm:$src2),
598 "ror{q}\t{$src2, $dst|$dst, $src2}",
599 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
603 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
605 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
607 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
609 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
611 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
613 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
615 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
617 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
619 } // Constraints = "$src = $dst"
622 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
623 "ror{b}\t{%cl, $dst|$dst, CL}",
624 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
626 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
627 "ror{w}\t{%cl, $dst|$dst, CL}",
628 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
630 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
631 "ror{l}\t{%cl, $dst|$dst, CL}",
632 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
634 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
635 "ror{q}\t{%cl, $dst|$dst, CL}",
636 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
639 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
640 "ror{b}\t{$src, $dst|$dst, $src}",
641 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
643 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
644 "ror{w}\t{$src, $dst|$dst, $src}",
645 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
648 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
649 "ror{l}\t{$src, $dst|$dst, $src}",
650 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
652 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
653 "ror{q}\t{$src, $dst|$dst, $src}",
654 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
658 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
660 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
662 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
664 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
667 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
669 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
671 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
673 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
677 //===----------------------------------------------------------------------===//
678 // Double shift instructions (generalizations of rotate)
679 //===----------------------------------------------------------------------===//
681 let Constraints = "$src1 = $dst" in {
684 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
685 (ins GR16:$src1, GR16:$src2),
686 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
687 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
690 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
691 (ins GR16:$src1, GR16:$src2),
692 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
693 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
696 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
697 (ins GR32:$src1, GR32:$src2),
698 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
699 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
700 IIC_SHD32_REG_CL>, TB;
701 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
702 (ins GR32:$src1, GR32:$src2),
703 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
704 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
705 IIC_SHD32_REG_CL>, TB;
706 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
707 (ins GR64:$src1, GR64:$src2),
708 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
709 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
712 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
713 (ins GR64:$src1, GR64:$src2),
714 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
715 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
720 let isCommutable = 1 in { // These instructions commute to each other.
721 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
723 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
724 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
725 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
726 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
728 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
730 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
731 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
732 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
733 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
735 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
737 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
738 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
739 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
740 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
742 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
744 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
745 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
746 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
747 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
749 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
751 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
752 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
753 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
754 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
756 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
758 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
759 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
760 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
761 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
764 } // Constraints = "$src = $dst"
767 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
768 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
769 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
770 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
771 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
772 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
773 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
774 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
776 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
777 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
778 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
779 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
780 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
781 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
782 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
783 addr:$dst)], IIC_SHD32_MEM_CL>, TB;
785 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
786 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
787 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
788 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
789 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
790 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, CL}",
791 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
792 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
795 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
796 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
797 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
798 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
799 (i8 imm:$src3)), addr:$dst)],
802 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
803 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
804 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
805 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
806 (i8 imm:$src3)), addr:$dst)],
810 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
811 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
812 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
813 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
814 (i8 imm:$src3)), addr:$dst)],
817 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
818 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
819 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
820 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
821 (i8 imm:$src3)), addr:$dst)],
825 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
826 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
827 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
828 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
829 (i8 imm:$src3)), addr:$dst)],
832 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
833 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
834 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
835 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
836 (i8 imm:$src3)), addr:$dst)],
842 multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
843 let neverHasSideEffects = 1 in {
844 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
845 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
848 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
849 (ins x86memop:$src1, i8imm:$src2),
850 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
855 multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
856 let neverHasSideEffects = 1 in {
857 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
858 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
861 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
862 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
867 let Predicates = [HasBMI2] in {
868 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
869 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
870 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
871 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
872 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
873 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
874 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8, OpSize;
875 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8, OpSize, VEX_W;