1 //===-- X86InstrShiftRotate.td - Shift and Rotate Instrs ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the shift and rotate instructions.
12 //===----------------------------------------------------------------------===//
14 // FIXME: Someone needs to smear multipattern goodness all over this file.
16 let Defs = [EFLAGS] in {
18 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
21 "shl{b}\t{%cl, $dst|$dst, cl}",
22 [(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
24 "shl{w}\t{%cl, $dst|$dst, cl}",
25 [(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
27 "shl{l}\t{%cl, $dst|$dst, cl}",
28 [(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize16;
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
30 "shl{q}\t{%cl, $dst|$dst, cl}",
31 [(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
35 "shl{b}\t{$src2, $dst|$dst, $src2}",
36 [(set GR8:$dst, (shl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
38 let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
40 "shl{w}\t{$src2, $dst|$dst, $src2}",
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
44 "shl{l}\t{$src2, $dst|$dst, $src2}",
45 [(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
47 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
48 (ins GR64:$src1, i8imm:$src2),
49 "shl{q}\t{$src2, $dst|$dst, $src2}",
50 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))],
53 // NOTE: We don't include patterns for shifts of a register by one, because
54 // 'add reg,reg' is cheaper (and we have a Pat pattern for shift-by-one).
55 let hasSideEffects = 0 in {
56 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 "shl{b}\t$dst", [], IIC_SR>;
58 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
59 "shl{w}\t$dst", [], IIC_SR>, OpSize;
60 def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
61 "shl{l}\t$dst", [], IIC_SR>, OpSize16;
62 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
63 "shl{q}\t$dst", [], IIC_SR>;
64 } // hasSideEffects = 0
65 } // isConvertibleToThreeAddress = 1
66 } // Constraints = "$src = $dst", SchedRW
69 let SchedRW = [WriteShiftLd, WriteRMW] in {
70 // FIXME: Why do we need an explicit "Uses = [CL]" when the instr has a pattern
73 def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
74 "shl{b}\t{%cl, $dst|$dst, cl}",
75 [(store (shl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
76 def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
77 "shl{w}\t{%cl, $dst|$dst, cl}",
78 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
80 def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
81 "shl{l}\t{%cl, $dst|$dst, cl}",
82 [(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
84 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
85 "shl{q}\t{%cl, $dst|$dst, cl}",
86 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
88 def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
89 "shl{b}\t{$src, $dst|$dst, $src}",
90 [(store (shl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
92 def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
93 "shl{w}\t{$src, $dst|$dst, $src}",
94 [(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
97 def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
98 "shl{l}\t{$src, $dst|$dst, $src}",
99 [(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
101 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
102 "shl{q}\t{$src, $dst|$dst, $src}",
103 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
107 def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
109 [(store (shl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
111 def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
113 [(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
116 def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
118 [(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
120 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
122 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
126 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
128 def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
129 "shr{b}\t{%cl, $dst|$dst, cl}",
130 [(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
131 def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
132 "shr{w}\t{%cl, $dst|$dst, cl}",
133 [(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
134 def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
135 "shr{l}\t{%cl, $dst|$dst, cl}",
136 [(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize16;
137 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
138 "shr{q}\t{%cl, $dst|$dst, cl}",
139 [(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
142 def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
143 "shr{b}\t{$src2, $dst|$dst, $src2}",
144 [(set GR8:$dst, (srl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
145 def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
146 "shr{w}\t{$src2, $dst|$dst, $src2}",
147 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
149 def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
150 "shr{l}\t{$src2, $dst|$dst, $src2}",
151 [(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
153 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
154 "shr{q}\t{$src2, $dst|$dst, $src2}",
155 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
158 def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
160 [(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
161 def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
163 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
164 def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
166 [(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize16;
167 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
169 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
170 } // Constraints = "$src = $dst", SchedRW
173 let SchedRW = [WriteShiftLd, WriteRMW] in {
175 def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
176 "shr{b}\t{%cl, $dst|$dst, cl}",
177 [(store (srl (loadi8 addr:$dst), CL), addr:$dst)], IIC_SR>;
178 def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
179 "shr{w}\t{%cl, $dst|$dst, cl}",
180 [(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
182 def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
183 "shr{l}\t{%cl, $dst|$dst, cl}",
184 [(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
186 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
187 "shr{q}\t{%cl, $dst|$dst, cl}",
188 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
190 def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
191 "shr{b}\t{$src, $dst|$dst, $src}",
192 [(store (srl (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
194 def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
195 "shr{w}\t{$src, $dst|$dst, $src}",
196 [(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
199 def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
200 "shr{l}\t{$src, $dst|$dst, $src}",
201 [(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
203 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
204 "shr{q}\t{$src, $dst|$dst, $src}",
205 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
209 def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
211 [(store (srl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
213 def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
215 [(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
217 def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
219 [(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
221 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
223 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
227 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
229 def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
230 "sar{b}\t{%cl, $dst|$dst, cl}",
231 [(set GR8:$dst, (sra GR8:$src1, CL))],
233 def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
234 "sar{w}\t{%cl, $dst|$dst, cl}",
235 [(set GR16:$dst, (sra GR16:$src1, CL))],
237 def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
238 "sar{l}\t{%cl, $dst|$dst, cl}",
239 [(set GR32:$dst, (sra GR32:$src1, CL))],
241 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
242 "sar{q}\t{%cl, $dst|$dst, cl}",
243 [(set GR64:$dst, (sra GR64:$src1, CL))],
247 def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
248 "sar{b}\t{$src2, $dst|$dst, $src2}",
249 [(set GR8:$dst, (sra GR8:$src1, (i8 imm:$src2)))],
251 def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
252 "sar{w}\t{$src2, $dst|$dst, $src2}",
253 [(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
256 def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
257 "sar{l}\t{$src2, $dst|$dst, $src2}",
258 [(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
260 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
261 (ins GR64:$src1, i8imm:$src2),
262 "sar{q}\t{$src2, $dst|$dst, $src2}",
263 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))],
267 def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
269 [(set GR8:$dst, (sra GR8:$src1, (i8 1)))],
271 def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
273 [(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
275 def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
277 [(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
279 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
281 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
283 } // Constraints = "$src = $dst", SchedRW
286 let SchedRW = [WriteShiftLd, WriteRMW] in {
288 def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
289 "sar{b}\t{%cl, $dst|$dst, cl}",
290 [(store (sra (loadi8 addr:$dst), CL), addr:$dst)],
292 def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
293 "sar{w}\t{%cl, $dst|$dst, cl}",
294 [(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
296 def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
297 "sar{l}\t{%cl, $dst|$dst, cl}",
298 [(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
300 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
301 "sar{q}\t{%cl, $dst|$dst, cl}",
302 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
305 def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
306 "sar{b}\t{$src, $dst|$dst, $src}",
307 [(store (sra (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
309 def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
310 "sar{w}\t{$src, $dst|$dst, $src}",
311 [(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
314 def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
315 "sar{l}\t{$src, $dst|$dst, $src}",
316 [(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
318 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
319 "sar{q}\t{$src, $dst|$dst, $src}",
320 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
324 def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
326 [(store (sra (loadi8 addr:$dst), (i8 1)), addr:$dst)],
328 def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
330 [(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
333 def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
335 [(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
337 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
339 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
343 //===----------------------------------------------------------------------===//
344 // Rotate instructions
345 //===----------------------------------------------------------------------===//
347 let hasSideEffects = 0 in {
348 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
349 def RCL8r1 : I<0xD0, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
350 "rcl{b}\t$dst", [], IIC_SR>;
351 def RCL8ri : Ii8<0xC0, MRM2r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
352 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
354 def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
355 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
357 def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
358 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
359 def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
360 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
362 def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
363 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
365 def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
366 "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
367 def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
368 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
370 def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
371 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
374 def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
375 "rcl{q}\t$dst", [], IIC_SR>;
376 def RCL64ri : RIi8<0xC1, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
377 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
379 def RCL64rCL : RI<0xD3, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
380 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
383 def RCR8r1 : I<0xD0, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
384 "rcr{b}\t$dst", [], IIC_SR>;
385 def RCR8ri : Ii8<0xC0, MRM3r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$cnt),
386 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
388 def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
389 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
391 def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
392 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
393 def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
394 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
396 def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
397 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
399 def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
400 "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
401 def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
402 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
404 def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
405 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
407 def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
408 "rcr{q}\t$dst", [], IIC_SR>;
409 def RCR64ri : RIi8<0xC1, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$cnt),
410 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
412 def RCR64rCL : RI<0xD3, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
413 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
415 } // Constraints = "$src = $dst"
417 let SchedRW = [WriteShiftLd, WriteRMW] in {
418 def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
419 "rcl{b}\t$dst", [], IIC_SR>;
420 def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
421 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
422 def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
423 "rcl{w}\t$dst", [], IIC_SR>, OpSize;
424 def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
425 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
426 def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
427 "rcl{l}\t$dst", [], IIC_SR>, OpSize16;
428 def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
429 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
430 def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
431 "rcl{q}\t$dst", [], IIC_SR>;
432 def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
433 "rcl{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
435 def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
436 "rcr{b}\t$dst", [], IIC_SR>;
437 def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
438 "rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
439 def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
440 "rcr{w}\t$dst", [], IIC_SR>, OpSize;
441 def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
442 "rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
443 def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
444 "rcr{l}\t$dst", [], IIC_SR>, OpSize16;
445 def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
446 "rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
447 def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
448 "rcr{q}\t$dst", [], IIC_SR>;
449 def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
450 "rcr{q}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
453 def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
454 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
455 def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
456 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
457 def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
458 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
459 def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
460 "rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
462 def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
463 "rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
464 def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
465 "rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
466 def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
467 "rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
468 def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
469 "rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
472 } // hasSideEffects = 0
474 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
475 // FIXME: provide shorter instructions when imm8 == 1
477 def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
478 "rol{b}\t{%cl, $dst|$dst, cl}",
479 [(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
480 def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
481 "rol{w}\t{%cl, $dst|$dst, cl}",
482 [(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
483 def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
484 "rol{l}\t{%cl, $dst|$dst, cl}",
485 [(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize16;
486 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
487 "rol{q}\t{%cl, $dst|$dst, cl}",
488 [(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
491 def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
492 "rol{b}\t{$src2, $dst|$dst, $src2}",
493 [(set GR8:$dst, (rotl GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
494 def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
495 "rol{w}\t{$src2, $dst|$dst, $src2}",
496 [(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
499 def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
500 "rol{l}\t{$src2, $dst|$dst, $src2}",
501 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
503 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
504 (ins GR64:$src1, i8imm:$src2),
505 "rol{q}\t{$src2, $dst|$dst, $src2}",
506 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))],
510 def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
512 [(set GR8:$dst, (rotl GR8:$src1, (i8 1)))],
514 def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
516 [(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
518 def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
520 [(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
522 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
524 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
526 } // Constraints = "$src = $dst", SchedRW
528 let SchedRW = [WriteShiftLd, WriteRMW] in {
530 def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
531 "rol{b}\t{%cl, $dst|$dst, cl}",
532 [(store (rotl (loadi8 addr:$dst), CL), addr:$dst)],
534 def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
535 "rol{w}\t{%cl, $dst|$dst, cl}",
536 [(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
538 def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
539 "rol{l}\t{%cl, $dst|$dst, cl}",
540 [(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
542 def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
543 "rol{q}\t{%cl, $dst|$dst, cl}",
544 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
547 def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
548 "rol{b}\t{$src1, $dst|$dst, $src1}",
549 [(store (rotl (loadi8 addr:$dst), (i8 imm:$src1)), addr:$dst)],
551 def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
552 "rol{w}\t{$src1, $dst|$dst, $src1}",
553 [(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
556 def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
557 "rol{l}\t{$src1, $dst|$dst, $src1}",
558 [(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
560 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
561 "rol{q}\t{$src1, $dst|$dst, $src1}",
562 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
566 def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
568 [(store (rotl (loadi8 addr:$dst), (i8 1)), addr:$dst)],
570 def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
572 [(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
575 def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
577 [(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
579 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
581 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
585 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
587 def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
588 "ror{b}\t{%cl, $dst|$dst, cl}",
589 [(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
590 def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
591 "ror{w}\t{%cl, $dst|$dst, cl}",
592 [(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
593 def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
594 "ror{l}\t{%cl, $dst|$dst, cl}",
595 [(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize16;
596 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
597 "ror{q}\t{%cl, $dst|$dst, cl}",
598 [(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
601 def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
602 "ror{b}\t{$src2, $dst|$dst, $src2}",
603 [(set GR8:$dst, (rotr GR8:$src1, (i8 imm:$src2)))], IIC_SR>;
604 def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
605 "ror{w}\t{$src2, $dst|$dst, $src2}",
606 [(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
609 def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
610 "ror{l}\t{$src2, $dst|$dst, $src2}",
611 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
613 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
614 (ins GR64:$src1, i8imm:$src2),
615 "ror{q}\t{$src2, $dst|$dst, $src2}",
616 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))],
620 def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
622 [(set GR8:$dst, (rotr GR8:$src1, (i8 1)))],
624 def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
626 [(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
628 def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
630 [(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
632 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
634 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
636 } // Constraints = "$src = $dst", SchedRW
638 let SchedRW = [WriteShiftLd, WriteRMW] in {
640 def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
641 "ror{b}\t{%cl, $dst|$dst, cl}",
642 [(store (rotr (loadi8 addr:$dst), CL), addr:$dst)],
644 def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
645 "ror{w}\t{%cl, $dst|$dst, cl}",
646 [(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
648 def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
649 "ror{l}\t{%cl, $dst|$dst, cl}",
650 [(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
652 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
653 "ror{q}\t{%cl, $dst|$dst, cl}",
654 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
657 def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
658 "ror{b}\t{$src, $dst|$dst, $src}",
659 [(store (rotr (loadi8 addr:$dst), (i8 imm:$src)), addr:$dst)],
661 def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
662 "ror{w}\t{$src, $dst|$dst, $src}",
663 [(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
666 def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
667 "ror{l}\t{$src, $dst|$dst, $src}",
668 [(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
670 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
671 "ror{q}\t{$src, $dst|$dst, $src}",
672 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
676 def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
678 [(store (rotr (loadi8 addr:$dst), (i8 1)), addr:$dst)],
680 def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
682 [(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
685 def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
687 [(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
689 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
691 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
696 //===----------------------------------------------------------------------===//
697 // Double shift instructions (generalizations of rotate)
698 //===----------------------------------------------------------------------===//
700 let Constraints = "$src1 = $dst", SchedRW = [WriteShift] in {
703 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
704 (ins GR16:$src1, GR16:$src2),
705 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
706 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
709 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
710 (ins GR16:$src1, GR16:$src2),
711 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
712 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
715 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
716 (ins GR32:$src1, GR32:$src2),
717 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
718 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
719 IIC_SHD32_REG_CL>, TB, OpSize16;
720 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
721 (ins GR32:$src1, GR32:$src2),
722 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
723 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
724 IIC_SHD32_REG_CL>, TB, OpSize16;
725 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
726 (ins GR64:$src1, GR64:$src2),
727 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
728 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))],
731 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
732 (ins GR64:$src1, GR64:$src2),
733 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
734 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))],
739 let isCommutable = 1 in { // These instructions commute to each other.
740 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
742 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
743 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
744 [(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
745 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
747 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
749 (ins GR16:$src1, GR16:$src2, i8imm:$src3),
750 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
751 [(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
752 (i8 imm:$src3)))], IIC_SHD16_REG_IM>,
754 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
756 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
757 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
758 [(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
759 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
761 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
763 (ins GR32:$src1, GR32:$src2, i8imm:$src3),
764 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
765 [(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
766 (i8 imm:$src3)))], IIC_SHD32_REG_IM>,
768 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
770 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
771 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
772 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
773 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
775 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
777 (ins GR64:$src1, GR64:$src2, i8imm:$src3),
778 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
779 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
780 (i8 imm:$src3)))], IIC_SHD64_REG_IM>,
783 } // Constraints = "$src = $dst", SchedRW
785 let SchedRW = [WriteShiftLd, WriteRMW] in {
787 def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
788 "shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
789 [(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
790 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
791 def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
792 "shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
793 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
794 addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
796 def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
797 "shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
798 [(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
799 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
800 def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
801 "shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
802 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
803 addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
805 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
806 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
807 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
808 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
809 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
810 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
811 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
812 addr:$dst)], IIC_SHD64_MEM_CL>, TB;
815 def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
816 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
817 "shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
818 [(store (X86shld (loadi16 addr:$dst), GR16:$src2,
819 (i8 imm:$src3)), addr:$dst)],
822 def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
823 (outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
824 "shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
825 [(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
826 (i8 imm:$src3)), addr:$dst)],
830 def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
831 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
832 "shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
833 [(store (X86shld (loadi32 addr:$dst), GR32:$src2,
834 (i8 imm:$src3)), addr:$dst)],
837 def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
838 (outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
839 "shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
840 [(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
841 (i8 imm:$src3)), addr:$dst)],
845 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
846 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
847 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
848 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
849 (i8 imm:$src3)), addr:$dst)],
852 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
853 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
854 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
855 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
856 (i8 imm:$src3)), addr:$dst)],
863 def ROT32L2R_imm8 : SDNodeXForm<imm, [{
864 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
865 return getI8Imm(32 - N->getZExtValue());
868 def ROT64L2R_imm8 : SDNodeXForm<imm, [{
869 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
870 return getI8Imm(64 - N->getZExtValue());
873 multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {
874 let neverHasSideEffects = 1 in {
875 def ri : Ii8<0xF0, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, i8imm:$src2),
876 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
877 []>, TAXD, VEX, Sched<[WriteShift]>;
879 def mi : Ii8<0xF0, MRMSrcMem, (outs RC:$dst),
880 (ins x86memop:$src1, i8imm:$src2),
881 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
882 []>, TAXD, VEX, Sched<[WriteShiftLd]>;
886 multiclass bmi_shift<string asm, RegisterClass RC, X86MemOperand x86memop> {
887 let neverHasSideEffects = 1 in {
888 def rr : I<0xF7, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
889 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
890 VEX_4VOp3, Sched<[WriteShift]>;
892 def rm : I<0xF7, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src1, RC:$src2),
893 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
897 ReadDefault, ReadDefault, ReadDefault, ReadDefault,
904 let Predicates = [HasBMI2] in {
905 defm RORX32 : bmi_rotate<"rorx{l}", GR32, i32mem>;
906 defm RORX64 : bmi_rotate<"rorx{q}", GR64, i64mem>, VEX_W;
907 defm SARX32 : bmi_shift<"sarx{l}", GR32, i32mem>, T8XS;
908 defm SARX64 : bmi_shift<"sarx{q}", GR64, i64mem>, T8XS, VEX_W;
909 defm SHRX32 : bmi_shift<"shrx{l}", GR32, i32mem>, T8XD;
910 defm SHRX64 : bmi_shift<"shrx{q}", GR64, i64mem>, T8XD, VEX_W;
911 defm SHLX32 : bmi_shift<"shlx{l}", GR32, i32mem>, T8PD;
912 defm SHLX64 : bmi_shift<"shlx{q}", GR64, i64mem>, T8PD, VEX_W;
914 // Prefer RORX which is non-destructive and doesn't update EFLAGS.
915 let AddedComplexity = 10 in {
916 def : Pat<(rotl GR32:$src, (i8 imm:$shamt)),
917 (RORX32ri GR32:$src, (ROT32L2R_imm8 imm:$shamt))>;
918 def : Pat<(rotl GR64:$src, (i8 imm:$shamt)),
919 (RORX64ri GR64:$src, (ROT64L2R_imm8 imm:$shamt))>;
922 def : Pat<(rotl (loadi32 addr:$src), (i8 imm:$shamt)),
923 (RORX32mi addr:$src, (ROT32L2R_imm8 imm:$shamt))>;
924 def : Pat<(rotl (loadi64 addr:$src), (i8 imm:$shamt)),
925 (RORX64mi addr:$src, (ROT64L2R_imm8 imm:$shamt))>;
927 // Prefer SARX/SHRX/SHLX over SAR/SHR/SHL with variable shift BUT not
928 // immedidate shift, i.e. the following code is considered better
937 // shlx %sil, %edi, %esi
940 let AddedComplexity = 1 in {
941 def : Pat<(sra GR32:$src1, GR8:$src2),
942 (SARX32rr GR32:$src1,
944 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
945 def : Pat<(sra GR64:$src1, GR8:$src2),
946 (SARX64rr GR64:$src1,
948 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
950 def : Pat<(srl GR32:$src1, GR8:$src2),
951 (SHRX32rr GR32:$src1,
953 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
954 def : Pat<(srl GR64:$src1, GR8:$src2),
955 (SHRX64rr GR64:$src1,
957 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
959 def : Pat<(shl GR32:$src1, GR8:$src2),
960 (SHLX32rr GR32:$src1,
962 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
963 def : Pat<(shl GR64:$src1, GR8:$src2),
964 (SHLX64rr GR64:$src1,
966 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
969 // Patterns on SARXrm/SHRXrm/SHLXrm are explicitly omitted to favor
977 // shlx %al, (%ecx), %esi
979 // As SARXrr/SHRXrr/SHLXrr is favored on variable shift, the peephole
980 // optimization will fold them into SARXrm/SHRXrm/SHLXrm if possible.