1 //===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let Defs = [RAX, RDX] in
17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
19 let Defs = [RAX, RCX, RDX] in
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
22 // CPU flow control instructions
24 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
32 // Interrupt and SysCall Instructions.
33 let Uses = [EFLAGS] in
34 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
35 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
36 [(int_x86_int (i8 3))]>;
38 // The long form of "int $3" turns into int3 as a size optimization.
39 // FIXME: This doesn't work because InstAlias can't match immediate constants.
40 //def : InstAlias<"int\t$3", (INT3)>;
43 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
44 [(int_x86_int imm:$trap)]>;
47 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
48 def SYSRETL : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
49 def SYSRETQ :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
50 Requires<[In64BitMode]>;
52 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
54 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexitl", []>, TB;
55 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexitq", []>, TB,
56 Requires<[In64BitMode]>;
58 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
59 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
60 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
61 Requires<[In64BitMode]>;
64 //===----------------------------------------------------------------------===//
65 // Input/Output Instructions.
67 let Defs = [AL], Uses = [DX] in
68 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
69 "in{b}\t{%dx, %al|AL, DX}", []>;
70 let Defs = [AX], Uses = [DX] in
71 def IN16rr : I<0xED, RawFrm, (outs), (ins),
72 "in{w}\t{%dx, %ax|AX, DX}", []>, OpSize;
73 let Defs = [EAX], Uses = [DX] in
74 def IN32rr : I<0xED, RawFrm, (outs), (ins),
75 "in{l}\t{%dx, %eax|EAX, DX}", []>;
78 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
79 "in{b}\t{$port, %al|AL, $port}", []>;
81 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
82 "in{w}\t{$port, %ax|AX, $port}", []>, OpSize;
84 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
85 "in{l}\t{$port, %eax|EAX, $port}", []>;
87 let Uses = [DX, AL] in
88 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
89 "out{b}\t{%al, %dx|DX, AL}", []>;
90 let Uses = [DX, AX] in
91 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
92 "out{w}\t{%ax, %dx|DX, AX}", []>, OpSize;
93 let Uses = [DX, EAX] in
94 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
95 "out{l}\t{%eax, %dx|DX, EAX}", []>;
98 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
99 "out{b}\t{%al, $port|$port, AL}", []>;
101 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
102 "out{w}\t{%ax, $port|$port, AX}", []>, OpSize;
104 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
105 "out{l}\t{%eax, $port|$port, EAX}", []>;
107 def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", []>;
108 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>, OpSize;
109 def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", []>;
111 //===----------------------------------------------------------------------===//
112 // Moves to and from debug registers
114 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
115 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
116 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
117 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
119 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
120 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
121 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
122 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
124 //===----------------------------------------------------------------------===//
125 // Moves to and from control registers
127 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
128 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
129 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
130 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
132 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
133 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
134 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
135 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
137 //===----------------------------------------------------------------------===//
138 // Segment override instruction prefixes
140 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
141 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
142 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
143 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
144 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
145 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
148 //===----------------------------------------------------------------------===//
149 // Moves to and from segment registers.
152 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
153 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
154 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
155 "mov{l}\t{$src, $dst|$dst, $src}", []>;
156 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
157 "mov{q}\t{$src, $dst|$dst, $src}", []>;
159 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
160 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
161 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
162 "mov{l}\t{$src, $dst|$dst, $src}", []>;
163 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
164 "mov{q}\t{$src, $dst|$dst, $src}", []>;
166 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
167 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
168 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
169 "mov{l}\t{$src, $dst|$dst, $src}", []>;
170 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
171 "mov{q}\t{$src, $dst|$dst, $src}", []>;
173 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
174 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
175 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
176 "mov{l}\t{$src, $dst|$dst, $src}", []>;
177 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
178 "mov{q}\t{$src, $dst|$dst, $src}", []>;
180 //===----------------------------------------------------------------------===//
181 // Segmentation support instructions.
183 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
185 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
186 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
187 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
188 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
190 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
191 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
192 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
193 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
194 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
195 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
196 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
197 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
198 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
199 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
201 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
202 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
203 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
204 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
205 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
206 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
207 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
208 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
209 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
210 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
211 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
212 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
214 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
216 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
217 "str{w}\t{$dst}", []>, TB, OpSize;
218 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
219 "str{l}\t{$dst}", []>, TB;
220 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
221 "str{q}\t{$dst}", []>, TB;
222 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
223 "str{w}\t{$dst}", []>, TB;
225 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
226 "ltr{w}\t{$src}", []>, TB;
227 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
228 "ltr{w}\t{$src}", []>, TB;
230 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
231 "push{w}\t{%cs|CS}", []>, Requires<[In32BitMode]>, OpSize;
232 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
233 "push{l}\t{%cs|CS}", []>, Requires<[In32BitMode]>;
234 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
235 "push{w}\t{%ss|SS}", []>, Requires<[In32BitMode]>, OpSize;
236 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
237 "push{l}\t{%ss|SS}", []>, Requires<[In32BitMode]>;
238 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
239 "push{w}\t{%ds|DS}", []>, Requires<[In32BitMode]>, OpSize;
240 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
241 "push{l}\t{%ds|DS}", []>, Requires<[In32BitMode]>;
242 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
243 "push{w}\t{%es|ES}", []>, Requires<[In32BitMode]>, OpSize;
244 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
245 "push{l}\t{%es|ES}", []>, Requires<[In32BitMode]>;
247 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
248 "push{w}\t{%fs|FS}", []>, OpSize, TB;
249 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
250 "push{l}\t{%fs|FS}", []>, TB, Requires<[In32BitMode]>;
251 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
252 "push{w}\t{%gs|GS}", []>, OpSize, TB;
253 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
254 "push{l}\t{%gs|GS}", []>, TB, Requires<[In32BitMode]>;
256 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
257 "push{q}\t{%fs|FS}", []>, TB;
258 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
259 "push{q}\t{%gs|GS}", []>, TB;
261 // No "pop cs" instruction.
262 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
263 "pop{w}\t{%ss|SS}", []>, OpSize, Requires<[In32BitMode]>;
264 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
265 "pop{l}\t{%ss|SS}", []> , Requires<[In32BitMode]>;
267 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
268 "pop{w}\t{%ds|DS}", []>, OpSize, Requires<[In32BitMode]>;
269 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
270 "pop{l}\t{%ds|DS}", []> , Requires<[In32BitMode]>;
272 def POPES16 : I<0x07, RawFrm, (outs), (ins),
273 "pop{w}\t{%es|ES}", []>, OpSize, Requires<[In32BitMode]>;
274 def POPES32 : I<0x07, RawFrm, (outs), (ins),
275 "pop{l}\t{%es|ES}", []> , Requires<[In32BitMode]>;
277 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
278 "pop{w}\t{%fs|FS}", []>, OpSize, TB;
279 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
280 "pop{l}\t{%fs|FS}", []>, TB , Requires<[In32BitMode]>;
281 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
282 "pop{q}\t{%fs|FS}", []>, TB;
284 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
285 "pop{w}\t{%gs|GS}", []>, OpSize, TB;
286 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
287 "pop{l}\t{%gs|GS}", []>, TB , Requires<[In32BitMode]>;
288 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
289 "pop{q}\t{%gs|GS}", []>, TB;
292 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
293 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
294 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
295 "lds{l}\t{$src, $dst|$dst, $src}", []>;
297 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
298 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
299 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
300 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
301 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
302 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
304 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
305 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
306 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
307 "les{l}\t{$src, $dst|$dst, $src}", []>;
309 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
310 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
311 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
312 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
313 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
314 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
316 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
317 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
318 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
319 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
321 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
322 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
325 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
326 "verr\t$seg", []>, TB;
327 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
328 "verr\t$seg", []>, TB;
329 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
330 "verw\t$seg", []>, TB;
331 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
332 "verw\t$seg", []>, TB;
334 //===----------------------------------------------------------------------===//
335 // Descriptor-table support instructions
337 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
338 "sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
339 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
340 "sgdt\t$dst", []>, TB;
341 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
342 "sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
343 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
344 "sidt\t$dst", []>, TB;
345 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
346 "sldt{w}\t$dst", []>, TB, OpSize;
347 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
348 "sldt{w}\t$dst", []>, TB;
349 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
350 "sldt{l}\t$dst", []>, TB;
352 // LLDT is not interpreted specially in 64-bit mode because there is no sign
354 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
355 "sldt{q}\t$dst", []>, TB;
356 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
357 "sldt{q}\t$dst", []>, TB;
359 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
360 "lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
361 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
362 "lgdt\t$src", []>, TB;
363 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
364 "lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
365 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
366 "lidt\t$src", []>, TB;
367 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
368 "lldt{w}\t$src", []>, TB;
369 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
370 "lldt{w}\t$src", []>, TB;
372 //===----------------------------------------------------------------------===//
373 // Specialized register support
374 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
375 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
376 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
378 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
379 "smsw{w}\t$dst", []>, OpSize, TB;
380 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
381 "smsw{l}\t$dst", []>, TB;
382 // no m form encodable; use SMSW16m
383 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
384 "smsw{q}\t$dst", []>, TB;
386 // For memory operands, there is only a 16-bit form
387 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
388 "smsw{w}\t$dst", []>, TB;
390 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
391 "lmsw{w}\t$src", []>, TB;
392 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
393 "lmsw{w}\t$src", []>, TB;
395 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
397 //===----------------------------------------------------------------------===//
398 // Cache instructions
399 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
400 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
402 //===----------------------------------------------------------------------===//
403 // XSAVE instructions
404 let Defs = [RDX, RAX], Uses = [RCX] in
405 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
407 let Uses = [RDX, RAX, RCX] in
408 def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
410 let Uses = [RDX, RAX] in {
411 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
412 "xsave\t$dst", []>, TB;
413 def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
414 "xsaveq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
415 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
416 "xrstor\t$dst", []>, TB;
417 def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
418 "xrstorq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
419 def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
420 "xsaveopt\t$dst", []>, TB;
421 def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
422 "xsaveoptq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
425 //===----------------------------------------------------------------------===//
426 // VIA PadLock crypto instructions
427 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
428 def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
430 def : InstAlias<"xstorerng", (XSTORE)>;
432 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
433 def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
434 def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
435 def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
436 def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
437 def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
440 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
441 def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
442 def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
444 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
445 def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
447 //===----------------------------------------------------------------------===//
448 // FS/GS Base Instructions
449 let Predicates = [HasFSGSBase, In64BitMode] in {
450 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
452 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
453 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
455 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
456 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
458 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
459 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
461 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
462 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
464 [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
465 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
467 [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
468 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
470 [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
471 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
473 [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
476 //===----------------------------------------------------------------------===//
477 // INVPCID Instruction
478 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
479 "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8,
480 Requires<[In32BitMode]>;
481 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
482 "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8,
483 Requires<[In64BitMode]>;