1 //===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let Defs = [RAX, RDX] in
17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
19 let Defs = [RAX, RCX, RDX] in
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
22 // CPU flow control instructions
24 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
28 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
30 // Interrupt and SysCall Instructions.
31 let Uses = [EFLAGS] in
32 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
33 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
34 [(int_x86_int (i8 3))]>;
35 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
36 [(int_x86_int imm:$trap)]>;
38 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
39 def SYSRETL : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
40 def SYSRETQ :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
41 Requires<[In64BitMode]>;
43 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
45 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
46 Requires<[In32BitMode]>;
47 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
48 Requires<[In64BitMode]>;
50 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
51 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
52 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
53 Requires<[In64BitMode]>;
56 //===----------------------------------------------------------------------===//
57 // Input/Output Instructions.
59 let Defs = [AL], Uses = [DX] in
60 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
61 "in{b}\t{%dx, %al|%AL, %DX}", []>;
62 let Defs = [AX], Uses = [DX] in
63 def IN16rr : I<0xED, RawFrm, (outs), (ins),
64 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
65 let Defs = [EAX], Uses = [DX] in
66 def IN32rr : I<0xED, RawFrm, (outs), (ins),
67 "in{l}\t{%dx, %eax|%EAX, %DX}", []>;
70 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
71 "in{b}\t{$port, %al|%AL, $port}", []>;
73 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
74 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
76 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
77 "in{l}\t{$port, %eax|%EAX, $port}", []>;
79 let Uses = [DX, AL] in
80 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
81 "out{b}\t{%al, %dx|%DX, %AL}", []>;
82 let Uses = [DX, AX] in
83 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
84 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
85 let Uses = [DX, EAX] in
86 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
87 "out{l}\t{%eax, %dx|%DX, %EAX}", []>;
90 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
91 "out{b}\t{%al, $port|$port, %AL}", []>;
93 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
94 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
96 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
97 "out{l}\t{%eax, $port|$port, %EAX}", []>;
99 def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", []>;
100 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>, OpSize;
101 def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", []>;
103 //===----------------------------------------------------------------------===//
104 // Moves to and from debug registers
106 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
107 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
108 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
109 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
111 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
112 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
113 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
114 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
116 //===----------------------------------------------------------------------===//
117 // Moves to and from control registers
119 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
120 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
121 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
122 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
124 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
125 "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
126 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
127 "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
129 //===----------------------------------------------------------------------===//
130 // Segment override instruction prefixes
132 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
133 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
134 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
135 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
136 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
137 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
140 //===----------------------------------------------------------------------===//
141 // Moves to and from segment registers.
144 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
145 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
146 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
147 "mov{l}\t{$src, $dst|$dst, $src}", []>;
148 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
149 "mov{q}\t{$src, $dst|$dst, $src}", []>;
151 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
152 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
153 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
154 "mov{l}\t{$src, $dst|$dst, $src}", []>;
155 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
156 "mov{q}\t{$src, $dst|$dst, $src}", []>;
158 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
159 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
160 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
161 "mov{l}\t{$src, $dst|$dst, $src}", []>;
162 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
163 "mov{q}\t{$src, $dst|$dst, $src}", []>;
165 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
166 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
167 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
168 "mov{l}\t{$src, $dst|$dst, $src}", []>;
169 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
170 "mov{q}\t{$src, $dst|$dst, $src}", []>;
172 //===----------------------------------------------------------------------===//
173 // Segmentation support instructions.
175 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
177 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
178 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
179 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
180 "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
182 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
183 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
184 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
185 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
186 "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
187 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
188 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
189 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
190 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
191 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
193 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
194 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
195 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
196 "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
197 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
198 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
199 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
200 "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
201 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
202 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
203 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
204 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
206 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
208 def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
209 "str{w}\t{$dst}", []>, TB;
210 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
211 "str{w}\t{$dst}", []>, TB;
212 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
213 "ltr{w}\t{$src}", []>, TB;
214 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
215 "ltr{w}\t{$src}", []>, TB;
217 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
218 "push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
219 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
220 "push{l}\t%cs", []>, Requires<[In32BitMode]>;
221 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
222 "push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
223 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
224 "push{l}\t%ss", []>, Requires<[In32BitMode]>;
225 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
226 "push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
227 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
228 "push{l}\t%ds", []>, Requires<[In32BitMode]>;
229 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
230 "push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
231 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
232 "push{l}\t%es", []>, Requires<[In32BitMode]>;
234 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
235 "push{w}\t%fs", []>, OpSize, TB;
236 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
237 "push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
238 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
239 "push{w}\t%gs", []>, OpSize, TB;
240 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
241 "push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
243 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
244 "push{q}\t%fs", []>, TB;
245 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
246 "push{q}\t%gs", []>, TB;
248 // No "pop cs" instruction.
249 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
250 "pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
251 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
252 "pop{l}\t%ss", []> , Requires<[In32BitMode]>;
254 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
255 "pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
256 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
257 "pop{l}\t%ds", []> , Requires<[In32BitMode]>;
259 def POPES16 : I<0x07, RawFrm, (outs), (ins),
260 "pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
261 def POPES32 : I<0x07, RawFrm, (outs), (ins),
262 "pop{l}\t%es", []> , Requires<[In32BitMode]>;
264 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
265 "pop{w}\t%fs", []>, OpSize, TB;
266 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
267 "pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
268 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
269 "pop{q}\t%fs", []>, TB;
271 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
272 "pop{w}\t%gs", []>, OpSize, TB;
273 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
274 "pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
275 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
276 "pop{q}\t%gs", []>, TB;
279 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
280 "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
281 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
282 "lds{l}\t{$src, $dst|$dst, $src}", []>;
284 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
285 "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
286 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
287 "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
288 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
289 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
291 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
292 "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
293 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
294 "les{l}\t{$src, $dst|$dst, $src}", []>;
296 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
297 "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
298 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
299 "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
300 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
301 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
303 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
304 "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
305 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
306 "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
308 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
309 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
312 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
313 "verr\t$seg", []>, TB;
314 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
315 "verr\t$seg", []>, TB;
316 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
317 "verw\t$seg", []>, TB;
318 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
319 "verw\t$seg", []>, TB;
321 //===----------------------------------------------------------------------===//
322 // Descriptor-table support instructions
324 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
325 "sgdt\t$dst", []>, TB;
326 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
327 "sidt\t$dst", []>, TB;
328 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
329 "sldt{w}\t$dst", []>, TB, OpSize;
330 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
331 "sldt{w}\t$dst", []>, TB;
332 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
333 "sldt{l}\t$dst", []>, TB;
335 // LLDT is not interpreted specially in 64-bit mode because there is no sign
337 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
338 "sldt{q}\t$dst", []>, TB;
339 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
340 "sldt{q}\t$dst", []>, TB;
342 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
343 "lgdt\t$src", []>, TB;
344 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
345 "lidt\t$src", []>, TB;
346 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
347 "lldt{w}\t$src", []>, TB;
348 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
349 "lldt{w}\t$src", []>, TB;
351 //===----------------------------------------------------------------------===//
352 // Specialized register support
353 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
354 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
355 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
357 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
358 "smsw{w}\t$dst", []>, OpSize, TB;
359 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
360 "smsw{l}\t$dst", []>, TB;
361 // no m form encodable; use SMSW16m
362 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
363 "smsw{q}\t$dst", []>, TB;
365 // For memory operands, there is only a 16-bit form
366 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
367 "smsw{w}\t$dst", []>, TB;
369 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
370 "lmsw{w}\t$src", []>, TB;
371 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
372 "lmsw{w}\t$src", []>, TB;
374 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
376 //===----------------------------------------------------------------------===//
377 // Cache instructions
378 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
379 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;