1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let SchedRW = [WriteSystem] in {
17 let Defs = [RAX, RDX] in
18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
21 let Defs = [RAX, RCX, RDX] in
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
24 // CPU flow control instructions
26 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
34 // Interrupt and SysCall Instructions.
35 let Uses = [EFLAGS] in
36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38 [(int_x86_int (i8 3))], IIC_INT3>;
41 def : Pat<(debugtrap),
44 // The long form of "int $3" turns into int3 as a size optimization.
45 // FIXME: This doesn't work because InstAlias can't match immediate constants.
46 //def : InstAlias<"int\t$3", (INT3)>;
48 let SchedRW = [WriteSystem] in {
50 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
51 [(int_x86_int imm:$trap)], IIC_INT>;
54 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
55 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
56 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
57 Requires<[In64BitMode]>;
59 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
60 IIC_SYS_ENTER_EXIT>, TB;
62 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
63 IIC_SYS_ENTER_EXIT>, TB;
64 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
65 Requires<[In64BitMode]>;
67 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;
68 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
70 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
71 Requires<[In64BitMode]>;
75 //===----------------------------------------------------------------------===//
76 // Input/Output Instructions.
78 let SchedRW = [WriteSystem] in {
79 let Defs = [AL], Uses = [DX] in
80 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
81 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
82 let Defs = [AX], Uses = [DX] in
83 def IN16rr : I<0xED, RawFrm, (outs), (ins),
84 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16;
85 let Defs = [EAX], Uses = [DX] in
86 def IN32rr : I<0xED, RawFrm, (outs), (ins),
87 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
90 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
91 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
93 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
94 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
96 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
97 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
99 let Uses = [DX, AL] in
100 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
101 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
102 let Uses = [DX, AX] in
103 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
104 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
105 let Uses = [DX, EAX] in
106 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
107 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
110 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
111 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
113 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
114 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
116 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
117 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
119 def IN8 : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
120 "insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
121 def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
122 "insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
123 def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
124 "ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
127 //===----------------------------------------------------------------------===//
128 // Moves to and from debug registers
130 let SchedRW = [WriteSystem] in {
131 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
132 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
133 Requires<[Not64BitMode]>;
134 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
135 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
136 Requires<[In64BitMode]>;
138 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
139 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
140 Requires<[Not64BitMode]>;
141 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
142 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
143 Requires<[In64BitMode]>;
146 //===----------------------------------------------------------------------===//
147 // Moves to and from control registers
149 let SchedRW = [WriteSystem] in {
150 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
151 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
152 Requires<[Not64BitMode]>;
153 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
154 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
155 Requires<[In64BitMode]>;
157 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
158 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
159 Requires<[Not64BitMode]>;
160 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
161 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
162 Requires<[In64BitMode]>;
165 //===----------------------------------------------------------------------===//
166 // Segment override instruction prefixes
168 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
169 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
170 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
171 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
172 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
173 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
176 //===----------------------------------------------------------------------===//
177 // Moves to and from segment registers.
180 let SchedRW = [WriteMove] in {
181 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
182 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
183 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
184 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
185 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
186 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
188 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
189 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
190 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
191 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
192 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
193 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
195 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
196 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
197 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
198 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
199 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
200 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
202 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
203 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
204 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
205 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
206 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
207 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
210 //===----------------------------------------------------------------------===//
211 // Segmentation support instructions.
213 let SchedRW = [WriteSystem] in {
214 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
216 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
217 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
219 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
220 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
223 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
224 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
225 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
227 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
228 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
230 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
231 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
232 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
233 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
234 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
236 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
237 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
239 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
240 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
242 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
243 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
245 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
246 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
248 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
249 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
250 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
251 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
253 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
256 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
257 "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
258 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
259 "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
260 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
261 "str{q}\t$dst", [], IIC_STR>, TB;
262 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
263 "str{w}\t$dst", [], IIC_STR>, TB;
265 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
266 "ltr{w}\t$src", [], IIC_LTR>, TB;
267 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
268 "ltr{w}\t$src", [], IIC_LTR>, TB;
270 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
271 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
272 OpSize16, Requires<[Not64BitMode]>;
273 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
274 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
275 OpSize32, Requires<[Not64BitMode]>;
276 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
277 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
278 OpSize16, Requires<[Not64BitMode]>;
279 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
280 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
281 OpSize32, Requires<[Not64BitMode]>;
282 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
283 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
284 OpSize16, Requires<[Not64BitMode]>;
285 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
286 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
287 OpSize32, Requires<[Not64BitMode]>;
288 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
289 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
290 OpSize16, Requires<[Not64BitMode]>;
291 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
292 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
293 OpSize32, Requires<[Not64BitMode]>;
294 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
295 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
296 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
297 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
298 OpSize32, Requires<[Not64BitMode]>;
299 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
300 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
301 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
302 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
303 OpSize32, Requires<[Not64BitMode]>;
304 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
305 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
306 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
307 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
309 // No "pop cs" instruction.
310 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
311 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
312 OpSize16, Requires<[Not64BitMode]>;
313 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
314 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
315 OpSize32, Requires<[Not64BitMode]>;
317 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
318 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
319 OpSize16, Requires<[Not64BitMode]>;
320 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
321 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
322 OpSize32, Requires<[Not64BitMode]>;
324 def POPES16 : I<0x07, RawFrm, (outs), (ins),
325 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
326 OpSize16, Requires<[Not64BitMode]>;
327 def POPES32 : I<0x07, RawFrm, (outs), (ins),
328 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
329 OpSize32, Requires<[Not64BitMode]>;
331 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
332 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
333 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
334 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
335 OpSize32, Requires<[Not64BitMode]>;
336 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
337 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
339 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
340 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
341 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
342 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
343 OpSize32, Requires<[Not64BitMode]>;
344 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
345 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
348 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
349 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
350 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
351 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
353 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
354 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
355 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
356 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
357 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
358 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
360 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
361 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
362 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
363 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
365 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
366 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
367 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
368 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
369 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
370 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
372 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
373 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
374 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
375 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
377 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
378 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
381 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
382 "verr\t$seg", [], IIC_VERR>, TB;
383 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
384 "verr\t$seg", [], IIC_VERR>, TB;
385 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
386 "verw\t$seg", [], IIC_VERW_MEM>, TB;
387 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
388 "verw\t$seg", [], IIC_VERW_REG>, TB;
391 //===----------------------------------------------------------------------===//
392 // Descriptor-table support instructions
394 let SchedRW = [WriteSystem] in {
395 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
396 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
397 def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
398 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
399 def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
400 "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
401 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
402 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
403 def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
404 "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
405 def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
406 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
407 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
408 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
409 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
410 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
411 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
412 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
414 // LLDT is not interpreted specially in 64-bit mode because there is no sign
416 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
417 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
418 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
419 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
421 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
422 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
423 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
424 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
425 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
426 "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
427 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
428 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
429 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
430 "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
431 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
432 "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
433 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
434 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
435 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
436 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
439 //===----------------------------------------------------------------------===//
440 // Specialized register support
441 let SchedRW = [WriteSystem] in {
442 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
443 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
444 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
446 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
447 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
448 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
449 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
450 // no m form encodable; use SMSW16m
451 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
452 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
454 // For memory operands, there is only a 16-bit form
455 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
456 "smsw{w}\t$dst", [], IIC_SMSW>, TB;
458 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
459 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
460 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
461 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
463 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
464 def CPUID32 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
465 Requires<[Not64BitMode]>;
466 let Defs = [RAX, RBX, RCX, RDX], Uses = [RAX, RCX] in
467 def CPUID64 : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB,
468 Requires<[In64BitMode]>;
471 //===----------------------------------------------------------------------===//
472 // Cache instructions
473 let SchedRW = [WriteSystem] in {
474 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
475 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
478 //===----------------------------------------------------------------------===//
479 // XSAVE instructions
480 let SchedRW = [WriteSystem] in {
481 let Defs = [RDX, RAX], Uses = [RCX] in
482 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
484 let Uses = [RDX, RAX, RCX] in
485 def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
487 let Uses = [RDX, RAX] in {
488 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
489 "xsave\t$dst", []>, TB;
490 def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
491 "xsave{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
492 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
493 "xrstor\t$dst", []>, TB;
494 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
495 "xrstor{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
496 def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
497 "xsaveopt\t$dst", []>, TB;
498 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
499 "xsaveopt{q|64}\t$dst", []>, TB, Requires<[In64BitMode]>;
503 //===----------------------------------------------------------------------===//
504 // VIA PadLock crypto instructions
505 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
506 def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
508 def : InstAlias<"xstorerng", (XSTORE)>;
510 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
511 def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
512 def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
513 def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
514 def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
515 def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
518 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
519 def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
520 def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
522 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
523 def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
525 //===----------------------------------------------------------------------===//
526 // FS/GS Base Instructions
527 let Predicates = [HasFSGSBase, In64BitMode] in {
528 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
530 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
531 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
533 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
534 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
536 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
537 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
539 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
540 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
542 [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
543 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
545 [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
546 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
548 [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
549 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
551 [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
554 //===----------------------------------------------------------------------===//
555 // INVPCID Instruction
556 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
557 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
558 Requires<[Not64BitMode]>;
559 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
560 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
561 Requires<[In64BitMode]>;
563 //===----------------------------------------------------------------------===//
565 let Defs = [EFLAGS], Uses = [EFLAGS] in {
566 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
567 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;