1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let Defs = [RAX, RDX] in
17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
20 let Defs = [RAX, RCX, RDX] in
21 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
23 // CPU flow control instructions
25 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
26 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
30 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
31 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33 // Interrupt and SysCall Instructions.
34 let Uses = [EFLAGS] in
35 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
36 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
37 [(int_x86_int (i8 3))], IIC_INT3>;
39 // The long form of "int $3" turns into int3 as a size optimization.
40 // FIXME: This doesn't work because InstAlias can't match immediate constants.
41 //def : InstAlias<"int\t$3", (INT3)>;
44 def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
45 [(int_x86_int imm:$trap)], IIC_INT>;
48 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
49 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
50 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
51 Requires<[In64BitMode]>;
53 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
54 IIC_SYS_ENTER_EXIT>, TB;
56 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
57 IIC_SYS_ENTER_EXIT>, TB;
58 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
59 Requires<[In64BitMode]>;
61 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
62 def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>;
63 def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
64 Requires<[In64BitMode]>;
67 //===----------------------------------------------------------------------===//
68 // Input/Output Instructions.
70 let Defs = [AL], Uses = [DX] in
71 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
72 "in{b}\t{%dx, %al|AL, DX}", [], IIC_IN_RR>;
73 let Defs = [AX], Uses = [DX] in
74 def IN16rr : I<0xED, RawFrm, (outs), (ins),
75 "in{w}\t{%dx, %ax|AX, DX}", [], IIC_IN_RR>, OpSize;
76 let Defs = [EAX], Uses = [DX] in
77 def IN32rr : I<0xED, RawFrm, (outs), (ins),
78 "in{l}\t{%dx, %eax|EAX, DX}", [], IIC_IN_RR>;
81 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
82 "in{b}\t{$port, %al|AL, $port}", [], IIC_IN_RI>;
84 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
85 "in{w}\t{$port, %ax|AX, $port}", [], IIC_IN_RI>, OpSize;
87 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
88 "in{l}\t{$port, %eax|EAX, $port}", [], IIC_IN_RI>;
90 let Uses = [DX, AL] in
91 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
92 "out{b}\t{%al, %dx|DX, AL}", [], IIC_OUT_RR>;
93 let Uses = [DX, AX] in
94 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
95 "out{w}\t{%ax, %dx|DX, AX}", [], IIC_OUT_RR>, OpSize;
96 let Uses = [DX, EAX] in
97 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
98 "out{l}\t{%eax, %dx|DX, EAX}", [], IIC_OUT_RR>;
101 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
102 "out{b}\t{%al, $port|$port, AL}", [], IIC_OUT_IR>;
104 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
105 "out{w}\t{%ax, $port|$port, AX}", [], IIC_OUT_IR>, OpSize;
107 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
108 "out{l}\t{%eax, $port|$port, EAX}", [], IIC_OUT_IR>;
110 def IN8 : I<0x6C, RawFrm, (outs), (ins), "ins{b}", [], IIC_INS>;
111 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", [], IIC_INS>, OpSize;
112 def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", [], IIC_INS>;
114 //===----------------------------------------------------------------------===//
115 // Moves to and from debug registers
117 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
118 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
119 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
120 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB;
122 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
123 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
124 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
125 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB;
127 //===----------------------------------------------------------------------===//
128 // Moves to and from control registers
130 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
131 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
132 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
133 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB;
135 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
136 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
137 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
138 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB;
140 //===----------------------------------------------------------------------===//
141 // Segment override instruction prefixes
143 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
144 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
145 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
146 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
147 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
148 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
151 //===----------------------------------------------------------------------===//
152 // Moves to and from segment registers.
155 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
156 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
157 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
158 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
159 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
160 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
162 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
163 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
164 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
165 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
166 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
167 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
169 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
170 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
171 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
172 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
173 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
174 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
176 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
177 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
178 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
179 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
180 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
181 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
183 //===----------------------------------------------------------------------===//
184 // Segmentation support instructions.
186 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
188 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
189 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
190 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
191 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
193 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
194 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
195 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
196 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
197 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
198 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
199 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
200 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
201 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
202 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
204 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
205 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize;
206 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
207 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
208 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
209 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
210 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
211 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
212 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
213 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
214 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
215 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
217 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
220 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
221 "str{w}\t$dst", [], IIC_STR>, TB, OpSize;
222 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
223 "str{l}\t$dst", [], IIC_STR>, TB;
224 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
225 "str{q}\t$dst", [], IIC_STR>, TB;
226 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
227 "str{w}\t$dst", [], IIC_STR>, TB;
229 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
230 "ltr{w}\t$src", [], IIC_LTR>, TB;
231 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
232 "ltr{w}\t$src", [], IIC_LTR>, TB;
234 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
235 "push{w}\t{%cs|CS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
237 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
238 "push{l}\t{%cs|CS}", [], IIC_PUSH_CS>, Requires<[In32BitMode]>;
239 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
240 "push{w}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
242 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
243 "push{l}\t{%ss|SS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
244 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
245 "push{w}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
247 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
248 "push{l}\t{%ds|DS}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
249 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
250 "push{w}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>,
252 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
253 "push{l}\t{%es|ES}", [], IIC_PUSH_SR>, Requires<[In32BitMode]>;
255 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
256 "push{w}\t{%fs|FS}", [], IIC_PUSH_SR>, OpSize, TB;
257 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
258 "push{l}\t{%fs|FS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
259 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
260 "push{w}\t{%gs|GS}", [], IIC_PUSH_SR>, OpSize, TB;
261 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
262 "push{l}\t{%gs|GS}", [], IIC_PUSH_SR>, TB, Requires<[In32BitMode]>;
264 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
265 "push{q}\t{%fs|FS}", [], IIC_PUSH_SR>, TB;
266 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
267 "push{q}\t{%gs|GS}", [], IIC_PUSH_SR>, TB;
269 // No "pop cs" instruction.
270 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
271 "pop{w}\t{%ss|SS}", [], IIC_POP_SR_SS>,
272 OpSize, Requires<[In32BitMode]>;
273 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
274 "pop{l}\t{%ss|SS}", [], IIC_POP_SR_SS>,
275 Requires<[In32BitMode]>;
277 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
278 "pop{w}\t{%ds|DS}", [], IIC_POP_SR>,
279 OpSize, Requires<[In32BitMode]>;
280 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
281 "pop{l}\t{%ds|DS}", [], IIC_POP_SR>,
282 Requires<[In32BitMode]>;
284 def POPES16 : I<0x07, RawFrm, (outs), (ins),
285 "pop{w}\t{%es|ES}", [], IIC_POP_SR>,
286 OpSize, Requires<[In32BitMode]>;
287 def POPES32 : I<0x07, RawFrm, (outs), (ins),
288 "pop{l}\t{%es|ES}", [], IIC_POP_SR>,
289 Requires<[In32BitMode]>;
291 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
292 "pop{w}\t{%fs|FS}", [], IIC_POP_SR>, OpSize, TB;
293 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
294 "pop{l}\t{%fs|FS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
295 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
296 "pop{q}\t{%fs|FS}", [], IIC_POP_SR>, TB;
298 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
299 "pop{w}\t{%gs|GS}", [], IIC_POP_SR>, OpSize, TB;
300 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
301 "pop{l}\t{%gs|GS}", [], IIC_POP_SR>, TB, Requires<[In32BitMode]>;
302 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
303 "pop{q}\t{%gs|GS}", [], IIC_POP_SR>, TB;
306 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
307 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
308 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
309 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
311 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
312 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
313 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
314 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
315 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
316 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
318 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
319 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
320 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
321 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>;
323 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
324 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
325 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
326 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
327 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
328 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
330 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
331 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
332 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
333 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
335 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
336 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
339 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
340 "verr\t$seg", [], IIC_VERR>, TB;
341 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
342 "verr\t$seg", [], IIC_VERR>, TB;
343 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
344 "verw\t$seg", [], IIC_VERW_MEM>, TB;
345 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
346 "verw\t$seg", [], IIC_VERW_REG>, TB;
348 //===----------------------------------------------------------------------===//
349 // Descriptor-table support instructions
351 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
352 "sgdtw\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[In32BitMode]>;
353 def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
354 "sgdt\t$dst", [], IIC_SGDT>, TB;
355 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
356 "sidtw\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[In32BitMode]>;
357 def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
358 "sidt\t$dst", []>, TB;
359 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
360 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
361 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
362 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
363 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
364 "sldt{l}\t$dst", [], IIC_SLDT>, TB;
366 // LLDT is not interpreted specially in 64-bit mode because there is no sign
368 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
369 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
370 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
371 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
373 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
374 "lgdtw\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[In32BitMode]>;
375 def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
376 "lgdt\t$src", [], IIC_LGDT>, TB;
377 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
378 "lidtw\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[In32BitMode]>;
379 def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
380 "lidt\t$src", [], IIC_LIDT>, TB;
381 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
382 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
383 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
384 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
386 //===----------------------------------------------------------------------===//
387 // Specialized register support
388 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
389 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
390 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
392 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
393 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
394 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
395 "smsw{l}\t$dst", [], IIC_SMSW>, TB;
396 // no m form encodable; use SMSW16m
397 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
398 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
400 // For memory operands, there is only a 16-bit form
401 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
402 "smsw{w}\t$dst", [], IIC_SMSW>, TB;
404 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
405 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
406 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
407 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
409 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
411 //===----------------------------------------------------------------------===//
412 // Cache instructions
413 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
414 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
416 //===----------------------------------------------------------------------===//
417 // XSAVE instructions
418 let Defs = [RDX, RAX], Uses = [RCX] in
419 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
421 let Uses = [RDX, RAX, RCX] in
422 def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
424 let Uses = [RDX, RAX] in {
425 def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
426 "xsave\t$dst", []>, TB;
427 def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
428 "xsaveq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
429 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
430 "xrstor\t$dst", []>, TB;
431 def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
432 "xrstorq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
433 def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
434 "xsaveopt\t$dst", []>, TB;
435 def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
436 "xsaveoptq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
439 //===----------------------------------------------------------------------===//
440 // VIA PadLock crypto instructions
441 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
442 def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
444 def : InstAlias<"xstorerng", (XSTORE)>;
446 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
447 def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
448 def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
449 def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
450 def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
451 def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
454 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
455 def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
456 def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
458 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
459 def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
461 //===----------------------------------------------------------------------===//
462 // FS/GS Base Instructions
463 let Predicates = [HasFSGSBase, In64BitMode] in {
464 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
466 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, TB, XS;
467 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
469 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, TB, XS;
470 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
472 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, TB, XS;
473 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
475 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, TB, XS;
476 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
478 [(int_x86_wrfsbase_32 GR32:$src)]>, TB, XS;
479 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
481 [(int_x86_wrfsbase_64 GR64:$src)]>, TB, XS;
482 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
484 [(int_x86_wrgsbase_32 GR32:$src)]>, TB, XS;
485 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
487 [(int_x86_wrgsbase_64 GR64:$src)]>, TB, XS;
490 //===----------------------------------------------------------------------===//
491 // INVPCID Instruction
492 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
493 "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8,
494 Requires<[In32BitMode]>;
495 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
496 "invpcid {$src2, $src1|$src1, $src2}", []>, OpSize, T8,
497 Requires<[In64BitMode]>;