1 //===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86 instructions that are generally used in
11 // privileged modes. These are not typically used by the compiler, but are
12 // supported for the assembler and disassembler.
14 //===----------------------------------------------------------------------===//
16 let SchedRW = [WriteSystem] in {
17 let Defs = [RAX, RDX] in
18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
21 let Defs = [RAX, RCX, RDX] in
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
24 // CPU flow control instructions
26 let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
34 // Interrupt and SysCall Instructions.
35 let Uses = [EFLAGS] in
36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38 [(int_x86_int (i8 3))], IIC_INT3>;
41 // The long form of "int $3" turns into int3 as a size optimization.
42 // FIXME: This doesn't work because InstAlias can't match immediate constants.
43 //def : InstAlias<"int\t$3", (INT3)>;
45 let SchedRW = [WriteSystem] in {
47 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
48 [(int_x86_int imm:$trap)], IIC_INT>;
51 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52 def SYSRET : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53 def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
54 Requires<[In64BitMode]>;
56 def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
57 IIC_SYS_ENTER_EXIT>, TB;
59 def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
60 IIC_SYS_ENTER_EXIT>, TB;
61 def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
62 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
65 def : Pat<(debugtrap),
66 (INT3)>, Requires<[NotPS4]>;
67 def : Pat<(debugtrap),
68 (INT (i8 0x41))>, Requires<[IsPS4]>;
70 //===----------------------------------------------------------------------===//
71 // Input/Output Instructions.
73 let SchedRW = [WriteSystem] in {
74 let Defs = [AL], Uses = [DX] in
75 def IN8rr : I<0xEC, RawFrm, (outs), (ins),
76 "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
77 let Defs = [AX], Uses = [DX] in
78 def IN16rr : I<0xED, RawFrm, (outs), (ins),
79 "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16;
80 let Defs = [EAX], Uses = [DX] in
81 def IN32rr : I<0xED, RawFrm, (outs), (ins),
82 "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
85 def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins u8imm:$port),
86 "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
88 def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
89 "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
91 def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins u8imm:$port),
92 "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
94 let Uses = [DX, AL] in
95 def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
96 "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
97 let Uses = [DX, AX] in
98 def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
99 "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
100 let Uses = [DX, EAX] in
101 def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
102 "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
105 def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins u8imm:$port),
106 "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
108 def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
109 "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
111 def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins u8imm:$port),
112 "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
116 //===----------------------------------------------------------------------===//
117 // Moves to and from debug registers
119 let SchedRW = [WriteSystem] in {
120 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
121 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
122 Requires<[Not64BitMode]>;
123 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
124 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
125 Requires<[In64BitMode]>;
127 def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
128 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
129 Requires<[Not64BitMode]>;
130 def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
131 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
132 Requires<[In64BitMode]>;
135 //===----------------------------------------------------------------------===//
136 // Moves to and from control registers
138 let SchedRW = [WriteSystem] in {
139 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
140 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
141 Requires<[Not64BitMode]>;
142 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
143 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
144 Requires<[In64BitMode]>;
146 def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
147 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
148 Requires<[Not64BitMode]>;
149 def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
150 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
151 Requires<[In64BitMode]>;
154 //===----------------------------------------------------------------------===//
155 // Segment override instruction prefixes
157 def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
158 def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
159 def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
160 def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
161 def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
162 def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
165 //===----------------------------------------------------------------------===//
166 // Moves to and from segment registers.
169 let SchedRW = [WriteMove] in {
170 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
171 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
172 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
173 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
174 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
175 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
177 def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
178 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
179 def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
180 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
181 def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
182 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
184 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
185 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
186 def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
187 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
188 def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
189 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
191 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
192 "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
193 def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
194 "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
195 def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
196 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
199 //===----------------------------------------------------------------------===//
200 // Segmentation support instructions.
202 let SchedRW = [WriteSystem] in {
203 def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
205 def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
206 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
208 def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
209 "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
212 // i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
213 def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
214 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
216 def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
217 "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
219 // i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
220 def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
221 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
222 def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
223 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
225 def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
226 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
228 def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
229 "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
231 def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
232 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
234 def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
235 "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
237 def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
238 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
239 def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
240 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
242 def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
245 def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
246 "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
247 def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
248 "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
249 def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
250 "str{q}\t$dst", [], IIC_STR>, TB;
251 def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
252 "str{w}\t$dst", [], IIC_STR>, TB;
254 def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
255 "ltr{w}\t$src", [], IIC_LTR>, TB;
256 def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
257 "ltr{w}\t$src", [], IIC_LTR>, TB;
259 def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
260 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
261 OpSize16, Requires<[Not64BitMode]>;
262 def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
263 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
264 OpSize32, Requires<[Not64BitMode]>;
265 def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
266 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
267 OpSize16, Requires<[Not64BitMode]>;
268 def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
269 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
270 OpSize32, Requires<[Not64BitMode]>;
271 def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
272 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
273 OpSize16, Requires<[Not64BitMode]>;
274 def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
275 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
276 OpSize32, Requires<[Not64BitMode]>;
277 def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
278 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
279 OpSize16, Requires<[Not64BitMode]>;
280 def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
281 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
282 OpSize32, Requires<[Not64BitMode]>;
283 def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
284 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
285 def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
286 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
287 OpSize32, Requires<[Not64BitMode]>;
288 def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
289 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
290 def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
291 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
292 OpSize32, Requires<[Not64BitMode]>;
293 def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
294 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
295 OpSize32, Requires<[In64BitMode]>;
296 def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
297 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
298 OpSize32, Requires<[In64BitMode]>;
300 // No "pop cs" instruction.
301 def POPSS16 : I<0x17, RawFrm, (outs), (ins),
302 "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
303 OpSize16, Requires<[Not64BitMode]>;
304 def POPSS32 : I<0x17, RawFrm, (outs), (ins),
305 "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
306 OpSize32, Requires<[Not64BitMode]>;
308 def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
309 "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
310 OpSize16, Requires<[Not64BitMode]>;
311 def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
312 "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
313 OpSize32, Requires<[Not64BitMode]>;
315 def POPES16 : I<0x07, RawFrm, (outs), (ins),
316 "pop{w}\t{%es|es}", [], IIC_POP_SR>,
317 OpSize16, Requires<[Not64BitMode]>;
318 def POPES32 : I<0x07, RawFrm, (outs), (ins),
319 "pop{l}\t{%es|es}", [], IIC_POP_SR>,
320 OpSize32, Requires<[Not64BitMode]>;
322 def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
323 "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
324 def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
325 "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
326 OpSize32, Requires<[Not64BitMode]>;
327 def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
328 "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
329 OpSize32, Requires<[In64BitMode]>;
331 def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
332 "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
333 def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
334 "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
335 OpSize32, Requires<[Not64BitMode]>;
336 def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
337 "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
338 OpSize32, Requires<[In64BitMode]>;
341 def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
342 "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
343 def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
344 "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
346 def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
347 "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
348 def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
349 "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
350 def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
351 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
353 def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
354 "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
355 def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
356 "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
358 def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
359 "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
360 def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
361 "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
362 def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
363 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
365 def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
366 "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
367 def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
368 "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
370 def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
371 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
374 def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
375 "verr\t$seg", [], IIC_VERR>, TB;
376 def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
377 "verr\t$seg", [], IIC_VERR>, TB;
378 def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
379 "verw\t$seg", [], IIC_VERW_MEM>, TB;
380 def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
381 "verw\t$seg", [], IIC_VERW_REG>, TB;
384 //===----------------------------------------------------------------------===//
385 // Descriptor-table support instructions
387 let SchedRW = [WriteSystem] in {
388 def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
389 "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
390 def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
391 "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
392 def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
393 "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
394 def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
395 "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
396 def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
397 "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
398 def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
399 "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
400 def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
401 "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
402 def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
403 "sldt{w}\t$dst", [], IIC_SLDT>, TB;
404 def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
405 "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
407 // LLDT is not interpreted specially in 64-bit mode because there is no sign
409 def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
410 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
411 def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
412 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
414 def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
415 "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
416 def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
417 "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
418 def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
419 "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
420 def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
421 "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
422 def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
423 "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
424 def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
425 "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
426 def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
427 "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
428 def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
429 "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
432 //===----------------------------------------------------------------------===//
433 // Specialized register support
434 let SchedRW = [WriteSystem] in {
435 let Uses = [EAX, ECX, EDX] in
436 def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
437 let Defs = [EAX, EDX], Uses = [ECX] in
438 def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
440 let Defs = [RAX, RDX], Uses = [ECX] in
441 def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
444 def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
445 "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
446 def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
447 "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
448 // no m form encodable; use SMSW16m
449 def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
450 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
452 // For memory operands, there is only a 16-bit form
453 def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
454 "smsw{w}\t$dst", [], IIC_SMSW>, TB;
456 def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
457 "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
458 def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
459 "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
461 let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
462 def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
465 //===----------------------------------------------------------------------===//
466 // Cache instructions
467 let SchedRW = [WriteSystem] in {
468 def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
469 def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
472 //===----------------------------------------------------------------------===//
473 // XSAVE instructions
474 let SchedRW = [WriteSystem] in {
475 let Predicates = [HasXSAVE] in {
476 let Defs = [EDX, EAX], Uses = [ECX] in
477 def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
479 let Uses = [EDX, EAX, ECX] in
480 def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
483 let Uses = [EDX, EAX] in {
484 let Predicates = [HasXSAVE] in {
485 def XSAVE : I<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
487 [(int_x86_xsave addr:$dst, EDX, EAX)]>, TB;
488 def XSAVE64 : RI<0xAE, MRM4m, (outs), (ins opaque512mem:$dst),
490 [(int_x86_xsave64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
491 def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
493 [(int_x86_xrstor addr:$dst, EDX, EAX)]>, TB;
494 def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
496 [(int_x86_xrstor64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
498 let Predicates = [HasXSAVEOPT] in {
499 def XSAVEOPT : I<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
501 [(int_x86_xsaveopt addr:$dst, EDX, EAX)]>, TB;
502 def XSAVEOPT64 : RI<0xAE, MRM6m, (outs), (ins opaque512mem:$dst),
504 [(int_x86_xsaveopt64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
506 let Predicates = [HasXSAVEC] in {
507 def XSAVEC : I<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
509 [(int_x86_xsavec addr:$dst, EDX, EAX)]>, TB;
510 def XSAVEC64 : RI<0xC7, MRM4m, (outs), (ins opaque512mem:$dst),
512 [(int_x86_xsavec64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
514 let Predicates = [HasXSAVES] in {
515 def XSAVES : I<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
517 [(int_x86_xsaves addr:$dst, EDX, EAX)]>, TB;
518 def XSAVES64 : RI<0xC7, MRM5m, (outs), (ins opaque512mem:$dst),
520 [(int_x86_xsaves64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
521 def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
523 [(int_x86_xrstors addr:$dst, EDX, EAX)]>, TB;
524 def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
526 [(int_x86_xrstors64 addr:$dst, EDX, EAX)]>, TB, Requires<[In64BitMode]>;
531 //===----------------------------------------------------------------------===//
532 // VIA PadLock crypto instructions
533 let Defs = [RAX, RDI], Uses = [RDX, RDI] in
534 def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
536 def : InstAlias<"xstorerng", (XSTORE)>;
538 let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
539 def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
540 def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
541 def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
542 def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
543 def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
546 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
547 def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
548 def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
550 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
551 def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
552 //==-----------------------------------------------------------------------===//
553 // PKU - enable protection key
554 let usesCustomInserter = 1 in {
555 def WRPKRU : PseudoI<(outs), (ins GR32:$src),
556 [(int_x86_wrpkru GR32:$src)]>;
557 def RDPKRU : PseudoI<(outs GR32:$dst), (ins),
558 [(set GR32:$dst, (int_x86_rdpkru))]>;
561 let Defs = [EAX, EDX], Uses = [ECX] in
562 def RDPKRUr : I<0x01, MRM_EE, (outs), (ins), "rdpkru", []>, TB;
563 let Uses = [EAX, ECX, EDX] in
564 def WRPKRUr : I<0x01, MRM_EF, (outs), (ins), "wrpkru", []>, TB;
566 //===----------------------------------------------------------------------===//
567 // FS/GS Base Instructions
568 let Predicates = [HasFSGSBase, In64BitMode] in {
569 def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
571 [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
572 def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
574 [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
575 def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
577 [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
578 def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
580 [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
581 def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
583 [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
584 def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
586 [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
587 def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
589 [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
590 def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
592 [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
595 //===----------------------------------------------------------------------===//
596 // INVPCID Instruction
597 def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
598 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
599 Requires<[Not64BitMode]>;
600 def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
601 "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
602 Requires<[In64BitMode]>;
604 //===----------------------------------------------------------------------===//
606 let Defs = [EFLAGS] in {
607 def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
608 def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
611 //===----------------------------------------------------------------------===//
613 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
614 def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;