1 //===-- X86InstrVMX.td - TSX Instruction Set Extension -----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the instructions that make up the Intel TSX instruction
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
19 [SDNPHasChain, SDNPSideEffect]>;
21 let usesCustomInserter = 1 in
22 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
23 "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
26 let isBranch = 1, isTerminator = 1, Defs = [EAX] in
27 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
28 "xbegin\t$dst", []>, Requires<[HasRTM]>;
30 def XEND : I<0x01, MRM_D5, (outs), (ins),
31 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
33 let Defs = [EFLAGS] in
34 def XTEST : I<0x01, MRM_D6, (outs), (ins),
35 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
37 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
39 [(int_x86_xabort imm:$imm)]>, Requires<[HasRTM]>;
43 let isAsmParserOnly = 1 in {
44 def XACQUIRE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "xacquire", []>, Requires<[HasHLE]>;
45 def XRELEASE_PREFIX : I<0xF3, RawFrm, (outs), (ins), "xrelease", []>, Requires<[HasHLE]>;