1 //====- X86InstrX86-64.td - Describe the X86 Instr. Set ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the X86-64 instruction set, defining the instructions,
11 // and properties of the instructions which are needed for code generation,
12 // machine code emission, and analysis.
14 //===----------------------------------------------------------------------===//
16 //===----------------------------------------------------------------------===//
17 // Operand Definitions...
20 // 64-bits but only 32 bits are significant.
21 def i64i32imm : Operand<i64>;
22 // 64-bits but only 8 bits are significant.
23 def i64i8imm : Operand<i64>;
25 def lea64mem : Operand<i64> {
26 let PrintMethod = "printi64mem";
27 let MIOperandInfo = (ops GR64, i8imm, GR64, i32imm);
30 def lea64_32mem : Operand<i32> {
31 let PrintMethod = "printlea64_32mem";
32 let MIOperandInfo = (ops GR32, i8imm, GR32, i32imm);
35 //===----------------------------------------------------------------------===//
36 // Complex Pattern Definitions...
38 def lea64addr : ComplexPattern<i64, 4, "SelectLEAAddr",
39 [add, mul, shl, or, frameindex, X86Wrapper],
42 //===----------------------------------------------------------------------===//
43 // Pattern fragments...
46 def i64immSExt32 : PatLeaf<(i64 imm), [{
47 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit
48 // sign extended field.
49 return (int64_t)N->getValue() == (int32_t)N->getValue();
52 def i64immZExt32 : PatLeaf<(i64 imm), [{
53 // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit
54 // unsignedsign extended field.
55 return (uint64_t)N->getValue() == (uint32_t)N->getValue();
58 def i64immSExt8 : PatLeaf<(i64 imm), [{
59 // i64immSExt8 predicate - True if the 64-bit immediate fits in a 8-bit
60 // sign extended field.
61 return (int64_t)N->getValue() == (int8_t)N->getValue();
64 def sextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (sextloadi1 node:$ptr))>;
65 def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>;
66 def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>;
67 def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>;
69 def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>;
70 def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>;
71 def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>;
72 def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>;
74 def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>;
75 def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>;
76 def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>;
77 def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>;
79 //===----------------------------------------------------------------------===//
80 // Instruction list...
83 let isImplicitDef = 1 in
84 def IMPLICIT_DEF_GR64 : I<0, Pseudo, (outs GR64:$dst), (ins),
86 [(set GR64:$dst, (undef))]>;
88 //===----------------------------------------------------------------------===//
89 // Call Instructions...
92 // All calls clobber the non-callee saved registers...
93 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
94 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
95 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
96 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
97 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS] in {
98 def CALL64pcrel32 : I<0xE8, RawFrm, (outs), (ins i64imm:$dst, variable_ops),
99 "call\t${dst:call}", []>;
100 def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops),
101 "call\t{*}$dst", [(X86call GR64:$dst)]>;
102 def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops),
103 "call\t{*}$dst", []>;
108 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
109 def TCRETURNdi64 : I<0, Pseudo, (outs), (ins i64imm:$dst, i32imm:$offset),
110 "#TC_RETURN $dst $offset",
113 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
114 def TCRETURNri64 : I<0, Pseudo, (outs), (ins GR64:$dst, i32imm:$offset),
115 "#TC_RETURN $dst $offset",
119 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
120 def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst # TAILCALL",
124 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
125 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
126 [(brind GR64:$dst)]>;
127 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
128 [(brind (loadi64 addr:$dst))]>;
131 //===----------------------------------------------------------------------===//
132 // Miscellaneous Instructions...
134 let Defs = [RBP,RSP], Uses = [RBP,RSP] in
135 def LEAVE64 : I<0xC9, RawFrm,
136 (outs), (ins), "leave", []>;
137 let Defs = [RSP], Uses = [RSP] in {
138 def POP64r : I<0x58, AddRegFrm,
139 (outs GR64:$reg), (ins), "pop{q}\t$reg", []>;
140 def PUSH64r : I<0x50, AddRegFrm,
141 (outs), (ins GR64:$reg), "push{q}\t$reg", []>;
144 let Defs = [RSP, EFLAGS], Uses = [RSP] in
145 def POPFQ : I<0x9D, RawFrm, (outs), (ins), "popf", []>, REX_W;
146 let Defs = [RSP], Uses = [RSP, EFLAGS] in
147 def PUSHFQ : I<0x9C, RawFrm, (outs), (ins), "pushf", []>;
149 def LEA64_32r : I<0x8D, MRMSrcMem,
150 (outs GR32:$dst), (ins lea64_32mem:$src),
151 "lea{l}\t{$src|$dst}, {$dst|$src}",
152 [(set GR32:$dst, lea32addr:$src)]>, Requires<[In64BitMode]>;
154 def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
155 "lea{q}\t{$src|$dst}, {$dst|$src}",
156 [(set GR64:$dst, lea64addr:$src)]>;
158 let isTwoAddress = 1 in
159 def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
161 [(set GR64:$dst, (bswap GR64:$src))]>, TB;
163 def XCHG64rr : RI<0x87, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
164 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
165 def XCHG64mr : RI<0x87, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
166 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
167 def XCHG64rm : RI<0x87, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
168 "xchg{q}\t{$src2|$src1}, {$src1|$src2}", []>;
170 // Bit scan instructions.
171 let Defs = [EFLAGS] in {
172 def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
173 "bsf{q}\t{$src, $dst|$dst, $src}",
174 [(set GR64:$dst, (X86bsf GR64:$src)), (implicit EFLAGS)]>, TB;
175 def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
176 "bsf{q}\t{$src, $dst|$dst, $src}",
177 [(set GR64:$dst, (X86bsf (loadi64 addr:$src))),
178 (implicit EFLAGS)]>, TB;
180 def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
181 "bsr{q}\t{$src, $dst|$dst, $src}",
182 [(set GR64:$dst, (X86bsr GR64:$src)), (implicit EFLAGS)]>, TB;
183 def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
184 "bsr{q}\t{$src, $dst|$dst, $src}",
185 [(set GR64:$dst, (X86bsr (loadi64 addr:$src))),
186 (implicit EFLAGS)]>, TB;
190 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI] in
191 def REP_MOVSQ : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
192 [(X86rep_movs i64)]>, REP;
193 let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI] in
194 def REP_STOSQ : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
195 [(X86rep_stos i64)]>, REP;
197 //===----------------------------------------------------------------------===//
198 // Move Instructions...
201 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
202 "mov{q}\t{$src, $dst|$dst, $src}", []>;
204 let isReMaterializable = 1, neverHasSideEffects = 1 in {
205 def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
206 "movabs{q}\t{$src, $dst|$dst, $src}",
207 [(set GR64:$dst, imm:$src)]>;
208 def MOV64ri32 : RIi32<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src),
209 "mov{q}\t{$src, $dst|$dst, $src}",
210 [(set GR64:$dst, i64immSExt32:$src)]>;
213 let isSimpleLoad = 1 in
214 def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
215 "mov{q}\t{$src, $dst|$dst, $src}",
216 [(set GR64:$dst, (load addr:$src))]>;
218 def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
219 "mov{q}\t{$src, $dst|$dst, $src}",
220 [(store GR64:$src, addr:$dst)]>;
221 def MOV64mi32 : RIi32<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
222 "mov{q}\t{$src, $dst|$dst, $src}",
223 [(store i64immSExt32:$src, addr:$dst)]>;
225 // Sign/Zero extenders
227 def MOVSX64rr8 : RI<0xBE, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
228 "movs{bq|x}\t{$src, $dst|$dst, $src}",
229 [(set GR64:$dst, (sext GR8:$src))]>, TB;
230 def MOVSX64rm8 : RI<0xBE, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
231 "movs{bq|x}\t{$src, $dst|$dst, $src}",
232 [(set GR64:$dst, (sextloadi64i8 addr:$src))]>, TB;
233 def MOVSX64rr16: RI<0xBF, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
234 "movs{wq|x}\t{$src, $dst|$dst, $src}",
235 [(set GR64:$dst, (sext GR16:$src))]>, TB;
236 def MOVSX64rm16: RI<0xBF, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
237 "movs{wq|x}\t{$src, $dst|$dst, $src}",
238 [(set GR64:$dst, (sextloadi64i16 addr:$src))]>, TB;
239 def MOVSX64rr32: RI<0x63, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
240 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
241 [(set GR64:$dst, (sext GR32:$src))]>;
242 def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
243 "movs{lq|xd}\t{$src, $dst|$dst, $src}",
244 [(set GR64:$dst, (sextloadi64i32 addr:$src))]>;
246 def MOVZX64rr8 : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8 :$src),
247 "movz{bq|x}\t{$src, $dst|$dst, $src}",
248 [(set GR64:$dst, (zext GR8:$src))]>, TB;
249 def MOVZX64rm8 : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem :$src),
250 "movz{bq|x}\t{$src, $dst|$dst, $src}",
251 [(set GR64:$dst, (zextloadi64i8 addr:$src))]>, TB;
252 def MOVZX64rr16: RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src),
253 "movz{wq|x}\t{$src, $dst|$dst, $src}",
254 [(set GR64:$dst, (zext GR16:$src))]>, TB;
255 def MOVZX64rm16: RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
256 "movz{wq|x}\t{$src, $dst|$dst, $src}",
257 [(set GR64:$dst, (zextloadi64i16 addr:$src))]>, TB;
259 let Defs = [RAX], Uses = [EAX] in
260 def CDQE : RI<0x98, RawFrm, (outs), (ins),
261 "{cltq|cdqe}", []>; // RAX = signext(EAX)
263 let Defs = [RAX,RDX], Uses = [RAX] in
264 def CQO : RI<0x99, RawFrm, (outs), (ins),
265 "{cqto|cqo}", []>; // RDX:RAX = signext(RAX)
267 //===----------------------------------------------------------------------===//
268 // Arithmetic Instructions...
271 let Defs = [EFLAGS] in {
272 let isTwoAddress = 1 in {
273 let isConvertibleToThreeAddress = 1 in {
274 let isCommutable = 1 in
275 def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
276 "add{q}\t{$src2, $dst|$dst, $src2}",
277 [(set GR64:$dst, (add GR64:$src1, GR64:$src2))]>;
279 def ADD64ri32 : RIi32<0x81, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
280 "add{q}\t{$src2, $dst|$dst, $src2}",
281 [(set GR64:$dst, (add GR64:$src1, i64immSExt32:$src2))]>;
282 def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
283 "add{q}\t{$src2, $dst|$dst, $src2}",
284 [(set GR64:$dst, (add GR64:$src1, i64immSExt8:$src2))]>;
285 } // isConvertibleToThreeAddress
287 def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
288 "add{q}\t{$src2, $dst|$dst, $src2}",
289 [(set GR64:$dst, (add GR64:$src1, (load addr:$src2)))]>;
292 def ADD64mr : RI<0x01, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
293 "add{q}\t{$src2, $dst|$dst, $src2}",
294 [(store (add (load addr:$dst), GR64:$src2), addr:$dst)]>;
295 def ADD64mi32 : RIi32<0x81, MRM0m, (outs), (ins i64mem:$dst, i64i32imm :$src2),
296 "add{q}\t{$src2, $dst|$dst, $src2}",
297 [(store (add (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
298 def ADD64mi8 : RIi8<0x83, MRM0m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
299 "add{q}\t{$src2, $dst|$dst, $src2}",
300 [(store (add (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
302 let Uses = [EFLAGS] in {
303 let isTwoAddress = 1 in {
304 let isCommutable = 1 in
305 def ADC64rr : RI<0x11, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
306 "adc{q}\t{$src2, $dst|$dst, $src2}",
307 [(set GR64:$dst, (adde GR64:$src1, GR64:$src2))]>;
309 def ADC64rm : RI<0x13, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
310 "adc{q}\t{$src2, $dst|$dst, $src2}",
311 [(set GR64:$dst, (adde GR64:$src1, (load addr:$src2)))]>;
313 def ADC64ri32 : RIi32<0x81, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
314 "adc{q}\t{$src2, $dst|$dst, $src2}",
315 [(set GR64:$dst, (adde GR64:$src1, i64immSExt32:$src2))]>;
316 def ADC64ri8 : RIi8<0x83, MRM2r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
317 "adc{q}\t{$src2, $dst|$dst, $src2}",
318 [(set GR64:$dst, (adde GR64:$src1, i64immSExt8:$src2))]>;
321 def ADC64mr : RI<0x11, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
322 "adc{q}\t{$src2, $dst|$dst, $src2}",
323 [(store (adde (load addr:$dst), GR64:$src2), addr:$dst)]>;
324 def ADC64mi32 : RIi32<0x81, MRM2m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
325 "adc{q}\t{$src2, $dst|$dst, $src2}",
326 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
327 def ADC64mi8 : RIi8<0x83, MRM2m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
328 "adc{q}\t{$src2, $dst|$dst, $src2}",
329 [(store (adde (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
332 let isTwoAddress = 1 in {
333 def SUB64rr : RI<0x29, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
334 "sub{q}\t{$src2, $dst|$dst, $src2}",
335 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
337 def SUB64rm : RI<0x2B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
338 "sub{q}\t{$src2, $dst|$dst, $src2}",
339 [(set GR64:$dst, (sub GR64:$src1, (load addr:$src2)))]>;
341 def SUB64ri32 : RIi32<0x81, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
342 "sub{q}\t{$src2, $dst|$dst, $src2}",
343 [(set GR64:$dst, (sub GR64:$src1, i64immSExt32:$src2))]>;
344 def SUB64ri8 : RIi8<0x83, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
345 "sub{q}\t{$src2, $dst|$dst, $src2}",
346 [(set GR64:$dst, (sub GR64:$src1, i64immSExt8:$src2))]>;
349 def SUB64mr : RI<0x29, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
350 "sub{q}\t{$src2, $dst|$dst, $src2}",
351 [(store (sub (load addr:$dst), GR64:$src2), addr:$dst)]>;
352 def SUB64mi32 : RIi32<0x81, MRM5m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
353 "sub{q}\t{$src2, $dst|$dst, $src2}",
354 [(store (sub (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
355 def SUB64mi8 : RIi8<0x83, MRM5m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
356 "sub{q}\t{$src2, $dst|$dst, $src2}",
357 [(store (sub (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
359 let Uses = [EFLAGS] in {
360 let isTwoAddress = 1 in {
361 def SBB64rr : RI<0x19, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
362 "sbb{q}\t{$src2, $dst|$dst, $src2}",
363 [(set GR64:$dst, (sube GR64:$src1, GR64:$src2))]>;
365 def SBB64rm : RI<0x1B, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
366 "sbb{q}\t{$src2, $dst|$dst, $src2}",
367 [(set GR64:$dst, (sube GR64:$src1, (load addr:$src2)))]>;
369 def SBB64ri32 : RIi32<0x81, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
370 "sbb{q}\t{$src2, $dst|$dst, $src2}",
371 [(set GR64:$dst, (sube GR64:$src1, i64immSExt32:$src2))]>;
372 def SBB64ri8 : RIi8<0x83, MRM3r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
373 "sbb{q}\t{$src2, $dst|$dst, $src2}",
374 [(set GR64:$dst, (sube GR64:$src1, i64immSExt8:$src2))]>;
377 def SBB64mr : RI<0x19, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
378 "sbb{q}\t{$src2, $dst|$dst, $src2}",
379 [(store (sube (load addr:$dst), GR64:$src2), addr:$dst)]>;
380 def SBB64mi32 : RIi32<0x81, MRM3m, (outs), (ins i64mem:$dst, i64i32imm:$src2),
381 "sbb{q}\t{$src2, $dst|$dst, $src2}",
382 [(store (sube (load addr:$dst), i64immSExt32:$src2), addr:$dst)]>;
383 def SBB64mi8 : RIi8<0x83, MRM3m, (outs), (ins i64mem:$dst, i64i8imm :$src2),
384 "sbb{q}\t{$src2, $dst|$dst, $src2}",
385 [(store (sube (load addr:$dst), i64immSExt8:$src2), addr:$dst)]>;
389 // Unsigned multiplication
390 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in {
391 def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
392 "mul{q}\t$src", []>; // RAX,RDX = RAX*GR64
393 def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
394 "mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
396 // Signed multiplication
397 def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src),
398 "imul{q}\t$src", []>; // RAX,RDX = RAX*GR64
399 def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
400 "imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
403 let Defs = [EFLAGS] in {
404 let isTwoAddress = 1 in {
405 let isCommutable = 1 in
406 def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
407 "imul{q}\t{$src2, $dst|$dst, $src2}",
408 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>, TB;
410 def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
411 "imul{q}\t{$src2, $dst|$dst, $src2}",
412 [(set GR64:$dst, (mul GR64:$src1, (load addr:$src2)))]>, TB;
415 // Suprisingly enough, these are not two address instructions!
416 def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32
417 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
418 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
419 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>;
420 def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8
421 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
422 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
423 [(set GR64:$dst, (mul GR64:$src1, i64immSExt8:$src2))]>;
424 def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32
425 (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
426 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
427 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt32:$src2))]>;
428 def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8
429 (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2),
430 "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
431 [(set GR64:$dst, (mul (load addr:$src1), i64immSExt8:$src2))]>;
434 // Unsigned division / remainder
435 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in {
436 def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
438 def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
441 // Signed division / remainder
442 def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), // RDX:RAX/r64 = RAX,RDX
443 "idiv{q}\t$src", []>;
444 def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), // RDX:RAX/[mem64] = RAX,RDX
445 "idiv{q}\t$src", []>;
448 // Unary instructions
449 let Defs = [EFLAGS], CodeSize = 2 in {
450 let isTwoAddress = 1 in
451 def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src), "neg{q}\t$dst",
452 [(set GR64:$dst, (ineg GR64:$src))]>;
453 def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
454 [(store (ineg (loadi64 addr:$dst)), addr:$dst)]>;
456 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
457 def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src), "inc{q}\t$dst",
458 [(set GR64:$dst, (add GR64:$src, 1))]>;
459 def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
460 [(store (add (loadi64 addr:$dst), 1), addr:$dst)]>;
462 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in
463 def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src), "dec{q}\t$dst",
464 [(set GR64:$dst, (add GR64:$src, -1))]>;
465 def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
466 [(store (add (loadi64 addr:$dst), -1), addr:$dst)]>;
468 // In 64-bit mode, single byte INC and DEC cannot be encoded.
469 let isTwoAddress = 1, isConvertibleToThreeAddress = 1 in {
470 // Can transform into LEA.
471 def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src), "inc{w}\t$dst",
472 [(set GR16:$dst, (add GR16:$src, 1))]>,
473 OpSize, Requires<[In64BitMode]>;
474 def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src), "inc{l}\t$dst",
475 [(set GR32:$dst, (add GR32:$src, 1))]>,
476 Requires<[In64BitMode]>;
477 def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src), "dec{w}\t$dst",
478 [(set GR16:$dst, (add GR16:$src, -1))]>,
479 OpSize, Requires<[In64BitMode]>;
480 def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src), "dec{l}\t$dst",
481 [(set GR32:$dst, (add GR32:$src, -1))]>,
482 Requires<[In64BitMode]>;
483 } // isConvertibleToThreeAddress
485 // These are duplicates of their 32-bit counterparts. Only needed so X86 knows
486 // how to unfold them.
487 let isTwoAddress = 0, CodeSize = 2 in {
488 def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
489 [(store (add (loadi16 addr:$dst), 1), addr:$dst)]>,
490 OpSize, Requires<[In64BitMode]>;
491 def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
492 [(store (add (loadi32 addr:$dst), 1), addr:$dst)]>,
493 Requires<[In64BitMode]>;
494 def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
495 [(store (add (loadi16 addr:$dst), -1), addr:$dst)]>,
496 OpSize, Requires<[In64BitMode]>;
497 def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
498 [(store (add (loadi32 addr:$dst), -1), addr:$dst)]>,
499 Requires<[In64BitMode]>;
501 } // Defs = [EFLAGS], CodeSize
504 let Defs = [EFLAGS] in {
505 // Shift instructions
506 let isTwoAddress = 1 in {
508 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src),
509 "shl{q}\t{%cl, $dst|$dst, %CL}",
510 [(set GR64:$dst, (shl GR64:$src, CL))]>;
511 let isConvertibleToThreeAddress = 1 in // Can transform into LEA.
512 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
513 "shl{q}\t{$src2, $dst|$dst, $src2}",
514 [(set GR64:$dst, (shl GR64:$src1, (i8 imm:$src2)))]>;
515 def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
520 def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
521 "shl{q}\t{%cl, $dst|$dst, %CL}",
522 [(store (shl (loadi64 addr:$dst), CL), addr:$dst)]>;
523 def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
524 "shl{q}\t{$src, $dst|$dst, $src}",
525 [(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
526 def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
528 [(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
530 let isTwoAddress = 1 in {
532 def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src),
533 "shr{q}\t{%cl, $dst|$dst, %CL}",
534 [(set GR64:$dst, (srl GR64:$src, CL))]>;
535 def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
536 "shr{q}\t{$src2, $dst|$dst, $src2}",
537 [(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))]>;
538 def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
540 [(set GR64:$dst, (srl GR64:$src1, (i8 1)))]>;
544 def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
545 "shr{q}\t{%cl, $dst|$dst, %CL}",
546 [(store (srl (loadi64 addr:$dst), CL), addr:$dst)]>;
547 def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
548 "shr{q}\t{$src, $dst|$dst, $src}",
549 [(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
550 def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
552 [(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
554 let isTwoAddress = 1 in {
556 def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src),
557 "sar{q}\t{%cl, $dst|$dst, %CL}",
558 [(set GR64:$dst, (sra GR64:$src, CL))]>;
559 def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
560 "sar{q}\t{$src2, $dst|$dst, $src2}",
561 [(set GR64:$dst, (sra GR64:$src1, (i8 imm:$src2)))]>;
562 def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
564 [(set GR64:$dst, (sra GR64:$src1, (i8 1)))]>;
568 def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
569 "sar{q}\t{%cl, $dst|$dst, %CL}",
570 [(store (sra (loadi64 addr:$dst), CL), addr:$dst)]>;
571 def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
572 "sar{q}\t{$src, $dst|$dst, $src}",
573 [(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
574 def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
576 [(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
578 // Rotate instructions
579 let isTwoAddress = 1 in {
581 def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src),
582 "rol{q}\t{%cl, $dst|$dst, %CL}",
583 [(set GR64:$dst, (rotl GR64:$src, CL))]>;
584 def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
585 "rol{q}\t{$src2, $dst|$dst, $src2}",
586 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$src2)))]>;
587 def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
589 [(set GR64:$dst, (rotl GR64:$src1, (i8 1)))]>;
593 def ROL64mCL : I<0xD3, MRM0m, (outs), (ins i64mem:$dst),
594 "rol{q}\t{%cl, $dst|$dst, %CL}",
595 [(store (rotl (loadi64 addr:$dst), CL), addr:$dst)]>;
596 def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src),
597 "rol{q}\t{$src, $dst|$dst, $src}",
598 [(store (rotl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
599 def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
601 [(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
603 let isTwoAddress = 1 in {
605 def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src),
606 "ror{q}\t{%cl, $dst|$dst, %CL}",
607 [(set GR64:$dst, (rotr GR64:$src, CL))]>;
608 def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
609 "ror{q}\t{$src2, $dst|$dst, $src2}",
610 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$src2)))]>;
611 def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
613 [(set GR64:$dst, (rotr GR64:$src1, (i8 1)))]>;
617 def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
618 "ror{q}\t{%cl, $dst|$dst, %CL}",
619 [(store (rotr (loadi64 addr:$dst), CL), addr:$dst)]>;
620 def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
621 "ror{q}\t{$src, $dst|$dst, $src}",
622 [(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)]>;
623 def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
625 [(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)]>;
627 // Double shift instructions (generalizations of rotate)
628 let isTwoAddress = 1 in {
630 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
631 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
632 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2, CL))]>, TB;
633 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
634 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
635 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2, CL))]>, TB;
638 let isCommutable = 1 in { // FIXME: Update X86InstrInfo::commuteInstruction
639 def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
640 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
641 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
642 [(set GR64:$dst, (X86shld GR64:$src1, GR64:$src2,
645 def SHRD64rri8 : RIi8<0xAC, MRMDestReg,
646 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$src3),
647 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
648 [(set GR64:$dst, (X86shrd GR64:$src1, GR64:$src2,
655 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
656 "shld{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
657 [(store (X86shld (loadi64 addr:$dst), GR64:$src2, CL),
659 def SHRD64mrCL : RI<0xAD, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
660 "shrd{q}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
661 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2, CL),
664 def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
665 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
666 "shld{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
667 [(store (X86shld (loadi64 addr:$dst), GR64:$src2,
668 (i8 imm:$src3)), addr:$dst)]>,
670 def SHRD64mri8 : RIi8<0xAC, MRMDestMem,
671 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
672 "shrd{q}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
673 [(store (X86shrd (loadi64 addr:$dst), GR64:$src2,
674 (i8 imm:$src3)), addr:$dst)]>,
678 //===----------------------------------------------------------------------===//
679 // Logical Instructions...
682 let isTwoAddress = 1 in
683 def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src), "not{q}\t$dst",
684 [(set GR64:$dst, (not GR64:$src))]>;
685 def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
686 [(store (not (loadi64 addr:$dst)), addr:$dst)]>;
688 let Defs = [EFLAGS] in {
689 let isTwoAddress = 1 in {
690 let isCommutable = 1 in
691 def AND64rr : RI<0x21, MRMDestReg,
692 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
693 "and{q}\t{$src2, $dst|$dst, $src2}",
694 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
695 def AND64rm : RI<0x23, MRMSrcMem,
696 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
697 "and{q}\t{$src2, $dst|$dst, $src2}",
698 [(set GR64:$dst, (and GR64:$src1, (load addr:$src2)))]>;
699 def AND64ri32 : RIi32<0x81, MRM4r,
700 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
701 "and{q}\t{$src2, $dst|$dst, $src2}",
702 [(set GR64:$dst, (and GR64:$src1, i64immSExt32:$src2))]>;
703 def AND64ri8 : RIi8<0x83, MRM4r,
704 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
705 "and{q}\t{$src2, $dst|$dst, $src2}",
706 [(set GR64:$dst, (and GR64:$src1, i64immSExt8:$src2))]>;
709 def AND64mr : RI<0x21, MRMDestMem,
710 (outs), (ins i64mem:$dst, GR64:$src),
711 "and{q}\t{$src, $dst|$dst, $src}",
712 [(store (and (load addr:$dst), GR64:$src), addr:$dst)]>;
713 def AND64mi32 : RIi32<0x81, MRM4m,
714 (outs), (ins i64mem:$dst, i64i32imm:$src),
715 "and{q}\t{$src, $dst|$dst, $src}",
716 [(store (and (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
717 def AND64mi8 : RIi8<0x83, MRM4m,
718 (outs), (ins i64mem:$dst, i64i8imm :$src),
719 "and{q}\t{$src, $dst|$dst, $src}",
720 [(store (and (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
722 let isTwoAddress = 1 in {
723 let isCommutable = 1 in
724 def OR64rr : RI<0x09, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
725 "or{q}\t{$src2, $dst|$dst, $src2}",
726 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
727 def OR64rm : RI<0x0B, MRMSrcMem , (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
728 "or{q}\t{$src2, $dst|$dst, $src2}",
729 [(set GR64:$dst, (or GR64:$src1, (load addr:$src2)))]>;
730 def OR64ri32 : RIi32<0x81, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
731 "or{q}\t{$src2, $dst|$dst, $src2}",
732 [(set GR64:$dst, (or GR64:$src1, i64immSExt32:$src2))]>;
733 def OR64ri8 : RIi8<0x83, MRM1r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
734 "or{q}\t{$src2, $dst|$dst, $src2}",
735 [(set GR64:$dst, (or GR64:$src1, i64immSExt8:$src2))]>;
738 def OR64mr : RI<0x09, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
739 "or{q}\t{$src, $dst|$dst, $src}",
740 [(store (or (load addr:$dst), GR64:$src), addr:$dst)]>;
741 def OR64mi32 : RIi32<0x81, MRM1m, (outs), (ins i64mem:$dst, i64i32imm:$src),
742 "or{q}\t{$src, $dst|$dst, $src}",
743 [(store (or (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
744 def OR64mi8 : RIi8<0x83, MRM1m, (outs), (ins i64mem:$dst, i64i8imm:$src),
745 "or{q}\t{$src, $dst|$dst, $src}",
746 [(store (or (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
748 let isTwoAddress = 1 in {
749 let isCommutable = 1 in
750 def XOR64rr : RI<0x31, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
751 "xor{q}\t{$src2, $dst|$dst, $src2}",
752 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
753 def XOR64rm : RI<0x33, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
754 "xor{q}\t{$src2, $dst|$dst, $src2}",
755 [(set GR64:$dst, (xor GR64:$src1, (load addr:$src2)))]>;
756 def XOR64ri32 : RIi32<0x81, MRM6r,
757 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
758 "xor{q}\t{$src2, $dst|$dst, $src2}",
759 [(set GR64:$dst, (xor GR64:$src1, i64immSExt32:$src2))]>;
760 def XOR64ri8 : RIi8<0x83, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
761 "xor{q}\t{$src2, $dst|$dst, $src2}",
762 [(set GR64:$dst, (xor GR64:$src1, i64immSExt8:$src2))]>;
765 def XOR64mr : RI<0x31, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
766 "xor{q}\t{$src, $dst|$dst, $src}",
767 [(store (xor (load addr:$dst), GR64:$src), addr:$dst)]>;
768 def XOR64mi32 : RIi32<0x81, MRM6m, (outs), (ins i64mem:$dst, i64i32imm:$src),
769 "xor{q}\t{$src, $dst|$dst, $src}",
770 [(store (xor (loadi64 addr:$dst), i64immSExt32:$src), addr:$dst)]>;
771 def XOR64mi8 : RIi8<0x83, MRM6m, (outs), (ins i64mem:$dst, i64i8imm :$src),
772 "xor{q}\t{$src, $dst|$dst, $src}",
773 [(store (xor (load addr:$dst), i64immSExt8:$src), addr:$dst)]>;
776 //===----------------------------------------------------------------------===//
777 // Comparison Instructions...
780 // Integer comparison
781 let Defs = [EFLAGS] in {
782 let isCommutable = 1 in
783 def TEST64rr : RI<0x85, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
784 "test{q}\t{$src2, $src1|$src1, $src2}",
785 [(X86cmp (and GR64:$src1, GR64:$src2), 0),
787 def TEST64rm : RI<0x85, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
788 "test{q}\t{$src2, $src1|$src1, $src2}",
789 [(X86cmp (and GR64:$src1, (loadi64 addr:$src2)), 0),
791 def TEST64ri32 : RIi32<0xF7, MRM0r, (outs),
792 (ins GR64:$src1, i64i32imm:$src2),
793 "test{q}\t{$src2, $src1|$src1, $src2}",
794 [(X86cmp (and GR64:$src1, i64immSExt32:$src2), 0),
796 def TEST64mi32 : RIi32<0xF7, MRM0m, (outs),
797 (ins i64mem:$src1, i64i32imm:$src2),
798 "test{q}\t{$src2, $src1|$src1, $src2}",
799 [(X86cmp (and (loadi64 addr:$src1), i64immSExt32:$src2), 0),
802 def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
803 "cmp{q}\t{$src2, $src1|$src1, $src2}",
804 [(X86cmp GR64:$src1, GR64:$src2),
806 def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
807 "cmp{q}\t{$src2, $src1|$src1, $src2}",
808 [(X86cmp (loadi64 addr:$src1), GR64:$src2),
810 def CMP64rm : RI<0x3B, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
811 "cmp{q}\t{$src2, $src1|$src1, $src2}",
812 [(X86cmp GR64:$src1, (loadi64 addr:$src2)),
814 def CMP64ri32 : RIi32<0x81, MRM7r, (outs), (ins GR64:$src1, i64i32imm:$src2),
815 "cmp{q}\t{$src2, $src1|$src1, $src2}",
816 [(X86cmp GR64:$src1, i64immSExt32:$src2),
818 def CMP64mi32 : RIi32<0x81, MRM7m, (outs),
819 (ins i64mem:$src1, i64i32imm:$src2),
820 "cmp{q}\t{$src2, $src1|$src1, $src2}",
821 [(X86cmp (loadi64 addr:$src1), i64immSExt32:$src2),
823 def CMP64mi8 : RIi8<0x83, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
824 "cmp{q}\t{$src2, $src1|$src1, $src2}",
825 [(X86cmp (loadi64 addr:$src1), i64immSExt8:$src2),
827 def CMP64ri8 : RIi8<0x83, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
828 "cmp{q}\t{$src2, $src1|$src1, $src2}",
829 [(X86cmp GR64:$src1, i64immSExt8:$src2),
834 let Uses = [EFLAGS], isTwoAddress = 1 in {
835 let isCommutable = 1 in {
836 def CMOVB64rr : RI<0x42, MRMSrcReg, // if <u, GR64 = GR64
837 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
838 "cmovb\t{$src2, $dst|$dst, $src2}",
839 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
840 X86_COND_B, EFLAGS))]>, TB;
841 def CMOVAE64rr: RI<0x43, MRMSrcReg, // if >=u, GR64 = GR64
842 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
843 "cmovae\t{$src2, $dst|$dst, $src2}",
844 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
845 X86_COND_AE, EFLAGS))]>, TB;
846 def CMOVE64rr : RI<0x44, MRMSrcReg, // if ==, GR64 = GR64
847 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
848 "cmove\t{$src2, $dst|$dst, $src2}",
849 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
850 X86_COND_E, EFLAGS))]>, TB;
851 def CMOVNE64rr: RI<0x45, MRMSrcReg, // if !=, GR64 = GR64
852 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
853 "cmovne\t{$src2, $dst|$dst, $src2}",
854 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
855 X86_COND_NE, EFLAGS))]>, TB;
856 def CMOVBE64rr: RI<0x46, MRMSrcReg, // if <=u, GR64 = GR64
857 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
858 "cmovbe\t{$src2, $dst|$dst, $src2}",
859 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
860 X86_COND_BE, EFLAGS))]>, TB;
861 def CMOVA64rr : RI<0x47, MRMSrcReg, // if >u, GR64 = GR64
862 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
863 "cmova\t{$src2, $dst|$dst, $src2}",
864 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
865 X86_COND_A, EFLAGS))]>, TB;
866 def CMOVL64rr : RI<0x4C, MRMSrcReg, // if <s, GR64 = GR64
867 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
868 "cmovl\t{$src2, $dst|$dst, $src2}",
869 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
870 X86_COND_L, EFLAGS))]>, TB;
871 def CMOVGE64rr: RI<0x4D, MRMSrcReg, // if >=s, GR64 = GR64
872 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
873 "cmovge\t{$src2, $dst|$dst, $src2}",
874 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
875 X86_COND_GE, EFLAGS))]>, TB;
876 def CMOVLE64rr: RI<0x4E, MRMSrcReg, // if <=s, GR64 = GR64
877 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
878 "cmovle\t{$src2, $dst|$dst, $src2}",
879 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
880 X86_COND_LE, EFLAGS))]>, TB;
881 def CMOVG64rr : RI<0x4F, MRMSrcReg, // if >s, GR64 = GR64
882 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
883 "cmovg\t{$src2, $dst|$dst, $src2}",
884 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
885 X86_COND_G, EFLAGS))]>, TB;
886 def CMOVS64rr : RI<0x48, MRMSrcReg, // if signed, GR64 = GR64
887 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
888 "cmovs\t{$src2, $dst|$dst, $src2}",
889 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
890 X86_COND_S, EFLAGS))]>, TB;
891 def CMOVNS64rr: RI<0x49, MRMSrcReg, // if !signed, GR64 = GR64
892 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
893 "cmovns\t{$src2, $dst|$dst, $src2}",
894 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
895 X86_COND_NS, EFLAGS))]>, TB;
896 def CMOVP64rr : RI<0x4A, MRMSrcReg, // if parity, GR64 = GR64
897 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
898 "cmovp\t{$src2, $dst|$dst, $src2}",
899 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
900 X86_COND_P, EFLAGS))]>, TB;
901 def CMOVNP64rr : RI<0x4B, MRMSrcReg, // if !parity, GR64 = GR64
902 (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
903 "cmovnp\t{$src2, $dst|$dst, $src2}",
904 [(set GR64:$dst, (X86cmov GR64:$src1, GR64:$src2,
905 X86_COND_NP, EFLAGS))]>, TB;
906 } // isCommutable = 1
908 def CMOVB64rm : RI<0x42, MRMSrcMem, // if <u, GR64 = [mem64]
909 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
910 "cmovb\t{$src2, $dst|$dst, $src2}",
911 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
912 X86_COND_B, EFLAGS))]>, TB;
913 def CMOVAE64rm: RI<0x43, MRMSrcMem, // if >=u, GR64 = [mem64]
914 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
915 "cmovae\t{$src2, $dst|$dst, $src2}",
916 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
917 X86_COND_AE, EFLAGS))]>, TB;
918 def CMOVE64rm : RI<0x44, MRMSrcMem, // if ==, GR64 = [mem64]
919 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
920 "cmove\t{$src2, $dst|$dst, $src2}",
921 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
922 X86_COND_E, EFLAGS))]>, TB;
923 def CMOVNE64rm: RI<0x45, MRMSrcMem, // if !=, GR64 = [mem64]
924 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
925 "cmovne\t{$src2, $dst|$dst, $src2}",
926 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
927 X86_COND_NE, EFLAGS))]>, TB;
928 def CMOVBE64rm: RI<0x46, MRMSrcMem, // if <=u, GR64 = [mem64]
929 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
930 "cmovbe\t{$src2, $dst|$dst, $src2}",
931 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
932 X86_COND_BE, EFLAGS))]>, TB;
933 def CMOVA64rm : RI<0x47, MRMSrcMem, // if >u, GR64 = [mem64]
934 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
935 "cmova\t{$src2, $dst|$dst, $src2}",
936 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
937 X86_COND_A, EFLAGS))]>, TB;
938 def CMOVL64rm : RI<0x4C, MRMSrcMem, // if <s, GR64 = [mem64]
939 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
940 "cmovl\t{$src2, $dst|$dst, $src2}",
941 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
942 X86_COND_L, EFLAGS))]>, TB;
943 def CMOVGE64rm: RI<0x4D, MRMSrcMem, // if >=s, GR64 = [mem64]
944 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
945 "cmovge\t{$src2, $dst|$dst, $src2}",
946 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
947 X86_COND_GE, EFLAGS))]>, TB;
948 def CMOVLE64rm: RI<0x4E, MRMSrcMem, // if <=s, GR64 = [mem64]
949 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
950 "cmovle\t{$src2, $dst|$dst, $src2}",
951 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
952 X86_COND_LE, EFLAGS))]>, TB;
953 def CMOVG64rm : RI<0x4F, MRMSrcMem, // if >s, GR64 = [mem64]
954 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
955 "cmovg\t{$src2, $dst|$dst, $src2}",
956 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
957 X86_COND_G, EFLAGS))]>, TB;
958 def CMOVS64rm : RI<0x48, MRMSrcMem, // if signed, GR64 = [mem64]
959 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
960 "cmovs\t{$src2, $dst|$dst, $src2}",
961 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
962 X86_COND_S, EFLAGS))]>, TB;
963 def CMOVNS64rm: RI<0x49, MRMSrcMem, // if !signed, GR64 = [mem64]
964 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
965 "cmovns\t{$src2, $dst|$dst, $src2}",
966 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
967 X86_COND_NS, EFLAGS))]>, TB;
968 def CMOVP64rm : RI<0x4A, MRMSrcMem, // if parity, GR64 = [mem64]
969 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
970 "cmovp\t{$src2, $dst|$dst, $src2}",
971 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
972 X86_COND_P, EFLAGS))]>, TB;
973 def CMOVNP64rm : RI<0x4B, MRMSrcMem, // if !parity, GR64 = [mem64]
974 (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
975 "cmovnp\t{$src2, $dst|$dst, $src2}",
976 [(set GR64:$dst, (X86cmov GR64:$src1, (loadi64 addr:$src2),
977 X86_COND_NP, EFLAGS))]>, TB;
980 //===----------------------------------------------------------------------===//
981 // Conversion Instructions...
985 def Int_CVTSD2SI64rr: RSDI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
986 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
988 (int_x86_sse2_cvtsd2si64 VR128:$src))]>;
989 def Int_CVTSD2SI64rm: RSDI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
990 "cvtsd2si{q}\t{$src, $dst|$dst, $src}",
991 [(set GR64:$dst, (int_x86_sse2_cvtsd2si64
992 (load addr:$src)))]>;
993 def CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src),
994 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
995 [(set GR64:$dst, (fp_to_sint FR64:$src))]>;
996 def CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f64mem:$src),
997 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
998 [(set GR64:$dst, (fp_to_sint (loadf64 addr:$src)))]>;
999 def Int_CVTTSD2SI64rr: RSDI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1000 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1002 (int_x86_sse2_cvttsd2si64 VR128:$src))]>;
1003 def Int_CVTTSD2SI64rm: RSDI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f128mem:$src),
1004 "cvttsd2si{q}\t{$src, $dst|$dst, $src}",
1006 (int_x86_sse2_cvttsd2si64
1007 (load addr:$src)))]>;
1009 // Signed i64 -> f64
1010 def CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1011 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1012 [(set FR64:$dst, (sint_to_fp GR64:$src))]>;
1013 def CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1014 "cvtsi2sd{q}\t{$src, $dst|$dst, $src}",
1015 [(set FR64:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1016 let isTwoAddress = 1 in {
1017 def Int_CVTSI2SD64rr: RSDI<0x2A, MRMSrcReg,
1018 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1019 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1021 (int_x86_sse2_cvtsi642sd VR128:$src1,
1023 def Int_CVTSI2SD64rm: RSDI<0x2A, MRMSrcMem,
1024 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1025 "cvtsi2sd{q}\t{$src2, $dst|$dst, $src2}",
1027 (int_x86_sse2_cvtsi642sd VR128:$src1,
1028 (loadi64 addr:$src2)))]>;
1031 // Signed i64 -> f32
1032 def CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg, (outs FR32:$dst), (ins GR64:$src),
1033 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1034 [(set FR32:$dst, (sint_to_fp GR64:$src))]>;
1035 def CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem, (outs FR32:$dst), (ins i64mem:$src),
1036 "cvtsi2ss{q}\t{$src, $dst|$dst, $src}",
1037 [(set FR32:$dst, (sint_to_fp (loadi64 addr:$src)))]>;
1038 let isTwoAddress = 1 in {
1039 def Int_CVTSI2SS64rr: RSSI<0x2A, MRMSrcReg,
1040 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1041 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1042 []>; // TODO: add intrinsic
1043 def Int_CVTSI2SS64rm: RSSI<0x2A, MRMSrcMem,
1044 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1045 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1046 []>; // TODO: add intrinsic
1049 // f32 -> signed i64
1050 def Int_CVTSS2SI64rr: RSSI<0x2D, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1051 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1053 (int_x86_sse_cvtss2si64 VR128:$src))]>;
1054 def Int_CVTSS2SI64rm: RSSI<0x2D, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1055 "cvtss2si{q}\t{$src, $dst|$dst, $src}",
1056 [(set GR64:$dst, (int_x86_sse_cvtss2si64
1057 (load addr:$src)))]>;
1058 def CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src),
1059 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1060 [(set GR64:$dst, (fp_to_sint FR32:$src))]>;
1061 def CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1062 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1063 [(set GR64:$dst, (fp_to_sint (loadf32 addr:$src)))]>;
1064 def Int_CVTTSS2SI64rr: RSSI<0x2C, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),
1065 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1067 (int_x86_sse_cvttss2si64 VR128:$src))]>;
1068 def Int_CVTTSS2SI64rm: RSSI<0x2C, MRMSrcMem, (outs GR64:$dst), (ins f32mem:$src),
1069 "cvttss2si{q}\t{$src, $dst|$dst, $src}",
1071 (int_x86_sse_cvttss2si64 (load addr:$src)))]>;
1073 let isTwoAddress = 1 in {
1074 def Int_CVTSI642SSrr : RSSI<0x2A, MRMSrcReg,
1075 (outs VR128:$dst), (ins VR128:$src1, GR64:$src2),
1076 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1078 (int_x86_sse_cvtsi642ss VR128:$src1,
1080 def Int_CVTSI642SSrm : RSSI<0x2A, MRMSrcMem,
1081 (outs VR128:$dst), (ins VR128:$src1, i64mem:$src2),
1082 "cvtsi2ss{q}\t{$src2, $dst|$dst, $src2}",
1084 (int_x86_sse_cvtsi642ss VR128:$src1,
1085 (loadi64 addr:$src2)))]>;
1088 //===----------------------------------------------------------------------===//
1089 // Alias Instructions
1090 //===----------------------------------------------------------------------===//
1093 // TODO: Remove this after proper i32 -> i64 zext support.
1094 def PsMOVZX64rr32: I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
1095 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1096 [(set GR64:$dst, (zext GR32:$src))]>;
1097 def PsMOVZX64rm32: I<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
1098 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1099 [(set GR64:$dst, (zextloadi64i32 addr:$src))]>;
1102 // Alias instructions that map movr0 to xor. Use xorl instead of xorq; it's
1103 // equivalent due to implicit zero-extending, and it sometimes has a smaller
1105 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
1106 // FIXME: AddedComplexity gives MOV64r0 a higher priority than MOV64ri32. Remove
1107 // when we have a better way to specify isel priority.
1108 let Defs = [EFLAGS], AddedComplexity = 1, isReMaterializable = 1,
1109 neverHasSideEffects = 1 in
1110 def MOV64r0 : RI<0x31, MRMInitReg, (outs GR64:$dst), (ins),
1111 "xor{l}\t${dst:subreg32}, ${dst:subreg32}",
1112 [(set GR64:$dst, 0)]>;
1114 // Materialize i64 constant where top 32-bits are zero.
1115 let AddedComplexity = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
1116 def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src),
1117 "mov{l}\t{$src, ${dst:subreg32}|${dst:subreg32}, $src}",
1118 [(set GR64:$dst, i64immZExt32:$src)]>;
1120 //===----------------------------------------------------------------------===//
1121 // Non-Instruction Patterns
1122 //===----------------------------------------------------------------------===//
1124 // ConstantPool GlobalAddress, ExternalSymbol, and JumpTable
1125 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1126 (MOV64ri tconstpool :$dst)>, Requires<[NotSmallCode]>;
1127 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1128 (MOV64ri tjumptable :$dst)>, Requires<[NotSmallCode]>;
1129 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1130 (MOV64ri tglobaladdr :$dst)>, Requires<[NotSmallCode]>;
1131 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1132 (MOV64ri texternalsym:$dst)>, Requires<[NotSmallCode]>;
1134 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1135 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1136 Requires<[SmallCode, HasLow4G, IsStatic]>;
1137 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1138 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1139 Requires<[SmallCode, HasLow4G, IsStatic]>;
1140 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1141 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1142 Requires<[SmallCode, HasLow4G, IsStatic]>;
1143 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1144 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1145 Requires<[SmallCode, HasLow4G, IsStatic]>;
1148 // Direct PC relative function call for small code model. 32-bit displacement
1149 // sign extended to 64-bit.
1150 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1151 (CALL64pcrel32 tglobaladdr:$dst)>;
1152 def : Pat<(X86call (i64 texternalsym:$dst)),
1153 (CALL64pcrel32 texternalsym:$dst)>;
1155 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1156 (CALL64pcrel32 tglobaladdr:$dst)>;
1157 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1158 (CALL64pcrel32 texternalsym:$dst)>;
1160 def : Pat<(X86tailcall GR64:$dst),
1161 (CALL64r GR64:$dst)>;
1165 def : Pat<(X86tailcall GR32:$dst),
1167 def : Pat<(X86tailcall (i64 tglobaladdr:$dst)),
1169 def : Pat<(X86tailcall (i64 texternalsym:$dst)),
1172 def : Pat<(X86tcret GR64:$dst, imm:$off),
1173 (TCRETURNri64 GR64:$dst, imm:$off)>;
1175 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1176 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1178 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1179 (TCRETURNdi64 texternalsym:$dst, imm:$off)>;
1183 // TEST R,R is smaller than CMP R,0
1184 def : Pat<(parallel (X86cmp GR64:$src1, 0), (implicit EFLAGS)),
1185 (TEST64rr GR64:$src1, GR64:$src1)>;
1187 // {s|z}extload bool -> {s|z}extload byte
1188 def : Pat<(sextloadi64i1 addr:$src), (MOVSX64rm8 addr:$src)>;
1189 def : Pat<(zextloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1192 def : Pat<(extloadi64i1 addr:$src), (MOVZX64rm8 addr:$src)>;
1193 def : Pat<(extloadi64i8 addr:$src), (MOVZX64rm8 addr:$src)>;
1194 def : Pat<(extloadi64i16 addr:$src), (MOVZX64rm16 addr:$src)>;
1195 def : Pat<(extloadi64i32 addr:$src), (PsMOVZX64rm32 addr:$src)>;
1198 def : Pat<(i64 (anyext GR8 :$src)), (MOVZX64rr8 GR8 :$src)>;
1199 def : Pat<(i64 (anyext GR16:$src)), (MOVZX64rr16 GR16:$src)>;
1200 def : Pat<(i64 (anyext GR32:$src)), (PsMOVZX64rr32 GR32:$src)>;
1201 def : Pat<(i64 (anyext (loadi8 addr:$src))), (MOVZX64rm8 addr:$src)>;
1202 def : Pat<(i64 (anyext (loadi16 addr:$src))), (MOVZX64rm16 addr:$src)>;
1203 def : Pat<(i64 (anyext (loadi32 addr:$src))), (PsMOVZX64rm32 addr:$src)>;
1205 //===----------------------------------------------------------------------===//
1207 //===----------------------------------------------------------------------===//
1209 // (shl x, 1) ==> (add x, x)
1210 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1212 // (or (x >> c) | (y << (64 - c))) ==> (shrd64 x, y, c)
1213 def : Pat<(or (srl GR64:$src1, CL:$amt),
1214 (shl GR64:$src2, (sub 64, CL:$amt))),
1215 (SHRD64rrCL GR64:$src1, GR64:$src2)>;
1217 def : Pat<(store (or (srl (loadi64 addr:$dst), CL:$amt),
1218 (shl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1219 (SHRD64mrCL addr:$dst, GR64:$src2)>;
1221 // (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c)
1222 def : Pat<(or (shl GR64:$src1, CL:$amt),
1223 (srl GR64:$src2, (sub 64, CL:$amt))),
1224 (SHLD64rrCL GR64:$src1, GR64:$src2)>;
1226 def : Pat<(store (or (shl (loadi64 addr:$dst), CL:$amt),
1227 (srl GR64:$src2, (sub 64, CL:$amt))), addr:$dst),
1228 (SHLD64mrCL addr:$dst, GR64:$src2)>;
1230 // X86 specific add which produces a flag.
1231 def : Pat<(addc GR64:$src1, GR64:$src2),
1232 (ADD64rr GR64:$src1, GR64:$src2)>;
1233 def : Pat<(addc GR64:$src1, (load addr:$src2)),
1234 (ADD64rm GR64:$src1, addr:$src2)>;
1235 def : Pat<(addc GR64:$src1, i64immSExt32:$src2),
1236 (ADD64ri32 GR64:$src1, imm:$src2)>;
1237 def : Pat<(addc GR64:$src1, i64immSExt8:$src2),
1238 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1240 def : Pat<(subc GR64:$src1, GR64:$src2),
1241 (SUB64rr GR64:$src1, GR64:$src2)>;
1242 def : Pat<(subc GR64:$src1, (load addr:$src2)),
1243 (SUB64rm GR64:$src1, addr:$src2)>;
1244 def : Pat<(subc GR64:$src1, imm:$src2),
1245 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1246 def : Pat<(subc GR64:$src1, i64immSExt8:$src2),
1247 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1250 //===----------------------------------------------------------------------===//
1251 // X86-64 SSE Instructions
1252 //===----------------------------------------------------------------------===//
1254 // Move instructions...
1256 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
1257 "mov{d|q}\t{$src, $dst|$dst, $src}",
1259 (v2i64 (scalar_to_vector GR64:$src)))]>;
1260 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
1261 "mov{d|q}\t{$src, $dst|$dst, $src}",
1262 [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
1265 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1266 "mov{d|q}\t{$src, $dst|$dst, $src}",
1267 [(set FR64:$dst, (bitconvert GR64:$src))]>;
1268 def MOV64toSDrm : RPDI<0x6E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
1269 "mov{d|q}\t{$src, $dst|$dst, $src}",
1270 [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
1272 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1273 "mov{d|q}\t{$src, $dst|$dst, $src}",
1274 [(set GR64:$dst, (bitconvert FR64:$src))]>;
1275 def MOVSDto64mr : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1276 "mov{d|q}\t{$src, $dst|$dst, $src}",
1277 [(store (i64 (bitconvert FR64:$src)), addr:$dst)]>;