1 //===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes XOP (eXtended OPerations)
12 //===----------------------------------------------------------------------===//
14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
17 [(set VR128:$dst, (Int VR128:$src))]>, VEX;
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
23 let isAsmParserOnly = 1 in {
24 defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, memopv2i64>;
25 defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, memopv2i64>;
26 defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, memopv2i64>;
27 defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, memopv2i64>;
28 defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, memopv2i64>;
29 defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, memopv2i64>;
30 defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, memopv2i64>;
31 defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, memopv2i64>;
32 defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, memopv2i64>;
33 defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, memopv2i64>;
34 defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, memopv2i64>;
35 defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, memopv2i64>;
36 defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, memopv2i64>;
37 defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, memopv2i64>;
38 defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, memopv2i64>;
41 // Scalar load 2 addr operand instructions
42 let Constraints = "$src1 = $dst" in {
43 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
44 Operand memop, ComplexPattern mem_cpat> {
45 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1,
47 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
48 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX;
49 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1,
51 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
52 [(set VR128:$dst, (Int VR128:$src1,
53 (bitconvert mem_cpat:$src2)))]>, VEX;
56 } // Constraints = "$src1 = $dst"
58 let isAsmParserOnly = 1 in {
59 defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
61 defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
65 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
67 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
68 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
69 [(set VR128:$dst, (Int VR128:$src))]>, VEX;
70 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
71 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
72 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
75 let isAsmParserOnly = 1 in {
76 defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, memopv4f32>;
77 defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, memopv2f64>;
80 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
82 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
83 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
84 [(set VR256:$dst, (Int VR256:$src))]>, VEX;
85 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
86 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
87 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, VEX;
90 let isAsmParserOnly = 1 in {
91 defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256,
93 defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256,
97 multiclass xop3op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
98 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
99 (ins VR128:$src1, VR128:$src2),
100 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
101 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, VEX_4VOp3;
102 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
106 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2))))]>,
108 def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
109 (ins i128mem:$src1, VR128:$src2),
110 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
112 (Int (bitconvert (memopv2i64 addr:$src1)), VR128:$src2))]>,
116 let isAsmParserOnly = 1 in {
117 defm VPSHLW : xop3op<0x95, "vpshlw", int_x86_xop_vpshlw>;
118 defm VPSHLQ : xop3op<0x97, "vpshlq", int_x86_xop_vpshlq>;
119 defm VPSHLD : xop3op<0x96, "vpshld", int_x86_xop_vpshld>;
120 defm VPSHLB : xop3op<0x94, "vpshlb", int_x86_xop_vpshlb>;
121 defm VPSHAW : xop3op<0x99, "vpshaw", int_x86_xop_vpshaw>;
122 defm VPSHAQ : xop3op<0x9B, "vpshaq", int_x86_xop_vpshaq>;
123 defm VPSHAD : xop3op<0x9A, "vpshad", int_x86_xop_vpshad>;
124 defm VPSHAB : xop3op<0x98, "vpshab", int_x86_xop_vpshab>;
125 defm VPROTW : xop3op<0x91, "vprotw", int_x86_xop_vprotw>;
126 defm VPROTQ : xop3op<0x93, "vprotq", int_x86_xop_vprotq>;
127 defm VPROTD : xop3op<0x92, "vprotd", int_x86_xop_vprotd>;
128 defm VPROTB : xop3op<0x90, "vprotb", int_x86_xop_vprotb>;
131 multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
132 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
133 (ins VR128:$src1, i8imm:$src2),
134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
135 [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, VEX;
136 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
137 (ins i128mem:$src1, i8imm:$src2),
138 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
140 (Int (bitconvert (memopv2i64 addr:$src1)), imm:$src2))]>, VEX;
143 let isAsmParserOnly = 1 in {
144 defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
145 defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
146 defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
147 defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
150 // Instruction where second source can be memory, but third must be register
151 multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
152 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
153 (ins VR128:$src1, VR128:$src2, VR128:$src3),
154 !strconcat(OpcodeStr,
155 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
157 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, VEX_4V, VEX_I8IMM;
158 def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
159 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
160 !strconcat(OpcodeStr,
161 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
163 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
164 VR128:$src3))]>, VEX_4V, VEX_I8IMM;
167 let isAsmParserOnly = 1 in {
168 defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
169 defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
170 defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
171 defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
172 defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
173 defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
174 defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
175 defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
176 defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
177 defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
178 defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
179 defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
182 // Instruction where second source can be memory, third must be imm8
183 multiclass xop4opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
184 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
185 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
186 !strconcat(OpcodeStr,
187 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
188 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, imm:$src3))]>,
190 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
191 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
192 !strconcat(OpcodeStr,
193 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
195 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
196 imm:$src3))]>, VEX_4V;
199 let isAsmParserOnly = 1 in {
200 defm VPCOMB : xop4opimm<0xCC, "vpcomb", int_x86_xop_vpcomb>;
201 defm VPCOMW : xop4opimm<0xCD, "vpcomw", int_x86_xop_vpcomw>;
202 defm VPCOMD : xop4opimm<0xCE, "vpcomd", int_x86_xop_vpcomd>;
203 defm VPCOMQ : xop4opimm<0xCF, "vpcomq", int_x86_xop_vpcomq>;
204 defm VPCOMUB : xop4opimm<0xEC, "vpcomub", int_x86_xop_vpcomub>;
205 defm VPCOMUW : xop4opimm<0xED, "vpcomuw", int_x86_xop_vpcomuw>;
206 defm VPCOMUD : xop4opimm<0xEE, "vpcomud", int_x86_xop_vpcomud>;
207 defm VPCOMUQ : xop4opimm<0xEF, "vpcomuq", int_x86_xop_vpcomuq>;
210 // Instruction where either second or third source can be memory
211 multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
212 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
213 (ins VR128:$src1, VR128:$src2, VR128:$src3),
214 !strconcat(OpcodeStr,
215 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
216 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
218 def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
219 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
220 !strconcat(OpcodeStr,
221 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
223 (Int VR128:$src1, VR128:$src2,
224 (bitconvert (memopv2i64 addr:$src3))))]>,
225 VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
226 def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
227 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
228 !strconcat(OpcodeStr,
229 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
231 (Int VR128:$src1, (bitconvert (memopv2i64 addr:$src2)),
236 let isAsmParserOnly = 1 in {
237 defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
238 defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
241 multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
242 def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
243 (ins VR256:$src1, VR256:$src2, VR256:$src3),
244 !strconcat(OpcodeStr,
245 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
246 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
248 def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
249 (ins VR256:$src1, VR256:$src2, i256mem:$src3),
250 !strconcat(OpcodeStr,
251 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
253 (Int VR256:$src1, VR256:$src2,
254 (bitconvert (memopv4i64 addr:$src3))))]>,
255 VEX_4V, VEX_I8IMM, VEX_W, MemOp4;
256 def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
257 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
258 !strconcat(OpcodeStr,
259 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
261 (Int VR256:$src1, (bitconvert (memopv4i64 addr:$src2)),
266 let isAsmParserOnly = 1 in {
267 defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
270 multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
271 Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
272 def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
273 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
274 !strconcat(OpcodeStr,
275 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
277 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
278 def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
279 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
280 !strconcat(OpcodeStr,
281 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
283 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
285 def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
286 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
287 !strconcat(OpcodeStr,
288 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
290 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
291 def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
292 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
293 !strconcat(OpcodeStr,
294 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
296 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>;
297 def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
298 (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
299 !strconcat(OpcodeStr,
300 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
302 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
304 def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
305 (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
306 !strconcat(OpcodeStr,
307 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
309 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>;
312 defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
313 int_x86_xop_vpermil2pd_256, memopv2f64, memopv4f64>;
314 defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
315 int_x86_xop_vpermil2ps_256, memopv4f32, memopv8f32>;