1 //===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes XOP (eXtended OPerations)
12 //===----------------------------------------------------------------------===//
14 multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
15 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
16 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
17 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
18 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
19 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
20 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
23 let ExeDomain = SSEPackedInt in {
24 defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>;
25 defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>;
26 defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>;
27 defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>;
28 defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>;
29 defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>;
30 defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>;
31 defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>;
32 defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>;
33 defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>;
34 defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>;
35 defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>;
36 defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>;
37 defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>;
38 defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>;
41 // Scalar load 2 addr operand instructions
42 multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
43 Operand memop, ComplexPattern mem_cpat> {
44 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
45 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
46 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
47 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
48 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
49 [(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
52 multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
54 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
55 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
56 [(set VR128:$dst, (Int VR128:$src))]>, XOP;
57 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
58 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
59 [(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
62 multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
64 def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
65 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
66 [(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
67 def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
68 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
69 [(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
72 let ExeDomain = SSEPackedSingle in {
73 defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
75 defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>;
76 defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>;
79 let ExeDomain = SSEPackedDouble in {
80 defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
82 defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>;
83 defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>;
86 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
88 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
89 (ins VR128:$src1, VR128:$src2),
90 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
92 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
93 XOP_4VOp3, Sched<[WriteVarVecShift]>;
94 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
95 (ins VR128:$src1, i128mem:$src2),
96 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
98 (vt128 (OpNode (vt128 VR128:$src1),
99 (vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
100 XOP_4V, VEX_W, Sched<[WriteVarVecShift, ReadAfterLd]>;
101 def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
102 (ins i128mem:$src1, VR128:$src2),
103 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
105 (vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
106 (vt128 VR128:$src2))))]>,
107 XOP_4VOp3, Sched<[WriteVarVecShift, ReadAfterLd]>;
110 let ExeDomain = SSEPackedInt in {
111 defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>;
112 defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>;
113 defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>;
114 defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>;
115 defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>;
116 defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>;
117 defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>;
118 defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>;
121 multiclass xop3op_int<bits<8> opc, string OpcodeStr, Intrinsic Int> {
122 def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
123 (ins VR128:$src1, VR128:$src2),
124 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
125 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2))]>, XOP_4VOp3;
126 def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
127 (ins VR128:$src1, i128mem:$src2),
128 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
130 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2))))]>,
132 def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
133 (ins i128mem:$src1, VR128:$src2),
134 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
136 (Int (bitconvert (loadv2i64 addr:$src1)), VR128:$src2))]>,
140 let ExeDomain = SSEPackedInt in {
141 defm VPROTW : xop3op_int<0x91, "vprotw", int_x86_xop_vprotw>;
142 defm VPROTQ : xop3op_int<0x93, "vprotq", int_x86_xop_vprotq>;
143 defm VPROTD : xop3op_int<0x92, "vprotd", int_x86_xop_vprotd>;
144 defm VPROTB : xop3op_int<0x90, "vprotb", int_x86_xop_vprotb>;
147 multiclass xop3opimm<bits<8> opc, string OpcodeStr, Intrinsic Int> {
148 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
149 (ins VR128:$src1, i8imm:$src2),
150 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
151 [(set VR128:$dst, (Int VR128:$src1, imm:$src2))]>, XOP;
152 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
153 (ins i128mem:$src1, i8imm:$src2),
154 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
156 (Int (bitconvert (loadv2i64 addr:$src1)), imm:$src2))]>, XOP;
159 let ExeDomain = SSEPackedInt in {
160 defm VPROTW : xop3opimm<0xC1, "vprotw", int_x86_xop_vprotwi>;
161 defm VPROTQ : xop3opimm<0xC3, "vprotq", int_x86_xop_vprotqi>;
162 defm VPROTD : xop3opimm<0xC2, "vprotd", int_x86_xop_vprotdi>;
163 defm VPROTB : xop3opimm<0xC0, "vprotb", int_x86_xop_vprotbi>;
166 // Instruction where second source can be memory, but third must be register
167 multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
168 let isCommutable = 1 in
169 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
170 (ins VR128:$src1, VR128:$src2, VR128:$src3),
171 !strconcat(OpcodeStr,
172 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
174 (Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
175 def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
176 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
177 !strconcat(OpcodeStr,
178 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
180 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
181 VR128:$src3))]>, XOP_4V, VEX_I8IMM;
184 let ExeDomain = SSEPackedInt in {
185 defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
186 defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
187 defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
188 defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
189 defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
190 defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
191 defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
192 defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
193 defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
194 defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
195 defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
196 defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
199 // Instruction where second source can be memory, third must be imm8
200 multiclass xopvpcom<bits<8> opc, string Suffix, Intrinsic Int> {
201 let isCommutable = 1 in
202 def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
203 (ins VR128:$src1, VR128:$src2, XOPCC:$cc),
204 !strconcat("vpcom${cc}", Suffix,
205 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
206 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, i8immZExt3:$cc))]>,
208 def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
209 (ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
210 !strconcat("vpcom${cc}", Suffix,
211 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
213 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
214 i8immZExt3:$cc))]>, XOP_4V;
215 let isAsmParserOnly = 1, hasSideEffects = 0 in {
216 def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
217 (ins VR128:$src1, VR128:$src2, i8imm:$src3),
218 !strconcat("vpcom", Suffix,
219 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
222 def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
223 (ins VR128:$src1, i128mem:$src2, i8imm:$src3),
224 !strconcat("vpcom", Suffix,
225 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
230 let ExeDomain = SSEPackedInt in { // SSE integer instructions
231 defm VPCOMB : xopvpcom<0xCC, "b", int_x86_xop_vpcomb>;
232 defm VPCOMW : xopvpcom<0xCD, "w", int_x86_xop_vpcomw>;
233 defm VPCOMD : xopvpcom<0xCE, "d", int_x86_xop_vpcomd>;
234 defm VPCOMQ : xopvpcom<0xCF, "q", int_x86_xop_vpcomq>;
235 defm VPCOMUB : xopvpcom<0xEC, "ub", int_x86_xop_vpcomub>;
236 defm VPCOMUW : xopvpcom<0xED, "uw", int_x86_xop_vpcomuw>;
237 defm VPCOMUD : xopvpcom<0xEE, "ud", int_x86_xop_vpcomud>;
238 defm VPCOMUQ : xopvpcom<0xEF, "uq", int_x86_xop_vpcomuq>;
241 // Instruction where either second or third source can be memory
242 multiclass xop4op<bits<8> opc, string OpcodeStr, Intrinsic Int> {
243 def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
244 (ins VR128:$src1, VR128:$src2, VR128:$src3),
245 !strconcat(OpcodeStr,
246 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
247 [(set VR128:$dst, (Int VR128:$src1, VR128:$src2, VR128:$src3))]>,
249 def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
250 (ins VR128:$src1, VR128:$src2, i128mem:$src3),
251 !strconcat(OpcodeStr,
252 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
254 (Int VR128:$src1, VR128:$src2,
255 (bitconvert (loadv2i64 addr:$src3))))]>,
256 XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
257 def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
258 (ins VR128:$src1, i128mem:$src2, VR128:$src3),
259 !strconcat(OpcodeStr,
260 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
262 (Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
267 let ExeDomain = SSEPackedInt in {
268 defm VPPERM : xop4op<0xA3, "vpperm", int_x86_xop_vpperm>;
269 defm VPCMOV : xop4op<0xA2, "vpcmov", int_x86_xop_vpcmov>;
272 multiclass xop4op256<bits<8> opc, string OpcodeStr, Intrinsic Int> {
273 def rrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
274 (ins VR256:$src1, VR256:$src2, VR256:$src3),
275 !strconcat(OpcodeStr,
276 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
277 [(set VR256:$dst, (Int VR256:$src1, VR256:$src2, VR256:$src3))]>,
278 XOP_4V, VEX_I8IMM, VEX_L;
279 def rmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
280 (ins VR256:$src1, VR256:$src2, i256mem:$src3),
281 !strconcat(OpcodeStr,
282 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
284 (Int VR256:$src1, VR256:$src2,
285 (bitconvert (loadv4i64 addr:$src3))))]>,
286 XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
287 def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
288 (ins VR256:$src1, f256mem:$src2, VR256:$src3),
289 !strconcat(OpcodeStr,
290 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
292 (Int VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
294 XOP_4V, VEX_I8IMM, VEX_L;
297 let ExeDomain = SSEPackedInt in
298 defm VPCMOV : xop4op256<0xA2, "vpcmov", int_x86_xop_vpcmov_256>;
300 multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
301 Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
302 def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
303 (ins VR128:$src1, VR128:$src2, VR128:$src3, i8imm:$src4),
304 !strconcat(OpcodeStr,
305 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
307 (Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
308 def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
309 (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4),
310 !strconcat(OpcodeStr,
311 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
313 (Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
315 def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
316 (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4),
317 !strconcat(OpcodeStr,
318 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
320 (Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
321 def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
322 (ins VR256:$src1, VR256:$src2, VR256:$src3, i8imm:$src4),
323 !strconcat(OpcodeStr,
324 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
326 (Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
327 def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
328 (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4),
329 !strconcat(OpcodeStr,
330 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
332 (Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
333 VEX_W, MemOp4, VEX_L;
334 def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
335 (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4),
336 !strconcat(OpcodeStr,
337 "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
339 (Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
343 let ExeDomain = SSEPackedDouble in
344 defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
345 int_x86_xop_vpermil2pd_256, loadv2f64, loadv4f64>;
347 let ExeDomain = SSEPackedSingle in
348 defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
349 int_x86_xop_vpermil2ps_256, loadv4f32, loadv8f32>;