1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8 },
47 { "reloc_pcrel_1byte", 0, 1 * 8 },
48 { "reloc_riprel_4byte", 0, 4 * 8 }
51 if (Kind < FirstTargetFixupKind)
52 return MCCodeEmitter::getFixupKindInfo(Kind);
54 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
56 return Infos[Kind - FirstTargetFixupKind];
59 static unsigned GetX86RegNum(const MCOperand &MO) {
60 return X86RegisterInfo::getX86RegNum(MO.getReg());
63 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
68 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
69 raw_ostream &OS) const {
70 // Output the constant in little endian byte order.
71 for (unsigned i = 0; i != Size; ++i) {
72 EmitByte(Val & 255, CurByte, OS);
77 void EmitImmediate(const MCOperand &Disp,
78 unsigned ImmSize, MCFixupKind FixupKind,
79 unsigned &CurByte, raw_ostream &OS,
80 SmallVectorImpl<MCFixup> &Fixups,
81 int ImmOffset = 0) const;
83 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
85 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
86 return RM | (RegOpcode << 3) | (Mod << 6);
89 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
90 unsigned &CurByte, raw_ostream &OS) const {
91 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
94 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
95 unsigned &CurByte, raw_ostream &OS) const {
96 // SIB byte is in the same format as the ModRMByte.
97 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
101 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
102 unsigned RegOpcodeField,
103 unsigned TSFlags, unsigned &CurByte, raw_ostream &OS,
104 SmallVectorImpl<MCFixup> &Fixups) const;
106 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
107 SmallVectorImpl<MCFixup> &Fixups) const;
111 } // end anonymous namespace
114 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
117 return new X86MCCodeEmitter(TM, Ctx, false);
120 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
123 return new X86MCCodeEmitter(TM, Ctx, true);
127 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
128 /// sign-extended field.
129 static bool isDisp8(int Value) {
130 return Value == (signed char)Value;
133 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
134 /// in an instruction with the specified TSFlags.
135 static MCFixupKind getImmFixupKind(unsigned TSFlags) {
136 unsigned Size = X86II::getSizeOfImm(TSFlags);
137 bool isPCRel = X86II::isImmPCRel(TSFlags);
140 default: assert(0 && "Unknown immediate size");
141 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
142 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
143 case 2: assert(!isPCRel); return FK_Data_2;
144 case 8: assert(!isPCRel); return FK_Data_8;
149 void X86MCCodeEmitter::
150 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
151 unsigned &CurByte, raw_ostream &OS,
152 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
153 // If this is a simple integer displacement that doesn't require a relocation,
155 if (DispOp.isImm()) {
156 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
158 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
162 // If we have an immoffset, add it to the expression.
163 const MCExpr *Expr = DispOp.getExpr();
165 // If the fixup is pc-relative, we need to bias the value to be relative to
166 // the start of the field, not the end of the field.
167 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
168 FixupKind == MCFixupKind(X86::reloc_riprel_4byte))
170 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
174 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
177 // Emit a symbolic constant as a fixup and 4 zeros.
178 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
179 EmitConstant(0, Size, CurByte, OS);
183 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
184 unsigned RegOpcodeField,
185 unsigned TSFlags, unsigned &CurByte,
187 SmallVectorImpl<MCFixup> &Fixups) const{
188 const MCOperand &Disp = MI.getOperand(Op+3);
189 const MCOperand &Base = MI.getOperand(Op);
190 const MCOperand &Scale = MI.getOperand(Op+1);
191 const MCOperand &IndexReg = MI.getOperand(Op+2);
192 unsigned BaseReg = Base.getReg();
194 // Handle %rip relative addressing.
195 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
196 assert(IndexReg.getReg() == 0 && Is64BitMode &&
197 "Invalid rip-relative address");
198 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
200 // rip-relative addressing is actually relative to the *next* instruction.
201 // Since an immediate can follow the mod/rm byte for an instruction, this
202 // means that we need to bias the immediate field of the instruction with
203 // the size of the immediate field. If we have this case, add it into the
204 // expression to emit.
205 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
207 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_riprel_4byte),
208 CurByte, OS, Fixups, -ImmSize);
212 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
214 // Determine whether a SIB byte is needed.
215 // If no BaseReg, issue a RIP relative instruction only if the MCE can
216 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
217 // 2-7) and absolute references.
219 if (// The SIB byte must be used if there is an index register.
220 IndexReg.getReg() == 0 &&
221 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
222 // encode to an R/M value of 4, which indicates that a SIB byte is
224 BaseRegNo != N86::ESP &&
225 // If there is no base register and we're in 64-bit mode, we need a SIB
226 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
227 (!Is64BitMode || BaseReg != 0)) {
229 if (BaseReg == 0) { // [disp32] in X86-32 mode
230 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
231 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
235 // If the base is not EBP/ESP and there is no displacement, use simple
236 // indirect register encoding, this handles addresses like [EAX]. The
237 // encoding for [EBP] with no displacement means [disp32] so we handle it
238 // by emitting a displacement of 0 below.
239 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
240 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
244 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
245 if (Disp.isImm() && isDisp8(Disp.getImm())) {
246 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
247 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
251 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
252 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
253 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
257 // We need a SIB byte, so start by outputting the ModR/M byte first
258 assert(IndexReg.getReg() != X86::ESP &&
259 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
261 bool ForceDisp32 = false;
262 bool ForceDisp8 = false;
264 // If there is no base register, we emit the special case SIB byte with
265 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
266 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
268 } else if (!Disp.isImm()) {
269 // Emit the normal disp32 encoding.
270 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
272 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
273 // Emit no displacement ModR/M byte
274 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
275 } else if (isDisp8(Disp.getImm())) {
276 // Emit the disp8 encoding.
277 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
278 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
280 // Emit the normal disp32 encoding.
281 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
284 // Calculate what the SS field value should be...
285 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
286 unsigned SS = SSTable[Scale.getImm()];
289 // Handle the SIB byte for the case where there is no base, see Intel
290 // Manual 2A, table 2-7. The displacement has already been output.
292 if (IndexReg.getReg())
293 IndexRegNo = GetX86RegNum(IndexReg);
294 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
296 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
299 if (IndexReg.getReg())
300 IndexRegNo = GetX86RegNum(IndexReg);
302 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
303 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
306 // Do we need to output a displacement?
308 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
309 else if (ForceDisp32 || Disp.getImm() != 0)
310 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
313 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
314 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
315 /// size, and 3) use of X86-64 extended registers.
316 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
317 const TargetInstrDesc &Desc) {
318 // Pseudo instructions never have a rex byte.
319 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
323 if (TSFlags & X86II::REX_W)
326 if (MI.getNumOperands() == 0) return REX;
328 unsigned NumOps = MI.getNumOperands();
329 // FIXME: MCInst should explicitize the two-addrness.
330 bool isTwoAddr = NumOps > 1 &&
331 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
333 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
334 unsigned i = isTwoAddr ? 1 : 0;
335 for (; i != NumOps; ++i) {
336 const MCOperand &MO = MI.getOperand(i);
337 if (!MO.isReg()) continue;
338 unsigned Reg = MO.getReg();
339 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
340 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
341 // that returns non-zero.
346 switch (TSFlags & X86II::FormMask) {
347 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
348 case X86II::MRMSrcReg:
349 if (MI.getOperand(0).isReg() &&
350 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
352 i = isTwoAddr ? 2 : 1;
353 for (; i != NumOps; ++i) {
354 const MCOperand &MO = MI.getOperand(i);
355 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
359 case X86II::MRMSrcMem: {
360 if (MI.getOperand(0).isReg() &&
361 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
364 i = isTwoAddr ? 2 : 1;
365 for (; i != NumOps; ++i) {
366 const MCOperand &MO = MI.getOperand(i);
368 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
375 case X86II::MRM0m: case X86II::MRM1m:
376 case X86II::MRM2m: case X86II::MRM3m:
377 case X86II::MRM4m: case X86II::MRM5m:
378 case X86II::MRM6m: case X86II::MRM7m:
379 case X86II::MRMDestMem: {
380 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
381 i = isTwoAddr ? 1 : 0;
382 if (NumOps > e && MI.getOperand(e).isReg() &&
383 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
386 for (; i != e; ++i) {
387 const MCOperand &MO = MI.getOperand(i);
389 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
397 if (MI.getOperand(0).isReg() &&
398 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
400 i = isTwoAddr ? 2 : 1;
401 for (unsigned e = NumOps; i != e; ++i) {
402 const MCOperand &MO = MI.getOperand(i);
403 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
411 void X86MCCodeEmitter::
412 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
413 SmallVectorImpl<MCFixup> &Fixups) const {
414 unsigned Opcode = MI.getOpcode();
415 const TargetInstrDesc &Desc = TII.get(Opcode);
416 unsigned TSFlags = Desc.TSFlags;
418 // Keep track of the current byte being emitted.
419 unsigned CurByte = 0;
421 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
422 // in order to provide diffability.
424 // Emit the lock opcode prefix as needed.
425 if (TSFlags & X86II::LOCK)
426 EmitByte(0xF0, CurByte, OS);
428 // Emit segment override opcode prefix as needed.
429 switch (TSFlags & X86II::SegOvrMask) {
430 default: assert(0 && "Invalid segment!");
431 case 0: break; // No segment override!
433 EmitByte(0x64, CurByte, OS);
436 EmitByte(0x65, CurByte, OS);
440 // Emit the repeat opcode prefix as needed.
441 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
442 EmitByte(0xF3, CurByte, OS);
444 // Emit the operand size opcode prefix as needed.
445 if (TSFlags & X86II::OpSize)
446 EmitByte(0x66, CurByte, OS);
448 // Emit the address size opcode prefix as needed.
449 if (TSFlags & X86II::AdSize)
450 EmitByte(0x67, CurByte, OS);
452 bool Need0FPrefix = false;
453 switch (TSFlags & X86II::Op0Mask) {
454 default: assert(0 && "Invalid prefix!");
455 case 0: break; // No prefix!
456 case X86II::REP: break; // already handled.
457 case X86II::TB: // Two-byte opcode prefix
458 case X86II::T8: // 0F 38
459 case X86II::TA: // 0F 3A
462 case X86II::TF: // F2 0F 38
463 EmitByte(0xF2, CurByte, OS);
466 case X86II::XS: // F3 0F
467 EmitByte(0xF3, CurByte, OS);
470 case X86II::XD: // F2 0F
471 EmitByte(0xF2, CurByte, OS);
474 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
475 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
476 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
477 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
478 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
479 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
480 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
481 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
484 // Handle REX prefix.
485 // FIXME: Can this come before F2 etc to simplify emission?
487 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
488 EmitByte(0x40 | REX, CurByte, OS);
491 // 0x0F escape code must be emitted just before the opcode.
493 EmitByte(0x0F, CurByte, OS);
495 // FIXME: Pull this up into previous switch if REX can be moved earlier.
496 switch (TSFlags & X86II::Op0Mask) {
497 case X86II::TF: // F2 0F 38
498 case X86II::T8: // 0F 38
499 EmitByte(0x38, CurByte, OS);
501 case X86II::TA: // 0F 3A
502 EmitByte(0x3A, CurByte, OS);
506 // If this is a two-address instruction, skip one of the register operands.
507 unsigned NumOps = Desc.getNumOperands();
509 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
511 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
512 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
515 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
516 switch (TSFlags & X86II::FormMask) {
517 case X86II::MRMInitReg:
518 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
519 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
520 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
521 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
523 EmitByte(BaseOpcode, CurByte, OS);
526 case X86II::AddRegFrm:
527 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
530 case X86II::MRMDestReg:
531 EmitByte(BaseOpcode, CurByte, OS);
532 EmitRegModRMByte(MI.getOperand(CurOp),
533 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
537 case X86II::MRMDestMem:
538 EmitByte(BaseOpcode, CurByte, OS);
539 EmitMemModRMByte(MI, CurOp,
540 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
541 TSFlags, CurByte, OS, Fixups);
542 CurOp += X86AddrNumOperands + 1;
545 case X86II::MRMSrcReg:
546 EmitByte(BaseOpcode, CurByte, OS);
547 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
552 case X86II::MRMSrcMem: {
553 EmitByte(BaseOpcode, CurByte, OS);
555 // FIXME: Maybe lea should have its own form? This is a horrible hack.
557 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
558 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
559 AddrOperands = X86AddrNumOperands - 1; // No segment register
561 AddrOperands = X86AddrNumOperands;
563 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
564 TSFlags, CurByte, OS, Fixups);
565 CurOp += AddrOperands + 1;
569 case X86II::MRM0r: case X86II::MRM1r:
570 case X86II::MRM2r: case X86II::MRM3r:
571 case X86II::MRM4r: case X86II::MRM5r:
572 case X86II::MRM6r: case X86II::MRM7r:
573 EmitByte(BaseOpcode, CurByte, OS);
574 EmitRegModRMByte(MI.getOperand(CurOp++),
575 (TSFlags & X86II::FormMask)-X86II::MRM0r,
578 case X86II::MRM0m: case X86II::MRM1m:
579 case X86II::MRM2m: case X86II::MRM3m:
580 case X86II::MRM4m: case X86II::MRM5m:
581 case X86II::MRM6m: case X86II::MRM7m:
582 EmitByte(BaseOpcode, CurByte, OS);
583 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
584 TSFlags, CurByte, OS, Fixups);
585 CurOp += X86AddrNumOperands;
588 EmitByte(BaseOpcode, CurByte, OS);
589 EmitByte(0xC1, CurByte, OS);
592 EmitByte(BaseOpcode, CurByte, OS);
593 EmitByte(0xC2, CurByte, OS);
596 EmitByte(BaseOpcode, CurByte, OS);
597 EmitByte(0xC3, CurByte, OS);
600 EmitByte(BaseOpcode, CurByte, OS);
601 EmitByte(0xC4, CurByte, OS);
604 EmitByte(BaseOpcode, CurByte, OS);
605 EmitByte(0xC8, CurByte, OS);
608 EmitByte(BaseOpcode, CurByte, OS);
609 EmitByte(0xC9, CurByte, OS);
612 EmitByte(BaseOpcode, CurByte, OS);
613 EmitByte(0xE8, CurByte, OS);
616 EmitByte(BaseOpcode, CurByte, OS);
617 EmitByte(0xF0, CurByte, OS);
620 EmitByte(BaseOpcode, CurByte, OS);
621 EmitByte(0xF8, CurByte, OS);
624 EmitByte(BaseOpcode, CurByte, OS);
625 EmitByte(0xF9, CurByte, OS);
629 // If there is a remaining operand, it must be a trailing immediate. Emit it
630 // according to the right size for the instruction.
632 EmitImmediate(MI.getOperand(CurOp++),
633 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
634 CurByte, OS, Fixups);
638 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
639 errs() << "Cannot encode all operands of: ";