1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/raw_ostream.h"
26 class X86MCCodeEmitter : public MCCodeEmitter {
27 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
29 const TargetMachine &TM;
30 const TargetInstrInfo &TII;
34 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
35 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
36 Is64BitMode = is64Bit;
39 ~X86MCCodeEmitter() {}
41 unsigned getNumFixupKinds() const {
45 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
46 const static MCFixupKindInfo Infos[] = {
47 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel },
50 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
52 { "reloc_signed_4byte", 0, 4 * 8, 0}
55 if (Kind < FirstTargetFixupKind)
56 return MCCodeEmitter::getFixupKindInfo(Kind);
58 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
60 return Infos[Kind - FirstTargetFixupKind];
63 static unsigned GetX86RegNum(const MCOperand &MO) {
64 return X86RegisterInfo::getX86RegNum(MO.getReg());
67 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
68 // 0-7 and the difference between the 2 groups is given by the REX prefix.
69 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
70 // in 1's complement form, example:
72 // ModRM field => XMM9 => 1
73 // VEX.VVVV => XMM9 => ~9
75 // See table 4-35 of Intel AVX Programming Reference for details.
76 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
78 unsigned SrcReg = MI.getOperand(OpNum).getReg();
79 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
80 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
81 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
84 // The registers represented through VEX_VVVV should
85 // be encoded in 1's complement form.
86 return (~SrcRegNum) & 0xf;
89 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
94 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
95 raw_ostream &OS) const {
96 // Output the constant in little endian byte order.
97 for (unsigned i = 0; i != Size; ++i) {
98 EmitByte(Val & 255, CurByte, OS);
103 void EmitImmediate(const MCOperand &Disp,
104 unsigned ImmSize, MCFixupKind FixupKind,
105 unsigned &CurByte, raw_ostream &OS,
106 SmallVectorImpl<MCFixup> &Fixups,
107 int ImmOffset = 0) const;
109 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
111 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
112 return RM | (RegOpcode << 3) | (Mod << 6);
115 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
116 unsigned &CurByte, raw_ostream &OS) const {
117 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
120 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
121 unsigned &CurByte, raw_ostream &OS) const {
122 // SIB byte is in the same format as the ModRMByte.
123 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
127 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
128 unsigned RegOpcodeField,
129 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
130 SmallVectorImpl<MCFixup> &Fixups) const;
132 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
133 SmallVectorImpl<MCFixup> &Fixups) const;
135 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
136 const MCInst &MI, const TargetInstrDesc &Desc,
137 raw_ostream &OS) const;
139 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
140 int MemOperand, const MCInst &MI,
141 raw_ostream &OS) const;
143 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
144 const MCInst &MI, const TargetInstrDesc &Desc,
145 raw_ostream &OS) const;
148 } // end anonymous namespace
151 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
154 return new X86MCCodeEmitter(TM, Ctx, false);
157 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
160 return new X86MCCodeEmitter(TM, Ctx, true);
163 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
164 /// sign-extended field.
165 static bool isDisp8(int Value) {
166 return Value == (signed char)Value;
169 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
170 /// in an instruction with the specified TSFlags.
171 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
172 unsigned Size = X86II::getSizeOfImm(TSFlags);
173 bool isPCRel = X86II::isImmPCRel(TSFlags);
176 default: assert(0 && "Unknown immediate size");
177 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
178 case 2: return isPCRel ? MCFixupKind(X86::reloc_pcrel_2byte) : FK_Data_2;
179 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
180 case 8: assert(!isPCRel); return FK_Data_8;
184 /// Is32BitMemOperand - Return true if the specified instruction with a memory
185 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
186 /// memory operand. Op specifies the operand # of the memoperand.
187 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
188 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
189 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
191 if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) ||
192 (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg())))
197 /// StartsWithGlobalOffsetTable - Return true for the simple cases where this
198 /// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
199 /// PIC on ELF i386 as that symbol is magic. We check only simple case that
200 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
201 /// of a binary expression.
202 static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
203 if (Expr->getKind() == MCExpr::Binary) {
204 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
208 if (Expr->getKind() != MCExpr::SymbolRef)
211 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
212 const MCSymbol &S = Ref->getSymbol();
213 return S.getName() == "_GLOBAL_OFFSET_TABLE_";
216 void X86MCCodeEmitter::
217 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
218 unsigned &CurByte, raw_ostream &OS,
219 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
220 // If this is a simple integer displacement that doesn't require a relocation,
222 if (DispOp.isImm()) {
223 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
225 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
229 // If we have an immoffset, add it to the expression.
230 const MCExpr *Expr = DispOp.getExpr();
232 if (StartsWithGlobalOffsetTable(Expr)) {
233 // FIXME: We should probably change the FixupKind to a special one so that
234 // other parts of MC don't have to check the symbol name.
235 assert(ImmOffset == 0);
239 // If the fixup is pc-relative, we need to bias the value to be relative to
240 // the start of the field, not the end of the field.
241 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
242 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
243 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
245 if (FixupKind == MCFixupKind(X86::reloc_pcrel_2byte))
247 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
251 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
254 // Emit a symbolic constant as a fixup and 4 zeros.
255 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
256 EmitConstant(0, Size, CurByte, OS);
259 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
260 unsigned RegOpcodeField,
261 uint64_t TSFlags, unsigned &CurByte,
263 SmallVectorImpl<MCFixup> &Fixups) const{
264 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
265 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
266 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
267 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
268 unsigned BaseReg = Base.getReg();
270 // Handle %rip relative addressing.
271 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
272 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
273 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
274 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
276 unsigned FixupKind = X86::reloc_riprel_4byte;
278 // movq loads are handled with a special relocation form which allows the
279 // linker to eliminate some loads for GOT references which end up in the
280 // same linkage unit.
281 if (MI.getOpcode() == X86::MOV64rm)
282 FixupKind = X86::reloc_riprel_4byte_movq_load;
284 // rip-relative addressing is actually relative to the *next* instruction.
285 // Since an immediate can follow the mod/rm byte for an instruction, this
286 // means that we need to bias the immediate field of the instruction with
287 // the size of the immediate field. If we have this case, add it into the
288 // expression to emit.
289 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
291 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
292 CurByte, OS, Fixups, -ImmSize);
296 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
298 // Determine whether a SIB byte is needed.
299 // If no BaseReg, issue a RIP relative instruction only if the MCE can
300 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
301 // 2-7) and absolute references.
303 if (// The SIB byte must be used if there is an index register.
304 IndexReg.getReg() == 0 &&
305 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
306 // encode to an R/M value of 4, which indicates that a SIB byte is
308 BaseRegNo != N86::ESP &&
309 // If there is no base register and we're in 64-bit mode, we need a SIB
310 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
311 (!Is64BitMode || BaseReg != 0)) {
313 if (BaseReg == 0) { // [disp32] in X86-32 mode
314 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
315 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
319 // If the base is not EBP/ESP and there is no displacement, use simple
320 // indirect register encoding, this handles addresses like [EAX]. The
321 // encoding for [EBP] with no displacement means [disp32] so we handle it
322 // by emitting a displacement of 0 below.
323 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
324 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
328 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
329 if (Disp.isImm() && isDisp8(Disp.getImm())) {
330 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
331 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
335 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
336 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
337 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
342 // We need a SIB byte, so start by outputting the ModR/M byte first
343 assert(IndexReg.getReg() != X86::ESP &&
344 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
346 bool ForceDisp32 = false;
347 bool ForceDisp8 = false;
349 // If there is no base register, we emit the special case SIB byte with
350 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
351 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
353 } else if (!Disp.isImm()) {
354 // Emit the normal disp32 encoding.
355 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
357 } else if (Disp.getImm() == 0 &&
358 // Base reg can't be anything that ends up with '5' as the base
359 // reg, it is the magic [*] nomenclature that indicates no base.
360 BaseRegNo != N86::EBP) {
361 // Emit no displacement ModR/M byte
362 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
363 } else if (isDisp8(Disp.getImm())) {
364 // Emit the disp8 encoding.
365 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
366 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
368 // Emit the normal disp32 encoding.
369 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
372 // Calculate what the SS field value should be...
373 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
374 unsigned SS = SSTable[Scale.getImm()];
377 // Handle the SIB byte for the case where there is no base, see Intel
378 // Manual 2A, table 2-7. The displacement has already been output.
380 if (IndexReg.getReg())
381 IndexRegNo = GetX86RegNum(IndexReg);
382 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
384 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
387 if (IndexReg.getReg())
388 IndexRegNo = GetX86RegNum(IndexReg);
390 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
391 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
394 // Do we need to output a displacement?
396 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
397 else if (ForceDisp32 || Disp.getImm() != 0)
398 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
402 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
404 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
405 int MemOperand, const MCInst &MI,
406 const TargetInstrDesc &Desc,
407 raw_ostream &OS) const {
408 bool HasVEX_4V = false;
409 if ((TSFlags >> 32) & X86II::VEX_4V)
412 // VEX_R: opcode externsion equivalent to REX.R in
413 // 1's complement (inverted) form
415 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
416 // 0: Same as REX_R=1 (64 bit mode only)
418 unsigned char VEX_R = 0x1;
420 // VEX_X: equivalent to REX.X, only used when a
421 // register is used for index in SIB Byte.
423 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
424 // 0: Same as REX.X=1 (64-bit mode only)
425 unsigned char VEX_X = 0x1;
429 // 1: Same as REX_B=0 (ignored in 32-bit mode)
430 // 0: Same as REX_B=1 (64 bit mode only)
432 unsigned char VEX_B = 0x1;
434 // VEX_W: opcode specific (use like REX.W, or used for
435 // opcode extension, or ignored, depending on the opcode byte)
436 unsigned char VEX_W = 0;
438 // VEX_5M (VEX m-mmmmm field):
440 // 0b00000: Reserved for future use
441 // 0b00001: implied 0F leading opcode
442 // 0b00010: implied 0F 38 leading opcode bytes
443 // 0b00011: implied 0F 3A leading opcode bytes
444 // 0b00100-0b11111: Reserved for future use
446 unsigned char VEX_5M = 0x1;
448 // VEX_4V (VEX vvvv field): a register specifier
449 // (in 1's complement form) or 1111 if unused.
450 unsigned char VEX_4V = 0xf;
452 // VEX_L (Vector Length):
454 // 0: scalar or 128-bit vector
457 unsigned char VEX_L = 0;
459 // VEX_PP: opcode extension providing equivalent
460 // functionality of a SIMD prefix
467 unsigned char VEX_PP = 0;
469 // Encode the operand size opcode prefix as needed.
470 if (TSFlags & X86II::OpSize)
473 if ((TSFlags >> 32) & X86II::VEX_W)
476 if ((TSFlags >> 32) & X86II::VEX_L)
479 switch (TSFlags & X86II::Op0Mask) {
480 default: assert(0 && "Invalid prefix!");
481 case X86II::T8: // 0F 38
484 case X86II::TA: // 0F 3A
487 case X86II::TF: // F2 0F 38
491 case X86II::XS: // F3 0F
494 case X86II::XD: // F2 0F
497 case X86II::TB: // Bypass: Not used by VEX
502 // Set the vector length to 256-bit if YMM0-YMM15 is used
503 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
504 if (!MI.getOperand(i).isReg())
506 unsigned SrcReg = MI.getOperand(i).getReg();
507 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
511 unsigned NumOps = MI.getNumOperands();
513 bool IsDestMem = false;
515 switch (TSFlags & X86II::FormMask) {
516 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
517 case X86II::MRMDestMem:
519 // The important info for the VEX prefix is never beyond the address
520 // registers. Don't check beyond that.
521 NumOps = CurOp = X86::AddrNumOperands;
522 case X86II::MRM0m: case X86II::MRM1m:
523 case X86II::MRM2m: case X86II::MRM3m:
524 case X86II::MRM4m: case X86II::MRM5m:
525 case X86II::MRM6m: case X86II::MRM7m:
526 case X86II::MRMSrcMem:
527 case X86II::MRMSrcReg:
528 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
529 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
534 VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
538 // To only check operands before the memory address ones, start
539 // the search from the begining
543 // If the last register should be encoded in the immediate field
544 // do not use any bit from VEX prefix to this register, ignore it
545 if ((TSFlags >> 32) & X86II::VEX_I8IMM)
548 for (; CurOp != NumOps; ++CurOp) {
549 const MCOperand &MO = MI.getOperand(CurOp);
550 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
552 if (!VEX_B && MO.isReg() &&
553 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
554 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
558 default: // MRMDestReg, MRM0r-MRM7r, RawFrm
559 if (!MI.getNumOperands())
562 if (MI.getOperand(CurOp).isReg() &&
563 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
567 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
570 for (; CurOp != NumOps; ++CurOp) {
571 const MCOperand &MO = MI.getOperand(CurOp);
572 if (MO.isReg() && !HasVEX_4V &&
573 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
579 // Emit segment override opcode prefix as needed.
580 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
582 // VEX opcode prefix can have 2 or 3 bytes
585 // +-----+ +--------------+ +-------------------+
586 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
587 // +-----+ +--------------+ +-------------------+
589 // +-----+ +-------------------+
590 // | C5h | | R | vvvv | L | pp |
591 // +-----+ +-------------------+
593 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
595 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
596 EmitByte(0xC5, CurByte, OS);
597 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
602 EmitByte(0xC4, CurByte, OS);
603 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
604 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
607 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
608 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
609 /// size, and 3) use of X86-64 extended registers.
610 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
611 const TargetInstrDesc &Desc) {
613 if (TSFlags & X86II::REX_W)
614 REX |= 1 << 3; // set REX.W
616 if (MI.getNumOperands() == 0) return REX;
618 unsigned NumOps = MI.getNumOperands();
619 // FIXME: MCInst should explicitize the two-addrness.
620 bool isTwoAddr = NumOps > 1 &&
621 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
623 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
624 unsigned i = isTwoAddr ? 1 : 0;
625 for (; i != NumOps; ++i) {
626 const MCOperand &MO = MI.getOperand(i);
627 if (!MO.isReg()) continue;
628 unsigned Reg = MO.getReg();
629 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
630 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
631 // that returns non-zero.
632 REX |= 0x40; // REX fixed encoding prefix
636 switch (TSFlags & X86II::FormMask) {
637 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
638 case X86II::MRMSrcReg:
639 if (MI.getOperand(0).isReg() &&
640 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
641 REX |= 1 << 2; // set REX.R
642 i = isTwoAddr ? 2 : 1;
643 for (; i != NumOps; ++i) {
644 const MCOperand &MO = MI.getOperand(i);
645 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
646 REX |= 1 << 0; // set REX.B
649 case X86II::MRMSrcMem: {
650 if (MI.getOperand(0).isReg() &&
651 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
652 REX |= 1 << 2; // set REX.R
654 i = isTwoAddr ? 2 : 1;
655 for (; i != NumOps; ++i) {
656 const MCOperand &MO = MI.getOperand(i);
658 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
659 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
665 case X86II::MRM0m: case X86II::MRM1m:
666 case X86II::MRM2m: case X86II::MRM3m:
667 case X86II::MRM4m: case X86II::MRM5m:
668 case X86II::MRM6m: case X86II::MRM7m:
669 case X86II::MRMDestMem: {
670 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
671 i = isTwoAddr ? 1 : 0;
672 if (NumOps > e && MI.getOperand(e).isReg() &&
673 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
674 REX |= 1 << 2; // set REX.R
676 for (; i != e; ++i) {
677 const MCOperand &MO = MI.getOperand(i);
679 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
680 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
687 if (MI.getOperand(0).isReg() &&
688 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
689 REX |= 1 << 0; // set REX.B
690 i = isTwoAddr ? 2 : 1;
691 for (unsigned e = NumOps; i != e; ++i) {
692 const MCOperand &MO = MI.getOperand(i);
693 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
694 REX |= 1 << 2; // set REX.R
701 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
702 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
703 unsigned &CurByte, int MemOperand,
705 raw_ostream &OS) const {
706 switch (TSFlags & X86II::SegOvrMask) {
707 default: assert(0 && "Invalid segment!");
709 // No segment override, check for explicit one on memory operand.
710 if (MemOperand != -1) { // If the instruction has a memory operand.
711 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
712 default: assert(0 && "Unknown segment register!");
714 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
715 case X86::SS: EmitByte(0x36, CurByte, OS); break;
716 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
717 case X86::ES: EmitByte(0x26, CurByte, OS); break;
718 case X86::FS: EmitByte(0x64, CurByte, OS); break;
719 case X86::GS: EmitByte(0x65, CurByte, OS); break;
724 EmitByte(0x64, CurByte, OS);
727 EmitByte(0x65, CurByte, OS);
732 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
734 /// MemOperand is the operand # of the start of a memory operand if present. If
735 /// Not present, it is -1.
736 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
737 int MemOperand, const MCInst &MI,
738 const TargetInstrDesc &Desc,
739 raw_ostream &OS) const {
741 // Emit the lock opcode prefix as needed.
742 if (TSFlags & X86II::LOCK)
743 EmitByte(0xF0, CurByte, OS);
745 // Emit segment override opcode prefix as needed.
746 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
748 // Emit the repeat opcode prefix as needed.
749 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
750 EmitByte(0xF3, CurByte, OS);
752 // Emit the address size opcode prefix as needed.
753 if ((TSFlags & X86II::AdSize) ||
754 (MemOperand != -1 && Is64BitMode && Is32BitMemOperand(MI, MemOperand)))
755 EmitByte(0x67, CurByte, OS);
757 // Emit the operand size opcode prefix as needed.
758 if (TSFlags & X86II::OpSize)
759 EmitByte(0x66, CurByte, OS);
761 bool Need0FPrefix = false;
762 switch (TSFlags & X86II::Op0Mask) {
763 default: assert(0 && "Invalid prefix!");
764 case 0: break; // No prefix!
765 case X86II::REP: break; // already handled.
766 case X86II::TB: // Two-byte opcode prefix
767 case X86II::T8: // 0F 38
768 case X86II::TA: // 0F 3A
771 case X86II::TF: // F2 0F 38
772 EmitByte(0xF2, CurByte, OS);
775 case X86II::XS: // F3 0F
776 EmitByte(0xF3, CurByte, OS);
779 case X86II::XD: // F2 0F
780 EmitByte(0xF2, CurByte, OS);
783 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
784 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
785 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
786 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
787 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
788 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
789 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
790 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
793 // Handle REX prefix.
794 // FIXME: Can this come before F2 etc to simplify emission?
796 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
797 EmitByte(0x40 | REX, CurByte, OS);
800 // 0x0F escape code must be emitted just before the opcode.
802 EmitByte(0x0F, CurByte, OS);
804 // FIXME: Pull this up into previous switch if REX can be moved earlier.
805 switch (TSFlags & X86II::Op0Mask) {
806 case X86II::TF: // F2 0F 38
807 case X86II::T8: // 0F 38
808 EmitByte(0x38, CurByte, OS);
810 case X86II::TA: // 0F 3A
811 EmitByte(0x3A, CurByte, OS);
816 void X86MCCodeEmitter::
817 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
818 SmallVectorImpl<MCFixup> &Fixups) const {
819 unsigned Opcode = MI.getOpcode();
820 const TargetInstrDesc &Desc = TII.get(Opcode);
821 uint64_t TSFlags = Desc.TSFlags;
823 // Pseudo instructions don't get encoded.
824 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
827 // If this is a two-address instruction, skip one of the register operands.
828 // FIXME: This should be handled during MCInst lowering.
829 unsigned NumOps = Desc.getNumOperands();
831 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
833 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
834 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
837 // Keep track of the current byte being emitted.
838 unsigned CurByte = 0;
840 // Is this instruction encoded using the AVX VEX prefix?
841 bool HasVEXPrefix = false;
843 // It uses the VEX.VVVV field?
844 bool HasVEX_4V = false;
846 if ((TSFlags >> 32) & X86II::VEX)
848 if ((TSFlags >> 32) & X86II::VEX_4V)
852 // Determine where the memory operand starts, if present.
853 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
854 if (MemoryOperand != -1) MemoryOperand += CurOp;
857 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
859 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
862 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
864 if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
865 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
867 unsigned SrcRegNum = 0;
868 switch (TSFlags & X86II::FormMask) {
869 case X86II::MRMInitReg:
870 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
871 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
872 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
874 assert(0 && "Pseudo instruction shouldn't be emitted");
876 EmitByte(BaseOpcode, CurByte, OS);
879 case X86II::RawFrmImm8:
880 EmitByte(BaseOpcode, CurByte, OS);
881 EmitImmediate(MI.getOperand(CurOp++),
882 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
883 CurByte, OS, Fixups);
884 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
886 case X86II::RawFrmImm16:
887 EmitByte(BaseOpcode, CurByte, OS);
888 EmitImmediate(MI.getOperand(CurOp++),
889 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
890 CurByte, OS, Fixups);
891 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
894 case X86II::AddRegFrm:
895 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
898 case X86II::MRMDestReg:
899 EmitByte(BaseOpcode, CurByte, OS);
900 EmitRegModRMByte(MI.getOperand(CurOp),
901 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
905 case X86II::MRMDestMem:
906 EmitByte(BaseOpcode, CurByte, OS);
907 SrcRegNum = CurOp + X86::AddrNumOperands;
909 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
912 EmitMemModRMByte(MI, CurOp,
913 GetX86RegNum(MI.getOperand(SrcRegNum)),
914 TSFlags, CurByte, OS, Fixups);
915 CurOp = SrcRegNum + 1;
918 case X86II::MRMSrcReg:
919 EmitByte(BaseOpcode, CurByte, OS);
920 SrcRegNum = CurOp + 1;
922 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
925 EmitRegModRMByte(MI.getOperand(SrcRegNum),
926 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
927 CurOp = SrcRegNum + 1;
930 case X86II::MRMSrcMem: {
931 int AddrOperands = X86::AddrNumOperands;
932 unsigned FirstMemOp = CurOp+1;
935 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
938 EmitByte(BaseOpcode, CurByte, OS);
940 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
941 TSFlags, CurByte, OS, Fixups);
942 CurOp += AddrOperands + 1;
946 case X86II::MRM0r: case X86II::MRM1r:
947 case X86II::MRM2r: case X86II::MRM3r:
948 case X86II::MRM4r: case X86II::MRM5r:
949 case X86II::MRM6r: case X86II::MRM7r:
950 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
952 EmitByte(BaseOpcode, CurByte, OS);
953 EmitRegModRMByte(MI.getOperand(CurOp++),
954 (TSFlags & X86II::FormMask)-X86II::MRM0r,
957 case X86II::MRM0m: case X86II::MRM1m:
958 case X86II::MRM2m: case X86II::MRM3m:
959 case X86II::MRM4m: case X86II::MRM5m:
960 case X86II::MRM6m: case X86II::MRM7m:
961 EmitByte(BaseOpcode, CurByte, OS);
962 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
963 TSFlags, CurByte, OS, Fixups);
964 CurOp += X86::AddrNumOperands;
967 EmitByte(BaseOpcode, CurByte, OS);
968 EmitByte(0xC1, CurByte, OS);
971 EmitByte(BaseOpcode, CurByte, OS);
972 EmitByte(0xC2, CurByte, OS);
975 EmitByte(BaseOpcode, CurByte, OS);
976 EmitByte(0xC3, CurByte, OS);
979 EmitByte(BaseOpcode, CurByte, OS);
980 EmitByte(0xC4, CurByte, OS);
983 EmitByte(BaseOpcode, CurByte, OS);
984 EmitByte(0xC8, CurByte, OS);
987 EmitByte(BaseOpcode, CurByte, OS);
988 EmitByte(0xC9, CurByte, OS);
991 EmitByte(BaseOpcode, CurByte, OS);
992 EmitByte(0xE8, CurByte, OS);
995 EmitByte(BaseOpcode, CurByte, OS);
996 EmitByte(0xF0, CurByte, OS);
999 EmitByte(BaseOpcode, CurByte, OS);
1000 EmitByte(0xF8, CurByte, OS);
1003 EmitByte(BaseOpcode, CurByte, OS);
1004 EmitByte(0xF9, CurByte, OS);
1008 // If there is a remaining operand, it must be a trailing immediate. Emit it
1009 // according to the right size for the instruction.
1010 if (CurOp != NumOps) {
1011 // The last source register of a 4 operand instruction in AVX is encoded
1012 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
1013 if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
1014 const MCOperand &MO = MI.getOperand(CurOp++);
1016 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
1017 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1018 RegNum |= GetX86RegNum(MO) << 4;
1019 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
1023 if (MI.getOpcode() == X86::MOV64ri32 || MI.getOpcode() == X86::MOV64mi32)
1024 FixupKind = X86::reloc_signed_4byte;
1026 FixupKind = getImmFixupKind(TSFlags);
1027 EmitImmediate(MI.getOperand(CurOp++),
1028 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1029 CurByte, OS, Fixups);
1033 if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
1034 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1039 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1040 errs() << "Cannot encode all operands of: ";