1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/raw_ostream.h"
26 class X86MCCodeEmitter : public MCCodeEmitter {
27 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
29 const TargetMachine &TM;
30 const TargetInstrInfo &TII;
34 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
35 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
36 Is64BitMode = is64Bit;
39 ~X86MCCodeEmitter() {}
41 static unsigned GetX86RegNum(const MCOperand &MO) {
42 return X86RegisterInfo::getX86RegNum(MO.getReg());
45 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
46 // 0-7 and the difference between the 2 groups is given by the REX prefix.
47 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
48 // in 1's complement form, example:
50 // ModRM field => XMM9 => 1
51 // VEX.VVVV => XMM9 => ~9
53 // See table 4-35 of Intel AVX Programming Reference for details.
54 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
56 unsigned SrcReg = MI.getOperand(OpNum).getReg();
57 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
58 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
59 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
62 // The registers represented through VEX_VVVV should
63 // be encoded in 1's complement form.
64 return (~SrcRegNum) & 0xf;
67 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
72 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
73 raw_ostream &OS) const {
74 // Output the constant in little endian byte order.
75 for (unsigned i = 0; i != Size; ++i) {
76 EmitByte(Val & 255, CurByte, OS);
81 void EmitImmediate(const MCOperand &Disp,
82 unsigned ImmSize, MCFixupKind FixupKind,
83 unsigned &CurByte, raw_ostream &OS,
84 SmallVectorImpl<MCFixup> &Fixups,
85 int ImmOffset = 0) const;
87 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
89 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
90 return RM | (RegOpcode << 3) | (Mod << 6);
93 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
94 unsigned &CurByte, raw_ostream &OS) const {
95 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
98 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
99 unsigned &CurByte, raw_ostream &OS) const {
100 // SIB byte is in the same format as the ModRMByte.
101 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
105 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
106 unsigned RegOpcodeField,
107 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
108 SmallVectorImpl<MCFixup> &Fixups) const;
110 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
114 const MCInst &MI, const TargetInstrDesc &Desc,
115 raw_ostream &OS) const;
117 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
118 int MemOperand, const MCInst &MI,
119 raw_ostream &OS) const;
121 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
122 const MCInst &MI, const TargetInstrDesc &Desc,
123 raw_ostream &OS) const;
126 } // end anonymous namespace
129 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
132 return new X86MCCodeEmitter(TM, Ctx, false);
135 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
138 return new X86MCCodeEmitter(TM, Ctx, true);
141 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
142 /// sign-extended field.
143 static bool isDisp8(int Value) {
144 return Value == (signed char)Value;
147 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
148 /// in an instruction with the specified TSFlags.
149 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
150 unsigned Size = X86II::getSizeOfImm(TSFlags);
151 bool isPCRel = X86II::isImmPCRel(TSFlags);
153 return MCFixup::getKindForSize(Size, isPCRel);
156 /// Is32BitMemOperand - Return true if the specified instruction with a memory
157 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
158 /// memory operand. Op specifies the operand # of the memoperand.
159 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
160 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
161 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
163 if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) ||
164 (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg())))
169 /// StartsWithGlobalOffsetTable - Return true for the simple cases where this
170 /// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
171 /// PIC on ELF i386 as that symbol is magic. We check only simple case that
172 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
173 /// of a binary expression.
174 static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
175 if (Expr->getKind() == MCExpr::Binary) {
176 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
180 if (Expr->getKind() != MCExpr::SymbolRef)
183 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
184 const MCSymbol &S = Ref->getSymbol();
185 return S.getName() == "_GLOBAL_OFFSET_TABLE_";
188 void X86MCCodeEmitter::
189 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
190 unsigned &CurByte, raw_ostream &OS,
191 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
192 const MCExpr *Expr = NULL;
193 if (DispOp.isImm()) {
194 // If this is a simple integer displacement that doesn't require a relocation,
196 if (FixupKind != FK_PCRel_1 &&
197 FixupKind != FK_PCRel_2 &&
198 FixupKind != FK_PCRel_4) {
199 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
202 Expr = MCConstantExpr::Create(DispOp.getImm(), Ctx);
204 Expr = DispOp.getExpr();
207 // If we have an immoffset, add it to the expression.
208 if (FixupKind == FK_Data_4 && StartsWithGlobalOffsetTable(Expr)) {
209 assert(ImmOffset == 0);
211 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
215 // If the fixup is pc-relative, we need to bias the value to be relative to
216 // the start of the field, not the end of the field.
217 if (FixupKind == FK_PCRel_4 ||
218 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
219 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
221 if (FixupKind == FK_PCRel_2)
223 if (FixupKind == FK_PCRel_1)
227 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
230 // Emit a symbolic constant as a fixup and 4 zeros.
231 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
232 EmitConstant(0, Size, CurByte, OS);
235 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
236 unsigned RegOpcodeField,
237 uint64_t TSFlags, unsigned &CurByte,
239 SmallVectorImpl<MCFixup> &Fixups) const{
240 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
241 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
242 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
243 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
244 unsigned BaseReg = Base.getReg();
246 // Handle %rip relative addressing.
247 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
248 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
249 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
250 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
252 unsigned FixupKind = X86::reloc_riprel_4byte;
254 // movq loads are handled with a special relocation form which allows the
255 // linker to eliminate some loads for GOT references which end up in the
256 // same linkage unit.
257 if (MI.getOpcode() == X86::MOV64rm)
258 FixupKind = X86::reloc_riprel_4byte_movq_load;
260 // rip-relative addressing is actually relative to the *next* instruction.
261 // Since an immediate can follow the mod/rm byte for an instruction, this
262 // means that we need to bias the immediate field of the instruction with
263 // the size of the immediate field. If we have this case, add it into the
264 // expression to emit.
265 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
267 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
268 CurByte, OS, Fixups, -ImmSize);
272 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
274 // Determine whether a SIB byte is needed.
275 // If no BaseReg, issue a RIP relative instruction only if the MCE can
276 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
277 // 2-7) and absolute references.
279 if (// The SIB byte must be used if there is an index register.
280 IndexReg.getReg() == 0 &&
281 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
282 // encode to an R/M value of 4, which indicates that a SIB byte is
284 BaseRegNo != N86::ESP &&
285 // If there is no base register and we're in 64-bit mode, we need a SIB
286 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
287 (!Is64BitMode || BaseReg != 0)) {
289 if (BaseReg == 0) { // [disp32] in X86-32 mode
290 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
291 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
295 // If the base is not EBP/ESP and there is no displacement, use simple
296 // indirect register encoding, this handles addresses like [EAX]. The
297 // encoding for [EBP] with no displacement means [disp32] so we handle it
298 // by emitting a displacement of 0 below.
299 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
300 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
304 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
305 if (Disp.isImm() && isDisp8(Disp.getImm())) {
306 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
307 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
311 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
312 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
313 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
318 // We need a SIB byte, so start by outputting the ModR/M byte first
319 assert(IndexReg.getReg() != X86::ESP &&
320 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
322 bool ForceDisp32 = false;
323 bool ForceDisp8 = false;
325 // If there is no base register, we emit the special case SIB byte with
326 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
327 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
329 } else if (!Disp.isImm()) {
330 // Emit the normal disp32 encoding.
331 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
333 } else if (Disp.getImm() == 0 &&
334 // Base reg can't be anything that ends up with '5' as the base
335 // reg, it is the magic [*] nomenclature that indicates no base.
336 BaseRegNo != N86::EBP) {
337 // Emit no displacement ModR/M byte
338 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
339 } else if (isDisp8(Disp.getImm())) {
340 // Emit the disp8 encoding.
341 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
342 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
344 // Emit the normal disp32 encoding.
345 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
348 // Calculate what the SS field value should be...
349 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
350 unsigned SS = SSTable[Scale.getImm()];
353 // Handle the SIB byte for the case where there is no base, see Intel
354 // Manual 2A, table 2-7. The displacement has already been output.
356 if (IndexReg.getReg())
357 IndexRegNo = GetX86RegNum(IndexReg);
358 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
360 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
363 if (IndexReg.getReg())
364 IndexRegNo = GetX86RegNum(IndexReg);
366 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
367 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
370 // Do we need to output a displacement?
372 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
373 else if (ForceDisp32 || Disp.getImm() != 0)
374 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
378 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
380 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
381 int MemOperand, const MCInst &MI,
382 const TargetInstrDesc &Desc,
383 raw_ostream &OS) const {
384 bool HasVEX_4V = false;
385 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
388 // VEX_R: opcode externsion equivalent to REX.R in
389 // 1's complement (inverted) form
391 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
392 // 0: Same as REX_R=1 (64 bit mode only)
394 unsigned char VEX_R = 0x1;
396 // VEX_X: equivalent to REX.X, only used when a
397 // register is used for index in SIB Byte.
399 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
400 // 0: Same as REX.X=1 (64-bit mode only)
401 unsigned char VEX_X = 0x1;
405 // 1: Same as REX_B=0 (ignored in 32-bit mode)
406 // 0: Same as REX_B=1 (64 bit mode only)
408 unsigned char VEX_B = 0x1;
410 // VEX_W: opcode specific (use like REX.W, or used for
411 // opcode extension, or ignored, depending on the opcode byte)
412 unsigned char VEX_W = 0;
414 // VEX_5M (VEX m-mmmmm field):
416 // 0b00000: Reserved for future use
417 // 0b00001: implied 0F leading opcode
418 // 0b00010: implied 0F 38 leading opcode bytes
419 // 0b00011: implied 0F 3A leading opcode bytes
420 // 0b00100-0b11111: Reserved for future use
422 unsigned char VEX_5M = 0x1;
424 // VEX_4V (VEX vvvv field): a register specifier
425 // (in 1's complement form) or 1111 if unused.
426 unsigned char VEX_4V = 0xf;
428 // VEX_L (Vector Length):
430 // 0: scalar or 128-bit vector
433 unsigned char VEX_L = 0;
435 // VEX_PP: opcode extension providing equivalent
436 // functionality of a SIMD prefix
443 unsigned char VEX_PP = 0;
445 // Encode the operand size opcode prefix as needed.
446 if (TSFlags & X86II::OpSize)
449 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
452 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
455 switch (TSFlags & X86II::Op0Mask) {
456 default: assert(0 && "Invalid prefix!");
457 case X86II::T8: // 0F 38
460 case X86II::TA: // 0F 3A
463 case X86II::TF: // F2 0F 38
467 case X86II::XS: // F3 0F
470 case X86II::XD: // F2 0F
473 case X86II::A6: // Bypass: Not used by VEX
474 case X86II::A7: // Bypass: Not used by VEX
475 case X86II::TB: // Bypass: Not used by VEX
480 // Set the vector length to 256-bit if YMM0-YMM15 is used
481 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
482 if (!MI.getOperand(i).isReg())
484 unsigned SrcReg = MI.getOperand(i).getReg();
485 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
489 unsigned NumOps = MI.getNumOperands();
491 bool IsDestMem = false;
493 switch (TSFlags & X86II::FormMask) {
494 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
495 case X86II::MRMDestMem:
497 // The important info for the VEX prefix is never beyond the address
498 // registers. Don't check beyond that.
499 NumOps = CurOp = X86::AddrNumOperands;
500 case X86II::MRM0m: case X86II::MRM1m:
501 case X86II::MRM2m: case X86II::MRM3m:
502 case X86II::MRM4m: case X86II::MRM5m:
503 case X86II::MRM6m: case X86II::MRM7m:
504 case X86II::MRMSrcMem:
505 case X86II::MRMSrcReg:
506 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
507 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
512 VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
516 // To only check operands before the memory address ones, start
517 // the search from the beginning
521 // If the last register should be encoded in the immediate field
522 // do not use any bit from VEX prefix to this register, ignore it
523 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
526 for (; CurOp != NumOps; ++CurOp) {
527 const MCOperand &MO = MI.getOperand(CurOp);
528 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
530 if (!VEX_B && MO.isReg() &&
531 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
532 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
536 default: // MRMDestReg, MRM0r-MRM7r, RawFrm
537 if (!MI.getNumOperands())
540 if (MI.getOperand(CurOp).isReg() &&
541 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
545 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
548 for (; CurOp != NumOps; ++CurOp) {
549 const MCOperand &MO = MI.getOperand(CurOp);
550 if (MO.isReg() && !HasVEX_4V &&
551 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
557 // Emit segment override opcode prefix as needed.
558 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
560 // VEX opcode prefix can have 2 or 3 bytes
563 // +-----+ +--------------+ +-------------------+
564 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
565 // +-----+ +--------------+ +-------------------+
567 // +-----+ +-------------------+
568 // | C5h | | R | vvvv | L | pp |
569 // +-----+ +-------------------+
571 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
573 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
574 EmitByte(0xC5, CurByte, OS);
575 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
580 EmitByte(0xC4, CurByte, OS);
581 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
582 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
585 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
586 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
587 /// size, and 3) use of X86-64 extended registers.
588 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
589 const TargetInstrDesc &Desc) {
591 if (TSFlags & X86II::REX_W)
592 REX |= 1 << 3; // set REX.W
594 if (MI.getNumOperands() == 0) return REX;
596 unsigned NumOps = MI.getNumOperands();
597 // FIXME: MCInst should explicitize the two-addrness.
598 bool isTwoAddr = NumOps > 1 &&
599 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
601 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
602 unsigned i = isTwoAddr ? 1 : 0;
603 for (; i != NumOps; ++i) {
604 const MCOperand &MO = MI.getOperand(i);
605 if (!MO.isReg()) continue;
606 unsigned Reg = MO.getReg();
607 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
608 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
609 // that returns non-zero.
610 REX |= 0x40; // REX fixed encoding prefix
614 switch (TSFlags & X86II::FormMask) {
615 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
616 case X86II::MRMSrcReg:
617 if (MI.getOperand(0).isReg() &&
618 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
619 REX |= 1 << 2; // set REX.R
620 i = isTwoAddr ? 2 : 1;
621 for (; i != NumOps; ++i) {
622 const MCOperand &MO = MI.getOperand(i);
623 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
624 REX |= 1 << 0; // set REX.B
627 case X86II::MRMSrcMem: {
628 if (MI.getOperand(0).isReg() &&
629 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
630 REX |= 1 << 2; // set REX.R
632 i = isTwoAddr ? 2 : 1;
633 for (; i != NumOps; ++i) {
634 const MCOperand &MO = MI.getOperand(i);
636 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
637 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
643 case X86II::MRM0m: case X86II::MRM1m:
644 case X86II::MRM2m: case X86II::MRM3m:
645 case X86II::MRM4m: case X86II::MRM5m:
646 case X86II::MRM6m: case X86II::MRM7m:
647 case X86II::MRMDestMem: {
648 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
649 i = isTwoAddr ? 1 : 0;
650 if (NumOps > e && MI.getOperand(e).isReg() &&
651 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
652 REX |= 1 << 2; // set REX.R
654 for (; i != e; ++i) {
655 const MCOperand &MO = MI.getOperand(i);
657 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
658 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
665 if (MI.getOperand(0).isReg() &&
666 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
667 REX |= 1 << 0; // set REX.B
668 i = isTwoAddr ? 2 : 1;
669 for (unsigned e = NumOps; i != e; ++i) {
670 const MCOperand &MO = MI.getOperand(i);
671 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
672 REX |= 1 << 2; // set REX.R
679 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
680 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
681 unsigned &CurByte, int MemOperand,
683 raw_ostream &OS) const {
684 switch (TSFlags & X86II::SegOvrMask) {
685 default: assert(0 && "Invalid segment!");
687 // No segment override, check for explicit one on memory operand.
688 if (MemOperand != -1) { // If the instruction has a memory operand.
689 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
690 default: assert(0 && "Unknown segment register!");
692 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
693 case X86::SS: EmitByte(0x36, CurByte, OS); break;
694 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
695 case X86::ES: EmitByte(0x26, CurByte, OS); break;
696 case X86::FS: EmitByte(0x64, CurByte, OS); break;
697 case X86::GS: EmitByte(0x65, CurByte, OS); break;
702 EmitByte(0x64, CurByte, OS);
705 EmitByte(0x65, CurByte, OS);
710 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
712 /// MemOperand is the operand # of the start of a memory operand if present. If
713 /// Not present, it is -1.
714 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
715 int MemOperand, const MCInst &MI,
716 const TargetInstrDesc &Desc,
717 raw_ostream &OS) const {
719 // Emit the lock opcode prefix as needed.
720 if (TSFlags & X86II::LOCK)
721 EmitByte(0xF0, CurByte, OS);
723 // Emit segment override opcode prefix as needed.
724 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
726 // Emit the repeat opcode prefix as needed.
727 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
728 EmitByte(0xF3, CurByte, OS);
730 // Emit the address size opcode prefix as needed.
731 if ((TSFlags & X86II::AdSize) ||
732 (MemOperand != -1 && Is64BitMode && Is32BitMemOperand(MI, MemOperand)))
733 EmitByte(0x67, CurByte, OS);
735 // Emit the operand size opcode prefix as needed.
736 if (TSFlags & X86II::OpSize)
737 EmitByte(0x66, CurByte, OS);
739 bool Need0FPrefix = false;
740 switch (TSFlags & X86II::Op0Mask) {
741 default: assert(0 && "Invalid prefix!");
742 case 0: break; // No prefix!
743 case X86II::REP: break; // already handled.
744 case X86II::TB: // Two-byte opcode prefix
745 case X86II::T8: // 0F 38
746 case X86II::TA: // 0F 3A
747 case X86II::A6: // 0F A6
748 case X86II::A7: // 0F A7
751 case X86II::TF: // F2 0F 38
752 EmitByte(0xF2, CurByte, OS);
755 case X86II::XS: // F3 0F
756 EmitByte(0xF3, CurByte, OS);
759 case X86II::XD: // F2 0F
760 EmitByte(0xF2, CurByte, OS);
763 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
764 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
765 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
766 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
767 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
768 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
769 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
770 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
773 // Handle REX prefix.
774 // FIXME: Can this come before F2 etc to simplify emission?
776 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
777 EmitByte(0x40 | REX, CurByte, OS);
780 // 0x0F escape code must be emitted just before the opcode.
782 EmitByte(0x0F, CurByte, OS);
784 // FIXME: Pull this up into previous switch if REX can be moved earlier.
785 switch (TSFlags & X86II::Op0Mask) {
786 case X86II::TF: // F2 0F 38
787 case X86II::T8: // 0F 38
788 EmitByte(0x38, CurByte, OS);
790 case X86II::TA: // 0F 3A
791 EmitByte(0x3A, CurByte, OS);
793 case X86II::A6: // 0F A6
794 EmitByte(0xA6, CurByte, OS);
796 case X86II::A7: // 0F A7
797 EmitByte(0xA7, CurByte, OS);
802 void X86MCCodeEmitter::
803 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
804 SmallVectorImpl<MCFixup> &Fixups) const {
805 unsigned Opcode = MI.getOpcode();
806 const TargetInstrDesc &Desc = TII.get(Opcode);
807 uint64_t TSFlags = Desc.TSFlags;
809 // Pseudo instructions don't get encoded.
810 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
813 // If this is a two-address instruction, skip one of the register operands.
814 // FIXME: This should be handled during MCInst lowering.
815 unsigned NumOps = Desc.getNumOperands();
817 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
819 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
820 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
823 // Keep track of the current byte being emitted.
824 unsigned CurByte = 0;
826 // Is this instruction encoded using the AVX VEX prefix?
827 bool HasVEXPrefix = false;
829 // It uses the VEX.VVVV field?
830 bool HasVEX_4V = false;
832 if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
834 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
838 // Determine where the memory operand starts, if present.
839 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
840 if (MemoryOperand != -1) MemoryOperand += CurOp;
843 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
845 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
848 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
850 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
851 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
853 unsigned SrcRegNum = 0;
854 switch (TSFlags & X86II::FormMask) {
855 case X86II::MRMInitReg:
856 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
857 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
858 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
860 assert(0 && "Pseudo instruction shouldn't be emitted");
862 EmitByte(BaseOpcode, CurByte, OS);
865 case X86II::RawFrmImm8:
866 EmitByte(BaseOpcode, CurByte, OS);
867 EmitImmediate(MI.getOperand(CurOp++),
868 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
869 CurByte, OS, Fixups);
870 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
872 case X86II::RawFrmImm16:
873 EmitByte(BaseOpcode, CurByte, OS);
874 EmitImmediate(MI.getOperand(CurOp++),
875 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
876 CurByte, OS, Fixups);
877 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
880 case X86II::AddRegFrm:
881 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
884 case X86II::MRMDestReg:
885 EmitByte(BaseOpcode, CurByte, OS);
886 EmitRegModRMByte(MI.getOperand(CurOp),
887 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
891 case X86II::MRMDestMem:
892 EmitByte(BaseOpcode, CurByte, OS);
893 SrcRegNum = CurOp + X86::AddrNumOperands;
895 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
898 EmitMemModRMByte(MI, CurOp,
899 GetX86RegNum(MI.getOperand(SrcRegNum)),
900 TSFlags, CurByte, OS, Fixups);
901 CurOp = SrcRegNum + 1;
904 case X86II::MRMSrcReg:
905 EmitByte(BaseOpcode, CurByte, OS);
906 SrcRegNum = CurOp + 1;
908 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
911 EmitRegModRMByte(MI.getOperand(SrcRegNum),
912 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
913 CurOp = SrcRegNum + 1;
916 case X86II::MRMSrcMem: {
917 int AddrOperands = X86::AddrNumOperands;
918 unsigned FirstMemOp = CurOp+1;
921 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
924 EmitByte(BaseOpcode, CurByte, OS);
926 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
927 TSFlags, CurByte, OS, Fixups);
928 CurOp += AddrOperands + 1;
932 case X86II::MRM0r: case X86II::MRM1r:
933 case X86II::MRM2r: case X86II::MRM3r:
934 case X86II::MRM4r: case X86II::MRM5r:
935 case X86II::MRM6r: case X86II::MRM7r:
936 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
938 EmitByte(BaseOpcode, CurByte, OS);
939 EmitRegModRMByte(MI.getOperand(CurOp++),
940 (TSFlags & X86II::FormMask)-X86II::MRM0r,
943 case X86II::MRM0m: case X86II::MRM1m:
944 case X86II::MRM2m: case X86II::MRM3m:
945 case X86II::MRM4m: case X86II::MRM5m:
946 case X86II::MRM6m: case X86II::MRM7m:
947 EmitByte(BaseOpcode, CurByte, OS);
948 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
949 TSFlags, CurByte, OS, Fixups);
950 CurOp += X86::AddrNumOperands;
953 EmitByte(BaseOpcode, CurByte, OS);
954 EmitByte(0xC1, CurByte, OS);
957 EmitByte(BaseOpcode, CurByte, OS);
958 EmitByte(0xC2, CurByte, OS);
961 EmitByte(BaseOpcode, CurByte, OS);
962 EmitByte(0xC3, CurByte, OS);
965 EmitByte(BaseOpcode, CurByte, OS);
966 EmitByte(0xC4, CurByte, OS);
969 EmitByte(BaseOpcode, CurByte, OS);
970 EmitByte(0xC8, CurByte, OS);
973 EmitByte(BaseOpcode, CurByte, OS);
974 EmitByte(0xC9, CurByte, OS);
977 EmitByte(BaseOpcode, CurByte, OS);
978 EmitByte(0xE8, CurByte, OS);
981 EmitByte(BaseOpcode, CurByte, OS);
982 EmitByte(0xF0, CurByte, OS);
985 EmitByte(BaseOpcode, CurByte, OS);
986 EmitByte(0xF8, CurByte, OS);
989 EmitByte(BaseOpcode, CurByte, OS);
990 EmitByte(0xF9, CurByte, OS);
993 EmitByte(BaseOpcode, CurByte, OS);
994 EmitByte(0xD0, CurByte, OS);
997 EmitByte(BaseOpcode, CurByte, OS);
998 EmitByte(0xD1, CurByte, OS);
1002 // If there is a remaining operand, it must be a trailing immediate. Emit it
1003 // according to the right size for the instruction.
1004 if (CurOp != NumOps) {
1005 // The last source register of a 4 operand instruction in AVX is encoded
1006 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
1007 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
1008 const MCOperand &MO = MI.getOperand(CurOp++);
1010 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
1011 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1012 RegNum |= GetX86RegNum(MO) << 4;
1013 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
1017 // FIXME: Is there a better way to know that we need a signed relocation?
1018 if (MI.getOpcode() == X86::ADD64ri32 ||
1019 MI.getOpcode() == X86::MOV64ri32 ||
1020 MI.getOpcode() == X86::MOV64mi32 ||
1021 MI.getOpcode() == X86::PUSH64i32)
1022 FixupKind = X86::reloc_signed_4byte;
1024 FixupKind = getImmFixupKind(TSFlags);
1025 EmitImmediate(MI.getOperand(CurOp++),
1026 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1027 CurByte, OS, Fixups);
1031 if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
1032 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1037 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1038 errs() << "Cannot encode all operands of: ";