1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
47 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
60 static unsigned GetX86RegNum(const MCOperand &MO) {
61 return X86RegisterInfo::getX86RegNum(MO.getReg());
64 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
65 // 0-7 and the difference between the 2 groups is given by the REX prefix.
66 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
67 // in 1's complement form, example:
69 // ModRM field => XMM9 => 1
70 // VEX.VVVV => XMM9 => ~9
72 // See table 4-35 of Intel AVX Programming Reference for details.
73 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
75 unsigned SrcReg = MI.getOperand(OpNum).getReg();
76 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
77 if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
80 // The registers represented through VEX_VVVV should
81 // be encoded in 1's complement form.
82 return (~SrcRegNum) & 0xf;
85 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
90 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
91 raw_ostream &OS) const {
92 // Output the constant in little endian byte order.
93 for (unsigned i = 0; i != Size; ++i) {
94 EmitByte(Val & 255, CurByte, OS);
99 void EmitImmediate(const MCOperand &Disp,
100 unsigned ImmSize, MCFixupKind FixupKind,
101 unsigned &CurByte, raw_ostream &OS,
102 SmallVectorImpl<MCFixup> &Fixups,
103 int ImmOffset = 0) const;
105 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
107 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
108 return RM | (RegOpcode << 3) | (Mod << 6);
111 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
112 unsigned &CurByte, raw_ostream &OS) const {
113 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
116 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
117 unsigned &CurByte, raw_ostream &OS) const {
118 // SIB byte is in the same format as the ModRMByte.
119 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
123 void EmitSegmentOverridePrefix(const MCOperand &Op, unsigned TSFlags,
124 unsigned &CurByte, raw_ostream &OS) const;
126 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
127 unsigned RegOpcodeField,
128 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
132 SmallVectorImpl<MCFixup> &Fixups) const;
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
135 const MCInst &MI, const TargetInstrDesc &Desc,
136 raw_ostream &OS) const;
138 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
139 const MCInst &MI, const TargetInstrDesc &Desc,
140 raw_ostream &OS) const;
143 } // end anonymous namespace
146 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
149 return new X86MCCodeEmitter(TM, Ctx, false);
152 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
155 return new X86MCCodeEmitter(TM, Ctx, true);
158 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
159 /// sign-extended field.
160 static bool isDisp8(int Value) {
161 return Value == (signed char)Value;
164 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
165 /// in an instruction with the specified TSFlags.
166 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
167 unsigned Size = X86II::getSizeOfImm(TSFlags);
168 bool isPCRel = X86II::isImmPCRel(TSFlags);
171 default: assert(0 && "Unknown immediate size");
172 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
173 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
174 case 2: assert(!isPCRel); return FK_Data_2;
175 case 8: assert(!isPCRel); return FK_Data_8;
180 void X86MCCodeEmitter::
181 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
182 unsigned &CurByte, raw_ostream &OS,
183 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
184 // If this is a simple integer displacement that doesn't require a relocation,
186 if (DispOp.isImm()) {
187 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
189 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
193 // If we have an immoffset, add it to the expression.
194 const MCExpr *Expr = DispOp.getExpr();
196 // If the fixup is pc-relative, we need to bias the value to be relative to
197 // the start of the field, not the end of the field.
198 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
199 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
200 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
202 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
206 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
209 // Emit a symbolic constant as a fixup and 4 zeros.
210 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
211 EmitConstant(0, Size, CurByte, OS);
214 void X86MCCodeEmitter::EmitSegmentOverridePrefix(const MCOperand &Op,
217 raw_ostream &OS) const {
218 // If no segment register is present, we don't need anything.
219 if (Op.getReg() == 0)
222 // Check if we need an override.
223 switch (Op.getReg()) {
224 case X86::CS: EmitByte(0x2E, CurByte, OS); return;
225 case X86::SS: EmitByte(0x36, CurByte, OS); return;
226 case X86::DS: EmitByte(0x3E, CurByte, OS); return;
227 case X86::ES: EmitByte(0x26, CurByte, OS); return;
228 case X86::FS: EmitByte(0x64, CurByte, OS); return;
229 case X86::GS: EmitByte(0x65, CurByte, OS); return;
232 assert(0 && "Invalid segment register!");
235 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
236 unsigned RegOpcodeField,
237 uint64_t TSFlags, unsigned &CurByte,
239 SmallVectorImpl<MCFixup> &Fixups) const{
240 const MCOperand &Disp = MI.getOperand(Op+3);
241 const MCOperand &Base = MI.getOperand(Op);
242 const MCOperand &Scale = MI.getOperand(Op+1);
243 const MCOperand &IndexReg = MI.getOperand(Op+2);
244 unsigned BaseReg = Base.getReg();
246 // Handle %rip relative addressing.
247 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
248 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
249 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
250 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
252 unsigned FixupKind = X86::reloc_riprel_4byte;
254 // movq loads are handled with a special relocation form which allows the
255 // linker to eliminate some loads for GOT references which end up in the
256 // same linkage unit.
257 if (MI.getOpcode() == X86::MOV64rm ||
258 MI.getOpcode() == X86::MOV64rm_TC)
259 FixupKind = X86::reloc_riprel_4byte_movq_load;
261 // rip-relative addressing is actually relative to the *next* instruction.
262 // Since an immediate can follow the mod/rm byte for an instruction, this
263 // means that we need to bias the immediate field of the instruction with
264 // the size of the immediate field. If we have this case, add it into the
265 // expression to emit.
266 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
268 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
269 CurByte, OS, Fixups, -ImmSize);
273 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
275 // Determine whether a SIB byte is needed.
276 // If no BaseReg, issue a RIP relative instruction only if the MCE can
277 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
278 // 2-7) and absolute references.
280 if (// The SIB byte must be used if there is an index register.
281 IndexReg.getReg() == 0 &&
282 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
283 // encode to an R/M value of 4, which indicates that a SIB byte is
285 BaseRegNo != N86::ESP &&
286 // If there is no base register and we're in 64-bit mode, we need a SIB
287 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
288 (!Is64BitMode || BaseReg != 0)) {
290 if (BaseReg == 0) { // [disp32] in X86-32 mode
291 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
292 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
296 // If the base is not EBP/ESP and there is no displacement, use simple
297 // indirect register encoding, this handles addresses like [EAX]. The
298 // encoding for [EBP] with no displacement means [disp32] so we handle it
299 // by emitting a displacement of 0 below.
300 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
301 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
305 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
306 if (Disp.isImm() && isDisp8(Disp.getImm())) {
307 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
308 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
312 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
313 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
314 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
318 // We need a SIB byte, so start by outputting the ModR/M byte first
319 assert(IndexReg.getReg() != X86::ESP &&
320 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
322 bool ForceDisp32 = false;
323 bool ForceDisp8 = false;
325 // If there is no base register, we emit the special case SIB byte with
326 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
327 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
329 } else if (!Disp.isImm()) {
330 // Emit the normal disp32 encoding.
331 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
333 } else if (Disp.getImm() == 0 &&
334 // Base reg can't be anything that ends up with '5' as the base
335 // reg, it is the magic [*] nomenclature that indicates no base.
336 BaseRegNo != N86::EBP) {
337 // Emit no displacement ModR/M byte
338 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
339 } else if (isDisp8(Disp.getImm())) {
340 // Emit the disp8 encoding.
341 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
342 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
344 // Emit the normal disp32 encoding.
345 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
348 // Calculate what the SS field value should be...
349 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
350 unsigned SS = SSTable[Scale.getImm()];
353 // Handle the SIB byte for the case where there is no base, see Intel
354 // Manual 2A, table 2-7. The displacement has already been output.
356 if (IndexReg.getReg())
357 IndexRegNo = GetX86RegNum(IndexReg);
358 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
360 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
363 if (IndexReg.getReg())
364 IndexRegNo = GetX86RegNum(IndexReg);
366 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
367 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
370 // Do we need to output a displacement?
372 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
373 else if (ForceDisp32 || Disp.getImm() != 0)
374 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
377 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
379 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
380 const MCInst &MI, const TargetInstrDesc &Desc,
381 raw_ostream &OS) const {
383 // Pseudo instructions never have a VEX prefix.
384 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
387 bool HasVEX_4V = false;
388 if ((TSFlags >> 32) & X86II::VEX_4V)
391 // VEX_R: opcode externsion equivalent to REX.R in
392 // 1's complement (inverted) form
394 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
395 // 0: Same as REX_R=1 (64 bit mode only)
397 unsigned char VEX_R = 0x1;
399 // VEX_X: equivalent to REX.X, only used when a
400 // register is used for index in SIB Byte.
402 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
403 // 0: Same as REX.X=1 (64-bit mode only)
404 unsigned char VEX_X = 0x1;
408 // 1: Same as REX_B=0 (ignored in 32-bit mode)
409 // 0: Same as REX_B=1 (64 bit mode only)
411 unsigned char VEX_B = 0x1;
413 // VEX_W: opcode specific (use like REX.W, or used for
414 // opcode extension, or ignored, depending on the opcode byte)
415 unsigned char VEX_W = 0;
417 // VEX_5M (VEX m-mmmmm field):
419 // 0b00000: Reserved for future use
420 // 0b00001: implied 0F leading opcode
421 // 0b00010: implied 0F 38 leading opcode bytes
422 // 0b00011: implied 0F 3A leading opcode bytes
423 // 0b00100-0b11111: Reserved for future use
425 unsigned char VEX_5M = 0x1;
427 // VEX_4V (VEX vvvv field): a register specifier
428 // (in 1's complement form) or 1111 if unused.
429 unsigned char VEX_4V = 0xf;
431 // VEX_L (Vector Length):
433 // 0: scalar or 128-bit vector
436 unsigned char VEX_L = 0;
438 // VEX_PP: opcode extension providing equivalent
439 // functionality of a SIMD prefix
446 unsigned char VEX_PP = 0;
448 // Encode the operand size opcode prefix as needed.
449 if (TSFlags & X86II::OpSize)
452 switch (TSFlags & X86II::Op0Mask) {
453 default: assert(0 && "Invalid prefix!");
454 case X86II::T8: // 0F 38
457 case X86II::TA: // 0F 3A
460 case X86II::TF: // F2 0F 38
464 case X86II::XS: // F3 0F
467 case X86II::XD: // F2 0F
470 case X86II::TB: // Bypass: Not used by VEX
475 unsigned NumOps = MI.getNumOperands();
478 switch (TSFlags & X86II::FormMask) {
479 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
480 case X86II::MRM0m: case X86II::MRM1m:
481 case X86II::MRM2m: case X86II::MRM3m:
482 case X86II::MRM4m: case X86II::MRM5m:
483 case X86II::MRM6m: case X86II::MRM7m:
484 case X86II::MRMDestMem:
485 NumOps = CurOp = X86AddrNumOperands;
486 case X86II::MRMSrcMem:
487 case X86II::MRMSrcReg:
488 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
489 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
492 // CurOp and NumOps are equal when VEX_R represents a register used
493 // to index a memory destination (which is the last operand)
494 CurOp = (CurOp == NumOps) ? 0 : CurOp+1;
497 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
501 for (; CurOp != NumOps; ++CurOp) {
502 const MCOperand &MO = MI.getOperand(CurOp);
503 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
505 if (!VEX_B && MO.isReg() &&
506 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
507 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
511 default: // MRM0r-MRM7r
513 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
516 for (; CurOp != NumOps; ++CurOp) {
517 const MCOperand &MO = MI.getOperand(CurOp);
518 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
522 assert(0 && "Not implemented!");
525 // VEX opcode prefix can have 2 or 3 bytes
528 // +-----+ +--------------+ +-------------------+
529 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
530 // +-----+ +--------------+ +-------------------+
532 // +-----+ +-------------------+
533 // | C5h | | R | vvvv | L | pp |
534 // +-----+ +-------------------+
536 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
538 if (VEX_B && VEX_X) { // 2 byte VEX prefix
539 EmitByte(0xC5, CurByte, OS);
540 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
545 EmitByte(0xC4, CurByte, OS);
546 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_5M, CurByte, OS);
547 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
550 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
551 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
552 /// size, and 3) use of X86-64 extended registers.
553 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
554 const TargetInstrDesc &Desc) {
555 // Pseudo instructions never have a rex byte.
556 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
560 if (TSFlags & X86II::REX_W)
561 REX |= 1 << 3; // set REX.W
563 if (MI.getNumOperands() == 0) return REX;
565 unsigned NumOps = MI.getNumOperands();
566 // FIXME: MCInst should explicitize the two-addrness.
567 bool isTwoAddr = NumOps > 1 &&
568 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
570 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
571 unsigned i = isTwoAddr ? 1 : 0;
572 for (; i != NumOps; ++i) {
573 const MCOperand &MO = MI.getOperand(i);
574 if (!MO.isReg()) continue;
575 unsigned Reg = MO.getReg();
576 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
577 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
578 // that returns non-zero.
579 REX |= 0x40; // REX fixed encoding prefix
583 switch (TSFlags & X86II::FormMask) {
584 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
585 case X86II::MRMSrcReg:
586 if (MI.getOperand(0).isReg() &&
587 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
588 REX |= 1 << 2; // set REX.R
589 i = isTwoAddr ? 2 : 1;
590 for (; i != NumOps; ++i) {
591 const MCOperand &MO = MI.getOperand(i);
592 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
593 REX |= 1 << 0; // set REX.B
596 case X86II::MRMSrcMem: {
597 if (MI.getOperand(0).isReg() &&
598 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
599 REX |= 1 << 2; // set REX.R
601 i = isTwoAddr ? 2 : 1;
602 for (; i != NumOps; ++i) {
603 const MCOperand &MO = MI.getOperand(i);
605 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
606 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
612 case X86II::MRM0m: case X86II::MRM1m:
613 case X86II::MRM2m: case X86II::MRM3m:
614 case X86II::MRM4m: case X86II::MRM5m:
615 case X86II::MRM6m: case X86II::MRM7m:
616 case X86II::MRMDestMem: {
617 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
618 i = isTwoAddr ? 1 : 0;
619 if (NumOps > e && MI.getOperand(e).isReg() &&
620 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
621 REX |= 1 << 2; // set REX.R
623 for (; i != e; ++i) {
624 const MCOperand &MO = MI.getOperand(i);
626 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
627 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
634 if (MI.getOperand(0).isReg() &&
635 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
636 REX |= 1 << 0; // set REX.B
637 i = isTwoAddr ? 2 : 1;
638 for (unsigned e = NumOps; i != e; ++i) {
639 const MCOperand &MO = MI.getOperand(i);
640 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
641 REX |= 1 << 2; // set REX.R
648 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
649 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
650 const MCInst &MI, const TargetInstrDesc &Desc,
651 raw_ostream &OS) const {
653 // Emit the lock opcode prefix as needed.
654 if (TSFlags & X86II::LOCK)
655 EmitByte(0xF0, CurByte, OS);
657 // Emit segment override opcode prefix as needed.
658 switch (TSFlags & X86II::SegOvrMask) {
659 default: assert(0 && "Invalid segment!");
660 case 0: break; // No segment override!
662 EmitByte(0x64, CurByte, OS);
665 EmitByte(0x65, CurByte, OS);
669 // Emit the repeat opcode prefix as needed.
670 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
671 EmitByte(0xF3, CurByte, OS);
673 // Emit the operand size opcode prefix as needed.
674 if (TSFlags & X86II::OpSize)
675 EmitByte(0x66, CurByte, OS);
677 // Emit the address size opcode prefix as needed.
678 if (TSFlags & X86II::AdSize)
679 EmitByte(0x67, CurByte, OS);
681 bool Need0FPrefix = false;
682 switch (TSFlags & X86II::Op0Mask) {
683 default: assert(0 && "Invalid prefix!");
684 case 0: break; // No prefix!
685 case X86II::REP: break; // already handled.
686 case X86II::TB: // Two-byte opcode prefix
687 case X86II::T8: // 0F 38
688 case X86II::TA: // 0F 3A
691 case X86II::TF: // F2 0F 38
692 EmitByte(0xF2, CurByte, OS);
695 case X86II::XS: // F3 0F
696 EmitByte(0xF3, CurByte, OS);
699 case X86II::XD: // F2 0F
700 EmitByte(0xF2, CurByte, OS);
703 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
704 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
705 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
706 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
707 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
708 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
709 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
710 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
713 // Handle REX prefix.
714 // FIXME: Can this come before F2 etc to simplify emission?
716 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
717 EmitByte(0x40 | REX, CurByte, OS);
720 // 0x0F escape code must be emitted just before the opcode.
722 EmitByte(0x0F, CurByte, OS);
724 // FIXME: Pull this up into previous switch if REX can be moved earlier.
725 switch (TSFlags & X86II::Op0Mask) {
726 case X86II::TF: // F2 0F 38
727 case X86II::T8: // 0F 38
728 EmitByte(0x38, CurByte, OS);
730 case X86II::TA: // 0F 3A
731 EmitByte(0x3A, CurByte, OS);
736 void X86MCCodeEmitter::
737 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
738 SmallVectorImpl<MCFixup> &Fixups) const {
739 unsigned Opcode = MI.getOpcode();
740 const TargetInstrDesc &Desc = TII.get(Opcode);
741 uint64_t TSFlags = Desc.TSFlags;
743 // Keep track of the current byte being emitted.
744 unsigned CurByte = 0;
746 // Is this instruction encoded using the AVX VEX prefix?
747 bool HasVEXPrefix = false;
749 // It uses the VEX.VVVV field?
750 bool HasVEX_4V = false;
752 if ((TSFlags >> 32) & X86II::VEX)
754 if ((TSFlags >> 32) & X86II::VEX_4V)
757 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
758 // in order to provide diffability.
761 EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
763 EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
765 // If this is a two-address instruction, skip one of the register operands.
766 unsigned NumOps = Desc.getNumOperands();
768 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
770 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
771 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
774 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
775 unsigned SrcRegNum = 0;
776 switch (TSFlags & X86II::FormMask) {
777 case X86II::MRMInitReg:
778 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
779 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
780 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
781 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
783 EmitByte(BaseOpcode, CurByte, OS);
786 case X86II::AddRegFrm:
787 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
790 case X86II::MRMDestReg:
791 EmitByte(BaseOpcode, CurByte, OS);
792 EmitRegModRMByte(MI.getOperand(CurOp),
793 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
797 case X86II::MRMDestMem:
798 EmitSegmentOverridePrefix(MI.getOperand(CurOp + 4), TSFlags, CurByte, OS);
799 EmitByte(BaseOpcode, CurByte, OS);
800 EmitMemModRMByte(MI, CurOp,
801 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
802 TSFlags, CurByte, OS, Fixups);
803 CurOp += X86AddrNumOperands + 1;
806 case X86II::MRMSrcReg:
807 EmitByte(BaseOpcode, CurByte, OS);
808 SrcRegNum = CurOp + 1;
810 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
813 EmitRegModRMByte(MI.getOperand(SrcRegNum),
814 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
815 CurOp = SrcRegNum + 1;
818 case X86II::MRMSrcMem: {
819 int AddrOperands = X86AddrNumOperands;
820 unsigned FirstMemOp = CurOp+1;
823 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
826 // FIXME: Maybe lea should have its own form? This is a horrible hack.
827 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
828 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
829 --AddrOperands; // No segment register
831 EmitSegmentOverridePrefix(MI.getOperand(FirstMemOp+4),
832 TSFlags, CurByte, OS);
834 EmitByte(BaseOpcode, CurByte, OS);
837 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
838 TSFlags, CurByte, OS, Fixups);
839 CurOp += AddrOperands + 1;
843 case X86II::MRM0r: case X86II::MRM1r:
844 case X86II::MRM2r: case X86II::MRM3r:
845 case X86II::MRM4r: case X86II::MRM5r:
846 case X86II::MRM6r: case X86II::MRM7r:
847 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
849 EmitByte(BaseOpcode, CurByte, OS);
850 EmitRegModRMByte(MI.getOperand(CurOp++),
851 (TSFlags & X86II::FormMask)-X86II::MRM0r,
854 case X86II::MRM0m: case X86II::MRM1m:
855 case X86II::MRM2m: case X86II::MRM3m:
856 case X86II::MRM4m: case X86II::MRM5m:
857 case X86II::MRM6m: case X86II::MRM7m:
858 EmitSegmentOverridePrefix(MI.getOperand(CurOp+4), TSFlags, CurByte, OS);
859 EmitByte(BaseOpcode, CurByte, OS);
860 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
861 TSFlags, CurByte, OS, Fixups);
862 CurOp += X86AddrNumOperands;
865 EmitByte(BaseOpcode, CurByte, OS);
866 EmitByte(0xC1, CurByte, OS);
869 EmitByte(BaseOpcode, CurByte, OS);
870 EmitByte(0xC2, CurByte, OS);
873 EmitByte(BaseOpcode, CurByte, OS);
874 EmitByte(0xC3, CurByte, OS);
877 EmitByte(BaseOpcode, CurByte, OS);
878 EmitByte(0xC4, CurByte, OS);
881 EmitByte(BaseOpcode, CurByte, OS);
882 EmitByte(0xC8, CurByte, OS);
885 EmitByte(BaseOpcode, CurByte, OS);
886 EmitByte(0xC9, CurByte, OS);
889 EmitByte(BaseOpcode, CurByte, OS);
890 EmitByte(0xE8, CurByte, OS);
893 EmitByte(BaseOpcode, CurByte, OS);
894 EmitByte(0xF0, CurByte, OS);
897 EmitByte(BaseOpcode, CurByte, OS);
898 EmitByte(0xF8, CurByte, OS);
901 EmitByte(BaseOpcode, CurByte, OS);
902 EmitByte(0xF9, CurByte, OS);
906 // If there is a remaining operand, it must be a trailing immediate. Emit it
907 // according to the right size for the instruction.
909 EmitImmediate(MI.getOperand(CurOp++),
910 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
911 CurByte, OS, Fixups);
915 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
916 errs() << "Cannot encode all operands of: ";