1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCSymbol.h"
22 #include "llvm/Support/raw_ostream.h"
26 class X86MCCodeEmitter : public MCCodeEmitter {
27 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
29 const TargetMachine &TM;
30 const TargetInstrInfo &TII;
34 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
35 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
36 Is64BitMode = is64Bit;
39 ~X86MCCodeEmitter() {}
41 unsigned getNumFixupKinds() const {
45 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
46 const static MCFixupKindInfo Infos[] = {
47 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel },
50 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
52 { "reloc_signed_4byte", 0, 4 * 8, 0},
53 { "reloc_global_offset_table", 0, 4 * 8, 0}
56 if (Kind < FirstTargetFixupKind)
57 return MCCodeEmitter::getFixupKindInfo(Kind);
59 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
61 return Infos[Kind - FirstTargetFixupKind];
64 static unsigned GetX86RegNum(const MCOperand &MO) {
65 return X86RegisterInfo::getX86RegNum(MO.getReg());
68 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
69 // 0-7 and the difference between the 2 groups is given by the REX prefix.
70 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
71 // in 1's complement form, example:
73 // ModRM field => XMM9 => 1
74 // VEX.VVVV => XMM9 => ~9
76 // See table 4-35 of Intel AVX Programming Reference for details.
77 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
79 unsigned SrcReg = MI.getOperand(OpNum).getReg();
80 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
81 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
82 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
85 // The registers represented through VEX_VVVV should
86 // be encoded in 1's complement form.
87 return (~SrcRegNum) & 0xf;
90 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
95 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
96 raw_ostream &OS) const {
97 // Output the constant in little endian byte order.
98 for (unsigned i = 0; i != Size; ++i) {
99 EmitByte(Val & 255, CurByte, OS);
104 void EmitImmediate(const MCOperand &Disp,
105 unsigned ImmSize, MCFixupKind FixupKind,
106 unsigned &CurByte, raw_ostream &OS,
107 SmallVectorImpl<MCFixup> &Fixups,
108 int ImmOffset = 0) const;
110 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
112 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
113 return RM | (RegOpcode << 3) | (Mod << 6);
116 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
117 unsigned &CurByte, raw_ostream &OS) const {
118 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
121 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
122 unsigned &CurByte, raw_ostream &OS) const {
123 // SIB byte is in the same format as the ModRMByte.
124 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
128 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
129 unsigned RegOpcodeField,
130 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
131 SmallVectorImpl<MCFixup> &Fixups) const;
133 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
134 SmallVectorImpl<MCFixup> &Fixups) const;
136 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
137 const MCInst &MI, const TargetInstrDesc &Desc,
138 raw_ostream &OS) const;
140 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
141 int MemOperand, const MCInst &MI,
142 raw_ostream &OS) const;
144 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
145 const MCInst &MI, const TargetInstrDesc &Desc,
146 raw_ostream &OS) const;
149 } // end anonymous namespace
152 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
155 return new X86MCCodeEmitter(TM, Ctx, false);
158 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
161 return new X86MCCodeEmitter(TM, Ctx, true);
164 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
165 /// sign-extended field.
166 static bool isDisp8(int Value) {
167 return Value == (signed char)Value;
170 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
171 /// in an instruction with the specified TSFlags.
172 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
173 unsigned Size = X86II::getSizeOfImm(TSFlags);
174 bool isPCRel = X86II::isImmPCRel(TSFlags);
177 default: assert(0 && "Unknown immediate size");
178 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
179 case 2: return isPCRel ? MCFixupKind(X86::reloc_pcrel_2byte) : FK_Data_2;
180 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
181 case 8: assert(!isPCRel); return FK_Data_8;
185 /// Is32BitMemOperand - Return true if the specified instruction with a memory
186 /// operand should emit the 0x67 prefix byte in 64-bit mode due to a 32-bit
187 /// memory operand. Op specifies the operand # of the memoperand.
188 static bool Is32BitMemOperand(const MCInst &MI, unsigned Op) {
189 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
190 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
192 if ((BaseReg.getReg() != 0 && X86::GR32RegClass.contains(BaseReg.getReg())) ||
193 (IndexReg.getReg() != 0 && X86::GR32RegClass.contains(IndexReg.getReg())))
198 /// StartsWithGlobalOffsetTable - Return true for the simple cases where this
199 /// expression starts with _GLOBAL_OFFSET_TABLE_. This is a needed to support
200 /// PIC on ELF i386 as that symbol is magic. We check only simple case that
201 /// are know to be used: _GLOBAL_OFFSET_TABLE_ by itself or at the start
202 /// of a binary expression.
203 static bool StartsWithGlobalOffsetTable(const MCExpr *Expr) {
204 if (Expr->getKind() == MCExpr::Binary) {
205 const MCBinaryExpr *BE = static_cast<const MCBinaryExpr *>(Expr);
209 if (Expr->getKind() != MCExpr::SymbolRef)
212 const MCSymbolRefExpr *Ref = static_cast<const MCSymbolRefExpr*>(Expr);
213 const MCSymbol &S = Ref->getSymbol();
214 return S.getName() == "_GLOBAL_OFFSET_TABLE_";
217 void X86MCCodeEmitter::
218 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
219 unsigned &CurByte, raw_ostream &OS,
220 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
221 // If this is a simple integer displacement that doesn't require a relocation,
223 if (DispOp.isImm()) {
224 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
226 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
230 // If we have an immoffset, add it to the expression.
231 const MCExpr *Expr = DispOp.getExpr();
233 if (FixupKind == FK_Data_4 && StartsWithGlobalOffsetTable(Expr)) {
234 assert(ImmOffset == 0);
236 FixupKind = MCFixupKind(X86::reloc_global_offset_table);
240 // If the fixup is pc-relative, we need to bias the value to be relative to
241 // the start of the field, not the end of the field.
242 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
243 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
244 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
246 if (FixupKind == MCFixupKind(X86::reloc_pcrel_2byte))
248 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
252 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
255 // Emit a symbolic constant as a fixup and 4 zeros.
256 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
257 EmitConstant(0, Size, CurByte, OS);
260 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
261 unsigned RegOpcodeField,
262 uint64_t TSFlags, unsigned &CurByte,
264 SmallVectorImpl<MCFixup> &Fixups) const{
265 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
266 const MCOperand &Base = MI.getOperand(Op+X86::AddrBaseReg);
267 const MCOperand &Scale = MI.getOperand(Op+X86::AddrScaleAmt);
268 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
269 unsigned BaseReg = Base.getReg();
271 // Handle %rip relative addressing.
272 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
273 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
274 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
275 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
277 unsigned FixupKind = X86::reloc_riprel_4byte;
279 // movq loads are handled with a special relocation form which allows the
280 // linker to eliminate some loads for GOT references which end up in the
281 // same linkage unit.
282 if (MI.getOpcode() == X86::MOV64rm)
283 FixupKind = X86::reloc_riprel_4byte_movq_load;
285 // rip-relative addressing is actually relative to the *next* instruction.
286 // Since an immediate can follow the mod/rm byte for an instruction, this
287 // means that we need to bias the immediate field of the instruction with
288 // the size of the immediate field. If we have this case, add it into the
289 // expression to emit.
290 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
292 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
293 CurByte, OS, Fixups, -ImmSize);
297 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
299 // Determine whether a SIB byte is needed.
300 // If no BaseReg, issue a RIP relative instruction only if the MCE can
301 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
302 // 2-7) and absolute references.
304 if (// The SIB byte must be used if there is an index register.
305 IndexReg.getReg() == 0 &&
306 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
307 // encode to an R/M value of 4, which indicates that a SIB byte is
309 BaseRegNo != N86::ESP &&
310 // If there is no base register and we're in 64-bit mode, we need a SIB
311 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
312 (!Is64BitMode || BaseReg != 0)) {
314 if (BaseReg == 0) { // [disp32] in X86-32 mode
315 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
316 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
320 // If the base is not EBP/ESP and there is no displacement, use simple
321 // indirect register encoding, this handles addresses like [EAX]. The
322 // encoding for [EBP] with no displacement means [disp32] so we handle it
323 // by emitting a displacement of 0 below.
324 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
325 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
329 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
330 if (Disp.isImm() && isDisp8(Disp.getImm())) {
331 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
332 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
336 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
337 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
338 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
343 // We need a SIB byte, so start by outputting the ModR/M byte first
344 assert(IndexReg.getReg() != X86::ESP &&
345 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
347 bool ForceDisp32 = false;
348 bool ForceDisp8 = false;
350 // If there is no base register, we emit the special case SIB byte with
351 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
352 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
354 } else if (!Disp.isImm()) {
355 // Emit the normal disp32 encoding.
356 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
358 } else if (Disp.getImm() == 0 &&
359 // Base reg can't be anything that ends up with '5' as the base
360 // reg, it is the magic [*] nomenclature that indicates no base.
361 BaseRegNo != N86::EBP) {
362 // Emit no displacement ModR/M byte
363 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
364 } else if (isDisp8(Disp.getImm())) {
365 // Emit the disp8 encoding.
366 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
367 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
369 // Emit the normal disp32 encoding.
370 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
373 // Calculate what the SS field value should be...
374 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
375 unsigned SS = SSTable[Scale.getImm()];
378 // Handle the SIB byte for the case where there is no base, see Intel
379 // Manual 2A, table 2-7. The displacement has already been output.
381 if (IndexReg.getReg())
382 IndexRegNo = GetX86RegNum(IndexReg);
383 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
385 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
388 if (IndexReg.getReg())
389 IndexRegNo = GetX86RegNum(IndexReg);
391 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
392 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
395 // Do we need to output a displacement?
397 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
398 else if (ForceDisp32 || Disp.getImm() != 0)
399 EmitImmediate(Disp, 4, MCFixupKind(X86::reloc_signed_4byte), CurByte, OS,
403 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
405 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
406 int MemOperand, const MCInst &MI,
407 const TargetInstrDesc &Desc,
408 raw_ostream &OS) const {
409 bool HasVEX_4V = false;
410 if ((TSFlags >> 32) & X86II::VEX_4V)
413 // VEX_R: opcode externsion equivalent to REX.R in
414 // 1's complement (inverted) form
416 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
417 // 0: Same as REX_R=1 (64 bit mode only)
419 unsigned char VEX_R = 0x1;
421 // VEX_X: equivalent to REX.X, only used when a
422 // register is used for index in SIB Byte.
424 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
425 // 0: Same as REX.X=1 (64-bit mode only)
426 unsigned char VEX_X = 0x1;
430 // 1: Same as REX_B=0 (ignored in 32-bit mode)
431 // 0: Same as REX_B=1 (64 bit mode only)
433 unsigned char VEX_B = 0x1;
435 // VEX_W: opcode specific (use like REX.W, or used for
436 // opcode extension, or ignored, depending on the opcode byte)
437 unsigned char VEX_W = 0;
439 // VEX_5M (VEX m-mmmmm field):
441 // 0b00000: Reserved for future use
442 // 0b00001: implied 0F leading opcode
443 // 0b00010: implied 0F 38 leading opcode bytes
444 // 0b00011: implied 0F 3A leading opcode bytes
445 // 0b00100-0b11111: Reserved for future use
447 unsigned char VEX_5M = 0x1;
449 // VEX_4V (VEX vvvv field): a register specifier
450 // (in 1's complement form) or 1111 if unused.
451 unsigned char VEX_4V = 0xf;
453 // VEX_L (Vector Length):
455 // 0: scalar or 128-bit vector
458 unsigned char VEX_L = 0;
460 // VEX_PP: opcode extension providing equivalent
461 // functionality of a SIMD prefix
468 unsigned char VEX_PP = 0;
470 // Encode the operand size opcode prefix as needed.
471 if (TSFlags & X86II::OpSize)
474 if ((TSFlags >> 32) & X86II::VEX_W)
477 if ((TSFlags >> 32) & X86II::VEX_L)
480 switch (TSFlags & X86II::Op0Mask) {
481 default: assert(0 && "Invalid prefix!");
482 case X86II::T8: // 0F 38
485 case X86II::TA: // 0F 3A
488 case X86II::TF: // F2 0F 38
492 case X86II::XS: // F3 0F
495 case X86II::XD: // F2 0F
498 case X86II::TB: // Bypass: Not used by VEX
503 // Set the vector length to 256-bit if YMM0-YMM15 is used
504 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
505 if (!MI.getOperand(i).isReg())
507 unsigned SrcReg = MI.getOperand(i).getReg();
508 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
512 unsigned NumOps = MI.getNumOperands();
514 bool IsDestMem = false;
516 switch (TSFlags & X86II::FormMask) {
517 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
518 case X86II::MRMDestMem:
520 // The important info for the VEX prefix is never beyond the address
521 // registers. Don't check beyond that.
522 NumOps = CurOp = X86::AddrNumOperands;
523 case X86II::MRM0m: case X86II::MRM1m:
524 case X86II::MRM2m: case X86II::MRM3m:
525 case X86II::MRM4m: case X86II::MRM5m:
526 case X86II::MRM6m: case X86II::MRM7m:
527 case X86II::MRMSrcMem:
528 case X86II::MRMSrcReg:
529 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
530 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
535 VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
539 // To only check operands before the memory address ones, start
540 // the search from the begining
544 // If the last register should be encoded in the immediate field
545 // do not use any bit from VEX prefix to this register, ignore it
546 if ((TSFlags >> 32) & X86II::VEX_I8IMM)
549 for (; CurOp != NumOps; ++CurOp) {
550 const MCOperand &MO = MI.getOperand(CurOp);
551 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
553 if (!VEX_B && MO.isReg() &&
554 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
555 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
559 default: // MRMDestReg, MRM0r-MRM7r, RawFrm
560 if (!MI.getNumOperands())
563 if (MI.getOperand(CurOp).isReg() &&
564 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
568 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
571 for (; CurOp != NumOps; ++CurOp) {
572 const MCOperand &MO = MI.getOperand(CurOp);
573 if (MO.isReg() && !HasVEX_4V &&
574 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
580 // Emit segment override opcode prefix as needed.
581 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
583 // VEX opcode prefix can have 2 or 3 bytes
586 // +-----+ +--------------+ +-------------------+
587 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
588 // +-----+ +--------------+ +-------------------+
590 // +-----+ +-------------------+
591 // | C5h | | R | vvvv | L | pp |
592 // +-----+ +-------------------+
594 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
596 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
597 EmitByte(0xC5, CurByte, OS);
598 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
603 EmitByte(0xC4, CurByte, OS);
604 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
605 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
608 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
609 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
610 /// size, and 3) use of X86-64 extended registers.
611 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
612 const TargetInstrDesc &Desc) {
614 if (TSFlags & X86II::REX_W)
615 REX |= 1 << 3; // set REX.W
617 if (MI.getNumOperands() == 0) return REX;
619 unsigned NumOps = MI.getNumOperands();
620 // FIXME: MCInst should explicitize the two-addrness.
621 bool isTwoAddr = NumOps > 1 &&
622 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
624 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
625 unsigned i = isTwoAddr ? 1 : 0;
626 for (; i != NumOps; ++i) {
627 const MCOperand &MO = MI.getOperand(i);
628 if (!MO.isReg()) continue;
629 unsigned Reg = MO.getReg();
630 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
631 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
632 // that returns non-zero.
633 REX |= 0x40; // REX fixed encoding prefix
637 switch (TSFlags & X86II::FormMask) {
638 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
639 case X86II::MRMSrcReg:
640 if (MI.getOperand(0).isReg() &&
641 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
642 REX |= 1 << 2; // set REX.R
643 i = isTwoAddr ? 2 : 1;
644 for (; i != NumOps; ++i) {
645 const MCOperand &MO = MI.getOperand(i);
646 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
647 REX |= 1 << 0; // set REX.B
650 case X86II::MRMSrcMem: {
651 if (MI.getOperand(0).isReg() &&
652 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
653 REX |= 1 << 2; // set REX.R
655 i = isTwoAddr ? 2 : 1;
656 for (; i != NumOps; ++i) {
657 const MCOperand &MO = MI.getOperand(i);
659 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
660 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
666 case X86II::MRM0m: case X86II::MRM1m:
667 case X86II::MRM2m: case X86II::MRM3m:
668 case X86II::MRM4m: case X86II::MRM5m:
669 case X86II::MRM6m: case X86II::MRM7m:
670 case X86II::MRMDestMem: {
671 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
672 i = isTwoAddr ? 1 : 0;
673 if (NumOps > e && MI.getOperand(e).isReg() &&
674 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
675 REX |= 1 << 2; // set REX.R
677 for (; i != e; ++i) {
678 const MCOperand &MO = MI.getOperand(i);
680 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
681 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
688 if (MI.getOperand(0).isReg() &&
689 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
690 REX |= 1 << 0; // set REX.B
691 i = isTwoAddr ? 2 : 1;
692 for (unsigned e = NumOps; i != e; ++i) {
693 const MCOperand &MO = MI.getOperand(i);
694 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
695 REX |= 1 << 2; // set REX.R
702 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
703 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
704 unsigned &CurByte, int MemOperand,
706 raw_ostream &OS) const {
707 switch (TSFlags & X86II::SegOvrMask) {
708 default: assert(0 && "Invalid segment!");
710 // No segment override, check for explicit one on memory operand.
711 if (MemOperand != -1) { // If the instruction has a memory operand.
712 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
713 default: assert(0 && "Unknown segment register!");
715 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
716 case X86::SS: EmitByte(0x36, CurByte, OS); break;
717 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
718 case X86::ES: EmitByte(0x26, CurByte, OS); break;
719 case X86::FS: EmitByte(0x64, CurByte, OS); break;
720 case X86::GS: EmitByte(0x65, CurByte, OS); break;
725 EmitByte(0x64, CurByte, OS);
728 EmitByte(0x65, CurByte, OS);
733 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
735 /// MemOperand is the operand # of the start of a memory operand if present. If
736 /// Not present, it is -1.
737 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
738 int MemOperand, const MCInst &MI,
739 const TargetInstrDesc &Desc,
740 raw_ostream &OS) const {
742 // Emit the lock opcode prefix as needed.
743 if (TSFlags & X86II::LOCK)
744 EmitByte(0xF0, CurByte, OS);
746 // Emit segment override opcode prefix as needed.
747 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
749 // Emit the repeat opcode prefix as needed.
750 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
751 EmitByte(0xF3, CurByte, OS);
753 // Emit the address size opcode prefix as needed.
754 if ((TSFlags & X86II::AdSize) ||
755 (MemOperand != -1 && Is64BitMode && Is32BitMemOperand(MI, MemOperand)))
756 EmitByte(0x67, CurByte, OS);
758 // Emit the operand size opcode prefix as needed.
759 if (TSFlags & X86II::OpSize)
760 EmitByte(0x66, CurByte, OS);
762 bool Need0FPrefix = false;
763 switch (TSFlags & X86II::Op0Mask) {
764 default: assert(0 && "Invalid prefix!");
765 case 0: break; // No prefix!
766 case X86II::REP: break; // already handled.
767 case X86II::TB: // Two-byte opcode prefix
768 case X86II::T8: // 0F 38
769 case X86II::TA: // 0F 3A
772 case X86II::TF: // F2 0F 38
773 EmitByte(0xF2, CurByte, OS);
776 case X86II::XS: // F3 0F
777 EmitByte(0xF3, CurByte, OS);
780 case X86II::XD: // F2 0F
781 EmitByte(0xF2, CurByte, OS);
784 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
785 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
786 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
787 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
788 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
789 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
790 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
791 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
794 // Handle REX prefix.
795 // FIXME: Can this come before F2 etc to simplify emission?
797 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
798 EmitByte(0x40 | REX, CurByte, OS);
801 // 0x0F escape code must be emitted just before the opcode.
803 EmitByte(0x0F, CurByte, OS);
805 // FIXME: Pull this up into previous switch if REX can be moved earlier.
806 switch (TSFlags & X86II::Op0Mask) {
807 case X86II::TF: // F2 0F 38
808 case X86II::T8: // 0F 38
809 EmitByte(0x38, CurByte, OS);
811 case X86II::TA: // 0F 3A
812 EmitByte(0x3A, CurByte, OS);
817 void X86MCCodeEmitter::
818 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
819 SmallVectorImpl<MCFixup> &Fixups) const {
820 unsigned Opcode = MI.getOpcode();
821 const TargetInstrDesc &Desc = TII.get(Opcode);
822 uint64_t TSFlags = Desc.TSFlags;
824 // Pseudo instructions don't get encoded.
825 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
828 // If this is a two-address instruction, skip one of the register operands.
829 // FIXME: This should be handled during MCInst lowering.
830 unsigned NumOps = Desc.getNumOperands();
832 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
834 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
835 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
838 // Keep track of the current byte being emitted.
839 unsigned CurByte = 0;
841 // Is this instruction encoded using the AVX VEX prefix?
842 bool HasVEXPrefix = false;
844 // It uses the VEX.VVVV field?
845 bool HasVEX_4V = false;
847 if ((TSFlags >> 32) & X86II::VEX)
849 if ((TSFlags >> 32) & X86II::VEX_4V)
853 // Determine where the memory operand starts, if present.
854 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
855 if (MemoryOperand != -1) MemoryOperand += CurOp;
858 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
860 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
863 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
865 if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
866 BaseOpcode = 0x0F; // Weird 3DNow! encoding.
868 unsigned SrcRegNum = 0;
869 switch (TSFlags & X86II::FormMask) {
870 case X86II::MRMInitReg:
871 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
872 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
873 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
875 assert(0 && "Pseudo instruction shouldn't be emitted");
877 EmitByte(BaseOpcode, CurByte, OS);
880 case X86II::RawFrmImm8:
881 EmitByte(BaseOpcode, CurByte, OS);
882 EmitImmediate(MI.getOperand(CurOp++),
883 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
884 CurByte, OS, Fixups);
885 EmitImmediate(MI.getOperand(CurOp++), 1, FK_Data_1, CurByte, OS, Fixups);
887 case X86II::RawFrmImm16:
888 EmitByte(BaseOpcode, CurByte, OS);
889 EmitImmediate(MI.getOperand(CurOp++),
890 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
891 CurByte, OS, Fixups);
892 EmitImmediate(MI.getOperand(CurOp++), 2, FK_Data_2, CurByte, OS, Fixups);
895 case X86II::AddRegFrm:
896 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
899 case X86II::MRMDestReg:
900 EmitByte(BaseOpcode, CurByte, OS);
901 EmitRegModRMByte(MI.getOperand(CurOp),
902 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
906 case X86II::MRMDestMem:
907 EmitByte(BaseOpcode, CurByte, OS);
908 SrcRegNum = CurOp + X86::AddrNumOperands;
910 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
913 EmitMemModRMByte(MI, CurOp,
914 GetX86RegNum(MI.getOperand(SrcRegNum)),
915 TSFlags, CurByte, OS, Fixups);
916 CurOp = SrcRegNum + 1;
919 case X86II::MRMSrcReg:
920 EmitByte(BaseOpcode, CurByte, OS);
921 SrcRegNum = CurOp + 1;
923 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
926 EmitRegModRMByte(MI.getOperand(SrcRegNum),
927 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
928 CurOp = SrcRegNum + 1;
931 case X86II::MRMSrcMem: {
932 int AddrOperands = X86::AddrNumOperands;
933 unsigned FirstMemOp = CurOp+1;
936 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
939 EmitByte(BaseOpcode, CurByte, OS);
941 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
942 TSFlags, CurByte, OS, Fixups);
943 CurOp += AddrOperands + 1;
947 case X86II::MRM0r: case X86II::MRM1r:
948 case X86II::MRM2r: case X86II::MRM3r:
949 case X86II::MRM4r: case X86II::MRM5r:
950 case X86II::MRM6r: case X86II::MRM7r:
951 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
953 EmitByte(BaseOpcode, CurByte, OS);
954 EmitRegModRMByte(MI.getOperand(CurOp++),
955 (TSFlags & X86II::FormMask)-X86II::MRM0r,
958 case X86II::MRM0m: case X86II::MRM1m:
959 case X86II::MRM2m: case X86II::MRM3m:
960 case X86II::MRM4m: case X86II::MRM5m:
961 case X86II::MRM6m: case X86II::MRM7m:
962 EmitByte(BaseOpcode, CurByte, OS);
963 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
964 TSFlags, CurByte, OS, Fixups);
965 CurOp += X86::AddrNumOperands;
968 EmitByte(BaseOpcode, CurByte, OS);
969 EmitByte(0xC1, CurByte, OS);
972 EmitByte(BaseOpcode, CurByte, OS);
973 EmitByte(0xC2, CurByte, OS);
976 EmitByte(BaseOpcode, CurByte, OS);
977 EmitByte(0xC3, CurByte, OS);
980 EmitByte(BaseOpcode, CurByte, OS);
981 EmitByte(0xC4, CurByte, OS);
984 EmitByte(BaseOpcode, CurByte, OS);
985 EmitByte(0xC8, CurByte, OS);
988 EmitByte(BaseOpcode, CurByte, OS);
989 EmitByte(0xC9, CurByte, OS);
992 EmitByte(BaseOpcode, CurByte, OS);
993 EmitByte(0xE8, CurByte, OS);
996 EmitByte(BaseOpcode, CurByte, OS);
997 EmitByte(0xF0, CurByte, OS);
1000 EmitByte(BaseOpcode, CurByte, OS);
1001 EmitByte(0xF8, CurByte, OS);
1004 EmitByte(BaseOpcode, CurByte, OS);
1005 EmitByte(0xF9, CurByte, OS);
1009 // If there is a remaining operand, it must be a trailing immediate. Emit it
1010 // according to the right size for the instruction.
1011 if (CurOp != NumOps) {
1012 // The last source register of a 4 operand instruction in AVX is encoded
1013 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
1014 if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
1015 const MCOperand &MO = MI.getOperand(CurOp++);
1017 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
1018 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
1019 RegNum |= GetX86RegNum(MO) << 4;
1020 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
1024 if (MI.getOpcode() == X86::MOV64ri32 || MI.getOpcode() == X86::MOV64mi32)
1025 FixupKind = X86::reloc_signed_4byte;
1027 FixupKind = getImmFixupKind(TSFlags);
1028 EmitImmediate(MI.getOperand(CurOp++),
1029 X86II::getSizeOfImm(TSFlags), MCFixupKind(FixupKind),
1030 CurByte, OS, Fixups);
1034 if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
1035 EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
1040 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
1041 errs() << "Cannot encode all operands of: ";