1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 reloc_pcrel_4byte = FirstTargetFixupKind, // 32-bit pcrel, e.g. a branch.
27 reloc_pcrel_1byte // 8-bit pcrel, e.g. branch_1
33 class X86MCCodeEmitter : public MCCodeEmitter {
34 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
35 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
36 const TargetMachine &TM;
37 const TargetInstrInfo &TII;
40 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
41 : TM(tm), TII(*TM.getInstrInfo()) {
42 Is64BitMode = is64Bit;
45 ~X86MCCodeEmitter() {}
47 unsigned getNumFixupKinds() const {
51 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
52 const static MCFixupKindInfo Infos[] = {
53 { "reloc_pcrel_4byte", 0, 4 * 8 },
54 { "reloc_pcrel_1byte", 0, 1 * 8 }
57 if (Kind < FirstTargetFixupKind)
58 return MCCodeEmitter::getFixupKindInfo(Kind);
60 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
62 return Infos[Kind - FirstTargetFixupKind];
65 static unsigned GetX86RegNum(const MCOperand &MO) {
66 return X86RegisterInfo::getX86RegNum(MO.getReg());
69 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
74 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
75 raw_ostream &OS) const {
76 // Output the constant in little endian byte order.
77 for (unsigned i = 0; i != Size; ++i) {
78 EmitByte(Val & 255, CurByte, OS);
83 void EmitImmediate(const MCOperand &Disp,
84 unsigned ImmSize, MCFixupKind FixupKind,
85 unsigned &CurByte, raw_ostream &OS,
86 SmallVectorImpl<MCFixup> &Fixups) const;
88 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
90 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
91 return RM | (RegOpcode << 3) | (Mod << 6);
94 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
95 unsigned &CurByte, raw_ostream &OS) const {
96 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
99 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
100 unsigned &CurByte, raw_ostream &OS) const {
101 // SIB byte is in the same format as the ModRMByte.
102 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
106 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
107 unsigned RegOpcodeField,
108 unsigned &CurByte, raw_ostream &OS,
109 SmallVectorImpl<MCFixup> &Fixups) const;
111 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
112 SmallVectorImpl<MCFixup> &Fixups) const;
116 } // end anonymous namespace
119 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
121 return new X86MCCodeEmitter(TM, false);
124 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
126 return new X86MCCodeEmitter(TM, true);
130 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
131 /// sign-extended field.
132 static bool isDisp8(int Value) {
133 return Value == (signed char)Value;
136 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
137 /// in an instruction with the specified TSFlags.
138 static MCFixupKind getImmFixupKind(unsigned TSFlags) {
139 unsigned Size = X86II::getSizeOfImm(TSFlags);
140 bool isPCRel = X86II::isImmPCRel(TSFlags);
143 default: assert(0 && "Unknown immediate size");
144 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
145 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
146 case 2: assert(!isPCRel); return FK_Data_2;
147 case 8: assert(!isPCRel); return FK_Data_8;
152 void X86MCCodeEmitter::
153 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
154 unsigned &CurByte, raw_ostream &OS,
155 SmallVectorImpl<MCFixup> &Fixups) const {
156 // If this is a simple integer displacement that doesn't require a relocation,
158 if (DispOp.isImm()) {
159 EmitConstant(DispOp.getImm(), Size, CurByte, OS);
163 // Emit a symbolic constant as a fixup and 4 zeros.
164 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(), FixupKind));
165 EmitConstant(0, Size, CurByte, OS);
169 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
170 unsigned RegOpcodeField,
173 SmallVectorImpl<MCFixup> &Fixups) const{
174 const MCOperand &Disp = MI.getOperand(Op+3);
175 const MCOperand &Base = MI.getOperand(Op);
176 const MCOperand &Scale = MI.getOperand(Op+1);
177 const MCOperand &IndexReg = MI.getOperand(Op+2);
178 unsigned BaseReg = Base.getReg();
180 // Handle %rip relative addressing.
181 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
182 assert(IndexReg.getReg() == 0 && Is64BitMode &&
183 "Invalid rip-relative address");
184 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
185 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
189 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
191 // Determine whether a SIB byte is needed.
192 // If no BaseReg, issue a RIP relative instruction only if the MCE can
193 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
194 // 2-7) and absolute references.
196 if (// The SIB byte must be used if there is an index register.
197 IndexReg.getReg() == 0 &&
198 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
199 // encode to an R/M value of 4, which indicates that a SIB byte is
201 BaseRegNo != N86::ESP &&
202 // If there is no base register and we're in 64-bit mode, we need a SIB
203 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
204 (!Is64BitMode || BaseReg != 0)) {
206 if (BaseReg == 0) { // [disp32] in X86-32 mode
207 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
208 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
212 // If the base is not EBP/ESP and there is no displacement, use simple
213 // indirect register encoding, this handles addresses like [EAX]. The
214 // encoding for [EBP] with no displacement means [disp32] so we handle it
215 // by emitting a displacement of 0 below.
216 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
217 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
221 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
222 if (Disp.isImm() && isDisp8(Disp.getImm())) {
223 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
224 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
228 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
229 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
230 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
234 // We need a SIB byte, so start by outputting the ModR/M byte first
235 assert(IndexReg.getReg() != X86::ESP &&
236 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
238 bool ForceDisp32 = false;
239 bool ForceDisp8 = false;
241 // If there is no base register, we emit the special case SIB byte with
242 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
243 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
245 } else if (!Disp.isImm()) {
246 // Emit the normal disp32 encoding.
247 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
249 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
250 // Emit no displacement ModR/M byte
251 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
252 } else if (isDisp8(Disp.getImm())) {
253 // Emit the disp8 encoding.
254 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
255 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
257 // Emit the normal disp32 encoding.
258 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
261 // Calculate what the SS field value should be...
262 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
263 unsigned SS = SSTable[Scale.getImm()];
266 // Handle the SIB byte for the case where there is no base, see Intel
267 // Manual 2A, table 2-7. The displacement has already been output.
269 if (IndexReg.getReg())
270 IndexRegNo = GetX86RegNum(IndexReg);
271 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
273 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
276 if (IndexReg.getReg())
277 IndexRegNo = GetX86RegNum(IndexReg);
279 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
280 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
283 // Do we need to output a displacement?
285 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
286 else if (ForceDisp32 || Disp.getImm() != 0)
287 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
290 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
291 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
292 /// size, and 3) use of X86-64 extended registers.
293 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
294 const TargetInstrDesc &Desc) {
295 // Pseudo instructions shouldn't get here.
296 assert((TSFlags & X86II::FormMask) != X86II::Pseudo &&
297 "Can't encode pseudo instrs");
300 if (TSFlags & X86II::REX_W)
303 if (MI.getNumOperands() == 0) return REX;
305 unsigned NumOps = MI.getNumOperands();
306 // FIXME: MCInst should explicitize the two-addrness.
307 bool isTwoAddr = NumOps > 1 &&
308 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
310 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
311 unsigned i = isTwoAddr ? 1 : 0;
312 for (; i != NumOps; ++i) {
313 const MCOperand &MO = MI.getOperand(i);
314 if (!MO.isReg()) continue;
315 unsigned Reg = MO.getReg();
316 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
317 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
318 // that returns non-zero.
323 switch (TSFlags & X86II::FormMask) {
324 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
325 case X86II::MRMSrcReg:
326 if (MI.getOperand(0).isReg() &&
327 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
329 i = isTwoAddr ? 2 : 1;
330 for (; i != NumOps; ++i) {
331 const MCOperand &MO = MI.getOperand(i);
332 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
336 case X86II::MRMSrcMem: {
337 if (MI.getOperand(0).isReg() &&
338 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
341 i = isTwoAddr ? 2 : 1;
342 for (; i != NumOps; ++i) {
343 const MCOperand &MO = MI.getOperand(i);
345 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
352 case X86II::MRM0m: case X86II::MRM1m:
353 case X86II::MRM2m: case X86II::MRM3m:
354 case X86II::MRM4m: case X86II::MRM5m:
355 case X86II::MRM6m: case X86II::MRM7m:
356 case X86II::MRMDestMem: {
357 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
358 i = isTwoAddr ? 1 : 0;
359 if (NumOps > e && MI.getOperand(e).isReg() &&
360 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
363 for (; i != e; ++i) {
364 const MCOperand &MO = MI.getOperand(i);
366 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
374 if (MI.getOperand(0).isReg() &&
375 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
377 i = isTwoAddr ? 2 : 1;
378 for (unsigned e = NumOps; i != e; ++i) {
379 const MCOperand &MO = MI.getOperand(i);
380 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
388 void X86MCCodeEmitter::
389 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
390 SmallVectorImpl<MCFixup> &Fixups) const {
391 unsigned Opcode = MI.getOpcode();
392 const TargetInstrDesc &Desc = TII.get(Opcode);
393 unsigned TSFlags = Desc.TSFlags;
395 // Keep track of the current byte being emitted.
396 unsigned CurByte = 0;
398 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
399 // in order to provide diffability.
401 // Emit the lock opcode prefix as needed.
402 if (TSFlags & X86II::LOCK)
403 EmitByte(0xF0, CurByte, OS);
405 // Emit segment override opcode prefix as needed.
406 switch (TSFlags & X86II::SegOvrMask) {
407 default: assert(0 && "Invalid segment!");
408 case 0: break; // No segment override!
410 EmitByte(0x64, CurByte, OS);
413 EmitByte(0x65, CurByte, OS);
417 // Emit the repeat opcode prefix as needed.
418 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
419 EmitByte(0xF3, CurByte, OS);
421 // Emit the operand size opcode prefix as needed.
422 if (TSFlags & X86II::OpSize)
423 EmitByte(0x66, CurByte, OS);
425 // Emit the address size opcode prefix as needed.
426 if (TSFlags & X86II::AdSize)
427 EmitByte(0x67, CurByte, OS);
429 bool Need0FPrefix = false;
430 switch (TSFlags & X86II::Op0Mask) {
431 default: assert(0 && "Invalid prefix!");
432 case 0: break; // No prefix!
433 case X86II::REP: break; // already handled.
434 case X86II::TB: // Two-byte opcode prefix
435 case X86II::T8: // 0F 38
436 case X86II::TA: // 0F 3A
439 case X86II::TF: // F2 0F 38
440 EmitByte(0xF2, CurByte, OS);
443 case X86II::XS: // F3 0F
444 EmitByte(0xF3, CurByte, OS);
447 case X86II::XD: // F2 0F
448 EmitByte(0xF2, CurByte, OS);
451 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
452 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
453 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
454 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
455 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
456 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
457 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
458 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
461 // Handle REX prefix.
462 // FIXME: Can this come before F2 etc to simplify emission?
464 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
465 EmitByte(0x40 | REX, CurByte, OS);
468 // 0x0F escape code must be emitted just before the opcode.
470 EmitByte(0x0F, CurByte, OS);
472 // FIXME: Pull this up into previous switch if REX can be moved earlier.
473 switch (TSFlags & X86II::Op0Mask) {
474 case X86II::TF: // F2 0F 38
475 case X86II::T8: // 0F 38
476 EmitByte(0x38, CurByte, OS);
478 case X86II::TA: // 0F 3A
479 EmitByte(0x3A, CurByte, OS);
483 // If this is a two-address instruction, skip one of the register operands.
484 unsigned NumOps = Desc.getNumOperands();
486 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
488 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
489 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
492 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
493 switch (TSFlags & X86II::FormMask) {
494 case X86II::MRMInitReg:
495 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
496 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
497 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
499 EmitByte(BaseOpcode, CurByte, OS);
502 case X86II::AddRegFrm:
503 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
506 case X86II::MRMDestReg:
507 EmitByte(BaseOpcode, CurByte, OS);
508 EmitRegModRMByte(MI.getOperand(CurOp),
509 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
513 case X86II::MRMDestMem:
514 EmitByte(BaseOpcode, CurByte, OS);
515 EmitMemModRMByte(MI, CurOp,
516 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
517 CurByte, OS, Fixups);
518 CurOp += X86AddrNumOperands + 1;
521 case X86II::MRMSrcReg:
522 EmitByte(BaseOpcode, CurByte, OS);
523 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
528 case X86II::MRMSrcMem: {
529 EmitByte(BaseOpcode, CurByte, OS);
531 // FIXME: Maybe lea should have its own form? This is a horrible hack.
533 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
534 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
535 AddrOperands = X86AddrNumOperands - 1; // No segment register
537 AddrOperands = X86AddrNumOperands;
539 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
540 CurByte, OS, Fixups);
541 CurOp += AddrOperands + 1;
545 case X86II::MRM0r: case X86II::MRM1r:
546 case X86II::MRM2r: case X86II::MRM3r:
547 case X86II::MRM4r: case X86II::MRM5r:
548 case X86II::MRM6r: case X86II::MRM7r:
549 EmitByte(BaseOpcode, CurByte, OS);
551 // Special handling of lfence, mfence, monitor, and mwait.
552 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
553 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
554 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
555 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r,
556 Opcode == X86::MWAIT),
559 EmitRegModRMByte(MI.getOperand(CurOp++),
560 (TSFlags & X86II::FormMask)-X86II::MRM0r,
564 case X86II::MRM0m: case X86II::MRM1m:
565 case X86II::MRM2m: case X86II::MRM3m:
566 case X86II::MRM4m: case X86II::MRM5m:
567 case X86II::MRM6m: case X86II::MRM7m:
568 EmitByte(BaseOpcode, CurByte, OS);
569 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
570 CurByte, OS, Fixups);
571 CurOp += X86AddrNumOperands;
574 EmitByte(BaseOpcode, CurByte, OS);
575 EmitByte(0xC1, CurByte, OS);
578 EmitByte(BaseOpcode, CurByte, OS);
579 EmitByte(0xC8, CurByte, OS);
582 EmitByte(BaseOpcode, CurByte, OS);
583 EmitByte(0xC9, CurByte, OS);
586 EmitByte(BaseOpcode, CurByte, OS);
587 EmitByte(0xE8, CurByte, OS);
590 EmitByte(BaseOpcode, CurByte, OS);
591 EmitByte(0xF0, CurByte, OS);
595 // If there is a remaining operand, it must be a trailing immediate. Emit it
596 // according to the right size for the instruction.
597 // FIXME: This should pass in whether the value is pc relative or not. This
598 // information should be aquired from TSFlags as well.
600 EmitImmediate(MI.getOperand(CurOp++),
601 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
602 CurByte, OS, Fixups);
606 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
607 errs() << "Cannot encode all operands of: ";