1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
23 class X86MCCodeEmitter : public MCCodeEmitter {
24 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
25 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
26 const TargetMachine &TM;
27 const TargetInstrInfo &TII;
29 X86MCCodeEmitter(TargetMachine &tm)
30 : TM(tm), TII(*TM.getInstrInfo()) {
33 ~X86MCCodeEmitter() {}
35 static unsigned GetX86RegNum(const MCOperand &MO) {
36 return X86RegisterInfo::getX86RegNum(MO.getReg());
39 void EmitByte(unsigned char C, raw_ostream &OS) const {
43 void EmitConstant(uint64_t Val, unsigned Size, raw_ostream &OS) const {
44 // Output the constant in little endian byte order.
45 for (unsigned i = 0; i != Size; ++i) {
46 EmitByte(Val & 255, OS);
51 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
53 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
54 return RM | (RegOpcode << 3) | (Mod << 6);
57 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
58 raw_ostream &OS) const {
59 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), OS);
63 void EncodeInstruction(const MCInst &MI, raw_ostream &OS) const;
67 } // end anonymous namespace
70 MCCodeEmitter *llvm::createX86MCCodeEmitter(const Target &,
72 return new X86MCCodeEmitter(TM);
77 void X86MCCodeEmitter::
78 EncodeInstruction(const MCInst &MI, raw_ostream &OS) const {
79 unsigned Opcode = MI.getOpcode();
80 const TargetInstrDesc &Desc = TII.get(Opcode);
81 unsigned TSFlags = Desc.TSFlags;
83 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
84 // in order to provide diffability.
86 // Emit the lock opcode prefix as needed.
87 if (TSFlags & X86II::LOCK)
90 // Emit segment override opcode prefix as needed.
91 switch (TSFlags & X86II::SegOvrMask) {
92 default: assert(0 && "Invalid segment!");
93 case 0: break; // No segment override!
102 // Emit the repeat opcode prefix as needed.
103 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
106 // Emit the operand size opcode prefix as needed.
107 if (TSFlags & X86II::OpSize)
110 // Emit the address size opcode prefix as needed.
111 if (TSFlags & X86II::AdSize)
114 bool Need0FPrefix = false;
115 switch (TSFlags & X86II::Op0Mask) {
116 default: assert(0 && "Invalid prefix!");
117 case 0: break; // No prefix!
118 case X86II::REP: break; // already handled.
119 case X86II::TB: // Two-byte opcode prefix
120 case X86II::T8: // 0F 38
121 case X86II::TA: // 0F 3A
124 case X86II::TF: // F2 0F 38
128 case X86II::XS: // F3 0F
132 case X86II::XD: // F2 0F
136 case X86II::D8: EmitByte(0xD8, OS); break;
137 case X86II::D9: EmitByte(0xD9, OS); break;
138 case X86II::DA: EmitByte(0xDA, OS); break;
139 case X86II::DB: EmitByte(0xDB, OS); break;
140 case X86II::DC: EmitByte(0xDC, OS); break;
141 case X86II::DD: EmitByte(0xDD, OS); break;
142 case X86II::DE: EmitByte(0xDE, OS); break;
143 case X86II::DF: EmitByte(0xDF, OS); break;
146 // Handle REX prefix.
147 #if 0 // FIXME: Add in, also, can this come before F2 etc to simplify emission?
149 if (unsigned REX = X86InstrInfo::determineREX(MI))
150 EmitByte(0x40 | REX, OS);
154 // 0x0F escape code must be emitted just before the opcode.
158 // FIXME: Pull this up into previous switch if REX can be moved earlier.
159 switch (TSFlags & X86II::Op0Mask) {
160 case X86II::TF: // F2 0F 38
161 case X86II::T8: // 0F 38
164 case X86II::TA: // 0F 3A
169 // If this is a two-address instruction, skip one of the register operands.
170 unsigned NumOps = Desc.getNumOperands();
172 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
174 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
175 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
178 unsigned char BaseOpcode = X86InstrInfo::getBaseOpcodeFor(Desc);
179 switch (TSFlags & X86II::FormMask) {
180 default: assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
181 case X86II::RawFrm: {
182 EmitByte(BaseOpcode, OS);
187 assert(0 && "Unimpl RawFrm expr");
191 case X86II::AddRegFrm: {
192 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)),OS);
196 const MCOperand &MO1 = MI.getOperand(CurOp++);
198 unsigned Size = X86InstrInfo::sizeOfImm(&Desc);
199 EmitConstant(MO1.getImm(), Size, OS);
203 assert(0 && "Unimpl AddRegFrm expr");
207 case X86II::MRMDestReg:
208 EmitByte(BaseOpcode, OS);
209 EmitRegModRMByte(MI.getOperand(CurOp),
210 GetX86RegNum(MI.getOperand(CurOp+1)), OS);
213 EmitConstant(MI.getOperand(CurOp++).getImm(),
214 X86InstrInfo::sizeOfImm(&Desc), OS);
219 if (!Desc.isVariadic() && CurOp != NumOps) {
220 errs() << "Cannot encode all operands of: ";