1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/Support/raw_ostream.h"
22 // FIXME: This should move to a header.
26 reloc_pcrel_word = FirstTargetFixupKind,
29 reloc_absolute_word_sext,
36 class X86MCCodeEmitter : public MCCodeEmitter {
37 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
38 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
39 const TargetMachine &TM;
40 const TargetInstrInfo &TII;
43 X86MCCodeEmitter(TargetMachine &tm, bool is64Bit)
44 : TM(tm), TII(*TM.getInstrInfo()) {
45 Is64BitMode = is64Bit;
48 ~X86MCCodeEmitter() {}
50 unsigned getNumFixupKinds() const {
54 MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
55 static MCFixupKindInfo Infos[] = {
56 { "reloc_pcrel_word", 0, 4 * 8 },
57 { "reloc_picrel_word", 0, 4 * 8 },
58 { "reloc_absolute_word", 0, 4 * 8 },
59 { "reloc_absolute_word_sext", 0, 4 * 8 },
60 { "reloc_absolute_dword", 0, 8 * 8 }
63 assert(Kind >= FirstTargetFixupKind && Kind < MaxTargetFixupKind &&
65 return Infos[Kind - FirstTargetFixupKind];
68 static unsigned GetX86RegNum(const MCOperand &MO) {
69 return X86RegisterInfo::getX86RegNum(MO.getReg());
72 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
77 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
78 raw_ostream &OS) const {
79 // Output the constant in little endian byte order.
80 for (unsigned i = 0; i != Size; ++i) {
81 EmitByte(Val & 255, CurByte, OS);
86 void EmitDisplacementField(const MCOperand &Disp, int64_t Adj, bool IsPCRel,
87 unsigned &CurByte, raw_ostream &OS,
88 SmallVectorImpl<MCFixup> &Fixups) const;
90 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
92 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
93 return RM | (RegOpcode << 3) | (Mod << 6);
96 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
97 unsigned &CurByte, raw_ostream &OS) const {
98 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
101 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
102 unsigned &CurByte, raw_ostream &OS) const {
103 // SIB byte is in the same format as the ModRMByte.
104 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
108 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
109 unsigned RegOpcodeField, intptr_t PCAdj,
110 unsigned &CurByte, raw_ostream &OS,
111 SmallVectorImpl<MCFixup> &Fixups) const;
113 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
114 SmallVectorImpl<MCFixup> &Fixups) const;
118 } // end anonymous namespace
121 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
123 return new X86MCCodeEmitter(TM, false);
126 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
128 return new X86MCCodeEmitter(TM, true);
132 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
133 /// sign-extended field.
134 static bool isDisp8(int Value) {
135 return Value == (signed char)Value;
138 void X86MCCodeEmitter::
139 EmitDisplacementField(const MCOperand &DispOp, int64_t Adj, bool IsPCRel,
140 unsigned &CurByte, raw_ostream &OS,
141 SmallVectorImpl<MCFixup> &Fixups) const {
142 // If this is a simple integer displacement that doesn't require a relocation,
144 if (DispOp.isImm()) {
145 EmitConstant(DispOp.getImm(), 4, CurByte, OS);
150 // Otherwise, this is something that requires a relocation. Emit it as such
152 unsigned RelocType = Is64BitMode ?
153 (IsPCRel ? X86::reloc_pcrel_word : X86::reloc_absolute_word_sext)
154 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
157 // Emit a symbolic constant as a fixup and 4 zeros.
158 Fixups.push_back(MCFixup::Create(CurByte, DispOp.getExpr(),
159 MCFixupKind(X86::reloc_absolute_word)));
160 EmitConstant(0, 4, CurByte, OS);
164 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
165 unsigned RegOpcodeField,
169 SmallVectorImpl<MCFixup> &Fixups) const{
170 const MCOperand &Disp = MI.getOperand(Op+3);
171 const MCOperand &Base = MI.getOperand(Op);
172 const MCOperand &Scale = MI.getOperand(Op+1);
173 const MCOperand &IndexReg = MI.getOperand(Op+2);
174 unsigned BaseReg = Base.getReg();
177 bool IsPCRel = false;
179 // Determine whether a SIB byte is needed.
180 // If no BaseReg, issue a RIP relative instruction only if the MCE can
181 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
182 // 2-7) and absolute references.
183 if (// The SIB byte must be used if there is an index register.
184 IndexReg.getReg() == 0 &&
185 // The SIB byte must be used if the base is ESP/RSP.
186 BaseReg != X86::ESP && BaseReg != X86::RSP &&
187 // If there is no base register and we're in 64-bit mode, we need a SIB
188 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
189 (!Is64BitMode || BaseReg != 0)) {
191 if (BaseReg == 0 || // [disp32] in X86-32 mode
192 BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
193 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
194 EmitDisplacementField(Disp, PCAdj, true, CurByte, OS, Fixups);
198 unsigned BaseRegNo = GetX86RegNum(Base);
200 // If the base is not EBP/ESP and there is no displacement, use simple
201 // indirect register encoding, this handles addresses like [EAX]. The
202 // encoding for [EBP] with no displacement means [disp32] so we handle it
203 // by emitting a displacement of 0 below.
204 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
205 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
209 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
210 if (Disp.isImm() && isDisp8(Disp.getImm())) {
211 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
212 EmitConstant(Disp.getImm(), 1, CurByte, OS);
216 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
217 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
218 EmitDisplacementField(Disp, PCAdj, IsPCRel, CurByte, OS, Fixups);
222 // We need a SIB byte, so start by outputting the ModR/M byte first
223 assert(IndexReg.getReg() != X86::ESP &&
224 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
226 bool ForceDisp32 = false;
227 bool ForceDisp8 = false;
229 // If there is no base register, we emit the special case SIB byte with
230 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
231 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
233 } else if (!Disp.isImm()) {
234 // Emit the normal disp32 encoding.
235 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
237 } else if (Disp.getImm() == 0 && BaseReg != X86::EBP) {
238 // Emit no displacement ModR/M byte
239 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
240 } else if (isDisp8(Disp.getImm())) {
241 // Emit the disp8 encoding.
242 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
243 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
245 // Emit the normal disp32 encoding.
246 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
249 // Calculate what the SS field value should be...
250 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
251 unsigned SS = SSTable[Scale.getImm()];
254 // Handle the SIB byte for the case where there is no base, see Intel
255 // Manual 2A, table 2-7. The displacement has already been output.
257 if (IndexReg.getReg())
258 IndexRegNo = GetX86RegNum(IndexReg);
259 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
261 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
264 if (IndexReg.getReg())
265 IndexRegNo = GetX86RegNum(IndexReg);
267 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
268 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
271 // Do we need to output a displacement?
273 EmitConstant(Disp.getImm(), 1, CurByte, OS);
274 else if (ForceDisp32 || Disp.getImm() != 0)
275 EmitDisplacementField(Disp, PCAdj, IsPCRel, CurByte, OS, Fixups);
278 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
279 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
280 /// size, and 3) use of X86-64 extended registers.
281 static unsigned DetermineREXPrefix(const MCInst &MI, unsigned TSFlags,
282 const TargetInstrDesc &Desc) {
285 // Pseudo instructions do not need REX prefix byte.
286 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
288 if (TSFlags & X86II::REX_W)
291 if (MI.getNumOperands() == 0) return REX;
293 unsigned NumOps = MI.getNumOperands();
294 // FIXME: MCInst should explicitize the two-addrness.
295 bool isTwoAddr = NumOps > 1 &&
296 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
298 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
299 unsigned i = isTwoAddr ? 1 : 0;
300 for (; i != NumOps; ++i) {
301 const MCOperand &MO = MI.getOperand(i);
302 if (!MO.isReg()) continue;
303 unsigned Reg = MO.getReg();
304 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
305 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
306 // that returns non-zero.
311 switch (TSFlags & X86II::FormMask) {
312 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
313 case X86II::MRMSrcReg:
314 if (MI.getOperand(0).isReg() &&
315 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
317 i = isTwoAddr ? 2 : 1;
318 for (; i != NumOps; ++i) {
319 const MCOperand &MO = MI.getOperand(i);
320 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
324 case X86II::MRMSrcMem: {
325 if (MI.getOperand(0).isReg() &&
326 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
329 i = isTwoAddr ? 2 : 1;
330 for (; i != NumOps; ++i) {
331 const MCOperand &MO = MI.getOperand(i);
333 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
340 case X86II::MRM0m: case X86II::MRM1m:
341 case X86II::MRM2m: case X86II::MRM3m:
342 case X86II::MRM4m: case X86II::MRM5m:
343 case X86II::MRM6m: case X86II::MRM7m:
344 case X86II::MRMDestMem: {
345 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
346 i = isTwoAddr ? 1 : 0;
347 if (NumOps > e && MI.getOperand(e).isReg() &&
348 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
351 for (; i != e; ++i) {
352 const MCOperand &MO = MI.getOperand(i);
354 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
362 if (MI.getOperand(0).isReg() &&
363 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
365 i = isTwoAddr ? 2 : 1;
366 for (unsigned e = NumOps; i != e; ++i) {
367 const MCOperand &MO = MI.getOperand(i);
368 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
376 void X86MCCodeEmitter::
377 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
378 SmallVectorImpl<MCFixup> &Fixups) const {
379 unsigned Opcode = MI.getOpcode();
380 const TargetInstrDesc &Desc = TII.get(Opcode);
381 unsigned TSFlags = Desc.TSFlags;
383 // Keep track of the current byte being emitted.
384 unsigned CurByte = 0;
386 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
387 // in order to provide diffability.
389 // Emit the lock opcode prefix as needed.
390 if (TSFlags & X86II::LOCK)
391 EmitByte(0xF0, CurByte, OS);
393 // Emit segment override opcode prefix as needed.
394 switch (TSFlags & X86II::SegOvrMask) {
395 default: assert(0 && "Invalid segment!");
396 case 0: break; // No segment override!
398 EmitByte(0x64, CurByte, OS);
401 EmitByte(0x65, CurByte, OS);
405 // Emit the repeat opcode prefix as needed.
406 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
407 EmitByte(0xF3, CurByte, OS);
409 // Emit the operand size opcode prefix as needed.
410 if (TSFlags & X86II::OpSize)
411 EmitByte(0x66, CurByte, OS);
413 // Emit the address size opcode prefix as needed.
414 if (TSFlags & X86II::AdSize)
415 EmitByte(0x67, CurByte, OS);
417 bool Need0FPrefix = false;
418 switch (TSFlags & X86II::Op0Mask) {
419 default: assert(0 && "Invalid prefix!");
420 case 0: break; // No prefix!
421 case X86II::REP: break; // already handled.
422 case X86II::TB: // Two-byte opcode prefix
423 case X86II::T8: // 0F 38
424 case X86II::TA: // 0F 3A
427 case X86II::TF: // F2 0F 38
428 EmitByte(0xF2, CurByte, OS);
431 case X86II::XS: // F3 0F
432 EmitByte(0xF3, CurByte, OS);
435 case X86II::XD: // F2 0F
436 EmitByte(0xF2, CurByte, OS);
439 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
440 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
441 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
442 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
443 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
444 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
445 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
446 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
449 // Handle REX prefix.
450 // FIXME: Can this come before F2 etc to simplify emission?
452 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
453 EmitByte(0x40 | REX, CurByte, OS);
456 // 0x0F escape code must be emitted just before the opcode.
458 EmitByte(0x0F, CurByte, OS);
460 // FIXME: Pull this up into previous switch if REX can be moved earlier.
461 switch (TSFlags & X86II::Op0Mask) {
462 case X86II::TF: // F2 0F 38
463 case X86II::T8: // 0F 38
464 EmitByte(0x38, CurByte, OS);
466 case X86II::TA: // 0F 3A
467 EmitByte(0x3A, CurByte, OS);
471 // If this is a two-address instruction, skip one of the register operands.
472 unsigned NumOps = Desc.getNumOperands();
474 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
476 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
477 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
480 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
481 switch (TSFlags & X86II::FormMask) {
482 case X86II::MRMInitReg:
483 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
484 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
485 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
486 case X86II::RawFrm: {
487 EmitByte(BaseOpcode, CurByte, OS);
492 assert(0 && "Unimpl RawFrm expr");
496 case X86II::AddRegFrm: {
497 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
501 const MCOperand &MO1 = MI.getOperand(CurOp++);
503 unsigned Size = X86II::getSizeOfImm(TSFlags);
504 EmitConstant(MO1.getImm(), Size, CurByte, OS);
508 assert(0 && "Unimpl AddRegFrm expr");
512 case X86II::MRMDestReg:
513 EmitByte(BaseOpcode, CurByte, OS);
514 EmitRegModRMByte(MI.getOperand(CurOp),
515 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
518 EmitConstant(MI.getOperand(CurOp++).getImm(),
519 X86II::getSizeOfImm(TSFlags), CurByte, OS);
522 case X86II::MRMDestMem:
523 EmitByte(BaseOpcode, CurByte, OS);
524 EmitMemModRMByte(MI, CurOp,
525 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
526 0, CurByte, OS, Fixups);
527 CurOp += X86AddrNumOperands + 1;
529 EmitConstant(MI.getOperand(CurOp++).getImm(),
530 X86II::getSizeOfImm(TSFlags), CurByte, OS);
533 case X86II::MRMSrcReg:
534 EmitByte(BaseOpcode, CurByte, OS);
535 EmitRegModRMByte(MI.getOperand(CurOp+1), GetX86RegNum(MI.getOperand(CurOp)),
539 EmitConstant(MI.getOperand(CurOp++).getImm(),
540 X86II::getSizeOfImm(TSFlags), CurByte, OS);
543 case X86II::MRMSrcMem: {
544 EmitByte(BaseOpcode, CurByte, OS);
546 // FIXME: Maybe lea should have its own form? This is a horrible hack.
548 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
549 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
550 AddrOperands = X86AddrNumOperands - 1; // No segment register
552 AddrOperands = X86AddrNumOperands;
554 // FIXME: What is this actually doing?
555 intptr_t PCAdj = (CurOp + AddrOperands + 1 != NumOps) ?
556 X86II::getSizeOfImm(TSFlags) : 0;
558 EmitMemModRMByte(MI, CurOp+1, GetX86RegNum(MI.getOperand(CurOp)),
559 PCAdj, CurByte, OS, Fixups);
560 CurOp += AddrOperands + 1;
562 EmitConstant(MI.getOperand(CurOp++).getImm(),
563 X86II::getSizeOfImm(TSFlags), CurByte, OS);
567 case X86II::MRM0r: case X86II::MRM1r:
568 case X86II::MRM2r: case X86II::MRM3r:
569 case X86II::MRM4r: case X86II::MRM5r:
570 case X86II::MRM6r: case X86II::MRM7r: {
571 EmitByte(BaseOpcode, CurByte, OS);
573 // Special handling of lfence, mfence, monitor, and mwait.
574 // FIXME: This is terrible, they should get proper encoding bits in TSFlags.
575 if (Opcode == X86::LFENCE || Opcode == X86::MFENCE ||
576 Opcode == X86::MONITOR || Opcode == X86::MWAIT) {
577 EmitByte(ModRMByte(3, (TSFlags & X86II::FormMask)-X86II::MRM0r, 0),
582 case X86::MONITOR: EmitByte(0xC8, CurByte, OS); break;
583 case X86::MWAIT: EmitByte(0xC9, CurByte, OS); break;
586 EmitRegModRMByte(MI.getOperand(CurOp++),
587 (TSFlags & X86II::FormMask)-X86II::MRM0r,
594 const MCOperand &MO1 = MI.getOperand(CurOp++);
596 EmitConstant(MO1.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
600 assert(0 && "relo unimpl");
602 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
603 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
604 if (Opcode == X86::MOV64ri32)
605 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
606 if (MO1.isGlobal()) {
607 bool Indirect = gvNeedsNonLazyPtr(MO1, TM);
608 emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
610 } else if (MO1.isSymbol())
611 emitExternalSymbolAddress(MO1.getSymbolName(), rt);
612 else if (MO1.isCPI())
613 emitConstPoolAddress(MO1.getIndex(), rt);
614 else if (MO1.isJTI())
615 emitJumpTableAddress(MO1.getIndex(), rt);
619 case X86II::MRM0m: case X86II::MRM1m:
620 case X86II::MRM2m: case X86II::MRM3m:
621 case X86II::MRM4m: case X86II::MRM5m:
622 case X86II::MRM6m: case X86II::MRM7m: {
624 if (CurOp + X86AddrNumOperands != NumOps) {
625 if (MI.getOperand(CurOp+X86AddrNumOperands).isImm())
626 PCAdj = X86II::getSizeOfImm(TSFlags);
631 EmitByte(BaseOpcode, CurByte, OS);
632 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
633 PCAdj, CurByte, OS, Fixups);
634 CurOp += X86AddrNumOperands;
639 const MCOperand &MO = MI.getOperand(CurOp++);
641 EmitConstant(MO.getImm(), X86II::getSizeOfImm(TSFlags), CurByte, OS);
645 assert(0 && "relo not handled");
647 unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
648 : (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
649 if (Opcode == X86::MOV64mi32)
650 rt = X86::reloc_absolute_word_sext; // FIXME: add X86II flag?
652 bool Indirect = gvNeedsNonLazyPtr(MO, TM);
653 emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
655 } else if (MO.isSymbol())
656 emitExternalSymbolAddress(MO.getSymbolName(), rt);
658 emitConstPoolAddress(MO.getIndex(), rt);
660 emitJumpTableAddress(MO.getIndex(), rt);
668 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
669 errs() << "Cannot encode all operands of: ";