1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Support/Compiler.h"
26 class X86MCCodeEmitter : public MCCodeEmitter {
27 X86MCCodeEmitter(const X86MCCodeEmitter &) ATTRIBUTE_UNUSED; // DONT IMPLEMENT
28 void operator=(const X86MCCodeEmitter &) ATTRIBUTE_UNUSED; // DO NOT IMPLEMENT
29 const TargetMachine &TM;
30 const TargetInstrInfo &TII;
34 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
35 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
36 Is64BitMode = is64Bit;
39 ~X86MCCodeEmitter() {}
41 unsigned getNumFixupKinds() const {
45 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
46 const static MCFixupKindInfo Infos[] = {
47 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel },
50 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
51 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
54 if (Kind < FirstTargetFixupKind)
55 return MCCodeEmitter::getFixupKindInfo(Kind);
57 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
59 return Infos[Kind - FirstTargetFixupKind];
62 static unsigned GetX86RegNum(const MCOperand &MO) {
63 return X86RegisterInfo::getX86RegNum(MO.getReg());
66 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
67 // 0-7 and the difference between the 2 groups is given by the REX prefix.
68 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
69 // in 1's complement form, example:
71 // ModRM field => XMM9 => 1
72 // VEX.VVVV => XMM9 => ~9
74 // See table 4-35 of Intel AVX Programming Reference for details.
75 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
77 unsigned SrcReg = MI.getOperand(OpNum).getReg();
78 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
79 if ((SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15) ||
80 (SrcReg >= X86::YMM8 && SrcReg <= X86::YMM15))
83 // The registers represented through VEX_VVVV should
84 // be encoded in 1's complement form.
85 return (~SrcRegNum) & 0xf;
88 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
93 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
94 raw_ostream &OS) const {
95 // Output the constant in little endian byte order.
96 for (unsigned i = 0; i != Size; ++i) {
97 EmitByte(Val & 255, CurByte, OS);
102 void EmitImmediate(const MCOperand &Disp,
103 unsigned ImmSize, MCFixupKind FixupKind,
104 unsigned &CurByte, raw_ostream &OS,
105 SmallVectorImpl<MCFixup> &Fixups,
106 int ImmOffset = 0) const;
108 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
110 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
111 return RM | (RegOpcode << 3) | (Mod << 6);
114 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
115 unsigned &CurByte, raw_ostream &OS) const {
116 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
119 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
120 unsigned &CurByte, raw_ostream &OS) const {
121 // SIB byte is in the same format as the ModRMByte.
122 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
126 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
127 unsigned RegOpcodeField,
128 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
129 SmallVectorImpl<MCFixup> &Fixups) const;
131 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
132 SmallVectorImpl<MCFixup> &Fixups) const;
134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
135 const MCInst &MI, const TargetInstrDesc &Desc,
136 raw_ostream &OS) const;
138 void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte,
139 int MemOperand, const MCInst &MI,
140 raw_ostream &OS) const;
142 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand,
143 const MCInst &MI, const TargetInstrDesc &Desc,
144 raw_ostream &OS) const;
147 } // end anonymous namespace
150 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
153 return new X86MCCodeEmitter(TM, Ctx, false);
156 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
159 return new X86MCCodeEmitter(TM, Ctx, true);
162 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
163 /// sign-extended field.
164 static bool isDisp8(int Value) {
165 return Value == (signed char)Value;
168 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
169 /// in an instruction with the specified TSFlags.
170 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
171 unsigned Size = X86II::getSizeOfImm(TSFlags);
172 bool isPCRel = X86II::isImmPCRel(TSFlags);
175 default: assert(0 && "Unknown immediate size");
176 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
177 case 2: return isPCRel ? MCFixupKind(X86::reloc_pcrel_2byte) : FK_Data_2;
178 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
179 case 8: assert(!isPCRel); return FK_Data_8;
184 void X86MCCodeEmitter::
185 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
186 unsigned &CurByte, raw_ostream &OS,
187 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
188 // If this is a simple integer displacement that doesn't require a relocation,
190 if (DispOp.isImm()) {
191 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
193 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
197 // If we have an immoffset, add it to the expression.
198 const MCExpr *Expr = DispOp.getExpr();
200 // If the fixup is pc-relative, we need to bias the value to be relative to
201 // the start of the field, not the end of the field.
202 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
203 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
204 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
206 if (FixupKind == MCFixupKind(X86::reloc_pcrel_2byte))
208 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
212 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
215 // Emit a symbolic constant as a fixup and 4 zeros.
216 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
217 EmitConstant(0, Size, CurByte, OS);
220 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
221 unsigned RegOpcodeField,
222 uint64_t TSFlags, unsigned &CurByte,
224 SmallVectorImpl<MCFixup> &Fixups) const{
225 const MCOperand &Disp = MI.getOperand(Op+3);
226 const MCOperand &Base = MI.getOperand(Op);
227 const MCOperand &Scale = MI.getOperand(Op+1);
228 const MCOperand &IndexReg = MI.getOperand(Op+2);
229 unsigned BaseReg = Base.getReg();
231 // Handle %rip relative addressing.
232 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
233 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
234 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
235 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
237 unsigned FixupKind = X86::reloc_riprel_4byte;
239 // movq loads are handled with a special relocation form which allows the
240 // linker to eliminate some loads for GOT references which end up in the
241 // same linkage unit.
242 if (MI.getOpcode() == X86::MOV64rm ||
243 MI.getOpcode() == X86::MOV64rm_TC)
244 FixupKind = X86::reloc_riprel_4byte_movq_load;
246 // rip-relative addressing is actually relative to the *next* instruction.
247 // Since an immediate can follow the mod/rm byte for an instruction, this
248 // means that we need to bias the immediate field of the instruction with
249 // the size of the immediate field. If we have this case, add it into the
250 // expression to emit.
251 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
253 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
254 CurByte, OS, Fixups, -ImmSize);
258 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
260 // Determine whether a SIB byte is needed.
261 // If no BaseReg, issue a RIP relative instruction only if the MCE can
262 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
263 // 2-7) and absolute references.
265 if (// The SIB byte must be used if there is an index register.
266 IndexReg.getReg() == 0 &&
267 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
268 // encode to an R/M value of 4, which indicates that a SIB byte is
270 BaseRegNo != N86::ESP &&
271 // If there is no base register and we're in 64-bit mode, we need a SIB
272 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
273 (!Is64BitMode || BaseReg != 0)) {
275 if (BaseReg == 0) { // [disp32] in X86-32 mode
276 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
277 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
281 // If the base is not EBP/ESP and there is no displacement, use simple
282 // indirect register encoding, this handles addresses like [EAX]. The
283 // encoding for [EBP] with no displacement means [disp32] so we handle it
284 // by emitting a displacement of 0 below.
285 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
286 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
290 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
291 if (Disp.isImm() && isDisp8(Disp.getImm())) {
292 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
293 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
297 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
298 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
299 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
303 // We need a SIB byte, so start by outputting the ModR/M byte first
304 assert(IndexReg.getReg() != X86::ESP &&
305 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
307 bool ForceDisp32 = false;
308 bool ForceDisp8 = false;
310 // If there is no base register, we emit the special case SIB byte with
311 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
312 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
314 } else if (!Disp.isImm()) {
315 // Emit the normal disp32 encoding.
316 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
318 } else if (Disp.getImm() == 0 &&
319 // Base reg can't be anything that ends up with '5' as the base
320 // reg, it is the magic [*] nomenclature that indicates no base.
321 BaseRegNo != N86::EBP) {
322 // Emit no displacement ModR/M byte
323 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
324 } else if (isDisp8(Disp.getImm())) {
325 // Emit the disp8 encoding.
326 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
327 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
329 // Emit the normal disp32 encoding.
330 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
333 // Calculate what the SS field value should be...
334 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
335 unsigned SS = SSTable[Scale.getImm()];
338 // Handle the SIB byte for the case where there is no base, see Intel
339 // Manual 2A, table 2-7. The displacement has already been output.
341 if (IndexReg.getReg())
342 IndexRegNo = GetX86RegNum(IndexReg);
343 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
345 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
348 if (IndexReg.getReg())
349 IndexRegNo = GetX86RegNum(IndexReg);
351 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
352 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
355 // Do we need to output a displacement?
357 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
358 else if (ForceDisp32 || Disp.getImm() != 0)
359 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
362 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
364 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
365 int MemOperand, const MCInst &MI,
366 const TargetInstrDesc &Desc,
367 raw_ostream &OS) const {
368 bool HasVEX_4V = false;
369 if (TSFlags & X86II::VEX_4V)
372 // VEX_R: opcode externsion equivalent to REX.R in
373 // 1's complement (inverted) form
375 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
376 // 0: Same as REX_R=1 (64 bit mode only)
378 unsigned char VEX_R = 0x1;
380 // VEX_X: equivalent to REX.X, only used when a
381 // register is used for index in SIB Byte.
383 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
384 // 0: Same as REX.X=1 (64-bit mode only)
385 unsigned char VEX_X = 0x1;
389 // 1: Same as REX_B=0 (ignored in 32-bit mode)
390 // 0: Same as REX_B=1 (64 bit mode only)
392 unsigned char VEX_B = 0x1;
394 // VEX_W: opcode specific (use like REX.W, or used for
395 // opcode extension, or ignored, depending on the opcode byte)
396 unsigned char VEX_W = 0;
398 // VEX_5M (VEX m-mmmmm field):
400 // 0b00000: Reserved for future use
401 // 0b00001: implied 0F leading opcode
402 // 0b00010: implied 0F 38 leading opcode bytes
403 // 0b00011: implied 0F 3A leading opcode bytes
404 // 0b00100-0b11111: Reserved for future use
406 unsigned char VEX_5M = 0x1;
408 // VEX_4V (VEX vvvv field): a register specifier
409 // (in 1's complement form) or 1111 if unused.
410 unsigned char VEX_4V = 0xf;
412 // VEX_L (Vector Length):
414 // 0: scalar or 128-bit vector
417 unsigned char VEX_L = 0;
419 // VEX_PP: opcode extension providing equivalent
420 // functionality of a SIMD prefix
427 unsigned char VEX_PP = 0;
429 // Encode the operand size opcode prefix as needed.
430 if (TSFlags & X86II::OpSize)
433 if (TSFlags & X86II::VEX_W)
436 if (TSFlags & X86II::VEX_L)
439 switch (TSFlags & X86II::Op0Mask) {
440 default: assert(0 && "Invalid prefix!");
441 case X86II::T8: // 0F 38
444 case X86II::TA: // 0F 3A
447 case X86II::TF: // F2 0F 38
451 case X86II::XS: // F3 0F
454 case X86II::XD: // F2 0F
457 case X86II::TB: // Bypass: Not used by VEX
462 // Set the vector length to 256-bit if YMM0-YMM15 is used
463 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
464 if (!MI.getOperand(i).isReg())
466 unsigned SrcReg = MI.getOperand(i).getReg();
467 if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
471 unsigned NumOps = MI.getNumOperands();
473 bool IsDestMem = false;
475 switch (TSFlags & X86II::FormMask) {
476 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
477 case X86II::MRMDestMem:
479 // The important info for the VEX prefix is never beyond the address
480 // registers. Don't check beyond that.
481 NumOps = CurOp = X86::AddrNumOperands;
482 case X86II::MRM0m: case X86II::MRM1m:
483 case X86II::MRM2m: case X86II::MRM3m:
484 case X86II::MRM4m: case X86II::MRM5m:
485 case X86II::MRM6m: case X86II::MRM7m:
486 case X86II::MRMSrcMem:
487 case X86II::MRMSrcReg:
488 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
489 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
494 VEX_4V = getVEXRegisterEncoding(MI, IsDestMem ? CurOp-1 : CurOp);
498 // To only check operands before the memory address ones, start
499 // the search from the begining
503 // If the last register should be encoded in the immediate field
504 // do not use any bit from VEX prefix to this register, ignore it
505 if (TSFlags & X86II::VEX_I8IMM)
508 for (; CurOp != NumOps; ++CurOp) {
509 const MCOperand &MO = MI.getOperand(CurOp);
510 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
512 if (!VEX_B && MO.isReg() &&
513 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
514 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
518 default: // MRMDestReg, MRM0r-MRM7r, RawFrm
519 if (!MI.getNumOperands())
522 if (MI.getOperand(CurOp).isReg() &&
523 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
527 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
530 for (; CurOp != NumOps; ++CurOp) {
531 const MCOperand &MO = MI.getOperand(CurOp);
532 if (MO.isReg() && !HasVEX_4V &&
533 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
539 // Emit segment override opcode prefix as needed.
540 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
542 // VEX opcode prefix can have 2 or 3 bytes
545 // +-----+ +--------------+ +-------------------+
546 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
547 // +-----+ +--------------+ +-------------------+
549 // +-----+ +-------------------+
550 // | C5h | | R | vvvv | L | pp |
551 // +-----+ +-------------------+
553 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
555 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
556 EmitByte(0xC5, CurByte, OS);
557 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
562 EmitByte(0xC4, CurByte, OS);
563 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
564 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
567 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
568 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
569 /// size, and 3) use of X86-64 extended registers.
570 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
571 const TargetInstrDesc &Desc) {
573 if (TSFlags & X86II::REX_W)
574 REX |= 1 << 3; // set REX.W
576 if (MI.getNumOperands() == 0) return REX;
578 unsigned NumOps = MI.getNumOperands();
579 // FIXME: MCInst should explicitize the two-addrness.
580 bool isTwoAddr = NumOps > 1 &&
581 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
583 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
584 unsigned i = isTwoAddr ? 1 : 0;
585 for (; i != NumOps; ++i) {
586 const MCOperand &MO = MI.getOperand(i);
587 if (!MO.isReg()) continue;
588 unsigned Reg = MO.getReg();
589 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
590 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
591 // that returns non-zero.
592 REX |= 0x40; // REX fixed encoding prefix
596 switch (TSFlags & X86II::FormMask) {
597 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
598 case X86II::MRMSrcReg:
599 if (MI.getOperand(0).isReg() &&
600 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
601 REX |= 1 << 2; // set REX.R
602 i = isTwoAddr ? 2 : 1;
603 for (; i != NumOps; ++i) {
604 const MCOperand &MO = MI.getOperand(i);
605 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
606 REX |= 1 << 0; // set REX.B
609 case X86II::MRMSrcMem: {
610 if (MI.getOperand(0).isReg() &&
611 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
612 REX |= 1 << 2; // set REX.R
614 i = isTwoAddr ? 2 : 1;
615 for (; i != NumOps; ++i) {
616 const MCOperand &MO = MI.getOperand(i);
618 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
619 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
625 case X86II::MRM0m: case X86II::MRM1m:
626 case X86II::MRM2m: case X86II::MRM3m:
627 case X86II::MRM4m: case X86II::MRM5m:
628 case X86II::MRM6m: case X86II::MRM7m:
629 case X86II::MRMDestMem: {
630 unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
631 i = isTwoAddr ? 1 : 0;
632 if (NumOps > e && MI.getOperand(e).isReg() &&
633 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
634 REX |= 1 << 2; // set REX.R
636 for (; i != e; ++i) {
637 const MCOperand &MO = MI.getOperand(i);
639 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
640 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
647 if (MI.getOperand(0).isReg() &&
648 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
649 REX |= 1 << 0; // set REX.B
650 i = isTwoAddr ? 2 : 1;
651 for (unsigned e = NumOps; i != e; ++i) {
652 const MCOperand &MO = MI.getOperand(i);
653 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
654 REX |= 1 << 2; // set REX.R
661 /// EmitSegmentOverridePrefix - Emit segment override opcode prefix as needed
662 void X86MCCodeEmitter::EmitSegmentOverridePrefix(uint64_t TSFlags,
663 unsigned &CurByte, int MemOperand,
665 raw_ostream &OS) const {
666 switch (TSFlags & X86II::SegOvrMask) {
667 default: assert(0 && "Invalid segment!");
669 // No segment override, check for explicit one on memory operand.
670 if (MemOperand != -1) { // If the instruction has a memory operand.
671 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
672 default: assert(0 && "Unknown segment register!");
674 case X86::CS: EmitByte(0x2E, CurByte, OS); break;
675 case X86::SS: EmitByte(0x36, CurByte, OS); break;
676 case X86::DS: EmitByte(0x3E, CurByte, OS); break;
677 case X86::ES: EmitByte(0x26, CurByte, OS); break;
678 case X86::FS: EmitByte(0x64, CurByte, OS); break;
679 case X86::GS: EmitByte(0x65, CurByte, OS); break;
684 EmitByte(0x64, CurByte, OS);
687 EmitByte(0x65, CurByte, OS);
692 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
694 /// MemOperand is the operand # of the start of a memory operand if present. If
695 /// Not present, it is -1.
696 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
697 int MemOperand, const MCInst &MI,
698 const TargetInstrDesc &Desc,
699 raw_ostream &OS) const {
701 // Emit the lock opcode prefix as needed.
702 if (TSFlags & X86II::LOCK)
703 EmitByte(0xF0, CurByte, OS);
705 // Emit segment override opcode prefix as needed.
706 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS);
708 // Emit the repeat opcode prefix as needed.
709 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
710 EmitByte(0xF3, CurByte, OS);
712 // Emit the operand size opcode prefix as needed.
713 if (TSFlags & X86II::OpSize)
714 EmitByte(0x66, CurByte, OS);
716 // Emit the address size opcode prefix as needed.
717 if (TSFlags & X86II::AdSize)
718 EmitByte(0x67, CurByte, OS);
720 bool Need0FPrefix = false;
721 switch (TSFlags & X86II::Op0Mask) {
722 default: assert(0 && "Invalid prefix!");
723 case 0: break; // No prefix!
724 case X86II::REP: break; // already handled.
725 case X86II::TB: // Two-byte opcode prefix
726 case X86II::T8: // 0F 38
727 case X86II::TA: // 0F 3A
730 case X86II::TF: // F2 0F 38
731 EmitByte(0xF2, CurByte, OS);
734 case X86II::XS: // F3 0F
735 EmitByte(0xF3, CurByte, OS);
738 case X86II::XD: // F2 0F
739 EmitByte(0xF2, CurByte, OS);
742 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
743 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
744 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
745 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
746 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
747 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
748 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
749 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
752 // Handle REX prefix.
753 // FIXME: Can this come before F2 etc to simplify emission?
755 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
756 EmitByte(0x40 | REX, CurByte, OS);
759 // 0x0F escape code must be emitted just before the opcode.
761 EmitByte(0x0F, CurByte, OS);
763 // FIXME: Pull this up into previous switch if REX can be moved earlier.
764 switch (TSFlags & X86II::Op0Mask) {
765 case X86II::TF: // F2 0F 38
766 case X86II::T8: // 0F 38
767 EmitByte(0x38, CurByte, OS);
769 case X86II::TA: // 0F 3A
770 EmitByte(0x3A, CurByte, OS);
775 void X86MCCodeEmitter::
776 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
777 SmallVectorImpl<MCFixup> &Fixups) const {
778 unsigned Opcode = MI.getOpcode();
779 const TargetInstrDesc &Desc = TII.get(Opcode);
780 uint64_t TSFlags = Desc.TSFlags;
782 // Pseudo instructions don't get encoded.
783 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
786 // If this is a two-address instruction, skip one of the register operands.
787 // FIXME: This should be handled during MCInst lowering.
788 unsigned NumOps = Desc.getNumOperands();
790 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
792 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
793 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
796 // Keep track of the current byte being emitted.
797 unsigned CurByte = 0;
799 // Is this instruction encoded using the AVX VEX prefix?
800 bool HasVEXPrefix = false;
802 // It uses the VEX.VVVV field?
803 bool HasVEX_4V = false;
805 if (TSFlags & X86II::VEX)
807 if (TSFlags & X86II::VEX_4V)
810 // Determine where the memory operand starts, if present.
811 int MemoryOperand = X86II::getMemoryOperandNo(TSFlags);
812 if (MemoryOperand != -1) MemoryOperand += CurOp;
815 EmitOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
817 EmitVEXOpcodePrefix(TSFlags, CurByte, MemoryOperand, MI, Desc, OS);
819 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
820 unsigned SrcRegNum = 0;
821 switch (TSFlags & X86II::FormMask) {
822 case X86II::MRMInitReg:
823 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
824 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
825 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
827 assert(0 && "Pseudo instruction shouldn't be emitted");
829 EmitByte(BaseOpcode, CurByte, OS);
832 case X86II::AddRegFrm:
833 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
836 case X86II::MRMDestReg:
837 EmitByte(BaseOpcode, CurByte, OS);
838 EmitRegModRMByte(MI.getOperand(CurOp),
839 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
843 case X86II::MRMDestMem:
844 EmitByte(BaseOpcode, CurByte, OS);
845 SrcRegNum = CurOp + X86::AddrNumOperands;
847 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
850 EmitMemModRMByte(MI, CurOp,
851 GetX86RegNum(MI.getOperand(SrcRegNum)),
852 TSFlags, CurByte, OS, Fixups);
853 CurOp = SrcRegNum + 1;
856 case X86II::MRMSrcReg:
857 EmitByte(BaseOpcode, CurByte, OS);
858 SrcRegNum = CurOp + 1;
860 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
863 EmitRegModRMByte(MI.getOperand(SrcRegNum),
864 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
865 CurOp = SrcRegNum + 1;
868 case X86II::MRMSrcMem: {
869 int AddrOperands = X86::AddrNumOperands;
870 unsigned FirstMemOp = CurOp+1;
873 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
876 EmitByte(BaseOpcode, CurByte, OS);
878 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
879 TSFlags, CurByte, OS, Fixups);
880 CurOp += AddrOperands + 1;
884 case X86II::MRM0r: case X86II::MRM1r:
885 case X86II::MRM2r: case X86II::MRM3r:
886 case X86II::MRM4r: case X86II::MRM5r:
887 case X86II::MRM6r: case X86II::MRM7r:
888 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
890 EmitByte(BaseOpcode, CurByte, OS);
891 EmitRegModRMByte(MI.getOperand(CurOp++),
892 (TSFlags & X86II::FormMask)-X86II::MRM0r,
895 case X86II::MRM0m: case X86II::MRM1m:
896 case X86II::MRM2m: case X86II::MRM3m:
897 case X86II::MRM4m: case X86II::MRM5m:
898 case X86II::MRM6m: case X86II::MRM7m:
899 EmitByte(BaseOpcode, CurByte, OS);
900 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
901 TSFlags, CurByte, OS, Fixups);
902 CurOp += X86::AddrNumOperands;
905 EmitByte(BaseOpcode, CurByte, OS);
906 EmitByte(0xC1, CurByte, OS);
909 EmitByte(BaseOpcode, CurByte, OS);
910 EmitByte(0xC2, CurByte, OS);
913 EmitByte(BaseOpcode, CurByte, OS);
914 EmitByte(0xC3, CurByte, OS);
917 EmitByte(BaseOpcode, CurByte, OS);
918 EmitByte(0xC4, CurByte, OS);
921 EmitByte(BaseOpcode, CurByte, OS);
922 EmitByte(0xC8, CurByte, OS);
925 EmitByte(BaseOpcode, CurByte, OS);
926 EmitByte(0xC9, CurByte, OS);
929 EmitByte(BaseOpcode, CurByte, OS);
930 EmitByte(0xE8, CurByte, OS);
933 EmitByte(BaseOpcode, CurByte, OS);
934 EmitByte(0xF0, CurByte, OS);
937 EmitByte(BaseOpcode, CurByte, OS);
938 EmitByte(0xF8, CurByte, OS);
941 EmitByte(BaseOpcode, CurByte, OS);
942 EmitByte(0xF9, CurByte, OS);
946 // If there is a remaining operand, it must be a trailing immediate. Emit it
947 // according to the right size for the instruction.
948 if (CurOp != NumOps) {
949 // The last source register of a 4 operand instruction in AVX is encoded
950 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
951 if (TSFlags & X86II::VEX_I8IMM) {
952 const MCOperand &MO = MI.getOperand(CurOp++);
954 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
955 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
956 RegNum |= GetX86RegNum(MO) << 4;
957 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
960 EmitImmediate(MI.getOperand(CurOp++),
961 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
962 CurByte, OS, Fixups);
968 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
969 errs() << "Cannot encode all operands of: ";