1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
47 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
52 if (Kind < FirstTargetFixupKind)
53 return MCCodeEmitter::getFixupKindInfo(Kind);
55 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
57 return Infos[Kind - FirstTargetFixupKind];
60 static unsigned GetX86RegNum(const MCOperand &MO) {
61 return X86RegisterInfo::getX86RegNum(MO.getReg());
64 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
69 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
70 raw_ostream &OS) const {
71 // Output the constant in little endian byte order.
72 for (unsigned i = 0; i != Size; ++i) {
73 EmitByte(Val & 255, CurByte, OS);
78 void EmitImmediate(const MCOperand &Disp,
79 unsigned ImmSize, MCFixupKind FixupKind,
80 unsigned &CurByte, raw_ostream &OS,
81 SmallVectorImpl<MCFixup> &Fixups,
82 int ImmOffset = 0) const;
84 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
86 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
87 return RM | (RegOpcode << 3) | (Mod << 6);
90 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
91 unsigned &CurByte, raw_ostream &OS) const {
92 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
95 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
96 unsigned &CurByte, raw_ostream &OS) const {
97 // SIB byte is in the same format as the ModRMByte.
98 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
102 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
103 unsigned RegOpcodeField,
104 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
105 SmallVectorImpl<MCFixup> &Fixups) const;
107 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
108 SmallVectorImpl<MCFixup> &Fixups) const;
110 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
111 const MCInst &MI, const TargetInstrDesc &Desc,
112 raw_ostream &OS) const;
114 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
115 const MCInst &MI, const TargetInstrDesc &Desc,
116 raw_ostream &OS) const;
119 } // end anonymous namespace
122 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
125 return new X86MCCodeEmitter(TM, Ctx, false);
128 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
131 return new X86MCCodeEmitter(TM, Ctx, true);
135 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
136 /// sign-extended field.
137 static bool isDisp8(int Value) {
138 return Value == (signed char)Value;
141 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
142 /// in an instruction with the specified TSFlags.
143 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
144 unsigned Size = X86II::getSizeOfImm(TSFlags);
145 bool isPCRel = X86II::isImmPCRel(TSFlags);
148 default: assert(0 && "Unknown immediate size");
149 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
150 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
151 case 2: assert(!isPCRel); return FK_Data_2;
152 case 8: assert(!isPCRel); return FK_Data_8;
157 void X86MCCodeEmitter::
158 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
159 unsigned &CurByte, raw_ostream &OS,
160 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
161 // If this is a simple integer displacement that doesn't require a relocation,
163 if (DispOp.isImm()) {
164 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
166 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
170 // If we have an immoffset, add it to the expression.
171 const MCExpr *Expr = DispOp.getExpr();
173 // If the fixup is pc-relative, we need to bias the value to be relative to
174 // the start of the field, not the end of the field.
175 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
176 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
177 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
179 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
183 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
186 // Emit a symbolic constant as a fixup and 4 zeros.
187 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
188 EmitConstant(0, Size, CurByte, OS);
192 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
193 unsigned RegOpcodeField,
194 uint64_t TSFlags, unsigned &CurByte,
196 SmallVectorImpl<MCFixup> &Fixups) const{
197 const MCOperand &Disp = MI.getOperand(Op+3);
198 const MCOperand &Base = MI.getOperand(Op);
199 const MCOperand &Scale = MI.getOperand(Op+1);
200 const MCOperand &IndexReg = MI.getOperand(Op+2);
201 unsigned BaseReg = Base.getReg();
203 // Handle %rip relative addressing.
204 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
205 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
206 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
207 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
209 unsigned FixupKind = X86::reloc_riprel_4byte;
211 // movq loads are handled with a special relocation form which allows the
212 // linker to eliminate some loads for GOT references which end up in the
213 // same linkage unit.
214 if (MI.getOpcode() == X86::MOV64rm ||
215 MI.getOpcode() == X86::MOV64rm_TC)
216 FixupKind = X86::reloc_riprel_4byte_movq_load;
218 // rip-relative addressing is actually relative to the *next* instruction.
219 // Since an immediate can follow the mod/rm byte for an instruction, this
220 // means that we need to bias the immediate field of the instruction with
221 // the size of the immediate field. If we have this case, add it into the
222 // expression to emit.
223 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
225 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
226 CurByte, OS, Fixups, -ImmSize);
230 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
232 // Determine whether a SIB byte is needed.
233 // If no BaseReg, issue a RIP relative instruction only if the MCE can
234 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
235 // 2-7) and absolute references.
237 if (// The SIB byte must be used if there is an index register.
238 IndexReg.getReg() == 0 &&
239 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
240 // encode to an R/M value of 4, which indicates that a SIB byte is
242 BaseRegNo != N86::ESP &&
243 // If there is no base register and we're in 64-bit mode, we need a SIB
244 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
245 (!Is64BitMode || BaseReg != 0)) {
247 if (BaseReg == 0) { // [disp32] in X86-32 mode
248 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
249 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
253 // If the base is not EBP/ESP and there is no displacement, use simple
254 // indirect register encoding, this handles addresses like [EAX]. The
255 // encoding for [EBP] with no displacement means [disp32] so we handle it
256 // by emitting a displacement of 0 below.
257 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
258 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
262 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
263 if (Disp.isImm() && isDisp8(Disp.getImm())) {
264 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
265 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
269 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
270 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
271 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
275 // We need a SIB byte, so start by outputting the ModR/M byte first
276 assert(IndexReg.getReg() != X86::ESP &&
277 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
279 bool ForceDisp32 = false;
280 bool ForceDisp8 = false;
282 // If there is no base register, we emit the special case SIB byte with
283 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
284 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
286 } else if (!Disp.isImm()) {
287 // Emit the normal disp32 encoding.
288 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
290 } else if (Disp.getImm() == 0 &&
291 // Base reg can't be anything that ends up with '5' as the base
292 // reg, it is the magic [*] nomenclature that indicates no base.
293 BaseRegNo != N86::EBP) {
294 // Emit no displacement ModR/M byte
295 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
296 } else if (isDisp8(Disp.getImm())) {
297 // Emit the disp8 encoding.
298 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
299 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
301 // Emit the normal disp32 encoding.
302 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
305 // Calculate what the SS field value should be...
306 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
307 unsigned SS = SSTable[Scale.getImm()];
310 // Handle the SIB byte for the case where there is no base, see Intel
311 // Manual 2A, table 2-7. The displacement has already been output.
313 if (IndexReg.getReg())
314 IndexRegNo = GetX86RegNum(IndexReg);
315 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
317 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
320 if (IndexReg.getReg())
321 IndexRegNo = GetX86RegNum(IndexReg);
323 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
324 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
327 // Do we need to output a displacement?
329 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
330 else if (ForceDisp32 || Disp.getImm() != 0)
331 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
334 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
336 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
337 const MCInst &MI, const TargetInstrDesc &Desc,
338 raw_ostream &OS) const {
340 // Pseudo instructions never have a VEX prefix.
341 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
344 // VEX_R: opcode externsion equivalent to REX.R in
345 // 1's complement (inverted) form
347 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
348 // 0: Same as REX_R=1 (64 bit mode only)
350 unsigned char VEX_R = 0x1;
352 // VEX_X: equivalent to REX.X, only used when a
353 // register is used for index in SIB Byte.
355 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
356 // 0: Same as REX.X=1 (64-bit mode only)
357 unsigned char VEX_X = 0x1;
361 // 1: Same as REX_B=0 (ignored in 32-bit mode)
362 // 0: Same as REX_B=1 (64 bit mode only)
364 unsigned char VEX_B = 0x1;
366 // VEX_W: opcode specific (use like REX.W, or used for
367 // opcode extension, or ignored, depending on the opcode byte)
368 unsigned char VEX_W = 0;
370 // VEX_5M (VEX m-mmmmm field):
372 // 0b00000: Reserved for future use
373 // 0b00001: implied 0F leading opcode
374 // 0b00010: implied 0F 38 leading opcode bytes
375 // 0b00011: implied 0F 3A leading opcode bytes
376 // 0b00100-0b11111: Reserved for future use
378 unsigned char VEX_5M = 0x1;
380 // VEX_4V (VEX vvvv field): a register specifier
381 // (in 1's complement form) or 1111 if unused.
382 unsigned char VEX_4V = 0xf;
384 // VEX_L (Vector Length):
386 // 0: scalar or 128-bit vector
389 unsigned char VEX_L = 0;
391 // VEX_PP: opcode extension providing equivalent
392 // functionality of a SIMD prefix
399 unsigned char VEX_PP = 0;
401 // Encode the operand size opcode prefix as needed.
402 if (TSFlags & X86II::OpSize)
405 switch (TSFlags & X86II::Op0Mask) {
406 default: assert(0 && "Invalid prefix!");
407 case 0: break; // No prefix!
408 case X86II::T8: // 0F 38
411 case X86II::TA: // 0F 3A
414 case X86II::TF: // F2 0F 38
418 case X86II::XS: // F3 0F
421 case X86II::XD: // F2 0F
426 unsigned NumOps = MI.getNumOperands();
428 unsigned SrcReg = 0, SrcRegNum = 0;
429 bool IsSrcMem = false;
431 switch (TSFlags & X86II::FormMask) {
432 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
433 case X86II::MRMSrcMem:
435 case X86II::MRMSrcReg:
436 if (MI.getOperand(0).isReg() &&
437 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
440 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the
441 // range 0-7 and the difference between the 2 groups is given by the
442 // REX prefix. In the VEX prefix, registers are seen sequencially
443 // from 0-15 and encoded in 1's complement form, example:
445 // ModRM field => XMM9 => 1
446 // VEX.VVVV => XMM9 => ~9
448 // See table 4-35 of Intel AVX Programming Reference for details.
449 SrcReg = MI.getOperand(1).getReg();
450 SrcRegNum = GetX86RegNum(MI.getOperand(1));
451 if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
454 // The registers represented through VEX_VVVV should
455 // be encoded in 1's complement form.
456 if ((TSFlags >> 32) & X86II::VEX_4V)
457 VEX_4V = (~SrcRegNum) & 0xf;
459 i = 2; // Skip the VEX.VVVV operand.
460 for (; i != NumOps; ++i) {
461 const MCOperand &MO = MI.getOperand(i);
462 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
464 if (!VEX_B && MO.isReg() && IsSrcMem &&
465 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
470 assert(0 && "Not implemented!");
473 // VEX opcode prefix can have 2 or 3 bytes
476 // +-----+ +--------------+ +-------------------+
477 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
478 // +-----+ +--------------+ +-------------------+
480 // +-----+ +-------------------+
481 // | C5h | | R | vvvv | L | pp |
482 // +-----+ +-------------------+
484 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
486 if (VEX_B && VEX_X) { // 2 byte VEX prefix
487 EmitByte(0xC5, CurByte, OS);
488 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
493 EmitByte(0xC4, CurByte, OS);
494 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_5M, CurByte, OS);
495 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
498 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
499 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
500 /// size, and 3) use of X86-64 extended registers.
501 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
502 const TargetInstrDesc &Desc) {
503 // Pseudo instructions never have a rex byte.
504 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
508 if (TSFlags & X86II::REX_W)
509 REX |= 1 << 3; // set REX.W
511 if (MI.getNumOperands() == 0) return REX;
513 unsigned NumOps = MI.getNumOperands();
514 // FIXME: MCInst should explicitize the two-addrness.
515 bool isTwoAddr = NumOps > 1 &&
516 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
518 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
519 unsigned i = isTwoAddr ? 1 : 0;
520 for (; i != NumOps; ++i) {
521 const MCOperand &MO = MI.getOperand(i);
522 if (!MO.isReg()) continue;
523 unsigned Reg = MO.getReg();
524 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
525 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
526 // that returns non-zero.
527 REX |= 0x40; // REX fixed encoding prefix
531 switch (TSFlags & X86II::FormMask) {
532 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
533 case X86II::MRMSrcReg:
534 if (MI.getOperand(0).isReg() &&
535 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
536 REX |= 1 << 2; // set REX.R
537 i = isTwoAddr ? 2 : 1;
538 for (; i != NumOps; ++i) {
539 const MCOperand &MO = MI.getOperand(i);
540 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
541 REX |= 1 << 0; // set REX.B
544 case X86II::MRMSrcMem: {
545 if (MI.getOperand(0).isReg() &&
546 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
547 REX |= 1 << 2; // set REX.R
549 i = isTwoAddr ? 2 : 1;
550 for (; i != NumOps; ++i) {
551 const MCOperand &MO = MI.getOperand(i);
553 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
554 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
560 case X86II::MRM0m: case X86II::MRM1m:
561 case X86II::MRM2m: case X86II::MRM3m:
562 case X86II::MRM4m: case X86II::MRM5m:
563 case X86II::MRM6m: case X86II::MRM7m:
564 case X86II::MRMDestMem: {
565 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
566 i = isTwoAddr ? 1 : 0;
567 if (NumOps > e && MI.getOperand(e).isReg() &&
568 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
569 REX |= 1 << 2; // set REX.R
571 for (; i != e; ++i) {
572 const MCOperand &MO = MI.getOperand(i);
574 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
575 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
582 if (MI.getOperand(0).isReg() &&
583 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
584 REX |= 1 << 0; // set REX.B
585 i = isTwoAddr ? 2 : 1;
586 for (unsigned e = NumOps; i != e; ++i) {
587 const MCOperand &MO = MI.getOperand(i);
588 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
589 REX |= 1 << 2; // set REX.R
596 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
597 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
598 const MCInst &MI, const TargetInstrDesc &Desc,
599 raw_ostream &OS) const {
601 // Emit the lock opcode prefix as needed.
602 if (TSFlags & X86II::LOCK)
603 EmitByte(0xF0, CurByte, OS);
605 // Emit segment override opcode prefix as needed.
606 switch (TSFlags & X86II::SegOvrMask) {
607 default: assert(0 && "Invalid segment!");
608 case 0: break; // No segment override!
610 EmitByte(0x64, CurByte, OS);
613 EmitByte(0x65, CurByte, OS);
617 // Emit the repeat opcode prefix as needed.
618 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
619 EmitByte(0xF3, CurByte, OS);
621 // Emit the operand size opcode prefix as needed.
622 if (TSFlags & X86II::OpSize)
623 EmitByte(0x66, CurByte, OS);
625 // Emit the address size opcode prefix as needed.
626 if (TSFlags & X86II::AdSize)
627 EmitByte(0x67, CurByte, OS);
629 bool Need0FPrefix = false;
630 switch (TSFlags & X86II::Op0Mask) {
631 default: assert(0 && "Invalid prefix!");
632 case 0: break; // No prefix!
633 case X86II::REP: break; // already handled.
634 case X86II::TB: // Two-byte opcode prefix
635 case X86II::T8: // 0F 38
636 case X86II::TA: // 0F 3A
639 case X86II::TF: // F2 0F 38
640 EmitByte(0xF2, CurByte, OS);
643 case X86II::XS: // F3 0F
644 EmitByte(0xF3, CurByte, OS);
647 case X86II::XD: // F2 0F
648 EmitByte(0xF2, CurByte, OS);
651 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
652 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
653 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
654 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
655 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
656 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
657 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
658 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
661 // Handle REX prefix.
662 // FIXME: Can this come before F2 etc to simplify emission?
664 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
665 EmitByte(0x40 | REX, CurByte, OS);
668 // 0x0F escape code must be emitted just before the opcode.
670 EmitByte(0x0F, CurByte, OS);
672 // FIXME: Pull this up into previous switch if REX can be moved earlier.
673 switch (TSFlags & X86II::Op0Mask) {
674 case X86II::TF: // F2 0F 38
675 case X86II::T8: // 0F 38
676 EmitByte(0x38, CurByte, OS);
678 case X86II::TA: // 0F 3A
679 EmitByte(0x3A, CurByte, OS);
684 void X86MCCodeEmitter::
685 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
686 SmallVectorImpl<MCFixup> &Fixups) const {
687 unsigned Opcode = MI.getOpcode();
688 const TargetInstrDesc &Desc = TII.get(Opcode);
689 uint64_t TSFlags = Desc.TSFlags;
691 // Keep track of the current byte being emitted.
692 unsigned CurByte = 0;
694 // Is this instruction encoded in AVX form?
695 bool IsAVXForm = false;
696 if ((TSFlags >> 32) & X86II::VEX_4V)
699 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
700 // in order to provide diffability.
703 EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
705 EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
707 // If this is a two-address instruction, skip one of the register operands.
708 unsigned NumOps = Desc.getNumOperands();
710 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
712 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
713 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
716 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
717 unsigned SrcRegNum = 0;
718 switch (TSFlags & X86II::FormMask) {
719 case X86II::MRMInitReg:
720 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
721 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
722 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
723 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
725 EmitByte(BaseOpcode, CurByte, OS);
728 case X86II::AddRegFrm:
729 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
732 case X86II::MRMDestReg:
733 EmitByte(BaseOpcode, CurByte, OS);
734 EmitRegModRMByte(MI.getOperand(CurOp),
735 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
739 case X86II::MRMDestMem:
740 EmitByte(BaseOpcode, CurByte, OS);
741 EmitMemModRMByte(MI, CurOp,
742 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
743 TSFlags, CurByte, OS, Fixups);
744 CurOp += X86AddrNumOperands + 1;
747 case X86II::MRMSrcReg:
748 EmitByte(BaseOpcode, CurByte, OS);
749 SrcRegNum = CurOp + 1;
751 if (IsAVXForm) // Skip 1st src (which is encoded in VEX_VVVV)
754 EmitRegModRMByte(MI.getOperand(SrcRegNum),
755 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
756 CurOp = SrcRegNum + 1;
759 case X86II::MRMSrcMem: {
760 EmitByte(BaseOpcode, CurByte, OS);
762 // FIXME: Maybe lea should have its own form? This is a horrible hack.
764 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
765 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
766 AddrOperands = X86AddrNumOperands - 1; // No segment register
768 AddrOperands = X86AddrNumOperands;
773 // Skip the register source (which is encoded in VEX_VVVV)
774 EmitMemModRMByte(MI, IsAVXForm ? CurOp+2 : CurOp+1,
775 GetX86RegNum(MI.getOperand(CurOp)),
776 TSFlags, CurByte, OS, Fixups);
777 CurOp += AddrOperands + 1;
781 case X86II::MRM0r: case X86II::MRM1r:
782 case X86II::MRM2r: case X86II::MRM3r:
783 case X86II::MRM4r: case X86II::MRM5r:
784 case X86II::MRM6r: case X86II::MRM7r:
785 EmitByte(BaseOpcode, CurByte, OS);
786 EmitRegModRMByte(MI.getOperand(CurOp++),
787 (TSFlags & X86II::FormMask)-X86II::MRM0r,
790 case X86II::MRM0m: case X86II::MRM1m:
791 case X86II::MRM2m: case X86II::MRM3m:
792 case X86II::MRM4m: case X86II::MRM5m:
793 case X86II::MRM6m: case X86II::MRM7m:
794 EmitByte(BaseOpcode, CurByte, OS);
795 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
796 TSFlags, CurByte, OS, Fixups);
797 CurOp += X86AddrNumOperands;
800 EmitByte(BaseOpcode, CurByte, OS);
801 EmitByte(0xC1, CurByte, OS);
804 EmitByte(BaseOpcode, CurByte, OS);
805 EmitByte(0xC2, CurByte, OS);
808 EmitByte(BaseOpcode, CurByte, OS);
809 EmitByte(0xC3, CurByte, OS);
812 EmitByte(BaseOpcode, CurByte, OS);
813 EmitByte(0xC4, CurByte, OS);
816 EmitByte(BaseOpcode, CurByte, OS);
817 EmitByte(0xC8, CurByte, OS);
820 EmitByte(BaseOpcode, CurByte, OS);
821 EmitByte(0xC9, CurByte, OS);
824 EmitByte(BaseOpcode, CurByte, OS);
825 EmitByte(0xE8, CurByte, OS);
828 EmitByte(BaseOpcode, CurByte, OS);
829 EmitByte(0xF0, CurByte, OS);
832 EmitByte(BaseOpcode, CurByte, OS);
833 EmitByte(0xF8, CurByte, OS);
836 EmitByte(BaseOpcode, CurByte, OS);
837 EmitByte(0xF9, CurByte, OS);
841 // If there is a remaining operand, it must be a trailing immediate. Emit it
842 // according to the right size for the instruction.
844 EmitImmediate(MI.getOperand(CurOp++),
845 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
846 CurByte, OS, Fixups);
850 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
851 errs() << "Cannot encode all operands of: ";