1 //===-- X86/X86MCCodeEmitter.cpp - Convert X86 code to machine code -------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the X86MCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "x86-emitter"
16 #include "X86InstrInfo.h"
17 #include "X86FixupKinds.h"
18 #include "llvm/MC/MCCodeEmitter.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/Support/raw_ostream.h"
25 class X86MCCodeEmitter : public MCCodeEmitter {
26 X86MCCodeEmitter(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
27 void operator=(const X86MCCodeEmitter &); // DO NOT IMPLEMENT
28 const TargetMachine &TM;
29 const TargetInstrInfo &TII;
33 X86MCCodeEmitter(TargetMachine &tm, MCContext &ctx, bool is64Bit)
34 : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) {
35 Is64BitMode = is64Bit;
38 ~X86MCCodeEmitter() {}
40 unsigned getNumFixupKinds() const {
44 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
45 const static MCFixupKindInfo Infos[] = {
46 { "reloc_pcrel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
47 { "reloc_pcrel_1byte", 0, 1 * 8, MCFixupKindInfo::FKF_IsPCRel },
48 { "reloc_pcrel_2byte", 0, 2 * 8, MCFixupKindInfo::FKF_IsPCRel },
49 { "reloc_riprel_4byte", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel },
50 { "reloc_riprel_4byte_movq_load", 0, 4 * 8, MCFixupKindInfo::FKF_IsPCRel }
53 if (Kind < FirstTargetFixupKind)
54 return MCCodeEmitter::getFixupKindInfo(Kind);
56 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
58 return Infos[Kind - FirstTargetFixupKind];
61 static unsigned GetX86RegNum(const MCOperand &MO) {
62 return X86RegisterInfo::getX86RegNum(MO.getReg());
65 // On regular x86, both XMM0-XMM7 and XMM8-XMM15 are encoded in the range
66 // 0-7 and the difference between the 2 groups is given by the REX prefix.
67 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
68 // in 1's complement form, example:
70 // ModRM field => XMM9 => 1
71 // VEX.VVVV => XMM9 => ~9
73 // See table 4-35 of Intel AVX Programming Reference for details.
74 static unsigned char getVEXRegisterEncoding(const MCInst &MI,
76 unsigned SrcReg = MI.getOperand(OpNum).getReg();
77 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
78 if (SrcReg >= X86::XMM8 && SrcReg <= X86::XMM15)
81 // The registers represented through VEX_VVVV should
82 // be encoded in 1's complement form.
83 return (~SrcRegNum) & 0xf;
86 void EmitByte(unsigned char C, unsigned &CurByte, raw_ostream &OS) const {
91 void EmitConstant(uint64_t Val, unsigned Size, unsigned &CurByte,
92 raw_ostream &OS) const {
93 // Output the constant in little endian byte order.
94 for (unsigned i = 0; i != Size; ++i) {
95 EmitByte(Val & 255, CurByte, OS);
100 void EmitImmediate(const MCOperand &Disp,
101 unsigned ImmSize, MCFixupKind FixupKind,
102 unsigned &CurByte, raw_ostream &OS,
103 SmallVectorImpl<MCFixup> &Fixups,
104 int ImmOffset = 0) const;
106 inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
108 assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
109 return RM | (RegOpcode << 3) | (Mod << 6);
112 void EmitRegModRMByte(const MCOperand &ModRMReg, unsigned RegOpcodeFld,
113 unsigned &CurByte, raw_ostream &OS) const {
114 EmitByte(ModRMByte(3, RegOpcodeFld, GetX86RegNum(ModRMReg)), CurByte, OS);
117 void EmitSIBByte(unsigned SS, unsigned Index, unsigned Base,
118 unsigned &CurByte, raw_ostream &OS) const {
119 // SIB byte is in the same format as the ModRMByte.
120 EmitByte(ModRMByte(SS, Index, Base), CurByte, OS);
124 void EmitSegmentOverridePrefix(const MCOperand &Op, unsigned TSFlags,
125 unsigned &CurByte, raw_ostream &OS) const;
127 void EmitMemModRMByte(const MCInst &MI, unsigned Op,
128 unsigned RegOpcodeField,
129 uint64_t TSFlags, unsigned &CurByte, raw_ostream &OS,
130 SmallVectorImpl<MCFixup> &Fixups) const;
132 void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
133 SmallVectorImpl<MCFixup> &Fixups) const;
135 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
136 const MCInst &MI, const TargetInstrDesc &Desc,
137 raw_ostream &OS) const;
139 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
140 const MCInst &MI, const TargetInstrDesc &Desc,
141 raw_ostream &OS) const;
144 } // end anonymous namespace
147 MCCodeEmitter *llvm::createX86_32MCCodeEmitter(const Target &,
150 return new X86MCCodeEmitter(TM, Ctx, false);
153 MCCodeEmitter *llvm::createX86_64MCCodeEmitter(const Target &,
156 return new X86MCCodeEmitter(TM, Ctx, true);
159 /// isDisp8 - Return true if this signed displacement fits in a 8-bit
160 /// sign-extended field.
161 static bool isDisp8(int Value) {
162 return Value == (signed char)Value;
165 /// getImmFixupKind - Return the appropriate fixup kind to use for an immediate
166 /// in an instruction with the specified TSFlags.
167 static MCFixupKind getImmFixupKind(uint64_t TSFlags) {
168 unsigned Size = X86II::getSizeOfImm(TSFlags);
169 bool isPCRel = X86II::isImmPCRel(TSFlags);
172 default: assert(0 && "Unknown immediate size");
173 case 1: return isPCRel ? MCFixupKind(X86::reloc_pcrel_1byte) : FK_Data_1;
174 case 2: return isPCRel ? MCFixupKind(X86::reloc_pcrel_2byte) : FK_Data_2;
175 case 4: return isPCRel ? MCFixupKind(X86::reloc_pcrel_4byte) : FK_Data_4;
176 case 8: assert(!isPCRel); return FK_Data_8;
181 void X86MCCodeEmitter::
182 EmitImmediate(const MCOperand &DispOp, unsigned Size, MCFixupKind FixupKind,
183 unsigned &CurByte, raw_ostream &OS,
184 SmallVectorImpl<MCFixup> &Fixups, int ImmOffset) const {
185 // If this is a simple integer displacement that doesn't require a relocation,
187 if (DispOp.isImm()) {
188 // FIXME: is this right for pc-rel encoding?? Probably need to emit this as
190 EmitConstant(DispOp.getImm()+ImmOffset, Size, CurByte, OS);
194 // If we have an immoffset, add it to the expression.
195 const MCExpr *Expr = DispOp.getExpr();
197 // If the fixup is pc-relative, we need to bias the value to be relative to
198 // the start of the field, not the end of the field.
199 if (FixupKind == MCFixupKind(X86::reloc_pcrel_4byte) ||
200 FixupKind == MCFixupKind(X86::reloc_riprel_4byte) ||
201 FixupKind == MCFixupKind(X86::reloc_riprel_4byte_movq_load))
203 if (FixupKind == MCFixupKind(X86::reloc_pcrel_2byte))
205 if (FixupKind == MCFixupKind(X86::reloc_pcrel_1byte))
209 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(ImmOffset, Ctx),
212 // Emit a symbolic constant as a fixup and 4 zeros.
213 Fixups.push_back(MCFixup::Create(CurByte, Expr, FixupKind));
214 EmitConstant(0, Size, CurByte, OS);
217 void X86MCCodeEmitter::EmitSegmentOverridePrefix(const MCOperand &Op,
220 raw_ostream &OS) const {
221 // If no segment register is present, we don't need anything.
222 if (Op.getReg() == 0)
225 // Check if we need an override.
226 switch (Op.getReg()) {
227 case X86::CS: EmitByte(0x2E, CurByte, OS); return;
228 case X86::SS: EmitByte(0x36, CurByte, OS); return;
229 case X86::DS: EmitByte(0x3E, CurByte, OS); return;
230 case X86::ES: EmitByte(0x26, CurByte, OS); return;
231 case X86::FS: EmitByte(0x64, CurByte, OS); return;
232 case X86::GS: EmitByte(0x65, CurByte, OS); return;
235 assert(0 && "Invalid segment register!");
238 void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
239 unsigned RegOpcodeField,
240 uint64_t TSFlags, unsigned &CurByte,
242 SmallVectorImpl<MCFixup> &Fixups) const{
243 const MCOperand &Disp = MI.getOperand(Op+3);
244 const MCOperand &Base = MI.getOperand(Op);
245 const MCOperand &Scale = MI.getOperand(Op+1);
246 const MCOperand &IndexReg = MI.getOperand(Op+2);
247 unsigned BaseReg = Base.getReg();
249 // Handle %rip relative addressing.
250 if (BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
251 assert(Is64BitMode && "Rip-relative addressing requires 64-bit mode");
252 assert(IndexReg.getReg() == 0 && "Invalid rip-relative address");
253 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
255 unsigned FixupKind = X86::reloc_riprel_4byte;
257 // movq loads are handled with a special relocation form which allows the
258 // linker to eliminate some loads for GOT references which end up in the
259 // same linkage unit.
260 if (MI.getOpcode() == X86::MOV64rm ||
261 MI.getOpcode() == X86::MOV64rm_TC)
262 FixupKind = X86::reloc_riprel_4byte_movq_load;
264 // rip-relative addressing is actually relative to the *next* instruction.
265 // Since an immediate can follow the mod/rm byte for an instruction, this
266 // means that we need to bias the immediate field of the instruction with
267 // the size of the immediate field. If we have this case, add it into the
268 // expression to emit.
269 int ImmSize = X86II::hasImm(TSFlags) ? X86II::getSizeOfImm(TSFlags) : 0;
271 EmitImmediate(Disp, 4, MCFixupKind(FixupKind),
272 CurByte, OS, Fixups, -ImmSize);
276 unsigned BaseRegNo = BaseReg ? GetX86RegNum(Base) : -1U;
278 // Determine whether a SIB byte is needed.
279 // If no BaseReg, issue a RIP relative instruction only if the MCE can
280 // resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
281 // 2-7) and absolute references.
283 if (// The SIB byte must be used if there is an index register.
284 IndexReg.getReg() == 0 &&
285 // The SIB byte must be used if the base is ESP/RSP/R12, all of which
286 // encode to an R/M value of 4, which indicates that a SIB byte is
288 BaseRegNo != N86::ESP &&
289 // If there is no base register and we're in 64-bit mode, we need a SIB
290 // byte to emit an addr that is just 'disp32' (the non-RIP relative form).
291 (!Is64BitMode || BaseReg != 0)) {
293 if (BaseReg == 0) { // [disp32] in X86-32 mode
294 EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
295 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
299 // If the base is not EBP/ESP and there is no displacement, use simple
300 // indirect register encoding, this handles addresses like [EAX]. The
301 // encoding for [EBP] with no displacement means [disp32] so we handle it
302 // by emitting a displacement of 0 below.
303 if (Disp.isImm() && Disp.getImm() == 0 && BaseRegNo != N86::EBP) {
304 EmitByte(ModRMByte(0, RegOpcodeField, BaseRegNo), CurByte, OS);
308 // Otherwise, if the displacement fits in a byte, encode as [REG+disp8].
309 if (Disp.isImm() && isDisp8(Disp.getImm())) {
310 EmitByte(ModRMByte(1, RegOpcodeField, BaseRegNo), CurByte, OS);
311 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
315 // Otherwise, emit the most general non-SIB encoding: [REG+disp32]
316 EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
317 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
321 // We need a SIB byte, so start by outputting the ModR/M byte first
322 assert(IndexReg.getReg() != X86::ESP &&
323 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
325 bool ForceDisp32 = false;
326 bool ForceDisp8 = false;
328 // If there is no base register, we emit the special case SIB byte with
329 // MOD=0, BASE=5, to JUST get the index, scale, and displacement.
330 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
332 } else if (!Disp.isImm()) {
333 // Emit the normal disp32 encoding.
334 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
336 } else if (Disp.getImm() == 0 &&
337 // Base reg can't be anything that ends up with '5' as the base
338 // reg, it is the magic [*] nomenclature that indicates no base.
339 BaseRegNo != N86::EBP) {
340 // Emit no displacement ModR/M byte
341 EmitByte(ModRMByte(0, RegOpcodeField, 4), CurByte, OS);
342 } else if (isDisp8(Disp.getImm())) {
343 // Emit the disp8 encoding.
344 EmitByte(ModRMByte(1, RegOpcodeField, 4), CurByte, OS);
345 ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
347 // Emit the normal disp32 encoding.
348 EmitByte(ModRMByte(2, RegOpcodeField, 4), CurByte, OS);
351 // Calculate what the SS field value should be...
352 static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
353 unsigned SS = SSTable[Scale.getImm()];
356 // Handle the SIB byte for the case where there is no base, see Intel
357 // Manual 2A, table 2-7. The displacement has already been output.
359 if (IndexReg.getReg())
360 IndexRegNo = GetX86RegNum(IndexReg);
361 else // Examples: [ESP+1*<noreg>+4] or [scaled idx]+disp32 (MOD=0,BASE=5)
363 EmitSIBByte(SS, IndexRegNo, 5, CurByte, OS);
366 if (IndexReg.getReg())
367 IndexRegNo = GetX86RegNum(IndexReg);
369 IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
370 EmitSIBByte(SS, IndexRegNo, GetX86RegNum(Base), CurByte, OS);
373 // Do we need to output a displacement?
375 EmitImmediate(Disp, 1, FK_Data_1, CurByte, OS, Fixups);
376 else if (ForceDisp32 || Disp.getImm() != 0)
377 EmitImmediate(Disp, 4, FK_Data_4, CurByte, OS, Fixups);
380 /// EmitVEXOpcodePrefix - AVX instructions are encoded using a opcode prefix
382 void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
383 const MCInst &MI, const TargetInstrDesc &Desc,
384 raw_ostream &OS) const {
386 // Pseudo instructions never have a VEX prefix.
387 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
390 bool HasVEX_4V = false;
391 if ((TSFlags >> 32) & X86II::VEX_4V)
394 // VEX_R: opcode externsion equivalent to REX.R in
395 // 1's complement (inverted) form
397 // 1: Same as REX_R=0 (must be 1 in 32-bit mode)
398 // 0: Same as REX_R=1 (64 bit mode only)
400 unsigned char VEX_R = 0x1;
402 // VEX_X: equivalent to REX.X, only used when a
403 // register is used for index in SIB Byte.
405 // 1: Same as REX.X=0 (must be 1 in 32-bit mode)
406 // 0: Same as REX.X=1 (64-bit mode only)
407 unsigned char VEX_X = 0x1;
411 // 1: Same as REX_B=0 (ignored in 32-bit mode)
412 // 0: Same as REX_B=1 (64 bit mode only)
414 unsigned char VEX_B = 0x1;
416 // VEX_W: opcode specific (use like REX.W, or used for
417 // opcode extension, or ignored, depending on the opcode byte)
418 unsigned char VEX_W = 0;
420 // VEX_5M (VEX m-mmmmm field):
422 // 0b00000: Reserved for future use
423 // 0b00001: implied 0F leading opcode
424 // 0b00010: implied 0F 38 leading opcode bytes
425 // 0b00011: implied 0F 3A leading opcode bytes
426 // 0b00100-0b11111: Reserved for future use
428 unsigned char VEX_5M = 0x1;
430 // VEX_4V (VEX vvvv field): a register specifier
431 // (in 1's complement form) or 1111 if unused.
432 unsigned char VEX_4V = 0xf;
434 // VEX_L (Vector Length):
436 // 0: scalar or 128-bit vector
439 unsigned char VEX_L = 0;
441 // VEX_PP: opcode extension providing equivalent
442 // functionality of a SIMD prefix
449 unsigned char VEX_PP = 0;
451 // Encode the operand size opcode prefix as needed.
452 if (TSFlags & X86II::OpSize)
455 if ((TSFlags >> 32) & X86II::VEX_W)
458 switch (TSFlags & X86II::Op0Mask) {
459 default: assert(0 && "Invalid prefix!");
460 case X86II::T8: // 0F 38
463 case X86II::TA: // 0F 3A
466 case X86II::TF: // F2 0F 38
470 case X86II::XS: // F3 0F
473 case X86II::XD: // F2 0F
476 case X86II::TB: // Bypass: Not used by VEX
481 unsigned NumOps = MI.getNumOperands();
484 switch (TSFlags & X86II::FormMask) {
485 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
486 case X86II::MRM0m: case X86II::MRM1m:
487 case X86II::MRM2m: case X86II::MRM3m:
488 case X86II::MRM4m: case X86II::MRM5m:
489 case X86II::MRM6m: case X86II::MRM7m:
490 case X86II::MRMDestMem:
491 NumOps = CurOp = X86AddrNumOperands;
492 case X86II::MRMSrcMem:
493 case X86II::MRMSrcReg:
494 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
495 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
498 // CurOp and NumOps are equal when VEX_R represents a register used
499 // to index a memory destination (which is the last operand)
500 CurOp = (CurOp == NumOps) ? 0 : CurOp+1;
503 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
507 // If the last register should be encoded in the immediate field
508 // do not use any bit from VEX prefix to this register, ignore it
509 if ((TSFlags >> 32) & X86II::VEX_I8IMM)
512 for (; CurOp != NumOps; ++CurOp) {
513 const MCOperand &MO = MI.getOperand(CurOp);
514 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
516 if (!VEX_B && MO.isReg() &&
517 ((TSFlags & X86II::FormMask) == X86II::MRMSrcMem) &&
518 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
522 default: // MRMDestReg, MRM0r-MRM7r
523 if (MI.getOperand(CurOp).isReg() &&
524 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(CurOp).getReg()))
528 VEX_4V = getVEXRegisterEncoding(MI, CurOp);
531 for (; CurOp != NumOps; ++CurOp) {
532 const MCOperand &MO = MI.getOperand(CurOp);
533 if (MO.isReg() && !HasVEX_4V &&
534 X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
538 assert(0 && "Not implemented!");
541 // VEX opcode prefix can have 2 or 3 bytes
544 // +-----+ +--------------+ +-------------------+
545 // | C4h | | RXB | m-mmmm | | W | vvvv | L | pp |
546 // +-----+ +--------------+ +-------------------+
548 // +-----+ +-------------------+
549 // | C5h | | R | vvvv | L | pp |
550 // +-----+ +-------------------+
552 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3);
554 if (VEX_B && VEX_X && !VEX_W && (VEX_5M == 1)) { // 2 byte VEX prefix
555 EmitByte(0xC5, CurByte, OS);
556 EmitByte(LastByte | (VEX_R << 7), CurByte, OS);
561 EmitByte(0xC4, CurByte, OS);
562 EmitByte(VEX_R << 7 | VEX_X << 6 | VEX_B << 5 | VEX_5M, CurByte, OS);
563 EmitByte(LastByte | (VEX_W << 7), CurByte, OS);
566 /// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
567 /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
568 /// size, and 3) use of X86-64 extended registers.
569 static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags,
570 const TargetInstrDesc &Desc) {
571 // Pseudo instructions never have a rex byte.
572 if ((TSFlags & X86II::FormMask) == X86II::Pseudo)
576 if (TSFlags & X86II::REX_W)
577 REX |= 1 << 3; // set REX.W
579 if (MI.getNumOperands() == 0) return REX;
581 unsigned NumOps = MI.getNumOperands();
582 // FIXME: MCInst should explicitize the two-addrness.
583 bool isTwoAddr = NumOps > 1 &&
584 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
586 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
587 unsigned i = isTwoAddr ? 1 : 0;
588 for (; i != NumOps; ++i) {
589 const MCOperand &MO = MI.getOperand(i);
590 if (!MO.isReg()) continue;
591 unsigned Reg = MO.getReg();
592 if (!X86InstrInfo::isX86_64NonExtLowByteReg(Reg)) continue;
593 // FIXME: The caller of DetermineREXPrefix slaps this prefix onto anything
594 // that returns non-zero.
595 REX |= 0x40; // REX fixed encoding prefix
599 switch (TSFlags & X86II::FormMask) {
600 case X86II::MRMInitReg: assert(0 && "FIXME: Remove this!");
601 case X86II::MRMSrcReg:
602 if (MI.getOperand(0).isReg() &&
603 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
604 REX |= 1 << 2; // set REX.R
605 i = isTwoAddr ? 2 : 1;
606 for (; i != NumOps; ++i) {
607 const MCOperand &MO = MI.getOperand(i);
608 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
609 REX |= 1 << 0; // set REX.B
612 case X86II::MRMSrcMem: {
613 if (MI.getOperand(0).isReg() &&
614 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
615 REX |= 1 << 2; // set REX.R
617 i = isTwoAddr ? 2 : 1;
618 for (; i != NumOps; ++i) {
619 const MCOperand &MO = MI.getOperand(i);
621 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
622 REX |= 1 << Bit; // set REX.B (Bit=0) and REX.X (Bit=1)
628 case X86II::MRM0m: case X86II::MRM1m:
629 case X86II::MRM2m: case X86II::MRM3m:
630 case X86II::MRM4m: case X86II::MRM5m:
631 case X86II::MRM6m: case X86II::MRM7m:
632 case X86II::MRMDestMem: {
633 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
634 i = isTwoAddr ? 1 : 0;
635 if (NumOps > e && MI.getOperand(e).isReg() &&
636 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
637 REX |= 1 << 2; // set REX.R
639 for (; i != e; ++i) {
640 const MCOperand &MO = MI.getOperand(i);
642 if (X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
643 REX |= 1 << Bit; // REX.B (Bit=0) and REX.X (Bit=1)
650 if (MI.getOperand(0).isReg() &&
651 X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(0).getReg()))
652 REX |= 1 << 0; // set REX.B
653 i = isTwoAddr ? 2 : 1;
654 for (unsigned e = NumOps; i != e; ++i) {
655 const MCOperand &MO = MI.getOperand(i);
656 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg()))
657 REX |= 1 << 2; // set REX.R
664 /// EmitOpcodePrefix - Emit all instruction prefixes prior to the opcode.
665 void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
667 const TargetInstrDesc &Desc,
668 raw_ostream &OS) const {
670 // Emit the lock opcode prefix as needed.
671 if (TSFlags & X86II::LOCK)
672 EmitByte(0xF0, CurByte, OS);
674 // Emit segment override opcode prefix as needed.
675 switch (TSFlags & X86II::SegOvrMask) {
676 default: assert(0 && "Invalid segment!");
677 case 0: break; // No segment override!
679 EmitByte(0x64, CurByte, OS);
682 EmitByte(0x65, CurByte, OS);
686 // Emit the repeat opcode prefix as needed.
687 if ((TSFlags & X86II::Op0Mask) == X86II::REP)
688 EmitByte(0xF3, CurByte, OS);
690 // Emit the operand size opcode prefix as needed.
691 if (TSFlags & X86II::OpSize)
692 EmitByte(0x66, CurByte, OS);
694 // Emit the address size opcode prefix as needed.
695 if (TSFlags & X86II::AdSize)
696 EmitByte(0x67, CurByte, OS);
698 bool Need0FPrefix = false;
699 switch (TSFlags & X86II::Op0Mask) {
700 default: assert(0 && "Invalid prefix!");
701 case 0: break; // No prefix!
702 case X86II::REP: break; // already handled.
703 case X86II::TB: // Two-byte opcode prefix
704 case X86II::T8: // 0F 38
705 case X86II::TA: // 0F 3A
708 case X86II::TF: // F2 0F 38
709 EmitByte(0xF2, CurByte, OS);
712 case X86II::XS: // F3 0F
713 EmitByte(0xF3, CurByte, OS);
716 case X86II::XD: // F2 0F
717 EmitByte(0xF2, CurByte, OS);
720 case X86II::D8: EmitByte(0xD8, CurByte, OS); break;
721 case X86II::D9: EmitByte(0xD9, CurByte, OS); break;
722 case X86II::DA: EmitByte(0xDA, CurByte, OS); break;
723 case X86II::DB: EmitByte(0xDB, CurByte, OS); break;
724 case X86II::DC: EmitByte(0xDC, CurByte, OS); break;
725 case X86II::DD: EmitByte(0xDD, CurByte, OS); break;
726 case X86II::DE: EmitByte(0xDE, CurByte, OS); break;
727 case X86II::DF: EmitByte(0xDF, CurByte, OS); break;
730 // Handle REX prefix.
731 // FIXME: Can this come before F2 etc to simplify emission?
733 if (unsigned REX = DetermineREXPrefix(MI, TSFlags, Desc))
734 EmitByte(0x40 | REX, CurByte, OS);
737 // 0x0F escape code must be emitted just before the opcode.
739 EmitByte(0x0F, CurByte, OS);
741 // FIXME: Pull this up into previous switch if REX can be moved earlier.
742 switch (TSFlags & X86II::Op0Mask) {
743 case X86II::TF: // F2 0F 38
744 case X86II::T8: // 0F 38
745 EmitByte(0x38, CurByte, OS);
747 case X86II::TA: // 0F 3A
748 EmitByte(0x3A, CurByte, OS);
753 void X86MCCodeEmitter::
754 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
755 SmallVectorImpl<MCFixup> &Fixups) const {
756 unsigned Opcode = MI.getOpcode();
757 const TargetInstrDesc &Desc = TII.get(Opcode);
758 uint64_t TSFlags = Desc.TSFlags;
760 // Keep track of the current byte being emitted.
761 unsigned CurByte = 0;
763 // Is this instruction encoded using the AVX VEX prefix?
764 bool HasVEXPrefix = false;
766 // It uses the VEX.VVVV field?
767 bool HasVEX_4V = false;
769 if ((TSFlags >> 32) & X86II::VEX)
771 if ((TSFlags >> 32) & X86II::VEX_4V)
774 // FIXME: We should emit the prefixes in exactly the same order as GAS does,
775 // in order to provide diffability.
778 EmitOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
780 EmitVEXOpcodePrefix(TSFlags, CurByte, MI, Desc, OS);
782 // If this is a two-address instruction, skip one of the register operands.
783 unsigned NumOps = Desc.getNumOperands();
785 if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1)
787 else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
788 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
791 unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
792 unsigned SrcRegNum = 0;
793 switch (TSFlags & X86II::FormMask) {
794 case X86II::MRMInitReg:
795 assert(0 && "FIXME: Remove this form when the JIT moves to MCCodeEmitter!");
796 default: errs() << "FORM: " << (TSFlags & X86II::FormMask) << "\n";
797 assert(0 && "Unknown FormMask value in X86MCCodeEmitter!");
798 case X86II::Pseudo: return; // Pseudo instructions encode to nothing.
800 EmitByte(BaseOpcode, CurByte, OS);
803 case X86II::AddRegFrm:
804 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS);
807 case X86II::MRMDestReg:
808 EmitByte(BaseOpcode, CurByte, OS);
809 EmitRegModRMByte(MI.getOperand(CurOp),
810 GetX86RegNum(MI.getOperand(CurOp+1)), CurByte, OS);
814 case X86II::MRMDestMem:
815 EmitSegmentOverridePrefix(MI.getOperand(CurOp + 4), TSFlags, CurByte, OS);
816 EmitByte(BaseOpcode, CurByte, OS);
817 EmitMemModRMByte(MI, CurOp,
818 GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
819 TSFlags, CurByte, OS, Fixups);
820 CurOp += X86AddrNumOperands + 1;
823 case X86II::MRMSrcReg:
824 EmitByte(BaseOpcode, CurByte, OS);
825 SrcRegNum = CurOp + 1;
827 if (HasVEX_4V) // Skip 1st src (which is encoded in VEX_VVVV)
830 EmitRegModRMByte(MI.getOperand(SrcRegNum),
831 GetX86RegNum(MI.getOperand(CurOp)), CurByte, OS);
832 CurOp = SrcRegNum + 1;
835 case X86II::MRMSrcMem: {
836 int AddrOperands = X86AddrNumOperands;
837 unsigned FirstMemOp = CurOp+1;
840 ++FirstMemOp; // Skip the register source (which is encoded in VEX_VVVV).
843 // FIXME: Maybe lea should have its own form? This is a horrible hack.
844 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
845 Opcode == X86::LEA16r || Opcode == X86::LEA32r)
846 --AddrOperands; // No segment register
848 EmitSegmentOverridePrefix(MI.getOperand(FirstMemOp+4),
849 TSFlags, CurByte, OS);
851 EmitByte(BaseOpcode, CurByte, OS);
854 EmitMemModRMByte(MI, FirstMemOp, GetX86RegNum(MI.getOperand(CurOp)),
855 TSFlags, CurByte, OS, Fixups);
856 CurOp += AddrOperands + 1;
860 case X86II::MRM0r: case X86II::MRM1r:
861 case X86II::MRM2r: case X86II::MRM3r:
862 case X86II::MRM4r: case X86II::MRM5r:
863 case X86II::MRM6r: case X86II::MRM7r:
864 if (HasVEX_4V) // Skip the register dst (which is encoded in VEX_VVVV).
866 EmitByte(BaseOpcode, CurByte, OS);
867 EmitRegModRMByte(MI.getOperand(CurOp++),
868 (TSFlags & X86II::FormMask)-X86II::MRM0r,
871 case X86II::MRM0m: case X86II::MRM1m:
872 case X86II::MRM2m: case X86II::MRM3m:
873 case X86II::MRM4m: case X86II::MRM5m:
874 case X86II::MRM6m: case X86II::MRM7m:
875 EmitSegmentOverridePrefix(MI.getOperand(CurOp+4), TSFlags, CurByte, OS);
876 EmitByte(BaseOpcode, CurByte, OS);
877 EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
878 TSFlags, CurByte, OS, Fixups);
879 CurOp += X86AddrNumOperands;
882 EmitByte(BaseOpcode, CurByte, OS);
883 EmitByte(0xC1, CurByte, OS);
886 EmitByte(BaseOpcode, CurByte, OS);
887 EmitByte(0xC2, CurByte, OS);
890 EmitByte(BaseOpcode, CurByte, OS);
891 EmitByte(0xC3, CurByte, OS);
894 EmitByte(BaseOpcode, CurByte, OS);
895 EmitByte(0xC4, CurByte, OS);
898 EmitByte(BaseOpcode, CurByte, OS);
899 EmitByte(0xC8, CurByte, OS);
902 EmitByte(BaseOpcode, CurByte, OS);
903 EmitByte(0xC9, CurByte, OS);
906 EmitByte(BaseOpcode, CurByte, OS);
907 EmitByte(0xE8, CurByte, OS);
910 EmitByte(BaseOpcode, CurByte, OS);
911 EmitByte(0xF0, CurByte, OS);
914 EmitByte(BaseOpcode, CurByte, OS);
915 EmitByte(0xF8, CurByte, OS);
918 EmitByte(BaseOpcode, CurByte, OS);
919 EmitByte(0xF9, CurByte, OS);
923 // If there is a remaining operand, it must be a trailing immediate. Emit it
924 // according to the right size for the instruction.
925 if (CurOp != NumOps) {
926 // The last source register of a 4 operand instruction in AVX is encoded
927 // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
928 if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
929 const MCOperand &MO = MI.getOperand(CurOp++);
931 X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
932 unsigned RegNum = (IsExtReg ? (1 << 7) : 0);
933 RegNum |= GetX86RegNum(MO) << 4;
934 EmitImmediate(MCOperand::CreateImm(RegNum), 1, FK_Data_1, CurByte, OS,
937 EmitImmediate(MI.getOperand(CurOp++),
938 X86II::getSizeOfImm(TSFlags), getImmFixupKind(TSFlags),
939 CurByte, OS, Fixups);
945 if (/*!Desc.isVariadic() &&*/ CurOp != NumOps) {
946 errs() << "Cannot encode all operands of: ";