1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86MCInstLower.h"
16 #include "X86AsmPrinter.h"
17 #include "X86COFFMachineModuleInfo.h"
18 #include "InstPrinter/X86ATTInstPrinter.h"
19 #include "llvm/Type.h"
20 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCExpr.h"
24 #include "llvm/MC/MCInst.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSymbol.h"
27 #include "llvm/Target/Mangler.h"
28 #include "llvm/Support/FormattedStream.h"
29 #include "llvm/ADT/SmallString.h"
32 X86MCInstLower::X86MCInstLower(Mangler *mang, const MachineFunction &mf,
33 X86AsmPrinter &asmprinter)
34 : Ctx(mf.getContext()), Mang(mang), MF(mf), TM(mf.getTarget()),
35 MAI(*TM.getMCAsmInfo()), AsmPrinter(asmprinter) {}
37 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
38 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
42 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
43 /// operand to an MCSymbol.
44 MCSymbol *X86MCInstLower::
45 GetSymbolFromOperand(const MachineOperand &MO) const {
46 assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference");
48 SmallString<128> Name;
51 assert(MO.isSymbol());
52 Name += MAI.getGlobalPrefix();
53 Name += MO.getSymbolName();
55 const GlobalValue *GV = MO.getGlobal();
56 bool isImplicitlyPrivate = false;
57 if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB ||
58 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY ||
59 MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE ||
60 MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE)
61 isImplicitlyPrivate = true;
63 Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate);
66 // If the target flags on the operand changes the name of the symbol, do that
67 // before we return the symbol.
68 switch (MO.getTargetFlags()) {
70 case X86II::MO_DLLIMPORT: {
71 // Handle dllimport linkage.
72 const char *Prefix = "__imp_";
73 Name.insert(Name.begin(), Prefix, Prefix+strlen(Prefix));
76 case X86II::MO_DARWIN_NONLAZY:
77 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
78 Name += "$non_lazy_ptr";
79 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
81 MachineModuleInfoImpl::StubValueTy &StubSym =
82 getMachOMMI().getGVStubEntry(Sym);
83 if (StubSym.getPointer() == 0) {
84 assert(MO.isGlobal() && "Extern symbol not handled yet");
86 MachineModuleInfoImpl::
87 StubValueTy(Mang->getSymbol(MO.getGlobal()),
88 !MO.getGlobal()->hasInternalLinkage());
92 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
93 Name += "$non_lazy_ptr";
94 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
95 MachineModuleInfoImpl::StubValueTy &StubSym =
96 getMachOMMI().getHiddenGVStubEntry(Sym);
97 if (StubSym.getPointer() == 0) {
98 assert(MO.isGlobal() && "Extern symbol not handled yet");
100 MachineModuleInfoImpl::
101 StubValueTy(Mang->getSymbol(MO.getGlobal()),
102 !MO.getGlobal()->hasInternalLinkage());
106 case X86II::MO_DARWIN_STUB: {
108 MCSymbol *Sym = Ctx.GetOrCreateSymbol(Name.str());
109 MachineModuleInfoImpl::StubValueTy &StubSym =
110 getMachOMMI().getFnStubEntry(Sym);
111 if (StubSym.getPointer())
116 MachineModuleInfoImpl::
117 StubValueTy(Mang->getSymbol(MO.getGlobal()),
118 !MO.getGlobal()->hasInternalLinkage());
120 Name.erase(Name.end()-5, Name.end());
122 MachineModuleInfoImpl::
123 StubValueTy(Ctx.GetOrCreateSymbol(Name.str()), false);
129 return Ctx.GetOrCreateSymbol(Name.str());
132 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
133 MCSymbol *Sym) const {
134 // FIXME: We would like an efficient form for this, so we don't have to do a
135 // lot of extra uniquing.
136 const MCExpr *Expr = 0;
137 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
139 switch (MO.getTargetFlags()) {
140 default: llvm_unreachable("Unknown target flag on GV operand");
141 case X86II::MO_NO_FLAG: // No flag.
142 // These affect the name of the symbol, not any suffix.
143 case X86II::MO_DARWIN_NONLAZY:
144 case X86II::MO_DLLIMPORT:
145 case X86II::MO_DARWIN_STUB:
148 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
149 case X86II::MO_TLVP_PIC_BASE:
150 Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
151 // Subtract the pic base.
152 Expr = MCBinaryExpr::CreateSub(Expr,
153 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(),
157 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
158 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
159 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
160 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
161 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
162 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
163 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
164 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
165 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
166 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
167 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
168 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
169 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
170 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
171 case X86II::MO_PIC_BASE_OFFSET:
172 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
173 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
174 Expr = MCSymbolRefExpr::Create(Sym, Ctx);
175 // Subtract the pic base.
176 Expr = MCBinaryExpr::CreateSub(Expr,
177 MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx),
179 if (MO.isJTI() && MAI.hasSetDirective()) {
180 // If .set directive is supported, use it to reduce the number of
181 // relocations the assembler will generate for differences between
182 // local labels. This is only safe when the symbols are in the same
183 // section so we are restricting it to jumptable references.
184 MCSymbol *Label = Ctx.CreateTempSymbol();
185 AsmPrinter.OutStreamer.EmitAssignment(Label, Expr);
186 Expr = MCSymbolRefExpr::Create(Label, Ctx);
192 Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx);
194 if (!MO.isJTI() && MO.getOffset())
195 Expr = MCBinaryExpr::CreateAdd(Expr,
196 MCConstantExpr::Create(MO.getOffset(), Ctx),
198 return MCOperand::CreateExpr(Expr);
203 static void lower_subreg32(MCInst *MI, unsigned OpNo) {
204 // Convert registers in the addr mode according to subreg32.
205 unsigned Reg = MI->getOperand(OpNo).getReg();
207 MI->getOperand(OpNo).setReg(getX86SubSuperRegister(Reg, MVT::i32));
210 static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
211 // Convert registers in the addr mode according to subreg64.
212 for (unsigned i = 0; i != 4; ++i) {
213 if (!MI->getOperand(OpNo+i).isReg()) continue;
215 unsigned Reg = MI->getOperand(OpNo+i).getReg();
216 if (Reg == 0) continue;
218 MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
222 /// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
223 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
224 OutMI.setOpcode(NewOpc);
225 lower_subreg32(&OutMI, 0);
227 /// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
228 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
229 OutMI.setOpcode(NewOpc);
230 OutMI.addOperand(OutMI.getOperand(0));
231 OutMI.addOperand(OutMI.getOperand(0));
234 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
235 /// a short fixed-register form.
236 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
237 unsigned ImmOp = Inst.getNumOperands() - 1;
238 assert(Inst.getOperand(0).isReg() &&
239 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
240 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
241 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
242 Inst.getNumOperands() == 2) && "Unexpected instruction!");
244 // Check whether the destination register can be fixed.
245 unsigned Reg = Inst.getOperand(0).getReg();
246 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
249 // If so, rewrite the instruction.
250 MCOperand Saved = Inst.getOperand(ImmOp);
252 Inst.setOpcode(Opcode);
253 Inst.addOperand(Saved);
256 /// \brief Simplify things like MOV32rm to MOV32o32a.
257 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
259 // Don't make these simplifications in 64-bit mode; other assemblers don't
260 // perform them because they make the code larger.
261 if (Printer.getSubtarget().is64Bit())
264 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
265 unsigned AddrBase = IsStore;
266 unsigned RegOp = IsStore ? 0 : 5;
267 unsigned AddrOp = AddrBase + 3;
268 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
269 Inst.getOperand(AddrBase + 0).isReg() && // base
270 Inst.getOperand(AddrBase + 1).isImm() && // scale
271 Inst.getOperand(AddrBase + 2).isReg() && // index register
272 (Inst.getOperand(AddrOp).isExpr() || // address
273 Inst.getOperand(AddrOp).isImm())&&
274 Inst.getOperand(AddrBase + 4).isReg() && // segment
275 "Unexpected instruction!");
277 // Check whether the destination register can be fixed.
278 unsigned Reg = Inst.getOperand(RegOp).getReg();
279 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
282 // Check whether this is an absolute address.
283 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
285 bool Absolute = true;
286 if (Inst.getOperand(AddrOp).isExpr()) {
287 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
288 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
289 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
294 (Inst.getOperand(AddrBase + 0).getReg() != 0 ||
295 Inst.getOperand(AddrBase + 2).getReg() != 0 ||
296 Inst.getOperand(AddrBase + 4).getReg() != 0 ||
297 Inst.getOperand(AddrBase + 1).getImm() != 1))
300 // If so, rewrite the instruction.
301 MCOperand Saved = Inst.getOperand(AddrOp);
303 Inst.setOpcode(Opcode);
304 Inst.addOperand(Saved);
307 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
308 OutMI.setOpcode(MI->getOpcode());
310 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
311 const MachineOperand &MO = MI->getOperand(i);
314 switch (MO.getType()) {
317 llvm_unreachable("unknown operand type");
318 case MachineOperand::MO_Register:
319 // Ignore all implicit register operands.
320 if (MO.isImplicit()) continue;
321 MCOp = MCOperand::CreateReg(MO.getReg());
323 case MachineOperand::MO_Immediate:
324 MCOp = MCOperand::CreateImm(MO.getImm());
326 case MachineOperand::MO_MachineBasicBlock:
327 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
328 MO.getMBB()->getSymbol(), Ctx));
330 case MachineOperand::MO_GlobalAddress:
331 case MachineOperand::MO_ExternalSymbol:
332 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
334 case MachineOperand::MO_JumpTableIndex:
335 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
337 case MachineOperand::MO_ConstantPoolIndex:
338 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
340 case MachineOperand::MO_BlockAddress:
341 MCOp = LowerSymbolOperand(MO,
342 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
344 case MachineOperand::MO_RegisterMask:
345 // Ignore call clobbers.
349 OutMI.addOperand(MCOp);
352 // Handle a few special cases to eliminate operand modifiers.
354 switch (OutMI.getOpcode()) {
355 case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
356 lower_lea64_32mem(&OutMI, 1);
361 // LEA should have a segment register, but it must be empty.
362 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
363 "Unexpected # of LEA operands");
364 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
365 "LEA has segment specified!");
367 case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
368 case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
369 case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
370 case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
371 case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
372 case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
373 case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
374 case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
375 case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
376 case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
377 case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
378 case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
379 case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
382 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
383 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
386 LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
387 LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
390 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
391 // inputs modeled as normal uses instead of implicit uses. As such, truncate
392 // off all but the first operand (the callee). FIXME: Change isel.
393 case X86::TAILJMPr64:
395 case X86::CALL64pcrel32: {
396 unsigned Opcode = OutMI.getOpcode();
397 MCOperand Saved = OutMI.getOperand(0);
399 OutMI.setOpcode(Opcode);
400 OutMI.addOperand(Saved);
405 case X86::EH_RETURN64: {
407 OutMI.setOpcode(X86::RET);
411 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
414 case X86::TAILJMPd64: {
416 switch (OutMI.getOpcode()) {
417 default: llvm_unreachable("Invalid opcode");
418 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
420 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
423 MCOperand Saved = OutMI.getOperand(0);
425 OutMI.setOpcode(Opcode);
426 OutMI.addOperand(Saved);
430 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
431 // this with an ugly goto in case the resultant OR uses EAX and needs the
433 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
434 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
435 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
436 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
437 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
438 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
439 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
440 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
441 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
443 // The assembler backend wants to see branches in their small form and relax
444 // them to their large form. The JIT can only handle the large form because
445 // it does not do relaxation. For now, translate the large form to the
447 case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
448 case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
449 case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
450 case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
451 case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
452 case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
453 case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
454 case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
455 case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
456 case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
457 case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
458 case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
459 case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
460 case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
461 case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
462 case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
463 case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
465 // Atomic load and store require a separate pseudo-inst because Acquire
466 // implies mayStore and Release implies mayLoad; fix these to regular MOV
468 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
469 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
470 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
471 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
472 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
473 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
474 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
475 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
477 // We don't currently select the correct instruction form for instructions
478 // which have a short %eax, etc. form. Handle this by custom lowering, for
481 // Note, we are currently not handling the following instructions:
482 // MOV64ao8, MOV64o8a
483 // XCHG16ar, XCHG32ar, XCHG64ar
484 case X86::MOV8mr_NOREX:
485 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
486 case X86::MOV8rm_NOREX:
487 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
488 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
489 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
490 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
491 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
493 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
494 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
495 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
496 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
497 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
498 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
499 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
500 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
501 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
502 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
503 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
504 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
505 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
506 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
507 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
508 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
509 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
510 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
511 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
512 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
513 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
514 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
515 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
516 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
517 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
518 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
519 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
520 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
521 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
522 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
523 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
524 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
525 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
526 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
527 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
528 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
530 case X86::MORESTACK_RET:
531 OutMI.setOpcode(X86::RET);
534 case X86::MORESTACK_RET_RESTORE_R10: {
537 OutMI.setOpcode(X86::MOV64rr);
538 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
539 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
541 retInst.setOpcode(X86::RET);
542 AsmPrinter.OutStreamer.EmitInstruction(retInst);
548 static void LowerTlsAddr(MCStreamer &OutStreamer,
549 X86MCInstLower &MCInstLowering,
550 const MachineInstr &MI) {
552 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
553 MI.getOpcode() == X86::TLS_base_addr64;
555 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
557 MCContext &context = OutStreamer.getContext();
561 prefix.setOpcode(X86::DATA16_PREFIX);
562 OutStreamer.EmitInstruction(prefix);
565 MCSymbolRefExpr::VariantKind SRVK;
566 switch (MI.getOpcode()) {
567 case X86::TLS_addr32:
568 case X86::TLS_addr64:
569 SRVK = MCSymbolRefExpr::VK_TLSGD;
571 case X86::TLS_base_addr32:
572 SRVK = MCSymbolRefExpr::VK_TLSLDM;
574 case X86::TLS_base_addr64:
575 SRVK = MCSymbolRefExpr::VK_TLSLD;
578 llvm_unreachable("unexpected opcode");
581 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
582 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::Create(sym, SRVK, context);
586 LEA.setOpcode(X86::LEA64r);
587 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest
588 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base
589 LEA.addOperand(MCOperand::CreateImm(1)); // scale
590 LEA.addOperand(MCOperand::CreateReg(0)); // index
591 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
592 LEA.addOperand(MCOperand::CreateReg(0)); // seg
593 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
594 LEA.setOpcode(X86::LEA32r);
595 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
596 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base
597 LEA.addOperand(MCOperand::CreateImm(1)); // scale
598 LEA.addOperand(MCOperand::CreateReg(0)); // index
599 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
600 LEA.addOperand(MCOperand::CreateReg(0)); // seg
602 LEA.setOpcode(X86::LEA32r);
603 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest
604 LEA.addOperand(MCOperand::CreateReg(0)); // base
605 LEA.addOperand(MCOperand::CreateImm(1)); // scale
606 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // index
607 LEA.addOperand(MCOperand::CreateExpr(symRef)); // disp
608 LEA.addOperand(MCOperand::CreateReg(0)); // seg
610 OutStreamer.EmitInstruction(LEA);
614 prefix.setOpcode(X86::DATA16_PREFIX);
615 OutStreamer.EmitInstruction(prefix);
616 prefix.setOpcode(X86::DATA16_PREFIX);
617 OutStreamer.EmitInstruction(prefix);
618 prefix.setOpcode(X86::REX64_PREFIX);
619 OutStreamer.EmitInstruction(prefix);
624 call.setOpcode(X86::CALL64pcrel32);
626 call.setOpcode(X86::CALLpcrel32);
627 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
628 MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
629 const MCSymbolRefExpr *tlsRef =
630 MCSymbolRefExpr::Create(tlsGetAddr,
631 MCSymbolRefExpr::VK_PLT,
634 call.addOperand(MCOperand::CreateExpr(tlsRef));
635 OutStreamer.EmitInstruction(call);
638 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
639 X86MCInstLower MCInstLowering(Mang, *MF, *this);
640 switch (MI->getOpcode()) {
641 case TargetOpcode::DBG_VALUE:
642 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
644 raw_string_ostream OS(TmpStr);
645 PrintDebugValueComment(MI, OS);
646 OutStreamer.EmitRawText(StringRef(OS.str()));
650 // Emit nothing here but a comment if we can.
651 case X86::Int_MemBarrier:
652 if (OutStreamer.hasRawTextSupport())
653 OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER"));
658 case X86::EH_RETURN64: {
659 // Lower these as normal, but add some comments.
660 unsigned Reg = MI->getOperand(0).getReg();
661 OutStreamer.AddComment(StringRef("eh_return, addr: %") +
662 X86ATTInstPrinter::getRegisterName(Reg));
667 case X86::TAILJMPd64:
668 // Lower these as normal, but add some comments.
669 OutStreamer.AddComment("TAILCALL");
672 case X86::TLS_addr32:
673 case X86::TLS_addr64:
674 case X86::TLS_base_addr32:
675 case X86::TLS_base_addr64:
676 return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
678 case X86::MOVPC32r: {
680 // This is a pseudo op for a two instruction sequence with a label, which
687 MCSymbol *PICBase = MF->getPICBaseSymbol();
688 TmpInst.setOpcode(X86::CALLpcrel32);
689 // FIXME: We would like an efficient form for this, so we don't have to do a
690 // lot of extra uniquing.
691 TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
693 OutStreamer.EmitInstruction(TmpInst);
696 OutStreamer.EmitLabel(PICBase);
699 TmpInst.setOpcode(X86::POP32r);
700 TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
701 OutStreamer.EmitInstruction(TmpInst);
706 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
707 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
710 // Okay, we have something like:
711 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
713 // For this, we want to print something like:
714 // MYGLOBAL + (. - PICBASE)
715 // However, we can't generate a ".", so just emit a new label here and refer
717 MCSymbol *DotSym = OutContext.CreateTempSymbol();
718 OutStreamer.EmitLabel(DotSym);
720 // Now that we have emitted the label, lower the complex operand expression.
721 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
723 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
724 const MCExpr *PICBase =
725 MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext);
726 DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
728 DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
729 DotExpr, OutContext);
732 TmpInst.setOpcode(X86::ADD32ri);
733 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
734 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
735 TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
736 OutStreamer.EmitInstruction(TmpInst);
742 MCInstLowering.Lower(MI, TmpInst);
743 OutStreamer.EmitInstruction(TmpInst);