1 //===-- X86MCInstLower.cpp - Convert X86 MachineInstr to an MCInst --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains code to lower X86 MachineInstrs to their corresponding
13 //===----------------------------------------------------------------------===//
15 #include "X86AsmPrinter.h"
16 #include "X86RegisterInfo.h"
17 #include "InstPrinter/X86ATTInstPrinter.h"
18 #include "MCTargetDesc/X86BaseInfo.h"
19 #include "Utils/X86ShuffleDecode.h"
20 #include "llvm/ADT/SmallString.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineConstantPool.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
25 #include "llvm/CodeGen/StackMaps.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Mangler.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCCodeEmitter.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCExpr.h"
33 #include "llvm/MC/MCFixup.h"
34 #include "llvm/MC/MCInst.h"
35 #include "llvm/MC/MCInstBuilder.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSymbol.h"
38 #include "llvm/Support/TargetRegistry.h"
43 /// X86MCInstLower - This class is used to lower an MachineInstr into an MCInst.
44 class X86MCInstLower {
46 const MachineFunction &MF;
47 const TargetMachine &TM;
49 X86AsmPrinter &AsmPrinter;
51 X86MCInstLower(const MachineFunction &MF, X86AsmPrinter &asmprinter);
53 void Lower(const MachineInstr *MI, MCInst &OutMI) const;
55 MCSymbol *GetSymbolFromOperand(const MachineOperand &MO) const;
56 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
59 MachineModuleInfoMachO &getMachOMMI() const;
60 Mangler *getMang() const {
61 return AsmPrinter.Mang;
65 } // end anonymous namespace
67 // Emit a minimal sequence of nops spanning NumBytes bytes.
68 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit,
69 const MCSubtargetInfo &STI);
72 X86AsmPrinter::StackMapShadowTracker::StackMapShadowTracker(TargetMachine &TM)
73 : TM(TM), InShadow(false), RequiredShadowSize(0), CurrentShadowSize(0) {}
75 X86AsmPrinter::StackMapShadowTracker::~StackMapShadowTracker() {}
78 X86AsmPrinter::StackMapShadowTracker::startFunction(MachineFunction &F) {
80 CodeEmitter.reset(TM.getTarget().createMCCodeEmitter(
81 *MF->getSubtarget().getInstrInfo(),
82 *MF->getSubtarget().getRegisterInfo(), MF->getContext()));
85 void X86AsmPrinter::StackMapShadowTracker::count(MCInst &Inst,
86 const MCSubtargetInfo &STI) {
88 SmallString<256> Code;
89 SmallVector<MCFixup, 4> Fixups;
90 raw_svector_ostream VecOS(Code);
91 CodeEmitter->encodeInstruction(Inst, VecOS, Fixups, STI);
93 CurrentShadowSize += Code.size();
94 if (CurrentShadowSize >= RequiredShadowSize)
95 InShadow = false; // The shadow is big enough. Stop counting.
99 void X86AsmPrinter::StackMapShadowTracker::emitShadowPadding(
100 MCStreamer &OutStreamer, const MCSubtargetInfo &STI) {
101 if (InShadow && CurrentShadowSize < RequiredShadowSize) {
103 EmitNops(OutStreamer, RequiredShadowSize - CurrentShadowSize,
104 MF->getSubtarget<X86Subtarget>().is64Bit(), STI);
108 void X86AsmPrinter::EmitAndCountInstruction(MCInst &Inst) {
109 OutStreamer->EmitInstruction(Inst, getSubtargetInfo());
110 SMShadowTracker.count(Inst, getSubtargetInfo());
112 } // end llvm namespace
114 X86MCInstLower::X86MCInstLower(const MachineFunction &mf,
115 X86AsmPrinter &asmprinter)
116 : Ctx(mf.getContext()), MF(mf), TM(mf.getTarget()), MAI(*TM.getMCAsmInfo()),
117 AsmPrinter(asmprinter) {}
119 MachineModuleInfoMachO &X86MCInstLower::getMachOMMI() const {
120 return MF.getMMI().getObjFileInfo<MachineModuleInfoMachO>();
124 /// GetSymbolFromOperand - Lower an MO_GlobalAddress or MO_ExternalSymbol
125 /// operand to an MCSymbol.
126 MCSymbol *X86MCInstLower::
127 GetSymbolFromOperand(const MachineOperand &MO) const {
128 const DataLayout *DL = TM.getDataLayout();
129 assert((MO.isGlobal() || MO.isSymbol() || MO.isMBB()) && "Isn't a symbol reference");
131 MCSymbol *Sym = nullptr;
132 SmallString<128> Name;
135 switch (MO.getTargetFlags()) {
136 case X86II::MO_DARWIN_STUB:
139 case X86II::MO_DARWIN_NONLAZY:
140 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
141 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
142 Suffix = "$non_lazy_ptr";
147 Name += DL->getPrivateGlobalPrefix();
149 unsigned PrefixLen = Name.size();
152 const GlobalValue *GV = MO.getGlobal();
153 AsmPrinter.getNameWithPrefix(Name, GV);
154 } else if (MO.isSymbol()) {
155 if (MO.getTargetFlags() == X86II::MO_NOPREFIX)
156 Name += MO.getSymbolName();
158 getMang()->getNameWithPrefix(Name, MO.getSymbolName());
159 } else if (MO.isMBB()) {
160 assert(Suffix.empty());
161 Sym = MO.getMBB()->getSymbol();
163 unsigned OrigLen = Name.size() - PrefixLen;
167 Sym = Ctx.getOrCreateSymbol(Name);
169 StringRef OrigName = StringRef(Name).substr(PrefixLen, OrigLen);
171 // If the target flags on the operand changes the name of the symbol, do that
172 // before we return the symbol.
173 switch (MO.getTargetFlags()) {
175 case X86II::MO_DARWIN_NONLAZY:
176 case X86II::MO_DARWIN_NONLAZY_PIC_BASE: {
177 MachineModuleInfoImpl::StubValueTy &StubSym =
178 getMachOMMI().getGVStubEntry(Sym);
179 if (!StubSym.getPointer()) {
180 assert(MO.isGlobal() && "Extern symbol not handled yet");
182 MachineModuleInfoImpl::
183 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
184 !MO.getGlobal()->hasInternalLinkage());
188 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: {
189 MachineModuleInfoImpl::StubValueTy &StubSym =
190 getMachOMMI().getHiddenGVStubEntry(Sym);
191 if (!StubSym.getPointer()) {
192 assert(MO.isGlobal() && "Extern symbol not handled yet");
194 MachineModuleInfoImpl::
195 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
196 !MO.getGlobal()->hasInternalLinkage());
200 case X86II::MO_DARWIN_STUB: {
201 MachineModuleInfoImpl::StubValueTy &StubSym =
202 getMachOMMI().getFnStubEntry(Sym);
203 if (StubSym.getPointer())
208 MachineModuleInfoImpl::
209 StubValueTy(AsmPrinter.getSymbol(MO.getGlobal()),
210 !MO.getGlobal()->hasInternalLinkage());
213 MachineModuleInfoImpl::
214 StubValueTy(Ctx.getOrCreateSymbol(OrigName), false);
223 MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
224 MCSymbol *Sym) const {
225 // FIXME: We would like an efficient form for this, so we don't have to do a
226 // lot of extra uniquing.
227 const MCExpr *Expr = nullptr;
228 MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None;
230 switch (MO.getTargetFlags()) {
231 default: llvm_unreachable("Unknown target flag on GV operand");
232 case X86II::MO_NO_FLAG: // No flag.
233 // These affect the name of the symbol, not any suffix.
234 case X86II::MO_DARWIN_NONLAZY:
235 case X86II::MO_DLLIMPORT:
236 case X86II::MO_DARWIN_STUB:
237 case X86II::MO_NOPREFIX:
240 case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break;
241 case X86II::MO_TLVP_PIC_BASE:
242 Expr = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx);
243 // Subtract the pic base.
244 Expr = MCBinaryExpr::createSub(Expr,
245 MCSymbolRefExpr::create(MF.getPICBaseSymbol(),
249 case X86II::MO_SECREL: RefKind = MCSymbolRefExpr::VK_SECREL; break;
250 case X86II::MO_TLSGD: RefKind = MCSymbolRefExpr::VK_TLSGD; break;
251 case X86II::MO_TLSLD: RefKind = MCSymbolRefExpr::VK_TLSLD; break;
252 case X86II::MO_TLSLDM: RefKind = MCSymbolRefExpr::VK_TLSLDM; break;
253 case X86II::MO_GOTTPOFF: RefKind = MCSymbolRefExpr::VK_GOTTPOFF; break;
254 case X86II::MO_INDNTPOFF: RefKind = MCSymbolRefExpr::VK_INDNTPOFF; break;
255 case X86II::MO_TPOFF: RefKind = MCSymbolRefExpr::VK_TPOFF; break;
256 case X86II::MO_DTPOFF: RefKind = MCSymbolRefExpr::VK_DTPOFF; break;
257 case X86II::MO_NTPOFF: RefKind = MCSymbolRefExpr::VK_NTPOFF; break;
258 case X86II::MO_GOTNTPOFF: RefKind = MCSymbolRefExpr::VK_GOTNTPOFF; break;
259 case X86II::MO_GOTPCREL: RefKind = MCSymbolRefExpr::VK_GOTPCREL; break;
260 case X86II::MO_GOT: RefKind = MCSymbolRefExpr::VK_GOT; break;
261 case X86II::MO_GOTOFF: RefKind = MCSymbolRefExpr::VK_GOTOFF; break;
262 case X86II::MO_PLT: RefKind = MCSymbolRefExpr::VK_PLT; break;
263 case X86II::MO_PIC_BASE_OFFSET:
264 case X86II::MO_DARWIN_NONLAZY_PIC_BASE:
265 case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
266 Expr = MCSymbolRefExpr::create(Sym, Ctx);
267 // Subtract the pic base.
268 Expr = MCBinaryExpr::createSub(Expr,
269 MCSymbolRefExpr::create(MF.getPICBaseSymbol(), Ctx),
272 assert(MAI.doesSetDirectiveSuppressesReloc());
273 // If .set directive is supported, use it to reduce the number of
274 // relocations the assembler will generate for differences between
275 // local labels. This is only safe when the symbols are in the same
276 // section so we are restricting it to jumptable references.
277 MCSymbol *Label = Ctx.createTempSymbol();
278 AsmPrinter.OutStreamer->EmitAssignment(Label, Expr);
279 Expr = MCSymbolRefExpr::create(Label, Ctx);
285 Expr = MCSymbolRefExpr::create(Sym, RefKind, Ctx);
287 if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
288 Expr = MCBinaryExpr::createAdd(Expr,
289 MCConstantExpr::create(MO.getOffset(), Ctx),
291 return MCOperand::createExpr(Expr);
295 /// \brief Simplify FOO $imm, %{al,ax,eax,rax} to FOO $imm, for instruction with
296 /// a short fixed-register form.
297 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) {
298 unsigned ImmOp = Inst.getNumOperands() - 1;
299 assert(Inst.getOperand(0).isReg() &&
300 (Inst.getOperand(ImmOp).isImm() || Inst.getOperand(ImmOp).isExpr()) &&
301 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() &&
302 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) ||
303 Inst.getNumOperands() == 2) && "Unexpected instruction!");
305 // Check whether the destination register can be fixed.
306 unsigned Reg = Inst.getOperand(0).getReg();
307 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
310 // If so, rewrite the instruction.
311 MCOperand Saved = Inst.getOperand(ImmOp);
313 Inst.setOpcode(Opcode);
314 Inst.addOperand(Saved);
317 /// \brief If a movsx instruction has a shorter encoding for the used register
318 /// simplify the instruction to use it instead.
319 static void SimplifyMOVSX(MCInst &Inst) {
320 unsigned NewOpcode = 0;
321 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
322 switch (Inst.getOpcode()) {
324 llvm_unreachable("Unexpected instruction!");
325 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw
326 if (Op0 == X86::AX && Op1 == X86::AL)
327 NewOpcode = X86::CBW;
329 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl
330 if (Op0 == X86::EAX && Op1 == X86::AX)
331 NewOpcode = X86::CWDE;
333 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq
334 if (Op0 == X86::RAX && Op1 == X86::EAX)
335 NewOpcode = X86::CDQE;
339 if (NewOpcode != 0) {
341 Inst.setOpcode(NewOpcode);
345 /// \brief Simplify things like MOV32rm to MOV32o32a.
346 static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst,
348 // Don't make these simplifications in 64-bit mode; other assemblers don't
349 // perform them because they make the code larger.
350 if (Printer.getSubtarget().is64Bit())
353 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg();
354 unsigned AddrBase = IsStore;
355 unsigned RegOp = IsStore ? 0 : 5;
356 unsigned AddrOp = AddrBase + 3;
357 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() &&
358 Inst.getOperand(AddrBase + X86::AddrBaseReg).isReg() &&
359 Inst.getOperand(AddrBase + X86::AddrScaleAmt).isImm() &&
360 Inst.getOperand(AddrBase + X86::AddrIndexReg).isReg() &&
361 Inst.getOperand(AddrBase + X86::AddrSegmentReg).isReg() &&
362 (Inst.getOperand(AddrOp).isExpr() ||
363 Inst.getOperand(AddrOp).isImm()) &&
364 "Unexpected instruction!");
366 // Check whether the destination register can be fixed.
367 unsigned Reg = Inst.getOperand(RegOp).getReg();
368 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX)
371 // Check whether this is an absolute address.
372 // FIXME: We know TLVP symbol refs aren't, but there should be a better way
374 bool Absolute = true;
375 if (Inst.getOperand(AddrOp).isExpr()) {
376 const MCExpr *MCE = Inst.getOperand(AddrOp).getExpr();
377 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(MCE))
378 if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP)
383 (Inst.getOperand(AddrBase + X86::AddrBaseReg).getReg() != 0 ||
384 Inst.getOperand(AddrBase + X86::AddrScaleAmt).getImm() != 1 ||
385 Inst.getOperand(AddrBase + X86::AddrIndexReg).getReg() != 0))
388 // If so, rewrite the instruction.
389 MCOperand Saved = Inst.getOperand(AddrOp);
390 MCOperand Seg = Inst.getOperand(AddrBase + X86::AddrSegmentReg);
392 Inst.setOpcode(Opcode);
393 Inst.addOperand(Saved);
394 Inst.addOperand(Seg);
397 static unsigned getRetOpcode(const X86Subtarget &Subtarget) {
398 return Subtarget.is64Bit() ? X86::RETQ : X86::RETL;
401 void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
402 OutMI.setOpcode(MI->getOpcode());
404 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
405 const MachineOperand &MO = MI->getOperand(i);
408 switch (MO.getType()) {
411 llvm_unreachable("unknown operand type");
412 case MachineOperand::MO_Register:
413 // Ignore all implicit register operands.
414 if (MO.isImplicit()) continue;
415 MCOp = MCOperand::createReg(MO.getReg());
417 case MachineOperand::MO_Immediate:
418 MCOp = MCOperand::createImm(MO.getImm());
420 case MachineOperand::MO_MachineBasicBlock:
421 case MachineOperand::MO_GlobalAddress:
422 case MachineOperand::MO_ExternalSymbol:
423 MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
425 case MachineOperand::MO_JumpTableIndex:
426 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
428 case MachineOperand::MO_ConstantPoolIndex:
429 MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
431 case MachineOperand::MO_BlockAddress:
432 MCOp = LowerSymbolOperand(MO,
433 AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
435 case MachineOperand::MO_RegisterMask:
436 // Ignore call clobbers.
440 OutMI.addOperand(MCOp);
443 // Handle a few special cases to eliminate operand modifiers.
445 switch (OutMI.getOpcode()) {
450 // LEA should have a segment register, but it must be empty.
451 assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
452 "Unexpected # of LEA operands");
453 assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
454 "LEA has segment specified!");
458 OutMI.setOpcode(X86::MOV32ri);
461 // Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
462 // if one of the registers is extended, but other isn't.
464 case X86::VMOVAPDYrr:
466 case X86::VMOVAPSYrr:
468 case X86::VMOVDQAYrr:
470 case X86::VMOVDQUYrr:
472 case X86::VMOVUPDYrr:
474 case X86::VMOVUPSYrr: {
475 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
476 X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
478 switch (OutMI.getOpcode()) {
479 default: llvm_unreachable("Invalid opcode");
480 case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
481 case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
482 case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
483 case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
484 case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
485 case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
486 case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
487 case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
488 case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
489 case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
490 case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
491 case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
493 OutMI.setOpcode(NewOpc);
498 case X86::VMOVSSrr: {
499 if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
500 X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
502 switch (OutMI.getOpcode()) {
503 default: llvm_unreachable("Invalid opcode");
504 case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
505 case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
507 OutMI.setOpcode(NewOpc);
512 // TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
513 // inputs modeled as normal uses instead of implicit uses. As such, truncate
514 // off all but the first operand (the callee). FIXME: Change isel.
515 case X86::TAILJMPr64:
516 case X86::TAILJMPr64_REX:
518 case X86::CALL64pcrel32: {
519 unsigned Opcode = OutMI.getOpcode();
520 MCOperand Saved = OutMI.getOperand(0);
522 OutMI.setOpcode(Opcode);
523 OutMI.addOperand(Saved);
528 case X86::EH_RETURN64: {
530 OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
534 // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
537 case X86::TAILJMPd64: {
539 switch (OutMI.getOpcode()) {
540 default: llvm_unreachable("Invalid opcode");
541 case X86::TAILJMPr: Opcode = X86::JMP32r; break;
543 case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
546 MCOperand Saved = OutMI.getOperand(0);
548 OutMI.setOpcode(Opcode);
549 OutMI.addOperand(Saved);
557 // If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
558 if (!AsmPrinter.getSubtarget().is64Bit()) {
560 switch (OutMI.getOpcode()) {
561 default: llvm_unreachable("Invalid opcode");
562 case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
563 case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
564 case X86::INC16r: Opcode = X86::INC16r_alt; break;
565 case X86::INC32r: Opcode = X86::INC32r_alt; break;
567 OutMI.setOpcode(Opcode);
571 // These are pseudo-ops for OR to help with the OR->ADD transformation. We do
572 // this with an ugly goto in case the resultant OR uses EAX and needs the
574 case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
575 case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
576 case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
577 case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
578 case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
579 case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
580 case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
581 case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
582 case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
584 // Atomic load and store require a separate pseudo-inst because Acquire
585 // implies mayStore and Release implies mayLoad; fix these to regular MOV
587 case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
588 case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
589 case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
590 case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
591 case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
592 case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
593 case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
594 case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
595 case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
596 case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
597 case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
598 case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
599 case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
600 case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
601 case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
602 case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
603 case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
604 case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
605 case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
606 case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
607 case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
608 case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
609 case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
610 case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
611 case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
612 case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
613 case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
614 case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
615 case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
616 case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
617 case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
618 case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
620 // We don't currently select the correct instruction form for instructions
621 // which have a short %eax, etc. form. Handle this by custom lowering, for
624 // Note, we are currently not handling the following instructions:
625 // MOV64ao8, MOV64o8a
626 // XCHG16ar, XCHG32ar, XCHG64ar
627 case X86::MOV8mr_NOREX:
628 case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
629 case X86::MOV8rm_NOREX:
630 case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
631 case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
632 case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
633 case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
634 case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
636 case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
637 case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
638 case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
639 case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
640 case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
641 case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
642 case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
643 case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
644 case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
645 case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
646 case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
647 case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
648 case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
649 case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
650 case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
651 case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
652 case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
653 case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
654 case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
655 case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
656 case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
657 case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
658 case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
659 case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
660 case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
661 case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
662 case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
663 case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
664 case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
665 case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
666 case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
667 case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
668 case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
669 case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
670 case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
671 case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
673 // Try to shrink some forms of movsx.
674 case X86::MOVSX16rr8:
675 case X86::MOVSX32rr16:
676 case X86::MOVSX64rr32:
677 SimplifyMOVSX(OutMI);
682 void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
683 const MachineInstr &MI) {
685 bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
686 MI.getOpcode() == X86::TLS_base_addr64;
688 bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
690 MCContext &context = OutStreamer->getContext();
693 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
695 MCSymbolRefExpr::VariantKind SRVK;
696 switch (MI.getOpcode()) {
697 case X86::TLS_addr32:
698 case X86::TLS_addr64:
699 SRVK = MCSymbolRefExpr::VK_TLSGD;
701 case X86::TLS_base_addr32:
702 SRVK = MCSymbolRefExpr::VK_TLSLDM;
704 case X86::TLS_base_addr64:
705 SRVK = MCSymbolRefExpr::VK_TLSLD;
708 llvm_unreachable("unexpected opcode");
711 MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
712 const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
716 LEA.setOpcode(X86::LEA64r);
717 LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
718 LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
719 LEA.addOperand(MCOperand::createImm(1)); // scale
720 LEA.addOperand(MCOperand::createReg(0)); // index
721 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
722 LEA.addOperand(MCOperand::createReg(0)); // seg
723 } else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
724 LEA.setOpcode(X86::LEA32r);
725 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
726 LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
727 LEA.addOperand(MCOperand::createImm(1)); // scale
728 LEA.addOperand(MCOperand::createReg(0)); // index
729 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
730 LEA.addOperand(MCOperand::createReg(0)); // seg
732 LEA.setOpcode(X86::LEA32r);
733 LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
734 LEA.addOperand(MCOperand::createReg(0)); // base
735 LEA.addOperand(MCOperand::createImm(1)); // scale
736 LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
737 LEA.addOperand(MCOperand::createExpr(symRef)); // disp
738 LEA.addOperand(MCOperand::createReg(0)); // seg
740 EmitAndCountInstruction(LEA);
743 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
744 EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
745 EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
748 StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
749 MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
750 const MCSymbolRefExpr *tlsRef =
751 MCSymbolRefExpr::create(tlsGetAddr,
752 MCSymbolRefExpr::VK_PLT,
755 EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
760 /// \brief Emit the optimal amount of multi-byte nops on X86.
761 static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit, const MCSubtargetInfo &STI) {
762 // This works only for 64bit. For 32bit we have to do additional checking if
763 // the CPU supports multi-byte nops.
764 assert(Is64Bit && "EmitNops only supports X86-64");
766 unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
767 Opc = IndexReg = Displacement = SegmentReg = 0;
768 BaseReg = X86::RAX; ScaleVal = 1;
770 case 0: llvm_unreachable("Zero nops?"); break;
771 case 1: NumBytes -= 1; Opc = X86::NOOP; break;
772 case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
773 case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
774 case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
775 case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
776 IndexReg = X86::RAX; break;
777 case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
778 IndexReg = X86::RAX; break;
779 case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
780 case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
781 IndexReg = X86::RAX; break;
782 case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
783 IndexReg = X86::RAX; break;
784 default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
785 IndexReg = X86::RAX; SegmentReg = X86::CS; break;
788 unsigned NumPrefixes = std::min(NumBytes, 5U);
789 NumBytes -= NumPrefixes;
790 for (unsigned i = 0; i != NumPrefixes; ++i)
791 OS.EmitBytes("\x66");
794 default: llvm_unreachable("Unexpected opcode"); break;
796 OS.EmitInstruction(MCInstBuilder(Opc), STI);
799 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX), STI);
803 OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg)
804 .addImm(ScaleVal).addReg(IndexReg)
805 .addImm(Displacement).addReg(SegmentReg), STI);
808 } // while (NumBytes)
811 void X86AsmPrinter::LowerSTATEPOINT(const MachineInstr &MI,
812 X86MCInstLower &MCIL) {
813 assert(Subtarget->is64Bit() && "Statepoint currently only supports X86-64");
815 StatepointOpers SOpers(&MI);
816 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
817 EmitNops(*OutStreamer, PatchBytes, Subtarget->is64Bit(),
820 // Lower call target and choose correct opcode
821 const MachineOperand &CallTarget = SOpers.getCallTarget();
822 MCOperand CallTargetMCOp;
824 switch (CallTarget.getType()) {
825 case MachineOperand::MO_GlobalAddress:
826 case MachineOperand::MO_ExternalSymbol:
827 CallTargetMCOp = MCIL.LowerSymbolOperand(
828 CallTarget, MCIL.GetSymbolFromOperand(CallTarget));
829 CallOpcode = X86::CALL64pcrel32;
830 // Currently, we only support relative addressing with statepoints.
831 // Otherwise, we'll need a scratch register to hold the target
832 // address. You'll fail asserts during load & relocation if this
833 // symbol is to far away. (TODO: support non-relative addressing)
835 case MachineOperand::MO_Immediate:
836 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
837 CallOpcode = X86::CALL64pcrel32;
838 // Currently, we only support relative addressing with statepoints.
839 // Otherwise, we'll need a scratch register to hold the target
840 // immediate. You'll fail asserts during load & relocation if this
841 // address is to far away. (TODO: support non-relative addressing)
843 case MachineOperand::MO_Register:
844 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
845 CallOpcode = X86::CALL64r;
848 llvm_unreachable("Unsupported operand type in statepoint call target");
854 CallInst.setOpcode(CallOpcode);
855 CallInst.addOperand(CallTargetMCOp);
856 OutStreamer->EmitInstruction(CallInst, getSubtargetInfo());
859 // Record our statepoint node in the same section used by STACKMAP
861 SM.recordStatepoint(MI);
865 // Lower a stackmap of the form:
866 // <id>, <shadowBytes>, ...
867 void X86AsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
868 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
869 SM.recordStackMap(MI);
870 unsigned NumShadowBytes = MI.getOperand(1).getImm();
871 SMShadowTracker.reset(NumShadowBytes);
874 // Lower a patchpoint of the form:
875 // [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
876 void X86AsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
877 X86MCInstLower &MCIL) {
878 assert(Subtarget->is64Bit() && "Patchpoint currently only supports X86-64");
880 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
882 SM.recordPatchPoint(MI);
884 PatchPointOpers opers(&MI);
885 unsigned ScratchIdx = opers.getNextScratchIdx();
886 unsigned EncodedBytes = 0;
887 const MachineOperand &CalleeMO =
888 opers.getMetaOper(PatchPointOpers::TargetPos);
890 // Check for null target. If target is non-null (i.e. is non-zero or is
891 // symbolic) then emit a call.
892 if (!(CalleeMO.isImm() && !CalleeMO.getImm())) {
893 MCOperand CalleeMCOp;
894 switch (CalleeMO.getType()) {
896 /// FIXME: Add a verifier check for bad callee types.
897 llvm_unreachable("Unrecognized callee operand type.");
898 case MachineOperand::MO_Immediate:
899 if (CalleeMO.getImm())
900 CalleeMCOp = MCOperand::createImm(CalleeMO.getImm());
902 case MachineOperand::MO_ExternalSymbol:
903 case MachineOperand::MO_GlobalAddress:
905 MCIL.LowerSymbolOperand(CalleeMO,
906 MCIL.GetSymbolFromOperand(CalleeMO));
910 // Emit MOV to materialize the target address and the CALL to target.
911 // This is encoded with 12-13 bytes, depending on which register is used.
912 unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
913 if (X86II::isX86_64ExtendedReg(ScratchReg))
918 EmitAndCountInstruction(
919 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp));
920 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
924 unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
925 assert(NumBytes >= EncodedBytes &&
926 "Patchpoint can't request size less than the length of a call.");
928 EmitNops(*OutStreamer, NumBytes - EncodedBytes, Subtarget->is64Bit(),
932 // Returns instruction preceding MBBI in MachineFunction.
933 // If MBBI is the first instruction of the first basic block, returns null.
934 static MachineBasicBlock::const_iterator
935 PrevCrossBBInst(MachineBasicBlock::const_iterator MBBI) {
936 const MachineBasicBlock *MBB = MBBI->getParent();
937 while (MBBI == MBB->begin()) {
938 if (MBB == MBB->getParent()->begin())
940 MBB = MBB->getPrevNode();
946 static const Constant *getConstantFromPool(const MachineInstr &MI,
947 const MachineOperand &Op) {
951 ArrayRef<MachineConstantPoolEntry> Constants =
952 MI.getParent()->getParent()->getConstantPool()->getConstants();
953 const MachineConstantPoolEntry &ConstantEntry =
954 Constants[Op.getIndex()];
956 // Bail if this is a machine constant pool entry, we won't be able to dig out
958 if (ConstantEntry.isMachineConstantPoolEntry())
961 auto *C = dyn_cast<Constant>(ConstantEntry.Val.ConstVal);
962 assert((!C || ConstantEntry.getType() == C->getType()) &&
963 "Expected a constant of the same type!");
967 static std::string getShuffleComment(const MachineOperand &DstOp,
968 const MachineOperand &SrcOp,
969 ArrayRef<int> Mask) {
972 // Compute the name for a register. This is really goofy because we have
973 // multiple instruction printers that could (in theory) use different
974 // names. Fortunately most people use the ATT style (outside of Windows)
975 // and they actually agree on register naming here. Ultimately, this is
976 // a comment, and so its OK if it isn't perfect.
977 auto GetRegisterName = [](unsigned RegNum) -> StringRef {
978 return X86ATTInstPrinter::getRegisterName(RegNum);
981 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
982 StringRef SrcName = SrcOp.isReg() ? GetRegisterName(SrcOp.getReg()) : "mem";
984 raw_string_ostream CS(Comment);
985 CS << DstName << " = ";
986 bool NeedComma = false;
989 // Wrap up any prior entry...
990 if (M == SM_SentinelZero && InSrc) {
999 // Print this shuffle...
1000 if (M == SM_SentinelZero) {
1005 CS << SrcName << "[";
1007 if (M == SM_SentinelUndef)
1020 void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
1021 X86MCInstLower MCInstLowering(*MF, *this);
1022 const X86RegisterInfo *RI = MF->getSubtarget<X86Subtarget>().getRegisterInfo();
1024 switch (MI->getOpcode()) {
1025 case TargetOpcode::DBG_VALUE:
1026 llvm_unreachable("Should be handled target independently");
1028 // Emit nothing here but a comment if we can.
1029 case X86::Int_MemBarrier:
1030 OutStreamer->emitRawComment("MEMBARRIER");
1034 case X86::EH_RETURN:
1035 case X86::EH_RETURN64: {
1036 // Lower these as normal, but add some comments.
1037 unsigned Reg = MI->getOperand(0).getReg();
1038 OutStreamer->AddComment(StringRef("eh_return, addr: %") +
1039 X86ATTInstPrinter::getRegisterName(Reg));
1045 case X86::TAILJMPr64:
1046 case X86::TAILJMPm64:
1047 case X86::TAILJMPd64:
1048 case X86::TAILJMPr64_REX:
1049 case X86::TAILJMPm64_REX:
1050 case X86::TAILJMPd64_REX:
1051 // Lower these as normal, but add some comments.
1052 OutStreamer->AddComment("TAILCALL");
1055 case X86::TLS_addr32:
1056 case X86::TLS_addr64:
1057 case X86::TLS_base_addr32:
1058 case X86::TLS_base_addr64:
1059 return LowerTlsAddr(MCInstLowering, *MI);
1061 case X86::MOVPC32r: {
1062 // This is a pseudo op for a two instruction sequence with a label, which
1069 MCSymbol *PICBase = MF->getPICBaseSymbol();
1070 // FIXME: We would like an efficient form for this, so we don't have to do a
1071 // lot of extra uniquing.
1072 EmitAndCountInstruction(MCInstBuilder(X86::CALLpcrel32)
1073 .addExpr(MCSymbolRefExpr::create(PICBase, OutContext)));
1076 OutStreamer->EmitLabel(PICBase);
1079 EmitAndCountInstruction(MCInstBuilder(X86::POP32r)
1080 .addReg(MI->getOperand(0).getReg()));
1084 case X86::ADD32ri: {
1085 // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
1086 if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
1089 // Okay, we have something like:
1090 // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
1092 // For this, we want to print something like:
1093 // MYGLOBAL + (. - PICBASE)
1094 // However, we can't generate a ".", so just emit a new label here and refer
1096 MCSymbol *DotSym = OutContext.createTempSymbol();
1097 OutStreamer->EmitLabel(DotSym);
1099 // Now that we have emitted the label, lower the complex operand expression.
1100 MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
1102 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
1103 const MCExpr *PICBase =
1104 MCSymbolRefExpr::create(MF->getPICBaseSymbol(), OutContext);
1105 DotExpr = MCBinaryExpr::createSub(DotExpr, PICBase, OutContext);
1107 DotExpr = MCBinaryExpr::createAdd(MCSymbolRefExpr::create(OpSym,OutContext),
1108 DotExpr, OutContext);
1110 EmitAndCountInstruction(MCInstBuilder(X86::ADD32ri)
1111 .addReg(MI->getOperand(0).getReg())
1112 .addReg(MI->getOperand(1).getReg())
1116 case TargetOpcode::STATEPOINT:
1117 return LowerSTATEPOINT(*MI, MCInstLowering);
1119 case TargetOpcode::STACKMAP:
1120 return LowerSTACKMAP(*MI);
1122 case TargetOpcode::PATCHPOINT:
1123 return LowerPATCHPOINT(*MI, MCInstLowering);
1125 case X86::MORESTACK_RET:
1126 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1129 case X86::MORESTACK_RET_RESTORE_R10:
1130 // Return, then restore R10.
1131 EmitAndCountInstruction(MCInstBuilder(getRetOpcode(*Subtarget)));
1132 EmitAndCountInstruction(MCInstBuilder(X86::MOV64rr)
1137 case X86::SEH_PushReg:
1138 OutStreamer->EmitWinCFIPushReg(RI->getSEHRegNum(MI->getOperand(0).getImm()));
1141 case X86::SEH_SaveReg:
1142 OutStreamer->EmitWinCFISaveReg(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1143 MI->getOperand(1).getImm());
1146 case X86::SEH_SaveXMM:
1147 OutStreamer->EmitWinCFISaveXMM(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1148 MI->getOperand(1).getImm());
1151 case X86::SEH_StackAlloc:
1152 OutStreamer->EmitWinCFIAllocStack(MI->getOperand(0).getImm());
1155 case X86::SEH_SetFrame:
1156 OutStreamer->EmitWinCFISetFrame(RI->getSEHRegNum(MI->getOperand(0).getImm()),
1157 MI->getOperand(1).getImm());
1160 case X86::SEH_PushFrame:
1161 OutStreamer->EmitWinCFIPushFrame(MI->getOperand(0).getImm());
1164 case X86::SEH_EndPrologue:
1165 OutStreamer->EmitWinCFIEndProlog();
1168 case X86::SEH_Epilogue: {
1169 MachineBasicBlock::const_iterator MBBI(MI);
1170 // Check if preceded by a call and emit nop if so.
1171 for (MBBI = PrevCrossBBInst(MBBI); MBBI; MBBI = PrevCrossBBInst(MBBI)) {
1172 // Conservatively assume that pseudo instructions don't emit code and keep
1173 // looking for a call. We may emit an unnecessary nop in some cases.
1174 if (!MBBI->isPseudo()) {
1176 EmitAndCountInstruction(MCInstBuilder(X86::NOOP));
1183 // Lower PSHUFB and VPERMILP normally but add a comment if we can find
1184 // a constant shuffle mask. We won't be able to do this at the MC layer
1185 // because the mask isn't an immediate.
1187 case X86::VPSHUFBrm:
1188 case X86::VPSHUFBYrm: {
1189 if (!OutStreamer->isVerboseAsm())
1191 assert(MI->getNumOperands() > 5 &&
1192 "We should always have at least 5 operands!");
1193 const MachineOperand &DstOp = MI->getOperand(0);
1194 const MachineOperand &SrcOp = MI->getOperand(1);
1195 const MachineOperand &MaskOp = MI->getOperand(5);
1197 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1198 SmallVector<int, 16> Mask;
1199 DecodePSHUFBMask(C, Mask);
1201 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1205 case X86::VPERMILPSrm:
1206 case X86::VPERMILPDrm:
1207 case X86::VPERMILPSYrm:
1208 case X86::VPERMILPDYrm: {
1209 if (!OutStreamer->isVerboseAsm())
1211 assert(MI->getNumOperands() > 5 &&
1212 "We should always have at least 5 operands!");
1213 const MachineOperand &DstOp = MI->getOperand(0);
1214 const MachineOperand &SrcOp = MI->getOperand(1);
1215 const MachineOperand &MaskOp = MI->getOperand(5);
1217 if (auto *C = getConstantFromPool(*MI, MaskOp)) {
1218 SmallVector<int, 16> Mask;
1219 DecodeVPERMILPMask(C, Mask);
1221 OutStreamer->AddComment(getShuffleComment(DstOp, SrcOp, Mask));
1226 // For loads from a constant pool to a vector register, print the constant
1229 case X86::VMOVAPDrm:
1230 case X86::VMOVAPDYrm:
1232 case X86::VMOVUPDrm:
1233 case X86::VMOVUPDYrm:
1235 case X86::VMOVAPSrm:
1236 case X86::VMOVAPSYrm:
1238 case X86::VMOVUPSrm:
1239 case X86::VMOVUPSYrm:
1241 case X86::VMOVDQArm:
1242 case X86::VMOVDQAYrm:
1244 case X86::VMOVDQUrm:
1245 case X86::VMOVDQUYrm:
1246 if (!OutStreamer->isVerboseAsm())
1248 if (MI->getNumOperands() > 4)
1249 if (auto *C = getConstantFromPool(*MI, MI->getOperand(4))) {
1250 std::string Comment;
1251 raw_string_ostream CS(Comment);
1252 const MachineOperand &DstOp = MI->getOperand(0);
1253 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
1254 if (auto *CDS = dyn_cast<ConstantDataSequential>(C)) {
1256 for (int i = 0, NumElements = CDS->getNumElements(); i < NumElements; ++i) {
1259 if (CDS->getElementType()->isIntegerTy())
1260 CS << CDS->getElementAsInteger(i);
1261 else if (CDS->getElementType()->isFloatTy())
1262 CS << CDS->getElementAsFloat(i);
1263 else if (CDS->getElementType()->isDoubleTy())
1264 CS << CDS->getElementAsDouble(i);
1269 OutStreamer->AddComment(CS.str());
1270 } else if (auto *CV = dyn_cast<ConstantVector>(C)) {
1272 for (int i = 0, NumOperands = CV->getNumOperands(); i < NumOperands; ++i) {
1275 Constant *COp = CV->getOperand(i);
1276 if (isa<UndefValue>(COp)) {
1278 } else if (auto *CI = dyn_cast<ConstantInt>(COp)) {
1279 CS << CI->getZExtValue();
1280 } else if (auto *CF = dyn_cast<ConstantFP>(COp)) {
1281 SmallString<32> Str;
1282 CF->getValueAPF().toString(Str);
1289 OutStreamer->AddComment(CS.str());
1296 MCInstLowering.Lower(MI, TmpInst);
1298 // Stackmap shadows cannot include branch targets, so we can count the bytes
1299 // in a call towards the shadow, but must ensure that the no thread returns
1300 // in to the stackmap shadow. The only way to achieve this is if the call
1301 // is at the end of the shadow.
1303 // Count then size of the call towards the shadow
1304 SMShadowTracker.count(TmpInst, getSubtargetInfo());
1305 // Then flush the shadow so that we fill with nops before the call, not
1307 SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
1308 // Then emit the call
1309 OutStreamer->EmitInstruction(TmpInst, getSubtargetInfo());
1313 EmitAndCountInstruction(TmpInst);